drivers/net/ethernet/mellanox/mlx5/core/en_rx.c

   1 /*
   2  * Copyright (c) 2015, Mellanox Technologies. All rights reserved.
   3  *
   4  * This software is available to you under a choice of one of two
   5  * licenses.  You may choose to be licensed under the terms of the GNU
   6  * General Public License (GPL) Version 2, available from the file
   7  * COPYING in the main directory of this source tree, or the
   8  * OpenIB.org BSD license below:
   9  *
  10  *     Redistribution and use in source and binary forms, with or
  11  *     without modification, are permitted provided that the following
  12  *     conditions are met:
  13  *
  14  *      - Redistributions of source code must retain the above
  15  *        copyright notice, this list of conditions and the following
  16  *        disclaimer.
  17  *
  18  *      - Redistributions in binary form must reproduce the above
  19  *        copyright notice, this list of conditions and the following
  20  *        disclaimer in the documentation and/or other materials
  21  *        provided with the distribution.
  22  *
  23  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  24  * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  25  * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
  26  * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
  27  * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
  28  * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
  29  * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
  30  * SOFTWARE.
  31  */
  32
  33 #include <linux/ip.h>
  34 #include <linux/ipv6.h>
  35 #include <linux/tcp.h>
  36 #include <net/ip6_checksum.h>
  37 #include <net/page_pool.h>
  38 #include <net/inet_ecn.h>
  39 #include "en.h"
  40 #include "en/txrx.h"
  41 #include "en_tc.h"
  42 #include "eswitch.h"
  43 #include "en_rep.h"
  44 #include "en/rep/tc.h"
  45 #include "ipoib/ipoib.h"
  46 #include "accel/ipsec.h"
  47 #include "fpga/ipsec.h"
  48 #include "en_accel/ipsec_rxtx.h"
  49 #include "en_accel/tls_rxtx.h"
  50 #include "lib/clock.h"
  51 #include "en/xdp.h"
  52 #include "en/xsk/rx.h"
  53 #include "en/health.h"
  54 #include "en/params.h"
  55
  56 static struct sk_buff *
  57 mlx5e_skb_from_cqe_mpwrq_linear(struct mlx5e_rq *rq, struct mlx5e_mpw_info *wi,
  58                                 u16 cqe_bcnt, u32 head_offset, u32 page_idx);
  59 static struct sk_buff *
  60 mlx5e_skb_from_cqe_mpwrq_nonlinear(struct mlx5e_rq *rq, struct mlx5e_mpw_info *wi,
  61                                    u16 cqe_bcnt, u32 head_offset, u32 page_idx);
  62 static void mlx5e_handle_rx_cqe(struct mlx5e_rq *rq, struct mlx5_cqe64 *cqe);
  63 static void mlx5e_handle_rx_cqe_mpwrq(struct mlx5e_rq *rq, struct mlx5_cqe64 *cqe);
  64
  65 const struct mlx5e_rx_handlers mlx5e_rx_handlers_nic = {
  66         .handle_rx_cqe       = mlx5e_handle_rx_cqe,
  67         .handle_rx_cqe_mpwqe = mlx5e_handle_rx_cqe_mpwrq,
  68 };
  69
  70 static inline bool mlx5e_rx_hw_stamp(struct hwtstamp_config *config)
  71 {
  72         return config->rx_filter == HWTSTAMP_FILTER_ALL;
  73 }
  74
  75 static inline void mlx5e_read_cqe_slot(struct mlx5_cqwq *wq,
  76                                        u32 cqcc, void *data)
  77 {
  78         u32 ci = mlx5_cqwq_ctr2ix(wq, cqcc);
  79
  80         memcpy(data, mlx5_cqwq_get_wqe(wq, ci), sizeof(struct mlx5_cqe64));
  81 }
  82
  83 static inline void mlx5e_read_title_slot(struct mlx5e_rq *rq,
  84                                          struct mlx5_cqwq *wq,
  85                                          u32 cqcc)
  86 {
  87         struct mlx5e_cq_decomp *cqd = &rq->cqd;
  88         struct mlx5_cqe64 *title = &cqd->title;
  89
  90         mlx5e_read_cqe_slot(wq, cqcc, title);
  91         cqd->left        = be32_to_cpu(title->byte_cnt);
  92         cqd->wqe_counter = be16_to_cpu(title->wqe_counter);
  93         rq->stats->cqe_compress_blks++;
  94 }
  95
  96 static inline void mlx5e_read_mini_arr_slot(struct mlx5_cqwq *wq,
  97                                             struct mlx5e_cq_decomp *cqd,
  98                                             u32 cqcc)
  99 {
 100         mlx5e_read_cqe_slot(wq, cqcc, cqd->mini_arr);
 101         cqd->mini_arr_idx = 0;
 102 }
 103
 104 static inline void mlx5e_cqes_update_owner(struct mlx5_cqwq *wq, int n)
 105 {
 106         u32 cqcc   = wq->cc;
 107         u8  op_own = mlx5_cqwq_get_ctr_wrap_cnt(wq, cqcc) & 1;
 108         u32 ci     = mlx5_cqwq_ctr2ix(wq, cqcc);
 109         u32 wq_sz  = mlx5_cqwq_get_size(wq);
 110         u32 ci_top = min_t(u32, wq_sz, ci + n);
 111
 112         for (; ci < ci_top; ci++, n--) {
 113                 struct mlx5_cqe64 *cqe = mlx5_cqwq_get_wqe(wq, ci);
 114
 115                 cqe->op_own = op_own;
 116         }
 117
 118         if (unlikely(ci == wq_sz)) {
 119                 op_own = !op_own;
 120                 for (ci = 0; ci < n; ci++) {
 121                         struct mlx5_cqe64 *cqe = mlx5_cqwq_get_wqe(wq, ci);
 122
 123                         cqe->op_own = op_own;
 124                 }
 125         }
 126 }
 127
 128 static inline void mlx5e_decompress_cqe(struct mlx5e_rq *rq,
 129                                         struct mlx5_cqwq *wq,
 130                                         u32 cqcc)
 131 {
 132         struct mlx5e_cq_decomp *cqd = &rq->cqd;
 133         struct mlx5_mini_cqe8 *mini_cqe = &cqd->mini_arr[cqd->mini_arr_idx];
 134         struct mlx5_cqe64 *title = &cqd->title;
 135
 136         title->byte_cnt     = mini_cqe->byte_cnt;
 137         title->check_sum    = mini_cqe->checksum;
 138         title->op_own      &= 0xf0;
 139         title->op_own      |= 0x01 & (cqcc >> wq->fbc.log_sz);
 140
 141         /* state bit set implies linked-list striding RQ wq type and
 142          * HW stride index capability supported
 143          */
 144         if (test_bit(MLX5E_RQ_STATE_MINI_CQE_HW_STRIDX, &rq->state)) {
 145                 title->wqe_counter = mini_cqe->stridx;
 146                 return;
 147         }
 148
 149         /* HW stride index capability not supported */
 150         title->wqe_counter = cpu_to_be16(cqd->wqe_counter);
 151         if (rq->wq_type == MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ)
 152                 cqd->wqe_counter += mpwrq_get_cqe_consumed_strides(title);
 153         else
 154                 cqd->wqe_counter =
 155                         mlx5_wq_cyc_ctr2ix(&rq->wqe.wq, cqd->wqe_counter + 1);
 156 }
 157
 158 static inline void mlx5e_decompress_cqe_no_hash(struct mlx5e_rq *rq,
 159                                                 struct mlx5_cqwq *wq,
 160                                                 u32 cqcc)
 161 {
 162         struct mlx5e_cq_decomp *cqd = &rq->cqd;
 163
 164         mlx5e_decompress_cqe(rq, wq, cqcc);
 165         cqd->title.rss_hash_type   = 0;
 166         cqd->title.rss_hash_result = 0;
 167 }
 168
 169 static inline u32 mlx5e_decompress_cqes_cont(struct mlx5e_rq *rq,
 170                                              struct mlx5_cqwq *wq,
 171                                              int update_owner_only,
 172                                              int budget_rem)
 173 {
 174         struct mlx5e_cq_decomp *cqd = &rq->cqd;
 175         u32 cqcc = wq->cc + update_owner_only;
 176         u32 cqe_count;
 177         u32 i;
 178
 179         cqe_count = min_t(u32, cqd->left, budget_rem);
 180
 181         for (i = update_owner_only; i < cqe_count;
 182              i++, cqd->mini_arr_idx++, cqcc++) {
 183                 if (cqd->mini_arr_idx == MLX5_MINI_CQE_ARRAY_SIZE)
 184                         mlx5e_read_mini_arr_slot(wq, cqd, cqcc);
 185
 186                 mlx5e_decompress_cqe_no_hash(rq, wq, cqcc);
 187                 INDIRECT_CALL_2(rq->handle_rx_cqe, mlx5e_handle_rx_cqe_mpwrq,
 188                                 mlx5e_handle_rx_cqe, rq, &cqd->title);
 189         }
 190         mlx5e_cqes_update_owner(wq, cqcc - wq->cc);
 191         wq->cc = cqcc;
 192         cqd->left -= cqe_count;
 193         rq->stats->cqe_compress_pkts += cqe_count;
 194
 195         return cqe_count;
 196 }
 197
 198 static inline u32 mlx5e_decompress_cqes_start(struct mlx5e_rq *rq,
 199                                               struct mlx5_cqwq *wq,
 200                                               int budget_rem)
 201 {
 202         struct mlx5e_cq_decomp *cqd = &rq->cqd;
 203         u32 cc = wq->cc;
 204
 205         mlx5e_read_title_slot(rq, wq, cc);
 206         mlx5e_read_mini_arr_slot(wq, cqd, cc + 1);
 207         mlx5e_decompress_cqe(rq, wq, cc);
 208         INDIRECT_CALL_2(rq->handle_rx_cqe, mlx5e_handle_rx_cqe_mpwrq,
 209                         mlx5e_handle_rx_cqe, rq, &cqd->title);
 210         cqd->mini_arr_idx++;
 211
 212         return mlx5e_decompress_cqes_cont(rq, wq, 1, budget_rem) - 1;
 213 }
 214
 215 static inline bool mlx5e_page_is_reserved(struct page *page)
 216 {
 217         return page_is_pfmemalloc(page) || page_to_nid(page) != numa_mem_id();
 218 }
 219
 220 static inline bool mlx5e_rx_cache_put(struct mlx5e_rq *rq,
 221                                       struct mlx5e_dma_info *dma_info)
 222 {
 223         struct mlx5e_page_cache *cache = &rq->page_cache;
 224         u32 tail_next = (cache->tail + 1) & (MLX5E_CACHE_SIZE - 1);
 225         struct mlx5e_rq_stats *stats = rq->stats;
 226
 227         if (tail_next == cache->head) {
 228                 stats->cache_full++;
 229                 return false;
 230         }
 231
 232         if (unlikely(mlx5e_page_is_reserved(dma_info->page))) {
 233                 stats->cache_waive++;
 234                 return false;
 235         }
 236
 237         cache->page_cache[cache->tail] = *dma_info;
 238         cache->tail = tail_next;
 239         return true;
 240 }
 241
 242 static inline bool mlx5e_rx_cache_get(struct mlx5e_rq *rq,
 243                                       struct mlx5e_dma_info *dma_info)
 244 {
 245         struct mlx5e_page_cache *cache = &rq->page_cache;
 246         struct mlx5e_rq_stats *stats = rq->stats;
 247
 248         if (unlikely(cache->head == cache->tail)) {
 249                 stats->cache_empty++;
 250                 return false;
 251         }
 252
 253         if (page_ref_count(cache->page_cache[cache->head].page) != 1) {
 254                 stats->cache_busy++;
 255                 return false;
 256         }
 257
 258         *dma_info = cache->page_cache[cache->head];
 259         cache->head = (cache->head + 1) & (MLX5E_CACHE_SIZE - 1);
 260         stats->cache_reuse++;
 261
 262         dma_sync_single_for_device(rq->pdev, dma_info->addr,
 263                                    PAGE_SIZE,
 264                                    DMA_FROM_DEVICE);
 265         return true;
 266 }
 267
 268 static inline int mlx5e_page_alloc_pool(struct mlx5e_rq *rq,
 269                                         struct mlx5e_dma_info *dma_info)
 270 {
 271         if (mlx5e_rx_cache_get(rq, dma_info))
 272                 return 0;
 273
 274         dma_info->page = page_pool_dev_alloc_pages(rq->page_pool);
 275         if (unlikely(!dma_info->page))
 276                 return -ENOMEM;
 277
 278         dma_info->addr = dma_map_page(rq->pdev, dma_info->page, 0,
 279                                       PAGE_SIZE, rq->buff.map_dir);
 280         if (unlikely(dma_mapping_error(rq->pdev, dma_info->addr))) {
 281                 page_pool_recycle_direct(rq->page_pool, dma_info->page);
 282                 dma_info->page = NULL;
 283                 return -ENOMEM;
 284         }
 285
 286         return 0;
 287 }
 288
 289 static inline int mlx5e_page_alloc(struct mlx5e_rq *rq,
 290                                    struct mlx5e_dma_info *dma_info)
 291 {
 292         if (rq->xsk_pool)
 293                 return mlx5e_xsk_page_alloc_pool(rq, dma_info);
 294         else
 295                 return mlx5e_page_alloc_pool(rq, dma_info);
 296 }
 297
 298 void mlx5e_page_dma_unmap(struct mlx5e_rq *rq, struct mlx5e_dma_info *dma_info)
 299 {
 300         dma_unmap_page(rq->pdev, dma_info->addr, PAGE_SIZE, rq->buff.map_dir);
 301 }
 302
 303 void mlx5e_page_release_dynamic(struct mlx5e_rq *rq,
 304                                 struct mlx5e_dma_info *dma_info,
 305                                 bool recycle)
 306 {
 307         if (likely(recycle)) {
 308                 if (mlx5e_rx_cache_put(rq, dma_info))
 309                         return;
 310
 311                 mlx5e_page_dma_unmap(rq, dma_info);
 312                 page_pool_recycle_direct(rq->page_pool, dma_info->page);
 313         } else {
 314                 mlx5e_page_dma_unmap(rq, dma_info);
 315                 page_pool_release_page(rq->page_pool, dma_info->page);
 316                 put_page(dma_info->page);
 317         }
 318 }
 319
 320 static inline void mlx5e_page_release(struct mlx5e_rq *rq,
 321                                       struct mlx5e_dma_info *dma_info,
 322                                       bool recycle)
 323 {
 324         if (rq->xsk_pool)
 325                 /* The `recycle` parameter is ignored, and the page is always
 326                  * put into the Reuse Ring, because there is no way to return
 327                  * the page to the userspace when the interface goes down.
 328                  */
 329                 xsk_buff_free(dma_info->xsk);
 330         else
 331                 mlx5e_page_release_dynamic(rq, dma_info, recycle);
 332 }
 333
 334 static inline int mlx5e_get_rx_frag(struct mlx5e_rq *rq,
 335                                     struct mlx5e_wqe_frag_info *frag)
 336 {
 337         int err = 0;
 338
 339         if (!frag->offset)
 340                 /* On first frag (offset == 0), replenish page (dma_info actually).
 341                  * Other frags that point to the same dma_info (with a different
 342                  * offset) should just use the new one without replenishing again
 343                  * by themselves.
 344                  */
 345                 err = mlx5e_page_alloc(rq, frag->di);
 346
 347         return err;
 348 }
 349
 350 static inline void mlx5e_put_rx_frag(struct mlx5e_rq *rq,
 351                                      struct mlx5e_wqe_frag_info *frag,
 352                                      bool recycle)
 353 {
 354         if (frag->last_in_page)
 355                 mlx5e_page_release(rq, frag->di, recycle);
 356 }
 357
 358 static inline struct mlx5e_wqe_frag_info *get_frag(struct mlx5e_rq *rq, u16 ix)
 359 {
 360         return &rq->wqe.frags[ix << rq->wqe.info.log_num_frags];
 361 }
 362
 363 static int mlx5e_alloc_rx_wqe(struct mlx5e_rq *rq, struct mlx5e_rx_wqe_cyc *wqe,
 364                               u16 ix)
 365 {
 366         struct mlx5e_wqe_frag_info *frag = get_frag(rq, ix);
 367         int err;
 368         int i;
 369
 370         for (i = 0; i < rq->wqe.info.num_frags; i++, frag++) {
 371                 err = mlx5e_get_rx_frag(rq, frag);
 372                 if (unlikely(err))
 373                         goto free_frags;
 374
 375                 wqe->data[i].addr = cpu_to_be64(frag->di->addr +
 376                                                 frag->offset + rq->buff.headroom);
 377         }
 378
 379         return 0;
 380
 381 free_frags:
 382         while (--i >= 0)
 383                 mlx5e_put_rx_frag(rq, --frag, true);
 384
 385         return err;
 386 }
 387
 388 static inline void mlx5e_free_rx_wqe(struct mlx5e_rq *rq,
 389                                      struct mlx5e_wqe_frag_info *wi,
 390                                      bool recycle)
 391 {
 392         int i;
 393
 394         for (i = 0; i < rq->wqe.info.num_frags; i++, wi++)
 395                 mlx5e_put_rx_frag(rq, wi, recycle);
 396 }
 397
 398 static void mlx5e_dealloc_rx_wqe(struct mlx5e_rq *rq, u16 ix)
 399 {
 400         struct mlx5e_wqe_frag_info *wi = get_frag(rq, ix);
 401
 402         mlx5e_free_rx_wqe(rq, wi, false);
 403 }
 404
 405 static int mlx5e_alloc_rx_wqes(struct mlx5e_rq *rq, u16 ix, u8 wqe_bulk)
 406 {
 407         struct mlx5_wq_cyc *wq = &rq->wqe.wq;
 408         int err;
 409         int i;
 410
 411         if (rq->xsk_pool) {
 412                 int pages_desired = wqe_bulk << rq->wqe.info.log_num_frags;
 413
 414                 /* Check in advance that we have enough frames, instead of
 415                  * allocating one-by-one, failing and moving frames to the
 416                  * Reuse Ring.
 417                  */
 418                 if (unlikely(!xsk_buff_can_alloc(rq->xsk_pool, pages_desired)))
 419                         return -ENOMEM;
 420         }
 421
 422         for (i = 0; i < wqe_bulk; i++) {
 423                 struct mlx5e_rx_wqe_cyc *wqe = mlx5_wq_cyc_get_wqe(wq, ix + i);
 424
 425                 err = mlx5e_alloc_rx_wqe(rq, wqe, ix + i);
 426                 if (unlikely(err))
 427                         goto free_wqes;
 428         }
 429
 430         return 0;
 431
 432 free_wqes:
 433         while (--i >= 0)
 434                 mlx5e_dealloc_rx_wqe(rq, ix + i);
 435
 436         return err;
 437 }
 438
 439 static inline void
 440 mlx5e_add_skb_frag(struct mlx5e_rq *rq, struct sk_buff *skb,
 441                    struct mlx5e_dma_info *di, u32 frag_offset, u32 len,
 442                    unsigned int truesize)
 443 {
 444         dma_sync_single_for_cpu(rq->pdev,
 445                                 di->addr + frag_offset,
 446                                 len, DMA_FROM_DEVICE);
 447         page_ref_inc(di->page);
 448         skb_add_rx_frag(skb, skb_shinfo(skb)->nr_frags,
 449                         di->page, frag_offset, len, truesize);
 450 }
 451
 452 static inline void
 453 mlx5e_copy_skb_header(struct device *pdev, struct sk_buff *skb,
 454                       struct mlx5e_dma_info *dma_info,
 455                       int offset_from, u32 headlen)
 456 {
 457         const void *from = page_address(dma_info->page) + offset_from;
 458         /* Aligning len to sizeof(long) optimizes memcpy performance */
 459         unsigned int len = ALIGN(headlen, sizeof(long));
 460
 461         dma_sync_single_for_cpu(pdev, dma_info->addr + offset_from, len,
 462                                 DMA_FROM_DEVICE);
 463         skb_copy_to_linear_data(skb, from, len);
 464 }
 465
 466 static void
 467 mlx5e_free_rx_mpwqe(struct mlx5e_rq *rq, struct mlx5e_mpw_info *wi, bool recycle)
 468 {
 469         bool no_xdp_xmit;
 470         struct mlx5e_dma_info *dma_info = wi->umr.dma_info;
 471         int i;
 472
 473         /* A common case for AF_XDP. */
 474         if (bitmap_full(wi->xdp_xmit_bitmap, MLX5_MPWRQ_PAGES_PER_WQE))
 475                 return;
 476
 477         no_xdp_xmit = bitmap_empty(wi->xdp_xmit_bitmap,
 478                                    MLX5_MPWRQ_PAGES_PER_WQE);
 479
 480         for (i = 0; i < MLX5_MPWRQ_PAGES_PER_WQE; i++)
 481                 if (no_xdp_xmit || !test_bit(i, wi->xdp_xmit_bitmap))
 482                         mlx5e_page_release(rq, &dma_info[i], recycle);
 483 }
 484
 485 static void mlx5e_post_rx_mpwqe(struct mlx5e_rq *rq, u8 n)
 486 {
 487         struct mlx5_wq_ll *wq = &rq->mpwqe.wq;
 488
 489         do {
 490                 u16 next_wqe_index = mlx5_wq_ll_get_wqe_next_ix(wq, wq->head);
 491
 492                 mlx5_wq_ll_push(wq, next_wqe_index);
 493         } while (--n);
 494
 495         /* ensure wqes are visible to device before updating doorbell record */
 496         dma_wmb();
 497
 498         mlx5_wq_ll_update_db_record(wq);
 499 }
 500
 501 static int mlx5e_alloc_rx_mpwqe(struct mlx5e_rq *rq, u16 ix)
 502 {
 503         struct mlx5e_mpw_info *wi = &rq->mpwqe.info[ix];
 504         struct mlx5e_dma_info *dma_info = &wi->umr.dma_info[0];
 505         struct mlx5e_icosq *sq = rq->icosq;
 506         struct mlx5_wq_cyc *wq = &sq->wq;
 507         struct mlx5e_umr_wqe *umr_wqe;
 508         u16 xlt_offset = ix << (MLX5E_LOG_ALIGNED_MPWQE_PPW - 1);
 509         u16 pi;
 510         int err;
 511         int i;
 512
 513         /* Check in advance that we have enough frames, instead of allocating
 514          * one-by-one, failing and moving frames to the Reuse Ring.
 515          */
 516         if (rq->xsk_pool &&
 517             unlikely(!xsk_buff_can_alloc(rq->xsk_pool, MLX5_MPWRQ_PAGES_PER_WQE))) {
 518                 err = -ENOMEM;
 519                 goto err;
 520         }
 521
 522         pi = mlx5e_icosq_get_next_pi(sq, MLX5E_UMR_WQEBBS);
 523         umr_wqe = mlx5_wq_cyc_get_wqe(wq, pi);
 524         memcpy(umr_wqe, &rq->mpwqe.umr_wqe, offsetof(struct mlx5e_umr_wqe, inline_mtts));
 525
 526         for (i = 0; i < MLX5_MPWRQ_PAGES_PER_WQE; i++, dma_info++) {
 527                 err = mlx5e_page_alloc(rq, dma_info);
 528                 if (unlikely(err))
 529                         goto err_unmap;
 530                 umr_wqe->inline_mtts[i].ptag = cpu_to_be64(dma_info->addr | MLX5_EN_WR);
 531         }
 532
 533         bitmap_zero(wi->xdp_xmit_bitmap, MLX5_MPWRQ_PAGES_PER_WQE);
 534         wi->consumed_strides = 0;
 535
 536         umr_wqe->ctrl.opmod_idx_opcode =
 537                 cpu_to_be32((sq->pc << MLX5_WQE_CTRL_WQE_INDEX_SHIFT) |
 538                             MLX5_OPCODE_UMR);
 539         umr_wqe->uctrl.xlt_offset = cpu_to_be16(xlt_offset);
 540
 541         sq->db.wqe_info[pi] = (struct mlx5e_icosq_wqe_info) {
 542                 .wqe_type   = MLX5E_ICOSQ_WQE_UMR_RX,
 543                 .num_wqebbs = MLX5E_UMR_WQEBBS,
 544                 .umr.rq     = rq,
 545         };
 546
 547         sq->pc += MLX5E_UMR_WQEBBS;
 548
 549         sq->doorbell_cseg = &umr_wqe->ctrl;
 550
 551         return 0;
 552
 553 err_unmap:
 554         while (--i >= 0) {
 555                 dma_info--;
 556                 mlx5e_page_release(rq, dma_info, true);
 557         }
 558
 559 err:
 560         rq->stats->buff_alloc_err++;
 561
 562         return err;
 563 }
 564
 565 static void mlx5e_dealloc_rx_mpwqe(struct mlx5e_rq *rq, u16 ix)
 566 {
 567         struct mlx5e_mpw_info *wi = &rq->mpwqe.info[ix];
 568         /* Don't recycle, this function is called on rq/netdev close */
 569         mlx5e_free_rx_mpwqe(rq, wi, false);
 570 }
 571
 572 INDIRECT_CALLABLE_SCOPE bool mlx5e_post_rx_wqes(struct mlx5e_rq *rq)
 573 {
 574         struct mlx5_wq_cyc *wq = &rq->wqe.wq;
 575         u8 wqe_bulk;
 576         int err;
 577
 578         if (unlikely(!test_bit(MLX5E_RQ_STATE_ENABLED, &rq->state)))
 579                 return false;
 580
 581         wqe_bulk = rq->wqe.info.wqe_bulk;
 582
 583         if (mlx5_wq_cyc_missing(wq) < wqe_bulk)
 584                 return false;
 585
 586         do {
 587                 u16 head = mlx5_wq_cyc_get_head(wq);
 588
 589                 err = mlx5e_alloc_rx_wqes(rq, head, wqe_bulk);
 590                 if (unlikely(err)) {
 591                         rq->stats->buff_alloc_err++;
 592                         break;
 593                 }
 594
 595                 mlx5_wq_cyc_push_n(wq, wqe_bulk);
 596         } while (mlx5_wq_cyc_missing(wq) >= wqe_bulk);
 597
 598         /* ensure wqes are visible to device before updating doorbell record */
 599         dma_wmb();
 600
 601         mlx5_wq_cyc_update_db_record(wq);
 602
 603         return !!err;
 604 }
 605
 606 void mlx5e_free_icosq_descs(struct mlx5e_icosq *sq)
 607 {
 608         u16 sqcc;
 609
 610         sqcc = sq->cc;
 611
 612         while (sqcc != sq->pc) {
 613                 struct mlx5e_icosq_wqe_info *wi;
 614                 u16 ci;
 615
 616                 ci = mlx5_wq_cyc_ctr2ix(&sq->wq, sqcc);
 617                 wi = &sq->db.wqe_info[ci];
 618                 sqcc += wi->num_wqebbs;
 619 #ifdef CONFIG_MLX5_EN_TLS
 620                 switch (wi->wqe_type) {
 621                 case MLX5E_ICOSQ_WQE_SET_PSV_TLS:
 622                         mlx5e_ktls_handle_ctx_completion(wi);
 623                         break;
 624                 case MLX5E_ICOSQ_WQE_GET_PSV_TLS:
 625                         mlx5e_ktls_handle_get_psv_completion(wi, sq);
 626                         break;
 627                 }
 628 #endif
 629         }
 630         sq->cc = sqcc;
 631 }
 632
 633 int mlx5e_poll_ico_cq(struct mlx5e_cq *cq)
 634 {
 635         struct mlx5e_icosq *sq = container_of(cq, struct mlx5e_icosq, cq);
 636         struct mlx5_cqe64 *cqe;
 637         u16 sqcc;
 638         int i;
 639
 640         if (unlikely(!test_bit(MLX5E_SQ_STATE_ENABLED, &sq->state)))
 641                 return 0;
 642
 643         cqe = mlx5_cqwq_get_cqe(&cq->wq);
 644         if (likely(!cqe))
 645                 return 0;
 646
 647         /* sq->cc must be updated only after mlx5_cqwq_update_db_record(),
 648          * otherwise a cq overrun may occur
 649          */
 650         sqcc = sq->cc;
 651
 652         i = 0;
 653         do {
 654                 u16 wqe_counter;
 655                 bool last_wqe;
 656
 657                 mlx5_cqwq_pop(&cq->wq);
 658
 659                 wqe_counter = be16_to_cpu(cqe->wqe_counter);
 660
 661                 do {
 662                         struct mlx5e_icosq_wqe_info *wi;
 663                         u16 ci;
 664
 665                         last_wqe = (sqcc == wqe_counter);
 666
 667                         ci = mlx5_wq_cyc_ctr2ix(&sq->wq, sqcc);
 668                         wi = &sq->db.wqe_info[ci];
 669                         sqcc += wi->num_wqebbs;
 670
 671                         if (last_wqe && unlikely(get_cqe_opcode(cqe) != MLX5_CQE_REQ)) {
 672                                 netdev_WARN_ONCE(cq->netdev,
 673                                                  "Bad OP in ICOSQ CQE: 0x%x\n",
 674                                                  get_cqe_opcode(cqe));
 675                                 mlx5e_dump_error_cqe(&sq->cq, sq->sqn,
 676                                                      (struct mlx5_err_cqe *)cqe);
 677                                 if (!test_and_set_bit(MLX5E_SQ_STATE_RECOVERING, &sq->state))
 678                                         queue_work(cq->priv->wq, &sq->recover_work);
 679                                 break;
 680                         }
 681
 682                         switch (wi->wqe_type) {
 683                         case MLX5E_ICOSQ_WQE_UMR_RX:
 684                                 wi->umr.rq->mpwqe.umr_completed++;
 685                                 break;
 686                         case MLX5E_ICOSQ_WQE_NOP:
 687                                 break;
 688 #ifdef CONFIG_MLX5_EN_TLS
 689                         case MLX5E_ICOSQ_WQE_UMR_TLS:
 690                                 break;
 691                         case MLX5E_ICOSQ_WQE_SET_PSV_TLS:
 692                                 mlx5e_ktls_handle_ctx_completion(wi);
 693                                 break;
 694                         case MLX5E_ICOSQ_WQE_GET_PSV_TLS:
 695                                 mlx5e_ktls_handle_get_psv_completion(wi, sq);
 696                                 break;
 697 #endif
 698                         default:
 699                                 netdev_WARN_ONCE(cq->netdev,
 700                                                  "Bad WQE type in ICOSQ WQE info: 0x%x\n",
 701                                                  wi->wqe_type);
 702                         }
 703                 } while (!last_wqe);
 704         } while ((++i < MLX5E_TX_CQ_POLL_BUDGET) && (cqe = mlx5_cqwq_get_cqe(&cq->wq)));
 705
 706         sq->cc = sqcc;
 707
 708         mlx5_cqwq_update_db_record(&cq->wq);
 709
 710         return i;
 711 }
 712
 713 INDIRECT_CALLABLE_SCOPE bool mlx5e_post_rx_mpwqes(struct mlx5e_rq *rq)
 714 {
 715         struct mlx5_wq_ll *wq = &rq->mpwqe.wq;
 716         u8  umr_completed = rq->mpwqe.umr_completed;
 717         struct mlx5e_icosq *sq = rq->icosq;
 718         int alloc_err = 0;
 719         u8  missing, i;
 720         u16 head;
 721
 722         if (unlikely(!test_bit(MLX5E_RQ_STATE_ENABLED, &rq->state)))
 723                 return false;
 724
 725         if (umr_completed) {
 726                 mlx5e_post_rx_mpwqe(rq, umr_completed);
 727                 rq->mpwqe.umr_in_progress -= umr_completed;
 728                 rq->mpwqe.umr_completed = 0;
 729         }
 730
 731         missing = mlx5_wq_ll_missing(wq) - rq->mpwqe.umr_in_progress;
 732
 733         if (unlikely(rq->mpwqe.umr_in_progress > rq->mpwqe.umr_last_bulk))
 734                 rq->stats->congst_umr++;
 735
 736 #define UMR_WQE_BULK (2)
 737         if (likely(missing < UMR_WQE_BULK))
 738                 return false;
 739
 740         head = rq->mpwqe.actual_wq_head;
 741         i = missing;
 742         do {
 743                 alloc_err = mlx5e_alloc_rx_mpwqe(rq, head);
 744
 745                 if (unlikely(alloc_err))
 746                         break;
 747                 head = mlx5_wq_ll_get_wqe_next_ix(wq, head);
 748         } while (--i);
 749
 750         rq->mpwqe.umr_last_bulk    = missing - i;
 751         if (sq->doorbell_cseg) {
 752                 mlx5e_notify_hw(&sq->wq, sq->pc, sq->uar_map, sq->doorbell_cseg);
 753                 sq->doorbell_cseg = NULL;
 754         }
 755
 756         rq->mpwqe.umr_in_progress += rq->mpwqe.umr_last_bulk;
 757         rq->mpwqe.actual_wq_head   = head;
 758
 759         /* If XSK Fill Ring doesn't have enough frames, report the error, so
 760          * that one of the actions can be performed:
 761          * 1. If need_wakeup is used, signal that the application has to kick
 762          * the driver when it refills the Fill Ring.
 763          * 2. Otherwise, busy poll by rescheduling the NAPI poll.
 764          */
 765         if (unlikely(alloc_err == -ENOMEM && rq->xsk_pool))
 766                 return true;
 767
 768         return false;
 769 }
 770
 771 static void mlx5e_lro_update_tcp_hdr(struct mlx5_cqe64 *cqe, struct tcphdr *tcp)
 772 {
 773         u8 l4_hdr_type = get_cqe_l4_hdr_type(cqe);
 774         u8 tcp_ack     = (l4_hdr_type == CQE_L4_HDR_TYPE_TCP_ACK_NO_DATA) ||
 775                          (l4_hdr_type == CQE_L4_HDR_TYPE_TCP_ACK_AND_DATA);
 776
 777         tcp->check                      = 0;
 778         tcp->psh                        = get_cqe_lro_tcppsh(cqe);
 779
 780         if (tcp_ack) {
 781                 tcp->ack                = 1;
 782                 tcp->ack_seq            = cqe->lro_ack_seq_num;
 783                 tcp->window             = cqe->lro_tcp_win;
 784         }
 785 }
 786
 787 static void mlx5e_lro_update_hdr(struct sk_buff *skb, struct mlx5_cqe64 *cqe,
 788                                  u32 cqe_bcnt)
 789 {
 790         struct ethhdr   *eth = (struct ethhdr *)(skb->data);
 791         struct tcphdr   *tcp;
 792         int network_depth = 0;
 793         __wsum check;
 794         __be16 proto;
 795         u16 tot_len;
 796         void *ip_p;
 797
 798         proto = __vlan_get_protocol(skb, eth->h_proto, &network_depth);
 799
 800         tot_len = cqe_bcnt - network_depth;
 801         ip_p = skb->data + network_depth;
 802
 803         if (proto == htons(ETH_P_IP)) {
 804                 struct iphdr *ipv4 = ip_p;
 805
 806                 tcp = ip_p + sizeof(struct iphdr);
 807                 skb_shinfo(skb)->gso_type = SKB_GSO_TCPV4;
 808
 809                 ipv4->ttl               = cqe->lro_min_ttl;
 810                 ipv4->tot_len           = cpu_to_be16(tot_len);
 811                 ipv4->check             = 0;
 812                 ipv4->check             = ip_fast_csum((unsigned char *)ipv4,
 813                                                        ipv4->ihl);
 814
 815                 mlx5e_lro_update_tcp_hdr(cqe, tcp);
 816                 check = csum_partial(tcp, tcp->doff * 4,
 817                                      csum_unfold((__force __sum16)cqe->check_sum));
 818                 /* Almost done, don't forget the pseudo header */
 819                 tcp->check = csum_tcpudp_magic(ipv4->saddr, ipv4->daddr,
 820                                                tot_len - sizeof(struct iphdr),
 821                                                IPPROTO_TCP, check);
 822         } else {
 823                 u16 payload_len = tot_len - sizeof(struct ipv6hdr);
 824                 struct ipv6hdr *ipv6 = ip_p;
 825
 826                 tcp = ip_p + sizeof(struct ipv6hdr);
 827                 skb_shinfo(skb)->gso_type = SKB_GSO_TCPV6;
 828
 829                 ipv6->hop_limit         = cqe->lro_min_ttl;
 830                 ipv6->payload_len       = cpu_to_be16(payload_len);
 831
 832                 mlx5e_lro_update_tcp_hdr(cqe, tcp);
 833                 check = csum_partial(tcp, tcp->doff * 4,
 834                                      csum_unfold((__force __sum16)cqe->check_sum));
 835                 /* Almost done, don't forget the pseudo header */
 836                 tcp->check = csum_ipv6_magic(&ipv6->saddr, &ipv6->daddr, payload_len,
 837                                              IPPROTO_TCP, check);
 838         }
 839 }
 840
 841 static inline void mlx5e_skb_set_hash(struct mlx5_cqe64 *cqe,
 842                                       struct sk_buff *skb)
 843 {
 844         u8 cht = cqe->rss_hash_type;
 845         int ht = (cht & CQE_RSS_HTYPE_L4) ? PKT_HASH_TYPE_L4 :
 846                  (cht & CQE_RSS_HTYPE_IP) ? PKT_HASH_TYPE_L3 :
 847                                             PKT_HASH_TYPE_NONE;
 848         skb_set_hash(skb, be32_to_cpu(cqe->rss_hash_result), ht);
 849 }
 850
 851 static inline bool is_last_ethertype_ip(struct sk_buff *skb, int *network_depth,
 852                                         __be16 *proto)
 853 {
 854         *proto = ((struct ethhdr *)skb->data)->h_proto;
 855         *proto = __vlan_get_protocol(skb, *proto, network_depth);
 856
 857         if (*proto == htons(ETH_P_IP))
 858                 return pskb_may_pull(skb, *network_depth + sizeof(struct iphdr));
 859
 860         if (*proto == htons(ETH_P_IPV6))
 861                 return pskb_may_pull(skb, *network_depth + sizeof(struct ipv6hdr));
 862
 863         return false;
 864 }
 865
 866 static inline void mlx5e_enable_ecn(struct mlx5e_rq *rq, struct sk_buff *skb)
 867 {
 868         int network_depth = 0;
 869         __be16 proto;
 870         void *ip;
 871         int rc;
 872
 873         if (unlikely(!is_last_ethertype_ip(skb, &network_depth, &proto)))
 874                 return;
 875
 876         ip = skb->data + network_depth;
 877         rc = ((proto == htons(ETH_P_IP)) ? IP_ECN_set_ce((struct iphdr *)ip) :
 878                                          IP6_ECN_set_ce(skb, (struct ipv6hdr *)ip));
 879
 880         rq->stats->ecn_mark += !!rc;
 881 }
 882
 883 static u8 get_ip_proto(struct sk_buff *skb, int network_depth, __be16 proto)
 884 {
 885         void *ip_p = skb->data + network_depth;
 886
 887         return (proto == htons(ETH_P_IP)) ? ((struct iphdr *)ip_p)->protocol :
 888                                             ((struct ipv6hdr *)ip_p)->nexthdr;
 889 }
 890
 891 #define short_frame(size) ((size) <= ETH_ZLEN + ETH_FCS_LEN)
 892
 893 #define MAX_PADDING 8
 894
 895 static void
 896 tail_padding_csum_slow(struct sk_buff *skb, int offset, int len,
 897                        struct mlx5e_rq_stats *stats)
 898 {
 899         stats->csum_complete_tail_slow++;
 900         skb->csum = csum_block_add(skb->csum,
 901                                    skb_checksum(skb, offset, len, 0),
 902                                    offset);
 903 }
 904
 905 static void
 906 tail_padding_csum(struct sk_buff *skb, int offset,
 907                   struct mlx5e_rq_stats *stats)
 908 {
 909         u8 tail_padding[MAX_PADDING];
 910         int len = skb->len - offset;
 911         void *tail;
 912
 913         if (unlikely(len > MAX_PADDING)) {
 914                 tail_padding_csum_slow(skb, offset, len, stats);
 915                 return;
 916         }
 917
 918         tail = skb_header_pointer(skb, offset, len, tail_padding);
 919         if (unlikely(!tail)) {
 920                 tail_padding_csum_slow(skb, offset, len, stats);
 921                 return;
 922         }
 923
 924         stats->csum_complete_tail++;
 925         skb->csum = csum_block_add(skb->csum, csum_partial(tail, len, 0), offset);
 926 }
 927
 928 static void
 929 mlx5e_skb_csum_fixup(struct sk_buff *skb, int network_depth, __be16 proto,
 930                      struct mlx5e_rq_stats *stats)
 931 {
 932         struct ipv6hdr *ip6;
 933         struct iphdr   *ip4;
 934         int pkt_len;
 935
 936         /* Fixup vlan headers, if any */
 937         if (network_depth > ETH_HLEN)
 938                 /* CQE csum is calculated from the IP header and does
 939                  * not cover VLAN headers (if present). This will add
 940                  * the checksum manually.
 941                  */
 942                 skb->csum = csum_partial(skb->data + ETH_HLEN,
 943                                          network_depth - ETH_HLEN,
 944                                          skb->csum);
 945
 946         /* Fixup tail padding, if any */
 947         switch (proto) {
 948         case htons(ETH_P_IP):
 949                 ip4 = (struct iphdr *)(skb->data + network_depth);
 950                 pkt_len = network_depth + ntohs(ip4->tot_len);
 951                 break;
 952         case htons(ETH_P_IPV6):
 953                 ip6 = (struct ipv6hdr *)(skb->data + network_depth);
 954                 pkt_len = network_depth + sizeof(*ip6) + ntohs(ip6->payload_len);
 955                 break;
 956         default:
 957                 return;
 958         }
 959
 960         if (likely(pkt_len >= skb->len))
 961                 return;
 962
 963         tail_padding_csum(skb, pkt_len, stats);
 964 }
 965
 966 static inline void mlx5e_handle_csum(struct net_device *netdev,
 967                                      struct mlx5_cqe64 *cqe,
 968                                      struct mlx5e_rq *rq,
 969                                      struct sk_buff *skb,
 970                                      bool   lro)
 971 {
 972         struct mlx5e_rq_stats *stats = rq->stats;
 973         int network_depth = 0;
 974         __be16 proto;
 975
 976         if (unlikely(!(netdev->features & NETIF_F_RXCSUM)))
 977                 goto csum_none;
 978
 979         if (lro) {
 980                 skb->ip_summed = CHECKSUM_UNNECESSARY;
 981                 stats->csum_unnecessary++;
 982                 return;
 983         }
 984
 985         /* True when explicitly set via priv flag, or XDP prog is loaded */
 986         if (test_bit(MLX5E_RQ_STATE_NO_CSUM_COMPLETE, &rq->state))
 987                 goto csum_unnecessary;
 988
 989         /* CQE csum doesn't cover padding octets in short ethernet
 990          * frames. And the pad field is appended prior to calculating
 991          * and appending the FCS field.
 992          *
 993          * Detecting these padded frames requires to verify and parse
 994          * IP headers, so we simply force all those small frames to be
 995          * CHECKSUM_UNNECESSARY even if they are not padded.
 996          */
 997         if (short_frame(skb->len))
 998                 goto csum_unnecessary;
 999
1000         if (likely(is_last_ethertype_ip(skb, &network_depth, &proto))) {
1001                 u8 ipproto = get_ip_proto(skb, network_depth, proto);
1002
1003                 if (unlikely(ipproto == IPPROTO_SCTP))
1004                         goto csum_unnecessary;
1005
1006                 if (unlikely(mlx5_ipsec_is_rx_flow(cqe)))
1007                         goto csum_none;
1008
1009                 stats->csum_complete++;
1010                 skb->ip_summed = CHECKSUM_COMPLETE;
1011                 skb->csum = csum_unfold((__force __sum16)cqe->check_sum);
1012
1013                 if (test_bit(MLX5E_RQ_STATE_CSUM_FULL, &rq->state))
1014                         return; /* CQE csum covers all received bytes */
1015
1016                 /* csum might need some fixups ...*/
1017                 mlx5e_skb_csum_fixup(skb, network_depth, proto, stats);
1018                 return;
1019         }
1020
1021 csum_unnecessary:
1022         if (likely((cqe->hds_ip_ext & CQE_L3_OK) &&
1023                    (cqe->hds_ip_ext & CQE_L4_OK))) {
1024                 skb->ip_summed = CHECKSUM_UNNECESSARY;
1025                 if (cqe_is_tunneled(cqe)) {
1026                         skb->csum_level = 1;
1027                         skb->encapsulation = 1;
1028                         stats->csum_unnecessary_inner++;
1029                         return;
1030                 }
1031                 stats->csum_unnecessary++;
1032                 return;
1033         }
1034 csum_none:
1035         skb->ip_summed = CHECKSUM_NONE;
1036         stats->csum_none++;
1037 }
1038
1039 #define MLX5E_CE_BIT_MASK 0x80
1040
1041 static inline void mlx5e_build_rx_skb(struct mlx5_cqe64 *cqe,
1042                                       u32 cqe_bcnt,
1043                                       struct mlx5e_rq *rq,
1044                                       struct sk_buff *skb)
1045 {
1046         u8 lro_num_seg = be32_to_cpu(cqe->srqn) >> 24;
1047         struct mlx5e_rq_stats *stats = rq->stats;
1048         struct net_device *netdev = rq->netdev;
1049
1050         skb->mac_len = ETH_HLEN;
1051
1052         mlx5e_tls_handle_rx_skb(rq, skb, cqe, &cqe_bcnt);
1053
1054         if (unlikely(mlx5_ipsec_is_rx_flow(cqe)))
1055                 mlx5e_ipsec_offload_handle_rx_skb(netdev, skb, cqe);
1056
1057         if (lro_num_seg > 1) {
1058                 mlx5e_lro_update_hdr(skb, cqe, cqe_bcnt);
1059                 skb_shinfo(skb)->gso_size = DIV_ROUND_UP(cqe_bcnt, lro_num_seg);
1060                 /* Subtract one since we already counted this as one
1061                  * "regular" packet in mlx5e_complete_rx_cqe()
1062                  */
1063                 stats->packets += lro_num_seg - 1;
1064                 stats->lro_packets++;
1065                 stats->lro_bytes += cqe_bcnt;
1066         }
1067
1068         if (unlikely(mlx5e_rx_hw_stamp(rq->tstamp)))
1069                 skb_hwtstamps(skb)->hwtstamp =
1070                                 mlx5_timecounter_cyc2time(rq->clock, get_cqe_ts(cqe));
1071
1072         skb_record_rx_queue(skb, rq->ix);
1073
1074         if (likely(netdev->features & NETIF_F_RXHASH))
1075                 mlx5e_skb_set_hash(cqe, skb);
1076
1077         if (cqe_has_vlan(cqe)) {
1078                 __vlan_hwaccel_put_tag(skb, htons(ETH_P_8021Q),
1079                                        be16_to_cpu(cqe->vlan_info));
1080                 stats->removed_vlan_packets++;
1081         }
1082
1083         skb->mark = be32_to_cpu(cqe->sop_drop_qpn) & MLX5E_TC_FLOW_ID_MASK;
1084
1085         mlx5e_handle_csum(netdev, cqe, rq, skb, !!lro_num_seg);
1086         /* checking CE bit in cqe - MSB in ml_path field */
1087         if (unlikely(cqe->ml_path & MLX5E_CE_BIT_MASK))
1088                 mlx5e_enable_ecn(rq, skb);
1089
1090         skb->protocol = eth_type_trans(skb, netdev);
1091
1092         if (unlikely(mlx5e_skb_is_multicast(skb)))
1093                 stats->mcast_packets++;
1094 }
1095
1096 static inline void mlx5e_complete_rx_cqe(struct mlx5e_rq *rq,
1097                                          struct mlx5_cqe64 *cqe,
1098                                          u32 cqe_bcnt,
1099                                          struct sk_buff *skb)
1100 {
1101         struct mlx5e_rq_stats *stats = rq->stats;
1102
1103         stats->packets++;
1104         stats->bytes += cqe_bcnt;
1105         mlx5e_build_rx_skb(cqe, cqe_bcnt, rq, skb);
1106 }
1107
1108 static inline
1109 struct sk_buff *mlx5e_build_linear_skb(struct mlx5e_rq *rq, void *va,
1110                                        u32 frag_size, u16 headroom,
1111                                        u32 cqe_bcnt)
1112 {
1113         struct sk_buff *skb = build_skb(va, frag_size);
1114
1115         if (unlikely(!skb)) {
1116                 rq->stats->buff_alloc_err++;
1117                 return NULL;
1118         }
1119
1120         skb_reserve(skb, headroom);
1121         skb_put(skb, cqe_bcnt);
1122
1123         return skb;
1124 }
1125
1126 static void mlx5e_fill_xdp_buff(struct mlx5e_rq *rq, void *va, u16 headroom,
1127                                 u32 len, struct xdp_buff *xdp)
1128 {
1129         xdp_init_buff(xdp, rq->buff.frame0_sz, &rq->xdp_rxq);
1130         xdp_prepare_buff(xdp, va, headroom, len, false);
1131 }
1132
1133 static struct sk_buff *
1134 mlx5e_skb_from_cqe_linear(struct mlx5e_rq *rq, struct mlx5_cqe64 *cqe,
1135                           struct mlx5e_wqe_frag_info *wi, u32 cqe_bcnt)
1136 {
1137         struct mlx5e_dma_info *di = wi->di;
1138         u16 rx_headroom = rq->buff.headroom;
1139         struct xdp_buff xdp;
1140         struct sk_buff *skb;
1141         void *va, *data;
1142         u32 frag_size;
1143
1144         va             = page_address(di->page) + wi->offset;
1145         data           = va + rx_headroom;
1146         frag_size      = MLX5_SKB_FRAG_SZ(rx_headroom + cqe_bcnt);
1147
1148         dma_sync_single_range_for_cpu(rq->pdev, di->addr, wi->offset,
1149                                       frag_size, DMA_FROM_DEVICE);
1150         net_prefetchw(va); /* xdp_frame data area */
1151         net_prefetch(data);
1152
1153         mlx5e_fill_xdp_buff(rq, va, rx_headroom, cqe_bcnt, &xdp);
1154         if (mlx5e_xdp_handle(rq, di, &cqe_bcnt, &xdp))
1155                 return NULL; /* page/packet was consumed by XDP */
1156
1157         rx_headroom = xdp.data - xdp.data_hard_start;
1158         frag_size = MLX5_SKB_FRAG_SZ(rx_headroom + cqe_bcnt);
1159         skb = mlx5e_build_linear_skb(rq, va, frag_size, rx_headroom, cqe_bcnt);
1160         if (unlikely(!skb))
1161                 return NULL;
1162
1163         /* queue up for recycling/reuse */
1164         page_ref_inc(di->page);
1165
1166         return skb;
1167 }
1168
1169 static struct sk_buff *
1170 mlx5e_skb_from_cqe_nonlinear(struct mlx5e_rq *rq, struct mlx5_cqe64 *cqe,
1171                              struct mlx5e_wqe_frag_info *wi, u32 cqe_bcnt)
1172 {
1173         struct mlx5e_rq_frag_info *frag_info = &rq->wqe.info.arr[0];
1174         struct mlx5e_wqe_frag_info *head_wi = wi;
1175         u16 headlen      = min_t(u32, MLX5E_RX_MAX_HEAD, cqe_bcnt);
1176         u16 frag_headlen = headlen;
1177         u16 byte_cnt     = cqe_bcnt - headlen;
1178         struct sk_buff *skb;
1179
1180         /* XDP is not supported in this configuration, as incoming packets
1181          * might spread among multiple pages.
1182          */
1183         skb = napi_alloc_skb(rq->cq.napi,
1184                              ALIGN(MLX5E_RX_MAX_HEAD, sizeof(long)));
1185         if (unlikely(!skb)) {
1186                 rq->stats->buff_alloc_err++;
1187                 return NULL;
1188         }
1189
1190         net_prefetchw(skb->data);
1191
1192         while (byte_cnt) {
1193                 u16 frag_consumed_bytes =
1194                         min_t(u16, frag_info->frag_size - frag_headlen, byte_cnt);
1195
1196                 mlx5e_add_skb_frag(rq, skb, wi->di, wi->offset + frag_headlen,
1197                                    frag_consumed_bytes, frag_info->frag_stride);
1198                 byte_cnt -= frag_consumed_bytes;
1199                 frag_headlen = 0;
1200                 frag_info++;
1201                 wi++;
1202         }
1203
1204         /* copy header */
1205         mlx5e_copy_skb_header(rq->pdev, skb, head_wi->di, head_wi->offset, headlen);
1206         /* skb linear part was allocated with headlen and aligned to long */
1207         skb->tail += headlen;
1208         skb->len  += headlen;
1209
1210         return skb;
1211 }
1212
1213 static void trigger_report(struct mlx5e_rq *rq, struct mlx5_cqe64 *cqe)
1214 {
1215         struct mlx5_err_cqe *err_cqe = (struct mlx5_err_cqe *)cqe;
1216         struct mlx5e_priv *priv = rq->priv;
1217
1218         if (cqe_syndrome_needs_recover(err_cqe->syndrome) &&
1219             !test_and_set_bit(MLX5E_RQ_STATE_RECOVERING, &rq->state)) {
1220                 mlx5e_dump_error_cqe(&rq->cq, rq->rqn, err_cqe);
1221                 queue_work(priv->wq, &rq->recover_work);
1222         }
1223 }
1224
1225 static void mlx5e_handle_rx_cqe(struct mlx5e_rq *rq, struct mlx5_cqe64 *cqe)
1226 {
1227         struct mlx5_wq_cyc *wq = &rq->wqe.wq;
1228         struct mlx5e_wqe_frag_info *wi;
1229         struct sk_buff *skb;
1230         u32 cqe_bcnt;
1231         u16 ci;
1232
1233         ci       = mlx5_wq_cyc_ctr2ix(wq, be16_to_cpu(cqe->wqe_counter));
1234         wi       = get_frag(rq, ci);
1235         cqe_bcnt = be32_to_cpu(cqe->byte_cnt);
1236
1237         if (unlikely(MLX5E_RX_ERR_CQE(cqe))) {
1238                 trigger_report(rq, cqe);
1239                 rq->stats->wqe_err++;
1240                 goto free_wqe;
1241         }
1242
1243         skb = INDIRECT_CALL_2(rq->wqe.skb_from_cqe,
1244                               mlx5e_skb_from_cqe_linear,
1245                               mlx5e_skb_from_cqe_nonlinear,
1246                               rq, cqe, wi, cqe_bcnt);
1247         if (!skb) {
1248                 /* probably for XDP */
1249                 if (__test_and_clear_bit(MLX5E_RQ_FLAG_XDP_XMIT, rq->flags)) {
1250                         /* do not return page to cache,
1251                          * it will be returned on XDP_TX completion.
1252                          */
1253                         goto wq_cyc_pop;
1254                 }
1255                 goto free_wqe;
1256         }
1257
1258         mlx5e_complete_rx_cqe(rq, cqe, cqe_bcnt, skb);
1259
1260         if (mlx5e_cqe_regb_chain(cqe))
1261                 if (!mlx5e_tc_update_skb(cqe, skb))
1262                         goto free_wqe;
1263
1264         napi_gro_receive(rq->cq.napi, skb);
1265
1266 free_wqe:
1267         mlx5e_free_rx_wqe(rq, wi, true);
1268 wq_cyc_pop:
1269         mlx5_wq_cyc_pop(wq);
1270 }
1271
1272 #ifdef CONFIG_MLX5_ESWITCH
1273 static void mlx5e_handle_rx_cqe_rep(struct mlx5e_rq *rq, struct mlx5_cqe64 *cqe)
1274 {
1275         struct net_device *netdev = rq->netdev;
1276         struct mlx5e_priv *priv = netdev_priv(netdev);
1277         struct mlx5e_rep_priv *rpriv  = priv->ppriv;
1278         struct mlx5_eswitch_rep *rep = rpriv->rep;
1279         struct mlx5e_tc_update_priv tc_priv = {};
1280         struct mlx5_wq_cyc *wq = &rq->wqe.wq;
1281         struct mlx5e_wqe_frag_info *wi;
1282         struct sk_buff *skb;
1283         u32 cqe_bcnt;
1284         u16 ci;
1285
1286         ci       = mlx5_wq_cyc_ctr2ix(wq, be16_to_cpu(cqe->wqe_counter));
1287         wi       = get_frag(rq, ci);
1288         cqe_bcnt = be32_to_cpu(cqe->byte_cnt);
1289
1290         if (unlikely(MLX5E_RX_ERR_CQE(cqe))) {
1291                 rq->stats->wqe_err++;
1292                 goto free_wqe;
1293         }
1294
1295         skb = INDIRECT_CALL_2(rq->wqe.skb_from_cqe,
1296                               mlx5e_skb_from_cqe_linear,
1297                               mlx5e_skb_from_cqe_nonlinear,
1298                               rq, cqe, wi, cqe_bcnt);
1299         if (!skb) {
1300                 /* probably for XDP */
1301                 if (__test_and_clear_bit(MLX5E_RQ_FLAG_XDP_XMIT, rq->flags)) {
1302                         /* do not return page to cache,
1303                          * it will be returned on XDP_TX completion.
1304                          */
1305                         goto wq_cyc_pop;
1306                 }
1307                 goto free_wqe;
1308         }
1309
1310         mlx5e_complete_rx_cqe(rq, cqe, cqe_bcnt, skb);
1311
1312         if (rep->vlan && skb_vlan_tag_present(skb))
1313                 skb_vlan_pop(skb);
1314
1315         if (!mlx5e_rep_tc_update_skb(cqe, skb, &tc_priv))
1316                 goto free_wqe;
1317
1318         napi_gro_receive(rq->cq.napi, skb);
1319
1320         mlx5_rep_tc_post_napi_receive(&tc_priv);
1321
1322 free_wqe:
1323         mlx5e_free_rx_wqe(rq, wi, true);
1324 wq_cyc_pop:
1325         mlx5_wq_cyc_pop(wq);
1326 }
1327
1328 static void mlx5e_handle_rx_cqe_mpwrq_rep(struct mlx5e_rq *rq, struct mlx5_cqe64 *cqe)
1329 {
1330         u16 cstrides       = mpwrq_get_cqe_consumed_strides(cqe);
1331         u16 wqe_id         = be16_to_cpu(cqe->wqe_id);
1332         struct mlx5e_mpw_info *wi = &rq->mpwqe.info[wqe_id];
1333         u16 stride_ix      = mpwrq_get_cqe_stride_index(cqe);
1334         u32 wqe_offset     = stride_ix << rq->mpwqe.log_stride_sz;
1335         u32 head_offset    = wqe_offset & (PAGE_SIZE - 1);
1336         u32 page_idx       = wqe_offset >> PAGE_SHIFT;
1337         struct mlx5e_tc_update_priv tc_priv = {};
1338         struct mlx5e_rx_wqe_ll *wqe;
1339         struct mlx5_wq_ll *wq;
1340         struct sk_buff *skb;
1341         u16 cqe_bcnt;
1342
1343         wi->consumed_strides += cstrides;
1344
1345         if (unlikely(MLX5E_RX_ERR_CQE(cqe))) {
1346                 trigger_report(rq, cqe);
1347                 rq->stats->wqe_err++;
1348                 goto mpwrq_cqe_out;
1349         }
1350
1351         if (unlikely(mpwrq_is_filler_cqe(cqe))) {
1352                 struct mlx5e_rq_stats *stats = rq->stats;
1353
1354                 stats->mpwqe_filler_cqes++;
1355                 stats->mpwqe_filler_strides += cstrides;
1356                 goto mpwrq_cqe_out;
1357         }
1358
1359         cqe_bcnt = mpwrq_get_cqe_byte_cnt(cqe);
1360
1361         skb = INDIRECT_CALL_2(rq->mpwqe.skb_from_cqe_mpwrq,
1362                               mlx5e_skb_from_cqe_mpwrq_linear,
1363                               mlx5e_skb_from_cqe_mpwrq_nonlinear,
1364                               rq, wi, cqe_bcnt, head_offset, page_idx);
1365         if (!skb)
1366                 goto mpwrq_cqe_out;
1367
1368         mlx5e_complete_rx_cqe(rq, cqe, cqe_bcnt, skb);
1369
1370         if (!mlx5e_rep_tc_update_skb(cqe, skb, &tc_priv))
1371                 goto mpwrq_cqe_out;
1372
1373         napi_gro_receive(rq->cq.napi, skb);
1374
1375         mlx5_rep_tc_post_napi_receive(&tc_priv);
1376
1377 mpwrq_cqe_out:
1378         if (likely(wi->consumed_strides < rq->mpwqe.num_strides))
1379                 return;
1380
1381         wq  = &rq->mpwqe.wq;
1382         wqe = mlx5_wq_ll_get_wqe(wq, wqe_id);
1383         mlx5e_free_rx_mpwqe(rq, wi, true);
1384         mlx5_wq_ll_pop(wq, cqe->wqe_id, &wqe->next.next_wqe_index);
1385 }
1386
1387 const struct mlx5e_rx_handlers mlx5e_rx_handlers_rep = {
1388         .handle_rx_cqe       = mlx5e_handle_rx_cqe_rep,
1389         .handle_rx_cqe_mpwqe = mlx5e_handle_rx_cqe_mpwrq_rep,
1390 };
1391 #endif
1392
1393 static struct sk_buff *
1394 mlx5e_skb_from_cqe_mpwrq_nonlinear(struct mlx5e_rq *rq, struct mlx5e_mpw_info *wi,
1395                                    u16 cqe_bcnt, u32 head_offset, u32 page_idx)
1396 {
1397         u16 headlen = min_t(u16, MLX5E_RX_MAX_HEAD, cqe_bcnt);
1398         struct mlx5e_dma_info *di = &wi->umr.dma_info[page_idx];
1399         u32 frag_offset    = head_offset + headlen;
1400         u32 byte_cnt       = cqe_bcnt - headlen;
1401         struct mlx5e_dma_info *head_di = di;
1402         struct sk_buff *skb;
1403
1404         skb = napi_alloc_skb(rq->cq.napi,
1405                              ALIGN(MLX5E_RX_MAX_HEAD, sizeof(long)));
1406         if (unlikely(!skb)) {
1407                 rq->stats->buff_alloc_err++;
1408                 return NULL;
1409         }
1410
1411         net_prefetchw(skb->data);
1412
1413         if (unlikely(frag_offset >= PAGE_SIZE)) {
1414                 di++;
1415                 frag_offset -= PAGE_SIZE;
1416         }
1417
1418         while (byte_cnt) {
1419                 u32 pg_consumed_bytes =
1420                         min_t(u32, PAGE_SIZE - frag_offset, byte_cnt);
1421                 unsigned int truesize =
1422                         ALIGN(pg_consumed_bytes, BIT(rq->mpwqe.log_stride_sz));
1423
1424                 mlx5e_add_skb_frag(rq, skb, di, frag_offset,
1425                                    pg_consumed_bytes, truesize);
1426                 byte_cnt -= pg_consumed_bytes;
1427                 frag_offset = 0;
1428                 di++;
1429         }
1430         /* copy header */
1431         mlx5e_copy_skb_header(rq->pdev, skb, head_di, head_offset, headlen);
1432         /* skb linear part was allocated with headlen and aligned to long */
1433         skb->tail += headlen;
1434         skb->len  += headlen;
1435
1436         return skb;
1437 }
1438
1439 static struct sk_buff *
1440 mlx5e_skb_from_cqe_mpwrq_linear(struct mlx5e_rq *rq, struct mlx5e_mpw_info *wi,
1441                                 u16 cqe_bcnt, u32 head_offset, u32 page_idx)
1442 {
1443         struct mlx5e_dma_info *di = &wi->umr.dma_info[page_idx];
1444         u16 rx_headroom = rq->buff.headroom;
1445         u32 cqe_bcnt32 = cqe_bcnt;
1446         struct xdp_buff xdp;
1447         struct sk_buff *skb;
1448         void *va, *data;
1449         u32 frag_size;
1450
1451         /* Check packet size. Note LRO doesn't use linear SKB */
1452         if (unlikely(cqe_bcnt > rq->hw_mtu)) {
1453                 rq->stats->oversize_pkts_sw_drop++;
1454                 return NULL;
1455         }
1456
1457         va             = page_address(di->page) + head_offset;
1458         data           = va + rx_headroom;
1459         frag_size      = MLX5_SKB_FRAG_SZ(rx_headroom + cqe_bcnt32);
1460
1461         dma_sync_single_range_for_cpu(rq->pdev, di->addr, head_offset,
1462                                       frag_size, DMA_FROM_DEVICE);
1463         net_prefetchw(va); /* xdp_frame data area */
1464         net_prefetch(data);
1465
1466         mlx5e_fill_xdp_buff(rq, va, rx_headroom, cqe_bcnt32, &xdp);
1467         if (mlx5e_xdp_handle(rq, di, &cqe_bcnt32, &xdp)) {
1468                 if (__test_and_clear_bit(MLX5E_RQ_FLAG_XDP_XMIT, rq->flags))
1469                         __set_bit(page_idx, wi->xdp_xmit_bitmap); /* non-atomic */
1470                 return NULL; /* page/packet was consumed by XDP */
1471         }
1472
1473         rx_headroom = xdp.data - xdp.data_hard_start;
1474         frag_size = MLX5_SKB_FRAG_SZ(rx_headroom + cqe_bcnt32);
1475         skb = mlx5e_build_linear_skb(rq, va, frag_size, rx_headroom, cqe_bcnt32);
1476         if (unlikely(!skb))
1477                 return NULL;
1478
1479         /* queue up for recycling/reuse */
1480         page_ref_inc(di->page);
1481
1482         return skb;
1483 }
1484
1485 static void mlx5e_handle_rx_cqe_mpwrq(struct mlx5e_rq *rq, struct mlx5_cqe64 *cqe)
1486 {
1487         u16 cstrides       = mpwrq_get_cqe_consumed_strides(cqe);
1488         u16 wqe_id         = be16_to_cpu(cqe->wqe_id);
1489         struct mlx5e_mpw_info *wi = &rq->mpwqe.info[wqe_id];
1490         u16 stride_ix      = mpwrq_get_cqe_stride_index(cqe);
1491         u32 wqe_offset     = stride_ix << rq->mpwqe.log_stride_sz;
1492         u32 head_offset    = wqe_offset & (PAGE_SIZE - 1);
1493         u32 page_idx       = wqe_offset >> PAGE_SHIFT;
1494         struct mlx5e_rx_wqe_ll *wqe;
1495         struct mlx5_wq_ll *wq;
1496         struct sk_buff *skb;
1497         u16 cqe_bcnt;
1498
1499         wi->consumed_strides += cstrides;
1500
1501         if (unlikely(MLX5E_RX_ERR_CQE(cqe))) {
1502                 trigger_report(rq, cqe);
1503                 rq->stats->wqe_err++;
1504                 goto mpwrq_cqe_out;
1505         }
1506
1507         if (unlikely(mpwrq_is_filler_cqe(cqe))) {
1508                 struct mlx5e_rq_stats *stats = rq->stats;
1509
1510                 stats->mpwqe_filler_cqes++;
1511                 stats->mpwqe_filler_strides += cstrides;
1512                 goto mpwrq_cqe_out;
1513         }
1514
1515         cqe_bcnt = mpwrq_get_cqe_byte_cnt(cqe);
1516
1517         skb = INDIRECT_CALL_2(rq->mpwqe.skb_from_cqe_mpwrq,
1518                               mlx5e_skb_from_cqe_mpwrq_linear,
1519                               mlx5e_skb_from_cqe_mpwrq_nonlinear,
1520                               rq, wi, cqe_bcnt, head_offset, page_idx);
1521         if (!skb)
1522                 goto mpwrq_cqe_out;
1523
1524         mlx5e_complete_rx_cqe(rq, cqe, cqe_bcnt, skb);
1525
1526         if (mlx5e_cqe_regb_chain(cqe))
1527                 if (!mlx5e_tc_update_skb(cqe, skb))
1528                         goto mpwrq_cqe_out;
1529
1530         napi_gro_receive(rq->cq.napi, skb);
1531
1532 mpwrq_cqe_out:
1533         if (likely(wi->consumed_strides < rq->mpwqe.num_strides))
1534                 return;
1535
1536         wq  = &rq->mpwqe.wq;
1537         wqe = mlx5_wq_ll_get_wqe(wq, wqe_id);
1538         mlx5e_free_rx_mpwqe(rq, wi, true);
1539         mlx5_wq_ll_pop(wq, cqe->wqe_id, &wqe->next.next_wqe_index);
1540 }
1541
1542 int mlx5e_poll_rx_cq(struct mlx5e_cq *cq, int budget)
1543 {
1544         struct mlx5e_rq *rq = container_of(cq, struct mlx5e_rq, cq);
1545         struct mlx5_cqwq *cqwq = &cq->wq;
1546         struct mlx5_cqe64 *cqe;
1547         int work_done = 0;
1548
1549         if (unlikely(!test_bit(MLX5E_RQ_STATE_ENABLED, &rq->state)))
1550                 return 0;
1551
1552         if (rq->page_pool)
1553                 page_pool_nid_changed(rq->page_pool, numa_mem_id());
1554
1555         if (rq->cqd.left) {
1556                 work_done += mlx5e_decompress_cqes_cont(rq, cqwq, 0, budget);
1557                 if (rq->cqd.left || work_done >= budget)
1558                         goto out;
1559         }
1560
1561         cqe = mlx5_cqwq_get_cqe(cqwq);
1562         if (!cqe) {
1563                 if (unlikely(work_done))
1564                         goto out;
1565                 return 0;
1566         }
1567
1568         do {
1569                 if (mlx5_get_cqe_format(cqe) == MLX5_COMPRESSED) {
1570                         work_done +=
1571                                 mlx5e_decompress_cqes_start(rq, cqwq,
1572                                                             budget - work_done);
1573                         continue;
1574                 }
1575
1576                 mlx5_cqwq_pop(cqwq);
1577
1578                 INDIRECT_CALL_2(rq->handle_rx_cqe, mlx5e_handle_rx_cqe_mpwrq,
1579                                 mlx5e_handle_rx_cqe, rq, cqe);
1580         } while ((++work_done < budget) && (cqe = mlx5_cqwq_get_cqe(cqwq)));
1581
1582 out:
1583         if (rcu_access_pointer(rq->xdp_prog))
1584                 mlx5e_xdp_rx_poll_complete(rq);
1585
1586         mlx5_cqwq_update_db_record(cqwq);
1587
1588         /* ensure cq space is freed before enabling more cqes */
1589         wmb();
1590
1591         return work_done;
1592 }
1593
1594 #ifdef CONFIG_MLX5_CORE_IPOIB
1595
1596 #define MLX5_IB_GRH_SGID_OFFSET 8
1597 #define MLX5_IB_GRH_DGID_OFFSET 24
1598 #define MLX5_GID_SIZE           16
1599
1600 static inline void mlx5i_complete_rx_cqe(struct mlx5e_rq *rq,
1601                                          struct mlx5_cqe64 *cqe,
1602                                          u32 cqe_bcnt,
1603                                          struct sk_buff *skb)
1604 {
1605         struct hwtstamp_config *tstamp;
1606         struct mlx5e_rq_stats *stats;
1607         struct net_device *netdev;
1608         struct mlx5e_priv *priv;
1609         char *pseudo_header;
1610         u32 flags_rqpn;
1611         u32 qpn;
1612         u8 *dgid;
1613         u8 g;
1614
1615         qpn = be32_to_cpu(cqe->sop_drop_qpn) & 0xffffff;
1616         netdev = mlx5i_pkey_get_netdev(rq->netdev, qpn);
1617
1618         /* No mapping present, cannot process SKB. This might happen if a child
1619          * interface is going down while having unprocessed CQEs on parent RQ
1620          */
1621         if (unlikely(!netdev)) {
1622                 /* TODO: add drop counters support */
1623                 skb->dev = NULL;
1624                 pr_warn_once("Unable to map QPN %u to dev - dropping skb\n", qpn);
1625                 return;
1626         }
1627
1628         priv = mlx5i_epriv(netdev);
1629         tstamp = &priv->tstamp;
1630         stats = &priv->channel_stats[rq->ix].rq;
1631
1632         flags_rqpn = be32_to_cpu(cqe->flags_rqpn);
1633         g = (flags_rqpn >> 28) & 3;
1634         dgid = skb->data + MLX5_IB_GRH_DGID_OFFSET;
1635         if ((!g) || dgid[0] != 0xff)
1636                 skb->pkt_type = PACKET_HOST;
1637         else if (memcmp(dgid, netdev->broadcast + 4, MLX5_GID_SIZE) == 0)
1638                 skb->pkt_type = PACKET_BROADCAST;
1639         else
1640                 skb->pkt_type = PACKET_MULTICAST;
1641
1642         /* Drop packets that this interface sent, ie multicast packets
1643          * that the HCA has replicated.
1644          */
1645         if (g && (qpn == (flags_rqpn & 0xffffff)) &&
1646             (memcmp(netdev->dev_addr + 4, skb->data + MLX5_IB_GRH_SGID_OFFSET,
1647                     MLX5_GID_SIZE) == 0)) {
1648                 skb->dev = NULL;
1649                 return;
1650         }
1651
1652         skb_pull(skb, MLX5_IB_GRH_BYTES);
1653
1654         skb->protocol = *((__be16 *)(skb->data));
1655
1656         if (netdev->features & NETIF_F_RXCSUM) {
1657                 skb->ip_summed = CHECKSUM_COMPLETE;
1658                 skb->csum = csum_unfold((__force __sum16)cqe->check_sum);
1659                 stats->csum_complete++;
1660         } else {
1661                 skb->ip_summed = CHECKSUM_NONE;
1662                 stats->csum_none++;
1663         }
1664
1665         if (unlikely(mlx5e_rx_hw_stamp(tstamp)))
1666                 skb_hwtstamps(skb)->hwtstamp =
1667                                 mlx5_timecounter_cyc2time(rq->clock, get_cqe_ts(cqe));
1668
1669         skb_record_rx_queue(skb, rq->ix);
1670
1671         if (likely(netdev->features & NETIF_F_RXHASH))
1672                 mlx5e_skb_set_hash(cqe, skb);
1673
1674         /* 20 bytes of ipoib header and 4 for encap existing */
1675         pseudo_header = skb_push(skb, MLX5_IPOIB_PSEUDO_LEN);
1676         memset(pseudo_header, 0, MLX5_IPOIB_PSEUDO_LEN);
1677         skb_reset_mac_header(skb);
1678         skb_pull(skb, MLX5_IPOIB_HARD_LEN);
1679
1680         skb->dev = netdev;
1681
1682         stats->packets++;
1683         stats->bytes += cqe_bcnt;
1684 }
1685
1686 static void mlx5i_handle_rx_cqe(struct mlx5e_rq *rq, struct mlx5_cqe64 *cqe)
1687 {
1688         struct mlx5_wq_cyc *wq = &rq->wqe.wq;
1689         struct mlx5e_wqe_frag_info *wi;
1690         struct sk_buff *skb;
1691         u32 cqe_bcnt;
1692         u16 ci;
1693
1694         ci       = mlx5_wq_cyc_ctr2ix(wq, be16_to_cpu(cqe->wqe_counter));
1695         wi       = get_frag(rq, ci);
1696         cqe_bcnt = be32_to_cpu(cqe->byte_cnt);
1697
1698         if (unlikely(MLX5E_RX_ERR_CQE(cqe))) {
1699                 rq->stats->wqe_err++;
1700                 goto wq_free_wqe;
1701         }
1702
1703         skb = INDIRECT_CALL_2(rq->wqe.skb_from_cqe,
1704                               mlx5e_skb_from_cqe_linear,
1705                               mlx5e_skb_from_cqe_nonlinear,
1706                               rq, cqe, wi, cqe_bcnt);
1707         if (!skb)
1708                 goto wq_free_wqe;
1709
1710         mlx5i_complete_rx_cqe(rq, cqe, cqe_bcnt, skb);
1711         if (unlikely(!skb->dev)) {
1712                 dev_kfree_skb_any(skb);
1713                 goto wq_free_wqe;
1714         }
1715         napi_gro_receive(rq->cq.napi, skb);
1716
1717 wq_free_wqe:
1718         mlx5e_free_rx_wqe(rq, wi, true);
1719         mlx5_wq_cyc_pop(wq);
1720 }
1721
1722 const struct mlx5e_rx_handlers mlx5i_rx_handlers = {
1723         .handle_rx_cqe       = mlx5i_handle_rx_cqe,
1724         .handle_rx_cqe_mpwqe = NULL, /* Not supported */
1725 };
1726 #endif /* CONFIG_MLX5_CORE_IPOIB */
1727
1728 #ifdef CONFIG_MLX5_EN_IPSEC
1729
1730 static void mlx5e_ipsec_handle_rx_cqe(struct mlx5e_rq *rq, struct mlx5_cqe64 *cqe)
1731 {
1732         struct mlx5_wq_cyc *wq = &rq->wqe.wq;
1733         struct mlx5e_wqe_frag_info *wi;
1734         struct sk_buff *skb;
1735         u32 cqe_bcnt;
1736         u16 ci;
1737
1738         ci       = mlx5_wq_cyc_ctr2ix(wq, be16_to_cpu(cqe->wqe_counter));
1739         wi       = get_frag(rq, ci);
1740         cqe_bcnt = be32_to_cpu(cqe->byte_cnt);
1741
1742         if (unlikely(MLX5E_RX_ERR_CQE(cqe))) {
1743                 rq->stats->wqe_err++;
1744                 goto wq_free_wqe;
1745         }
1746
1747         skb = INDIRECT_CALL_2(rq->wqe.skb_from_cqe,
1748                               mlx5e_skb_from_cqe_linear,
1749                               mlx5e_skb_from_cqe_nonlinear,
1750                               rq, cqe, wi, cqe_bcnt);
1751         if (unlikely(!skb)) /* a DROP, save the page-reuse checks */
1752                 goto wq_free_wqe;
1753
1754         skb = mlx5e_ipsec_handle_rx_skb(rq->netdev, skb, &cqe_bcnt);
1755         if (unlikely(!skb))
1756                 goto wq_free_wqe;
1757
1758         mlx5e_complete_rx_cqe(rq, cqe, cqe_bcnt, skb);
1759         napi_gro_receive(rq->cq.napi, skb);
1760
1761 wq_free_wqe:
1762         mlx5e_free_rx_wqe(rq, wi, true);
1763         mlx5_wq_cyc_pop(wq);
1764 }
1765
1766 #endif /* CONFIG_MLX5_EN_IPSEC */
1767
1768 int mlx5e_rq_set_handlers(struct mlx5e_rq *rq, struct mlx5e_params *params, bool xsk)
1769 {
1770         struct net_device *netdev = rq->netdev;
1771         struct mlx5_core_dev *mdev = rq->mdev;
1772         struct mlx5e_priv *priv = rq->priv;
1773
1774         switch (rq->wq_type) {
1775         case MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ:
1776                 rq->mpwqe.skb_from_cqe_mpwrq = xsk ?
1777                         mlx5e_xsk_skb_from_cqe_mpwrq_linear :
1778                         mlx5e_rx_mpwqe_is_linear_skb(mdev, params, NULL) ?
1779                                 mlx5e_skb_from_cqe_mpwrq_linear :
1780                                 mlx5e_skb_from_cqe_mpwrq_nonlinear;
1781                 rq->post_wqes = mlx5e_post_rx_mpwqes;
1782                 rq->dealloc_wqe = mlx5e_dealloc_rx_mpwqe;
1783
1784                 rq->handle_rx_cqe = priv->profile->rx_handlers->handle_rx_cqe_mpwqe;
1785 #ifdef CONFIG_MLX5_EN_IPSEC
1786                 if (MLX5_IPSEC_DEV(mdev)) {
1787                         netdev_err(netdev, "MPWQE RQ with IPSec offload not supported\n");
1788                         return -EINVAL;
1789                 }
1790 #endif
1791                 if (!rq->handle_rx_cqe) {
1792                         netdev_err(netdev, "RX handler of MPWQE RQ is not set\n");
1793                         return -EINVAL;
1794                 }
1795                 break;
1796         default: /* MLX5_WQ_TYPE_CYCLIC */
1797                 rq->wqe.skb_from_cqe = xsk ?
1798                         mlx5e_xsk_skb_from_cqe_linear :
1799                         mlx5e_rx_is_linear_skb(params, NULL) ?
1800                                 mlx5e_skb_from_cqe_linear :
1801                                 mlx5e_skb_from_cqe_nonlinear;
1802                 rq->post_wqes = mlx5e_post_rx_wqes;
1803                 rq->dealloc_wqe = mlx5e_dealloc_rx_wqe;
1804
1805 #ifdef CONFIG_MLX5_EN_IPSEC
1806                 if ((mlx5_fpga_ipsec_device_caps(mdev) & MLX5_ACCEL_IPSEC_CAP_DEVICE) &&
1807                     priv->ipsec)
1808                         rq->handle_rx_cqe = mlx5e_ipsec_handle_rx_cqe;
1809                 else
1810 #endif
1811                         rq->handle_rx_cqe = priv->profile->rx_handlers->handle_rx_cqe;
1812                 if (!rq->handle_rx_cqe) {
1813                         netdev_err(netdev, "RX handler of RQ is not set\n");
1814                         return -EINVAL;
1815                 }
1816         }
1817
1818         return 0;
1819 }