drivers/net/ethernet/mellanox/mlx5/core/en_rx.c

   1 /*
   2  * Copyright (c) 2015, Mellanox Technologies. All rights reserved.
   3  *
   4  * This software is available to you under a choice of one of two
   5  * licenses.  You may choose to be licensed under the terms of the GNU
   6  * General Public License (GPL) Version 2, available from the file
   7  * COPYING in the main directory of this source tree, or the
   8  * OpenIB.org BSD license below:
   9  *
  10  *     Redistribution and use in source and binary forms, with or
  11  *     without modification, are permitted provided that the following
  12  *     conditions are met:
  13  *
  14  *      - Redistributions of source code must retain the above
  15  *        copyright notice, this list of conditions and the following
  16  *        disclaimer.
  17  *
  18  *      - Redistributions in binary form must reproduce the above
  19  *        copyright notice, this list of conditions and the following
  20  *        disclaimer in the documentation and/or other materials
  21  *        provided with the distribution.
  22  *
  23  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  24  * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  25  * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
  26  * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
  27  * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
  28  * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
  29  * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
  30  * SOFTWARE.
  31  */
  32
  33 #include <linux/prefetch.h>
  34 #include <linux/ip.h>
  35 #include <linux/ipv6.h>
  36 #include <linux/tcp.h>
  37 #include <linux/indirect_call_wrapper.h>
  38 #include <net/ip6_checksum.h>
  39 #include <net/page_pool.h>
  40 #include <net/inet_ecn.h>
  41 #include "en.h"
  42 #include "en_tc.h"
  43 #include "eswitch.h"
  44 #include "en_rep.h"
  45 #include "en/rep/tc.h"
  46 #include "ipoib/ipoib.h"
  47 #include "accel/ipsec.h"
  48 #include "fpga/ipsec.h"
  49 #include "en_accel/ipsec_rxtx.h"
  50 #include "en_accel/tls_rxtx.h"
  51 #include "lib/clock.h"
  52 #include "en/xdp.h"
  53 #include "en/xsk/rx.h"
  54 #include "en/health.h"
  55 #include "en/params.h"
  56
  57 static struct sk_buff *
  58 mlx5e_skb_from_cqe_mpwrq_linear(struct mlx5e_rq *rq, struct mlx5e_mpw_info *wi,
  59                                 u16 cqe_bcnt, u32 head_offset, u32 page_idx);
  60 static struct sk_buff *
  61 mlx5e_skb_from_cqe_mpwrq_nonlinear(struct mlx5e_rq *rq, struct mlx5e_mpw_info *wi,
  62                                    u16 cqe_bcnt, u32 head_offset, u32 page_idx);
  63 static void mlx5e_handle_rx_cqe(struct mlx5e_rq *rq, struct mlx5_cqe64 *cqe);
  64 static void mlx5e_handle_rx_cqe_mpwrq(struct mlx5e_rq *rq, struct mlx5_cqe64 *cqe);
  65
  66 const struct mlx5e_rx_handlers mlx5e_rx_handlers_nic = {
  67         .handle_rx_cqe       = mlx5e_handle_rx_cqe,
  68         .handle_rx_cqe_mpwqe = mlx5e_handle_rx_cqe_mpwrq,
  69 };
  70
  71 static inline bool mlx5e_rx_hw_stamp(struct hwtstamp_config *config)
  72 {
  73         return config->rx_filter == HWTSTAMP_FILTER_ALL;
  74 }
  75
  76 static inline void mlx5e_read_cqe_slot(struct mlx5_cqwq *wq,
  77                                        u32 cqcc, void *data)
  78 {
  79         u32 ci = mlx5_cqwq_ctr2ix(wq, cqcc);
  80
  81         memcpy(data, mlx5_cqwq_get_wqe(wq, ci), sizeof(struct mlx5_cqe64));
  82 }
  83
  84 static inline void mlx5e_read_title_slot(struct mlx5e_rq *rq,
  85                                          struct mlx5_cqwq *wq,
  86                                          u32 cqcc)
  87 {
  88         struct mlx5e_cq_decomp *cqd = &rq->cqd;
  89         struct mlx5_cqe64 *title = &cqd->title;
  90
  91         mlx5e_read_cqe_slot(wq, cqcc, title);
  92         cqd->left        = be32_to_cpu(title->byte_cnt);
  93         cqd->wqe_counter = be16_to_cpu(title->wqe_counter);
  94         rq->stats->cqe_compress_blks++;
  95 }
  96
  97 static inline void mlx5e_read_mini_arr_slot(struct mlx5_cqwq *wq,
  98                                             struct mlx5e_cq_decomp *cqd,
  99                                             u32 cqcc)
 100 {
 101         mlx5e_read_cqe_slot(wq, cqcc, cqd->mini_arr);
 102         cqd->mini_arr_idx = 0;
 103 }
 104
 105 static inline void mlx5e_cqes_update_owner(struct mlx5_cqwq *wq, int n)
 106 {
 107         u32 cqcc   = wq->cc;
 108         u8  op_own = mlx5_cqwq_get_ctr_wrap_cnt(wq, cqcc) & 1;
 109         u32 ci     = mlx5_cqwq_ctr2ix(wq, cqcc);
 110         u32 wq_sz  = mlx5_cqwq_get_size(wq);
 111         u32 ci_top = min_t(u32, wq_sz, ci + n);
 112
 113         for (; ci < ci_top; ci++, n--) {
 114                 struct mlx5_cqe64 *cqe = mlx5_cqwq_get_wqe(wq, ci);
 115
 116                 cqe->op_own = op_own;
 117         }
 118
 119         if (unlikely(ci == wq_sz)) {
 120                 op_own = !op_own;
 121                 for (ci = 0; ci < n; ci++) {
 122                         struct mlx5_cqe64 *cqe = mlx5_cqwq_get_wqe(wq, ci);
 123
 124                         cqe->op_own = op_own;
 125                 }
 126         }
 127 }
 128
 129 static inline void mlx5e_decompress_cqe(struct mlx5e_rq *rq,
 130                                         struct mlx5_cqwq *wq,
 131                                         u32 cqcc)
 132 {
 133         struct mlx5e_cq_decomp *cqd = &rq->cqd;
 134         struct mlx5_mini_cqe8 *mini_cqe = &cqd->mini_arr[cqd->mini_arr_idx];
 135         struct mlx5_cqe64 *title = &cqd->title;
 136
 137         title->byte_cnt     = mini_cqe->byte_cnt;
 138         title->check_sum    = mini_cqe->checksum;
 139         title->op_own      &= 0xf0;
 140         title->op_own      |= 0x01 & (cqcc >> wq->fbc.log_sz);
 141         title->wqe_counter  = cpu_to_be16(cqd->wqe_counter);
 142
 143         if (rq->wq_type == MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ)
 144                 cqd->wqe_counter += mpwrq_get_cqe_consumed_strides(title);
 145         else
 146                 cqd->wqe_counter =
 147                         mlx5_wq_cyc_ctr2ix(&rq->wqe.wq, cqd->wqe_counter + 1);
 148 }
 149
 150 static inline void mlx5e_decompress_cqe_no_hash(struct mlx5e_rq *rq,
 151                                                 struct mlx5_cqwq *wq,
 152                                                 u32 cqcc)
 153 {
 154         struct mlx5e_cq_decomp *cqd = &rq->cqd;
 155
 156         mlx5e_decompress_cqe(rq, wq, cqcc);
 157         cqd->title.rss_hash_type   = 0;
 158         cqd->title.rss_hash_result = 0;
 159 }
 160
 161 static inline u32 mlx5e_decompress_cqes_cont(struct mlx5e_rq *rq,
 162                                              struct mlx5_cqwq *wq,
 163                                              int update_owner_only,
 164                                              int budget_rem)
 165 {
 166         struct mlx5e_cq_decomp *cqd = &rq->cqd;
 167         u32 cqcc = wq->cc + update_owner_only;
 168         u32 cqe_count;
 169         u32 i;
 170
 171         cqe_count = min_t(u32, cqd->left, budget_rem);
 172
 173         for (i = update_owner_only; i < cqe_count;
 174              i++, cqd->mini_arr_idx++, cqcc++) {
 175                 if (cqd->mini_arr_idx == MLX5_MINI_CQE_ARRAY_SIZE)
 176                         mlx5e_read_mini_arr_slot(wq, cqd, cqcc);
 177
 178                 mlx5e_decompress_cqe_no_hash(rq, wq, cqcc);
 179                 INDIRECT_CALL_2(rq->handle_rx_cqe, mlx5e_handle_rx_cqe_mpwrq,
 180                                 mlx5e_handle_rx_cqe, rq, &cqd->title);
 181         }
 182         mlx5e_cqes_update_owner(wq, cqcc - wq->cc);
 183         wq->cc = cqcc;
 184         cqd->left -= cqe_count;
 185         rq->stats->cqe_compress_pkts += cqe_count;
 186
 187         return cqe_count;
 188 }
 189
 190 static inline u32 mlx5e_decompress_cqes_start(struct mlx5e_rq *rq,
 191                                               struct mlx5_cqwq *wq,
 192                                               int budget_rem)
 193 {
 194         struct mlx5e_cq_decomp *cqd = &rq->cqd;
 195         u32 cc = wq->cc;
 196
 197         mlx5e_read_title_slot(rq, wq, cc);
 198         mlx5e_read_mini_arr_slot(wq, cqd, cc + 1);
 199         mlx5e_decompress_cqe(rq, wq, cc);
 200         INDIRECT_CALL_2(rq->handle_rx_cqe, mlx5e_handle_rx_cqe_mpwrq,
 201                         mlx5e_handle_rx_cqe, rq, &cqd->title);
 202         cqd->mini_arr_idx++;
 203
 204         return mlx5e_decompress_cqes_cont(rq, wq, 1, budget_rem) - 1;
 205 }
 206
 207 static inline bool mlx5e_page_is_reserved(struct page *page)
 208 {
 209         return page_is_pfmemalloc(page) || page_to_nid(page) != numa_mem_id();
 210 }
 211
 212 static inline bool mlx5e_rx_cache_put(struct mlx5e_rq *rq,
 213                                       struct mlx5e_dma_info *dma_info)
 214 {
 215         struct mlx5e_page_cache *cache = &rq->page_cache;
 216         u32 tail_next = (cache->tail + 1) & (MLX5E_CACHE_SIZE - 1);
 217         struct mlx5e_rq_stats *stats = rq->stats;
 218
 219         if (tail_next == cache->head) {
 220                 stats->cache_full++;
 221                 return false;
 222         }
 223
 224         if (unlikely(mlx5e_page_is_reserved(dma_info->page))) {
 225                 stats->cache_waive++;
 226                 return false;
 227         }
 228
 229         cache->page_cache[cache->tail] = *dma_info;
 230         cache->tail = tail_next;
 231         return true;
 232 }
 233
 234 static inline bool mlx5e_rx_cache_get(struct mlx5e_rq *rq,
 235                                       struct mlx5e_dma_info *dma_info)
 236 {
 237         struct mlx5e_page_cache *cache = &rq->page_cache;
 238         struct mlx5e_rq_stats *stats = rq->stats;
 239
 240         if (unlikely(cache->head == cache->tail)) {
 241                 stats->cache_empty++;
 242                 return false;
 243         }
 244
 245         if (page_ref_count(cache->page_cache[cache->head].page) != 1) {
 246                 stats->cache_busy++;
 247                 return false;
 248         }
 249
 250         *dma_info = cache->page_cache[cache->head];
 251         cache->head = (cache->head + 1) & (MLX5E_CACHE_SIZE - 1);
 252         stats->cache_reuse++;
 253
 254         dma_sync_single_for_device(rq->pdev, dma_info->addr,
 255                                    PAGE_SIZE,
 256                                    DMA_FROM_DEVICE);
 257         return true;
 258 }
 259
 260 static inline int mlx5e_page_alloc_pool(struct mlx5e_rq *rq,
 261                                         struct mlx5e_dma_info *dma_info)
 262 {
 263         if (mlx5e_rx_cache_get(rq, dma_info))
 264                 return 0;
 265
 266         dma_info->page = page_pool_dev_alloc_pages(rq->page_pool);
 267         if (unlikely(!dma_info->page))
 268                 return -ENOMEM;
 269
 270         dma_info->addr = dma_map_page(rq->pdev, dma_info->page, 0,
 271                                       PAGE_SIZE, rq->buff.map_dir);
 272         if (unlikely(dma_mapping_error(rq->pdev, dma_info->addr))) {
 273                 page_pool_recycle_direct(rq->page_pool, dma_info->page);
 274                 dma_info->page = NULL;
 275                 return -ENOMEM;
 276         }
 277
 278         return 0;
 279 }
 280
 281 static inline int mlx5e_page_alloc(struct mlx5e_rq *rq,
 282                                    struct mlx5e_dma_info *dma_info)
 283 {
 284         if (rq->umem)
 285                 return mlx5e_xsk_page_alloc_umem(rq, dma_info);
 286         else
 287                 return mlx5e_page_alloc_pool(rq, dma_info);
 288 }
 289
 290 void mlx5e_page_dma_unmap(struct mlx5e_rq *rq, struct mlx5e_dma_info *dma_info)
 291 {
 292         dma_unmap_page(rq->pdev, dma_info->addr, PAGE_SIZE, rq->buff.map_dir);
 293 }
 294
 295 void mlx5e_page_release_dynamic(struct mlx5e_rq *rq,
 296                                 struct mlx5e_dma_info *dma_info,
 297                                 bool recycle)
 298 {
 299         if (likely(recycle)) {
 300                 if (mlx5e_rx_cache_put(rq, dma_info))
 301                         return;
 302
 303                 mlx5e_page_dma_unmap(rq, dma_info);
 304                 page_pool_recycle_direct(rq->page_pool, dma_info->page);
 305         } else {
 306                 mlx5e_page_dma_unmap(rq, dma_info);
 307                 page_pool_release_page(rq->page_pool, dma_info->page);
 308                 put_page(dma_info->page);
 309         }
 310 }
 311
 312 static inline void mlx5e_page_release(struct mlx5e_rq *rq,
 313                                       struct mlx5e_dma_info *dma_info,
 314                                       bool recycle)
 315 {
 316         if (rq->umem)
 317                 /* The `recycle` parameter is ignored, and the page is always
 318                  * put into the Reuse Ring, because there is no way to return
 319                  * the page to the userspace when the interface goes down.
 320                  */
 321                 xsk_buff_free(dma_info->xsk);
 322         else
 323                 mlx5e_page_release_dynamic(rq, dma_info, recycle);
 324 }
 325
 326 static inline int mlx5e_get_rx_frag(struct mlx5e_rq *rq,
 327                                     struct mlx5e_wqe_frag_info *frag)
 328 {
 329         int err = 0;
 330
 331         if (!frag->offset)
 332                 /* On first frag (offset == 0), replenish page (dma_info actually).
 333                  * Other frags that point to the same dma_info (with a different
 334                  * offset) should just use the new one without replenishing again
 335                  * by themselves.
 336                  */
 337                 err = mlx5e_page_alloc(rq, frag->di);
 338
 339         return err;
 340 }
 341
 342 static inline void mlx5e_put_rx_frag(struct mlx5e_rq *rq,
 343                                      struct mlx5e_wqe_frag_info *frag,
 344                                      bool recycle)
 345 {
 346         if (frag->last_in_page)
 347                 mlx5e_page_release(rq, frag->di, recycle);
 348 }
 349
 350 static inline struct mlx5e_wqe_frag_info *get_frag(struct mlx5e_rq *rq, u16 ix)
 351 {
 352         return &rq->wqe.frags[ix << rq->wqe.info.log_num_frags];
 353 }
 354
 355 static int mlx5e_alloc_rx_wqe(struct mlx5e_rq *rq, struct mlx5e_rx_wqe_cyc *wqe,
 356                               u16 ix)
 357 {
 358         struct mlx5e_wqe_frag_info *frag = get_frag(rq, ix);
 359         int err;
 360         int i;
 361
 362         for (i = 0; i < rq->wqe.info.num_frags; i++, frag++) {
 363                 err = mlx5e_get_rx_frag(rq, frag);
 364                 if (unlikely(err))
 365                         goto free_frags;
 366
 367                 wqe->data[i].addr = cpu_to_be64(frag->di->addr +
 368                                                 frag->offset + rq->buff.headroom);
 369         }
 370
 371         return 0;
 372
 373 free_frags:
 374         while (--i >= 0)
 375                 mlx5e_put_rx_frag(rq, --frag, true);
 376
 377         return err;
 378 }
 379
 380 static inline void mlx5e_free_rx_wqe(struct mlx5e_rq *rq,
 381                                      struct mlx5e_wqe_frag_info *wi,
 382                                      bool recycle)
 383 {
 384         int i;
 385
 386         for (i = 0; i < rq->wqe.info.num_frags; i++, wi++)
 387                 mlx5e_put_rx_frag(rq, wi, recycle);
 388 }
 389
 390 static void mlx5e_dealloc_rx_wqe(struct mlx5e_rq *rq, u16 ix)
 391 {
 392         struct mlx5e_wqe_frag_info *wi = get_frag(rq, ix);
 393
 394         mlx5e_free_rx_wqe(rq, wi, false);
 395 }
 396
 397 static int mlx5e_alloc_rx_wqes(struct mlx5e_rq *rq, u16 ix, u8 wqe_bulk)
 398 {
 399         struct mlx5_wq_cyc *wq = &rq->wqe.wq;
 400         int err;
 401         int i;
 402
 403         if (rq->umem) {
 404                 int pages_desired = wqe_bulk << rq->wqe.info.log_num_frags;
 405
 406                 /* Check in advance that we have enough frames, instead of
 407                  * allocating one-by-one, failing and moving frames to the
 408                  * Reuse Ring.
 409                  */
 410                 if (unlikely(!xsk_buff_can_alloc(rq->umem, pages_desired)))
 411                         return -ENOMEM;
 412         }
 413
 414         for (i = 0; i < wqe_bulk; i++) {
 415                 struct mlx5e_rx_wqe_cyc *wqe = mlx5_wq_cyc_get_wqe(wq, ix + i);
 416
 417                 err = mlx5e_alloc_rx_wqe(rq, wqe, ix + i);
 418                 if (unlikely(err))
 419                         goto free_wqes;
 420         }
 421
 422         return 0;
 423
 424 free_wqes:
 425         while (--i >= 0)
 426                 mlx5e_dealloc_rx_wqe(rq, ix + i);
 427
 428         return err;
 429 }
 430
 431 static inline void
 432 mlx5e_add_skb_frag(struct mlx5e_rq *rq, struct sk_buff *skb,
 433                    struct mlx5e_dma_info *di, u32 frag_offset, u32 len,
 434                    unsigned int truesize)
 435 {
 436         dma_sync_single_for_cpu(rq->pdev,
 437                                 di->addr + frag_offset,
 438                                 len, DMA_FROM_DEVICE);
 439         page_ref_inc(di->page);
 440         skb_add_rx_frag(skb, skb_shinfo(skb)->nr_frags,
 441                         di->page, frag_offset, len, truesize);
 442 }
 443
 444 static inline void
 445 mlx5e_copy_skb_header(struct device *pdev, struct sk_buff *skb,
 446                       struct mlx5e_dma_info *dma_info,
 447                       int offset_from, u32 headlen)
 448 {
 449         const void *from = page_address(dma_info->page) + offset_from;
 450         /* Aligning len to sizeof(long) optimizes memcpy performance */
 451         unsigned int len = ALIGN(headlen, sizeof(long));
 452
 453         dma_sync_single_for_cpu(pdev, dma_info->addr + offset_from, len,
 454                                 DMA_FROM_DEVICE);
 455         skb_copy_to_linear_data(skb, from, len);
 456 }
 457
 458 static void
 459 mlx5e_free_rx_mpwqe(struct mlx5e_rq *rq, struct mlx5e_mpw_info *wi, bool recycle)
 460 {
 461         bool no_xdp_xmit;
 462         struct mlx5e_dma_info *dma_info = wi->umr.dma_info;
 463         int i;
 464
 465         /* A common case for AF_XDP. */
 466         if (bitmap_full(wi->xdp_xmit_bitmap, MLX5_MPWRQ_PAGES_PER_WQE))
 467                 return;
 468
 469         no_xdp_xmit = bitmap_empty(wi->xdp_xmit_bitmap,
 470                                    MLX5_MPWRQ_PAGES_PER_WQE);
 471
 472         for (i = 0; i < MLX5_MPWRQ_PAGES_PER_WQE; i++)
 473                 if (no_xdp_xmit || !test_bit(i, wi->xdp_xmit_bitmap))
 474                         mlx5e_page_release(rq, &dma_info[i], recycle);
 475 }
 476
 477 static void mlx5e_post_rx_mpwqe(struct mlx5e_rq *rq, u8 n)
 478 {
 479         struct mlx5_wq_ll *wq = &rq->mpwqe.wq;
 480
 481         do {
 482                 u16 next_wqe_index = mlx5_wq_ll_get_wqe_next_ix(wq, wq->head);
 483
 484                 mlx5_wq_ll_push(wq, next_wqe_index);
 485         } while (--n);
 486
 487         /* ensure wqes are visible to device before updating doorbell record */
 488         dma_wmb();
 489
 490         mlx5_wq_ll_update_db_record(wq);
 491 }
 492
 493 static int mlx5e_alloc_rx_mpwqe(struct mlx5e_rq *rq, u16 ix)
 494 {
 495         struct mlx5e_mpw_info *wi = &rq->mpwqe.info[ix];
 496         struct mlx5e_dma_info *dma_info = &wi->umr.dma_info[0];
 497         struct mlx5e_icosq *sq = &rq->channel->icosq;
 498         struct mlx5_wq_cyc *wq = &sq->wq;
 499         struct mlx5e_umr_wqe *umr_wqe;
 500         u16 xlt_offset = ix << (MLX5E_LOG_ALIGNED_MPWQE_PPW - 1);
 501         u16 pi;
 502         int err;
 503         int i;
 504
 505         /* Check in advance that we have enough frames, instead of allocating
 506          * one-by-one, failing and moving frames to the Reuse Ring.
 507          */
 508         if (rq->umem &&
 509             unlikely(!xsk_buff_can_alloc(rq->umem, MLX5_MPWRQ_PAGES_PER_WQE))) {
 510                 err = -ENOMEM;
 511                 goto err;
 512         }
 513
 514         pi = mlx5e_icosq_get_next_pi(sq, MLX5E_UMR_WQEBBS);
 515         umr_wqe = mlx5_wq_cyc_get_wqe(wq, pi);
 516         memcpy(umr_wqe, &rq->mpwqe.umr_wqe, offsetof(struct mlx5e_umr_wqe, inline_mtts));
 517
 518         for (i = 0; i < MLX5_MPWRQ_PAGES_PER_WQE; i++, dma_info++) {
 519                 err = mlx5e_page_alloc(rq, dma_info);
 520                 if (unlikely(err))
 521                         goto err_unmap;
 522                 umr_wqe->inline_mtts[i].ptag = cpu_to_be64(dma_info->addr | MLX5_EN_WR);
 523         }
 524
 525         bitmap_zero(wi->xdp_xmit_bitmap, MLX5_MPWRQ_PAGES_PER_WQE);
 526         wi->consumed_strides = 0;
 527
 528         umr_wqe->ctrl.opmod_idx_opcode =
 529                 cpu_to_be32((sq->pc << MLX5_WQE_CTRL_WQE_INDEX_SHIFT) |
 530                             MLX5_OPCODE_UMR);
 531         umr_wqe->uctrl.xlt_offset = cpu_to_be16(xlt_offset);
 532
 533         sq->db.wqe_info[pi] = (struct mlx5e_icosq_wqe_info) {
 534                 .wqe_type   = MLX5E_ICOSQ_WQE_UMR_RX,
 535                 .num_wqebbs = MLX5E_UMR_WQEBBS,
 536                 .umr.rq     = rq,
 537         };
 538
 539         sq->pc += MLX5E_UMR_WQEBBS;
 540
 541         sq->doorbell_cseg = &umr_wqe->ctrl;
 542
 543         return 0;
 544
 545 err_unmap:
 546         while (--i >= 0) {
 547                 dma_info--;
 548                 mlx5e_page_release(rq, dma_info, true);
 549         }
 550
 551 err:
 552         rq->stats->buff_alloc_err++;
 553
 554         return err;
 555 }
 556
 557 static void mlx5e_dealloc_rx_mpwqe(struct mlx5e_rq *rq, u16 ix)
 558 {
 559         struct mlx5e_mpw_info *wi = &rq->mpwqe.info[ix];
 560         /* Don't recycle, this function is called on rq/netdev close */
 561         mlx5e_free_rx_mpwqe(rq, wi, false);
 562 }
 563
 564 bool mlx5e_post_rx_wqes(struct mlx5e_rq *rq)
 565 {
 566         struct mlx5_wq_cyc *wq = &rq->wqe.wq;
 567         u8 wqe_bulk;
 568         int err;
 569
 570         if (unlikely(!test_bit(MLX5E_RQ_STATE_ENABLED, &rq->state)))
 571                 return false;
 572
 573         wqe_bulk = rq->wqe.info.wqe_bulk;
 574
 575         if (mlx5_wq_cyc_missing(wq) < wqe_bulk)
 576                 return false;
 577
 578         do {
 579                 u16 head = mlx5_wq_cyc_get_head(wq);
 580
 581                 err = mlx5e_alloc_rx_wqes(rq, head, wqe_bulk);
 582                 if (unlikely(err)) {
 583                         rq->stats->buff_alloc_err++;
 584                         break;
 585                 }
 586
 587                 mlx5_wq_cyc_push_n(wq, wqe_bulk);
 588         } while (mlx5_wq_cyc_missing(wq) >= wqe_bulk);
 589
 590         /* ensure wqes are visible to device before updating doorbell record */
 591         dma_wmb();
 592
 593         mlx5_wq_cyc_update_db_record(wq);
 594
 595         return !!err;
 596 }
 597
 598 void mlx5e_free_icosq_descs(struct mlx5e_icosq *sq)
 599 {
 600         u16 sqcc;
 601
 602         sqcc = sq->cc;
 603
 604         while (sqcc != sq->pc) {
 605                 struct mlx5e_icosq_wqe_info *wi;
 606                 u16 ci;
 607
 608                 ci = mlx5_wq_cyc_ctr2ix(&sq->wq, sqcc);
 609                 wi = &sq->db.wqe_info[ci];
 610                 sqcc += wi->num_wqebbs;
 611 #ifdef CONFIG_MLX5_EN_TLS
 612                 switch (wi->wqe_type) {
 613                 case MLX5E_ICOSQ_WQE_SET_PSV_TLS:
 614                         mlx5e_ktls_handle_ctx_completion(wi);
 615                         break;
 616                 case MLX5E_ICOSQ_WQE_GET_PSV_TLS:
 617                         mlx5e_ktls_handle_get_psv_completion(wi, sq);
 618                         break;
 619                 }
 620 #endif
 621         }
 622         sq->cc = sqcc;
 623 }
 624
 625 int mlx5e_poll_ico_cq(struct mlx5e_cq *cq)
 626 {
 627         struct mlx5e_icosq *sq = container_of(cq, struct mlx5e_icosq, cq);
 628         struct mlx5_cqe64 *cqe;
 629         u16 sqcc;
 630         int i;
 631
 632         if (unlikely(!test_bit(MLX5E_SQ_STATE_ENABLED, &sq->state)))
 633                 return 0;
 634
 635         cqe = mlx5_cqwq_get_cqe(&cq->wq);
 636         if (likely(!cqe))
 637                 return 0;
 638
 639         /* sq->cc must be updated only after mlx5_cqwq_update_db_record(),
 640          * otherwise a cq overrun may occur
 641          */
 642         sqcc = sq->cc;
 643
 644         i = 0;
 645         do {
 646                 u16 wqe_counter;
 647                 bool last_wqe;
 648
 649                 mlx5_cqwq_pop(&cq->wq);
 650
 651                 wqe_counter = be16_to_cpu(cqe->wqe_counter);
 652
 653                 do {
 654                         struct mlx5e_icosq_wqe_info *wi;
 655                         u16 ci;
 656
 657                         last_wqe = (sqcc == wqe_counter);
 658
 659                         ci = mlx5_wq_cyc_ctr2ix(&sq->wq, sqcc);
 660                         wi = &sq->db.wqe_info[ci];
 661                         sqcc += wi->num_wqebbs;
 662
 663                         if (last_wqe && unlikely(get_cqe_opcode(cqe) != MLX5_CQE_REQ)) {
 664                                 netdev_WARN_ONCE(cq->channel->netdev,
 665                                                  "Bad OP in ICOSQ CQE: 0x%x\n",
 666                                                  get_cqe_opcode(cqe));
 667                                 mlx5e_dump_error_cqe(&sq->cq, sq->sqn,
 668                                                      (struct mlx5_err_cqe *)cqe);
 669                                 if (!test_and_set_bit(MLX5E_SQ_STATE_RECOVERING, &sq->state))
 670                                         queue_work(cq->channel->priv->wq, &sq->recover_work);
 671                                 break;
 672                         }
 673
 674                         switch (wi->wqe_type) {
 675                         case MLX5E_ICOSQ_WQE_UMR_RX:
 676                                 wi->umr.rq->mpwqe.umr_completed++;
 677                                 break;
 678                         case MLX5E_ICOSQ_WQE_NOP:
 679                                 break;
 680 #ifdef CONFIG_MLX5_EN_TLS
 681                         case MLX5E_ICOSQ_WQE_UMR_TLS:
 682                                 break;
 683                         case MLX5E_ICOSQ_WQE_SET_PSV_TLS:
 684                                 mlx5e_ktls_handle_ctx_completion(wi);
 685                                 break;
 686                         case MLX5E_ICOSQ_WQE_GET_PSV_TLS:
 687                                 mlx5e_ktls_handle_get_psv_completion(wi, sq);
 688                                 break;
 689 #endif
 690                         default:
 691                                 netdev_WARN_ONCE(cq->channel->netdev,
 692                                                  "Bad WQE type in ICOSQ WQE info: 0x%x\n",
 693                                                  wi->wqe_type);
 694                         }
 695                 } while (!last_wqe);
 696         } while ((++i < MLX5E_TX_CQ_POLL_BUDGET) && (cqe = mlx5_cqwq_get_cqe(&cq->wq)));
 697
 698         sq->cc = sqcc;
 699
 700         mlx5_cqwq_update_db_record(&cq->wq);
 701
 702         return i;
 703 }
 704
 705 bool mlx5e_post_rx_mpwqes(struct mlx5e_rq *rq)
 706 {
 707         struct mlx5e_icosq *sq = &rq->channel->icosq;
 708         struct mlx5_wq_ll *wq = &rq->mpwqe.wq;
 709         u8  umr_completed = rq->mpwqe.umr_completed;
 710         int alloc_err = 0;
 711         u8  missing, i;
 712         u16 head;
 713
 714         if (unlikely(!test_bit(MLX5E_RQ_STATE_ENABLED, &rq->state)))
 715                 return false;
 716
 717         if (umr_completed) {
 718                 mlx5e_post_rx_mpwqe(rq, umr_completed);
 719                 rq->mpwqe.umr_in_progress -= umr_completed;
 720                 rq->mpwqe.umr_completed = 0;
 721         }
 722
 723         missing = mlx5_wq_ll_missing(wq) - rq->mpwqe.umr_in_progress;
 724
 725         if (unlikely(rq->mpwqe.umr_in_progress > rq->mpwqe.umr_last_bulk))
 726                 rq->stats->congst_umr++;
 727
 728 #define UMR_WQE_BULK (2)
 729         if (likely(missing < UMR_WQE_BULK))
 730                 return false;
 731
 732         head = rq->mpwqe.actual_wq_head;
 733         i = missing;
 734         do {
 735                 alloc_err = mlx5e_alloc_rx_mpwqe(rq, head);
 736
 737                 if (unlikely(alloc_err))
 738                         break;
 739                 head = mlx5_wq_ll_get_wqe_next_ix(wq, head);
 740         } while (--i);
 741
 742         rq->mpwqe.umr_last_bulk    = missing - i;
 743         if (sq->doorbell_cseg) {
 744                 mlx5e_notify_hw(&sq->wq, sq->pc, sq->uar_map, sq->doorbell_cseg);
 745                 sq->doorbell_cseg = NULL;
 746         }
 747
 748         rq->mpwqe.umr_in_progress += rq->mpwqe.umr_last_bulk;
 749         rq->mpwqe.actual_wq_head   = head;
 750
 751         /* If XSK Fill Ring doesn't have enough frames, report the error, so
 752          * that one of the actions can be performed:
 753          * 1. If need_wakeup is used, signal that the application has to kick
 754          * the driver when it refills the Fill Ring.
 755          * 2. Otherwise, busy poll by rescheduling the NAPI poll.
 756          */
 757         if (unlikely(alloc_err == -ENOMEM && rq->umem))
 758                 return true;
 759
 760         return false;
 761 }
 762
 763 static void mlx5e_lro_update_tcp_hdr(struct mlx5_cqe64 *cqe, struct tcphdr *tcp)
 764 {
 765         u8 l4_hdr_type = get_cqe_l4_hdr_type(cqe);
 766         u8 tcp_ack     = (l4_hdr_type == CQE_L4_HDR_TYPE_TCP_ACK_NO_DATA) ||
 767                          (l4_hdr_type == CQE_L4_HDR_TYPE_TCP_ACK_AND_DATA);
 768
 769         tcp->check                      = 0;
 770         tcp->psh                        = get_cqe_lro_tcppsh(cqe);
 771
 772         if (tcp_ack) {
 773                 tcp->ack                = 1;
 774                 tcp->ack_seq            = cqe->lro_ack_seq_num;
 775                 tcp->window             = cqe->lro_tcp_win;
 776         }
 777 }
 778
 779 static void mlx5e_lro_update_hdr(struct sk_buff *skb, struct mlx5_cqe64 *cqe,
 780                                  u32 cqe_bcnt)
 781 {
 782         struct ethhdr   *eth = (struct ethhdr *)(skb->data);
 783         struct tcphdr   *tcp;
 784         int network_depth = 0;
 785         __wsum check;
 786         __be16 proto;
 787         u16 tot_len;
 788         void *ip_p;
 789
 790         proto = __vlan_get_protocol(skb, eth->h_proto, &network_depth);
 791
 792         tot_len = cqe_bcnt - network_depth;
 793         ip_p = skb->data + network_depth;
 794
 795         if (proto == htons(ETH_P_IP)) {
 796                 struct iphdr *ipv4 = ip_p;
 797
 798                 tcp = ip_p + sizeof(struct iphdr);
 799                 skb_shinfo(skb)->gso_type = SKB_GSO_TCPV4;
 800
 801                 ipv4->ttl               = cqe->lro_min_ttl;
 802                 ipv4->tot_len           = cpu_to_be16(tot_len);
 803                 ipv4->check             = 0;
 804                 ipv4->check             = ip_fast_csum((unsigned char *)ipv4,
 805                                                        ipv4->ihl);
 806
 807                 mlx5e_lro_update_tcp_hdr(cqe, tcp);
 808                 check = csum_partial(tcp, tcp->doff * 4,
 809                                      csum_unfold((__force __sum16)cqe->check_sum));
 810                 /* Almost done, don't forget the pseudo header */
 811                 tcp->check = csum_tcpudp_magic(ipv4->saddr, ipv4->daddr,
 812                                                tot_len - sizeof(struct iphdr),
 813                                                IPPROTO_TCP, check);
 814         } else {
 815                 u16 payload_len = tot_len - sizeof(struct ipv6hdr);
 816                 struct ipv6hdr *ipv6 = ip_p;
 817
 818                 tcp = ip_p + sizeof(struct ipv6hdr);
 819                 skb_shinfo(skb)->gso_type = SKB_GSO_TCPV6;
 820
 821                 ipv6->hop_limit         = cqe->lro_min_ttl;
 822                 ipv6->payload_len       = cpu_to_be16(payload_len);
 823
 824                 mlx5e_lro_update_tcp_hdr(cqe, tcp);
 825                 check = csum_partial(tcp, tcp->doff * 4,
 826                                      csum_unfold((__force __sum16)cqe->check_sum));
 827                 /* Almost done, don't forget the pseudo header */
 828                 tcp->check = csum_ipv6_magic(&ipv6->saddr, &ipv6->daddr, payload_len,
 829                                              IPPROTO_TCP, check);
 830         }
 831 }
 832
 833 static inline void mlx5e_skb_set_hash(struct mlx5_cqe64 *cqe,
 834                                       struct sk_buff *skb)
 835 {
 836         u8 cht = cqe->rss_hash_type;
 837         int ht = (cht & CQE_RSS_HTYPE_L4) ? PKT_HASH_TYPE_L4 :
 838                  (cht & CQE_RSS_HTYPE_IP) ? PKT_HASH_TYPE_L3 :
 839                                             PKT_HASH_TYPE_NONE;
 840         skb_set_hash(skb, be32_to_cpu(cqe->rss_hash_result), ht);
 841 }
 842
 843 static inline bool is_last_ethertype_ip(struct sk_buff *skb, int *network_depth,
 844                                         __be16 *proto)
 845 {
 846         *proto = ((struct ethhdr *)skb->data)->h_proto;
 847         *proto = __vlan_get_protocol(skb, *proto, network_depth);
 848
 849         if (*proto == htons(ETH_P_IP))
 850                 return pskb_may_pull(skb, *network_depth + sizeof(struct iphdr));
 851
 852         if (*proto == htons(ETH_P_IPV6))
 853                 return pskb_may_pull(skb, *network_depth + sizeof(struct ipv6hdr));
 854
 855         return false;
 856 }
 857
 858 static inline void mlx5e_enable_ecn(struct mlx5e_rq *rq, struct sk_buff *skb)
 859 {
 860         int network_depth = 0;
 861         __be16 proto;
 862         void *ip;
 863         int rc;
 864
 865         if (unlikely(!is_last_ethertype_ip(skb, &network_depth, &proto)))
 866                 return;
 867
 868         ip = skb->data + network_depth;
 869         rc = ((proto == htons(ETH_P_IP)) ? IP_ECN_set_ce((struct iphdr *)ip) :
 870                                          IP6_ECN_set_ce(skb, (struct ipv6hdr *)ip));
 871
 872         rq->stats->ecn_mark += !!rc;
 873 }
 874
 875 static u8 get_ip_proto(struct sk_buff *skb, int network_depth, __be16 proto)
 876 {
 877         void *ip_p = skb->data + network_depth;
 878
 879         return (proto == htons(ETH_P_IP)) ? ((struct iphdr *)ip_p)->protocol :
 880                                             ((struct ipv6hdr *)ip_p)->nexthdr;
 881 }
 882
 883 #define short_frame(size) ((size) <= ETH_ZLEN + ETH_FCS_LEN)
 884
 885 #define MAX_PADDING 8
 886
 887 static void
 888 tail_padding_csum_slow(struct sk_buff *skb, int offset, int len,
 889                        struct mlx5e_rq_stats *stats)
 890 {
 891         stats->csum_complete_tail_slow++;
 892         skb->csum = csum_block_add(skb->csum,
 893                                    skb_checksum(skb, offset, len, 0),
 894                                    offset);
 895 }
 896
 897 static void
 898 tail_padding_csum(struct sk_buff *skb, int offset,
 899                   struct mlx5e_rq_stats *stats)
 900 {
 901         u8 tail_padding[MAX_PADDING];
 902         int len = skb->len - offset;
 903         void *tail;
 904
 905         if (unlikely(len > MAX_PADDING)) {
 906                 tail_padding_csum_slow(skb, offset, len, stats);
 907                 return;
 908         }
 909
 910         tail = skb_header_pointer(skb, offset, len, tail_padding);
 911         if (unlikely(!tail)) {
 912                 tail_padding_csum_slow(skb, offset, len, stats);
 913                 return;
 914         }
 915
 916         stats->csum_complete_tail++;
 917         skb->csum = csum_block_add(skb->csum, csum_partial(tail, len, 0), offset);
 918 }
 919
 920 static void
 921 mlx5e_skb_csum_fixup(struct sk_buff *skb, int network_depth, __be16 proto,
 922                      struct mlx5e_rq_stats *stats)
 923 {
 924         struct ipv6hdr *ip6;
 925         struct iphdr   *ip4;
 926         int pkt_len;
 927
 928         /* Fixup vlan headers, if any */
 929         if (network_depth > ETH_HLEN)
 930                 /* CQE csum is calculated from the IP header and does
 931                  * not cover VLAN headers (if present). This will add
 932                  * the checksum manually.
 933                  */
 934                 skb->csum = csum_partial(skb->data + ETH_HLEN,
 935                                          network_depth - ETH_HLEN,
 936                                          skb->csum);
 937
 938         /* Fixup tail padding, if any */
 939         switch (proto) {
 940         case htons(ETH_P_IP):
 941                 ip4 = (struct iphdr *)(skb->data + network_depth);
 942                 pkt_len = network_depth + ntohs(ip4->tot_len);
 943                 break;
 944         case htons(ETH_P_IPV6):
 945                 ip6 = (struct ipv6hdr *)(skb->data + network_depth);
 946                 pkt_len = network_depth + sizeof(*ip6) + ntohs(ip6->payload_len);
 947                 break;
 948         default:
 949                 return;
 950         }
 951
 952         if (likely(pkt_len >= skb->len))
 953                 return;
 954
 955         tail_padding_csum(skb, pkt_len, stats);
 956 }
 957
 958 static inline void mlx5e_handle_csum(struct net_device *netdev,
 959                                      struct mlx5_cqe64 *cqe,
 960                                      struct mlx5e_rq *rq,
 961                                      struct sk_buff *skb,
 962                                      bool   lro)
 963 {
 964         struct mlx5e_rq_stats *stats = rq->stats;
 965         int network_depth = 0;
 966         __be16 proto;
 967
 968         if (unlikely(!(netdev->features & NETIF_F_RXCSUM)))
 969                 goto csum_none;
 970
 971         if (lro) {
 972                 skb->ip_summed = CHECKSUM_UNNECESSARY;
 973                 stats->csum_unnecessary++;
 974                 return;
 975         }
 976
 977         /* True when explicitly set via priv flag, or XDP prog is loaded */
 978         if (test_bit(MLX5E_RQ_STATE_NO_CSUM_COMPLETE, &rq->state))
 979                 goto csum_unnecessary;
 980
 981         /* CQE csum doesn't cover padding octets in short ethernet
 982          * frames. And the pad field is appended prior to calculating
 983          * and appending the FCS field.
 984          *
 985          * Detecting these padded frames requires to verify and parse
 986          * IP headers, so we simply force all those small frames to be
 987          * CHECKSUM_UNNECESSARY even if they are not padded.
 988          */
 989         if (short_frame(skb->len))
 990                 goto csum_unnecessary;
 991
 992         if (likely(is_last_ethertype_ip(skb, &network_depth, &proto))) {
 993                 u8 ipproto = get_ip_proto(skb, network_depth, proto);
 994
 995                 if (unlikely(ipproto == IPPROTO_SCTP))
 996                         goto csum_unnecessary;
 997
 998                 if (unlikely(mlx5_ipsec_is_rx_flow(cqe)))
 999                         goto csum_none;
1000
1001                 stats->csum_complete++;
1002                 skb->ip_summed = CHECKSUM_COMPLETE;
1003                 skb->csum = csum_unfold((__force __sum16)cqe->check_sum);
1004
1005                 if (test_bit(MLX5E_RQ_STATE_CSUM_FULL, &rq->state))
1006                         return; /* CQE csum covers all received bytes */
1007
1008                 /* csum might need some fixups ...*/
1009                 mlx5e_skb_csum_fixup(skb, network_depth, proto, stats);
1010                 return;
1011         }
1012
1013 csum_unnecessary:
1014         if (likely((cqe->hds_ip_ext & CQE_L3_OK) &&
1015                    (cqe->hds_ip_ext & CQE_L4_OK))) {
1016                 skb->ip_summed = CHECKSUM_UNNECESSARY;
1017                 if (cqe_is_tunneled(cqe)) {
1018                         skb->csum_level = 1;
1019                         skb->encapsulation = 1;
1020                         stats->csum_unnecessary_inner++;
1021                         return;
1022                 }
1023                 stats->csum_unnecessary++;
1024                 return;
1025         }
1026 csum_none:
1027         skb->ip_summed = CHECKSUM_NONE;
1028         stats->csum_none++;
1029 }
1030
1031 #define MLX5E_CE_BIT_MASK 0x80
1032
1033 static inline void mlx5e_build_rx_skb(struct mlx5_cqe64 *cqe,
1034                                       u32 cqe_bcnt,
1035                                       struct mlx5e_rq *rq,
1036                                       struct sk_buff *skb)
1037 {
1038         u8 lro_num_seg = be32_to_cpu(cqe->srqn) >> 24;
1039         struct mlx5e_rq_stats *stats = rq->stats;
1040         struct net_device *netdev = rq->netdev;
1041
1042         skb->mac_len = ETH_HLEN;
1043
1044         mlx5e_tls_handle_rx_skb(rq, skb, cqe, &cqe_bcnt);
1045
1046         if (unlikely(mlx5_ipsec_is_rx_flow(cqe)))
1047                 mlx5e_ipsec_offload_handle_rx_skb(netdev, skb, cqe);
1048
1049         if (lro_num_seg > 1) {
1050                 mlx5e_lro_update_hdr(skb, cqe, cqe_bcnt);
1051                 skb_shinfo(skb)->gso_size = DIV_ROUND_UP(cqe_bcnt, lro_num_seg);
1052                 /* Subtract one since we already counted this as one
1053                  * "regular" packet in mlx5e_complete_rx_cqe()
1054                  */
1055                 stats->packets += lro_num_seg - 1;
1056                 stats->lro_packets++;
1057                 stats->lro_bytes += cqe_bcnt;
1058         }
1059
1060         if (unlikely(mlx5e_rx_hw_stamp(rq->tstamp)))
1061                 skb_hwtstamps(skb)->hwtstamp =
1062                                 mlx5_timecounter_cyc2time(rq->clock, get_cqe_ts(cqe));
1063
1064         skb_record_rx_queue(skb, rq->ix);
1065
1066         if (likely(netdev->features & NETIF_F_RXHASH))
1067                 mlx5e_skb_set_hash(cqe, skb);
1068
1069         if (cqe_has_vlan(cqe)) {
1070                 __vlan_hwaccel_put_tag(skb, htons(ETH_P_8021Q),
1071                                        be16_to_cpu(cqe->vlan_info));
1072                 stats->removed_vlan_packets++;
1073         }
1074
1075         skb->mark = be32_to_cpu(cqe->sop_drop_qpn) & MLX5E_TC_FLOW_ID_MASK;
1076
1077         mlx5e_handle_csum(netdev, cqe, rq, skb, !!lro_num_seg);
1078         /* checking CE bit in cqe - MSB in ml_path field */
1079         if (unlikely(cqe->ml_path & MLX5E_CE_BIT_MASK))
1080                 mlx5e_enable_ecn(rq, skb);
1081
1082         skb->protocol = eth_type_trans(skb, netdev);
1083 }
1084
1085 static inline void mlx5e_complete_rx_cqe(struct mlx5e_rq *rq,
1086                                          struct mlx5_cqe64 *cqe,
1087                                          u32 cqe_bcnt,
1088                                          struct sk_buff *skb)
1089 {
1090         struct mlx5e_rq_stats *stats = rq->stats;
1091
1092         stats->packets++;
1093         stats->bytes += cqe_bcnt;
1094         mlx5e_build_rx_skb(cqe, cqe_bcnt, rq, skb);
1095 }
1096
1097 static inline
1098 struct sk_buff *mlx5e_build_linear_skb(struct mlx5e_rq *rq, void *va,
1099                                        u32 frag_size, u16 headroom,
1100                                        u32 cqe_bcnt)
1101 {
1102         struct sk_buff *skb = build_skb(va, frag_size);
1103
1104         if (unlikely(!skb)) {
1105                 rq->stats->buff_alloc_err++;
1106                 return NULL;
1107         }
1108
1109         skb_reserve(skb, headroom);
1110         skb_put(skb, cqe_bcnt);
1111
1112         return skb;
1113 }
1114
1115 static void mlx5e_fill_xdp_buff(struct mlx5e_rq *rq, void *va, u16 headroom,
1116                                 u32 len, struct xdp_buff *xdp)
1117 {
1118         xdp->data_hard_start = va;
1119         xdp->data = va + headroom;
1120         xdp_set_data_meta_invalid(xdp);
1121         xdp->data_end = xdp->data + len;
1122         xdp->rxq = &rq->xdp_rxq;
1123         xdp->frame_sz = rq->buff.frame0_sz;
1124 }
1125
1126 static struct sk_buff *
1127 mlx5e_skb_from_cqe_linear(struct mlx5e_rq *rq, struct mlx5_cqe64 *cqe,
1128                           struct mlx5e_wqe_frag_info *wi, u32 cqe_bcnt)
1129 {
1130         struct mlx5e_dma_info *di = wi->di;
1131         u16 rx_headroom = rq->buff.headroom;
1132         struct xdp_buff xdp;
1133         struct sk_buff *skb;
1134         void *va, *data;
1135         bool consumed;
1136         u32 frag_size;
1137
1138         va             = page_address(di->page) + wi->offset;
1139         data           = va + rx_headroom;
1140         frag_size      = MLX5_SKB_FRAG_SZ(rx_headroom + cqe_bcnt);
1141
1142         dma_sync_single_range_for_cpu(rq->pdev, di->addr, wi->offset,
1143                                       frag_size, DMA_FROM_DEVICE);
1144         prefetchw(va); /* xdp_frame data area */
1145         prefetch(data);
1146
1147         rcu_read_lock();
1148         mlx5e_fill_xdp_buff(rq, va, rx_headroom, cqe_bcnt, &xdp);
1149         consumed = mlx5e_xdp_handle(rq, di, &cqe_bcnt, &xdp);
1150         rcu_read_unlock();
1151         if (consumed)
1152                 return NULL; /* page/packet was consumed by XDP */
1153
1154         rx_headroom = xdp.data - xdp.data_hard_start;
1155         frag_size = MLX5_SKB_FRAG_SZ(rx_headroom + cqe_bcnt);
1156         skb = mlx5e_build_linear_skb(rq, va, frag_size, rx_headroom, cqe_bcnt);
1157         if (unlikely(!skb))
1158                 return NULL;
1159
1160         /* queue up for recycling/reuse */
1161         page_ref_inc(di->page);
1162
1163         return skb;
1164 }
1165
1166 static struct sk_buff *
1167 mlx5e_skb_from_cqe_nonlinear(struct mlx5e_rq *rq, struct mlx5_cqe64 *cqe,
1168                              struct mlx5e_wqe_frag_info *wi, u32 cqe_bcnt)
1169 {
1170         struct mlx5e_rq_frag_info *frag_info = &rq->wqe.info.arr[0];
1171         struct mlx5e_wqe_frag_info *head_wi = wi;
1172         u16 headlen      = min_t(u32, MLX5E_RX_MAX_HEAD, cqe_bcnt);
1173         u16 frag_headlen = headlen;
1174         u16 byte_cnt     = cqe_bcnt - headlen;
1175         struct sk_buff *skb;
1176
1177         /* XDP is not supported in this configuration, as incoming packets
1178          * might spread among multiple pages.
1179          */
1180         skb = napi_alloc_skb(rq->cq.napi,
1181                              ALIGN(MLX5E_RX_MAX_HEAD, sizeof(long)));
1182         if (unlikely(!skb)) {
1183                 rq->stats->buff_alloc_err++;
1184                 return NULL;
1185         }
1186
1187         prefetchw(skb->data);
1188
1189         while (byte_cnt) {
1190                 u16 frag_consumed_bytes =
1191                         min_t(u16, frag_info->frag_size - frag_headlen, byte_cnt);
1192
1193                 mlx5e_add_skb_frag(rq, skb, wi->di, wi->offset + frag_headlen,
1194                                    frag_consumed_bytes, frag_info->frag_stride);
1195                 byte_cnt -= frag_consumed_bytes;
1196                 frag_headlen = 0;
1197                 frag_info++;
1198                 wi++;
1199         }
1200
1201         /* copy header */
1202         mlx5e_copy_skb_header(rq->pdev, skb, head_wi->di, head_wi->offset, headlen);
1203         /* skb linear part was allocated with headlen and aligned to long */
1204         skb->tail += headlen;
1205         skb->len  += headlen;
1206
1207         return skb;
1208 }
1209
1210 static void trigger_report(struct mlx5e_rq *rq, struct mlx5_cqe64 *cqe)
1211 {
1212         struct mlx5_err_cqe *err_cqe = (struct mlx5_err_cqe *)cqe;
1213
1214         if (cqe_syndrome_needs_recover(err_cqe->syndrome) &&
1215             !test_and_set_bit(MLX5E_RQ_STATE_RECOVERING, &rq->state)) {
1216                 mlx5e_dump_error_cqe(&rq->cq, rq->rqn, err_cqe);
1217                 queue_work(rq->channel->priv->wq, &rq->recover_work);
1218         }
1219 }
1220
1221 static void mlx5e_handle_rx_cqe(struct mlx5e_rq *rq, struct mlx5_cqe64 *cqe)
1222 {
1223         struct mlx5_wq_cyc *wq = &rq->wqe.wq;
1224         struct mlx5e_wqe_frag_info *wi;
1225         struct sk_buff *skb;
1226         u32 cqe_bcnt;
1227         u16 ci;
1228
1229         ci       = mlx5_wq_cyc_ctr2ix(wq, be16_to_cpu(cqe->wqe_counter));
1230         wi       = get_frag(rq, ci);
1231         cqe_bcnt = be32_to_cpu(cqe->byte_cnt);
1232
1233         if (unlikely(MLX5E_RX_ERR_CQE(cqe))) {
1234                 trigger_report(rq, cqe);
1235                 rq->stats->wqe_err++;
1236                 goto free_wqe;
1237         }
1238
1239         skb = INDIRECT_CALL_2(rq->wqe.skb_from_cqe,
1240                               mlx5e_skb_from_cqe_linear,
1241                               mlx5e_skb_from_cqe_nonlinear,
1242                               rq, cqe, wi, cqe_bcnt);
1243         if (!skb) {
1244                 /* probably for XDP */
1245                 if (__test_and_clear_bit(MLX5E_RQ_FLAG_XDP_XMIT, rq->flags)) {
1246                         /* do not return page to cache,
1247                          * it will be returned on XDP_TX completion.
1248                          */
1249                         goto wq_cyc_pop;
1250                 }
1251                 goto free_wqe;
1252         }
1253
1254         mlx5e_complete_rx_cqe(rq, cqe, cqe_bcnt, skb);
1255         napi_gro_receive(rq->cq.napi, skb);
1256
1257 free_wqe:
1258         mlx5e_free_rx_wqe(rq, wi, true);
1259 wq_cyc_pop:
1260         mlx5_wq_cyc_pop(wq);
1261 }
1262
1263 #ifdef CONFIG_MLX5_ESWITCH
1264 static void mlx5e_handle_rx_cqe_rep(struct mlx5e_rq *rq, struct mlx5_cqe64 *cqe)
1265 {
1266         struct net_device *netdev = rq->netdev;
1267         struct mlx5e_priv *priv = netdev_priv(netdev);
1268         struct mlx5e_rep_priv *rpriv  = priv->ppriv;
1269         struct mlx5_eswitch_rep *rep = rpriv->rep;
1270         struct mlx5e_tc_update_priv tc_priv = {};
1271         struct mlx5_wq_cyc *wq = &rq->wqe.wq;
1272         struct mlx5e_wqe_frag_info *wi;
1273         struct sk_buff *skb;
1274         u32 cqe_bcnt;
1275         u16 ci;
1276
1277         ci       = mlx5_wq_cyc_ctr2ix(wq, be16_to_cpu(cqe->wqe_counter));
1278         wi       = get_frag(rq, ci);
1279         cqe_bcnt = be32_to_cpu(cqe->byte_cnt);
1280
1281         if (unlikely(MLX5E_RX_ERR_CQE(cqe))) {
1282                 rq->stats->wqe_err++;
1283                 goto free_wqe;
1284         }
1285
1286         skb = INDIRECT_CALL_2(rq->wqe.skb_from_cqe,
1287                               mlx5e_skb_from_cqe_linear,
1288                               mlx5e_skb_from_cqe_nonlinear,
1289                               rq, cqe, wi, cqe_bcnt);
1290         if (!skb) {
1291                 /* probably for XDP */
1292                 if (__test_and_clear_bit(MLX5E_RQ_FLAG_XDP_XMIT, rq->flags)) {
1293                         /* do not return page to cache,
1294                          * it will be returned on XDP_TX completion.
1295                          */
1296                         goto wq_cyc_pop;
1297                 }
1298                 goto free_wqe;
1299         }
1300
1301         mlx5e_complete_rx_cqe(rq, cqe, cqe_bcnt, skb);
1302
1303         if (rep->vlan && skb_vlan_tag_present(skb))
1304                 skb_vlan_pop(skb);
1305
1306         if (!mlx5e_rep_tc_update_skb(cqe, skb, &tc_priv))
1307                 goto free_wqe;
1308
1309         napi_gro_receive(rq->cq.napi, skb);
1310
1311         mlx5_rep_tc_post_napi_receive(&tc_priv);
1312
1313 free_wqe:
1314         mlx5e_free_rx_wqe(rq, wi, true);
1315 wq_cyc_pop:
1316         mlx5_wq_cyc_pop(wq);
1317 }
1318
1319 static void mlx5e_handle_rx_cqe_mpwrq_rep(struct mlx5e_rq *rq, struct mlx5_cqe64 *cqe)
1320 {
1321         u16 cstrides       = mpwrq_get_cqe_consumed_strides(cqe);
1322         u16 wqe_id         = be16_to_cpu(cqe->wqe_id);
1323         struct mlx5e_mpw_info *wi = &rq->mpwqe.info[wqe_id];
1324         u16 stride_ix      = mpwrq_get_cqe_stride_index(cqe);
1325         u32 wqe_offset     = stride_ix << rq->mpwqe.log_stride_sz;
1326         u32 head_offset    = wqe_offset & (PAGE_SIZE - 1);
1327         u32 page_idx       = wqe_offset >> PAGE_SHIFT;
1328         struct mlx5e_tc_update_priv tc_priv = {};
1329         struct mlx5e_rx_wqe_ll *wqe;
1330         struct mlx5_wq_ll *wq;
1331         struct sk_buff *skb;
1332         u16 cqe_bcnt;
1333
1334         wi->consumed_strides += cstrides;
1335
1336         if (unlikely(MLX5E_RX_ERR_CQE(cqe))) {
1337                 trigger_report(rq, cqe);
1338                 rq->stats->wqe_err++;
1339                 goto mpwrq_cqe_out;
1340         }
1341
1342         if (unlikely(mpwrq_is_filler_cqe(cqe))) {
1343                 struct mlx5e_rq_stats *stats = rq->stats;
1344
1345                 stats->mpwqe_filler_cqes++;
1346                 stats->mpwqe_filler_strides += cstrides;
1347                 goto mpwrq_cqe_out;
1348         }
1349
1350         cqe_bcnt = mpwrq_get_cqe_byte_cnt(cqe);
1351
1352         skb = INDIRECT_CALL_2(rq->mpwqe.skb_from_cqe_mpwrq,
1353                               mlx5e_skb_from_cqe_mpwrq_linear,
1354                               mlx5e_skb_from_cqe_mpwrq_nonlinear,
1355                               rq, wi, cqe_bcnt, head_offset, page_idx);
1356         if (!skb)
1357                 goto mpwrq_cqe_out;
1358
1359         mlx5e_complete_rx_cqe(rq, cqe, cqe_bcnt, skb);
1360
1361         if (!mlx5e_rep_tc_update_skb(cqe, skb, &tc_priv))
1362                 goto mpwrq_cqe_out;
1363
1364         napi_gro_receive(rq->cq.napi, skb);
1365
1366         mlx5_rep_tc_post_napi_receive(&tc_priv);
1367
1368 mpwrq_cqe_out:
1369         if (likely(wi->consumed_strides < rq->mpwqe.num_strides))
1370                 return;
1371
1372         wq  = &rq->mpwqe.wq;
1373         wqe = mlx5_wq_ll_get_wqe(wq, wqe_id);
1374         mlx5e_free_rx_mpwqe(rq, wi, true);
1375         mlx5_wq_ll_pop(wq, cqe->wqe_id, &wqe->next.next_wqe_index);
1376 }
1377
1378 const struct mlx5e_rx_handlers mlx5e_rx_handlers_rep = {
1379         .handle_rx_cqe       = mlx5e_handle_rx_cqe_rep,
1380         .handle_rx_cqe_mpwqe = mlx5e_handle_rx_cqe_mpwrq_rep,
1381 };
1382 #endif
1383
1384 static struct sk_buff *
1385 mlx5e_skb_from_cqe_mpwrq_nonlinear(struct mlx5e_rq *rq, struct mlx5e_mpw_info *wi,
1386                                    u16 cqe_bcnt, u32 head_offset, u32 page_idx)
1387 {
1388         u16 headlen = min_t(u16, MLX5E_RX_MAX_HEAD, cqe_bcnt);
1389         struct mlx5e_dma_info *di = &wi->umr.dma_info[page_idx];
1390         u32 frag_offset    = head_offset + headlen;
1391         u32 byte_cnt       = cqe_bcnt - headlen;
1392         struct mlx5e_dma_info *head_di = di;
1393         struct sk_buff *skb;
1394
1395         skb = napi_alloc_skb(rq->cq.napi,
1396                              ALIGN(MLX5E_RX_MAX_HEAD, sizeof(long)));
1397         if (unlikely(!skb)) {
1398                 rq->stats->buff_alloc_err++;
1399                 return NULL;
1400         }
1401
1402         prefetchw(skb->data);
1403
1404         if (unlikely(frag_offset >= PAGE_SIZE)) {
1405                 di++;
1406                 frag_offset -= PAGE_SIZE;
1407         }
1408
1409         while (byte_cnt) {
1410                 u32 pg_consumed_bytes =
1411                         min_t(u32, PAGE_SIZE - frag_offset, byte_cnt);
1412                 unsigned int truesize =
1413                         ALIGN(pg_consumed_bytes, BIT(rq->mpwqe.log_stride_sz));
1414
1415                 mlx5e_add_skb_frag(rq, skb, di, frag_offset,
1416                                    pg_consumed_bytes, truesize);
1417                 byte_cnt -= pg_consumed_bytes;
1418                 frag_offset = 0;
1419                 di++;
1420         }
1421         /* copy header */
1422         mlx5e_copy_skb_header(rq->pdev, skb, head_di, head_offset, headlen);
1423         /* skb linear part was allocated with headlen and aligned to long */
1424         skb->tail += headlen;
1425         skb->len  += headlen;
1426
1427         return skb;
1428 }
1429
1430 static struct sk_buff *
1431 mlx5e_skb_from_cqe_mpwrq_linear(struct mlx5e_rq *rq, struct mlx5e_mpw_info *wi,
1432                                 u16 cqe_bcnt, u32 head_offset, u32 page_idx)
1433 {
1434         struct mlx5e_dma_info *di = &wi->umr.dma_info[page_idx];
1435         u16 rx_headroom = rq->buff.headroom;
1436         u32 cqe_bcnt32 = cqe_bcnt;
1437         struct xdp_buff xdp;
1438         struct sk_buff *skb;
1439         void *va, *data;
1440         u32 frag_size;
1441         bool consumed;
1442
1443         /* Check packet size. Note LRO doesn't use linear SKB */
1444         if (unlikely(cqe_bcnt > rq->hw_mtu)) {
1445                 rq->stats->oversize_pkts_sw_drop++;
1446                 return NULL;
1447         }
1448
1449         va             = page_address(di->page) + head_offset;
1450         data           = va + rx_headroom;
1451         frag_size      = MLX5_SKB_FRAG_SZ(rx_headroom + cqe_bcnt32);
1452
1453         dma_sync_single_range_for_cpu(rq->pdev, di->addr, head_offset,
1454                                       frag_size, DMA_FROM_DEVICE);
1455         prefetchw(va); /* xdp_frame data area */
1456         prefetch(data);
1457
1458         rcu_read_lock();
1459         mlx5e_fill_xdp_buff(rq, va, rx_headroom, cqe_bcnt32, &xdp);
1460         consumed = mlx5e_xdp_handle(rq, di, &cqe_bcnt32, &xdp);
1461         rcu_read_unlock();
1462         if (consumed) {
1463                 if (__test_and_clear_bit(MLX5E_RQ_FLAG_XDP_XMIT, rq->flags))
1464                         __set_bit(page_idx, wi->xdp_xmit_bitmap); /* non-atomic */
1465                 return NULL; /* page/packet was consumed by XDP */
1466         }
1467
1468         rx_headroom = xdp.data - xdp.data_hard_start;
1469         frag_size = MLX5_SKB_FRAG_SZ(rx_headroom + cqe_bcnt32);
1470         skb = mlx5e_build_linear_skb(rq, va, frag_size, rx_headroom, cqe_bcnt32);
1471         if (unlikely(!skb))
1472                 return NULL;
1473
1474         /* queue up for recycling/reuse */
1475         page_ref_inc(di->page);
1476
1477         return skb;
1478 }
1479
1480 static void mlx5e_handle_rx_cqe_mpwrq(struct mlx5e_rq *rq, struct mlx5_cqe64 *cqe)
1481 {
1482         u16 cstrides       = mpwrq_get_cqe_consumed_strides(cqe);
1483         u16 wqe_id         = be16_to_cpu(cqe->wqe_id);
1484         struct mlx5e_mpw_info *wi = &rq->mpwqe.info[wqe_id];
1485         u16 stride_ix      = mpwrq_get_cqe_stride_index(cqe);
1486         u32 wqe_offset     = stride_ix << rq->mpwqe.log_stride_sz;
1487         u32 head_offset    = wqe_offset & (PAGE_SIZE - 1);
1488         u32 page_idx       = wqe_offset >> PAGE_SHIFT;
1489         struct mlx5e_rx_wqe_ll *wqe;
1490         struct mlx5_wq_ll *wq;
1491         struct sk_buff *skb;
1492         u16 cqe_bcnt;
1493
1494         wi->consumed_strides += cstrides;
1495
1496         if (unlikely(MLX5E_RX_ERR_CQE(cqe))) {
1497                 trigger_report(rq, cqe);
1498                 rq->stats->wqe_err++;
1499                 goto mpwrq_cqe_out;
1500         }
1501
1502         if (unlikely(mpwrq_is_filler_cqe(cqe))) {
1503                 struct mlx5e_rq_stats *stats = rq->stats;
1504
1505                 stats->mpwqe_filler_cqes++;
1506                 stats->mpwqe_filler_strides += cstrides;
1507                 goto mpwrq_cqe_out;
1508         }
1509
1510         cqe_bcnt = mpwrq_get_cqe_byte_cnt(cqe);
1511
1512         skb = INDIRECT_CALL_2(rq->mpwqe.skb_from_cqe_mpwrq,
1513                               mlx5e_skb_from_cqe_mpwrq_linear,
1514                               mlx5e_skb_from_cqe_mpwrq_nonlinear,
1515                               rq, wi, cqe_bcnt, head_offset, page_idx);
1516         if (!skb)
1517                 goto mpwrq_cqe_out;
1518
1519         mlx5e_complete_rx_cqe(rq, cqe, cqe_bcnt, skb);
1520         napi_gro_receive(rq->cq.napi, skb);
1521
1522 mpwrq_cqe_out:
1523         if (likely(wi->consumed_strides < rq->mpwqe.num_strides))
1524                 return;
1525
1526         wq  = &rq->mpwqe.wq;
1527         wqe = mlx5_wq_ll_get_wqe(wq, wqe_id);
1528         mlx5e_free_rx_mpwqe(rq, wi, true);
1529         mlx5_wq_ll_pop(wq, cqe->wqe_id, &wqe->next.next_wqe_index);
1530 }
1531
1532 int mlx5e_poll_rx_cq(struct mlx5e_cq *cq, int budget)
1533 {
1534         struct mlx5e_rq *rq = container_of(cq, struct mlx5e_rq, cq);
1535         struct mlx5_cqwq *cqwq = &cq->wq;
1536         struct mlx5_cqe64 *cqe;
1537         int work_done = 0;
1538
1539         if (unlikely(!test_bit(MLX5E_RQ_STATE_ENABLED, &rq->state)))
1540                 return 0;
1541
1542         if (rq->page_pool)
1543                 page_pool_nid_changed(rq->page_pool, numa_mem_id());
1544
1545         if (rq->cqd.left) {
1546                 work_done += mlx5e_decompress_cqes_cont(rq, cqwq, 0, budget);
1547                 if (rq->cqd.left || work_done >= budget)
1548                         goto out;
1549         }
1550
1551         cqe = mlx5_cqwq_get_cqe(cqwq);
1552         if (!cqe) {
1553                 if (unlikely(work_done))
1554                         goto out;
1555                 return 0;
1556         }
1557
1558         do {
1559                 if (mlx5_get_cqe_format(cqe) == MLX5_COMPRESSED) {
1560                         work_done +=
1561                                 mlx5e_decompress_cqes_start(rq, cqwq,
1562                                                             budget - work_done);
1563                         continue;
1564                 }
1565
1566                 mlx5_cqwq_pop(cqwq);
1567
1568                 INDIRECT_CALL_2(rq->handle_rx_cqe, mlx5e_handle_rx_cqe_mpwrq,
1569                                 mlx5e_handle_rx_cqe, rq, cqe);
1570         } while ((++work_done < budget) && (cqe = mlx5_cqwq_get_cqe(cqwq)));
1571
1572 out:
1573         if (rq->xdp_prog)
1574                 mlx5e_xdp_rx_poll_complete(rq);
1575
1576         mlx5_cqwq_update_db_record(cqwq);
1577
1578         /* ensure cq space is freed before enabling more cqes */
1579         wmb();
1580
1581         return work_done;
1582 }
1583
1584 #ifdef CONFIG_MLX5_CORE_IPOIB
1585
1586 #define MLX5_IB_GRH_SGID_OFFSET 8
1587 #define MLX5_IB_GRH_DGID_OFFSET 24
1588 #define MLX5_GID_SIZE           16
1589
1590 static inline void mlx5i_complete_rx_cqe(struct mlx5e_rq *rq,
1591                                          struct mlx5_cqe64 *cqe,
1592                                          u32 cqe_bcnt,
1593                                          struct sk_buff *skb)
1594 {
1595         struct hwtstamp_config *tstamp;
1596         struct mlx5e_rq_stats *stats;
1597         struct net_device *netdev;
1598         struct mlx5e_priv *priv;
1599         char *pseudo_header;
1600         u32 flags_rqpn;
1601         u32 qpn;
1602         u8 *dgid;
1603         u8 g;
1604
1605         qpn = be32_to_cpu(cqe->sop_drop_qpn) & 0xffffff;
1606         netdev = mlx5i_pkey_get_netdev(rq->netdev, qpn);
1607
1608         /* No mapping present, cannot process SKB. This might happen if a child
1609          * interface is going down while having unprocessed CQEs on parent RQ
1610          */
1611         if (unlikely(!netdev)) {
1612                 /* TODO: add drop counters support */
1613                 skb->dev = NULL;
1614                 pr_warn_once("Unable to map QPN %u to dev - dropping skb\n", qpn);
1615                 return;
1616         }
1617
1618         priv = mlx5i_epriv(netdev);
1619         tstamp = &priv->tstamp;
1620         stats = &priv->channel_stats[rq->ix].rq;
1621
1622         flags_rqpn = be32_to_cpu(cqe->flags_rqpn);
1623         g = (flags_rqpn >> 28) & 3;
1624         dgid = skb->data + MLX5_IB_GRH_DGID_OFFSET;
1625         if ((!g) || dgid[0] != 0xff)
1626                 skb->pkt_type = PACKET_HOST;
1627         else if (memcmp(dgid, netdev->broadcast + 4, MLX5_GID_SIZE) == 0)
1628                 skb->pkt_type = PACKET_BROADCAST;
1629         else
1630                 skb->pkt_type = PACKET_MULTICAST;
1631
1632         /* Drop packets that this interface sent, ie multicast packets
1633          * that the HCA has replicated.
1634          */
1635         if (g && (qpn == (flags_rqpn & 0xffffff)) &&
1636             (memcmp(netdev->dev_addr + 4, skb->data + MLX5_IB_GRH_SGID_OFFSET,
1637                     MLX5_GID_SIZE) == 0)) {
1638                 skb->dev = NULL;
1639                 return;
1640         }
1641
1642         skb_pull(skb, MLX5_IB_GRH_BYTES);
1643
1644         skb->protocol = *((__be16 *)(skb->data));
1645
1646         if (netdev->features & NETIF_F_RXCSUM) {
1647                 skb->ip_summed = CHECKSUM_COMPLETE;
1648                 skb->csum = csum_unfold((__force __sum16)cqe->check_sum);
1649                 stats->csum_complete++;
1650         } else {
1651                 skb->ip_summed = CHECKSUM_NONE;
1652                 stats->csum_none++;
1653         }
1654
1655         if (unlikely(mlx5e_rx_hw_stamp(tstamp)))
1656                 skb_hwtstamps(skb)->hwtstamp =
1657                                 mlx5_timecounter_cyc2time(rq->clock, get_cqe_ts(cqe));
1658
1659         skb_record_rx_queue(skb, rq->ix);
1660
1661         if (likely(netdev->features & NETIF_F_RXHASH))
1662                 mlx5e_skb_set_hash(cqe, skb);
1663
1664         /* 20 bytes of ipoib header and 4 for encap existing */
1665         pseudo_header = skb_push(skb, MLX5_IPOIB_PSEUDO_LEN);
1666         memset(pseudo_header, 0, MLX5_IPOIB_PSEUDO_LEN);
1667         skb_reset_mac_header(skb);
1668         skb_pull(skb, MLX5_IPOIB_HARD_LEN);
1669
1670         skb->dev = netdev;
1671
1672         stats->packets++;
1673         stats->bytes += cqe_bcnt;
1674 }
1675
1676 static void mlx5i_handle_rx_cqe(struct mlx5e_rq *rq, struct mlx5_cqe64 *cqe)
1677 {
1678         struct mlx5_wq_cyc *wq = &rq->wqe.wq;
1679         struct mlx5e_wqe_frag_info *wi;
1680         struct sk_buff *skb;
1681         u32 cqe_bcnt;
1682         u16 ci;
1683
1684         ci       = mlx5_wq_cyc_ctr2ix(wq, be16_to_cpu(cqe->wqe_counter));
1685         wi       = get_frag(rq, ci);
1686         cqe_bcnt = be32_to_cpu(cqe->byte_cnt);
1687
1688         if (unlikely(MLX5E_RX_ERR_CQE(cqe))) {
1689                 rq->stats->wqe_err++;
1690                 goto wq_free_wqe;
1691         }
1692
1693         skb = INDIRECT_CALL_2(rq->wqe.skb_from_cqe,
1694                               mlx5e_skb_from_cqe_linear,
1695                               mlx5e_skb_from_cqe_nonlinear,
1696                               rq, cqe, wi, cqe_bcnt);
1697         if (!skb)
1698                 goto wq_free_wqe;
1699
1700         mlx5i_complete_rx_cqe(rq, cqe, cqe_bcnt, skb);
1701         if (unlikely(!skb->dev)) {
1702                 dev_kfree_skb_any(skb);
1703                 goto wq_free_wqe;
1704         }
1705         napi_gro_receive(rq->cq.napi, skb);
1706
1707 wq_free_wqe:
1708         mlx5e_free_rx_wqe(rq, wi, true);
1709         mlx5_wq_cyc_pop(wq);
1710 }
1711
1712 const struct mlx5e_rx_handlers mlx5i_rx_handlers = {
1713         .handle_rx_cqe       = mlx5i_handle_rx_cqe,
1714         .handle_rx_cqe_mpwqe = NULL, /* Not supported */
1715 };
1716 #endif /* CONFIG_MLX5_CORE_IPOIB */
1717
1718 #ifdef CONFIG_MLX5_EN_IPSEC
1719
1720 static void mlx5e_ipsec_handle_rx_cqe(struct mlx5e_rq *rq, struct mlx5_cqe64 *cqe)
1721 {
1722         struct mlx5_wq_cyc *wq = &rq->wqe.wq;
1723         struct mlx5e_wqe_frag_info *wi;
1724         struct sk_buff *skb;
1725         u32 cqe_bcnt;
1726         u16 ci;
1727
1728         ci       = mlx5_wq_cyc_ctr2ix(wq, be16_to_cpu(cqe->wqe_counter));
1729         wi       = get_frag(rq, ci);
1730         cqe_bcnt = be32_to_cpu(cqe->byte_cnt);
1731
1732         if (unlikely(MLX5E_RX_ERR_CQE(cqe))) {
1733                 rq->stats->wqe_err++;
1734                 goto wq_free_wqe;
1735         }
1736
1737         skb = INDIRECT_CALL_2(rq->wqe.skb_from_cqe,
1738                               mlx5e_skb_from_cqe_linear,
1739                               mlx5e_skb_from_cqe_nonlinear,
1740                               rq, cqe, wi, cqe_bcnt);
1741         if (unlikely(!skb)) /* a DROP, save the page-reuse checks */
1742                 goto wq_free_wqe;
1743
1744         skb = mlx5e_ipsec_handle_rx_skb(rq->netdev, skb, &cqe_bcnt);
1745         if (unlikely(!skb))
1746                 goto wq_free_wqe;
1747
1748         mlx5e_complete_rx_cqe(rq, cqe, cqe_bcnt, skb);
1749         napi_gro_receive(rq->cq.napi, skb);
1750
1751 wq_free_wqe:
1752         mlx5e_free_rx_wqe(rq, wi, true);
1753         mlx5_wq_cyc_pop(wq);
1754 }
1755
1756 #endif /* CONFIG_MLX5_EN_IPSEC */
1757
1758 int mlx5e_rq_set_handlers(struct mlx5e_rq *rq, struct mlx5e_params *params, bool xsk)
1759 {
1760         struct mlx5_core_dev *mdev = rq->mdev;
1761         struct mlx5e_channel *c = rq->channel;
1762
1763         switch (rq->wq_type) {
1764         case MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ:
1765                 rq->mpwqe.skb_from_cqe_mpwrq = xsk ?
1766                         mlx5e_xsk_skb_from_cqe_mpwrq_linear :
1767                         mlx5e_rx_mpwqe_is_linear_skb(mdev, params, NULL) ?
1768                                 mlx5e_skb_from_cqe_mpwrq_linear :
1769                                 mlx5e_skb_from_cqe_mpwrq_nonlinear;
1770                 rq->post_wqes = mlx5e_post_rx_mpwqes;
1771                 rq->dealloc_wqe = mlx5e_dealloc_rx_mpwqe;
1772
1773                 rq->handle_rx_cqe = c->priv->profile->rx_handlers->handle_rx_cqe_mpwqe;
1774 #ifdef CONFIG_MLX5_EN_IPSEC
1775                 if (MLX5_IPSEC_DEV(mdev)) {
1776                         netdev_err(c->netdev, "MPWQE RQ with IPSec offload not supported\n");
1777                         return -EINVAL;
1778                 }
1779 #endif
1780                 if (!rq->handle_rx_cqe) {
1781                         netdev_err(c->netdev, "RX handler of MPWQE RQ is not set\n");
1782                         return -EINVAL;
1783                 }
1784                 break;
1785         default: /* MLX5_WQ_TYPE_CYCLIC */
1786                 rq->wqe.skb_from_cqe = xsk ?
1787                         mlx5e_xsk_skb_from_cqe_linear :
1788                         mlx5e_rx_is_linear_skb(params, NULL) ?
1789                                 mlx5e_skb_from_cqe_linear :
1790                                 mlx5e_skb_from_cqe_nonlinear;
1791                 rq->post_wqes = mlx5e_post_rx_wqes;
1792                 rq->dealloc_wqe = mlx5e_dealloc_rx_wqe;
1793
1794 #ifdef CONFIG_MLX5_EN_IPSEC
1795                 if ((mlx5_fpga_ipsec_device_caps(mdev) & MLX5_ACCEL_IPSEC_CAP_DEVICE) &&
1796                     c->priv->ipsec)
1797                         rq->handle_rx_cqe = mlx5e_ipsec_handle_rx_cqe;
1798                 else
1799 #endif
1800                         rq->handle_rx_cqe = c->priv->profile->rx_handlers->handle_rx_cqe;
1801                 if (!rq->handle_rx_cqe) {
1802                         netdev_err(c->netdev, "RX handler of RQ is not set\n");
1803                         return -EINVAL;
1804                 }
1805         }
1806
1807         return 0;
1808 }