drivers/net/ethernet/mellanox/mlx5/core/en_main.c

   1 /*
   2  * Copyright (c) 2015-2016, Mellanox Technologies. All rights reserved.
   3  *
   4  * This software is available to you under a choice of one of two
   5  * licenses.  You may choose to be licensed under the terms of the GNU
   6  * General Public License (GPL) Version 2, available from the file
   7  * COPYING in the main directory of this source tree, or the
   8  * OpenIB.org BSD license below:
   9  *
  10  *     Redistribution and use in source and binary forms, with or
  11  *     without modification, are permitted provided that the following
  12  *     conditions are met:
  13  *
  14  *      - Redistributions of source code must retain the above
  15  *        copyright notice, this list of conditions and the following
  16  *        disclaimer.
  17  *
  18  *      - Redistributions in binary form must reproduce the above
  19  *        copyright notice, this list of conditions and the following
  20  *        disclaimer in the documentation and/or other materials
  21  *        provided with the distribution.
  22  *
  23  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  24  * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  25  * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
  26  * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
  27  * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
  28  * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
  29  * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
  30  * SOFTWARE.
  31  */
  32
  33 #include <net/tc_act/tc_gact.h>
  34 #include <net/pkt_cls.h>
  35 #include <linux/mlx5/fs.h>
  36 #include <net/vxlan.h>
  37 #include <net/geneve.h>
  38 #include <linux/bpf.h>
  39 #include <linux/if_bridge.h>
  40 #include <net/page_pool.h>
  41 #include <net/xdp_sock_drv.h>
  42 #include "eswitch.h"
  43 #include "en.h"
  44 #include "en/txrx.h"
  45 #include "en_tc.h"
  46 #include "en_rep.h"
  47 #include "en_accel/ipsec.h"
  48 #include "en_accel/ipsec_rxtx.h"
  49 #include "en_accel/en_accel.h"
  50 #include "en_accel/tls.h"
  51 #include "accel/ipsec.h"
  52 #include "accel/tls.h"
  53 #include "lib/vxlan.h"
  54 #include "lib/clock.h"
  55 #include "en/port.h"
  56 #include "en/xdp.h"
  57 #include "lib/eq.h"
  58 #include "en/monitor_stats.h"
  59 #include "en/health.h"
  60 #include "en/params.h"
  61 #include "en/xsk/umem.h"
  62 #include "en/xsk/setup.h"
  63 #include "en/xsk/rx.h"
  64 #include "en/xsk/tx.h"
  65 #include "en/hv_vhca_stats.h"
  66 #include "en/devlink.h"
  67 #include "lib/mlx5.h"
  68
  69 bool mlx5e_check_fragmented_striding_rq_cap(struct mlx5_core_dev *mdev)
  70 {
  71         bool striding_rq_umr = MLX5_CAP_GEN(mdev, striding_rq) &&
  72                 MLX5_CAP_GEN(mdev, umr_ptr_rlky) &&
  73                 MLX5_CAP_ETH(mdev, reg_umr_sq);
  74         u16 max_wqe_sz_cap = MLX5_CAP_GEN(mdev, max_wqe_sz_sq);
  75         bool inline_umr = MLX5E_UMR_WQE_INLINE_SZ <= max_wqe_sz_cap;
  76
  77         if (!striding_rq_umr)
  78                 return false;
  79         if (!inline_umr) {
  80                 mlx5_core_warn(mdev, "Cannot support Striding RQ: UMR WQE size (%d) exceeds maximum supported (%d).\n",
  81                                (int)MLX5E_UMR_WQE_INLINE_SZ, max_wqe_sz_cap);
  82                 return false;
  83         }
  84         return true;
  85 }
  86
  87 void mlx5e_init_rq_type_params(struct mlx5_core_dev *mdev,
  88                                struct mlx5e_params *params)
  89 {
  90         params->log_rq_mtu_frames = is_kdump_kernel() ?
  91                 MLX5E_PARAMS_MINIMUM_LOG_RQ_SIZE :
  92                 MLX5E_PARAMS_DEFAULT_LOG_RQ_SIZE;
  93
  94         mlx5_core_info(mdev, "MLX5E: StrdRq(%d) RqSz(%ld) StrdSz(%ld) RxCqeCmprss(%d)\n",
  95                        params->rq_wq_type == MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ,
  96                        params->rq_wq_type == MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ ?
  97                        BIT(mlx5e_mpwqe_get_log_rq_size(params, NULL)) :
  98                        BIT(params->log_rq_mtu_frames),
  99                        BIT(mlx5e_mpwqe_get_log_stride_size(mdev, params, NULL)),
 100                        MLX5E_GET_PFLAG(params, MLX5E_PFLAG_RX_CQE_COMPRESS));
 101 }
 102
 103 bool mlx5e_striding_rq_possible(struct mlx5_core_dev *mdev,
 104                                 struct mlx5e_params *params)
 105 {
 106         if (!mlx5e_check_fragmented_striding_rq_cap(mdev))
 107                 return false;
 108
 109         if (MLX5_IPSEC_DEV(mdev))
 110                 return false;
 111
 112         if (params->xdp_prog) {
 113                 /* XSK params are not considered here. If striding RQ is in use,
 114                  * and an XSK is being opened, mlx5e_rx_mpwqe_is_linear_skb will
 115                  * be called with the known XSK params.
 116                  */
 117                 if (!mlx5e_rx_mpwqe_is_linear_skb(mdev, params, NULL))
 118                         return false;
 119         }
 120
 121         return true;
 122 }
 123
 124 void mlx5e_set_rq_type(struct mlx5_core_dev *mdev, struct mlx5e_params *params)
 125 {
 126         params->rq_wq_type = mlx5e_striding_rq_possible(mdev, params) &&
 127                 MLX5E_GET_PFLAG(params, MLX5E_PFLAG_RX_STRIDING_RQ) ?
 128                 MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ :
 129                 MLX5_WQ_TYPE_CYCLIC;
 130 }
 131
 132 void mlx5e_update_carrier(struct mlx5e_priv *priv)
 133 {
 134         struct mlx5_core_dev *mdev = priv->mdev;
 135         u8 port_state;
 136
 137         port_state = mlx5_query_vport_state(mdev,
 138                                             MLX5_VPORT_STATE_OP_MOD_VNIC_VPORT,
 139                                             0);
 140
 141         if (port_state == VPORT_STATE_UP) {
 142                 netdev_info(priv->netdev, "Link up\n");
 143                 netif_carrier_on(priv->netdev);
 144         } else {
 145                 netdev_info(priv->netdev, "Link down\n");
 146                 netif_carrier_off(priv->netdev);
 147         }
 148 }
 149
 150 static void mlx5e_update_carrier_work(struct work_struct *work)
 151 {
 152         struct mlx5e_priv *priv = container_of(work, struct mlx5e_priv,
 153                                                update_carrier_work);
 154
 155         mutex_lock(&priv->state_lock);
 156         if (test_bit(MLX5E_STATE_OPENED, &priv->state))
 157                 if (priv->profile->update_carrier)
 158                         priv->profile->update_carrier(priv);
 159         mutex_unlock(&priv->state_lock);
 160 }
 161
 162 void mlx5e_update_ndo_stats(struct mlx5e_priv *priv)
 163 {
 164         int i;
 165
 166         for (i = mlx5e_nic_stats_grps_num(priv) - 1; i >= 0; i--)
 167                 if (mlx5e_nic_stats_grps[i]->update_stats_mask &
 168                     MLX5E_NDO_UPDATE_STATS)
 169                         mlx5e_nic_stats_grps[i]->update_stats(priv);
 170 }
 171
 172 static void mlx5e_update_stats_work(struct work_struct *work)
 173 {
 174         struct mlx5e_priv *priv = container_of(work, struct mlx5e_priv,
 175                                                update_stats_work);
 176
 177         mutex_lock(&priv->state_lock);
 178         priv->profile->update_stats(priv);
 179         mutex_unlock(&priv->state_lock);
 180 }
 181
 182 void mlx5e_queue_update_stats(struct mlx5e_priv *priv)
 183 {
 184         if (!priv->profile->update_stats)
 185                 return;
 186
 187         if (unlikely(test_bit(MLX5E_STATE_DESTROYING, &priv->state)))
 188                 return;
 189
 190         queue_work(priv->wq, &priv->update_stats_work);
 191 }
 192
 193 static int async_event(struct notifier_block *nb, unsigned long event, void *data)
 194 {
 195         struct mlx5e_priv *priv = container_of(nb, struct mlx5e_priv, events_nb);
 196         struct mlx5_eqe   *eqe = data;
 197
 198         if (event != MLX5_EVENT_TYPE_PORT_CHANGE)
 199                 return NOTIFY_DONE;
 200
 201         switch (eqe->sub_type) {
 202         case MLX5_PORT_CHANGE_SUBTYPE_DOWN:
 203         case MLX5_PORT_CHANGE_SUBTYPE_ACTIVE:
 204                 queue_work(priv->wq, &priv->update_carrier_work);
 205                 break;
 206         default:
 207                 return NOTIFY_DONE;
 208         }
 209
 210         return NOTIFY_OK;
 211 }
 212
 213 static void mlx5e_enable_async_events(struct mlx5e_priv *priv)
 214 {
 215         priv->events_nb.notifier_call = async_event;
 216         mlx5_notifier_register(priv->mdev, &priv->events_nb);
 217 }
 218
 219 static void mlx5e_disable_async_events(struct mlx5e_priv *priv)
 220 {
 221         mlx5_notifier_unregister(priv->mdev, &priv->events_nb);
 222 }
 223
 224 static inline void mlx5e_build_umr_wqe(struct mlx5e_rq *rq,
 225                                        struct mlx5e_icosq *sq,
 226                                        struct mlx5e_umr_wqe *wqe)
 227 {
 228         struct mlx5_wqe_ctrl_seg      *cseg = &wqe->ctrl;
 229         struct mlx5_wqe_umr_ctrl_seg *ucseg = &wqe->uctrl;
 230         u8 ds_cnt = DIV_ROUND_UP(MLX5E_UMR_WQE_INLINE_SZ, MLX5_SEND_WQE_DS);
 231
 232         cseg->qpn_ds    = cpu_to_be32((sq->sqn << MLX5_WQE_CTRL_QPN_SHIFT) |
 233                                       ds_cnt);
 234         cseg->fm_ce_se  = MLX5_WQE_CTRL_CQ_UPDATE;
 235         cseg->umr_mkey  = rq->mkey_be;
 236
 237         ucseg->flags = MLX5_UMR_TRANSLATION_OFFSET_EN | MLX5_UMR_INLINE;
 238         ucseg->xlt_octowords =
 239                 cpu_to_be16(MLX5_MTT_OCTW(MLX5_MPWRQ_PAGES_PER_WQE));
 240         ucseg->mkey_mask     = cpu_to_be64(MLX5_MKEY_MASK_FREE);
 241 }
 242
 243 static int mlx5e_rq_alloc_mpwqe_info(struct mlx5e_rq *rq,
 244                                      struct mlx5e_channel *c)
 245 {
 246         int wq_sz = mlx5_wq_ll_get_size(&rq->mpwqe.wq);
 247
 248         rq->mpwqe.info = kvzalloc_node(array_size(wq_sz,
 249                                                   sizeof(*rq->mpwqe.info)),
 250                                        GFP_KERNEL, cpu_to_node(c->cpu));
 251         if (!rq->mpwqe.info)
 252                 return -ENOMEM;
 253
 254         mlx5e_build_umr_wqe(rq, &c->icosq, &rq->mpwqe.umr_wqe);
 255
 256         return 0;
 257 }
 258
 259 static int mlx5e_create_umr_mkey(struct mlx5_core_dev *mdev,
 260                                  u64 npages, u8 page_shift,
 261                                  struct mlx5_core_mkey *umr_mkey)
 262 {
 263         int inlen = MLX5_ST_SZ_BYTES(create_mkey_in);
 264         void *mkc;
 265         u32 *in;
 266         int err;
 267
 268         in = kvzalloc(inlen, GFP_KERNEL);
 269         if (!in)
 270                 return -ENOMEM;
 271
 272         mkc = MLX5_ADDR_OF(create_mkey_in, in, memory_key_mkey_entry);
 273
 274         MLX5_SET(mkc, mkc, free, 1);
 275         MLX5_SET(mkc, mkc, umr_en, 1);
 276         MLX5_SET(mkc, mkc, lw, 1);
 277         MLX5_SET(mkc, mkc, lr, 1);
 278         MLX5_SET(mkc, mkc, access_mode_1_0, MLX5_MKC_ACCESS_MODE_MTT);
 279
 280         MLX5_SET(mkc, mkc, qpn, 0xffffff);
 281         MLX5_SET(mkc, mkc, pd, mdev->mlx5e_res.pdn);
 282         MLX5_SET64(mkc, mkc, len, npages << page_shift);
 283         MLX5_SET(mkc, mkc, translations_octword_size,
 284                  MLX5_MTT_OCTW(npages));
 285         MLX5_SET(mkc, mkc, log_page_size, page_shift);
 286
 287         err = mlx5_core_create_mkey(mdev, umr_mkey, in, inlen);
 288
 289         kvfree(in);
 290         return err;
 291 }
 292
 293 static int mlx5e_create_rq_umr_mkey(struct mlx5_core_dev *mdev, struct mlx5e_rq *rq)
 294 {
 295         u64 num_mtts = MLX5E_REQUIRED_MTTS(mlx5_wq_ll_get_size(&rq->mpwqe.wq));
 296
 297         return mlx5e_create_umr_mkey(mdev, num_mtts, PAGE_SHIFT, &rq->umr_mkey);
 298 }
 299
 300 static inline u64 mlx5e_get_mpwqe_offset(struct mlx5e_rq *rq, u16 wqe_ix)
 301 {
 302         return (wqe_ix << MLX5E_LOG_ALIGNED_MPWQE_PPW) << PAGE_SHIFT;
 303 }
 304
 305 static void mlx5e_init_frags_partition(struct mlx5e_rq *rq)
 306 {
 307         struct mlx5e_wqe_frag_info next_frag = {};
 308         struct mlx5e_wqe_frag_info *prev = NULL;
 309         int i;
 310
 311         next_frag.di = &rq->wqe.di[0];
 312
 313         for (i = 0; i < mlx5_wq_cyc_get_size(&rq->wqe.wq); i++) {
 314                 struct mlx5e_rq_frag_info *frag_info = &rq->wqe.info.arr[0];
 315                 struct mlx5e_wqe_frag_info *frag =
 316                         &rq->wqe.frags[i << rq->wqe.info.log_num_frags];
 317                 int f;
 318
 319                 for (f = 0; f < rq->wqe.info.num_frags; f++, frag++) {
 320                         if (next_frag.offset + frag_info[f].frag_stride > PAGE_SIZE) {
 321                                 next_frag.di++;
 322                                 next_frag.offset = 0;
 323                                 if (prev)
 324                                         prev->last_in_page = true;
 325                         }
 326                         *frag = next_frag;
 327
 328                         /* prepare next */
 329                         next_frag.offset += frag_info[f].frag_stride;
 330                         prev = frag;
 331                 }
 332         }
 333
 334         if (prev)
 335                 prev->last_in_page = true;
 336 }
 337
 338 static int mlx5e_init_di_list(struct mlx5e_rq *rq,
 339                               int wq_sz, int cpu)
 340 {
 341         int len = wq_sz << rq->wqe.info.log_num_frags;
 342
 343         rq->wqe.di = kvzalloc_node(array_size(len, sizeof(*rq->wqe.di)),
 344                                    GFP_KERNEL, cpu_to_node(cpu));
 345         if (!rq->wqe.di)
 346                 return -ENOMEM;
 347
 348         mlx5e_init_frags_partition(rq);
 349
 350         return 0;
 351 }
 352
 353 static void mlx5e_free_di_list(struct mlx5e_rq *rq)
 354 {
 355         kvfree(rq->wqe.di);
 356 }
 357
 358 static void mlx5e_rq_err_cqe_work(struct work_struct *recover_work)
 359 {
 360         struct mlx5e_rq *rq = container_of(recover_work, struct mlx5e_rq, recover_work);
 361
 362         mlx5e_reporter_rq_cqe_err(rq);
 363 }
 364
 365 static int mlx5e_alloc_rq(struct mlx5e_channel *c,
 366                           struct mlx5e_params *params,
 367                           struct mlx5e_xsk_param *xsk,
 368                           struct xdp_umem *umem,
 369                           struct mlx5e_rq_param *rqp,
 370                           struct mlx5e_rq *rq)
 371 {
 372         struct page_pool_params pp_params = { 0 };
 373         struct mlx5_core_dev *mdev = c->mdev;
 374         void *rqc = rqp->rqc;
 375         void *rqc_wq = MLX5_ADDR_OF(rqc, rqc, wq);
 376         u32 rq_xdp_ix;
 377         u32 pool_size;
 378         int wq_sz;
 379         int err;
 380         int i;
 381
 382         rqp->wq.db_numa_node = cpu_to_node(c->cpu);
 383
 384         rq->wq_type = params->rq_wq_type;
 385         rq->pdev    = c->pdev;
 386         rq->netdev  = c->netdev;
 387         rq->tstamp  = c->tstamp;
 388         rq->clock   = &mdev->clock;
 389         rq->channel = c;
 390         rq->ix      = c->ix;
 391         rq->mdev    = mdev;
 392         rq->hw_mtu  = MLX5E_SW2HW_MTU(params, params->sw_mtu);
 393         rq->xdpsq   = &c->rq_xdpsq;
 394         rq->umem    = umem;
 395
 396         if (rq->umem)
 397                 rq->stats = &c->priv->channel_stats[c->ix].xskrq;
 398         else
 399                 rq->stats = &c->priv->channel_stats[c->ix].rq;
 400         INIT_WORK(&rq->recover_work, mlx5e_rq_err_cqe_work);
 401
 402         if (params->xdp_prog)
 403                 bpf_prog_inc(params->xdp_prog);
 404         rq->xdp_prog = params->xdp_prog;
 405
 406         rq_xdp_ix = rq->ix;
 407         if (xsk)
 408                 rq_xdp_ix += params->num_channels * MLX5E_RQ_GROUP_XSK;
 409         err = xdp_rxq_info_reg(&rq->xdp_rxq, rq->netdev, rq_xdp_ix);
 410         if (err < 0)
 411                 goto err_rq_wq_destroy;
 412
 413         rq->buff.map_dir = rq->xdp_prog ? DMA_BIDIRECTIONAL : DMA_FROM_DEVICE;
 414         rq->buff.headroom = mlx5e_get_rq_headroom(mdev, params, xsk);
 415         pool_size = 1 << params->log_rq_mtu_frames;
 416
 417         switch (rq->wq_type) {
 418         case MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ:
 419                 err = mlx5_wq_ll_create(mdev, &rqp->wq, rqc_wq, &rq->mpwqe.wq,
 420                                         &rq->wq_ctrl);
 421                 if (err)
 422                         return err;
 423
 424                 rq->mpwqe.wq.db = &rq->mpwqe.wq.db[MLX5_RCV_DBR];
 425
 426                 wq_sz = mlx5_wq_ll_get_size(&rq->mpwqe.wq);
 427
 428                 pool_size = MLX5_MPWRQ_PAGES_PER_WQE <<
 429                         mlx5e_mpwqe_get_log_rq_size(params, xsk);
 430
 431                 rq->post_wqes = mlx5e_post_rx_mpwqes;
 432                 rq->dealloc_wqe = mlx5e_dealloc_rx_mpwqe;
 433
 434                 rq->handle_rx_cqe = c->priv->profile->rx_handlers.handle_rx_cqe_mpwqe;
 435 #ifdef CONFIG_MLX5_EN_IPSEC
 436                 if (MLX5_IPSEC_DEV(mdev)) {
 437                         err = -EINVAL;
 438                         netdev_err(c->netdev, "MPWQE RQ with IPSec offload not supported\n");
 439                         goto err_rq_wq_destroy;
 440                 }
 441 #endif
 442                 if (!rq->handle_rx_cqe) {
 443                         err = -EINVAL;
 444                         netdev_err(c->netdev, "RX handler of MPWQE RQ is not set, err %d\n", err);
 445                         goto err_rq_wq_destroy;
 446                 }
 447
 448                 rq->mpwqe.skb_from_cqe_mpwrq = xsk ?
 449                         mlx5e_xsk_skb_from_cqe_mpwrq_linear :
 450                         mlx5e_rx_mpwqe_is_linear_skb(mdev, params, NULL) ?
 451                                 mlx5e_skb_from_cqe_mpwrq_linear :
 452                                 mlx5e_skb_from_cqe_mpwrq_nonlinear;
 453
 454                 rq->mpwqe.log_stride_sz = mlx5e_mpwqe_get_log_stride_size(mdev, params, xsk);
 455                 rq->mpwqe.num_strides =
 456                         BIT(mlx5e_mpwqe_get_log_num_strides(mdev, params, xsk));
 457
 458                 rq->buff.frame0_sz = (1 << rq->mpwqe.log_stride_sz);
 459
 460                 err = mlx5e_create_rq_umr_mkey(mdev, rq);
 461                 if (err)
 462                         goto err_rq_wq_destroy;
 463                 rq->mkey_be = cpu_to_be32(rq->umr_mkey.key);
 464
 465                 err = mlx5e_rq_alloc_mpwqe_info(rq, c);
 466                 if (err)
 467                         goto err_free;
 468                 break;
 469         default: /* MLX5_WQ_TYPE_CYCLIC */
 470                 err = mlx5_wq_cyc_create(mdev, &rqp->wq, rqc_wq, &rq->wqe.wq,
 471                                          &rq->wq_ctrl);
 472                 if (err)
 473                         return err;
 474
 475                 rq->wqe.wq.db = &rq->wqe.wq.db[MLX5_RCV_DBR];
 476
 477                 wq_sz = mlx5_wq_cyc_get_size(&rq->wqe.wq);
 478
 479                 rq->wqe.info = rqp->frags_info;
 480                 rq->buff.frame0_sz = rq->wqe.info.arr[0].frag_stride;
 481
 482                 rq->wqe.frags =
 483                         kvzalloc_node(array_size(sizeof(*rq->wqe.frags),
 484                                         (wq_sz << rq->wqe.info.log_num_frags)),
 485                                       GFP_KERNEL, cpu_to_node(c->cpu));
 486                 if (!rq->wqe.frags) {
 487                         err = -ENOMEM;
 488                         goto err_free;
 489                 }
 490
 491                 err = mlx5e_init_di_list(rq, wq_sz, c->cpu);
 492                 if (err)
 493                         goto err_free;
 494
 495                 rq->post_wqes = mlx5e_post_rx_wqes;
 496                 rq->dealloc_wqe = mlx5e_dealloc_rx_wqe;
 497
 498 #ifdef CONFIG_MLX5_EN_IPSEC
 499                 if (c->priv->ipsec)
 500                         rq->handle_rx_cqe = mlx5e_ipsec_handle_rx_cqe;
 501                 else
 502 #endif
 503                         rq->handle_rx_cqe = c->priv->profile->rx_handlers.handle_rx_cqe;
 504                 if (!rq->handle_rx_cqe) {
 505                         err = -EINVAL;
 506                         netdev_err(c->netdev, "RX handler of RQ is not set, err %d\n", err);
 507                         goto err_free;
 508                 }
 509
 510                 rq->wqe.skb_from_cqe = xsk ?
 511                         mlx5e_xsk_skb_from_cqe_linear :
 512                         mlx5e_rx_is_linear_skb(params, NULL) ?
 513                                 mlx5e_skb_from_cqe_linear :
 514                                 mlx5e_skb_from_cqe_nonlinear;
 515                 rq->mkey_be = c->mkey_be;
 516         }
 517
 518         if (xsk) {
 519                 err = xdp_rxq_info_reg_mem_model(&rq->xdp_rxq,
 520                                                  MEM_TYPE_XSK_BUFF_POOL, NULL);
 521                 xsk_buff_set_rxq_info(rq->umem, &rq->xdp_rxq);
 522         } else {
 523                 /* Create a page_pool and register it with rxq */
 524                 pp_params.order     = 0;
 525                 pp_params.flags     = 0; /* No-internal DMA mapping in page_pool */
 526                 pp_params.pool_size = pool_size;
 527                 pp_params.nid       = cpu_to_node(c->cpu);
 528                 pp_params.dev       = c->pdev;
 529                 pp_params.dma_dir   = rq->buff.map_dir;
 530
 531                 /* page_pool can be used even when there is no rq->xdp_prog,
 532                  * given page_pool does not handle DMA mapping there is no
 533                  * required state to clear. And page_pool gracefully handle
 534                  * elevated refcnt.
 535                  */
 536                 rq->page_pool = page_pool_create(&pp_params);
 537                 if (IS_ERR(rq->page_pool)) {
 538                         err = PTR_ERR(rq->page_pool);
 539                         rq->page_pool = NULL;
 540                         goto err_free;
 541                 }
 542                 err = xdp_rxq_info_reg_mem_model(&rq->xdp_rxq,
 543                                                  MEM_TYPE_PAGE_POOL, rq->page_pool);
 544         }
 545         if (err)
 546                 goto err_free;
 547
 548         for (i = 0; i < wq_sz; i++) {
 549                 if (rq->wq_type == MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ) {
 550                         struct mlx5e_rx_wqe_ll *wqe =
 551                                 mlx5_wq_ll_get_wqe(&rq->mpwqe.wq, i);
 552                         u32 byte_count =
 553                                 rq->mpwqe.num_strides << rq->mpwqe.log_stride_sz;
 554                         u64 dma_offset = mlx5e_get_mpwqe_offset(rq, i);
 555
 556                         wqe->data[0].addr = cpu_to_be64(dma_offset + rq->buff.headroom);
 557                         wqe->data[0].byte_count = cpu_to_be32(byte_count);
 558                         wqe->data[0].lkey = rq->mkey_be;
 559                 } else {
 560                         struct mlx5e_rx_wqe_cyc *wqe =
 561                                 mlx5_wq_cyc_get_wqe(&rq->wqe.wq, i);
 562                         int f;
 563
 564                         for (f = 0; f < rq->wqe.info.num_frags; f++) {
 565                                 u32 frag_size = rq->wqe.info.arr[f].frag_size |
 566                                         MLX5_HW_START_PADDING;
 567
 568                                 wqe->data[f].byte_count = cpu_to_be32(frag_size);
 569                                 wqe->data[f].lkey = rq->mkey_be;
 570                         }
 571                         /* check if num_frags is not a pow of two */
 572                         if (rq->wqe.info.num_frags < (1 << rq->wqe.info.log_num_frags)) {
 573                                 wqe->data[f].byte_count = 0;
 574                                 wqe->data[f].lkey = cpu_to_be32(MLX5_INVALID_LKEY);
 575                                 wqe->data[f].addr = 0;
 576                         }
 577                 }
 578         }
 579
 580         INIT_WORK(&rq->dim.work, mlx5e_rx_dim_work);
 581
 582         switch (params->rx_cq_moderation.cq_period_mode) {
 583         case MLX5_CQ_PERIOD_MODE_START_FROM_CQE:
 584                 rq->dim.mode = DIM_CQ_PERIOD_MODE_START_FROM_CQE;
 585                 break;
 586         case MLX5_CQ_PERIOD_MODE_START_FROM_EQE:
 587         default:
 588                 rq->dim.mode = DIM_CQ_PERIOD_MODE_START_FROM_EQE;
 589         }
 590
 591         rq->page_cache.head = 0;
 592         rq->page_cache.tail = 0;
 593
 594         return 0;
 595
 596 err_free:
 597         switch (rq->wq_type) {
 598         case MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ:
 599                 kvfree(rq->mpwqe.info);
 600                 mlx5_core_destroy_mkey(mdev, &rq->umr_mkey);
 601                 break;
 602         default: /* MLX5_WQ_TYPE_CYCLIC */
 603                 kvfree(rq->wqe.frags);
 604                 mlx5e_free_di_list(rq);
 605         }
 606
 607 err_rq_wq_destroy:
 608         if (rq->xdp_prog)
 609                 bpf_prog_put(rq->xdp_prog);
 610         xdp_rxq_info_unreg(&rq->xdp_rxq);
 611         page_pool_destroy(rq->page_pool);
 612         mlx5_wq_destroy(&rq->wq_ctrl);
 613
 614         return err;
 615 }
 616
 617 static void mlx5e_free_rq(struct mlx5e_rq *rq)
 618 {
 619         int i;
 620
 621         if (rq->xdp_prog)
 622                 bpf_prog_put(rq->xdp_prog);
 623
 624         switch (rq->wq_type) {
 625         case MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ:
 626                 kvfree(rq->mpwqe.info);
 627                 mlx5_core_destroy_mkey(rq->mdev, &rq->umr_mkey);
 628                 break;
 629         default: /* MLX5_WQ_TYPE_CYCLIC */
 630                 kvfree(rq->wqe.frags);
 631                 mlx5e_free_di_list(rq);
 632         }
 633
 634         for (i = rq->page_cache.head; i != rq->page_cache.tail;
 635              i = (i + 1) & (MLX5E_CACHE_SIZE - 1)) {
 636                 struct mlx5e_dma_info *dma_info = &rq->page_cache.page_cache[i];
 637
 638                 /* With AF_XDP, page_cache is not used, so this loop is not
 639                  * entered, and it's safe to call mlx5e_page_release_dynamic
 640                  * directly.
 641                  */
 642                 mlx5e_page_release_dynamic(rq, dma_info, false);
 643         }
 644
 645         xdp_rxq_info_unreg(&rq->xdp_rxq);
 646         page_pool_destroy(rq->page_pool);
 647         mlx5_wq_destroy(&rq->wq_ctrl);
 648 }
 649
 650 static int mlx5e_create_rq(struct mlx5e_rq *rq,
 651                            struct mlx5e_rq_param *param)
 652 {
 653         struct mlx5_core_dev *mdev = rq->mdev;
 654
 655         void *in;
 656         void *rqc;
 657         void *wq;
 658         int inlen;
 659         int err;
 660
 661         inlen = MLX5_ST_SZ_BYTES(create_rq_in) +
 662                 sizeof(u64) * rq->wq_ctrl.buf.npages;
 663         in = kvzalloc(inlen, GFP_KERNEL);
 664         if (!in)
 665                 return -ENOMEM;
 666
 667         rqc = MLX5_ADDR_OF(create_rq_in, in, ctx);
 668         wq  = MLX5_ADDR_OF(rqc, rqc, wq);
 669
 670         memcpy(rqc, param->rqc, sizeof(param->rqc));
 671
 672         MLX5_SET(rqc,  rqc, cqn,                rq->cq.mcq.cqn);
 673         MLX5_SET(rqc,  rqc, state,              MLX5_RQC_STATE_RST);
 674         MLX5_SET(wq,   wq,  log_wq_pg_sz,       rq->wq_ctrl.buf.page_shift -
 675                                                 MLX5_ADAPTER_PAGE_SHIFT);
 676         MLX5_SET64(wq, wq,  dbr_addr,           rq->wq_ctrl.db.dma);
 677
 678         mlx5_fill_page_frag_array(&rq->wq_ctrl.buf,
 679                                   (__be64 *)MLX5_ADDR_OF(wq, wq, pas));
 680
 681         err = mlx5_core_create_rq(mdev, in, inlen, &rq->rqn);
 682
 683         kvfree(in);
 684
 685         return err;
 686 }
 687
 688 int mlx5e_modify_rq_state(struct mlx5e_rq *rq, int curr_state, int next_state)
 689 {
 690         struct mlx5_core_dev *mdev = rq->mdev;
 691
 692         void *in;
 693         void *rqc;
 694         int inlen;
 695         int err;
 696
 697         inlen = MLX5_ST_SZ_BYTES(modify_rq_in);
 698         in = kvzalloc(inlen, GFP_KERNEL);
 699         if (!in)
 700                 return -ENOMEM;
 701
 702         if (curr_state == MLX5_RQC_STATE_RST && next_state == MLX5_RQC_STATE_RDY)
 703                 mlx5e_rqwq_reset(rq);
 704
 705         rqc = MLX5_ADDR_OF(modify_rq_in, in, ctx);
 706
 707         MLX5_SET(modify_rq_in, in, rq_state, curr_state);
 708         MLX5_SET(rqc, rqc, state, next_state);
 709
 710         err = mlx5_core_modify_rq(mdev, rq->rqn, in);
 711
 712         kvfree(in);
 713
 714         return err;
 715 }
 716
 717 static int mlx5e_modify_rq_scatter_fcs(struct mlx5e_rq *rq, bool enable)
 718 {
 719         struct mlx5e_channel *c = rq->channel;
 720         struct mlx5e_priv *priv = c->priv;
 721         struct mlx5_core_dev *mdev = priv->mdev;
 722
 723         void *in;
 724         void *rqc;
 725         int inlen;
 726         int err;
 727
 728         inlen = MLX5_ST_SZ_BYTES(modify_rq_in);
 729         in = kvzalloc(inlen, GFP_KERNEL);
 730         if (!in)
 731                 return -ENOMEM;
 732
 733         rqc = MLX5_ADDR_OF(modify_rq_in, in, ctx);
 734
 735         MLX5_SET(modify_rq_in, in, rq_state, MLX5_RQC_STATE_RDY);
 736         MLX5_SET64(modify_rq_in, in, modify_bitmask,
 737                    MLX5_MODIFY_RQ_IN_MODIFY_BITMASK_SCATTER_FCS);
 738         MLX5_SET(rqc, rqc, scatter_fcs, enable);
 739         MLX5_SET(rqc, rqc, state, MLX5_RQC_STATE_RDY);
 740
 741         err = mlx5_core_modify_rq(mdev, rq->rqn, in);
 742
 743         kvfree(in);
 744
 745         return err;
 746 }
 747
 748 static int mlx5e_modify_rq_vsd(struct mlx5e_rq *rq, bool vsd)
 749 {
 750         struct mlx5e_channel *c = rq->channel;
 751         struct mlx5_core_dev *mdev = c->mdev;
 752         void *in;
 753         void *rqc;
 754         int inlen;
 755         int err;
 756
 757         inlen = MLX5_ST_SZ_BYTES(modify_rq_in);
 758         in = kvzalloc(inlen, GFP_KERNEL);
 759         if (!in)
 760                 return -ENOMEM;
 761
 762         rqc = MLX5_ADDR_OF(modify_rq_in, in, ctx);
 763
 764         MLX5_SET(modify_rq_in, in, rq_state, MLX5_RQC_STATE_RDY);
 765         MLX5_SET64(modify_rq_in, in, modify_bitmask,
 766                    MLX5_MODIFY_RQ_IN_MODIFY_BITMASK_VSD);
 767         MLX5_SET(rqc, rqc, vsd, vsd);
 768         MLX5_SET(rqc, rqc, state, MLX5_RQC_STATE_RDY);
 769
 770         err = mlx5_core_modify_rq(mdev, rq->rqn, in);
 771
 772         kvfree(in);
 773
 774         return err;
 775 }
 776
 777 static void mlx5e_destroy_rq(struct mlx5e_rq *rq)
 778 {
 779         mlx5_core_destroy_rq(rq->mdev, rq->rqn);
 780 }
 781
 782 int mlx5e_wait_for_min_rx_wqes(struct mlx5e_rq *rq, int wait_time)
 783 {
 784         unsigned long exp_time = jiffies + msecs_to_jiffies(wait_time);
 785         struct mlx5e_channel *c = rq->channel;
 786
 787         u16 min_wqes = mlx5_min_rx_wqes(rq->wq_type, mlx5e_rqwq_get_size(rq));
 788
 789         do {
 790                 if (mlx5e_rqwq_get_cur_sz(rq) >= min_wqes)
 791                         return 0;
 792
 793                 msleep(20);
 794         } while (time_before(jiffies, exp_time));
 795
 796         netdev_warn(c->netdev, "Failed to get min RX wqes on Channel[%d] RQN[0x%x] wq cur_sz(%d) min_rx_wqes(%d)\n",
 797                     c->ix, rq->rqn, mlx5e_rqwq_get_cur_sz(rq), min_wqes);
 798
 799         mlx5e_reporter_rx_timeout(rq);
 800         return -ETIMEDOUT;
 801 }
 802
 803 void mlx5e_free_rx_in_progress_descs(struct mlx5e_rq *rq)
 804 {
 805         struct mlx5_wq_ll *wq;
 806         u16 head;
 807         int i;
 808
 809         if (rq->wq_type != MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ)
 810                 return;
 811
 812         wq = &rq->mpwqe.wq;
 813         head = wq->head;
 814
 815         /* Outstanding UMR WQEs (in progress) start at wq->head */
 816         for (i = 0; i < rq->mpwqe.umr_in_progress; i++) {
 817                 rq->dealloc_wqe(rq, head);
 818                 head = mlx5_wq_ll_get_wqe_next_ix(wq, head);
 819         }
 820
 821         rq->mpwqe.actual_wq_head = wq->head;
 822         rq->mpwqe.umr_in_progress = 0;
 823         rq->mpwqe.umr_completed = 0;
 824 }
 825
 826 void mlx5e_free_rx_descs(struct mlx5e_rq *rq)
 827 {
 828         __be16 wqe_ix_be;
 829         u16 wqe_ix;
 830
 831         if (rq->wq_type == MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ) {
 832                 struct mlx5_wq_ll *wq = &rq->mpwqe.wq;
 833
 834                 mlx5e_free_rx_in_progress_descs(rq);
 835
 836                 while (!mlx5_wq_ll_is_empty(wq)) {
 837                         struct mlx5e_rx_wqe_ll *wqe;
 838
 839                         wqe_ix_be = *wq->tail_next;
 840                         wqe_ix    = be16_to_cpu(wqe_ix_be);
 841                         wqe       = mlx5_wq_ll_get_wqe(wq, wqe_ix);
 842                         rq->dealloc_wqe(rq, wqe_ix);
 843                         mlx5_wq_ll_pop(wq, wqe_ix_be,
 844                                        &wqe->next.next_wqe_index);
 845                 }
 846         } else {
 847                 struct mlx5_wq_cyc *wq = &rq->wqe.wq;
 848
 849                 while (!mlx5_wq_cyc_is_empty(wq)) {
 850                         wqe_ix = mlx5_wq_cyc_get_tail(wq);
 851                         rq->dealloc_wqe(rq, wqe_ix);
 852                         mlx5_wq_cyc_pop(wq);
 853                 }
 854         }
 855
 856 }
 857
 858 int mlx5e_open_rq(struct mlx5e_channel *c, struct mlx5e_params *params,
 859                   struct mlx5e_rq_param *param, struct mlx5e_xsk_param *xsk,
 860                   struct xdp_umem *umem, struct mlx5e_rq *rq)
 861 {
 862         int err;
 863
 864         err = mlx5e_alloc_rq(c, params, xsk, umem, param, rq);
 865         if (err)
 866                 return err;
 867
 868         err = mlx5e_create_rq(rq, param);
 869         if (err)
 870                 goto err_free_rq;
 871
 872         err = mlx5e_modify_rq_state(rq, MLX5_RQC_STATE_RST, MLX5_RQC_STATE_RDY);
 873         if (err)
 874                 goto err_destroy_rq;
 875
 876         if (MLX5_CAP_ETH(c->mdev, cqe_checksum_full))
 877                 __set_bit(MLX5E_RQ_STATE_CSUM_FULL, &c->rq.state);
 878
 879         if (params->rx_dim_enabled)
 880                 __set_bit(MLX5E_RQ_STATE_AM, &c->rq.state);
 881
 882         /* We disable csum_complete when XDP is enabled since
 883          * XDP programs might manipulate packets which will render
 884          * skb->checksum incorrect.
 885          */
 886         if (MLX5E_GET_PFLAG(params, MLX5E_PFLAG_RX_NO_CSUM_COMPLETE) || c->xdp)
 887                 __set_bit(MLX5E_RQ_STATE_NO_CSUM_COMPLETE, &c->rq.state);
 888
 889         return 0;
 890
 891 err_destroy_rq:
 892         mlx5e_destroy_rq(rq);
 893 err_free_rq:
 894         mlx5e_free_rq(rq);
 895
 896         return err;
 897 }
 898
 899 void mlx5e_activate_rq(struct mlx5e_rq *rq)
 900 {
 901         set_bit(MLX5E_RQ_STATE_ENABLED, &rq->state);
 902         mlx5e_trigger_irq(&rq->channel->icosq);
 903 }
 904
 905 void mlx5e_deactivate_rq(struct mlx5e_rq *rq)
 906 {
 907         clear_bit(MLX5E_RQ_STATE_ENABLED, &rq->state);
 908         napi_synchronize(&rq->channel->napi); /* prevent mlx5e_post_rx_wqes */
 909 }
 910
 911 void mlx5e_close_rq(struct mlx5e_rq *rq)
 912 {
 913         cancel_work_sync(&rq->dim.work);
 914         cancel_work_sync(&rq->channel->icosq.recover_work);
 915         cancel_work_sync(&rq->recover_work);
 916         mlx5e_destroy_rq(rq);
 917         mlx5e_free_rx_descs(rq);
 918         mlx5e_free_rq(rq);
 919 }
 920
 921 static void mlx5e_free_xdpsq_db(struct mlx5e_xdpsq *sq)
 922 {
 923         kvfree(sq->db.xdpi_fifo.xi);
 924         kvfree(sq->db.wqe_info);
 925 }
 926
 927 static int mlx5e_alloc_xdpsq_fifo(struct mlx5e_xdpsq *sq, int numa)
 928 {
 929         struct mlx5e_xdp_info_fifo *xdpi_fifo = &sq->db.xdpi_fifo;
 930         int wq_sz        = mlx5_wq_cyc_get_size(&sq->wq);
 931         int dsegs_per_wq = wq_sz * MLX5_SEND_WQEBB_NUM_DS;
 932
 933         xdpi_fifo->xi = kvzalloc_node(sizeof(*xdpi_fifo->xi) * dsegs_per_wq,
 934                                       GFP_KERNEL, numa);
 935         if (!xdpi_fifo->xi)
 936                 return -ENOMEM;
 937
 938         xdpi_fifo->pc   = &sq->xdpi_fifo_pc;
 939         xdpi_fifo->cc   = &sq->xdpi_fifo_cc;
 940         xdpi_fifo->mask = dsegs_per_wq - 1;
 941
 942         return 0;
 943 }
 944
 945 static int mlx5e_alloc_xdpsq_db(struct mlx5e_xdpsq *sq, int numa)
 946 {
 947         int wq_sz = mlx5_wq_cyc_get_size(&sq->wq);
 948         int err;
 949
 950         sq->db.wqe_info = kvzalloc_node(sizeof(*sq->db.wqe_info) * wq_sz,
 951                                         GFP_KERNEL, numa);
 952         if (!sq->db.wqe_info)
 953                 return -ENOMEM;
 954
 955         err = mlx5e_alloc_xdpsq_fifo(sq, numa);
 956         if (err) {
 957                 mlx5e_free_xdpsq_db(sq);
 958                 return err;
 959         }
 960
 961         return 0;
 962 }
 963
 964 static int mlx5e_alloc_xdpsq(struct mlx5e_channel *c,
 965                              struct mlx5e_params *params,
 966                              struct xdp_umem *umem,
 967                              struct mlx5e_sq_param *param,
 968                              struct mlx5e_xdpsq *sq,
 969                              bool is_redirect)
 970 {
 971         void *sqc_wq               = MLX5_ADDR_OF(sqc, param->sqc, wq);
 972         struct mlx5_core_dev *mdev = c->mdev;
 973         struct mlx5_wq_cyc *wq = &sq->wq;
 974         int err;
 975
 976         sq->pdev      = c->pdev;
 977         sq->mkey_be   = c->mkey_be;
 978         sq->channel   = c;
 979         sq->uar_map   = mdev->mlx5e_res.bfreg.map;
 980         sq->min_inline_mode = params->tx_min_inline_mode;
 981         sq->hw_mtu    = MLX5E_SW2HW_MTU(params, params->sw_mtu);
 982         sq->umem      = umem;
 983
 984         sq->stats = sq->umem ?
 985                 &c->priv->channel_stats[c->ix].xsksq :
 986                 is_redirect ?
 987                         &c->priv->channel_stats[c->ix].xdpsq :
 988                         &c->priv->channel_stats[c->ix].rq_xdpsq;
 989
 990         param->wq.db_numa_node = cpu_to_node(c->cpu);
 991         err = mlx5_wq_cyc_create(mdev, &param->wq, sqc_wq, wq, &sq->wq_ctrl);
 992         if (err)
 993                 return err;
 994         wq->db = &wq->db[MLX5_SND_DBR];
 995
 996         err = mlx5e_alloc_xdpsq_db(sq, cpu_to_node(c->cpu));
 997         if (err)
 998                 goto err_sq_wq_destroy;
 999
1000         return 0;
1001
1002 err_sq_wq_destroy:
1003         mlx5_wq_destroy(&sq->wq_ctrl);
1004
1005         return err;
1006 }
1007
1008 static void mlx5e_free_xdpsq(struct mlx5e_xdpsq *sq)
1009 {
1010         mlx5e_free_xdpsq_db(sq);
1011         mlx5_wq_destroy(&sq->wq_ctrl);
1012 }
1013
1014 static void mlx5e_free_icosq_db(struct mlx5e_icosq *sq)
1015 {
1016         kvfree(sq->db.wqe_info);
1017 }
1018
1019 static int mlx5e_alloc_icosq_db(struct mlx5e_icosq *sq, int numa)
1020 {
1021         int wq_sz = mlx5_wq_cyc_get_size(&sq->wq);
1022         size_t size;
1023
1024         size = array_size(wq_sz, sizeof(*sq->db.wqe_info));
1025         sq->db.wqe_info = kvzalloc_node(size, GFP_KERNEL, numa);
1026         if (!sq->db.wqe_info)
1027                 return -ENOMEM;
1028
1029         return 0;
1030 }
1031
1032 static void mlx5e_icosq_err_cqe_work(struct work_struct *recover_work)
1033 {
1034         struct mlx5e_icosq *sq = container_of(recover_work, struct mlx5e_icosq,
1035                                               recover_work);
1036
1037         mlx5e_reporter_icosq_cqe_err(sq);
1038 }
1039
1040 static int mlx5e_alloc_icosq(struct mlx5e_channel *c,
1041                              struct mlx5e_sq_param *param,
1042                              struct mlx5e_icosq *sq)
1043 {
1044         void *sqc_wq               = MLX5_ADDR_OF(sqc, param->sqc, wq);
1045         struct mlx5_core_dev *mdev = c->mdev;
1046         struct mlx5_wq_cyc *wq = &sq->wq;
1047         int err;
1048
1049         sq->channel   = c;
1050         sq->uar_map   = mdev->mlx5e_res.bfreg.map;
1051
1052         param->wq.db_numa_node = cpu_to_node(c->cpu);
1053         err = mlx5_wq_cyc_create(mdev, &param->wq, sqc_wq, wq, &sq->wq_ctrl);
1054         if (err)
1055                 return err;
1056         wq->db = &wq->db[MLX5_SND_DBR];
1057
1058         err = mlx5e_alloc_icosq_db(sq, cpu_to_node(c->cpu));
1059         if (err)
1060                 goto err_sq_wq_destroy;
1061
1062         INIT_WORK(&sq->recover_work, mlx5e_icosq_err_cqe_work);
1063
1064         return 0;
1065
1066 err_sq_wq_destroy:
1067         mlx5_wq_destroy(&sq->wq_ctrl);
1068
1069         return err;
1070 }
1071
1072 static void mlx5e_free_icosq(struct mlx5e_icosq *sq)
1073 {
1074         mlx5e_free_icosq_db(sq);
1075         mlx5_wq_destroy(&sq->wq_ctrl);
1076 }
1077
1078 static void mlx5e_free_txqsq_db(struct mlx5e_txqsq *sq)
1079 {
1080         kvfree(sq->db.wqe_info);
1081         kvfree(sq->db.dma_fifo);
1082 }
1083
1084 static int mlx5e_alloc_txqsq_db(struct mlx5e_txqsq *sq, int numa)
1085 {
1086         int wq_sz = mlx5_wq_cyc_get_size(&sq->wq);
1087         int df_sz = wq_sz * MLX5_SEND_WQEBB_NUM_DS;
1088
1089         sq->db.dma_fifo = kvzalloc_node(array_size(df_sz,
1090                                                    sizeof(*sq->db.dma_fifo)),
1091                                         GFP_KERNEL, numa);
1092         sq->db.wqe_info = kvzalloc_node(array_size(wq_sz,
1093                                                    sizeof(*sq->db.wqe_info)),
1094                                         GFP_KERNEL, numa);
1095         if (!sq->db.dma_fifo || !sq->db.wqe_info) {
1096                 mlx5e_free_txqsq_db(sq);
1097                 return -ENOMEM;
1098         }
1099
1100         sq->dma_fifo_mask = df_sz - 1;
1101
1102         return 0;
1103 }
1104
1105 static int mlx5e_calc_sq_stop_room(struct mlx5e_txqsq *sq, u8 log_sq_size)
1106 {
1107         int sq_size = 1 << log_sq_size;
1108
1109         sq->stop_room  = mlx5e_tls_get_stop_room(sq);
1110         sq->stop_room += mlx5e_stop_room_for_wqe(MLX5_SEND_WQE_MAX_WQEBBS);
1111
1112         if (WARN_ON(sq->stop_room >= sq_size)) {
1113                 netdev_err(sq->channel->netdev, "Stop room %hu is bigger than the SQ size %d\n",
1114                            sq->stop_room, sq_size);
1115                 return -ENOSPC;
1116         }
1117
1118         return 0;
1119 }
1120
1121 static void mlx5e_tx_err_cqe_work(struct work_struct *recover_work);
1122 static int mlx5e_alloc_txqsq(struct mlx5e_channel *c,
1123                              int txq_ix,
1124                              struct mlx5e_params *params,
1125                              struct mlx5e_sq_param *param,
1126                              struct mlx5e_txqsq *sq,
1127                              int tc)
1128 {
1129         void *sqc_wq               = MLX5_ADDR_OF(sqc, param->sqc, wq);
1130         struct mlx5_core_dev *mdev = c->mdev;
1131         struct mlx5_wq_cyc *wq = &sq->wq;
1132         int err;
1133
1134         sq->pdev      = c->pdev;
1135         sq->tstamp    = c->tstamp;
1136         sq->clock     = &mdev->clock;
1137         sq->mkey_be   = c->mkey_be;
1138         sq->channel   = c;
1139         sq->ch_ix     = c->ix;
1140         sq->txq_ix    = txq_ix;
1141         sq->uar_map   = mdev->mlx5e_res.bfreg.map;
1142         sq->min_inline_mode = params->tx_min_inline_mode;
1143         sq->hw_mtu    = MLX5E_SW2HW_MTU(params, params->sw_mtu);
1144         sq->stats     = &c->priv->channel_stats[c->ix].sq[tc];
1145         INIT_WORK(&sq->recover_work, mlx5e_tx_err_cqe_work);
1146         if (!MLX5_CAP_ETH(mdev, wqe_vlan_insert))
1147                 set_bit(MLX5E_SQ_STATE_VLAN_NEED_L2_INLINE, &sq->state);
1148         if (MLX5_IPSEC_DEV(c->priv->mdev))
1149                 set_bit(MLX5E_SQ_STATE_IPSEC, &sq->state);
1150         if (mlx5_accel_is_tls_device(c->priv->mdev))
1151                 set_bit(MLX5E_SQ_STATE_TLS, &sq->state);
1152         err = mlx5e_calc_sq_stop_room(sq, params->log_sq_size);
1153         if (err)
1154                 return err;
1155
1156         param->wq.db_numa_node = cpu_to_node(c->cpu);
1157         err = mlx5_wq_cyc_create(mdev, &param->wq, sqc_wq, wq, &sq->wq_ctrl);
1158         if (err)
1159                 return err;
1160         wq->db    = &wq->db[MLX5_SND_DBR];
1161
1162         err = mlx5e_alloc_txqsq_db(sq, cpu_to_node(c->cpu));
1163         if (err)
1164                 goto err_sq_wq_destroy;
1165
1166         INIT_WORK(&sq->dim.work, mlx5e_tx_dim_work);
1167         sq->dim.mode = params->tx_cq_moderation.cq_period_mode;
1168
1169         return 0;
1170
1171 err_sq_wq_destroy:
1172         mlx5_wq_destroy(&sq->wq_ctrl);
1173
1174         return err;
1175 }
1176
1177 static void mlx5e_free_txqsq(struct mlx5e_txqsq *sq)
1178 {
1179         mlx5e_free_txqsq_db(sq);
1180         mlx5_wq_destroy(&sq->wq_ctrl);
1181 }
1182
1183 struct mlx5e_create_sq_param {
1184         struct mlx5_wq_ctrl        *wq_ctrl;
1185         u32                         cqn;
1186         u32                         tisn;
1187         u8                          tis_lst_sz;
1188         u8                          min_inline_mode;
1189 };
1190
1191 static int mlx5e_create_sq(struct mlx5_core_dev *mdev,
1192                            struct mlx5e_sq_param *param,
1193                            struct mlx5e_create_sq_param *csp,
1194                            u32 *sqn)
1195 {
1196         void *in;
1197         void *sqc;
1198         void *wq;
1199         int inlen;
1200         int err;
1201
1202         inlen = MLX5_ST_SZ_BYTES(create_sq_in) +
1203                 sizeof(u64) * csp->wq_ctrl->buf.npages;
1204         in = kvzalloc(inlen, GFP_KERNEL);
1205         if (!in)
1206                 return -ENOMEM;
1207
1208         sqc = MLX5_ADDR_OF(create_sq_in, in, ctx);
1209         wq = MLX5_ADDR_OF(sqc, sqc, wq);
1210
1211         memcpy(sqc, param->sqc, sizeof(param->sqc));
1212         MLX5_SET(sqc,  sqc, tis_lst_sz, csp->tis_lst_sz);
1213         MLX5_SET(sqc,  sqc, tis_num_0, csp->tisn);
1214         MLX5_SET(sqc,  sqc, cqn, csp->cqn);
1215
1216         if (MLX5_CAP_ETH(mdev, wqe_inline_mode) == MLX5_CAP_INLINE_MODE_VPORT_CONTEXT)
1217                 MLX5_SET(sqc,  sqc, min_wqe_inline_mode, csp->min_inline_mode);
1218
1219         MLX5_SET(sqc,  sqc, state, MLX5_SQC_STATE_RST);
1220         MLX5_SET(sqc,  sqc, flush_in_error_en, 1);
1221
1222         MLX5_SET(wq,   wq, wq_type,       MLX5_WQ_TYPE_CYCLIC);
1223         MLX5_SET(wq,   wq, uar_page,      mdev->mlx5e_res.bfreg.index);
1224         MLX5_SET(wq,   wq, log_wq_pg_sz,  csp->wq_ctrl->buf.page_shift -
1225                                           MLX5_ADAPTER_PAGE_SHIFT);
1226         MLX5_SET64(wq, wq, dbr_addr,      csp->wq_ctrl->db.dma);
1227
1228         mlx5_fill_page_frag_array(&csp->wq_ctrl->buf,
1229                                   (__be64 *)MLX5_ADDR_OF(wq, wq, pas));
1230
1231         err = mlx5_core_create_sq(mdev, in, inlen, sqn);
1232
1233         kvfree(in);
1234
1235         return err;
1236 }
1237
1238 int mlx5e_modify_sq(struct mlx5_core_dev *mdev, u32 sqn,
1239                     struct mlx5e_modify_sq_param *p)
1240 {
1241         void *in;
1242         void *sqc;
1243         int inlen;
1244         int err;
1245
1246         inlen = MLX5_ST_SZ_BYTES(modify_sq_in);
1247         in = kvzalloc(inlen, GFP_KERNEL);
1248         if (!in)
1249                 return -ENOMEM;
1250
1251         sqc = MLX5_ADDR_OF(modify_sq_in, in, ctx);
1252
1253         MLX5_SET(modify_sq_in, in, sq_state, p->curr_state);
1254         MLX5_SET(sqc, sqc, state, p->next_state);
1255         if (p->rl_update && p->next_state == MLX5_SQC_STATE_RDY) {
1256                 MLX5_SET64(modify_sq_in, in, modify_bitmask, 1);
1257                 MLX5_SET(sqc,  sqc, packet_pacing_rate_limit_index, p->rl_index);
1258         }
1259
1260         err = mlx5_core_modify_sq(mdev, sqn, in);
1261
1262         kvfree(in);
1263
1264         return err;
1265 }
1266
1267 static void mlx5e_destroy_sq(struct mlx5_core_dev *mdev, u32 sqn)
1268 {
1269         mlx5_core_destroy_sq(mdev, sqn);
1270 }
1271
1272 static int mlx5e_create_sq_rdy(struct mlx5_core_dev *mdev,
1273                                struct mlx5e_sq_param *param,
1274                                struct mlx5e_create_sq_param *csp,
1275                                u32 *sqn)
1276 {
1277         struct mlx5e_modify_sq_param msp = {0};
1278         int err;
1279
1280         err = mlx5e_create_sq(mdev, param, csp, sqn);
1281         if (err)
1282                 return err;
1283
1284         msp.curr_state = MLX5_SQC_STATE_RST;
1285         msp.next_state = MLX5_SQC_STATE_RDY;
1286         err = mlx5e_modify_sq(mdev, *sqn, &msp);
1287         if (err)
1288                 mlx5e_destroy_sq(mdev, *sqn);
1289
1290         return err;
1291 }
1292
1293 static int mlx5e_set_sq_maxrate(struct net_device *dev,
1294                                 struct mlx5e_txqsq *sq, u32 rate);
1295
1296 static int mlx5e_open_txqsq(struct mlx5e_channel *c,
1297                             u32 tisn,
1298                             int txq_ix,
1299                             struct mlx5e_params *params,
1300                             struct mlx5e_sq_param *param,
1301                             struct mlx5e_txqsq *sq,
1302                             int tc)
1303 {
1304         struct mlx5e_create_sq_param csp = {};
1305         u32 tx_rate;
1306         int err;
1307
1308         err = mlx5e_alloc_txqsq(c, txq_ix, params, param, sq, tc);
1309         if (err)
1310                 return err;
1311
1312         csp.tisn            = tisn;
1313         csp.tis_lst_sz      = 1;
1314         csp.cqn             = sq->cq.mcq.cqn;
1315         csp.wq_ctrl         = &sq->wq_ctrl;
1316         csp.min_inline_mode = sq->min_inline_mode;
1317         err = mlx5e_create_sq_rdy(c->mdev, param, &csp, &sq->sqn);
1318         if (err)
1319                 goto err_free_txqsq;
1320
1321         tx_rate = c->priv->tx_rates[sq->txq_ix];
1322         if (tx_rate)
1323                 mlx5e_set_sq_maxrate(c->netdev, sq, tx_rate);
1324
1325         if (params->tx_dim_enabled)
1326                 sq->state |= BIT(MLX5E_SQ_STATE_AM);
1327
1328         return 0;
1329
1330 err_free_txqsq:
1331         mlx5e_free_txqsq(sq);
1332
1333         return err;
1334 }
1335
1336 void mlx5e_activate_txqsq(struct mlx5e_txqsq *sq)
1337 {
1338         sq->txq = netdev_get_tx_queue(sq->channel->netdev, sq->txq_ix);
1339         set_bit(MLX5E_SQ_STATE_ENABLED, &sq->state);
1340         netdev_tx_reset_queue(sq->txq);
1341         netif_tx_start_queue(sq->txq);
1342 }
1343
1344 void mlx5e_tx_disable_queue(struct netdev_queue *txq)
1345 {
1346         __netif_tx_lock_bh(txq);
1347         netif_tx_stop_queue(txq);
1348         __netif_tx_unlock_bh(txq);
1349 }
1350
1351 static void mlx5e_deactivate_txqsq(struct mlx5e_txqsq *sq)
1352 {
1353         struct mlx5e_channel *c = sq->channel;
1354         struct mlx5_wq_cyc *wq = &sq->wq;
1355
1356         clear_bit(MLX5E_SQ_STATE_ENABLED, &sq->state);
1357         /* prevent netif_tx_wake_queue */
1358         napi_synchronize(&c->napi);
1359
1360         mlx5e_tx_disable_queue(sq->txq);
1361
1362         /* last doorbell out, godspeed .. */
1363         if (mlx5e_wqc_has_room_for(wq, sq->cc, sq->pc, 1)) {
1364                 u16 pi = mlx5_wq_cyc_ctr2ix(wq, sq->pc);
1365                 struct mlx5e_tx_wqe *nop;
1366
1367                 sq->db.wqe_info[pi] = (struct mlx5e_tx_wqe_info) {
1368                         .num_wqebbs = 1,
1369                 };
1370
1371                 nop = mlx5e_post_nop(wq, sq->sqn, &sq->pc);
1372                 mlx5e_notify_hw(wq, sq->pc, sq->uar_map, &nop->ctrl);
1373         }
1374 }
1375
1376 static void mlx5e_close_txqsq(struct mlx5e_txqsq *sq)
1377 {
1378         struct mlx5e_channel *c = sq->channel;
1379         struct mlx5_core_dev *mdev = c->mdev;
1380         struct mlx5_rate_limit rl = {0};
1381
1382         cancel_work_sync(&sq->dim.work);
1383         cancel_work_sync(&sq->recover_work);
1384         mlx5e_destroy_sq(mdev, sq->sqn);
1385         if (sq->rate_limit) {
1386                 rl.rate = sq->rate_limit;
1387                 mlx5_rl_remove_rate(mdev, &rl);
1388         }
1389         mlx5e_free_txqsq_descs(sq);
1390         mlx5e_free_txqsq(sq);
1391 }
1392
1393 static void mlx5e_tx_err_cqe_work(struct work_struct *recover_work)
1394 {
1395         struct mlx5e_txqsq *sq = container_of(recover_work, struct mlx5e_txqsq,
1396                                               recover_work);
1397
1398         mlx5e_reporter_tx_err_cqe(sq);
1399 }
1400
1401 int mlx5e_open_icosq(struct mlx5e_channel *c, struct mlx5e_params *params,
1402                      struct mlx5e_sq_param *param, struct mlx5e_icosq *sq)
1403 {
1404         struct mlx5e_create_sq_param csp = {};
1405         int err;
1406
1407         err = mlx5e_alloc_icosq(c, param, sq);
1408         if (err)
1409                 return err;
1410
1411         csp.cqn             = sq->cq.mcq.cqn;
1412         csp.wq_ctrl         = &sq->wq_ctrl;
1413         csp.min_inline_mode = params->tx_min_inline_mode;
1414         err = mlx5e_create_sq_rdy(c->mdev, param, &csp, &sq->sqn);
1415         if (err)
1416                 goto err_free_icosq;
1417
1418         return 0;
1419
1420 err_free_icosq:
1421         mlx5e_free_icosq(sq);
1422
1423         return err;
1424 }
1425
1426 void mlx5e_activate_icosq(struct mlx5e_icosq *icosq)
1427 {
1428         set_bit(MLX5E_SQ_STATE_ENABLED, &icosq->state);
1429 }
1430
1431 void mlx5e_deactivate_icosq(struct mlx5e_icosq *icosq)
1432 {
1433         struct mlx5e_channel *c = icosq->channel;
1434
1435         clear_bit(MLX5E_SQ_STATE_ENABLED, &icosq->state);
1436         napi_synchronize(&c->napi);
1437 }
1438
1439 void mlx5e_close_icosq(struct mlx5e_icosq *sq)
1440 {
1441         struct mlx5e_channel *c = sq->channel;
1442
1443         mlx5e_destroy_sq(c->mdev, sq->sqn);
1444         mlx5e_free_icosq(sq);
1445 }
1446
1447 int mlx5e_open_xdpsq(struct mlx5e_channel *c, struct mlx5e_params *params,
1448                      struct mlx5e_sq_param *param, struct xdp_umem *umem,
1449                      struct mlx5e_xdpsq *sq, bool is_redirect)
1450 {
1451         struct mlx5e_create_sq_param csp = {};
1452         int err;
1453
1454         err = mlx5e_alloc_xdpsq(c, params, umem, param, sq, is_redirect);
1455         if (err)
1456                 return err;
1457
1458         csp.tis_lst_sz      = 1;
1459         csp.tisn            = c->priv->tisn[c->lag_port][0]; /* tc = 0 */
1460         csp.cqn             = sq->cq.mcq.cqn;
1461         csp.wq_ctrl         = &sq->wq_ctrl;
1462         csp.min_inline_mode = sq->min_inline_mode;
1463         set_bit(MLX5E_SQ_STATE_ENABLED, &sq->state);
1464         err = mlx5e_create_sq_rdy(c->mdev, param, &csp, &sq->sqn);
1465         if (err)
1466                 goto err_free_xdpsq;
1467
1468         mlx5e_set_xmit_fp(sq, param->is_mpw);
1469
1470         if (!param->is_mpw) {
1471                 unsigned int ds_cnt = MLX5E_XDP_TX_DS_COUNT;
1472                 unsigned int inline_hdr_sz = 0;
1473                 int i;
1474
1475                 if (sq->min_inline_mode != MLX5_INLINE_MODE_NONE) {
1476                         inline_hdr_sz = MLX5E_XDP_MIN_INLINE;
1477                         ds_cnt++;
1478                 }
1479
1480                 /* Pre initialize fixed WQE fields */
1481                 for (i = 0; i < mlx5_wq_cyc_get_size(&sq->wq); i++) {
1482                         struct mlx5e_tx_wqe      *wqe  = mlx5_wq_cyc_get_wqe(&sq->wq, i);
1483                         struct mlx5_wqe_ctrl_seg *cseg = &wqe->ctrl;
1484                         struct mlx5_wqe_eth_seg  *eseg = &wqe->eth;
1485                         struct mlx5_wqe_data_seg *dseg;
1486
1487                         sq->db.wqe_info[i] = (struct mlx5e_xdp_wqe_info) {
1488                                 .num_wqebbs = 1,
1489                                 .num_pkts   = 1,
1490                         };
1491
1492                         cseg->qpn_ds = cpu_to_be32((sq->sqn << 8) | ds_cnt);
1493                         eseg->inline_hdr.sz = cpu_to_be16(inline_hdr_sz);
1494
1495                         dseg = (struct mlx5_wqe_data_seg *)cseg + (ds_cnt - 1);
1496                         dseg->lkey = sq->mkey_be;
1497                 }
1498         }
1499
1500         return 0;
1501
1502 err_free_xdpsq:
1503         clear_bit(MLX5E_SQ_STATE_ENABLED, &sq->state);
1504         mlx5e_free_xdpsq(sq);
1505
1506         return err;
1507 }
1508
1509 void mlx5e_close_xdpsq(struct mlx5e_xdpsq *sq)
1510 {
1511         struct mlx5e_channel *c = sq->channel;
1512
1513         clear_bit(MLX5E_SQ_STATE_ENABLED, &sq->state);
1514         napi_synchronize(&c->napi);
1515
1516         mlx5e_destroy_sq(c->mdev, sq->sqn);
1517         mlx5e_free_xdpsq_descs(sq);
1518         mlx5e_free_xdpsq(sq);
1519 }
1520
1521 static int mlx5e_alloc_cq_common(struct mlx5_core_dev *mdev,
1522                                  struct mlx5e_cq_param *param,
1523                                  struct mlx5e_cq *cq)
1524 {
1525         struct mlx5_core_cq *mcq = &cq->mcq;
1526         int eqn_not_used;
1527         unsigned int irqn;
1528         int err;
1529         u32 i;
1530
1531         err = mlx5_vector2eqn(mdev, param->eq_ix, &eqn_not_used, &irqn);
1532         if (err)
1533                 return err;
1534
1535         err = mlx5_cqwq_create(mdev, &param->wq, param->cqc, &cq->wq,
1536                                &cq->wq_ctrl);
1537         if (err)
1538                 return err;
1539
1540         mcq->cqe_sz     = 64;
1541         mcq->set_ci_db  = cq->wq_ctrl.db.db;
1542         mcq->arm_db     = cq->wq_ctrl.db.db + 1;
1543         *mcq->set_ci_db = 0;
1544         *mcq->arm_db    = 0;
1545         mcq->vector     = param->eq_ix;
1546         mcq->comp       = mlx5e_completion_event;
1547         mcq->event      = mlx5e_cq_error_event;
1548         mcq->irqn       = irqn;
1549
1550         for (i = 0; i < mlx5_cqwq_get_size(&cq->wq); i++) {
1551                 struct mlx5_cqe64 *cqe = mlx5_cqwq_get_wqe(&cq->wq, i);
1552
1553                 cqe->op_own = 0xf1;
1554         }
1555
1556         cq->mdev = mdev;
1557
1558         return 0;
1559 }
1560
1561 static int mlx5e_alloc_cq(struct mlx5e_channel *c,
1562                           struct mlx5e_cq_param *param,
1563                           struct mlx5e_cq *cq)
1564 {
1565         struct mlx5_core_dev *mdev = c->priv->mdev;
1566         int err;
1567
1568         param->wq.buf_numa_node = cpu_to_node(c->cpu);
1569         param->wq.db_numa_node  = cpu_to_node(c->cpu);
1570         param->eq_ix   = c->ix;
1571
1572         err = mlx5e_alloc_cq_common(mdev, param, cq);
1573
1574         cq->napi    = &c->napi;
1575         cq->channel = c;
1576
1577         return err;
1578 }
1579
1580 static void mlx5e_free_cq(struct mlx5e_cq *cq)
1581 {
1582         mlx5_wq_destroy(&cq->wq_ctrl);
1583 }
1584
1585 static int mlx5e_create_cq(struct mlx5e_cq *cq, struct mlx5e_cq_param *param)
1586 {
1587         u32 out[MLX5_ST_SZ_DW(create_cq_out)];
1588         struct mlx5_core_dev *mdev = cq->mdev;
1589         struct mlx5_core_cq *mcq = &cq->mcq;
1590
1591         void *in;
1592         void *cqc;
1593         int inlen;
1594         unsigned int irqn_not_used;
1595         int eqn;
1596         int err;
1597
1598         err = mlx5_vector2eqn(mdev, param->eq_ix, &eqn, &irqn_not_used);
1599         if (err)
1600                 return err;
1601
1602         inlen = MLX5_ST_SZ_BYTES(create_cq_in) +
1603                 sizeof(u64) * cq->wq_ctrl.buf.npages;
1604         in = kvzalloc(inlen, GFP_KERNEL);
1605         if (!in)
1606                 return -ENOMEM;
1607
1608         cqc = MLX5_ADDR_OF(create_cq_in, in, cq_context);
1609
1610         memcpy(cqc, param->cqc, sizeof(param->cqc));
1611
1612         mlx5_fill_page_frag_array(&cq->wq_ctrl.buf,
1613                                   (__be64 *)MLX5_ADDR_OF(create_cq_in, in, pas));
1614
1615         MLX5_SET(cqc,   cqc, cq_period_mode, param->cq_period_mode);
1616         MLX5_SET(cqc,   cqc, c_eqn,         eqn);
1617         MLX5_SET(cqc,   cqc, uar_page,      mdev->priv.uar->index);
1618         MLX5_SET(cqc,   cqc, log_page_size, cq->wq_ctrl.buf.page_shift -
1619                                             MLX5_ADAPTER_PAGE_SHIFT);
1620         MLX5_SET64(cqc, cqc, dbr_addr,      cq->wq_ctrl.db.dma);
1621
1622         err = mlx5_core_create_cq(mdev, mcq, in, inlen, out, sizeof(out));
1623
1624         kvfree(in);
1625
1626         if (err)
1627                 return err;
1628
1629         mlx5e_cq_arm(cq);
1630
1631         return 0;
1632 }
1633
1634 static void mlx5e_destroy_cq(struct mlx5e_cq *cq)
1635 {
1636         mlx5_core_destroy_cq(cq->mdev, &cq->mcq);
1637 }
1638
1639 int mlx5e_open_cq(struct mlx5e_channel *c, struct dim_cq_moder moder,
1640                   struct mlx5e_cq_param *param, struct mlx5e_cq *cq)
1641 {
1642         struct mlx5_core_dev *mdev = c->mdev;
1643         int err;
1644
1645         err = mlx5e_alloc_cq(c, param, cq);
1646         if (err)
1647                 return err;
1648
1649         err = mlx5e_create_cq(cq, param);
1650         if (err)
1651                 goto err_free_cq;
1652
1653         if (MLX5_CAP_GEN(mdev, cq_moderation))
1654                 mlx5_core_modify_cq_moderation(mdev, &cq->mcq, moder.usec, moder.pkts);
1655         return 0;
1656
1657 err_free_cq:
1658         mlx5e_free_cq(cq);
1659
1660         return err;
1661 }
1662
1663 void mlx5e_close_cq(struct mlx5e_cq *cq)
1664 {
1665         mlx5e_destroy_cq(cq);
1666         mlx5e_free_cq(cq);
1667 }
1668
1669 static int mlx5e_open_tx_cqs(struct mlx5e_channel *c,
1670                              struct mlx5e_params *params,
1671                              struct mlx5e_channel_param *cparam)
1672 {
1673         int err;
1674         int tc;
1675
1676         for (tc = 0; tc < c->num_tc; tc++) {
1677                 err = mlx5e_open_cq(c, params->tx_cq_moderation,
1678                                     &cparam->txq_sq.cqp, &c->sq[tc].cq);
1679                 if (err)
1680                         goto err_close_tx_cqs;
1681         }
1682
1683         return 0;
1684
1685 err_close_tx_cqs:
1686         for (tc--; tc >= 0; tc--)
1687                 mlx5e_close_cq(&c->sq[tc].cq);
1688
1689         return err;
1690 }
1691
1692 static void mlx5e_close_tx_cqs(struct mlx5e_channel *c)
1693 {
1694         int tc;
1695
1696         for (tc = 0; tc < c->num_tc; tc++)
1697                 mlx5e_close_cq(&c->sq[tc].cq);
1698 }
1699
1700 static int mlx5e_open_sqs(struct mlx5e_channel *c,
1701                           struct mlx5e_params *params,
1702                           struct mlx5e_channel_param *cparam)
1703 {
1704         int err, tc;
1705
1706         for (tc = 0; tc < params->num_tc; tc++) {
1707                 int txq_ix = c->ix + tc * params->num_channels;
1708
1709                 err = mlx5e_open_txqsq(c, c->priv->tisn[c->lag_port][tc], txq_ix,
1710                                        params, &cparam->txq_sq, &c->sq[tc], tc);
1711                 if (err)
1712                         goto err_close_sqs;
1713         }
1714
1715         return 0;
1716
1717 err_close_sqs:
1718         for (tc--; tc >= 0; tc--)
1719                 mlx5e_close_txqsq(&c->sq[tc]);
1720
1721         return err;
1722 }
1723
1724 static void mlx5e_close_sqs(struct mlx5e_channel *c)
1725 {
1726         int tc;
1727
1728         for (tc = 0; tc < c->num_tc; tc++)
1729                 mlx5e_close_txqsq(&c->sq[tc]);
1730 }
1731
1732 static int mlx5e_set_sq_maxrate(struct net_device *dev,
1733                                 struct mlx5e_txqsq *sq, u32 rate)
1734 {
1735         struct mlx5e_priv *priv = netdev_priv(dev);
1736         struct mlx5_core_dev *mdev = priv->mdev;
1737         struct mlx5e_modify_sq_param msp = {0};
1738         struct mlx5_rate_limit rl = {0};
1739         u16 rl_index = 0;
1740         int err;
1741
1742         if (rate == sq->rate_limit)
1743                 /* nothing to do */
1744                 return 0;
1745
1746         if (sq->rate_limit) {
1747                 rl.rate = sq->rate_limit;
1748                 /* remove current rl index to free space to next ones */
1749                 mlx5_rl_remove_rate(mdev, &rl);
1750         }
1751
1752         sq->rate_limit = 0;
1753
1754         if (rate) {
1755                 rl.rate = rate;
1756                 err = mlx5_rl_add_rate(mdev, &rl_index, &rl);
1757                 if (err) {
1758                         netdev_err(dev, "Failed configuring rate %u: %d\n",
1759                                    rate, err);
1760                         return err;
1761                 }
1762         }
1763
1764         msp.curr_state = MLX5_SQC_STATE_RDY;
1765         msp.next_state = MLX5_SQC_STATE_RDY;
1766         msp.rl_index   = rl_index;
1767         msp.rl_update  = true;
1768         err = mlx5e_modify_sq(mdev, sq->sqn, &msp);
1769         if (err) {
1770                 netdev_err(dev, "Failed configuring rate %u: %d\n",
1771                            rate, err);
1772                 /* remove the rate from the table */
1773                 if (rate)
1774                         mlx5_rl_remove_rate(mdev, &rl);
1775                 return err;
1776         }
1777
1778         sq->rate_limit = rate;
1779         return 0;
1780 }
1781
1782 static int mlx5e_set_tx_maxrate(struct net_device *dev, int index, u32 rate)
1783 {
1784         struct mlx5e_priv *priv = netdev_priv(dev);
1785         struct mlx5_core_dev *mdev = priv->mdev;
1786         struct mlx5e_txqsq *sq = priv->txq2sq[index];
1787         int err = 0;
1788
1789         if (!mlx5_rl_is_supported(mdev)) {
1790                 netdev_err(dev, "Rate limiting is not supported on this device\n");
1791                 return -EINVAL;
1792         }
1793
1794         /* rate is given in Mb/sec, HW config is in Kb/sec */
1795         rate = rate << 10;
1796
1797         /* Check whether rate in valid range, 0 is always valid */
1798         if (rate && !mlx5_rl_is_in_range(mdev, rate)) {
1799                 netdev_err(dev, "TX rate %u, is not in range\n", rate);
1800                 return -ERANGE;
1801         }
1802
1803         mutex_lock(&priv->state_lock);
1804         if (test_bit(MLX5E_STATE_OPENED, &priv->state))
1805                 err = mlx5e_set_sq_maxrate(dev, sq, rate);
1806         if (!err)
1807                 priv->tx_rates[index] = rate;
1808         mutex_unlock(&priv->state_lock);
1809
1810         return err;
1811 }
1812
1813 static int mlx5e_open_queues(struct mlx5e_channel *c,
1814                              struct mlx5e_params *params,
1815                              struct mlx5e_channel_param *cparam)
1816 {
1817         struct dim_cq_moder icocq_moder = {0, 0};
1818         int err;
1819
1820         err = mlx5e_open_cq(c, icocq_moder, &cparam->icosq.cqp, &c->async_icosq.cq);
1821         if (err)
1822                 return err;
1823
1824         err = mlx5e_open_cq(c, icocq_moder, &cparam->async_icosq.cqp, &c->icosq.cq);
1825         if (err)
1826                 goto err_close_async_icosq_cq;
1827
1828         err = mlx5e_open_tx_cqs(c, params, cparam);
1829         if (err)
1830                 goto err_close_icosq_cq;
1831
1832         err = mlx5e_open_cq(c, params->tx_cq_moderation, &cparam->xdp_sq.cqp, &c->xdpsq.cq);
1833         if (err)
1834                 goto err_close_tx_cqs;
1835
1836         err = mlx5e_open_cq(c, params->rx_cq_moderation, &cparam->rq.cqp, &c->rq.cq);
1837         if (err)
1838                 goto err_close_xdp_tx_cqs;
1839
1840         err = c->xdp ? mlx5e_open_cq(c, params->tx_cq_moderation,
1841                                      &cparam->xdp_sq.cqp, &c->rq_xdpsq.cq) : 0;
1842         if (err)
1843                 goto err_close_rx_cq;
1844
1845         napi_enable(&c->napi);
1846
1847         spin_lock_init(&c->async_icosq_lock);
1848
1849         err = mlx5e_open_icosq(c, params, &cparam->async_icosq, &c->async_icosq);
1850         if (err)
1851                 goto err_disable_napi;
1852
1853         err = mlx5e_open_icosq(c, params, &cparam->icosq, &c->icosq);
1854         if (err)
1855                 goto err_close_async_icosq;
1856
1857         err = mlx5e_open_sqs(c, params, cparam);
1858         if (err)
1859                 goto err_close_icosq;
1860
1861         if (c->xdp) {
1862                 err = mlx5e_open_xdpsq(c, params, &cparam->xdp_sq, NULL,
1863                                        &c->rq_xdpsq, false);
1864                 if (err)
1865                         goto err_close_sqs;
1866         }
1867
1868         err = mlx5e_open_rq(c, params, &cparam->rq, NULL, NULL, &c->rq);
1869         if (err)
1870                 goto err_close_xdp_sq;
1871
1872         err = mlx5e_open_xdpsq(c, params, &cparam->xdp_sq, NULL, &c->xdpsq, true);
1873         if (err)
1874                 goto err_close_rq;
1875
1876         return 0;
1877
1878 err_close_rq:
1879         mlx5e_close_rq(&c->rq);
1880
1881 err_close_xdp_sq:
1882         if (c->xdp)
1883                 mlx5e_close_xdpsq(&c->rq_xdpsq);
1884
1885 err_close_sqs:
1886         mlx5e_close_sqs(c);
1887
1888 err_close_icosq:
1889         mlx5e_close_icosq(&c->icosq);
1890
1891 err_close_async_icosq:
1892         mlx5e_close_icosq(&c->async_icosq);
1893
1894 err_disable_napi:
1895         napi_disable(&c->napi);
1896
1897         if (c->xdp)
1898                 mlx5e_close_cq(&c->rq_xdpsq.cq);
1899
1900 err_close_rx_cq:
1901         mlx5e_close_cq(&c->rq.cq);
1902
1903 err_close_xdp_tx_cqs:
1904         mlx5e_close_cq(&c->xdpsq.cq);
1905
1906 err_close_tx_cqs:
1907         mlx5e_close_tx_cqs(c);
1908
1909 err_close_icosq_cq:
1910         mlx5e_close_cq(&c->icosq.cq);
1911
1912 err_close_async_icosq_cq:
1913         mlx5e_close_cq(&c->async_icosq.cq);
1914
1915         return err;
1916 }
1917
1918 static void mlx5e_close_queues(struct mlx5e_channel *c)
1919 {
1920         mlx5e_close_xdpsq(&c->xdpsq);
1921         mlx5e_close_rq(&c->rq);
1922         if (c->xdp)
1923                 mlx5e_close_xdpsq(&c->rq_xdpsq);
1924         mlx5e_close_sqs(c);
1925         mlx5e_close_icosq(&c->icosq);
1926         mlx5e_close_icosq(&c->async_icosq);
1927         napi_disable(&c->napi);
1928         if (c->xdp)
1929                 mlx5e_close_cq(&c->rq_xdpsq.cq);
1930         mlx5e_close_cq(&c->rq.cq);
1931         mlx5e_close_cq(&c->xdpsq.cq);
1932         mlx5e_close_tx_cqs(c);
1933         mlx5e_close_cq(&c->icosq.cq);
1934         mlx5e_close_cq(&c->async_icosq.cq);
1935 }
1936
1937 static u8 mlx5e_enumerate_lag_port(struct mlx5_core_dev *mdev, int ix)
1938 {
1939         u16 port_aff_bias = mlx5_core_is_pf(mdev) ? 0 : MLX5_CAP_GEN(mdev, vhca_id);
1940
1941         return (ix + port_aff_bias) % mlx5e_get_num_lag_ports(mdev);
1942 }
1943
1944 static int mlx5e_open_channel(struct mlx5e_priv *priv, int ix,
1945                               struct mlx5e_params *params,
1946                               struct mlx5e_channel_param *cparam,
1947                               struct xdp_umem *umem,
1948                               struct mlx5e_channel **cp)
1949 {
1950         int cpu = cpumask_first(mlx5_comp_irq_get_affinity_mask(priv->mdev, ix));
1951         struct net_device *netdev = priv->netdev;
1952         struct mlx5e_xsk_param xsk;
1953         struct mlx5e_channel *c;
1954         unsigned int irq;
1955         int err;
1956         int eqn;
1957
1958         err = mlx5_vector2eqn(priv->mdev, ix, &eqn, &irq);
1959         if (err)
1960                 return err;
1961
1962         c = kvzalloc_node(sizeof(*c), GFP_KERNEL, cpu_to_node(cpu));
1963         if (!c)
1964                 return -ENOMEM;
1965
1966         c->priv     = priv;
1967         c->mdev     = priv->mdev;
1968         c->tstamp   = &priv->tstamp;
1969         c->ix       = ix;
1970         c->cpu      = cpu;
1971         c->pdev     = priv->mdev->device;
1972         c->netdev   = priv->netdev;
1973         c->mkey_be  = cpu_to_be32(priv->mdev->mlx5e_res.mkey.key);
1974         c->num_tc   = params->num_tc;
1975         c->xdp      = !!params->xdp_prog;
1976         c->stats    = &priv->channel_stats[ix].ch;
1977         c->irq_desc = irq_to_desc(irq);
1978         c->lag_port = mlx5e_enumerate_lag_port(priv->mdev, ix);
1979
1980         netif_napi_add(netdev, &c->napi, mlx5e_napi_poll, 64);
1981
1982         err = mlx5e_open_queues(c, params, cparam);
1983         if (unlikely(err))
1984                 goto err_napi_del;
1985
1986         if (umem) {
1987                 mlx5e_build_xsk_param(umem, &xsk);
1988                 err = mlx5e_open_xsk(priv, params, &xsk, umem, c);
1989                 if (unlikely(err))
1990                         goto err_close_queues;
1991         }
1992
1993         *cp = c;
1994
1995         return 0;
1996
1997 err_close_queues:
1998         mlx5e_close_queues(c);
1999
2000 err_napi_del:
2001         netif_napi_del(&c->napi);
2002
2003         kvfree(c);
2004
2005         return err;
2006 }
2007
2008 static void mlx5e_activate_channel(struct mlx5e_channel *c)
2009 {
2010         int tc;
2011
2012         for (tc = 0; tc < c->num_tc; tc++)
2013                 mlx5e_activate_txqsq(&c->sq[tc]);
2014         mlx5e_activate_icosq(&c->icosq);
2015         mlx5e_activate_icosq(&c->async_icosq);
2016         mlx5e_activate_rq(&c->rq);
2017
2018         if (test_bit(MLX5E_CHANNEL_STATE_XSK, c->state))
2019                 mlx5e_activate_xsk(c);
2020 }
2021
2022 static void mlx5e_deactivate_channel(struct mlx5e_channel *c)
2023 {
2024         int tc;
2025
2026         if (test_bit(MLX5E_CHANNEL_STATE_XSK, c->state))
2027                 mlx5e_deactivate_xsk(c);
2028
2029         mlx5e_deactivate_rq(&c->rq);
2030         mlx5e_deactivate_icosq(&c->async_icosq);
2031         mlx5e_deactivate_icosq(&c->icosq);
2032         for (tc = 0; tc < c->num_tc; tc++)
2033                 mlx5e_deactivate_txqsq(&c->sq[tc]);
2034 }
2035
2036 static void mlx5e_close_channel(struct mlx5e_channel *c)
2037 {
2038         if (test_bit(MLX5E_CHANNEL_STATE_XSK, c->state))
2039                 mlx5e_close_xsk(c);
2040         mlx5e_close_queues(c);
2041         netif_napi_del(&c->napi);
2042
2043         kvfree(c);
2044 }
2045
2046 #define DEFAULT_FRAG_SIZE (2048)
2047
2048 static void mlx5e_build_rq_frags_info(struct mlx5_core_dev *mdev,
2049                                       struct mlx5e_params *params,
2050                                       struct mlx5e_xsk_param *xsk,
2051                                       struct mlx5e_rq_frags_info *info)
2052 {
2053         u32 byte_count = MLX5E_SW2HW_MTU(params, params->sw_mtu);
2054         int frag_size_max = DEFAULT_FRAG_SIZE;
2055         u32 buf_size = 0;
2056         int i;
2057
2058 #ifdef CONFIG_MLX5_EN_IPSEC
2059         if (MLX5_IPSEC_DEV(mdev))
2060                 byte_count += MLX5E_METADATA_ETHER_LEN;
2061 #endif
2062
2063         if (mlx5e_rx_is_linear_skb(params, xsk)) {
2064                 int frag_stride;
2065
2066                 frag_stride = mlx5e_rx_get_linear_frag_sz(params, xsk);
2067                 frag_stride = roundup_pow_of_two(frag_stride);
2068
2069                 info->arr[0].frag_size = byte_count;
2070                 info->arr[0].frag_stride = frag_stride;
2071                 info->num_frags = 1;
2072                 info->wqe_bulk = PAGE_SIZE / frag_stride;
2073                 goto out;
2074         }
2075
2076         if (byte_count > PAGE_SIZE +
2077             (MLX5E_MAX_RX_FRAGS - 1) * frag_size_max)
2078                 frag_size_max = PAGE_SIZE;
2079
2080         i = 0;
2081         while (buf_size < byte_count) {
2082                 int frag_size = byte_count - buf_size;
2083
2084                 if (i < MLX5E_MAX_RX_FRAGS - 1)
2085                         frag_size = min(frag_size, frag_size_max);
2086
2087                 info->arr[i].frag_size = frag_size;
2088                 info->arr[i].frag_stride = roundup_pow_of_two(frag_size);
2089
2090                 buf_size += frag_size;
2091                 i++;
2092         }
2093         info->num_frags = i;
2094         /* number of different wqes sharing a page */
2095         info->wqe_bulk = 1 + (info->num_frags % 2);
2096
2097 out:
2098         info->wqe_bulk = max_t(u8, info->wqe_bulk, 8);
2099         info->log_num_frags = order_base_2(info->num_frags);
2100 }
2101
2102 static inline u8 mlx5e_get_rqwq_log_stride(u8 wq_type, int ndsegs)
2103 {
2104         int sz = sizeof(struct mlx5_wqe_data_seg) * ndsegs;
2105
2106         switch (wq_type) {
2107         case MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ:
2108                 sz += sizeof(struct mlx5e_rx_wqe_ll);
2109                 break;
2110         default: /* MLX5_WQ_TYPE_CYCLIC */
2111                 sz += sizeof(struct mlx5e_rx_wqe_cyc);
2112         }
2113
2114         return order_base_2(sz);
2115 }
2116
2117 static u8 mlx5e_get_rq_log_wq_sz(void *rqc)
2118 {
2119         void *wq = MLX5_ADDR_OF(rqc, rqc, wq);
2120
2121         return MLX5_GET(wq, wq, log_wq_sz);
2122 }
2123
2124 void mlx5e_build_rq_param(struct mlx5e_priv *priv,
2125                           struct mlx5e_params *params,
2126                           struct mlx5e_xsk_param *xsk,
2127                           struct mlx5e_rq_param *param)
2128 {
2129         struct mlx5_core_dev *mdev = priv->mdev;
2130         void *rqc = param->rqc;
2131         void *wq = MLX5_ADDR_OF(rqc, rqc, wq);
2132         int ndsegs = 1;
2133
2134         switch (params->rq_wq_type) {
2135         case MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ:
2136                 MLX5_SET(wq, wq, log_wqe_num_of_strides,
2137                          mlx5e_mpwqe_get_log_num_strides(mdev, params, xsk) -
2138                          MLX5_MPWQE_LOG_NUM_STRIDES_BASE);
2139                 MLX5_SET(wq, wq, log_wqe_stride_size,
2140                          mlx5e_mpwqe_get_log_stride_size(mdev, params, xsk) -
2141                          MLX5_MPWQE_LOG_STRIDE_SZ_BASE);
2142                 MLX5_SET(wq, wq, log_wq_sz, mlx5e_mpwqe_get_log_rq_size(params, xsk));
2143                 break;
2144         default: /* MLX5_WQ_TYPE_CYCLIC */
2145                 MLX5_SET(wq, wq, log_wq_sz, params->log_rq_mtu_frames);
2146                 mlx5e_build_rq_frags_info(mdev, params, xsk, &param->frags_info);
2147                 ndsegs = param->frags_info.num_frags;
2148         }
2149
2150         MLX5_SET(wq, wq, wq_type,          params->rq_wq_type);
2151         MLX5_SET(wq, wq, end_padding_mode, MLX5_WQ_END_PAD_MODE_ALIGN);
2152         MLX5_SET(wq, wq, log_wq_stride,
2153                  mlx5e_get_rqwq_log_stride(params->rq_wq_type, ndsegs));
2154         MLX5_SET(wq, wq, pd,               mdev->mlx5e_res.pdn);
2155         MLX5_SET(rqc, rqc, counter_set_id, priv->q_counter);
2156         MLX5_SET(rqc, rqc, vsd,            params->vlan_strip_disable);
2157         MLX5_SET(rqc, rqc, scatter_fcs,    params->scatter_fcs_en);
2158
2159         param->wq.buf_numa_node = dev_to_node(mdev->device);
2160         mlx5e_build_rx_cq_param(priv, params, xsk, &param->cqp);
2161 }
2162
2163 static void mlx5e_build_drop_rq_param(struct mlx5e_priv *priv,
2164                                       struct mlx5e_rq_param *param)
2165 {
2166         struct mlx5_core_dev *mdev = priv->mdev;
2167         void *rqc = param->rqc;
2168         void *wq = MLX5_ADDR_OF(rqc, rqc, wq);
2169
2170         MLX5_SET(wq, wq, wq_type, MLX5_WQ_TYPE_CYCLIC);
2171         MLX5_SET(wq, wq, log_wq_stride,
2172                  mlx5e_get_rqwq_log_stride(MLX5_WQ_TYPE_CYCLIC, 1));
2173         MLX5_SET(rqc, rqc, counter_set_id, priv->drop_rq_q_counter);
2174
2175         param->wq.buf_numa_node = dev_to_node(mdev->device);
2176 }
2177
2178 void mlx5e_build_sq_param_common(struct mlx5e_priv *priv,
2179                                  struct mlx5e_sq_param *param)
2180 {
2181         void *sqc = param->sqc;
2182         void *wq = MLX5_ADDR_OF(sqc, sqc, wq);
2183
2184         MLX5_SET(wq, wq, log_wq_stride, ilog2(MLX5_SEND_WQE_BB));
2185         MLX5_SET(wq, wq, pd,            priv->mdev->mlx5e_res.pdn);
2186
2187         param->wq.buf_numa_node = dev_to_node(priv->mdev->device);
2188 }
2189
2190 static void mlx5e_build_sq_param(struct mlx5e_priv *priv,
2191                                  struct mlx5e_params *params,
2192                                  struct mlx5e_sq_param *param)
2193 {
2194         void *sqc = param->sqc;
2195         void *wq = MLX5_ADDR_OF(sqc, sqc, wq);
2196         bool allow_swp;
2197
2198         allow_swp = mlx5_geneve_tx_allowed(priv->mdev) ||
2199                     !!MLX5_IPSEC_DEV(priv->mdev);
2200         mlx5e_build_sq_param_common(priv, param);
2201         MLX5_SET(wq, wq, log_wq_sz, params->log_sq_size);
2202         MLX5_SET(sqc, sqc, allow_swp, allow_swp);
2203         mlx5e_build_tx_cq_param(priv, params, &param->cqp);
2204 }
2205
2206 static void mlx5e_build_common_cq_param(struct mlx5e_priv *priv,
2207                                         struct mlx5e_cq_param *param)
2208 {
2209         void *cqc = param->cqc;
2210
2211         MLX5_SET(cqc, cqc, uar_page, priv->mdev->priv.uar->index);
2212         if (MLX5_CAP_GEN(priv->mdev, cqe_128_always) && cache_line_size() >= 128)
2213                 MLX5_SET(cqc, cqc, cqe_sz, CQE_STRIDE_128_PAD);
2214 }
2215
2216 void mlx5e_build_rx_cq_param(struct mlx5e_priv *priv,
2217                              struct mlx5e_params *params,
2218                              struct mlx5e_xsk_param *xsk,
2219                              struct mlx5e_cq_param *param)
2220 {
2221         struct mlx5_core_dev *mdev = priv->mdev;
2222         void *cqc = param->cqc;
2223         u8 log_cq_size;
2224
2225         switch (params->rq_wq_type) {
2226         case MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ:
2227                 log_cq_size = mlx5e_mpwqe_get_log_rq_size(params, xsk) +
2228                         mlx5e_mpwqe_get_log_num_strides(mdev, params, xsk);
2229                 break;
2230         default: /* MLX5_WQ_TYPE_CYCLIC */
2231                 log_cq_size = params->log_rq_mtu_frames;
2232         }
2233
2234         MLX5_SET(cqc, cqc, log_cq_size, log_cq_size);
2235         if (MLX5E_GET_PFLAG(params, MLX5E_PFLAG_RX_CQE_COMPRESS)) {
2236                 MLX5_SET(cqc, cqc, mini_cqe_res_format, MLX5_CQE_FORMAT_CSUM);
2237                 MLX5_SET(cqc, cqc, cqe_comp_en, 1);
2238         }
2239
2240         mlx5e_build_common_cq_param(priv, param);
2241         param->cq_period_mode = params->rx_cq_moderation.cq_period_mode;
2242 }
2243
2244 void mlx5e_build_tx_cq_param(struct mlx5e_priv *priv,
2245                              struct mlx5e_params *params,
2246                              struct mlx5e_cq_param *param)
2247 {
2248         void *cqc = param->cqc;
2249
2250         MLX5_SET(cqc, cqc, log_cq_size, params->log_sq_size);
2251
2252         mlx5e_build_common_cq_param(priv, param);
2253         param->cq_period_mode = params->tx_cq_moderation.cq_period_mode;
2254 }
2255
2256 void mlx5e_build_ico_cq_param(struct mlx5e_priv *priv,
2257                               u8 log_wq_size,
2258                               struct mlx5e_cq_param *param)
2259 {
2260         void *cqc = param->cqc;
2261
2262         MLX5_SET(cqc, cqc, log_cq_size, log_wq_size);
2263
2264         mlx5e_build_common_cq_param(priv, param);
2265
2266         param->cq_period_mode = DIM_CQ_PERIOD_MODE_START_FROM_EQE;
2267 }
2268
2269 void mlx5e_build_icosq_param(struct mlx5e_priv *priv,
2270                              u8 log_wq_size,
2271                              struct mlx5e_sq_param *param)
2272 {
2273         void *sqc = param->sqc;
2274         void *wq = MLX5_ADDR_OF(sqc, sqc, wq);
2275
2276         mlx5e_build_sq_param_common(priv, param);
2277
2278         MLX5_SET(wq, wq, log_wq_sz, log_wq_size);
2279         MLX5_SET(sqc, sqc, reg_umr, MLX5_CAP_ETH(priv->mdev, reg_umr_sq));
2280         mlx5e_build_ico_cq_param(priv, log_wq_size, &param->cqp);
2281 }
2282
2283 void mlx5e_build_xdpsq_param(struct mlx5e_priv *priv,
2284                              struct mlx5e_params *params,
2285                              struct mlx5e_sq_param *param)
2286 {
2287         void *sqc = param->sqc;
2288         void *wq = MLX5_ADDR_OF(sqc, sqc, wq);
2289
2290         mlx5e_build_sq_param_common(priv, param);
2291         MLX5_SET(wq, wq, log_wq_sz, params->log_sq_size);
2292         param->is_mpw = MLX5E_GET_PFLAG(params, MLX5E_PFLAG_XDP_TX_MPWQE);
2293         mlx5e_build_tx_cq_param(priv, params, &param->cqp);
2294 }
2295
2296 static u8 mlx5e_build_icosq_log_wq_sz(struct mlx5e_params *params,
2297                                       struct mlx5e_rq_param *rqp)
2298 {
2299         switch (params->rq_wq_type) {
2300         case MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ:
2301                 return order_base_2(MLX5E_UMR_WQEBBS) +
2302                         mlx5e_get_rq_log_wq_sz(rqp->rqc);
2303         default: /* MLX5_WQ_TYPE_CYCLIC */
2304                 return MLX5E_PARAMS_MINIMUM_LOG_SQ_SIZE;
2305         }
2306 }
2307
2308 static void mlx5e_build_channel_param(struct mlx5e_priv *priv,
2309                                       struct mlx5e_params *params,
2310                                       struct mlx5e_channel_param *cparam)
2311 {
2312         u8 icosq_log_wq_sz, async_icosq_log_wq_sz;
2313
2314         mlx5e_build_rq_param(priv, params, NULL, &cparam->rq);
2315
2316         icosq_log_wq_sz = mlx5e_build_icosq_log_wq_sz(params, &cparam->rq);
2317         async_icosq_log_wq_sz = MLX5E_PARAMS_MINIMUM_LOG_SQ_SIZE;
2318
2319         mlx5e_build_sq_param(priv, params, &cparam->txq_sq);
2320         mlx5e_build_xdpsq_param(priv, params, &cparam->xdp_sq);
2321         mlx5e_build_icosq_param(priv, icosq_log_wq_sz, &cparam->icosq);
2322         mlx5e_build_icosq_param(priv, async_icosq_log_wq_sz, &cparam->async_icosq);
2323 }
2324
2325 int mlx5e_open_channels(struct mlx5e_priv *priv,
2326                         struct mlx5e_channels *chs)
2327 {
2328         struct mlx5e_channel_param *cparam;
2329         int err = -ENOMEM;
2330         int i;
2331
2332         chs->num = chs->params.num_channels;
2333
2334         chs->c = kcalloc(chs->num, sizeof(struct mlx5e_channel *), GFP_KERNEL);
2335         cparam = kvzalloc(sizeof(struct mlx5e_channel_param), GFP_KERNEL);
2336         if (!chs->c || !cparam)
2337                 goto err_free;
2338
2339         mlx5e_build_channel_param(priv, &chs->params, cparam);
2340         for (i = 0; i < chs->num; i++) {
2341                 struct xdp_umem *umem = NULL;
2342
2343                 if (chs->params.xdp_prog)
2344                         umem = mlx5e_xsk_get_umem(&chs->params, chs->params.xsk, i);
2345
2346                 err = mlx5e_open_channel(priv, i, &chs->params, cparam, umem, &chs->c[i]);
2347                 if (err)
2348                         goto err_close_channels;
2349         }
2350
2351         mlx5e_health_channels_update(priv);
2352         kvfree(cparam);
2353         return 0;
2354
2355 err_close_channels:
2356         for (i--; i >= 0; i--)
2357                 mlx5e_close_channel(chs->c[i]);
2358
2359 err_free:
2360         kfree(chs->c);
2361         kvfree(cparam);
2362         chs->num = 0;
2363         return err;
2364 }
2365
2366 static void mlx5e_activate_channels(struct mlx5e_channels *chs)
2367 {
2368         int i;
2369
2370         for (i = 0; i < chs->num; i++)
2371                 mlx5e_activate_channel(chs->c[i]);
2372 }
2373
2374 #define MLX5E_RQ_WQES_TIMEOUT 20000 /* msecs */
2375
2376 static int mlx5e_wait_channels_min_rx_wqes(struct mlx5e_channels *chs)
2377 {
2378         int err = 0;
2379         int i;
2380
2381         for (i = 0; i < chs->num; i++) {
2382                 int timeout = err ? 0 : MLX5E_RQ_WQES_TIMEOUT;
2383
2384                 err |= mlx5e_wait_for_min_rx_wqes(&chs->c[i]->rq, timeout);
2385
2386                 /* Don't wait on the XSK RQ, because the newer xdpsock sample
2387                  * doesn't provide any Fill Ring entries at the setup stage.
2388                  */
2389         }
2390
2391         return err ? -ETIMEDOUT : 0;
2392 }
2393
2394 static void mlx5e_deactivate_channels(struct mlx5e_channels *chs)
2395 {
2396         int i;
2397
2398         for (i = 0; i < chs->num; i++)
2399                 mlx5e_deactivate_channel(chs->c[i]);
2400 }
2401
2402 void mlx5e_close_channels(struct mlx5e_channels *chs)
2403 {
2404         int i;
2405
2406         for (i = 0; i < chs->num; i++)
2407                 mlx5e_close_channel(chs->c[i]);
2408
2409         kfree(chs->c);
2410         chs->num = 0;
2411 }
2412
2413 static int
2414 mlx5e_create_rqt(struct mlx5e_priv *priv, int sz, struct mlx5e_rqt *rqt)
2415 {
2416         struct mlx5_core_dev *mdev = priv->mdev;
2417         void *rqtc;
2418         int inlen;
2419         int err;
2420         u32 *in;
2421         int i;
2422
2423         inlen = MLX5_ST_SZ_BYTES(create_rqt_in) + sizeof(u32) * sz;
2424         in = kvzalloc(inlen, GFP_KERNEL);
2425         if (!in)
2426                 return -ENOMEM;
2427
2428         rqtc = MLX5_ADDR_OF(create_rqt_in, in, rqt_context);
2429
2430         MLX5_SET(rqtc, rqtc, rqt_actual_size, sz);
2431         MLX5_SET(rqtc, rqtc, rqt_max_size, sz);
2432
2433         for (i = 0; i < sz; i++)
2434                 MLX5_SET(rqtc, rqtc, rq_num[i], priv->drop_rq.rqn);
2435
2436         err = mlx5_core_create_rqt(mdev, in, inlen, &rqt->rqtn);
2437         if (!err)
2438                 rqt->enabled = true;
2439
2440         kvfree(in);
2441         return err;
2442 }
2443
2444 void mlx5e_destroy_rqt(struct mlx5e_priv *priv, struct mlx5e_rqt *rqt)
2445 {
2446         rqt->enabled = false;
2447         mlx5_core_destroy_rqt(priv->mdev, rqt->rqtn);
2448 }
2449
2450 int mlx5e_create_indirect_rqt(struct mlx5e_priv *priv)
2451 {
2452         struct mlx5e_rqt *rqt = &priv->indir_rqt;
2453         int err;
2454
2455         err = mlx5e_create_rqt(priv, MLX5E_INDIR_RQT_SIZE, rqt);
2456         if (err)
2457                 mlx5_core_warn(priv->mdev, "create indirect rqts failed, %d\n", err);
2458         return err;
2459 }
2460
2461 int mlx5e_create_direct_rqts(struct mlx5e_priv *priv, struct mlx5e_tir *tirs)
2462 {
2463         int err;
2464         int ix;
2465
2466         for (ix = 0; ix < priv->max_nch; ix++) {
2467                 err = mlx5e_create_rqt(priv, 1 /*size */, &tirs[ix].rqt);
2468                 if (unlikely(err))
2469                         goto err_destroy_rqts;
2470         }
2471
2472         return 0;
2473
2474 err_destroy_rqts:
2475         mlx5_core_warn(priv->mdev, "create rqts failed, %d\n", err);
2476         for (ix--; ix >= 0; ix--)
2477                 mlx5e_destroy_rqt(priv, &tirs[ix].rqt);
2478
2479         return err;
2480 }
2481
2482 void mlx5e_destroy_direct_rqts(struct mlx5e_priv *priv, struct mlx5e_tir *tirs)
2483 {
2484         int i;
2485
2486         for (i = 0; i < priv->max_nch; i++)
2487                 mlx5e_destroy_rqt(priv, &tirs[i].rqt);
2488 }
2489
2490 static int mlx5e_rx_hash_fn(int hfunc)
2491 {
2492         return (hfunc == ETH_RSS_HASH_TOP) ?
2493                MLX5_RX_HASH_FN_TOEPLITZ :
2494                MLX5_RX_HASH_FN_INVERTED_XOR8;
2495 }
2496
2497 int mlx5e_bits_invert(unsigned long a, int size)
2498 {
2499         int inv = 0;
2500         int i;
2501
2502         for (i = 0; i < size; i++)
2503                 inv |= (test_bit(size - i - 1, &a) ? 1 : 0) << i;
2504
2505         return inv;
2506 }
2507
2508 static void mlx5e_fill_rqt_rqns(struct mlx5e_priv *priv, int sz,
2509                                 struct mlx5e_redirect_rqt_param rrp, void *rqtc)
2510 {
2511         int i;
2512
2513         for (i = 0; i < sz; i++) {
2514                 u32 rqn;
2515
2516                 if (rrp.is_rss) {
2517                         int ix = i;
2518
2519                         if (rrp.rss.hfunc == ETH_RSS_HASH_XOR)
2520                                 ix = mlx5e_bits_invert(i, ilog2(sz));
2521
2522                         ix = priv->rss_params.indirection_rqt[ix];
2523                         rqn = rrp.rss.channels->c[ix]->rq.rqn;
2524                 } else {
2525                         rqn = rrp.rqn;
2526                 }
2527                 MLX5_SET(rqtc, rqtc, rq_num[i], rqn);
2528         }
2529 }
2530
2531 int mlx5e_redirect_rqt(struct mlx5e_priv *priv, u32 rqtn, int sz,
2532                        struct mlx5e_redirect_rqt_param rrp)
2533 {
2534         struct mlx5_core_dev *mdev = priv->mdev;
2535         void *rqtc;
2536         int inlen;
2537         u32 *in;
2538         int err;
2539
2540         inlen = MLX5_ST_SZ_BYTES(modify_rqt_in) + sizeof(u32) * sz;
2541         in = kvzalloc(inlen, GFP_KERNEL);
2542         if (!in)
2543                 return -ENOMEM;
2544
2545         rqtc = MLX5_ADDR_OF(modify_rqt_in, in, ctx);
2546
2547         MLX5_SET(rqtc, rqtc, rqt_actual_size, sz);
2548         MLX5_SET(modify_rqt_in, in, bitmask.rqn_list, 1);
2549         mlx5e_fill_rqt_rqns(priv, sz, rrp, rqtc);
2550         err = mlx5_core_modify_rqt(mdev, rqtn, in, inlen);
2551
2552         kvfree(in);
2553         return err;
2554 }
2555
2556 static u32 mlx5e_get_direct_rqn(struct mlx5e_priv *priv, int ix,
2557                                 struct mlx5e_redirect_rqt_param rrp)
2558 {
2559         if (!rrp.is_rss)
2560                 return rrp.rqn;
2561
2562         if (ix >= rrp.rss.channels->num)
2563                 return priv->drop_rq.rqn;
2564
2565         return rrp.rss.channels->c[ix]->rq.rqn;
2566 }
2567
2568 static void mlx5e_redirect_rqts(struct mlx5e_priv *priv,
2569                                 struct mlx5e_redirect_rqt_param rrp)
2570 {
2571         u32 rqtn;
2572         int ix;
2573
2574         if (priv->indir_rqt.enabled) {
2575                 /* RSS RQ table */
2576                 rqtn = priv->indir_rqt.rqtn;
2577                 mlx5e_redirect_rqt(priv, rqtn, MLX5E_INDIR_RQT_SIZE, rrp);
2578         }
2579
2580         for (ix = 0; ix < priv->max_nch; ix++) {
2581                 struct mlx5e_redirect_rqt_param direct_rrp = {
2582                         .is_rss = false,
2583                         {
2584                                 .rqn    = mlx5e_get_direct_rqn(priv, ix, rrp)
2585                         },
2586                 };
2587
2588                 /* Direct RQ Tables */
2589                 if (!priv->direct_tir[ix].rqt.enabled)
2590                         continue;
2591
2592                 rqtn = priv->direct_tir[ix].rqt.rqtn;
2593                 mlx5e_redirect_rqt(priv, rqtn, 1, direct_rrp);
2594         }
2595 }
2596
2597 static void mlx5e_redirect_rqts_to_channels(struct mlx5e_priv *priv,
2598                                             struct mlx5e_channels *chs)
2599 {
2600         struct mlx5e_redirect_rqt_param rrp = {
2601                 .is_rss        = true,
2602                 {
2603                         .rss = {
2604                                 .channels  = chs,
2605                                 .hfunc     = priv->rss_params.hfunc,
2606                         }
2607                 },
2608         };
2609
2610         mlx5e_redirect_rqts(priv, rrp);
2611 }
2612
2613 static void mlx5e_redirect_rqts_to_drop(struct mlx5e_priv *priv)
2614 {
2615         struct mlx5e_redirect_rqt_param drop_rrp = {
2616                 .is_rss = false,
2617                 {
2618                         .rqn = priv->drop_rq.rqn,
2619                 },
2620         };
2621
2622         mlx5e_redirect_rqts(priv, drop_rrp);
2623 }
2624
2625 static const struct mlx5e_tirc_config tirc_default_config[MLX5E_NUM_INDIR_TIRS] = {
2626         [MLX5E_TT_IPV4_TCP] = { .l3_prot_type = MLX5_L3_PROT_TYPE_IPV4,
2627                                 .l4_prot_type = MLX5_L4_PROT_TYPE_TCP,
2628                                 .rx_hash_fields = MLX5_HASH_IP_L4PORTS,
2629         },
2630         [MLX5E_TT_IPV6_TCP] = { .l3_prot_type = MLX5_L3_PROT_TYPE_IPV6,
2631                                 .l4_prot_type = MLX5_L4_PROT_TYPE_TCP,
2632                                 .rx_hash_fields = MLX5_HASH_IP_L4PORTS,
2633         },
2634         [MLX5E_TT_IPV4_UDP] = { .l3_prot_type = MLX5_L3_PROT_TYPE_IPV4,
2635                                 .l4_prot_type = MLX5_L4_PROT_TYPE_UDP,
2636                                 .rx_hash_fields = MLX5_HASH_IP_L4PORTS,
2637         },
2638         [MLX5E_TT_IPV6_UDP] = { .l3_prot_type = MLX5_L3_PROT_TYPE_IPV6,
2639                                 .l4_prot_type = MLX5_L4_PROT_TYPE_UDP,
2640                                 .rx_hash_fields = MLX5_HASH_IP_L4PORTS,
2641         },
2642         [MLX5E_TT_IPV4_IPSEC_AH] = { .l3_prot_type = MLX5_L3_PROT_TYPE_IPV4,
2643                                      .l4_prot_type = 0,
2644                                      .rx_hash_fields = MLX5_HASH_IP_IPSEC_SPI,
2645         },
2646         [MLX5E_TT_IPV6_IPSEC_AH] = { .l3_prot_type = MLX5_L3_PROT_TYPE_IPV6,
2647                                      .l4_prot_type = 0,
2648                                      .rx_hash_fields = MLX5_HASH_IP_IPSEC_SPI,
2649         },
2650         [MLX5E_TT_IPV4_IPSEC_ESP] = { .l3_prot_type = MLX5_L3_PROT_TYPE_IPV4,
2651                                       .l4_prot_type = 0,
2652                                       .rx_hash_fields = MLX5_HASH_IP_IPSEC_SPI,
2653         },
2654         [MLX5E_TT_IPV6_IPSEC_ESP] = { .l3_prot_type = MLX5_L3_PROT_TYPE_IPV6,
2655                                       .l4_prot_type = 0,
2656                                       .rx_hash_fields = MLX5_HASH_IP_IPSEC_SPI,
2657         },
2658         [MLX5E_TT_IPV4] = { .l3_prot_type = MLX5_L3_PROT_TYPE_IPV4,
2659                             .l4_prot_type = 0,
2660                             .rx_hash_fields = MLX5_HASH_IP,
2661         },
2662         [MLX5E_TT_IPV6] = { .l3_prot_type = MLX5_L3_PROT_TYPE_IPV6,
2663                             .l4_prot_type = 0,
2664                             .rx_hash_fields = MLX5_HASH_IP,
2665         },
2666 };
2667
2668 struct mlx5e_tirc_config mlx5e_tirc_get_default_config(enum mlx5e_traffic_types tt)
2669 {
2670         return tirc_default_config[tt];
2671 }
2672
2673 static void mlx5e_build_tir_ctx_lro(struct mlx5e_params *params, void *tirc)
2674 {
2675         if (!params->lro_en)
2676                 return;
2677
2678 #define ROUGH_MAX_L2_L3_HDR_SZ 256
2679
2680         MLX5_SET(tirc, tirc, lro_enable_mask,
2681                  MLX5_TIRC_LRO_ENABLE_MASK_IPV4_LRO |
2682                  MLX5_TIRC_LRO_ENABLE_MASK_IPV6_LRO);
2683         MLX5_SET(tirc, tirc, lro_max_ip_payload_size,
2684                  (MLX5E_PARAMS_DEFAULT_LRO_WQE_SZ - ROUGH_MAX_L2_L3_HDR_SZ) >> 8);
2685         MLX5_SET(tirc, tirc, lro_timeout_period_usecs, params->lro_timeout);
2686 }
2687
2688 void mlx5e_build_indir_tir_ctx_hash(struct mlx5e_rss_params *rss_params,
2689                                     const struct mlx5e_tirc_config *ttconfig,
2690                                     void *tirc, bool inner)
2691 {
2692         void *hfso = inner ? MLX5_ADDR_OF(tirc, tirc, rx_hash_field_selector_inner) :
2693                              MLX5_ADDR_OF(tirc, tirc, rx_hash_field_selector_outer);
2694
2695         MLX5_SET(tirc, tirc, rx_hash_fn, mlx5e_rx_hash_fn(rss_params->hfunc));
2696         if (rss_params->hfunc == ETH_RSS_HASH_TOP) {
2697                 void *rss_key = MLX5_ADDR_OF(tirc, tirc,
2698                                              rx_hash_toeplitz_key);
2699                 size_t len = MLX5_FLD_SZ_BYTES(tirc,
2700                                                rx_hash_toeplitz_key);
2701
2702                 MLX5_SET(tirc, tirc, rx_hash_symmetric, 1);
2703                 memcpy(rss_key, rss_params->toeplitz_hash_key, len);
2704         }
2705         MLX5_SET(rx_hash_field_select, hfso, l3_prot_type,
2706                  ttconfig->l3_prot_type);
2707         MLX5_SET(rx_hash_field_select, hfso, l4_prot_type,
2708                  ttconfig->l4_prot_type);
2709         MLX5_SET(rx_hash_field_select, hfso, selected_fields,
2710                  ttconfig->rx_hash_fields);
2711 }
2712
2713 static void mlx5e_update_rx_hash_fields(struct mlx5e_tirc_config *ttconfig,
2714                                         enum mlx5e_traffic_types tt,
2715                                         u32 rx_hash_fields)
2716 {
2717         *ttconfig                = tirc_default_config[tt];
2718         ttconfig->rx_hash_fields = rx_hash_fields;
2719 }
2720
2721 void mlx5e_modify_tirs_hash(struct mlx5e_priv *priv, void *in)
2722 {
2723         void *tirc = MLX5_ADDR_OF(modify_tir_in, in, ctx);
2724         struct mlx5e_rss_params *rss = &priv->rss_params;
2725         struct mlx5_core_dev *mdev = priv->mdev;
2726         int ctxlen = MLX5_ST_SZ_BYTES(tirc);
2727         struct mlx5e_tirc_config ttconfig;
2728         int tt;
2729
2730         MLX5_SET(modify_tir_in, in, bitmask.hash, 1);
2731
2732         for (tt = 0; tt < MLX5E_NUM_INDIR_TIRS; tt++) {
2733                 memset(tirc, 0, ctxlen);
2734                 mlx5e_update_rx_hash_fields(&ttconfig, tt,
2735                                             rss->rx_hash_fields[tt]);
2736                 mlx5e_build_indir_tir_ctx_hash(rss, &ttconfig, tirc, false);
2737                 mlx5_core_modify_tir(mdev, priv->indir_tir[tt].tirn, in);
2738         }
2739
2740         /* Verify inner tirs resources allocated */
2741         if (!priv->inner_indir_tir[0].tirn)
2742                 return;
2743
2744         for (tt = 0; tt < MLX5E_NUM_INDIR_TIRS; tt++) {
2745                 memset(tirc, 0, ctxlen);
2746                 mlx5e_update_rx_hash_fields(&ttconfig, tt,
2747                                             rss->rx_hash_fields[tt]);
2748                 mlx5e_build_indir_tir_ctx_hash(rss, &ttconfig, tirc, true);
2749                 mlx5_core_modify_tir(mdev, priv->inner_indir_tir[tt].tirn, in);
2750         }
2751 }
2752
2753 static int mlx5e_modify_tirs_lro(struct mlx5e_priv *priv)
2754 {
2755         struct mlx5_core_dev *mdev = priv->mdev;
2756
2757         void *in;
2758         void *tirc;
2759         int inlen;
2760         int err;
2761         int tt;
2762         int ix;
2763
2764         inlen = MLX5_ST_SZ_BYTES(modify_tir_in);
2765         in = kvzalloc(inlen, GFP_KERNEL);
2766         if (!in)
2767                 return -ENOMEM;
2768
2769         MLX5_SET(modify_tir_in, in, bitmask.lro, 1);
2770         tirc = MLX5_ADDR_OF(modify_tir_in, in, ctx);
2771
2772         mlx5e_build_tir_ctx_lro(&priv->channels.params, tirc);
2773
2774         for (tt = 0; tt < MLX5E_NUM_INDIR_TIRS; tt++) {
2775                 err = mlx5_core_modify_tir(mdev, priv->indir_tir[tt].tirn, in);
2776                 if (err)
2777                         goto free_in;
2778         }
2779
2780         for (ix = 0; ix < priv->max_nch; ix++) {
2781                 err = mlx5_core_modify_tir(mdev, priv->direct_tir[ix].tirn, in);
2782                 if (err)
2783                         goto free_in;
2784         }
2785
2786 free_in:
2787         kvfree(in);
2788
2789         return err;
2790 }
2791
2792 static MLX5E_DEFINE_PREACTIVATE_WRAPPER_CTX(mlx5e_modify_tirs_lro);
2793
2794 static int mlx5e_set_mtu(struct mlx5_core_dev *mdev,
2795                          struct mlx5e_params *params, u16 mtu)
2796 {
2797         u16 hw_mtu = MLX5E_SW2HW_MTU(params, mtu);
2798         int err;
2799
2800         err = mlx5_set_port_mtu(mdev, hw_mtu, 1);
2801         if (err)
2802                 return err;
2803
2804         /* Update vport context MTU */
2805         mlx5_modify_nic_vport_mtu(mdev, hw_mtu);
2806         return 0;
2807 }
2808
2809 static void mlx5e_query_mtu(struct mlx5_core_dev *mdev,
2810                             struct mlx5e_params *params, u16 *mtu)
2811 {
2812         u16 hw_mtu = 0;
2813         int err;
2814
2815         err = mlx5_query_nic_vport_mtu(mdev, &hw_mtu);
2816         if (err || !hw_mtu) /* fallback to port oper mtu */
2817                 mlx5_query_port_oper_mtu(mdev, &hw_mtu, 1);
2818
2819         *mtu = MLX5E_HW2SW_MTU(params, hw_mtu);
2820 }
2821
2822 int mlx5e_set_dev_port_mtu(struct mlx5e_priv *priv)
2823 {
2824         struct mlx5e_params *params = &priv->channels.params;
2825         struct net_device *netdev = priv->netdev;
2826         struct mlx5_core_dev *mdev = priv->mdev;
2827         u16 mtu;
2828         int err;
2829
2830         err = mlx5e_set_mtu(mdev, params, params->sw_mtu);
2831         if (err)
2832                 return err;
2833
2834         mlx5e_query_mtu(mdev, params, &mtu);
2835         if (mtu != params->sw_mtu)
2836                 netdev_warn(netdev, "%s: VPort MTU %d is different than netdev mtu %d\n",
2837                             __func__, mtu, params->sw_mtu);
2838
2839         params->sw_mtu = mtu;
2840         return 0;
2841 }
2842
2843 MLX5E_DEFINE_PREACTIVATE_WRAPPER_CTX(mlx5e_set_dev_port_mtu);
2844
2845 void mlx5e_set_netdev_mtu_boundaries(struct mlx5e_priv *priv)
2846 {
2847         struct mlx5e_params *params = &priv->channels.params;
2848         struct net_device *netdev   = priv->netdev;
2849         struct mlx5_core_dev *mdev  = priv->mdev;
2850         u16 max_mtu;
2851
2852         /* MTU range: 68 - hw-specific max */
2853         netdev->min_mtu = ETH_MIN_MTU;
2854
2855         mlx5_query_port_max_mtu(mdev, &max_mtu, 1);
2856         netdev->max_mtu = min_t(unsigned int, MLX5E_HW2SW_MTU(params, max_mtu),
2857                                 ETH_MAX_MTU);
2858 }
2859
2860 static void mlx5e_netdev_set_tcs(struct net_device *netdev, u16 nch, u8 ntc)
2861 {
2862         int tc;
2863
2864         netdev_reset_tc(netdev);
2865
2866         if (ntc == 1)
2867                 return;
2868
2869         netdev_set_num_tc(netdev, ntc);
2870
2871         /* Map netdev TCs to offset 0
2872          * We have our own UP to TXQ mapping for QoS
2873          */
2874         for (tc = 0; tc < ntc; tc++)
2875                 netdev_set_tc_queue(netdev, tc, nch, 0);
2876 }
2877
2878 static int mlx5e_update_netdev_queues(struct mlx5e_priv *priv)
2879 {
2880         struct net_device *netdev = priv->netdev;
2881         int num_txqs, num_rxqs, nch, ntc;
2882         int old_num_txqs, old_ntc;
2883         int err;
2884
2885         old_num_txqs = netdev->real_num_tx_queues;
2886         old_ntc = netdev->num_tc;
2887
2888         nch = priv->channels.params.num_channels;
2889         ntc = priv->channels.params.num_tc;
2890         num_txqs = nch * ntc;
2891         num_rxqs = nch * priv->profile->rq_groups;
2892
2893         mlx5e_netdev_set_tcs(netdev, nch, ntc);
2894
2895         err = netif_set_real_num_tx_queues(netdev, num_txqs);
2896         if (err) {
2897                 netdev_warn(netdev, "netif_set_real_num_tx_queues failed, %d\n", err);
2898                 goto err_tcs;
2899         }
2900         err = netif_set_real_num_rx_queues(netdev, num_rxqs);
2901         if (err) {
2902                 netdev_warn(netdev, "netif_set_real_num_rx_queues failed, %d\n", err);
2903                 goto err_txqs;
2904         }
2905
2906         return 0;
2907
2908 err_txqs:
2909         /* netif_set_real_num_rx_queues could fail only when nch increased. Only
2910          * one of nch and ntc is changed in this function. That means, the call
2911          * to netif_set_real_num_tx_queues below should not fail, because it
2912          * decreases the number of TX queues.
2913          */
2914         WARN_ON_ONCE(netif_set_real_num_tx_queues(netdev, old_num_txqs));
2915
2916 err_tcs:
2917         mlx5e_netdev_set_tcs(netdev, old_num_txqs / old_ntc, old_ntc);
2918         return err;
2919 }
2920
2921 static void mlx5e_set_default_xps_cpumasks(struct mlx5e_priv *priv,
2922                                            struct mlx5e_params *params)
2923 {
2924         struct mlx5_core_dev *mdev = priv->mdev;
2925         int num_comp_vectors, ix, irq;
2926
2927         num_comp_vectors = mlx5_comp_vectors_count(mdev);
2928
2929         for (ix = 0; ix < params->num_channels; ix++) {
2930                 cpumask_clear(priv->scratchpad.cpumask);
2931
2932                 for (irq = ix; irq < num_comp_vectors; irq += params->num_channels) {
2933                         int cpu = cpumask_first(mlx5_comp_irq_get_affinity_mask(mdev, irq));
2934
2935                         cpumask_set_cpu(cpu, priv->scratchpad.cpumask);
2936                 }
2937
2938                 netif_set_xps_queue(priv->netdev, priv->scratchpad.cpumask, ix);
2939         }
2940 }
2941
2942 int mlx5e_num_channels_changed(struct mlx5e_priv *priv)
2943 {
2944         u16 count = priv->channels.params.num_channels;
2945         int err;
2946
2947         err = mlx5e_update_netdev_queues(priv);
2948         if (err)
2949                 return err;
2950
2951         mlx5e_set_default_xps_cpumasks(priv, &priv->channels.params);
2952
2953         if (!netif_is_rxfh_configured(priv->netdev))
2954                 mlx5e_build_default_indir_rqt(priv->rss_params.indirection_rqt,
2955                                               MLX5E_INDIR_RQT_SIZE, count);
2956
2957         return 0;
2958 }
2959
2960 MLX5E_DEFINE_PREACTIVATE_WRAPPER_CTX(mlx5e_num_channels_changed);
2961
2962 static void mlx5e_build_txq_maps(struct mlx5e_priv *priv)
2963 {
2964         int i, ch;
2965
2966         ch = priv->channels.num;
2967
2968         for (i = 0; i < ch; i++) {
2969                 int tc;
2970
2971                 for (tc = 0; tc < priv->channels.params.num_tc; tc++) {
2972                         struct mlx5e_channel *c = priv->channels.c[i];
2973                         struct mlx5e_txqsq *sq = &c->sq[tc];
2974
2975                         priv->txq2sq[sq->txq_ix] = sq;
2976                         priv->channel_tc2realtxq[i][tc] = i + tc * ch;
2977                 }
2978         }
2979 }
2980
2981 void mlx5e_activate_priv_channels(struct mlx5e_priv *priv)
2982 {
2983         mlx5e_build_txq_maps(priv);
2984         mlx5e_activate_channels(&priv->channels);
2985         mlx5e_xdp_tx_enable(priv);
2986         netif_tx_start_all_queues(priv->netdev);
2987
2988         if (mlx5e_is_vport_rep(priv))
2989                 mlx5e_add_sqs_fwd_rules(priv);
2990
2991         mlx5e_wait_channels_min_rx_wqes(&priv->channels);
2992         mlx5e_redirect_rqts_to_channels(priv, &priv->channels);
2993
2994         mlx5e_xsk_redirect_rqts_to_channels(priv, &priv->channels);
2995 }
2996
2997 void mlx5e_deactivate_priv_channels(struct mlx5e_priv *priv)
2998 {
2999         mlx5e_xsk_redirect_rqts_to_drop(priv, &priv->channels);
3000
3001         mlx5e_redirect_rqts_to_drop(priv);
3002
3003         if (mlx5e_is_vport_rep(priv))
3004                 mlx5e_remove_sqs_fwd_rules(priv);
3005
3006         /* FIXME: This is a W/A only for tx timeout watch dog false alarm when
3007          * polling for inactive tx queues.
3008          */
3009         netif_tx_stop_all_queues(priv->netdev);
3010         netif_tx_disable(priv->netdev);
3011         mlx5e_xdp_tx_disable(priv);
3012         mlx5e_deactivate_channels(&priv->channels);
3013 }
3014
3015 static int mlx5e_switch_priv_channels(struct mlx5e_priv *priv,
3016                                       struct mlx5e_channels *new_chs,
3017                                       mlx5e_fp_preactivate preactivate,
3018                                       void *context)
3019 {
3020         struct net_device *netdev = priv->netdev;
3021         struct mlx5e_channels old_chs;
3022         int carrier_ok;
3023         int err = 0;
3024
3025         carrier_ok = netif_carrier_ok(netdev);
3026         netif_carrier_off(netdev);
3027
3028         mlx5e_deactivate_priv_channels(priv);
3029
3030         old_chs = priv->channels;
3031         priv->channels = *new_chs;
3032
3033         /* New channels are ready to roll, call the preactivate hook if needed
3034          * to modify HW settings or update kernel parameters.
3035          */
3036         if (preactivate) {
3037                 err = preactivate(priv, context);
3038                 if (err) {
3039                         priv->channels = old_chs;
3040                         goto out;
3041                 }
3042         }
3043
3044         mlx5e_close_channels(&old_chs);
3045         priv->profile->update_rx(priv);
3046
3047 out:
3048         mlx5e_activate_priv_channels(priv);
3049
3050         /* return carrier back if needed */
3051         if (carrier_ok)
3052                 netif_carrier_on(netdev);
3053
3054         return err;
3055 }
3056
3057 int mlx5e_safe_switch_channels(struct mlx5e_priv *priv,
3058                                struct mlx5e_channels *new_chs,
3059                                mlx5e_fp_preactivate preactivate,
3060                                void *context)
3061 {
3062         int err;
3063
3064         err = mlx5e_open_channels(priv, new_chs);
3065         if (err)
3066                 return err;
3067
3068         err = mlx5e_switch_priv_channels(priv, new_chs, preactivate, context);
3069         if (err)
3070                 goto err_close;
3071
3072         return 0;
3073
3074 err_close:
3075         mlx5e_close_channels(new_chs);
3076
3077         return err;
3078 }
3079
3080 int mlx5e_safe_reopen_channels(struct mlx5e_priv *priv)
3081 {
3082         struct mlx5e_channels new_channels = {};
3083
3084         new_channels.params = priv->channels.params;
3085         return mlx5e_safe_switch_channels(priv, &new_channels, NULL, NULL);
3086 }
3087
3088 void mlx5e_timestamp_init(struct mlx5e_priv *priv)
3089 {
3090         priv->tstamp.tx_type   = HWTSTAMP_TX_OFF;
3091         priv->tstamp.rx_filter = HWTSTAMP_FILTER_NONE;
3092 }
3093
3094 int mlx5e_open_locked(struct net_device *netdev)
3095 {
3096         struct mlx5e_priv *priv = netdev_priv(netdev);
3097         int err;
3098
3099         set_bit(MLX5E_STATE_OPENED, &priv->state);
3100
3101         err = mlx5e_open_channels(priv, &priv->channels);
3102         if (err)
3103                 goto err_clear_state_opened_flag;
3104
3105         priv->profile->update_rx(priv);
3106         mlx5e_activate_priv_channels(priv);
3107         if (priv->profile->update_carrier)
3108                 priv->profile->update_carrier(priv);
3109
3110         mlx5e_queue_update_stats(priv);
3111         return 0;
3112
3113 err_clear_state_opened_flag:
3114         clear_bit(MLX5E_STATE_OPENED, &priv->state);
3115         return err;
3116 }
3117
3118 int mlx5e_open(struct net_device *netdev)
3119 {
3120         struct mlx5e_priv *priv = netdev_priv(netdev);
3121         int err;
3122
3123         mutex_lock(&priv->state_lock);
3124         err = mlx5e_open_locked(netdev);
3125         if (!err)
3126                 mlx5_set_port_admin_status(priv->mdev, MLX5_PORT_UP);
3127         mutex_unlock(&priv->state_lock);
3128
3129         if (mlx5_vxlan_allowed(priv->mdev->vxlan))
3130                 udp_tunnel_get_rx_info(netdev);
3131
3132         return err;
3133 }
3134
3135 int mlx5e_close_locked(struct net_device *netdev)
3136 {
3137         struct mlx5e_priv *priv = netdev_priv(netdev);
3138
3139         /* May already be CLOSED in case a previous configuration operation
3140          * (e.g RX/TX queue size change) that involves close&open failed.
3141          */
3142         if (!test_bit(MLX5E_STATE_OPENED, &priv->state))
3143                 return 0;
3144
3145         clear_bit(MLX5E_STATE_OPENED, &priv->state);
3146
3147         netif_carrier_off(priv->netdev);
3148         mlx5e_deactivate_priv_channels(priv);
3149         mlx5e_close_channels(&priv->channels);
3150
3151         return 0;
3152 }
3153
3154 int mlx5e_close(struct net_device *netdev)
3155 {
3156         struct mlx5e_priv *priv = netdev_priv(netdev);
3157         int err;
3158
3159         if (!netif_device_present(netdev))
3160                 return -ENODEV;
3161
3162         mutex_lock(&priv->state_lock);
3163         mlx5_set_port_admin_status(priv->mdev, MLX5_PORT_DOWN);
3164         err = mlx5e_close_locked(netdev);
3165         mutex_unlock(&priv->state_lock);
3166
3167         return err;
3168 }
3169
3170 static int mlx5e_alloc_drop_rq(struct mlx5_core_dev *mdev,
3171                                struct mlx5e_rq *rq,
3172                                struct mlx5e_rq_param *param)
3173 {
3174         void *rqc = param->rqc;
3175         void *rqc_wq = MLX5_ADDR_OF(rqc, rqc, wq);
3176         int err;
3177
3178         param->wq.db_numa_node = param->wq.buf_numa_node;
3179
3180         err = mlx5_wq_cyc_create(mdev, &param->wq, rqc_wq, &rq->wqe.wq,
3181                                  &rq->wq_ctrl);
3182         if (err)
3183                 return err;
3184
3185         /* Mark as unused given "Drop-RQ" packets never reach XDP */
3186         xdp_rxq_info_unused(&rq->xdp_rxq);
3187
3188         rq->mdev = mdev;
3189
3190         return 0;
3191 }
3192
3193 static int mlx5e_alloc_drop_cq(struct mlx5_core_dev *mdev,
3194                                struct mlx5e_cq *cq,
3195                                struct mlx5e_cq_param *param)
3196 {
3197         param->wq.buf_numa_node = dev_to_node(mdev->device);
3198         param->wq.db_numa_node  = dev_to_node(mdev->device);
3199
3200         return mlx5e_alloc_cq_common(mdev, param, cq);
3201 }
3202
3203 int mlx5e_open_drop_rq(struct mlx5e_priv *priv,
3204                        struct mlx5e_rq *drop_rq)
3205 {
3206         struct mlx5_core_dev *mdev = priv->mdev;
3207         struct mlx5e_cq_param cq_param = {};
3208         struct mlx5e_rq_param rq_param = {};
3209         struct mlx5e_cq *cq = &drop_rq->cq;
3210         int err;
3211
3212         mlx5e_build_drop_rq_param(priv, &rq_param);
3213
3214         err = mlx5e_alloc_drop_cq(mdev, cq, &cq_param);
3215         if (err)
3216                 return err;
3217
3218         err = mlx5e_create_cq(cq, &cq_param);
3219         if (err)
3220                 goto err_free_cq;
3221
3222         err = mlx5e_alloc_drop_rq(mdev, drop_rq, &rq_param);
3223         if (err)
3224                 goto err_destroy_cq;
3225
3226         err = mlx5e_create_rq(drop_rq, &rq_param);
3227         if (err)
3228                 goto err_free_rq;
3229
3230         err = mlx5e_modify_rq_state(drop_rq, MLX5_RQC_STATE_RST, MLX5_RQC_STATE_RDY);
3231         if (err)
3232                 mlx5_core_warn(priv->mdev, "modify_rq_state failed, rx_if_down_packets won't be counted %d\n", err);
3233
3234         return 0;
3235
3236 err_free_rq:
3237         mlx5e_free_rq(drop_rq);
3238
3239 err_destroy_cq:
3240         mlx5e_destroy_cq(cq);
3241
3242 err_free_cq:
3243         mlx5e_free_cq(cq);
3244
3245         return err;
3246 }
3247
3248 void mlx5e_close_drop_rq(struct mlx5e_rq *drop_rq)
3249 {
3250         mlx5e_destroy_rq(drop_rq);
3251         mlx5e_free_rq(drop_rq);
3252         mlx5e_destroy_cq(&drop_rq->cq);
3253         mlx5e_free_cq(&drop_rq->cq);
3254 }
3255
3256 int mlx5e_create_tis(struct mlx5_core_dev *mdev, void *in, u32 *tisn)
3257 {
3258         void *tisc = MLX5_ADDR_OF(create_tis_in, in, ctx);
3259
3260         MLX5_SET(tisc, tisc, transport_domain, mdev->mlx5e_res.td.tdn);
3261
3262         if (MLX5_GET(tisc, tisc, tls_en))
3263                 MLX5_SET(tisc, tisc, pd, mdev->mlx5e_res.pdn);
3264
3265         if (mlx5_lag_is_lacp_owner(mdev))
3266                 MLX5_SET(tisc, tisc, strict_lag_tx_port_affinity, 1);
3267
3268         return mlx5_core_create_tis(mdev, in, tisn);
3269 }
3270
3271 void mlx5e_destroy_tis(struct mlx5_core_dev *mdev, u32 tisn)
3272 {
3273         mlx5_core_destroy_tis(mdev, tisn);
3274 }
3275
3276 void mlx5e_destroy_tises(struct mlx5e_priv *priv)
3277 {
3278         int tc, i;
3279
3280         for (i = 0; i < mlx5e_get_num_lag_ports(priv->mdev); i++)
3281                 for (tc = 0; tc < priv->profile->max_tc; tc++)
3282                         mlx5e_destroy_tis(priv->mdev, priv->tisn[i][tc]);
3283 }
3284
3285 static bool mlx5e_lag_should_assign_affinity(struct mlx5_core_dev *mdev)
3286 {
3287         return MLX5_CAP_GEN(mdev, lag_tx_port_affinity) && mlx5e_get_num_lag_ports(mdev) > 1;
3288 }
3289
3290 int mlx5e_create_tises(struct mlx5e_priv *priv)
3291 {
3292         int tc, i;
3293         int err;
3294
3295         for (i = 0; i < mlx5e_get_num_lag_ports(priv->mdev); i++) {
3296                 for (tc = 0; tc < priv->profile->max_tc; tc++) {
3297                         u32 in[MLX5_ST_SZ_DW(create_tis_in)] = {};
3298                         void *tisc;
3299
3300                         tisc = MLX5_ADDR_OF(create_tis_in, in, ctx);
3301
3302                         MLX5_SET(tisc, tisc, prio, tc << 1);
3303
3304                         if (mlx5e_lag_should_assign_affinity(priv->mdev))
3305                                 MLX5_SET(tisc, tisc, lag_tx_port_affinity, i + 1);
3306
3307                         err = mlx5e_create_tis(priv->mdev, in, &priv->tisn[i][tc]);
3308                         if (err)
3309                                 goto err_close_tises;
3310                 }
3311         }
3312
3313         return 0;
3314
3315 err_close_tises:
3316         for (; i >= 0; i--) {
3317                 for (tc--; tc >= 0; tc--)
3318                         mlx5e_destroy_tis(priv->mdev, priv->tisn[i][tc]);
3319                 tc = priv->profile->max_tc;
3320         }
3321
3322         return err;
3323 }
3324
3325 static void mlx5e_cleanup_nic_tx(struct mlx5e_priv *priv)
3326 {
3327         mlx5e_destroy_tises(priv);
3328 }
3329
3330 static void mlx5e_build_indir_tir_ctx_common(struct mlx5e_priv *priv,
3331                                              u32 rqtn, u32 *tirc)
3332 {
3333         MLX5_SET(tirc, tirc, transport_domain, priv->mdev->mlx5e_res.td.tdn);
3334         MLX5_SET(tirc, tirc, disp_type, MLX5_TIRC_DISP_TYPE_INDIRECT);
3335         MLX5_SET(tirc, tirc, indirect_table, rqtn);
3336         MLX5_SET(tirc, tirc, tunneled_offload_en,
3337                  priv->channels.params.tunneled_offload_en);
3338
3339         mlx5e_build_tir_ctx_lro(&priv->channels.params, tirc);
3340 }
3341
3342 static void mlx5e_build_indir_tir_ctx(struct mlx5e_priv *priv,
3343                                       enum mlx5e_traffic_types tt,
3344                                       u32 *tirc)
3345 {
3346         mlx5e_build_indir_tir_ctx_common(priv, priv->indir_rqt.rqtn, tirc);
3347         mlx5e_build_indir_tir_ctx_hash(&priv->rss_params,
3348                                        &tirc_default_config[tt], tirc, false);
3349 }
3350
3351 static void mlx5e_build_direct_tir_ctx(struct mlx5e_priv *priv, u32 rqtn, u32 *tirc)
3352 {
3353         mlx5e_build_indir_tir_ctx_common(priv, rqtn, tirc);
3354         MLX5_SET(tirc, tirc, rx_hash_fn, MLX5_RX_HASH_FN_INVERTED_XOR8);
3355 }
3356
3357 static void mlx5e_build_inner_indir_tir_ctx(struct mlx5e_priv *priv,
3358                                             enum mlx5e_traffic_types tt,
3359                                             u32 *tirc)
3360 {
3361         mlx5e_build_indir_tir_ctx_common(priv, priv->indir_rqt.rqtn, tirc);
3362         mlx5e_build_indir_tir_ctx_hash(&priv->rss_params,
3363                                        &tirc_default_config[tt], tirc, true);
3364 }
3365
3366 int mlx5e_create_indirect_tirs(struct mlx5e_priv *priv, bool inner_ttc)
3367 {
3368         struct mlx5e_tir *tir;
3369         void *tirc;
3370         int inlen;
3371         int i = 0;
3372         int err;
3373         u32 *in;
3374         int tt;
3375
3376         inlen = MLX5_ST_SZ_BYTES(create_tir_in);
3377         in = kvzalloc(inlen, GFP_KERNEL);
3378         if (!in)
3379                 return -ENOMEM;
3380
3381         for (tt = 0; tt < MLX5E_NUM_INDIR_TIRS; tt++) {
3382                 memset(in, 0, inlen);
3383                 tir = &priv->indir_tir[tt];
3384                 tirc = MLX5_ADDR_OF(create_tir_in, in, ctx);
3385                 mlx5e_build_indir_tir_ctx(priv, tt, tirc);
3386                 err = mlx5e_create_tir(priv->mdev, tir, in);
3387                 if (err) {
3388                         mlx5_core_warn(priv->mdev, "create indirect tirs failed, %d\n", err);
3389                         goto err_destroy_inner_tirs;
3390                 }
3391         }
3392
3393         if (!inner_ttc || !mlx5e_tunnel_inner_ft_supported(priv->mdev))
3394                 goto out;
3395
3396         for (i = 0; i < MLX5E_NUM_INDIR_TIRS; i++) {
3397                 memset(in, 0, inlen);
3398                 tir = &priv->inner_indir_tir[i];
3399                 tirc = MLX5_ADDR_OF(create_tir_in, in, ctx);
3400                 mlx5e_build_inner_indir_tir_ctx(priv, i, tirc);
3401                 err = mlx5e_create_tir(priv->mdev, tir, in);
3402                 if (err) {
3403                         mlx5_core_warn(priv->mdev, "create inner indirect tirs failed, %d\n", err);
3404                         goto err_destroy_inner_tirs;
3405                 }
3406         }
3407
3408 out:
3409         kvfree(in);
3410
3411         return 0;
3412
3413 err_destroy_inner_tirs:
3414         for (i--; i >= 0; i--)
3415                 mlx5e_destroy_tir(priv->mdev, &priv->inner_indir_tir[i]);
3416
3417         for (tt--; tt >= 0; tt--)
3418                 mlx5e_destroy_tir(priv->mdev, &priv->indir_tir[tt]);
3419
3420         kvfree(in);
3421
3422         return err;
3423 }
3424
3425 int mlx5e_create_direct_tirs(struct mlx5e_priv *priv, struct mlx5e_tir *tirs)
3426 {
3427         struct mlx5e_tir *tir;
3428         void *tirc;
3429         int inlen;
3430         int err = 0;
3431         u32 *in;
3432         int ix;
3433
3434         inlen = MLX5_ST_SZ_BYTES(create_tir_in);
3435         in = kvzalloc(inlen, GFP_KERNEL);
3436         if (!in)
3437                 return -ENOMEM;
3438
3439         for (ix = 0; ix < priv->max_nch; ix++) {
3440                 memset(in, 0, inlen);
3441                 tir = &tirs[ix];
3442                 tirc = MLX5_ADDR_OF(create_tir_in, in, ctx);
3443                 mlx5e_build_direct_tir_ctx(priv, tir->rqt.rqtn, tirc);
3444                 err = mlx5e_create_tir(priv->mdev, tir, in);
3445                 if (unlikely(err))
3446                         goto err_destroy_ch_tirs;
3447         }
3448
3449         goto out;
3450
3451 err_destroy_ch_tirs:
3452         mlx5_core_warn(priv->mdev, "create tirs failed, %d\n", err);
3453         for (ix--; ix >= 0; ix--)
3454                 mlx5e_destroy_tir(priv->mdev, &tirs[ix]);
3455
3456 out:
3457         kvfree(in);
3458
3459         return err;
3460 }
3461
3462 void mlx5e_destroy_indirect_tirs(struct mlx5e_priv *priv)
3463 {
3464         int i;
3465
3466         for (i = 0; i < MLX5E_NUM_INDIR_TIRS; i++)
3467                 mlx5e_destroy_tir(priv->mdev, &priv->indir_tir[i]);
3468
3469         /* Verify inner tirs resources allocated */
3470         if (!priv->inner_indir_tir[0].tirn)
3471                 return;
3472
3473         for (i = 0; i < MLX5E_NUM_INDIR_TIRS; i++)
3474                 mlx5e_destroy_tir(priv->mdev, &priv->inner_indir_tir[i]);
3475 }
3476
3477 void mlx5e_destroy_direct_tirs(struct mlx5e_priv *priv, struct mlx5e_tir *tirs)
3478 {
3479         int i;
3480
3481         for (i = 0; i < priv->max_nch; i++)
3482                 mlx5e_destroy_tir(priv->mdev, &tirs[i]);
3483 }
3484
3485 static int mlx5e_modify_channels_scatter_fcs(struct mlx5e_channels *chs, bool enable)
3486 {
3487         int err = 0;
3488         int i;
3489
3490         for (i = 0; i < chs->num; i++) {
3491                 err = mlx5e_modify_rq_scatter_fcs(&chs->c[i]->rq, enable);
3492                 if (err)
3493                         return err;
3494         }
3495
3496         return 0;
3497 }
3498
3499 static int mlx5e_modify_channels_vsd(struct mlx5e_channels *chs, bool vsd)
3500 {
3501         int err = 0;
3502         int i;
3503
3504         for (i = 0; i < chs->num; i++) {
3505                 err = mlx5e_modify_rq_vsd(&chs->c[i]->rq, vsd);
3506                 if (err)
3507                         return err;
3508         }
3509
3510         return 0;
3511 }
3512
3513 static int mlx5e_setup_tc_mqprio(struct mlx5e_priv *priv,
3514                                  struct tc_mqprio_qopt *mqprio)
3515 {
3516         struct mlx5e_channels new_channels = {};
3517         u8 tc = mqprio->num_tc;
3518         int err = 0;
3519
3520         mqprio->hw = TC_MQPRIO_HW_OFFLOAD_TCS;
3521
3522         if (tc && tc != MLX5E_MAX_NUM_TC)
3523                 return -EINVAL;
3524
3525         mutex_lock(&priv->state_lock);
3526
3527         new_channels.params = priv->channels.params;
3528         new_channels.params.num_tc = tc ? tc : 1;
3529
3530         if (!test_bit(MLX5E_STATE_OPENED, &priv->state)) {
3531                 priv->channels.params = new_channels.params;
3532                 goto out;
3533         }
3534
3535         err = mlx5e_safe_switch_channels(priv, &new_channels,
3536                                          mlx5e_num_channels_changed_ctx, NULL);
3537         if (err)
3538                 goto out;
3539
3540         priv->max_opened_tc = max_t(u8, priv->max_opened_tc,
3541                                     new_channels.params.num_tc);
3542 out:
3543         mutex_unlock(&priv->state_lock);
3544         return err;
3545 }
3546
3547 static LIST_HEAD(mlx5e_block_cb_list);
3548
3549 static int mlx5e_setup_tc(struct net_device *dev, enum tc_setup_type type,
3550                           void *type_data)
3551 {
3552         struct mlx5e_priv *priv = netdev_priv(dev);
3553
3554         switch (type) {
3555         case TC_SETUP_BLOCK: {
3556                 struct flow_block_offload *f = type_data;
3557
3558                 f->unlocked_driver_cb = true;
3559                 return flow_block_cb_setup_simple(type_data,
3560                                                   &mlx5e_block_cb_list,
3561                                                   mlx5e_setup_tc_block_cb,
3562                                                   priv, priv, true);
3563         }
3564         case TC_SETUP_QDISC_MQPRIO:
3565                 return mlx5e_setup_tc_mqprio(priv, type_data);
3566         default:
3567                 return -EOPNOTSUPP;
3568         }
3569 }
3570
3571 void mlx5e_fold_sw_stats64(struct mlx5e_priv *priv, struct rtnl_link_stats64 *s)
3572 {
3573         int i;
3574
3575         for (i = 0; i < priv->max_nch; i++) {
3576                 struct mlx5e_channel_stats *channel_stats = &priv->channel_stats[i];
3577                 struct mlx5e_rq_stats *xskrq_stats = &channel_stats->xskrq;
3578                 struct mlx5e_rq_stats *rq_stats = &channel_stats->rq;
3579                 int j;
3580
3581                 s->rx_packets   += rq_stats->packets + xskrq_stats->packets;
3582                 s->rx_bytes     += rq_stats->bytes + xskrq_stats->bytes;
3583
3584                 for (j = 0; j < priv->max_opened_tc; j++) {
3585                         struct mlx5e_sq_stats *sq_stats = &channel_stats->sq[j];
3586
3587                         s->tx_packets    += sq_stats->packets;
3588                         s->tx_bytes      += sq_stats->bytes;
3589                         s->tx_dropped    += sq_stats->dropped;
3590                 }
3591         }
3592 }
3593
3594 void
3595 mlx5e_get_stats(struct net_device *dev, struct rtnl_link_stats64 *stats)
3596 {
3597         struct mlx5e_priv *priv = netdev_priv(dev);
3598         struct mlx5e_vport_stats *vstats = &priv->stats.vport;
3599         struct mlx5e_pport_stats *pstats = &priv->stats.pport;
3600
3601         /* In switchdev mode, monitor counters doesn't monitor
3602          * rx/tx stats of 802_3. The update stats mechanism
3603          * should keep the 802_3 layout counters updated
3604          */
3605         if (!mlx5e_monitor_counter_supported(priv) ||
3606             mlx5e_is_uplink_rep(priv)) {
3607                 /* update HW stats in background for next time */
3608                 mlx5e_queue_update_stats(priv);
3609         }
3610
3611         if (mlx5e_is_uplink_rep(priv)) {
3612                 stats->rx_packets = PPORT_802_3_GET(pstats, a_frames_received_ok);
3613                 stats->rx_bytes   = PPORT_802_3_GET(pstats, a_octets_received_ok);
3614                 stats->tx_packets = PPORT_802_3_GET(pstats, a_frames_transmitted_ok);
3615                 stats->tx_bytes   = PPORT_802_3_GET(pstats, a_octets_transmitted_ok);
3616         } else {
3617                 mlx5e_fold_sw_stats64(priv, stats);
3618         }
3619
3620         stats->rx_dropped = priv->stats.qcnt.rx_out_of_buffer;
3621
3622         stats->rx_length_errors =
3623                 PPORT_802_3_GET(pstats, a_in_range_length_errors) +
3624                 PPORT_802_3_GET(pstats, a_out_of_range_length_field) +
3625                 PPORT_802_3_GET(pstats, a_frame_too_long_errors);
3626         stats->rx_crc_errors =
3627                 PPORT_802_3_GET(pstats, a_frame_check_sequence_errors);
3628         stats->rx_frame_errors = PPORT_802_3_GET(pstats, a_alignment_errors);
3629         stats->tx_aborted_errors = PPORT_2863_GET(pstats, if_out_discards);
3630         stats->rx_errors = stats->rx_length_errors + stats->rx_crc_errors +
3631                            stats->rx_frame_errors;
3632         stats->tx_errors = stats->tx_aborted_errors + stats->tx_carrier_errors;
3633
3634         /* vport multicast also counts packets that are dropped due to steering
3635          * or rx out of buffer
3636          */
3637         stats->multicast =
3638                 VPORT_COUNTER_GET(vstats, received_eth_multicast.packets);
3639 }
3640
3641 static void mlx5e_set_rx_mode(struct net_device *dev)
3642 {
3643         struct mlx5e_priv *priv = netdev_priv(dev);
3644
3645         queue_work(priv->wq, &priv->set_rx_mode_work);
3646 }
3647
3648 static int mlx5e_set_mac(struct net_device *netdev, void *addr)
3649 {
3650         struct mlx5e_priv *priv = netdev_priv(netdev);
3651         struct sockaddr *saddr = addr;
3652
3653         if (!is_valid_ether_addr(saddr->sa_data))
3654                 return -EADDRNOTAVAIL;
3655
3656         netif_addr_lock_bh(netdev);
3657         ether_addr_copy(netdev->dev_addr, saddr->sa_data);
3658         netif_addr_unlock_bh(netdev);
3659
3660         queue_work(priv->wq, &priv->set_rx_mode_work);
3661
3662         return 0;
3663 }
3664
3665 #define MLX5E_SET_FEATURE(features, feature, enable)    \
3666         do {                                            \
3667                 if (enable)                             \
3668                         *features |= feature;           \
3669                 else                                    \
3670                         *features &= ~feature;          \
3671         } while (0)
3672
3673 typedef int (*mlx5e_feature_handler)(struct net_device *netdev, bool enable);
3674
3675 static int set_feature_lro(struct net_device *netdev, bool enable)
3676 {
3677         struct mlx5e_priv *priv = netdev_priv(netdev);
3678         struct mlx5_core_dev *mdev = priv->mdev;
3679         struct mlx5e_channels new_channels = {};
3680         struct mlx5e_params *old_params;
3681         int err = 0;
3682         bool reset;
3683
3684         mutex_lock(&priv->state_lock);
3685
3686         if (enable && priv->xsk.refcnt) {
3687                 netdev_warn(netdev, "LRO is incompatible with AF_XDP (%hu XSKs are active)\n",
3688                             priv->xsk.refcnt);
3689                 err = -EINVAL;
3690                 goto out;
3691         }
3692
3693         old_params = &priv->channels.params;
3694         if (enable && !MLX5E_GET_PFLAG(old_params, MLX5E_PFLAG_RX_STRIDING_RQ)) {
3695                 netdev_warn(netdev, "can't set LRO with legacy RQ\n");
3696                 err = -EINVAL;
3697                 goto out;
3698         }
3699
3700         reset = test_bit(MLX5E_STATE_OPENED, &priv->state);
3701
3702         new_channels.params = *old_params;
3703         new_channels.params.lro_en = enable;
3704
3705         if (old_params->rq_wq_type != MLX5_WQ_TYPE_CYCLIC) {
3706                 if (mlx5e_rx_mpwqe_is_linear_skb(mdev, old_params, NULL) ==
3707                     mlx5e_rx_mpwqe_is_linear_skb(mdev, &new_channels.params, NULL))
3708                         reset = false;
3709         }
3710
3711         if (!reset) {
3712                 *old_params = new_channels.params;
3713                 err = mlx5e_modify_tirs_lro(priv);
3714                 goto out;
3715         }
3716
3717         err = mlx5e_safe_switch_channels(priv, &new_channels,
3718                                          mlx5e_modify_tirs_lro_ctx, NULL);
3719 out:
3720         mutex_unlock(&priv->state_lock);
3721         return err;
3722 }
3723
3724 static int set_feature_cvlan_filter(struct net_device *netdev, bool enable)
3725 {
3726         struct mlx5e_priv *priv = netdev_priv(netdev);
3727
3728         if (enable)
3729                 mlx5e_enable_cvlan_filter(priv);
3730         else
3731                 mlx5e_disable_cvlan_filter(priv);
3732
3733         return 0;
3734 }
3735
3736 #if IS_ENABLED(CONFIG_MLX5_CLS_ACT)
3737 static int set_feature_tc_num_filters(struct net_device *netdev, bool enable)
3738 {
3739         struct mlx5e_priv *priv = netdev_priv(netdev);
3740
3741         if (!enable && mlx5e_tc_num_filters(priv, MLX5_TC_FLAG(NIC_OFFLOAD))) {
3742                 netdev_err(netdev,
3743                            "Active offloaded tc filters, can't turn hw_tc_offload off\n");
3744                 return -EINVAL;
3745         }
3746
3747         return 0;
3748 }
3749 #endif
3750
3751 static int set_feature_rx_all(struct net_device *netdev, bool enable)
3752 {
3753         struct mlx5e_priv *priv = netdev_priv(netdev);
3754         struct mlx5_core_dev *mdev = priv->mdev;
3755
3756         return mlx5_set_port_fcs(mdev, !enable);
3757 }
3758
3759 static int set_feature_rx_fcs(struct net_device *netdev, bool enable)
3760 {
3761         struct mlx5e_priv *priv = netdev_priv(netdev);
3762         int err;
3763
3764         mutex_lock(&priv->state_lock);
3765
3766         priv->channels.params.scatter_fcs_en = enable;
3767         err = mlx5e_modify_channels_scatter_fcs(&priv->channels, enable);
3768         if (err)
3769                 priv->channels.params.scatter_fcs_en = !enable;
3770
3771         mutex_unlock(&priv->state_lock);
3772
3773         return err;
3774 }
3775
3776 static int set_feature_rx_vlan(struct net_device *netdev, bool enable)
3777 {
3778         struct mlx5e_priv *priv = netdev_priv(netdev);
3779         int err = 0;
3780
3781         mutex_lock(&priv->state_lock);
3782
3783         priv->channels.params.vlan_strip_disable = !enable;
3784         if (!test_bit(MLX5E_STATE_OPENED, &priv->state))
3785                 goto unlock;
3786
3787         err = mlx5e_modify_channels_vsd(&priv->channels, !enable);
3788         if (err)
3789                 priv->channels.params.vlan_strip_disable = enable;
3790
3791 unlock:
3792         mutex_unlock(&priv->state_lock);
3793
3794         return err;
3795 }
3796
3797 #ifdef CONFIG_MLX5_EN_ARFS
3798 static int set_feature_arfs(struct net_device *netdev, bool enable)
3799 {
3800         struct mlx5e_priv *priv = netdev_priv(netdev);
3801         int err;
3802
3803         if (enable)
3804                 err = mlx5e_arfs_enable(priv);
3805         else
3806                 err = mlx5e_arfs_disable(priv);
3807
3808         return err;
3809 }
3810 #endif
3811
3812 static int mlx5e_handle_feature(struct net_device *netdev,
3813                                 netdev_features_t *features,
3814                                 netdev_features_t wanted_features,
3815                                 netdev_features_t feature,
3816                                 mlx5e_feature_handler feature_handler)
3817 {
3818         netdev_features_t changes = wanted_features ^ netdev->features;
3819         bool enable = !!(wanted_features & feature);
3820         int err;
3821
3822         if (!(changes & feature))
3823                 return 0;
3824
3825         err = feature_handler(netdev, enable);
3826         if (err) {
3827                 netdev_err(netdev, "%s feature %pNF failed, err %d\n",
3828                            enable ? "Enable" : "Disable", &feature, err);
3829                 return err;
3830         }
3831
3832         MLX5E_SET_FEATURE(features, feature, enable);
3833         return 0;
3834 }
3835
3836 int mlx5e_set_features(struct net_device *netdev, netdev_features_t features)
3837 {
3838         netdev_features_t oper_features = netdev->features;
3839         int err = 0;
3840
3841 #define MLX5E_HANDLE_FEATURE(feature, handler) \
3842         mlx5e_handle_feature(netdev, &oper_features, features, feature, handler)
3843
3844         err |= MLX5E_HANDLE_FEATURE(NETIF_F_LRO, set_feature_lro);
3845         err |= MLX5E_HANDLE_FEATURE(NETIF_F_HW_VLAN_CTAG_FILTER,
3846                                     set_feature_cvlan_filter);
3847 #if IS_ENABLED(CONFIG_MLX5_CLS_ACT)
3848         err |= MLX5E_HANDLE_FEATURE(NETIF_F_HW_TC, set_feature_tc_num_filters);
3849 #endif
3850         err |= MLX5E_HANDLE_FEATURE(NETIF_F_RXALL, set_feature_rx_all);
3851         err |= MLX5E_HANDLE_FEATURE(NETIF_F_RXFCS, set_feature_rx_fcs);
3852         err |= MLX5E_HANDLE_FEATURE(NETIF_F_HW_VLAN_CTAG_RX, set_feature_rx_vlan);
3853 #ifdef CONFIG_MLX5_EN_ARFS
3854         err |= MLX5E_HANDLE_FEATURE(NETIF_F_NTUPLE, set_feature_arfs);
3855 #endif
3856
3857         if (err) {
3858                 netdev->features = oper_features;
3859                 return -EINVAL;
3860         }
3861
3862         return 0;
3863 }
3864
3865 static netdev_features_t mlx5e_fix_features(struct net_device *netdev,
3866                                             netdev_features_t features)
3867 {
3868         struct mlx5e_priv *priv = netdev_priv(netdev);
3869         struct mlx5e_params *params;
3870
3871         mutex_lock(&priv->state_lock);
3872         params = &priv->channels.params;
3873         if (!bitmap_empty(priv->fs.vlan.active_svlans, VLAN_N_VID)) {
3874                 /* HW strips the outer C-tag header, this is a problem
3875                  * for S-tag traffic.
3876                  */
3877                 features &= ~NETIF_F_HW_VLAN_CTAG_RX;
3878                 if (!params->vlan_strip_disable)
3879                         netdev_warn(netdev, "Dropping C-tag vlan stripping offload due to S-tag vlan\n");
3880         }
3881         if (!MLX5E_GET_PFLAG(params, MLX5E_PFLAG_RX_STRIDING_RQ)) {
3882                 if (features & NETIF_F_LRO) {
3883                         netdev_warn(netdev, "Disabling LRO, not supported in legacy RQ\n");
3884                         features &= ~NETIF_F_LRO;
3885                 }
3886         }
3887
3888         if (MLX5E_GET_PFLAG(params, MLX5E_PFLAG_RX_CQE_COMPRESS)) {
3889                 features &= ~NETIF_F_RXHASH;
3890                 if (netdev->features & NETIF_F_RXHASH)
3891                         netdev_warn(netdev, "Disabling rxhash, not supported when CQE compress is active\n");
3892         }
3893
3894         mutex_unlock(&priv->state_lock);
3895
3896         return features;
3897 }
3898
3899 static bool mlx5e_xsk_validate_mtu(struct net_device *netdev,
3900                                    struct mlx5e_channels *chs,
3901                                    struct mlx5e_params *new_params,
3902                                    struct mlx5_core_dev *mdev)
3903 {
3904         u16 ix;
3905
3906         for (ix = 0; ix < chs->params.num_channels; ix++) {
3907                 struct xdp_umem *umem = mlx5e_xsk_get_umem(&chs->params, chs->params.xsk, ix);
3908                 struct mlx5e_xsk_param xsk;
3909
3910                 if (!umem)
3911                         continue;
3912
3913                 mlx5e_build_xsk_param(umem, &xsk);
3914
3915                 if (!mlx5e_validate_xsk_param(new_params, &xsk, mdev)) {
3916                         u32 hr = mlx5e_get_linear_rq_headroom(new_params, &xsk);
3917                         int max_mtu_frame, max_mtu_page, max_mtu;
3918
3919                         /* Two criteria must be met:
3920                          * 1. HW MTU + all headrooms <= XSK frame size.
3921                          * 2. Size of SKBs allocated on XDP_PASS <= PAGE_SIZE.
3922                          */
3923                         max_mtu_frame = MLX5E_HW2SW_MTU(new_params, xsk.chunk_size - hr);
3924                         max_mtu_page = mlx5e_xdp_max_mtu(new_params, &xsk);
3925                         max_mtu = min(max_mtu_frame, max_mtu_page);
3926
3927                         netdev_err(netdev, "MTU %d is too big for an XSK running on channel %hu. Try MTU <= %d\n",
3928                                    new_params->sw_mtu, ix, max_mtu);
3929                         return false;
3930                 }
3931         }
3932
3933         return true;
3934 }
3935
3936 int mlx5e_change_mtu(struct net_device *netdev, int new_mtu,
3937                      mlx5e_fp_preactivate preactivate)
3938 {
3939         struct mlx5e_priv *priv = netdev_priv(netdev);
3940         struct mlx5e_channels new_channels = {};
3941         struct mlx5e_params *params;
3942         int err = 0;
3943         bool reset;
3944
3945         mutex_lock(&priv->state_lock);
3946
3947         params = &priv->channels.params;
3948
3949         reset = !params->lro_en;
3950         reset = reset && test_bit(MLX5E_STATE_OPENED, &priv->state);
3951
3952         new_channels.params = *params;
3953         new_channels.params.sw_mtu = new_mtu;
3954
3955         if (params->xdp_prog &&
3956             !mlx5e_rx_is_linear_skb(&new_channels.params, NULL)) {
3957                 netdev_err(netdev, "MTU(%d) > %d is not allowed while XDP enabled\n",
3958                            new_mtu, mlx5e_xdp_max_mtu(params, NULL));
3959                 err = -EINVAL;
3960                 goto out;
3961         }
3962
3963         if (priv->xsk.refcnt &&
3964             !mlx5e_xsk_validate_mtu(netdev, &priv->channels,
3965                                     &new_channels.params, priv->mdev)) {
3966                 err = -EINVAL;
3967                 goto out;
3968         }
3969
3970         if (params->rq_wq_type == MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ) {
3971                 bool is_linear = mlx5e_rx_mpwqe_is_linear_skb(priv->mdev,
3972                                                               &new_channels.params,
3973                                                               NULL);
3974                 u8 ppw_old = mlx5e_mpwqe_log_pkts_per_wqe(params, NULL);
3975                 u8 ppw_new = mlx5e_mpwqe_log_pkts_per_wqe(&new_channels.params, NULL);
3976
3977                 /* If XSK is active, XSK RQs are linear. */
3978                 is_linear |= priv->xsk.refcnt;
3979
3980                 /* Always reset in linear mode - hw_mtu is used in data path. */
3981                 reset = reset && (is_linear || (ppw_old != ppw_new));
3982         }
3983
3984         if (!reset) {
3985                 params->sw_mtu = new_mtu;
3986                 if (preactivate)
3987                         preactivate(priv, NULL);
3988                 netdev->mtu = params->sw_mtu;
3989                 goto out;
3990         }
3991
3992         err = mlx5e_safe_switch_channels(priv, &new_channels, preactivate, NULL);
3993         if (err)
3994                 goto out;
3995
3996         netdev->mtu = new_channels.params.sw_mtu;
3997
3998 out:
3999         mutex_unlock(&priv->state_lock);
4000         return err;
4001 }
4002
4003 static int mlx5e_change_nic_mtu(struct net_device *netdev, int new_mtu)
4004 {
4005         return mlx5e_change_mtu(netdev, new_mtu, mlx5e_set_dev_port_mtu_ctx);
4006 }
4007
4008 int mlx5e_hwstamp_set(struct mlx5e_priv *priv, struct ifreq *ifr)
4009 {
4010         struct hwtstamp_config config;
4011         int err;
4012
4013         if (!MLX5_CAP_GEN(priv->mdev, device_frequency_khz) ||
4014             (mlx5_clock_get_ptp_index(priv->mdev) == -1))
4015                 return -EOPNOTSUPP;
4016
4017         if (copy_from_user(&config, ifr->ifr_data, sizeof(config)))
4018                 return -EFAULT;
4019
4020         /* TX HW timestamp */
4021         switch (config.tx_type) {
4022         case HWTSTAMP_TX_OFF:
4023         case HWTSTAMP_TX_ON:
4024                 break;
4025         default:
4026                 return -ERANGE;
4027         }
4028
4029         mutex_lock(&priv->state_lock);
4030         /* RX HW timestamp */
4031         switch (config.rx_filter) {
4032         case HWTSTAMP_FILTER_NONE:
4033                 /* Reset CQE compression to Admin default */
4034                 mlx5e_modify_rx_cqe_compression_locked(priv, priv->channels.params.rx_cqe_compress_def);
4035                 break;
4036         case HWTSTAMP_FILTER_ALL:
4037         case HWTSTAMP_FILTER_SOME:
4038         case HWTSTAMP_FILTER_PTP_V1_L4_EVENT:
4039         case HWTSTAMP_FILTER_PTP_V1_L4_SYNC:
4040         case HWTSTAMP_FILTER_PTP_V1_L4_DELAY_REQ:
4041         case HWTSTAMP_FILTER_PTP_V2_L4_EVENT:
4042         case HWTSTAMP_FILTER_PTP_V2_L4_SYNC:
4043         case HWTSTAMP_FILTER_PTP_V2_L4_DELAY_REQ:
4044         case HWTSTAMP_FILTER_PTP_V2_L2_EVENT:
4045         case HWTSTAMP_FILTER_PTP_V2_L2_SYNC:
4046         case HWTSTAMP_FILTER_PTP_V2_L2_DELAY_REQ:
4047         case HWTSTAMP_FILTER_PTP_V2_EVENT:
4048         case HWTSTAMP_FILTER_PTP_V2_SYNC:
4049         case HWTSTAMP_FILTER_PTP_V2_DELAY_REQ:
4050         case HWTSTAMP_FILTER_NTP_ALL:
4051                 /* Disable CQE compression */
4052                 if (MLX5E_GET_PFLAG(&priv->channels.params, MLX5E_PFLAG_RX_CQE_COMPRESS))
4053                         netdev_warn(priv->netdev, "Disabling RX cqe compression\n");
4054                 err = mlx5e_modify_rx_cqe_compression_locked(priv, false);
4055                 if (err) {
4056                         netdev_err(priv->netdev, "Failed disabling cqe compression err=%d\n", err);
4057                         mutex_unlock(&priv->state_lock);
4058                         return err;
4059                 }
4060                 config.rx_filter = HWTSTAMP_FILTER_ALL;
4061                 break;
4062         default:
4063                 mutex_unlock(&priv->state_lock);
4064                 return -ERANGE;
4065         }
4066
4067         memcpy(&priv->tstamp, &config, sizeof(config));
4068         mutex_unlock(&priv->state_lock);
4069
4070         /* might need to fix some features */
4071         netdev_update_features(priv->netdev);
4072
4073         return copy_to_user(ifr->ifr_data, &config,
4074                             sizeof(config)) ? -EFAULT : 0;
4075 }
4076
4077 int mlx5e_hwstamp_get(struct mlx5e_priv *priv, struct ifreq *ifr)
4078 {
4079         struct hwtstamp_config *cfg = &priv->tstamp;
4080
4081         if (!MLX5_CAP_GEN(priv->mdev, device_frequency_khz))
4082                 return -EOPNOTSUPP;
4083
4084         return copy_to_user(ifr->ifr_data, cfg, sizeof(*cfg)) ? -EFAULT : 0;
4085 }
4086
4087 static int mlx5e_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
4088 {
4089         struct mlx5e_priv *priv = netdev_priv(dev);
4090
4091         switch (cmd) {
4092         case SIOCSHWTSTAMP:
4093                 return mlx5e_hwstamp_set(priv, ifr);
4094         case SIOCGHWTSTAMP:
4095                 return mlx5e_hwstamp_get(priv, ifr);
4096         default:
4097                 return -EOPNOTSUPP;
4098         }
4099 }
4100
4101 #ifdef CONFIG_MLX5_ESWITCH
4102 int mlx5e_set_vf_mac(struct net_device *dev, int vf, u8 *mac)
4103 {
4104         struct mlx5e_priv *priv = netdev_priv(dev);
4105         struct mlx5_core_dev *mdev = priv->mdev;
4106
4107         return mlx5_eswitch_set_vport_mac(mdev->priv.eswitch, vf + 1, mac);
4108 }
4109
4110 static int mlx5e_set_vf_vlan(struct net_device *dev, int vf, u16 vlan, u8 qos,
4111                              __be16 vlan_proto)
4112 {
4113         struct mlx5e_priv *priv = netdev_priv(dev);
4114         struct mlx5_core_dev *mdev = priv->mdev;
4115
4116         if (vlan_proto != htons(ETH_P_8021Q))
4117                 return -EPROTONOSUPPORT;
4118
4119         return mlx5_eswitch_set_vport_vlan(mdev->priv.eswitch, vf + 1,
4120                                            vlan, qos);
4121 }
4122
4123 static int mlx5e_set_vf_spoofchk(struct net_device *dev, int vf, bool setting)
4124 {
4125         struct mlx5e_priv *priv = netdev_priv(dev);
4126         struct mlx5_core_dev *mdev = priv->mdev;
4127
4128         return mlx5_eswitch_set_vport_spoofchk(mdev->priv.eswitch, vf + 1, setting);
4129 }
4130
4131 static int mlx5e_set_vf_trust(struct net_device *dev, int vf, bool setting)
4132 {
4133         struct mlx5e_priv *priv = netdev_priv(dev);
4134         struct mlx5_core_dev *mdev = priv->mdev;
4135
4136         return mlx5_eswitch_set_vport_trust(mdev->priv.eswitch, vf + 1, setting);
4137 }
4138
4139 int mlx5e_set_vf_rate(struct net_device *dev, int vf, int min_tx_rate,
4140                       int max_tx_rate)
4141 {
4142         struct mlx5e_priv *priv = netdev_priv(dev);
4143         struct mlx5_core_dev *mdev = priv->mdev;
4144
4145         return mlx5_eswitch_set_vport_rate(mdev->priv.eswitch, vf + 1,
4146                                            max_tx_rate, min_tx_rate);
4147 }
4148
4149 static int mlx5_vport_link2ifla(u8 esw_link)
4150 {
4151         switch (esw_link) {
4152         case MLX5_VPORT_ADMIN_STATE_DOWN:
4153                 return IFLA_VF_LINK_STATE_DISABLE;
4154         case MLX5_VPORT_ADMIN_STATE_UP:
4155                 return IFLA_VF_LINK_STATE_ENABLE;
4156         }
4157         return IFLA_VF_LINK_STATE_AUTO;
4158 }
4159
4160 static int mlx5_ifla_link2vport(u8 ifla_link)
4161 {
4162         switch (ifla_link) {
4163         case IFLA_VF_LINK_STATE_DISABLE:
4164                 return MLX5_VPORT_ADMIN_STATE_DOWN;
4165         case IFLA_VF_LINK_STATE_ENABLE:
4166                 return MLX5_VPORT_ADMIN_STATE_UP;
4167         }
4168         return MLX5_VPORT_ADMIN_STATE_AUTO;
4169 }
4170
4171 static int mlx5e_set_vf_link_state(struct net_device *dev, int vf,
4172                                    int link_state)
4173 {
4174         struct mlx5e_priv *priv = netdev_priv(dev);
4175         struct mlx5_core_dev *mdev = priv->mdev;
4176
4177         return mlx5_eswitch_set_vport_state(mdev->priv.eswitch, vf + 1,
4178                                             mlx5_ifla_link2vport(link_state));
4179 }
4180
4181 int mlx5e_get_vf_config(struct net_device *dev,
4182                         int vf, struct ifla_vf_info *ivi)
4183 {
4184         struct mlx5e_priv *priv = netdev_priv(dev);
4185         struct mlx5_core_dev *mdev = priv->mdev;
4186         int err;
4187
4188         err = mlx5_eswitch_get_vport_config(mdev->priv.eswitch, vf + 1, ivi);
4189         if (err)
4190                 return err;
4191         ivi->linkstate = mlx5_vport_link2ifla(ivi->linkstate);
4192         return 0;
4193 }
4194
4195 int mlx5e_get_vf_stats(struct net_device *dev,
4196                        int vf, struct ifla_vf_stats *vf_stats)
4197 {
4198         struct mlx5e_priv *priv = netdev_priv(dev);
4199         struct mlx5_core_dev *mdev = priv->mdev;
4200
4201         return mlx5_eswitch_get_vport_stats(mdev->priv.eswitch, vf + 1,
4202                                             vf_stats);
4203 }
4204 #endif
4205
4206 struct mlx5e_vxlan_work {
4207         struct work_struct      work;
4208         struct mlx5e_priv       *priv;
4209         u16                     port;
4210 };
4211
4212 static void mlx5e_vxlan_add_work(struct work_struct *work)
4213 {
4214         struct mlx5e_vxlan_work *vxlan_work =
4215                 container_of(work, struct mlx5e_vxlan_work, work);
4216         struct mlx5e_priv *priv = vxlan_work->priv;
4217         u16 port = vxlan_work->port;
4218
4219         mutex_lock(&priv->state_lock);
4220         mlx5_vxlan_add_port(priv->mdev->vxlan, port);
4221         mutex_unlock(&priv->state_lock);
4222
4223         kfree(vxlan_work);
4224 }
4225
4226 static void mlx5e_vxlan_del_work(struct work_struct *work)
4227 {
4228         struct mlx5e_vxlan_work *vxlan_work =
4229                 container_of(work, struct mlx5e_vxlan_work, work);
4230         struct mlx5e_priv *priv         = vxlan_work->priv;
4231         u16 port = vxlan_work->port;
4232
4233         mutex_lock(&priv->state_lock);
4234         mlx5_vxlan_del_port(priv->mdev->vxlan, port);
4235         mutex_unlock(&priv->state_lock);
4236         kfree(vxlan_work);
4237 }
4238
4239 static void mlx5e_vxlan_queue_work(struct mlx5e_priv *priv, u16 port, int add)
4240 {
4241         struct mlx5e_vxlan_work *vxlan_work;
4242
4243         vxlan_work = kmalloc(sizeof(*vxlan_work), GFP_ATOMIC);
4244         if (!vxlan_work)
4245                 return;
4246
4247         if (add)
4248                 INIT_WORK(&vxlan_work->work, mlx5e_vxlan_add_work);
4249         else
4250                 INIT_WORK(&vxlan_work->work, mlx5e_vxlan_del_work);
4251
4252         vxlan_work->priv = priv;
4253         vxlan_work->port = port;
4254         queue_work(priv->wq, &vxlan_work->work);
4255 }
4256
4257 void mlx5e_add_vxlan_port(struct net_device *netdev, struct udp_tunnel_info *ti)
4258 {
4259         struct mlx5e_priv *priv = netdev_priv(netdev);
4260
4261         if (ti->type != UDP_TUNNEL_TYPE_VXLAN)
4262                 return;
4263
4264         if (!mlx5_vxlan_allowed(priv->mdev->vxlan))
4265                 return;
4266
4267         mlx5e_vxlan_queue_work(priv, be16_to_cpu(ti->port), 1);
4268 }
4269
4270 void mlx5e_del_vxlan_port(struct net_device *netdev, struct udp_tunnel_info *ti)
4271 {
4272         struct mlx5e_priv *priv = netdev_priv(netdev);
4273
4274         if (ti->type != UDP_TUNNEL_TYPE_VXLAN)
4275                 return;
4276
4277         if (!mlx5_vxlan_allowed(priv->mdev->vxlan))
4278                 return;
4279
4280         mlx5e_vxlan_queue_work(priv, be16_to_cpu(ti->port), 0);
4281 }
4282
4283 static netdev_features_t mlx5e_tunnel_features_check(struct mlx5e_priv *priv,
4284                                                      struct sk_buff *skb,
4285                                                      netdev_features_t features)
4286 {
4287         unsigned int offset = 0;
4288         struct udphdr *udph;
4289         u8 proto;
4290         u16 port;
4291
4292         switch (vlan_get_protocol(skb)) {
4293         case htons(ETH_P_IP):
4294                 proto = ip_hdr(skb)->protocol;
4295                 break;
4296         case htons(ETH_P_IPV6):
4297                 proto = ipv6_find_hdr(skb, &offset, -1, NULL, NULL);
4298                 break;
4299         default:
4300                 goto out;
4301         }
4302
4303         switch (proto) {
4304         case IPPROTO_GRE:
4305                 return features;
4306         case IPPROTO_IPIP:
4307         case IPPROTO_IPV6:
4308                 if (mlx5e_tunnel_proto_supported(priv->mdev, IPPROTO_IPIP))
4309                         return features;
4310                 break;
4311         case IPPROTO_UDP:
4312                 udph = udp_hdr(skb);
4313                 port = be16_to_cpu(udph->dest);
4314
4315                 /* Verify if UDP port is being offloaded by HW */
4316                 if (mlx5_vxlan_lookup_port(priv->mdev->vxlan, port))
4317                         return features;
4318
4319 #if IS_ENABLED(CONFIG_GENEVE)
4320                 /* Support Geneve offload for default UDP port */
4321                 if (port == GENEVE_UDP_PORT && mlx5_geneve_tx_allowed(priv->mdev))
4322                         return features;
4323 #endif
4324         }
4325
4326 out:
4327         /* Disable CSUM and GSO if the udp dport is not offloaded by HW */
4328         return features & ~(NETIF_F_CSUM_MASK | NETIF_F_GSO_MASK);
4329 }
4330
4331 netdev_features_t mlx5e_features_check(struct sk_buff *skb,
4332                                        struct net_device *netdev,
4333                                        netdev_features_t features)
4334 {
4335         struct mlx5e_priv *priv = netdev_priv(netdev);
4336
4337         features = vlan_features_check(skb, features);
4338         features = vxlan_features_check(skb, features);
4339
4340 #ifdef CONFIG_MLX5_EN_IPSEC
4341         if (mlx5e_ipsec_feature_check(skb, netdev, features))
4342                 return features;
4343 #endif
4344
4345         /* Validate if the tunneled packet is being offloaded by HW */
4346         if (skb->encapsulation &&
4347             (features & NETIF_F_CSUM_MASK || features & NETIF_F_GSO_MASK))
4348                 return mlx5e_tunnel_features_check(priv, skb, features);
4349
4350         return features;
4351 }
4352
4353 static void mlx5e_tx_timeout_work(struct work_struct *work)
4354 {
4355         struct mlx5e_priv *priv = container_of(work, struct mlx5e_priv,
4356                                                tx_timeout_work);
4357         bool report_failed = false;
4358         int err;
4359         int i;
4360
4361         rtnl_lock();
4362         mutex_lock(&priv->state_lock);
4363
4364         if (!test_bit(MLX5E_STATE_OPENED, &priv->state))
4365                 goto unlock;
4366
4367         for (i = 0; i < priv->channels.num * priv->channels.params.num_tc; i++) {
4368                 struct netdev_queue *dev_queue =
4369                         netdev_get_tx_queue(priv->netdev, i);
4370                 struct mlx5e_txqsq *sq = priv->txq2sq[i];
4371
4372                 if (!netif_xmit_stopped(dev_queue))
4373                         continue;
4374
4375                 if (mlx5e_reporter_tx_timeout(sq))
4376                         report_failed = true;
4377         }
4378
4379         if (!report_failed)
4380                 goto unlock;
4381
4382         err = mlx5e_safe_reopen_channels(priv);
4383         if (err)
4384                 netdev_err(priv->netdev,
4385                            "mlx5e_safe_reopen_channels failed recovering from a tx_timeout, err(%d).\n",
4386                            err);
4387
4388 unlock:
4389         mutex_unlock(&priv->state_lock);
4390         rtnl_unlock();
4391 }
4392
4393 static void mlx5e_tx_timeout(struct net_device *dev, unsigned int txqueue)
4394 {
4395         struct mlx5e_priv *priv = netdev_priv(dev);
4396
4397         netdev_err(dev, "TX timeout detected\n");
4398         queue_work(priv->wq, &priv->tx_timeout_work);
4399 }
4400
4401 static int mlx5e_xdp_allowed(struct mlx5e_priv *priv, struct bpf_prog *prog)
4402 {
4403         struct net_device *netdev = priv->netdev;
4404         struct mlx5e_channels new_channels = {};
4405
4406         if (priv->channels.params.lro_en) {
4407                 netdev_warn(netdev, "can't set XDP while LRO is on, disable LRO first\n");
4408                 return -EINVAL;
4409         }
4410
4411         if (MLX5_IPSEC_DEV(priv->mdev)) {
4412                 netdev_warn(netdev, "can't set XDP with IPSec offload\n");
4413                 return -EINVAL;
4414         }
4415
4416         new_channels.params = priv->channels.params;
4417         new_channels.params.xdp_prog = prog;
4418
4419         /* No XSK params: AF_XDP can't be enabled yet at the point of setting
4420          * the XDP program.
4421          */
4422         if (!mlx5e_rx_is_linear_skb(&new_channels.params, NULL)) {
4423                 netdev_warn(netdev, "XDP is not allowed with MTU(%d) > %d\n",
4424                             new_channels.params.sw_mtu,
4425                             mlx5e_xdp_max_mtu(&new_channels.params, NULL));
4426                 return -EINVAL;
4427         }
4428
4429         return 0;
4430 }
4431
4432 static int mlx5e_xdp_set(struct net_device *netdev, struct bpf_prog *prog)
4433 {
4434         struct mlx5e_priv *priv = netdev_priv(netdev);
4435         struct bpf_prog *old_prog;
4436         bool reset, was_opened;
4437         int err = 0;
4438         int i;
4439
4440         mutex_lock(&priv->state_lock);
4441
4442         if (prog) {
4443                 err = mlx5e_xdp_allowed(priv, prog);
4444                 if (err)
4445                         goto unlock;
4446         }
4447
4448         was_opened = test_bit(MLX5E_STATE_OPENED, &priv->state);
4449         /* no need for full reset when exchanging programs */
4450         reset = (!priv->channels.params.xdp_prog || !prog);
4451
4452         if (was_opened && !reset)
4453                 /* num_channels is invariant here, so we can take the
4454                  * batched reference right upfront.
4455                  */
4456                 bpf_prog_add(prog, priv->channels.num);
4457
4458         if (was_opened && reset) {
4459                 struct mlx5e_channels new_channels = {};
4460
4461                 new_channels.params = priv->channels.params;
4462                 new_channels.params.xdp_prog = prog;
4463                 mlx5e_set_rq_type(priv->mdev, &new_channels.params);
4464                 old_prog = priv->channels.params.xdp_prog;
4465
4466                 err = mlx5e_safe_switch_channels(priv, &new_channels, NULL, NULL);
4467                 if (err)
4468                         goto unlock;
4469         } else {
4470                 /* exchange programs, extra prog reference we got from caller
4471                  * as long as we don't fail from this point onwards.
4472                  */
4473                 old_prog = xchg(&priv->channels.params.xdp_prog, prog);
4474         }
4475
4476         if (old_prog)
4477                 bpf_prog_put(old_prog);
4478
4479         if (!was_opened && reset) /* change RQ type according to priv->xdp_prog */
4480                 mlx5e_set_rq_type(priv->mdev, &priv->channels.params);
4481
4482         if (!was_opened || reset)
4483                 goto unlock;
4484
4485         /* exchanging programs w/o reset, we update ref counts on behalf
4486          * of the channels RQs here.
4487          */
4488         for (i = 0; i < priv->channels.num; i++) {
4489                 struct mlx5e_channel *c = priv->channels.c[i];
4490                 bool xsk_open = test_bit(MLX5E_CHANNEL_STATE_XSK, c->state);
4491
4492                 clear_bit(MLX5E_RQ_STATE_ENABLED, &c->rq.state);
4493                 if (xsk_open)
4494                         clear_bit(MLX5E_RQ_STATE_ENABLED, &c->xskrq.state);
4495                 napi_synchronize(&c->napi);
4496                 /* prevent mlx5e_poll_rx_cq from accessing rq->xdp_prog */
4497
4498                 old_prog = xchg(&c->rq.xdp_prog, prog);
4499                 if (old_prog)
4500                         bpf_prog_put(old_prog);
4501
4502                 if (xsk_open) {
4503                         old_prog = xchg(&c->xskrq.xdp_prog, prog);
4504                         if (old_prog)
4505                                 bpf_prog_put(old_prog);
4506                 }
4507
4508                 set_bit(MLX5E_RQ_STATE_ENABLED, &c->rq.state);
4509                 if (xsk_open)
4510                         set_bit(MLX5E_RQ_STATE_ENABLED, &c->xskrq.state);
4511                 /* napi_schedule in case we have missed anything */
4512                 napi_schedule(&c->napi);
4513         }
4514
4515 unlock:
4516         mutex_unlock(&priv->state_lock);
4517         return err;
4518 }
4519
4520 static u32 mlx5e_xdp_query(struct net_device *dev)
4521 {
4522         struct mlx5e_priv *priv = netdev_priv(dev);
4523         const struct bpf_prog *xdp_prog;
4524         u32 prog_id = 0;
4525
4526         mutex_lock(&priv->state_lock);
4527         xdp_prog = priv->channels.params.xdp_prog;
4528         if (xdp_prog)
4529                 prog_id = xdp_prog->aux->id;
4530         mutex_unlock(&priv->state_lock);
4531
4532         return prog_id;
4533 }
4534
4535 static int mlx5e_xdp(struct net_device *dev, struct netdev_bpf *xdp)
4536 {
4537         switch (xdp->command) {
4538         case XDP_SETUP_PROG:
4539                 return mlx5e_xdp_set(dev, xdp->prog);
4540         case XDP_QUERY_PROG:
4541                 xdp->prog_id = mlx5e_xdp_query(dev);
4542                 return 0;
4543         case XDP_SETUP_XSK_UMEM:
4544                 return mlx5e_xsk_setup_umem(dev, xdp->xsk.umem,
4545                                             xdp->xsk.queue_id);
4546         default:
4547                 return -EINVAL;
4548         }
4549 }
4550
4551 #ifdef CONFIG_MLX5_ESWITCH
4552 static int mlx5e_bridge_getlink(struct sk_buff *skb, u32 pid, u32 seq,
4553                                 struct net_device *dev, u32 filter_mask,
4554                                 int nlflags)
4555 {
4556         struct mlx5e_priv *priv = netdev_priv(dev);
4557         struct mlx5_core_dev *mdev = priv->mdev;
4558         u8 mode, setting;
4559         int err;
4560
4561         err = mlx5_eswitch_get_vepa(mdev->priv.eswitch, &setting);
4562         if (err)
4563                 return err;
4564         mode = setting ? BRIDGE_MODE_VEPA : BRIDGE_MODE_VEB;
4565         return ndo_dflt_bridge_getlink(skb, pid, seq, dev,
4566                                        mode,
4567                                        0, 0, nlflags, filter_mask, NULL);
4568 }
4569
4570 static int mlx5e_bridge_setlink(struct net_device *dev, struct nlmsghdr *nlh,
4571                                 u16 flags, struct netlink_ext_ack *extack)
4572 {
4573         struct mlx5e_priv *priv = netdev_priv(dev);
4574         struct mlx5_core_dev *mdev = priv->mdev;
4575         struct nlattr *attr, *br_spec;
4576         u16 mode = BRIDGE_MODE_UNDEF;
4577         u8 setting;
4578         int rem;
4579
4580         br_spec = nlmsg_find_attr(nlh, sizeof(struct ifinfomsg), IFLA_AF_SPEC);
4581         if (!br_spec)
4582                 return -EINVAL;
4583
4584         nla_for_each_nested(attr, br_spec, rem) {
4585                 if (nla_type(attr) != IFLA_BRIDGE_MODE)
4586                         continue;
4587
4588                 if (nla_len(attr) < sizeof(mode))
4589                         return -EINVAL;
4590
4591                 mode = nla_get_u16(attr);
4592                 if (mode > BRIDGE_MODE_VEPA)
4593                         return -EINVAL;
4594
4595                 break;
4596         }
4597
4598         if (mode == BRIDGE_MODE_UNDEF)
4599                 return -EINVAL;
4600
4601         setting = (mode == BRIDGE_MODE_VEPA) ?  1 : 0;
4602         return mlx5_eswitch_set_vepa(mdev->priv.eswitch, setting);
4603 }
4604 #endif
4605
4606 const struct net_device_ops mlx5e_netdev_ops = {
4607         .ndo_open                = mlx5e_open,
4608         .ndo_stop                = mlx5e_close,
4609         .ndo_start_xmit          = mlx5e_xmit,
4610         .ndo_setup_tc            = mlx5e_setup_tc,
4611         .ndo_select_queue        = mlx5e_select_queue,
4612         .ndo_get_stats64         = mlx5e_get_stats,
4613         .ndo_set_rx_mode         = mlx5e_set_rx_mode,
4614         .ndo_set_mac_address     = mlx5e_set_mac,
4615         .ndo_vlan_rx_add_vid     = mlx5e_vlan_rx_add_vid,
4616         .ndo_vlan_rx_kill_vid    = mlx5e_vlan_rx_kill_vid,
4617         .ndo_set_features        = mlx5e_set_features,
4618         .ndo_fix_features        = mlx5e_fix_features,
4619         .ndo_change_mtu          = mlx5e_change_nic_mtu,
4620         .ndo_do_ioctl            = mlx5e_ioctl,
4621         .ndo_set_tx_maxrate      = mlx5e_set_tx_maxrate,
4622         .ndo_udp_tunnel_add      = mlx5e_add_vxlan_port,
4623         .ndo_udp_tunnel_del      = mlx5e_del_vxlan_port,
4624         .ndo_features_check      = mlx5e_features_check,
4625         .ndo_tx_timeout          = mlx5e_tx_timeout,
4626         .ndo_bpf                 = mlx5e_xdp,
4627         .ndo_xdp_xmit            = mlx5e_xdp_xmit,
4628         .ndo_xsk_wakeup          = mlx5e_xsk_wakeup,
4629 #ifdef CONFIG_MLX5_EN_ARFS
4630         .ndo_rx_flow_steer       = mlx5e_rx_flow_steer,
4631 #endif
4632 #ifdef CONFIG_MLX5_ESWITCH
4633         .ndo_bridge_setlink      = mlx5e_bridge_setlink,
4634         .ndo_bridge_getlink      = mlx5e_bridge_getlink,
4635
4636         /* SRIOV E-Switch NDOs */
4637         .ndo_set_vf_mac          = mlx5e_set_vf_mac,
4638         .ndo_set_vf_vlan         = mlx5e_set_vf_vlan,
4639         .ndo_set_vf_spoofchk     = mlx5e_set_vf_spoofchk,
4640         .ndo_set_vf_trust        = mlx5e_set_vf_trust,
4641         .ndo_set_vf_rate         = mlx5e_set_vf_rate,
4642         .ndo_get_vf_config       = mlx5e_get_vf_config,
4643         .ndo_set_vf_link_state   = mlx5e_set_vf_link_state,
4644         .ndo_get_vf_stats        = mlx5e_get_vf_stats,
4645 #endif
4646         .ndo_get_devlink_port    = mlx5e_get_devlink_port,
4647 };
4648
4649 static int mlx5e_check_required_hca_cap(struct mlx5_core_dev *mdev)
4650 {
4651         if (MLX5_CAP_GEN(mdev, port_type) != MLX5_CAP_PORT_TYPE_ETH)
4652                 return -EOPNOTSUPP;
4653         if (!MLX5_CAP_GEN(mdev, eth_net_offloads) ||
4654             !MLX5_CAP_GEN(mdev, nic_flow_table) ||
4655             !MLX5_CAP_ETH(mdev, csum_cap) ||
4656             !MLX5_CAP_ETH(mdev, max_lso_cap) ||
4657             !MLX5_CAP_ETH(mdev, vlan_cap) ||
4658             !MLX5_CAP_ETH(mdev, rss_ind_tbl_cap) ||
4659             MLX5_CAP_FLOWTABLE(mdev,
4660                                flow_table_properties_nic_receive.max_ft_level)
4661                                < 3) {
4662                 mlx5_core_warn(mdev,
4663                                "Not creating net device, some required device capabilities are missing\n");
4664                 return -EOPNOTSUPP;
4665         }
4666         if (!MLX5_CAP_ETH(mdev, self_lb_en_modifiable))
4667                 mlx5_core_warn(mdev, "Self loop back prevention is not supported\n");
4668         if (!MLX5_CAP_GEN(mdev, cq_moderation))
4669                 mlx5_core_warn(mdev, "CQ moderation is not supported\n");
4670
4671         return 0;
4672 }
4673
4674 void mlx5e_build_default_indir_rqt(u32 *indirection_rqt, int len,
4675                                    int num_channels)
4676 {
4677         int i;
4678
4679         for (i = 0; i < len; i++)
4680                 indirection_rqt[i] = i % num_channels;
4681 }
4682
4683 static bool slow_pci_heuristic(struct mlx5_core_dev *mdev)
4684 {
4685         u32 link_speed = 0;
4686         u32 pci_bw = 0;
4687
4688         mlx5e_port_max_linkspeed(mdev, &link_speed);
4689         pci_bw = pcie_bandwidth_available(mdev->pdev, NULL, NULL, NULL);
4690         mlx5_core_dbg_once(mdev, "Max link speed = %d, PCI BW = %d\n",
4691                            link_speed, pci_bw);
4692
4693 #define MLX5E_SLOW_PCI_RATIO (2)
4694
4695         return link_speed && pci_bw &&
4696                 link_speed > MLX5E_SLOW_PCI_RATIO * pci_bw;
4697 }
4698
4699 static struct dim_cq_moder mlx5e_get_def_tx_moderation(u8 cq_period_mode)
4700 {
4701         struct dim_cq_moder moder;
4702
4703         moder.cq_period_mode = cq_period_mode;
4704         moder.pkts = MLX5E_PARAMS_DEFAULT_TX_CQ_MODERATION_PKTS;
4705         moder.usec = MLX5E_PARAMS_DEFAULT_TX_CQ_MODERATION_USEC;
4706         if (cq_period_mode == MLX5_CQ_PERIOD_MODE_START_FROM_CQE)
4707                 moder.usec = MLX5E_PARAMS_DEFAULT_TX_CQ_MODERATION_USEC_FROM_CQE;
4708
4709         return moder;
4710 }
4711
4712 static struct dim_cq_moder mlx5e_get_def_rx_moderation(u8 cq_period_mode)
4713 {
4714         struct dim_cq_moder moder;
4715
4716         moder.cq_period_mode = cq_period_mode;
4717         moder.pkts = MLX5E_PARAMS_DEFAULT_RX_CQ_MODERATION_PKTS;
4718         moder.usec = MLX5E_PARAMS_DEFAULT_RX_CQ_MODERATION_USEC;
4719         if (cq_period_mode == MLX5_CQ_PERIOD_MODE_START_FROM_CQE)
4720                 moder.usec = MLX5E_PARAMS_DEFAULT_RX_CQ_MODERATION_USEC_FROM_CQE;
4721
4722         return moder;
4723 }
4724
4725 static u8 mlx5_to_net_dim_cq_period_mode(u8 cq_period_mode)
4726 {
4727         return cq_period_mode == MLX5_CQ_PERIOD_MODE_START_FROM_CQE ?
4728                 DIM_CQ_PERIOD_MODE_START_FROM_CQE :
4729                 DIM_CQ_PERIOD_MODE_START_FROM_EQE;
4730 }
4731
4732 void mlx5e_reset_tx_moderation(struct mlx5e_params *params, u8 cq_period_mode)
4733 {
4734         if (params->tx_dim_enabled) {
4735                 u8 dim_period_mode = mlx5_to_net_dim_cq_period_mode(cq_period_mode);
4736
4737                 params->tx_cq_moderation = net_dim_get_def_tx_moderation(dim_period_mode);
4738         } else {
4739                 params->tx_cq_moderation = mlx5e_get_def_tx_moderation(cq_period_mode);
4740         }
4741 }
4742
4743 void mlx5e_reset_rx_moderation(struct mlx5e_params *params, u8 cq_period_mode)
4744 {
4745         if (params->rx_dim_enabled) {
4746                 u8 dim_period_mode = mlx5_to_net_dim_cq_period_mode(cq_period_mode);
4747
4748                 params->rx_cq_moderation = net_dim_get_def_rx_moderation(dim_period_mode);
4749         } else {
4750                 params->rx_cq_moderation = mlx5e_get_def_rx_moderation(cq_period_mode);
4751         }
4752 }
4753
4754 void mlx5e_set_tx_cq_mode_params(struct mlx5e_params *params, u8 cq_period_mode)
4755 {
4756         mlx5e_reset_tx_moderation(params, cq_period_mode);
4757         MLX5E_SET_PFLAG(params, MLX5E_PFLAG_TX_CQE_BASED_MODER,
4758                         params->tx_cq_moderation.cq_period_mode ==
4759                                 MLX5_CQ_PERIOD_MODE_START_FROM_CQE);
4760 }
4761
4762 void mlx5e_set_rx_cq_mode_params(struct mlx5e_params *params, u8 cq_period_mode)
4763 {
4764         mlx5e_reset_rx_moderation(params, cq_period_mode);
4765         MLX5E_SET_PFLAG(params, MLX5E_PFLAG_RX_CQE_BASED_MODER,
4766                         params->rx_cq_moderation.cq_period_mode ==
4767                                 MLX5_CQ_PERIOD_MODE_START_FROM_CQE);
4768 }
4769
4770 static u32 mlx5e_choose_lro_timeout(struct mlx5_core_dev *mdev, u32 wanted_timeout)
4771 {
4772         int i;
4773
4774         /* The supported periods are organized in ascending order */
4775         for (i = 0; i < MLX5E_LRO_TIMEOUT_ARR_SIZE - 1; i++)
4776                 if (MLX5_CAP_ETH(mdev, lro_timer_supported_periods[i]) >= wanted_timeout)
4777                         break;
4778
4779         return MLX5_CAP_ETH(mdev, lro_timer_supported_periods[i]);
4780 }
4781
4782 void mlx5e_build_rq_params(struct mlx5_core_dev *mdev,
4783                            struct mlx5e_params *params)
4784 {
4785         /* Prefer Striding RQ, unless any of the following holds:
4786          * - Striding RQ configuration is not possible/supported.
4787          * - Slow PCI heuristic.
4788          * - Legacy RQ would use linear SKB while Striding RQ would use non-linear.
4789          *
4790          * No XSK params: checking the availability of striding RQ in general.
4791          */
4792         if (!slow_pci_heuristic(mdev) &&
4793             mlx5e_striding_rq_possible(mdev, params) &&
4794             (mlx5e_rx_mpwqe_is_linear_skb(mdev, params, NULL) ||
4795              !mlx5e_rx_is_linear_skb(params, NULL)))
4796                 MLX5E_SET_PFLAG(params, MLX5E_PFLAG_RX_STRIDING_RQ, true);
4797         mlx5e_set_rq_type(mdev, params);
4798         mlx5e_init_rq_type_params(mdev, params);
4799 }
4800
4801 void mlx5e_build_rss_params(struct mlx5e_rss_params *rss_params,
4802                             u16 num_channels)
4803 {
4804         enum mlx5e_traffic_types tt;
4805
4806         rss_params->hfunc = ETH_RSS_HASH_TOP;
4807         netdev_rss_key_fill(rss_params->toeplitz_hash_key,
4808                             sizeof(rss_params->toeplitz_hash_key));
4809         mlx5e_build_default_indir_rqt(rss_params->indirection_rqt,
4810                                       MLX5E_INDIR_RQT_SIZE, num_channels);
4811         for (tt = 0; tt < MLX5E_NUM_INDIR_TIRS; tt++)
4812                 rss_params->rx_hash_fields[tt] =
4813                         tirc_default_config[tt].rx_hash_fields;
4814 }
4815
4816 void mlx5e_build_nic_params(struct mlx5e_priv *priv,
4817                             struct mlx5e_xsk *xsk,
4818                             struct mlx5e_rss_params *rss_params,
4819                             struct mlx5e_params *params,
4820                             u16 mtu)
4821 {
4822         struct mlx5_core_dev *mdev = priv->mdev;
4823         u8 rx_cq_period_mode;
4824
4825         params->sw_mtu = mtu;
4826         params->hard_mtu = MLX5E_ETH_HARD_MTU;
4827         params->num_channels = min_t(unsigned int, MLX5E_MAX_NUM_CHANNELS / 2,
4828                                      priv->max_nch);
4829         params->num_tc       = 1;
4830
4831         /* SQ */
4832         params->log_sq_size = is_kdump_kernel() ?
4833                 MLX5E_PARAMS_MINIMUM_LOG_SQ_SIZE :
4834                 MLX5E_PARAMS_DEFAULT_LOG_SQ_SIZE;
4835
4836         /* XDP SQ */
4837         MLX5E_SET_PFLAG(params, MLX5E_PFLAG_XDP_TX_MPWQE,
4838                         MLX5_CAP_ETH(mdev, enhanced_multi_pkt_send_wqe));
4839
4840         /* set CQE compression */
4841         params->rx_cqe_compress_def = false;
4842         if (MLX5_CAP_GEN(mdev, cqe_compression) &&
4843             MLX5_CAP_GEN(mdev, vport_group_manager))
4844                 params->rx_cqe_compress_def = slow_pci_heuristic(mdev);
4845
4846         MLX5E_SET_PFLAG(params, MLX5E_PFLAG_RX_CQE_COMPRESS, params->rx_cqe_compress_def);
4847         MLX5E_SET_PFLAG(params, MLX5E_PFLAG_RX_NO_CSUM_COMPLETE, false);
4848
4849         /* RQ */
4850         mlx5e_build_rq_params(mdev, params);
4851
4852         /* HW LRO */
4853         if (MLX5_CAP_ETH(mdev, lro_cap) &&
4854             params->rq_wq_type == MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ) {
4855                 /* No XSK params: checking the availability of striding RQ in general. */
4856                 if (!mlx5e_rx_mpwqe_is_linear_skb(mdev, params, NULL))
4857                         params->lro_en = !slow_pci_heuristic(mdev);
4858         }
4859         params->lro_timeout = mlx5e_choose_lro_timeout(mdev, MLX5E_DEFAULT_LRO_TIMEOUT);
4860
4861         /* CQ moderation params */
4862         rx_cq_period_mode = MLX5_CAP_GEN(mdev, cq_period_start_from_cqe) ?
4863                         MLX5_CQ_PERIOD_MODE_START_FROM_CQE :
4864                         MLX5_CQ_PERIOD_MODE_START_FROM_EQE;
4865         params->rx_dim_enabled = MLX5_CAP_GEN(mdev, cq_moderation);
4866         params->tx_dim_enabled = MLX5_CAP_GEN(mdev, cq_moderation);
4867         mlx5e_set_rx_cq_mode_params(params, rx_cq_period_mode);
4868         mlx5e_set_tx_cq_mode_params(params, MLX5_CQ_PERIOD_MODE_START_FROM_EQE);
4869
4870         /* TX inline */
4871         mlx5_query_min_inline(mdev, &params->tx_min_inline_mode);
4872
4873         /* RSS */
4874         mlx5e_build_rss_params(rss_params, params->num_channels);
4875         params->tunneled_offload_en =
4876                 mlx5e_tunnel_inner_ft_supported(mdev);
4877
4878         /* AF_XDP */
4879         params->xsk = xsk;
4880 }
4881
4882 static void mlx5e_set_netdev_dev_addr(struct net_device *netdev)
4883 {
4884         struct mlx5e_priv *priv = netdev_priv(netdev);
4885
4886         mlx5_query_mac_address(priv->mdev, netdev->dev_addr);
4887         if (is_zero_ether_addr(netdev->dev_addr) &&
4888             !MLX5_CAP_GEN(priv->mdev, vport_group_manager)) {
4889                 eth_hw_addr_random(netdev);
4890                 mlx5_core_info(priv->mdev, "Assigned random MAC address %pM\n", netdev->dev_addr);
4891         }
4892 }
4893
4894 static void mlx5e_build_nic_netdev(struct net_device *netdev)
4895 {
4896         struct mlx5e_priv *priv = netdev_priv(netdev);
4897         struct mlx5_core_dev *mdev = priv->mdev;
4898         bool fcs_supported;
4899         bool fcs_enabled;
4900
4901         SET_NETDEV_DEV(netdev, mdev->device);
4902
4903         netdev->netdev_ops = &mlx5e_netdev_ops;
4904
4905         mlx5e_dcbnl_build_netdev(netdev);
4906
4907         netdev->watchdog_timeo    = 15 * HZ;
4908
4909         netdev->ethtool_ops       = &mlx5e_ethtool_ops;
4910
4911         netdev->vlan_features    |= NETIF_F_SG;
4912         netdev->vlan_features    |= NETIF_F_HW_CSUM;
4913         netdev->vlan_features    |= NETIF_F_GRO;
4914         netdev->vlan_features    |= NETIF_F_TSO;
4915         netdev->vlan_features    |= NETIF_F_TSO6;
4916         netdev->vlan_features    |= NETIF_F_RXCSUM;
4917         netdev->vlan_features    |= NETIF_F_RXHASH;
4918
4919         netdev->mpls_features    |= NETIF_F_SG;
4920         netdev->mpls_features    |= NETIF_F_HW_CSUM;
4921         netdev->mpls_features    |= NETIF_F_TSO;
4922         netdev->mpls_features    |= NETIF_F_TSO6;
4923
4924         netdev->hw_enc_features  |= NETIF_F_HW_VLAN_CTAG_TX;
4925         netdev->hw_enc_features  |= NETIF_F_HW_VLAN_CTAG_RX;
4926
4927         if (!!MLX5_CAP_ETH(mdev, lro_cap) &&
4928             mlx5e_check_fragmented_striding_rq_cap(mdev))
4929                 netdev->vlan_features    |= NETIF_F_LRO;
4930
4931         netdev->hw_features       = netdev->vlan_features;
4932         netdev->hw_features      |= NETIF_F_HW_VLAN_CTAG_TX;
4933         netdev->hw_features      |= NETIF_F_HW_VLAN_CTAG_RX;
4934         netdev->hw_features      |= NETIF_F_HW_VLAN_CTAG_FILTER;
4935         netdev->hw_features      |= NETIF_F_HW_VLAN_STAG_TX;
4936
4937         if (mlx5_vxlan_allowed(mdev->vxlan) || mlx5_geneve_tx_allowed(mdev) ||
4938             mlx5e_any_tunnel_proto_supported(mdev)) {
4939                 netdev->hw_enc_features |= NETIF_F_HW_CSUM;
4940                 netdev->hw_enc_features |= NETIF_F_TSO;
4941                 netdev->hw_enc_features |= NETIF_F_TSO6;
4942                 netdev->hw_enc_features |= NETIF_F_GSO_PARTIAL;
4943         }
4944
4945         if (mlx5_vxlan_allowed(mdev->vxlan) || mlx5_geneve_tx_allowed(mdev)) {
4946                 netdev->hw_features     |= NETIF_F_GSO_UDP_TUNNEL |
4947                                            NETIF_F_GSO_UDP_TUNNEL_CSUM;
4948                 netdev->hw_enc_features |= NETIF_F_GSO_UDP_TUNNEL |
4949                                            NETIF_F_GSO_UDP_TUNNEL_CSUM;
4950                 netdev->gso_partial_features = NETIF_F_GSO_UDP_TUNNEL_CSUM;
4951                 netdev->vlan_features |= NETIF_F_GSO_UDP_TUNNEL |
4952                                          NETIF_F_GSO_UDP_TUNNEL_CSUM;
4953         }
4954
4955         if (mlx5e_tunnel_proto_supported(mdev, IPPROTO_GRE)) {
4956                 netdev->hw_features     |= NETIF_F_GSO_GRE |
4957                                            NETIF_F_GSO_GRE_CSUM;
4958                 netdev->hw_enc_features |= NETIF_F_GSO_GRE |
4959                                            NETIF_F_GSO_GRE_CSUM;
4960                 netdev->gso_partial_features |= NETIF_F_GSO_GRE |
4961                                                 NETIF_F_GSO_GRE_CSUM;
4962         }
4963
4964         if (mlx5e_tunnel_proto_supported(mdev, IPPROTO_IPIP)) {
4965                 netdev->hw_features |= NETIF_F_GSO_IPXIP4 |
4966                                        NETIF_F_GSO_IPXIP6;
4967                 netdev->hw_enc_features |= NETIF_F_GSO_IPXIP4 |
4968                                            NETIF_F_GSO_IPXIP6;
4969                 netdev->gso_partial_features |= NETIF_F_GSO_IPXIP4 |
4970                                                 NETIF_F_GSO_IPXIP6;
4971         }
4972
4973         netdev->hw_features                      |= NETIF_F_GSO_PARTIAL;
4974         netdev->gso_partial_features             |= NETIF_F_GSO_UDP_L4;
4975         netdev->hw_features                      |= NETIF_F_GSO_UDP_L4;
4976         netdev->features                         |= NETIF_F_GSO_UDP_L4;
4977
4978         mlx5_query_port_fcs(mdev, &fcs_supported, &fcs_enabled);
4979
4980         if (fcs_supported)
4981                 netdev->hw_features |= NETIF_F_RXALL;
4982
4983         if (MLX5_CAP_ETH(mdev, scatter_fcs))
4984                 netdev->hw_features |= NETIF_F_RXFCS;
4985
4986         netdev->features          = netdev->hw_features;
4987         if (!priv->channels.params.lro_en)
4988                 netdev->features  &= ~NETIF_F_LRO;
4989
4990         if (fcs_enabled)
4991                 netdev->features  &= ~NETIF_F_RXALL;
4992
4993         if (!priv->channels.params.scatter_fcs_en)
4994                 netdev->features  &= ~NETIF_F_RXFCS;
4995
4996         /* prefere CQE compression over rxhash */
4997         if (MLX5E_GET_PFLAG(&priv->channels.params, MLX5E_PFLAG_RX_CQE_COMPRESS))
4998                 netdev->features &= ~NETIF_F_RXHASH;
4999
5000 #define FT_CAP(f) MLX5_CAP_FLOWTABLE(mdev, flow_table_properties_nic_receive.f)
5001         if (FT_CAP(flow_modify_en) &&
5002             FT_CAP(modify_root) &&
5003             FT_CAP(identified_miss_table_mode) &&
5004             FT_CAP(flow_table_modify)) {
5005 #ifdef CONFIG_MLX5_ESWITCH
5006                 netdev->hw_features      |= NETIF_F_HW_TC;
5007 #endif
5008 #ifdef CONFIG_MLX5_EN_ARFS
5009                 netdev->hw_features      |= NETIF_F_NTUPLE;
5010 #endif
5011         }
5012
5013         netdev->features         |= NETIF_F_HIGHDMA;
5014         netdev->features         |= NETIF_F_HW_VLAN_STAG_FILTER;
5015
5016         netdev->priv_flags       |= IFF_UNICAST_FLT;
5017
5018         mlx5e_set_netdev_dev_addr(netdev);
5019         mlx5e_ipsec_build_netdev(priv);
5020         mlx5e_tls_build_netdev(priv);
5021 }
5022
5023 void mlx5e_create_q_counters(struct mlx5e_priv *priv)
5024 {
5025         u32 out[MLX5_ST_SZ_DW(alloc_q_counter_out)] = {};
5026         u32 in[MLX5_ST_SZ_DW(alloc_q_counter_in)] = {};
5027         struct mlx5_core_dev *mdev = priv->mdev;
5028         int err;
5029
5030         MLX5_SET(alloc_q_counter_in, in, opcode, MLX5_CMD_OP_ALLOC_Q_COUNTER);
5031         err = mlx5_cmd_exec_inout(mdev, alloc_q_counter, in, out);
5032         if (!err)
5033                 priv->q_counter =
5034                         MLX5_GET(alloc_q_counter_out, out, counter_set_id);
5035
5036         err = mlx5_cmd_exec_inout(mdev, alloc_q_counter, in, out);
5037         if (!err)
5038                 priv->drop_rq_q_counter =
5039                         MLX5_GET(alloc_q_counter_out, out, counter_set_id);
5040 }
5041
5042 void mlx5e_destroy_q_counters(struct mlx5e_priv *priv)
5043 {
5044         u32 in[MLX5_ST_SZ_DW(dealloc_q_counter_in)] = {};
5045
5046         MLX5_SET(dealloc_q_counter_in, in, opcode,
5047                  MLX5_CMD_OP_DEALLOC_Q_COUNTER);
5048         if (priv->q_counter) {
5049                 MLX5_SET(dealloc_q_counter_in, in, counter_set_id,
5050                          priv->q_counter);
5051                 mlx5_cmd_exec_in(priv->mdev, dealloc_q_counter, in);
5052         }
5053
5054         if (priv->drop_rq_q_counter) {
5055                 MLX5_SET(dealloc_q_counter_in, in, counter_set_id,
5056                          priv->drop_rq_q_counter);
5057                 mlx5_cmd_exec_in(priv->mdev, dealloc_q_counter, in);
5058         }
5059 }
5060
5061 static int mlx5e_nic_init(struct mlx5_core_dev *mdev,
5062                           struct net_device *netdev,
5063                           const struct mlx5e_profile *profile,
5064                           void *ppriv)
5065 {
5066         struct mlx5e_priv *priv = netdev_priv(netdev);
5067         struct mlx5e_rss_params *rss = &priv->rss_params;
5068         int err;
5069
5070         err = mlx5e_netdev_init(netdev, priv, mdev, profile, ppriv);
5071         if (err)
5072                 return err;
5073
5074         mlx5e_build_nic_params(priv, &priv->xsk, rss, &priv->channels.params,
5075                                netdev->mtu);
5076
5077         mlx5e_timestamp_init(priv);
5078
5079         err = mlx5e_ipsec_init(priv);
5080         if (err)
5081                 mlx5_core_err(mdev, "IPSec initialization failed, %d\n", err);
5082         err = mlx5e_tls_init(priv);
5083         if (err)
5084                 mlx5_core_err(mdev, "TLS initialization failed, %d\n", err);
5085         mlx5e_build_nic_netdev(netdev);
5086         mlx5e_health_create_reporters(priv);
5087
5088         return 0;
5089 }
5090
5091 static void mlx5e_nic_cleanup(struct mlx5e_priv *priv)
5092 {
5093         mlx5e_health_destroy_reporters(priv);
5094         mlx5e_tls_cleanup(priv);
5095         mlx5e_ipsec_cleanup(priv);
5096         mlx5e_netdev_cleanup(priv->netdev, priv);
5097 }
5098
5099 static int mlx5e_init_nic_rx(struct mlx5e_priv *priv)
5100 {
5101         struct mlx5_core_dev *mdev = priv->mdev;
5102         int err;
5103
5104         mlx5e_create_q_counters(priv);
5105
5106         err = mlx5e_open_drop_rq(priv, &priv->drop_rq);
5107         if (err) {
5108                 mlx5_core_err(mdev, "open drop rq failed, %d\n", err);
5109                 goto err_destroy_q_counters;
5110         }
5111
5112         err = mlx5e_create_indirect_rqt(priv);
5113         if (err)
5114                 goto err_close_drop_rq;
5115
5116         err = mlx5e_create_direct_rqts(priv, priv->direct_tir);
5117         if (err)
5118                 goto err_destroy_indirect_rqts;
5119
5120         err = mlx5e_create_indirect_tirs(priv, true);
5121         if (err)
5122                 goto err_destroy_direct_rqts;
5123
5124         err = mlx5e_create_direct_tirs(priv, priv->direct_tir);
5125         if (err)
5126                 goto err_destroy_indirect_tirs;
5127
5128         err = mlx5e_create_direct_rqts(priv, priv->xsk_tir);
5129         if (unlikely(err))
5130                 goto err_destroy_direct_tirs;
5131
5132         err = mlx5e_create_direct_tirs(priv, priv->xsk_tir);
5133         if (unlikely(err))
5134                 goto err_destroy_xsk_rqts;
5135
5136         err = mlx5e_create_flow_steering(priv);
5137         if (err) {
5138                 mlx5_core_warn(mdev, "create flow steering failed, %d\n", err);
5139                 goto err_destroy_xsk_tirs;
5140         }
5141
5142         err = mlx5e_tc_nic_init(priv);
5143         if (err)
5144                 goto err_destroy_flow_steering;
5145
5146         return 0;
5147
5148 err_destroy_flow_steering:
5149         mlx5e_destroy_flow_steering(priv);
5150 err_destroy_xsk_tirs:
5151         mlx5e_destroy_direct_tirs(priv, priv->xsk_tir);
5152 err_destroy_xsk_rqts:
5153         mlx5e_destroy_direct_rqts(priv, priv->xsk_tir);
5154 err_destroy_direct_tirs:
5155         mlx5e_destroy_direct_tirs(priv, priv->direct_tir);
5156 err_destroy_indirect_tirs:
5157         mlx5e_destroy_indirect_tirs(priv);
5158 err_destroy_direct_rqts:
5159         mlx5e_destroy_direct_rqts(priv, priv->direct_tir);
5160 err_destroy_indirect_rqts:
5161         mlx5e_destroy_rqt(priv, &priv->indir_rqt);
5162 err_close_drop_rq:
5163         mlx5e_close_drop_rq(&priv->drop_rq);
5164 err_destroy_q_counters:
5165         mlx5e_destroy_q_counters(priv);
5166         return err;
5167 }
5168
5169 static void mlx5e_cleanup_nic_rx(struct mlx5e_priv *priv)
5170 {
5171         mlx5e_tc_nic_cleanup(priv);
5172         mlx5e_destroy_flow_steering(priv);
5173         mlx5e_destroy_direct_tirs(priv, priv->xsk_tir);
5174         mlx5e_destroy_direct_rqts(priv, priv->xsk_tir);
5175         mlx5e_destroy_direct_tirs(priv, priv->direct_tir);
5176         mlx5e_destroy_indirect_tirs(priv);
5177         mlx5e_destroy_direct_rqts(priv, priv->direct_tir);
5178         mlx5e_destroy_rqt(priv, &priv->indir_rqt);
5179         mlx5e_close_drop_rq(&priv->drop_rq);
5180         mlx5e_destroy_q_counters(priv);
5181 }
5182
5183 static int mlx5e_init_nic_tx(struct mlx5e_priv *priv)
5184 {
5185         int err;
5186
5187         err = mlx5e_create_tises(priv);
5188         if (err) {
5189                 mlx5_core_warn(priv->mdev, "create tises failed, %d\n", err);
5190                 return err;
5191         }
5192
5193         mlx5e_dcbnl_initialize(priv);
5194         return 0;
5195 }
5196
5197 static void mlx5e_nic_enable(struct mlx5e_priv *priv)
5198 {
5199         struct net_device *netdev = priv->netdev;
5200         struct mlx5_core_dev *mdev = priv->mdev;
5201
5202         mlx5e_init_l2_addr(priv);
5203
5204         /* Marking the link as currently not needed by the Driver */
5205         if (!netif_running(netdev))
5206                 mlx5_set_port_admin_status(mdev, MLX5_PORT_DOWN);
5207
5208         mlx5e_set_netdev_mtu_boundaries(priv);
5209         mlx5e_set_dev_port_mtu(priv);
5210
5211         mlx5_lag_add(mdev, netdev);
5212
5213         mlx5e_enable_async_events(priv);
5214         if (mlx5e_monitor_counter_supported(priv))
5215                 mlx5e_monitor_counter_init(priv);
5216
5217         mlx5e_hv_vhca_stats_create(priv);
5218         if (netdev->reg_state != NETREG_REGISTERED)
5219                 return;
5220         mlx5e_dcbnl_init_app(priv);
5221
5222         queue_work(priv->wq, &priv->set_rx_mode_work);
5223
5224         rtnl_lock();
5225         if (netif_running(netdev))
5226                 mlx5e_open(netdev);
5227         netif_device_attach(netdev);
5228         rtnl_unlock();
5229 }
5230
5231 static void mlx5e_nic_disable(struct mlx5e_priv *priv)
5232 {
5233         struct mlx5_core_dev *mdev = priv->mdev;
5234
5235         if (priv->netdev->reg_state == NETREG_REGISTERED)
5236                 mlx5e_dcbnl_delete_app(priv);
5237
5238         rtnl_lock();
5239         if (netif_running(priv->netdev))
5240                 mlx5e_close(priv->netdev);
5241         netif_device_detach(priv->netdev);
5242         rtnl_unlock();
5243
5244         queue_work(priv->wq, &priv->set_rx_mode_work);
5245
5246         mlx5e_hv_vhca_stats_destroy(priv);
5247         if (mlx5e_monitor_counter_supported(priv))
5248                 mlx5e_monitor_counter_cleanup(priv);
5249
5250         mlx5e_disable_async_events(priv);
5251         mlx5_lag_remove(mdev);
5252 }
5253
5254 int mlx5e_update_nic_rx(struct mlx5e_priv *priv)
5255 {
5256         return mlx5e_refresh_tirs(priv, false, false);
5257 }
5258
5259 static const struct mlx5e_profile mlx5e_nic_profile = {
5260         .init              = mlx5e_nic_init,
5261         .cleanup           = mlx5e_nic_cleanup,
5262         .init_rx           = mlx5e_init_nic_rx,
5263         .cleanup_rx        = mlx5e_cleanup_nic_rx,
5264         .init_tx           = mlx5e_init_nic_tx,
5265         .cleanup_tx        = mlx5e_cleanup_nic_tx,
5266         .enable            = mlx5e_nic_enable,
5267         .disable           = mlx5e_nic_disable,
5268         .update_rx         = mlx5e_update_nic_rx,
5269         .update_stats      = mlx5e_update_ndo_stats,
5270         .update_carrier    = mlx5e_update_carrier,
5271         .rx_handlers.handle_rx_cqe       = mlx5e_handle_rx_cqe,
5272         .rx_handlers.handle_rx_cqe_mpwqe = mlx5e_handle_rx_cqe_mpwrq,
5273         .max_tc            = MLX5E_MAX_NUM_TC,
5274         .rq_groups         = MLX5E_NUM_RQ_GROUPS(XSK),
5275         .stats_grps        = mlx5e_nic_stats_grps,
5276         .stats_grps_num    = mlx5e_nic_stats_grps_num,
5277 };
5278
5279 /* mlx5e generic netdev management API (move to en_common.c) */
5280
5281 /* mlx5e_netdev_init/cleanup must be called from profile->init/cleanup callbacks */
5282 int mlx5e_netdev_init(struct net_device *netdev,
5283                       struct mlx5e_priv *priv,
5284                       struct mlx5_core_dev *mdev,
5285                       const struct mlx5e_profile *profile,
5286                       void *ppriv)
5287 {
5288         /* priv init */
5289         priv->mdev        = mdev;
5290         priv->netdev      = netdev;
5291         priv->profile     = profile;
5292         priv->ppriv       = ppriv;
5293         priv->msglevel    = MLX5E_MSG_LEVEL;
5294         priv->max_nch     = netdev->num_rx_queues / max_t(u8, profile->rq_groups, 1);
5295         priv->max_opened_tc = 1;
5296
5297         if (!alloc_cpumask_var(&priv->scratchpad.cpumask, GFP_KERNEL))
5298                 return -ENOMEM;
5299
5300         mutex_init(&priv->state_lock);
5301         INIT_WORK(&priv->update_carrier_work, mlx5e_update_carrier_work);
5302         INIT_WORK(&priv->set_rx_mode_work, mlx5e_set_rx_mode_work);
5303         INIT_WORK(&priv->tx_timeout_work, mlx5e_tx_timeout_work);
5304         INIT_WORK(&priv->update_stats_work, mlx5e_update_stats_work);
5305
5306         priv->wq = create_singlethread_workqueue("mlx5e");
5307         if (!priv->wq)
5308                 goto err_free_cpumask;
5309
5310         /* netdev init */
5311         netif_carrier_off(netdev);
5312
5313 #ifdef CONFIG_MLX5_EN_ARFS
5314         netdev->rx_cpu_rmap =  mlx5_eq_table_get_rmap(mdev);
5315 #endif
5316
5317         return 0;
5318
5319 err_free_cpumask:
5320         free_cpumask_var(priv->scratchpad.cpumask);
5321
5322         return -ENOMEM;
5323 }
5324
5325 void mlx5e_netdev_cleanup(struct net_device *netdev, struct mlx5e_priv *priv)
5326 {
5327         destroy_workqueue(priv->wq);
5328         free_cpumask_var(priv->scratchpad.cpumask);
5329 }
5330
5331 struct net_device *mlx5e_create_netdev(struct mlx5_core_dev *mdev,
5332                                        const struct mlx5e_profile *profile,
5333                                        int nch,
5334                                        void *ppriv)
5335 {
5336         struct net_device *netdev;
5337         int err;
5338
5339         netdev = alloc_etherdev_mqs(sizeof(struct mlx5e_priv),
5340                                     nch * profile->max_tc,
5341                                     nch * profile->rq_groups);
5342         if (!netdev) {
5343                 mlx5_core_err(mdev, "alloc_etherdev_mqs() failed\n");
5344                 return NULL;
5345         }
5346
5347         err = profile->init(mdev, netdev, profile, ppriv);
5348         if (err) {
5349                 mlx5_core_err(mdev, "failed to init mlx5e profile %d\n", err);
5350                 goto err_free_netdev;
5351         }
5352
5353         return netdev;
5354
5355 err_free_netdev:
5356         free_netdev(netdev);
5357
5358         return NULL;
5359 }
5360
5361 int mlx5e_attach_netdev(struct mlx5e_priv *priv)
5362 {
5363         const bool take_rtnl = priv->netdev->reg_state == NETREG_REGISTERED;
5364         const struct mlx5e_profile *profile;
5365         int max_nch;
5366         int err;
5367
5368         profile = priv->profile;
5369         clear_bit(MLX5E_STATE_DESTROYING, &priv->state);
5370
5371         /* max number of channels may have changed */
5372         max_nch = mlx5e_get_max_num_channels(priv->mdev);
5373         if (priv->channels.params.num_channels > max_nch) {
5374                 mlx5_core_warn(priv->mdev, "MLX5E: Reducing number of channels to %d\n", max_nch);
5375                 /* Reducing the number of channels - RXFH has to be reset, and
5376                  * mlx5e_num_channels_changed below will build the RQT.
5377                  */
5378                 priv->netdev->priv_flags &= ~IFF_RXFH_CONFIGURED;
5379                 priv->channels.params.num_channels = max_nch;
5380         }
5381         /* 1. Set the real number of queues in the kernel the first time.
5382          * 2. Set our default XPS cpumask.
5383          * 3. Build the RQT.
5384          *
5385          * rtnl_lock is required by netif_set_real_num_*_queues in case the
5386          * netdev has been registered by this point (if this function was called
5387          * in the reload or resume flow).
5388          */
5389         if (take_rtnl)
5390                 rtnl_lock();
5391         err = mlx5e_num_channels_changed(priv);
5392         if (take_rtnl)
5393                 rtnl_unlock();
5394         if (err)
5395                 goto out;
5396
5397         err = profile->init_tx(priv);
5398         if (err)
5399                 goto out;
5400
5401         err = profile->init_rx(priv);
5402         if (err)
5403                 goto err_cleanup_tx;
5404
5405         if (profile->enable)
5406                 profile->enable(priv);
5407
5408         return 0;
5409
5410 err_cleanup_tx:
5411         profile->cleanup_tx(priv);
5412
5413 out:
5414         return err;
5415 }
5416
5417 void mlx5e_detach_netdev(struct mlx5e_priv *priv)
5418 {
5419         const struct mlx5e_profile *profile = priv->profile;
5420
5421         set_bit(MLX5E_STATE_DESTROYING, &priv->state);
5422
5423         if (profile->disable)
5424                 profile->disable(priv);
5425         flush_workqueue(priv->wq);
5426
5427         profile->cleanup_rx(priv);
5428         profile->cleanup_tx(priv);
5429         cancel_work_sync(&priv->update_stats_work);
5430 }
5431
5432 void mlx5e_destroy_netdev(struct mlx5e_priv *priv)
5433 {
5434         const struct mlx5e_profile *profile = priv->profile;
5435         struct net_device *netdev = priv->netdev;
5436
5437         if (profile->cleanup)
5438                 profile->cleanup(priv);
5439         free_netdev(netdev);
5440 }
5441
5442 /* mlx5e_attach and mlx5e_detach scope should be only creating/destroying
5443  * hardware contexts and to connect it to the current netdev.
5444  */
5445 static int mlx5e_attach(struct mlx5_core_dev *mdev, void *vpriv)
5446 {
5447         struct mlx5e_priv *priv = vpriv;
5448         struct net_device *netdev = priv->netdev;
5449         int err;
5450
5451         if (netif_device_present(netdev))
5452                 return 0;
5453
5454         err = mlx5e_create_mdev_resources(mdev);
5455         if (err)
5456                 return err;
5457
5458         err = mlx5e_attach_netdev(priv);
5459         if (err) {
5460                 mlx5e_destroy_mdev_resources(mdev);
5461                 return err;
5462         }
5463
5464         return 0;
5465 }
5466
5467 static void mlx5e_detach(struct mlx5_core_dev *mdev, void *vpriv)
5468 {
5469         struct mlx5e_priv *priv = vpriv;
5470         struct net_device *netdev = priv->netdev;
5471
5472 #ifdef CONFIG_MLX5_ESWITCH
5473         if (MLX5_ESWITCH_MANAGER(mdev) && vpriv == mdev)
5474                 return;
5475 #endif
5476
5477         if (!netif_device_present(netdev))
5478                 return;
5479
5480         mlx5e_detach_netdev(priv);
5481         mlx5e_destroy_mdev_resources(mdev);
5482 }
5483
5484 static void *mlx5e_add(struct mlx5_core_dev *mdev)
5485 {
5486         struct net_device *netdev;
5487         void *priv;
5488         int err;
5489         int nch;
5490
5491         err = mlx5e_check_required_hca_cap(mdev);
5492         if (err)
5493                 return NULL;
5494
5495 #ifdef CONFIG_MLX5_ESWITCH
5496         if (MLX5_ESWITCH_MANAGER(mdev) &&
5497             mlx5_eswitch_mode(mdev->priv.eswitch) == MLX5_ESWITCH_OFFLOADS) {
5498                 mlx5e_rep_register_vport_reps(mdev);
5499                 return mdev;
5500         }
5501 #endif
5502
5503         nch = mlx5e_get_max_num_channels(mdev);
5504         netdev = mlx5e_create_netdev(mdev, &mlx5e_nic_profile, nch, NULL);
5505         if (!netdev) {
5506                 mlx5_core_err(mdev, "mlx5e_create_netdev failed\n");
5507                 return NULL;
5508         }
5509
5510         dev_net_set(netdev, mlx5_core_net(mdev));
5511         priv = netdev_priv(netdev);
5512
5513         err = mlx5e_attach(mdev, priv);
5514         if (err) {
5515                 mlx5_core_err(mdev, "mlx5e_attach failed, %d\n", err);
5516                 goto err_destroy_netdev;
5517         }
5518
5519         err = mlx5e_devlink_port_register(priv);
5520         if (err) {
5521                 mlx5_core_err(mdev, "mlx5e_devlink_port_register failed, %d\n", err);
5522                 goto err_detach;
5523         }
5524
5525         err = register_netdev(netdev);
5526         if (err) {
5527                 mlx5_core_err(mdev, "register_netdev failed, %d\n", err);
5528                 goto err_devlink_port_unregister;
5529         }
5530
5531         mlx5e_devlink_port_type_eth_set(priv);
5532
5533         mlx5e_dcbnl_init_app(priv);
5534         return priv;
5535
5536 err_devlink_port_unregister:
5537         mlx5e_devlink_port_unregister(priv);
5538 err_detach:
5539         mlx5e_detach(mdev, priv);
5540 err_destroy_netdev:
5541         mlx5e_destroy_netdev(priv);
5542         return NULL;
5543 }
5544
5545 static void mlx5e_remove(struct mlx5_core_dev *mdev, void *vpriv)
5546 {
5547         struct mlx5e_priv *priv;
5548
5549 #ifdef CONFIG_MLX5_ESWITCH
5550         if (MLX5_ESWITCH_MANAGER(mdev) && vpriv == mdev) {
5551                 mlx5e_rep_unregister_vport_reps(mdev);
5552                 return;
5553         }
5554 #endif
5555         priv = vpriv;
5556         mlx5e_dcbnl_delete_app(priv);
5557         unregister_netdev(priv->netdev);
5558         mlx5e_devlink_port_unregister(priv);
5559         mlx5e_detach(mdev, vpriv);
5560         mlx5e_destroy_netdev(priv);
5561 }
5562
5563 static struct mlx5_interface mlx5e_interface = {
5564         .add       = mlx5e_add,
5565         .remove    = mlx5e_remove,
5566         .attach    = mlx5e_attach,
5567         .detach    = mlx5e_detach,
5568         .protocol  = MLX5_INTERFACE_PROTOCOL_ETH,
5569 };
5570
5571 void mlx5e_init(void)
5572 {
5573         mlx5e_ipsec_build_inverse_table();
5574         mlx5e_build_ptys2ethtool_map();
5575         mlx5_register_interface(&mlx5e_interface);
5576 }
5577
5578 void mlx5e_cleanup(void)
5579 {
5580         mlx5_unregister_interface(&mlx5e_interface);
5581 }