2 * Copyright (c) 2015-2016, Mellanox Technologies. All rights reserved.
4 * This software is available to you under a choice of one of two
5 * licenses. You may choose to be licensed under the terms of the GNU
6 * General Public License (GPL) Version 2, available from the file
7 * COPYING in the main directory of this source tree, or the
8 * OpenIB.org BSD license below:
10 * Redistribution and use in source and binary forms, with or
11 * without modification, are permitted provided that the following
14 * - Redistributions of source code must retain the above
15 * copyright notice, this list of conditions and the following
18 * - Redistributions in binary form must reproduce the above
19 * copyright notice, this list of conditions and the following
20 * disclaimer in the documentation and/or other materials
21 * provided with the distribution.
23 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
24 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
25 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
26 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
27 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
28 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
29 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
33 #include <net/tc_act/tc_gact.h>
34 #include <net/pkt_cls.h>
35 #include <linux/mlx5/fs.h>
36 #include <net/vxlan.h>
37 #include <net/geneve.h>
38 #include <linux/bpf.h>
39 #include <linux/if_bridge.h>
40 #include <net/page_pool.h>
41 #include <net/xdp_sock_drv.h>
47 #include "en_accel/ipsec.h"
48 #include "en_accel/en_accel.h"
49 #include "en_accel/tls.h"
50 #include "accel/ipsec.h"
51 #include "accel/tls.h"
52 #include "lib/vxlan.h"
53 #include "lib/clock.h"
57 #include "en/monitor_stats.h"
58 #include "en/health.h"
59 #include "en/params.h"
60 #include "en/xsk/pool.h"
61 #include "en/xsk/setup.h"
62 #include "en/xsk/rx.h"
63 #include "en/xsk/tx.h"
64 #include "en/hv_vhca_stats.h"
65 #include "en/devlink.h"
70 #include "fpga/ipsec.h"
72 bool mlx5e_check_fragmented_striding_rq_cap(struct mlx5_core_dev *mdev)
74 bool striding_rq_umr = MLX5_CAP_GEN(mdev, striding_rq) &&
75 MLX5_CAP_GEN(mdev, umr_ptr_rlky) &&
76 MLX5_CAP_ETH(mdev, reg_umr_sq);
77 u16 max_wqe_sz_cap = MLX5_CAP_GEN(mdev, max_wqe_sz_sq);
78 bool inline_umr = MLX5E_UMR_WQE_INLINE_SZ <= max_wqe_sz_cap;
83 mlx5_core_warn(mdev, "Cannot support Striding RQ: UMR WQE size (%d) exceeds maximum supported (%d).\n",
84 (int)MLX5E_UMR_WQE_INLINE_SZ, max_wqe_sz_cap);
90 void mlx5e_update_carrier(struct mlx5e_priv *priv)
92 struct mlx5_core_dev *mdev = priv->mdev;
95 port_state = mlx5_query_vport_state(mdev,
96 MLX5_VPORT_STATE_OP_MOD_VNIC_VPORT,
99 if (port_state == VPORT_STATE_UP) {
100 netdev_info(priv->netdev, "Link up\n");
101 netif_carrier_on(priv->netdev);
103 netdev_info(priv->netdev, "Link down\n");
104 netif_carrier_off(priv->netdev);
108 static void mlx5e_update_carrier_work(struct work_struct *work)
110 struct mlx5e_priv *priv = container_of(work, struct mlx5e_priv,
111 update_carrier_work);
113 mutex_lock(&priv->state_lock);
114 if (test_bit(MLX5E_STATE_OPENED, &priv->state))
115 if (priv->profile->update_carrier)
116 priv->profile->update_carrier(priv);
117 mutex_unlock(&priv->state_lock);
120 static void mlx5e_update_stats_work(struct work_struct *work)
122 struct mlx5e_priv *priv = container_of(work, struct mlx5e_priv,
125 mutex_lock(&priv->state_lock);
126 priv->profile->update_stats(priv);
127 mutex_unlock(&priv->state_lock);
130 void mlx5e_queue_update_stats(struct mlx5e_priv *priv)
132 if (!priv->profile->update_stats)
135 if (unlikely(test_bit(MLX5E_STATE_DESTROYING, &priv->state)))
138 queue_work(priv->wq, &priv->update_stats_work);
141 static int async_event(struct notifier_block *nb, unsigned long event, void *data)
143 struct mlx5e_priv *priv = container_of(nb, struct mlx5e_priv, events_nb);
144 struct mlx5_eqe *eqe = data;
146 if (event != MLX5_EVENT_TYPE_PORT_CHANGE)
149 switch (eqe->sub_type) {
150 case MLX5_PORT_CHANGE_SUBTYPE_DOWN:
151 case MLX5_PORT_CHANGE_SUBTYPE_ACTIVE:
152 queue_work(priv->wq, &priv->update_carrier_work);
161 static void mlx5e_enable_async_events(struct mlx5e_priv *priv)
163 priv->events_nb.notifier_call = async_event;
164 mlx5_notifier_register(priv->mdev, &priv->events_nb);
167 static void mlx5e_disable_async_events(struct mlx5e_priv *priv)
169 mlx5_notifier_unregister(priv->mdev, &priv->events_nb);
172 static int blocking_event(struct notifier_block *nb, unsigned long event, void *data)
174 struct mlx5e_priv *priv = container_of(nb, struct mlx5e_priv, blocking_events_nb);
178 case MLX5_DRIVER_EVENT_TYPE_TRAP:
179 err = mlx5e_handle_trap_event(priv, data);
182 netdev_warn(priv->netdev, "Sync event: Unknown event %ld\n", event);
188 static void mlx5e_enable_blocking_events(struct mlx5e_priv *priv)
190 priv->blocking_events_nb.notifier_call = blocking_event;
191 mlx5_blocking_notifier_register(priv->mdev, &priv->blocking_events_nb);
194 static void mlx5e_disable_blocking_events(struct mlx5e_priv *priv)
196 mlx5_blocking_notifier_unregister(priv->mdev, &priv->blocking_events_nb);
199 static inline void mlx5e_build_umr_wqe(struct mlx5e_rq *rq,
200 struct mlx5e_icosq *sq,
201 struct mlx5e_umr_wqe *wqe)
203 struct mlx5_wqe_ctrl_seg *cseg = &wqe->ctrl;
204 struct mlx5_wqe_umr_ctrl_seg *ucseg = &wqe->uctrl;
205 u8 ds_cnt = DIV_ROUND_UP(MLX5E_UMR_WQE_INLINE_SZ, MLX5_SEND_WQE_DS);
207 cseg->qpn_ds = cpu_to_be32((sq->sqn << MLX5_WQE_CTRL_QPN_SHIFT) |
209 cseg->umr_mkey = rq->mkey_be;
211 ucseg->flags = MLX5_UMR_TRANSLATION_OFFSET_EN | MLX5_UMR_INLINE;
212 ucseg->xlt_octowords =
213 cpu_to_be16(MLX5_MTT_OCTW(MLX5_MPWRQ_PAGES_PER_WQE));
214 ucseg->mkey_mask = cpu_to_be64(MLX5_MKEY_MASK_FREE);
217 static int mlx5e_rq_alloc_mpwqe_info(struct mlx5e_rq *rq, int node)
219 int wq_sz = mlx5_wq_ll_get_size(&rq->mpwqe.wq);
221 rq->mpwqe.info = kvzalloc_node(array_size(wq_sz,
222 sizeof(*rq->mpwqe.info)),
227 mlx5e_build_umr_wqe(rq, rq->icosq, &rq->mpwqe.umr_wqe);
232 static int mlx5e_create_umr_mkey(struct mlx5_core_dev *mdev,
233 u64 npages, u8 page_shift,
234 struct mlx5_core_mkey *umr_mkey,
235 dma_addr_t filler_addr)
237 struct mlx5_mtt *mtt;
244 inlen = MLX5_ST_SZ_BYTES(create_mkey_in) + sizeof(*mtt) * npages;
246 in = kvzalloc(inlen, GFP_KERNEL);
250 mkc = MLX5_ADDR_OF(create_mkey_in, in, memory_key_mkey_entry);
252 MLX5_SET(mkc, mkc, free, 1);
253 MLX5_SET(mkc, mkc, umr_en, 1);
254 MLX5_SET(mkc, mkc, lw, 1);
255 MLX5_SET(mkc, mkc, lr, 1);
256 MLX5_SET(mkc, mkc, access_mode_1_0, MLX5_MKC_ACCESS_MODE_MTT);
257 mlx5e_mkey_set_relaxed_ordering(mdev, mkc);
258 MLX5_SET(mkc, mkc, qpn, 0xffffff);
259 MLX5_SET(mkc, mkc, pd, mdev->mlx5e_res.hw_objs.pdn);
260 MLX5_SET64(mkc, mkc, len, npages << page_shift);
261 MLX5_SET(mkc, mkc, translations_octword_size,
262 MLX5_MTT_OCTW(npages));
263 MLX5_SET(mkc, mkc, log_page_size, page_shift);
264 MLX5_SET(create_mkey_in, in, translations_octword_actual_size,
265 MLX5_MTT_OCTW(npages));
267 /* Initialize the mkey with all MTTs pointing to a default
268 * page (filler_addr). When the channels are activated, UMR
269 * WQEs will redirect the RX WQEs to the actual memory from
270 * the RQ's pool, while the gaps (wqe_overflow) remain mapped
271 * to the default page.
273 mtt = MLX5_ADDR_OF(create_mkey_in, in, klm_pas_mtt);
274 for (i = 0 ; i < npages ; i++)
275 mtt[i].ptag = cpu_to_be64(filler_addr);
277 err = mlx5_core_create_mkey(mdev, umr_mkey, in, inlen);
283 static int mlx5e_create_rq_umr_mkey(struct mlx5_core_dev *mdev, struct mlx5e_rq *rq)
285 u64 num_mtts = MLX5E_REQUIRED_MTTS(mlx5_wq_ll_get_size(&rq->mpwqe.wq));
287 return mlx5e_create_umr_mkey(mdev, num_mtts, PAGE_SHIFT, &rq->umr_mkey,
288 rq->wqe_overflow.addr);
291 static u64 mlx5e_get_mpwqe_offset(u16 wqe_ix)
293 return MLX5E_REQUIRED_MTTS(wqe_ix) << PAGE_SHIFT;
296 static void mlx5e_init_frags_partition(struct mlx5e_rq *rq)
298 struct mlx5e_wqe_frag_info next_frag = {};
299 struct mlx5e_wqe_frag_info *prev = NULL;
302 next_frag.di = &rq->wqe.di[0];
304 for (i = 0; i < mlx5_wq_cyc_get_size(&rq->wqe.wq); i++) {
305 struct mlx5e_rq_frag_info *frag_info = &rq->wqe.info.arr[0];
306 struct mlx5e_wqe_frag_info *frag =
307 &rq->wqe.frags[i << rq->wqe.info.log_num_frags];
310 for (f = 0; f < rq->wqe.info.num_frags; f++, frag++) {
311 if (next_frag.offset + frag_info[f].frag_stride > PAGE_SIZE) {
313 next_frag.offset = 0;
315 prev->last_in_page = true;
320 next_frag.offset += frag_info[f].frag_stride;
326 prev->last_in_page = true;
329 int mlx5e_init_di_list(struct mlx5e_rq *rq, int wq_sz, int node)
331 int len = wq_sz << rq->wqe.info.log_num_frags;
333 rq->wqe.di = kvzalloc_node(array_size(len, sizeof(*rq->wqe.di)), GFP_KERNEL, node);
337 mlx5e_init_frags_partition(rq);
342 void mlx5e_free_di_list(struct mlx5e_rq *rq)
347 static void mlx5e_rq_err_cqe_work(struct work_struct *recover_work)
349 struct mlx5e_rq *rq = container_of(recover_work, struct mlx5e_rq, recover_work);
351 mlx5e_reporter_rq_cqe_err(rq);
354 static int mlx5e_alloc_mpwqe_rq_drop_page(struct mlx5e_rq *rq)
356 rq->wqe_overflow.page = alloc_page(GFP_KERNEL);
357 if (!rq->wqe_overflow.page)
360 rq->wqe_overflow.addr = dma_map_page(rq->pdev, rq->wqe_overflow.page, 0,
361 PAGE_SIZE, rq->buff.map_dir);
362 if (dma_mapping_error(rq->pdev, rq->wqe_overflow.addr)) {
363 __free_page(rq->wqe_overflow.page);
369 static void mlx5e_free_mpwqe_rq_drop_page(struct mlx5e_rq *rq)
371 dma_unmap_page(rq->pdev, rq->wqe_overflow.addr, PAGE_SIZE,
373 __free_page(rq->wqe_overflow.page);
376 static int mlx5e_init_rxq_rq(struct mlx5e_channel *c, struct mlx5e_params *params,
379 struct mlx5_core_dev *mdev = c->mdev;
382 rq->wq_type = params->rq_wq_type;
384 rq->netdev = c->netdev;
386 rq->tstamp = c->tstamp;
387 rq->clock = &mdev->clock;
388 rq->icosq = &c->icosq;
391 rq->hw_mtu = MLX5E_SW2HW_MTU(params, params->sw_mtu);
392 rq->xdpsq = &c->rq_xdpsq;
393 rq->stats = &c->priv->channel_stats[c->ix].rq;
394 rq->ptp_cyc2time = mlx5_rq_ts_translator(mdev);
395 err = mlx5e_rq_set_handlers(rq, params, NULL);
399 return xdp_rxq_info_reg(&rq->xdp_rxq, rq->netdev, rq->ix, 0);
402 static int mlx5e_alloc_rq(struct mlx5e_params *params,
403 struct mlx5e_xsk_param *xsk,
404 struct mlx5e_rq_param *rqp,
405 int node, struct mlx5e_rq *rq)
407 struct page_pool_params pp_params = { 0 };
408 struct mlx5_core_dev *mdev = rq->mdev;
409 void *rqc = rqp->rqc;
410 void *rqc_wq = MLX5_ADDR_OF(rqc, rqc, wq);
416 rqp->wq.db_numa_node = node;
417 INIT_WORK(&rq->recover_work, mlx5e_rq_err_cqe_work);
419 if (params->xdp_prog)
420 bpf_prog_inc(params->xdp_prog);
421 RCU_INIT_POINTER(rq->xdp_prog, params->xdp_prog);
423 rq->buff.map_dir = params->xdp_prog ? DMA_BIDIRECTIONAL : DMA_FROM_DEVICE;
424 rq->buff.headroom = mlx5e_get_rq_headroom(mdev, params, xsk);
425 pool_size = 1 << params->log_rq_mtu_frames;
427 switch (rq->wq_type) {
428 case MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ:
429 err = mlx5_wq_ll_create(mdev, &rqp->wq, rqc_wq, &rq->mpwqe.wq,
432 goto err_rq_xdp_prog;
434 err = mlx5e_alloc_mpwqe_rq_drop_page(rq);
436 goto err_rq_wq_destroy;
438 rq->mpwqe.wq.db = &rq->mpwqe.wq.db[MLX5_RCV_DBR];
440 wq_sz = mlx5_wq_ll_get_size(&rq->mpwqe.wq);
442 pool_size = MLX5_MPWRQ_PAGES_PER_WQE <<
443 mlx5e_mpwqe_get_log_rq_size(params, xsk);
445 rq->mpwqe.log_stride_sz = mlx5e_mpwqe_get_log_stride_size(mdev, params, xsk);
446 rq->mpwqe.num_strides =
447 BIT(mlx5e_mpwqe_get_log_num_strides(mdev, params, xsk));
449 rq->buff.frame0_sz = (1 << rq->mpwqe.log_stride_sz);
451 err = mlx5e_create_rq_umr_mkey(mdev, rq);
453 goto err_rq_drop_page;
454 rq->mkey_be = cpu_to_be32(rq->umr_mkey.key);
456 err = mlx5e_rq_alloc_mpwqe_info(rq, node);
460 default: /* MLX5_WQ_TYPE_CYCLIC */
461 err = mlx5_wq_cyc_create(mdev, &rqp->wq, rqc_wq, &rq->wqe.wq,
464 goto err_rq_xdp_prog;
466 rq->wqe.wq.db = &rq->wqe.wq.db[MLX5_RCV_DBR];
468 wq_sz = mlx5_wq_cyc_get_size(&rq->wqe.wq);
470 rq->wqe.info = rqp->frags_info;
471 rq->buff.frame0_sz = rq->wqe.info.arr[0].frag_stride;
474 kvzalloc_node(array_size(sizeof(*rq->wqe.frags),
475 (wq_sz << rq->wqe.info.log_num_frags)),
477 if (!rq->wqe.frags) {
479 goto err_rq_wq_destroy;
482 err = mlx5e_init_di_list(rq, wq_sz, node);
486 rq->mkey_be = cpu_to_be32(mdev->mlx5e_res.hw_objs.mkey.key);
490 err = xdp_rxq_info_reg_mem_model(&rq->xdp_rxq,
491 MEM_TYPE_XSK_BUFF_POOL, NULL);
492 xsk_pool_set_rxq_info(rq->xsk_pool, &rq->xdp_rxq);
494 /* Create a page_pool and register it with rxq */
496 pp_params.flags = 0; /* No-internal DMA mapping in page_pool */
497 pp_params.pool_size = pool_size;
498 pp_params.nid = node;
499 pp_params.dev = rq->pdev;
500 pp_params.dma_dir = rq->buff.map_dir;
502 /* page_pool can be used even when there is no rq->xdp_prog,
503 * given page_pool does not handle DMA mapping there is no
504 * required state to clear. And page_pool gracefully handle
507 rq->page_pool = page_pool_create(&pp_params);
508 if (IS_ERR(rq->page_pool)) {
509 err = PTR_ERR(rq->page_pool);
510 rq->page_pool = NULL;
511 goto err_free_by_rq_type;
513 if (xdp_rxq_info_is_reg(&rq->xdp_rxq))
514 err = xdp_rxq_info_reg_mem_model(&rq->xdp_rxq,
515 MEM_TYPE_PAGE_POOL, rq->page_pool);
518 goto err_free_by_rq_type;
520 for (i = 0; i < wq_sz; i++) {
521 if (rq->wq_type == MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ) {
522 struct mlx5e_rx_wqe_ll *wqe =
523 mlx5_wq_ll_get_wqe(&rq->mpwqe.wq, i);
525 rq->mpwqe.num_strides << rq->mpwqe.log_stride_sz;
526 u64 dma_offset = mlx5e_get_mpwqe_offset(i);
528 wqe->data[0].addr = cpu_to_be64(dma_offset + rq->buff.headroom);
529 wqe->data[0].byte_count = cpu_to_be32(byte_count);
530 wqe->data[0].lkey = rq->mkey_be;
532 struct mlx5e_rx_wqe_cyc *wqe =
533 mlx5_wq_cyc_get_wqe(&rq->wqe.wq, i);
536 for (f = 0; f < rq->wqe.info.num_frags; f++) {
537 u32 frag_size = rq->wqe.info.arr[f].frag_size |
538 MLX5_HW_START_PADDING;
540 wqe->data[f].byte_count = cpu_to_be32(frag_size);
541 wqe->data[f].lkey = rq->mkey_be;
543 /* check if num_frags is not a pow of two */
544 if (rq->wqe.info.num_frags < (1 << rq->wqe.info.log_num_frags)) {
545 wqe->data[f].byte_count = 0;
546 wqe->data[f].lkey = cpu_to_be32(MLX5_INVALID_LKEY);
547 wqe->data[f].addr = 0;
552 INIT_WORK(&rq->dim.work, mlx5e_rx_dim_work);
554 switch (params->rx_cq_moderation.cq_period_mode) {
555 case MLX5_CQ_PERIOD_MODE_START_FROM_CQE:
556 rq->dim.mode = DIM_CQ_PERIOD_MODE_START_FROM_CQE;
558 case MLX5_CQ_PERIOD_MODE_START_FROM_EQE:
560 rq->dim.mode = DIM_CQ_PERIOD_MODE_START_FROM_EQE;
563 rq->page_cache.head = 0;
564 rq->page_cache.tail = 0;
569 switch (rq->wq_type) {
570 case MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ:
571 kvfree(rq->mpwqe.info);
573 mlx5_core_destroy_mkey(mdev, &rq->umr_mkey);
575 mlx5e_free_mpwqe_rq_drop_page(rq);
577 default: /* MLX5_WQ_TYPE_CYCLIC */
578 mlx5e_free_di_list(rq);
580 kvfree(rq->wqe.frags);
583 mlx5_wq_destroy(&rq->wq_ctrl);
585 if (params->xdp_prog)
586 bpf_prog_put(params->xdp_prog);
591 static void mlx5e_free_rq(struct mlx5e_rq *rq)
593 struct bpf_prog *old_prog;
596 if (xdp_rxq_info_is_reg(&rq->xdp_rxq)) {
597 old_prog = rcu_dereference_protected(rq->xdp_prog,
598 lockdep_is_held(&rq->priv->state_lock));
600 bpf_prog_put(old_prog);
603 switch (rq->wq_type) {
604 case MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ:
605 kvfree(rq->mpwqe.info);
606 mlx5_core_destroy_mkey(rq->mdev, &rq->umr_mkey);
607 mlx5e_free_mpwqe_rq_drop_page(rq);
609 default: /* MLX5_WQ_TYPE_CYCLIC */
610 kvfree(rq->wqe.frags);
611 mlx5e_free_di_list(rq);
614 for (i = rq->page_cache.head; i != rq->page_cache.tail;
615 i = (i + 1) & (MLX5E_CACHE_SIZE - 1)) {
616 struct mlx5e_dma_info *dma_info = &rq->page_cache.page_cache[i];
618 /* With AF_XDP, page_cache is not used, so this loop is not
619 * entered, and it's safe to call mlx5e_page_release_dynamic
622 mlx5e_page_release_dynamic(rq, dma_info, false);
625 xdp_rxq_info_unreg(&rq->xdp_rxq);
626 page_pool_destroy(rq->page_pool);
627 mlx5_wq_destroy(&rq->wq_ctrl);
630 int mlx5e_create_rq(struct mlx5e_rq *rq, struct mlx5e_rq_param *param)
632 struct mlx5_core_dev *mdev = rq->mdev;
640 inlen = MLX5_ST_SZ_BYTES(create_rq_in) +
641 sizeof(u64) * rq->wq_ctrl.buf.npages;
642 in = kvzalloc(inlen, GFP_KERNEL);
646 ts_format = mlx5_is_real_time_rq(mdev) ?
647 MLX5_RQC_TIMESTAMP_FORMAT_REAL_TIME :
648 MLX5_RQC_TIMESTAMP_FORMAT_FREE_RUNNING;
649 rqc = MLX5_ADDR_OF(create_rq_in, in, ctx);
650 wq = MLX5_ADDR_OF(rqc, rqc, wq);
652 memcpy(rqc, param->rqc, sizeof(param->rqc));
654 MLX5_SET(rqc, rqc, cqn, rq->cq.mcq.cqn);
655 MLX5_SET(rqc, rqc, state, MLX5_RQC_STATE_RST);
656 MLX5_SET(rqc, rqc, ts_format, ts_format);
657 MLX5_SET(wq, wq, log_wq_pg_sz, rq->wq_ctrl.buf.page_shift -
658 MLX5_ADAPTER_PAGE_SHIFT);
659 MLX5_SET64(wq, wq, dbr_addr, rq->wq_ctrl.db.dma);
661 mlx5_fill_page_frag_array(&rq->wq_ctrl.buf,
662 (__be64 *)MLX5_ADDR_OF(wq, wq, pas));
664 err = mlx5_core_create_rq(mdev, in, inlen, &rq->rqn);
671 int mlx5e_modify_rq_state(struct mlx5e_rq *rq, int curr_state, int next_state)
673 struct mlx5_core_dev *mdev = rq->mdev;
680 inlen = MLX5_ST_SZ_BYTES(modify_rq_in);
681 in = kvzalloc(inlen, GFP_KERNEL);
685 if (curr_state == MLX5_RQC_STATE_RST && next_state == MLX5_RQC_STATE_RDY)
686 mlx5e_rqwq_reset(rq);
688 rqc = MLX5_ADDR_OF(modify_rq_in, in, ctx);
690 MLX5_SET(modify_rq_in, in, rq_state, curr_state);
691 MLX5_SET(rqc, rqc, state, next_state);
693 err = mlx5_core_modify_rq(mdev, rq->rqn, in);
700 static int mlx5e_modify_rq_scatter_fcs(struct mlx5e_rq *rq, bool enable)
702 struct mlx5_core_dev *mdev = rq->mdev;
709 inlen = MLX5_ST_SZ_BYTES(modify_rq_in);
710 in = kvzalloc(inlen, GFP_KERNEL);
714 rqc = MLX5_ADDR_OF(modify_rq_in, in, ctx);
716 MLX5_SET(modify_rq_in, in, rq_state, MLX5_RQC_STATE_RDY);
717 MLX5_SET64(modify_rq_in, in, modify_bitmask,
718 MLX5_MODIFY_RQ_IN_MODIFY_BITMASK_SCATTER_FCS);
719 MLX5_SET(rqc, rqc, scatter_fcs, enable);
720 MLX5_SET(rqc, rqc, state, MLX5_RQC_STATE_RDY);
722 err = mlx5_core_modify_rq(mdev, rq->rqn, in);
729 static int mlx5e_modify_rq_vsd(struct mlx5e_rq *rq, bool vsd)
731 struct mlx5_core_dev *mdev = rq->mdev;
737 inlen = MLX5_ST_SZ_BYTES(modify_rq_in);
738 in = kvzalloc(inlen, GFP_KERNEL);
742 rqc = MLX5_ADDR_OF(modify_rq_in, in, ctx);
744 MLX5_SET(modify_rq_in, in, rq_state, MLX5_RQC_STATE_RDY);
745 MLX5_SET64(modify_rq_in, in, modify_bitmask,
746 MLX5_MODIFY_RQ_IN_MODIFY_BITMASK_VSD);
747 MLX5_SET(rqc, rqc, vsd, vsd);
748 MLX5_SET(rqc, rqc, state, MLX5_RQC_STATE_RDY);
750 err = mlx5_core_modify_rq(mdev, rq->rqn, in);
757 void mlx5e_destroy_rq(struct mlx5e_rq *rq)
759 mlx5_core_destroy_rq(rq->mdev, rq->rqn);
762 int mlx5e_wait_for_min_rx_wqes(struct mlx5e_rq *rq, int wait_time)
764 unsigned long exp_time = jiffies + msecs_to_jiffies(wait_time);
766 u16 min_wqes = mlx5_min_rx_wqes(rq->wq_type, mlx5e_rqwq_get_size(rq));
769 if (mlx5e_rqwq_get_cur_sz(rq) >= min_wqes)
773 } while (time_before(jiffies, exp_time));
775 netdev_warn(rq->netdev, "Failed to get min RX wqes on Channel[%d] RQN[0x%x] wq cur_sz(%d) min_rx_wqes(%d)\n",
776 rq->ix, rq->rqn, mlx5e_rqwq_get_cur_sz(rq), min_wqes);
778 mlx5e_reporter_rx_timeout(rq);
782 void mlx5e_free_rx_in_progress_descs(struct mlx5e_rq *rq)
784 struct mlx5_wq_ll *wq;
788 if (rq->wq_type != MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ)
794 /* Outstanding UMR WQEs (in progress) start at wq->head */
795 for (i = 0; i < rq->mpwqe.umr_in_progress; i++) {
796 rq->dealloc_wqe(rq, head);
797 head = mlx5_wq_ll_get_wqe_next_ix(wq, head);
800 rq->mpwqe.actual_wq_head = wq->head;
801 rq->mpwqe.umr_in_progress = 0;
802 rq->mpwqe.umr_completed = 0;
805 void mlx5e_free_rx_descs(struct mlx5e_rq *rq)
810 if (rq->wq_type == MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ) {
811 struct mlx5_wq_ll *wq = &rq->mpwqe.wq;
813 mlx5e_free_rx_in_progress_descs(rq);
815 while (!mlx5_wq_ll_is_empty(wq)) {
816 struct mlx5e_rx_wqe_ll *wqe;
818 wqe_ix_be = *wq->tail_next;
819 wqe_ix = be16_to_cpu(wqe_ix_be);
820 wqe = mlx5_wq_ll_get_wqe(wq, wqe_ix);
821 rq->dealloc_wqe(rq, wqe_ix);
822 mlx5_wq_ll_pop(wq, wqe_ix_be,
823 &wqe->next.next_wqe_index);
826 struct mlx5_wq_cyc *wq = &rq->wqe.wq;
828 while (!mlx5_wq_cyc_is_empty(wq)) {
829 wqe_ix = mlx5_wq_cyc_get_tail(wq);
830 rq->dealloc_wqe(rq, wqe_ix);
837 int mlx5e_open_rq(struct mlx5e_params *params, struct mlx5e_rq_param *param,
838 struct mlx5e_xsk_param *xsk, int node,
841 struct mlx5_core_dev *mdev = rq->mdev;
844 err = mlx5e_alloc_rq(params, xsk, param, node, rq);
848 err = mlx5e_create_rq(rq, param);
852 err = mlx5e_modify_rq_state(rq, MLX5_RQC_STATE_RST, MLX5_RQC_STATE_RDY);
856 if (mlx5e_is_tls_on(rq->priv) && !mlx5_accel_is_ktls_device(mdev))
857 __set_bit(MLX5E_RQ_STATE_FPGA_TLS, &rq->state); /* must be FPGA */
859 if (MLX5_CAP_ETH(mdev, cqe_checksum_full))
860 __set_bit(MLX5E_RQ_STATE_CSUM_FULL, &rq->state);
862 if (params->rx_dim_enabled)
863 __set_bit(MLX5E_RQ_STATE_AM, &rq->state);
865 /* We disable csum_complete when XDP is enabled since
866 * XDP programs might manipulate packets which will render
867 * skb->checksum incorrect.
869 if (MLX5E_GET_PFLAG(params, MLX5E_PFLAG_RX_NO_CSUM_COMPLETE) || params->xdp_prog)
870 __set_bit(MLX5E_RQ_STATE_NO_CSUM_COMPLETE, &rq->state);
872 /* For CQE compression on striding RQ, use stride index provided by
873 * HW if capability is supported.
875 if (MLX5E_GET_PFLAG(params, MLX5E_PFLAG_RX_STRIDING_RQ) &&
876 MLX5_CAP_GEN(mdev, mini_cqe_resp_stride_index))
877 __set_bit(MLX5E_RQ_STATE_MINI_CQE_HW_STRIDX, &rq->state);
882 mlx5e_destroy_rq(rq);
889 void mlx5e_activate_rq(struct mlx5e_rq *rq)
891 set_bit(MLX5E_RQ_STATE_ENABLED, &rq->state);
893 mlx5e_trigger_irq(rq->icosq);
895 napi_schedule(rq->cq.napi);
898 void mlx5e_deactivate_rq(struct mlx5e_rq *rq)
900 clear_bit(MLX5E_RQ_STATE_ENABLED, &rq->state);
901 synchronize_net(); /* Sync with NAPI to prevent mlx5e_post_rx_wqes. */
904 void mlx5e_close_rq(struct mlx5e_rq *rq)
906 cancel_work_sync(&rq->dim.work);
908 cancel_work_sync(&rq->icosq->recover_work);
909 cancel_work_sync(&rq->recover_work);
910 mlx5e_destroy_rq(rq);
911 mlx5e_free_rx_descs(rq);
915 static void mlx5e_free_xdpsq_db(struct mlx5e_xdpsq *sq)
917 kvfree(sq->db.xdpi_fifo.xi);
918 kvfree(sq->db.wqe_info);
921 static int mlx5e_alloc_xdpsq_fifo(struct mlx5e_xdpsq *sq, int numa)
923 struct mlx5e_xdp_info_fifo *xdpi_fifo = &sq->db.xdpi_fifo;
924 int wq_sz = mlx5_wq_cyc_get_size(&sq->wq);
925 int dsegs_per_wq = wq_sz * MLX5_SEND_WQEBB_NUM_DS;
927 xdpi_fifo->xi = kvzalloc_node(sizeof(*xdpi_fifo->xi) * dsegs_per_wq,
932 xdpi_fifo->pc = &sq->xdpi_fifo_pc;
933 xdpi_fifo->cc = &sq->xdpi_fifo_cc;
934 xdpi_fifo->mask = dsegs_per_wq - 1;
939 static int mlx5e_alloc_xdpsq_db(struct mlx5e_xdpsq *sq, int numa)
941 int wq_sz = mlx5_wq_cyc_get_size(&sq->wq);
944 sq->db.wqe_info = kvzalloc_node(sizeof(*sq->db.wqe_info) * wq_sz,
946 if (!sq->db.wqe_info)
949 err = mlx5e_alloc_xdpsq_fifo(sq, numa);
951 mlx5e_free_xdpsq_db(sq);
958 static int mlx5e_alloc_xdpsq(struct mlx5e_channel *c,
959 struct mlx5e_params *params,
960 struct xsk_buff_pool *xsk_pool,
961 struct mlx5e_sq_param *param,
962 struct mlx5e_xdpsq *sq,
965 void *sqc_wq = MLX5_ADDR_OF(sqc, param->sqc, wq);
966 struct mlx5_core_dev *mdev = c->mdev;
967 struct mlx5_wq_cyc *wq = &sq->wq;
971 sq->mkey_be = c->mkey_be;
973 sq->uar_map = mdev->mlx5e_res.hw_objs.bfreg.map;
974 sq->min_inline_mode = params->tx_min_inline_mode;
975 sq->hw_mtu = MLX5E_SW2HW_MTU(params, params->sw_mtu);
976 sq->xsk_pool = xsk_pool;
978 sq->stats = sq->xsk_pool ?
979 &c->priv->channel_stats[c->ix].xsksq :
981 &c->priv->channel_stats[c->ix].xdpsq :
982 &c->priv->channel_stats[c->ix].rq_xdpsq;
984 param->wq.db_numa_node = cpu_to_node(c->cpu);
985 err = mlx5_wq_cyc_create(mdev, ¶m->wq, sqc_wq, wq, &sq->wq_ctrl);
988 wq->db = &wq->db[MLX5_SND_DBR];
990 err = mlx5e_alloc_xdpsq_db(sq, cpu_to_node(c->cpu));
992 goto err_sq_wq_destroy;
997 mlx5_wq_destroy(&sq->wq_ctrl);
1002 static void mlx5e_free_xdpsq(struct mlx5e_xdpsq *sq)
1004 mlx5e_free_xdpsq_db(sq);
1005 mlx5_wq_destroy(&sq->wq_ctrl);
1008 static void mlx5e_free_icosq_db(struct mlx5e_icosq *sq)
1010 kvfree(sq->db.wqe_info);
1013 static int mlx5e_alloc_icosq_db(struct mlx5e_icosq *sq, int numa)
1015 int wq_sz = mlx5_wq_cyc_get_size(&sq->wq);
1018 size = array_size(wq_sz, sizeof(*sq->db.wqe_info));
1019 sq->db.wqe_info = kvzalloc_node(size, GFP_KERNEL, numa);
1020 if (!sq->db.wqe_info)
1026 static void mlx5e_icosq_err_cqe_work(struct work_struct *recover_work)
1028 struct mlx5e_icosq *sq = container_of(recover_work, struct mlx5e_icosq,
1031 mlx5e_reporter_icosq_cqe_err(sq);
1034 static int mlx5e_alloc_icosq(struct mlx5e_channel *c,
1035 struct mlx5e_sq_param *param,
1036 struct mlx5e_icosq *sq)
1038 void *sqc_wq = MLX5_ADDR_OF(sqc, param->sqc, wq);
1039 struct mlx5_core_dev *mdev = c->mdev;
1040 struct mlx5_wq_cyc *wq = &sq->wq;
1044 sq->uar_map = mdev->mlx5e_res.hw_objs.bfreg.map;
1045 sq->reserved_room = param->stop_room;
1047 param->wq.db_numa_node = cpu_to_node(c->cpu);
1048 err = mlx5_wq_cyc_create(mdev, ¶m->wq, sqc_wq, wq, &sq->wq_ctrl);
1051 wq->db = &wq->db[MLX5_SND_DBR];
1053 err = mlx5e_alloc_icosq_db(sq, cpu_to_node(c->cpu));
1055 goto err_sq_wq_destroy;
1057 INIT_WORK(&sq->recover_work, mlx5e_icosq_err_cqe_work);
1062 mlx5_wq_destroy(&sq->wq_ctrl);
1067 static void mlx5e_free_icosq(struct mlx5e_icosq *sq)
1069 mlx5e_free_icosq_db(sq);
1070 mlx5_wq_destroy(&sq->wq_ctrl);
1073 void mlx5e_free_txqsq_db(struct mlx5e_txqsq *sq)
1075 kvfree(sq->db.wqe_info);
1076 kvfree(sq->db.skb_fifo.fifo);
1077 kvfree(sq->db.dma_fifo);
1080 int mlx5e_alloc_txqsq_db(struct mlx5e_txqsq *sq, int numa)
1082 int wq_sz = mlx5_wq_cyc_get_size(&sq->wq);
1083 int df_sz = wq_sz * MLX5_SEND_WQEBB_NUM_DS;
1085 sq->db.dma_fifo = kvzalloc_node(array_size(df_sz,
1086 sizeof(*sq->db.dma_fifo)),
1088 sq->db.skb_fifo.fifo = kvzalloc_node(array_size(df_sz,
1089 sizeof(*sq->db.skb_fifo.fifo)),
1091 sq->db.wqe_info = kvzalloc_node(array_size(wq_sz,
1092 sizeof(*sq->db.wqe_info)),
1094 if (!sq->db.dma_fifo || !sq->db.skb_fifo.fifo || !sq->db.wqe_info) {
1095 mlx5e_free_txqsq_db(sq);
1099 sq->dma_fifo_mask = df_sz - 1;
1101 sq->db.skb_fifo.pc = &sq->skb_fifo_pc;
1102 sq->db.skb_fifo.cc = &sq->skb_fifo_cc;
1103 sq->db.skb_fifo.mask = df_sz - 1;
1108 static int mlx5e_alloc_txqsq(struct mlx5e_channel *c,
1110 struct mlx5e_params *params,
1111 struct mlx5e_sq_param *param,
1112 struct mlx5e_txqsq *sq,
1115 void *sqc_wq = MLX5_ADDR_OF(sqc, param->sqc, wq);
1116 struct mlx5_core_dev *mdev = c->mdev;
1117 struct mlx5_wq_cyc *wq = &sq->wq;
1121 sq->tstamp = c->tstamp;
1122 sq->clock = &mdev->clock;
1123 sq->mkey_be = c->mkey_be;
1124 sq->netdev = c->netdev;
1128 sq->txq_ix = txq_ix;
1129 sq->uar_map = mdev->mlx5e_res.hw_objs.bfreg.map;
1130 sq->min_inline_mode = params->tx_min_inline_mode;
1131 sq->hw_mtu = MLX5E_SW2HW_MTU(params, params->sw_mtu);
1132 INIT_WORK(&sq->recover_work, mlx5e_tx_err_cqe_work);
1133 if (!MLX5_CAP_ETH(mdev, wqe_vlan_insert))
1134 set_bit(MLX5E_SQ_STATE_VLAN_NEED_L2_INLINE, &sq->state);
1135 if (MLX5_IPSEC_DEV(c->priv->mdev))
1136 set_bit(MLX5E_SQ_STATE_IPSEC, &sq->state);
1138 set_bit(MLX5E_SQ_STATE_MPWQE, &sq->state);
1139 sq->stop_room = param->stop_room;
1140 sq->ptp_cyc2time = mlx5_sq_ts_translator(mdev);
1142 param->wq.db_numa_node = cpu_to_node(c->cpu);
1143 err = mlx5_wq_cyc_create(mdev, ¶m->wq, sqc_wq, wq, &sq->wq_ctrl);
1146 wq->db = &wq->db[MLX5_SND_DBR];
1148 err = mlx5e_alloc_txqsq_db(sq, cpu_to_node(c->cpu));
1150 goto err_sq_wq_destroy;
1152 INIT_WORK(&sq->dim.work, mlx5e_tx_dim_work);
1153 sq->dim.mode = params->tx_cq_moderation.cq_period_mode;
1158 mlx5_wq_destroy(&sq->wq_ctrl);
1163 void mlx5e_free_txqsq(struct mlx5e_txqsq *sq)
1165 mlx5e_free_txqsq_db(sq);
1166 mlx5_wq_destroy(&sq->wq_ctrl);
1169 static int mlx5e_create_sq(struct mlx5_core_dev *mdev,
1170 struct mlx5e_sq_param *param,
1171 struct mlx5e_create_sq_param *csp,
1181 inlen = MLX5_ST_SZ_BYTES(create_sq_in) +
1182 sizeof(u64) * csp->wq_ctrl->buf.npages;
1183 in = kvzalloc(inlen, GFP_KERNEL);
1187 ts_format = mlx5_is_real_time_sq(mdev) ?
1188 MLX5_SQC_TIMESTAMP_FORMAT_REAL_TIME :
1189 MLX5_SQC_TIMESTAMP_FORMAT_FREE_RUNNING;
1190 sqc = MLX5_ADDR_OF(create_sq_in, in, ctx);
1191 wq = MLX5_ADDR_OF(sqc, sqc, wq);
1193 memcpy(sqc, param->sqc, sizeof(param->sqc));
1194 MLX5_SET(sqc, sqc, tis_lst_sz, csp->tis_lst_sz);
1195 MLX5_SET(sqc, sqc, tis_num_0, csp->tisn);
1196 MLX5_SET(sqc, sqc, cqn, csp->cqn);
1197 MLX5_SET(sqc, sqc, ts_cqe_to_dest_cqn, csp->ts_cqe_to_dest_cqn);
1198 MLX5_SET(sqc, sqc, ts_format, ts_format);
1201 if (MLX5_CAP_ETH(mdev, wqe_inline_mode) == MLX5_CAP_INLINE_MODE_VPORT_CONTEXT)
1202 MLX5_SET(sqc, sqc, min_wqe_inline_mode, csp->min_inline_mode);
1204 MLX5_SET(sqc, sqc, state, MLX5_SQC_STATE_RST);
1205 MLX5_SET(sqc, sqc, flush_in_error_en, 1);
1207 MLX5_SET(wq, wq, wq_type, MLX5_WQ_TYPE_CYCLIC);
1208 MLX5_SET(wq, wq, uar_page, mdev->mlx5e_res.hw_objs.bfreg.index);
1209 MLX5_SET(wq, wq, log_wq_pg_sz, csp->wq_ctrl->buf.page_shift -
1210 MLX5_ADAPTER_PAGE_SHIFT);
1211 MLX5_SET64(wq, wq, dbr_addr, csp->wq_ctrl->db.dma);
1213 mlx5_fill_page_frag_array(&csp->wq_ctrl->buf,
1214 (__be64 *)MLX5_ADDR_OF(wq, wq, pas));
1216 err = mlx5_core_create_sq(mdev, in, inlen, sqn);
1223 int mlx5e_modify_sq(struct mlx5_core_dev *mdev, u32 sqn,
1224 struct mlx5e_modify_sq_param *p)
1232 inlen = MLX5_ST_SZ_BYTES(modify_sq_in);
1233 in = kvzalloc(inlen, GFP_KERNEL);
1237 sqc = MLX5_ADDR_OF(modify_sq_in, in, ctx);
1239 MLX5_SET(modify_sq_in, in, sq_state, p->curr_state);
1240 MLX5_SET(sqc, sqc, state, p->next_state);
1241 if (p->rl_update && p->next_state == MLX5_SQC_STATE_RDY) {
1243 MLX5_SET(sqc, sqc, packet_pacing_rate_limit_index, p->rl_index);
1245 if (p->qos_update && p->next_state == MLX5_SQC_STATE_RDY) {
1247 MLX5_SET(sqc, sqc, qos_queue_group_id, p->qos_queue_group_id);
1249 MLX5_SET64(modify_sq_in, in, modify_bitmask, bitmask);
1251 err = mlx5_core_modify_sq(mdev, sqn, in);
1258 static void mlx5e_destroy_sq(struct mlx5_core_dev *mdev, u32 sqn)
1260 mlx5_core_destroy_sq(mdev, sqn);
1263 int mlx5e_create_sq_rdy(struct mlx5_core_dev *mdev,
1264 struct mlx5e_sq_param *param,
1265 struct mlx5e_create_sq_param *csp,
1266 u16 qos_queue_group_id,
1269 struct mlx5e_modify_sq_param msp = {0};
1272 err = mlx5e_create_sq(mdev, param, csp, sqn);
1276 msp.curr_state = MLX5_SQC_STATE_RST;
1277 msp.next_state = MLX5_SQC_STATE_RDY;
1278 if (qos_queue_group_id) {
1279 msp.qos_update = true;
1280 msp.qos_queue_group_id = qos_queue_group_id;
1282 err = mlx5e_modify_sq(mdev, *sqn, &msp);
1284 mlx5e_destroy_sq(mdev, *sqn);
1289 static int mlx5e_set_sq_maxrate(struct net_device *dev,
1290 struct mlx5e_txqsq *sq, u32 rate);
1292 int mlx5e_open_txqsq(struct mlx5e_channel *c, u32 tisn, int txq_ix,
1293 struct mlx5e_params *params, struct mlx5e_sq_param *param,
1294 struct mlx5e_txqsq *sq, int tc, u16 qos_queue_group_id, u16 qos_qid)
1296 struct mlx5e_create_sq_param csp = {};
1300 err = mlx5e_alloc_txqsq(c, txq_ix, params, param, sq, tc);
1304 if (qos_queue_group_id)
1305 sq->stats = c->priv->htb.qos_sq_stats[qos_qid];
1307 sq->stats = &c->priv->channel_stats[c->ix].sq[tc];
1311 csp.cqn = sq->cq.mcq.cqn;
1312 csp.wq_ctrl = &sq->wq_ctrl;
1313 csp.min_inline_mode = sq->min_inline_mode;
1314 err = mlx5e_create_sq_rdy(c->mdev, param, &csp, qos_queue_group_id, &sq->sqn);
1316 goto err_free_txqsq;
1318 tx_rate = c->priv->tx_rates[sq->txq_ix];
1320 mlx5e_set_sq_maxrate(c->netdev, sq, tx_rate);
1322 if (params->tx_dim_enabled)
1323 sq->state |= BIT(MLX5E_SQ_STATE_AM);
1328 mlx5e_free_txqsq(sq);
1333 void mlx5e_activate_txqsq(struct mlx5e_txqsq *sq)
1335 sq->txq = netdev_get_tx_queue(sq->netdev, sq->txq_ix);
1336 set_bit(MLX5E_SQ_STATE_ENABLED, &sq->state);
1337 netdev_tx_reset_queue(sq->txq);
1338 netif_tx_start_queue(sq->txq);
1341 void mlx5e_tx_disable_queue(struct netdev_queue *txq)
1343 __netif_tx_lock_bh(txq);
1344 netif_tx_stop_queue(txq);
1345 __netif_tx_unlock_bh(txq);
1348 void mlx5e_deactivate_txqsq(struct mlx5e_txqsq *sq)
1350 struct mlx5_wq_cyc *wq = &sq->wq;
1352 clear_bit(MLX5E_SQ_STATE_ENABLED, &sq->state);
1353 synchronize_net(); /* Sync with NAPI to prevent netif_tx_wake_queue. */
1355 mlx5e_tx_disable_queue(sq->txq);
1357 /* last doorbell out, godspeed .. */
1358 if (mlx5e_wqc_has_room_for(wq, sq->cc, sq->pc, 1)) {
1359 u16 pi = mlx5_wq_cyc_ctr2ix(wq, sq->pc);
1360 struct mlx5e_tx_wqe *nop;
1362 sq->db.wqe_info[pi] = (struct mlx5e_tx_wqe_info) {
1366 nop = mlx5e_post_nop(wq, sq->sqn, &sq->pc);
1367 mlx5e_notify_hw(wq, sq->pc, sq->uar_map, &nop->ctrl);
1371 void mlx5e_close_txqsq(struct mlx5e_txqsq *sq)
1373 struct mlx5_core_dev *mdev = sq->mdev;
1374 struct mlx5_rate_limit rl = {0};
1376 cancel_work_sync(&sq->dim.work);
1377 cancel_work_sync(&sq->recover_work);
1378 mlx5e_destroy_sq(mdev, sq->sqn);
1379 if (sq->rate_limit) {
1380 rl.rate = sq->rate_limit;
1381 mlx5_rl_remove_rate(mdev, &rl);
1383 mlx5e_free_txqsq_descs(sq);
1384 mlx5e_free_txqsq(sq);
1387 void mlx5e_tx_err_cqe_work(struct work_struct *recover_work)
1389 struct mlx5e_txqsq *sq = container_of(recover_work, struct mlx5e_txqsq,
1392 mlx5e_reporter_tx_err_cqe(sq);
1395 int mlx5e_open_icosq(struct mlx5e_channel *c, struct mlx5e_params *params,
1396 struct mlx5e_sq_param *param, struct mlx5e_icosq *sq)
1398 struct mlx5e_create_sq_param csp = {};
1401 err = mlx5e_alloc_icosq(c, param, sq);
1405 csp.cqn = sq->cq.mcq.cqn;
1406 csp.wq_ctrl = &sq->wq_ctrl;
1407 csp.min_inline_mode = params->tx_min_inline_mode;
1408 err = mlx5e_create_sq_rdy(c->mdev, param, &csp, 0, &sq->sqn);
1410 goto err_free_icosq;
1412 if (param->is_tls) {
1413 sq->ktls_resync = mlx5e_ktls_rx_resync_create_resp_list();
1414 if (IS_ERR(sq->ktls_resync)) {
1415 err = PTR_ERR(sq->ktls_resync);
1416 goto err_destroy_icosq;
1422 mlx5e_destroy_sq(c->mdev, sq->sqn);
1424 mlx5e_free_icosq(sq);
1429 void mlx5e_activate_icosq(struct mlx5e_icosq *icosq)
1431 set_bit(MLX5E_SQ_STATE_ENABLED, &icosq->state);
1434 void mlx5e_deactivate_icosq(struct mlx5e_icosq *icosq)
1436 clear_bit(MLX5E_SQ_STATE_ENABLED, &icosq->state);
1437 synchronize_net(); /* Sync with NAPI. */
1440 void mlx5e_close_icosq(struct mlx5e_icosq *sq)
1442 struct mlx5e_channel *c = sq->channel;
1444 if (sq->ktls_resync)
1445 mlx5e_ktls_rx_resync_destroy_resp_list(sq->ktls_resync);
1446 mlx5e_destroy_sq(c->mdev, sq->sqn);
1447 mlx5e_free_icosq_descs(sq);
1448 mlx5e_free_icosq(sq);
1451 int mlx5e_open_xdpsq(struct mlx5e_channel *c, struct mlx5e_params *params,
1452 struct mlx5e_sq_param *param, struct xsk_buff_pool *xsk_pool,
1453 struct mlx5e_xdpsq *sq, bool is_redirect)
1455 struct mlx5e_create_sq_param csp = {};
1458 err = mlx5e_alloc_xdpsq(c, params, xsk_pool, param, sq, is_redirect);
1463 csp.tisn = c->priv->tisn[c->lag_port][0]; /* tc = 0 */
1464 csp.cqn = sq->cq.mcq.cqn;
1465 csp.wq_ctrl = &sq->wq_ctrl;
1466 csp.min_inline_mode = sq->min_inline_mode;
1467 set_bit(MLX5E_SQ_STATE_ENABLED, &sq->state);
1468 err = mlx5e_create_sq_rdy(c->mdev, param, &csp, 0, &sq->sqn);
1470 goto err_free_xdpsq;
1472 mlx5e_set_xmit_fp(sq, param->is_mpw);
1474 if (!param->is_mpw) {
1475 unsigned int ds_cnt = MLX5E_XDP_TX_DS_COUNT;
1476 unsigned int inline_hdr_sz = 0;
1479 if (sq->min_inline_mode != MLX5_INLINE_MODE_NONE) {
1480 inline_hdr_sz = MLX5E_XDP_MIN_INLINE;
1484 /* Pre initialize fixed WQE fields */
1485 for (i = 0; i < mlx5_wq_cyc_get_size(&sq->wq); i++) {
1486 struct mlx5e_tx_wqe *wqe = mlx5_wq_cyc_get_wqe(&sq->wq, i);
1487 struct mlx5_wqe_ctrl_seg *cseg = &wqe->ctrl;
1488 struct mlx5_wqe_eth_seg *eseg = &wqe->eth;
1489 struct mlx5_wqe_data_seg *dseg;
1491 sq->db.wqe_info[i] = (struct mlx5e_xdp_wqe_info) {
1496 cseg->qpn_ds = cpu_to_be32((sq->sqn << 8) | ds_cnt);
1497 eseg->inline_hdr.sz = cpu_to_be16(inline_hdr_sz);
1499 dseg = (struct mlx5_wqe_data_seg *)cseg + (ds_cnt - 1);
1500 dseg->lkey = sq->mkey_be;
1507 clear_bit(MLX5E_SQ_STATE_ENABLED, &sq->state);
1508 mlx5e_free_xdpsq(sq);
1513 void mlx5e_close_xdpsq(struct mlx5e_xdpsq *sq)
1515 struct mlx5e_channel *c = sq->channel;
1517 clear_bit(MLX5E_SQ_STATE_ENABLED, &sq->state);
1518 synchronize_net(); /* Sync with NAPI. */
1520 mlx5e_destroy_sq(c->mdev, sq->sqn);
1521 mlx5e_free_xdpsq_descs(sq);
1522 mlx5e_free_xdpsq(sq);
1525 static int mlx5e_alloc_cq_common(struct mlx5e_priv *priv,
1526 struct mlx5e_cq_param *param,
1527 struct mlx5e_cq *cq)
1529 struct mlx5_core_dev *mdev = priv->mdev;
1530 struct mlx5_core_cq *mcq = &cq->mcq;
1536 err = mlx5_vector2eqn(mdev, param->eq_ix, &eqn_not_used, &irqn);
1540 err = mlx5_cqwq_create(mdev, ¶m->wq, param->cqc, &cq->wq,
1546 mcq->set_ci_db = cq->wq_ctrl.db.db;
1547 mcq->arm_db = cq->wq_ctrl.db.db + 1;
1548 *mcq->set_ci_db = 0;
1550 mcq->vector = param->eq_ix;
1551 mcq->comp = mlx5e_completion_event;
1552 mcq->event = mlx5e_cq_error_event;
1555 for (i = 0; i < mlx5_cqwq_get_size(&cq->wq); i++) {
1556 struct mlx5_cqe64 *cqe = mlx5_cqwq_get_wqe(&cq->wq, i);
1562 cq->netdev = priv->netdev;
1568 static int mlx5e_alloc_cq(struct mlx5e_priv *priv,
1569 struct mlx5e_cq_param *param,
1570 struct mlx5e_create_cq_param *ccp,
1571 struct mlx5e_cq *cq)
1575 param->wq.buf_numa_node = ccp->node;
1576 param->wq.db_numa_node = ccp->node;
1577 param->eq_ix = ccp->ix;
1579 err = mlx5e_alloc_cq_common(priv, param, cq);
1581 cq->napi = ccp->napi;
1582 cq->ch_stats = ccp->ch_stats;
1587 static void mlx5e_free_cq(struct mlx5e_cq *cq)
1589 mlx5_wq_destroy(&cq->wq_ctrl);
1592 static int mlx5e_create_cq(struct mlx5e_cq *cq, struct mlx5e_cq_param *param)
1594 u32 out[MLX5_ST_SZ_DW(create_cq_out)];
1595 struct mlx5_core_dev *mdev = cq->mdev;
1596 struct mlx5_core_cq *mcq = &cq->mcq;
1601 unsigned int irqn_not_used;
1605 err = mlx5_vector2eqn(mdev, param->eq_ix, &eqn, &irqn_not_used);
1609 inlen = MLX5_ST_SZ_BYTES(create_cq_in) +
1610 sizeof(u64) * cq->wq_ctrl.buf.npages;
1611 in = kvzalloc(inlen, GFP_KERNEL);
1615 cqc = MLX5_ADDR_OF(create_cq_in, in, cq_context);
1617 memcpy(cqc, param->cqc, sizeof(param->cqc));
1619 mlx5_fill_page_frag_array(&cq->wq_ctrl.buf,
1620 (__be64 *)MLX5_ADDR_OF(create_cq_in, in, pas));
1622 MLX5_SET(cqc, cqc, cq_period_mode, param->cq_period_mode);
1623 MLX5_SET(cqc, cqc, c_eqn, eqn);
1624 MLX5_SET(cqc, cqc, uar_page, mdev->priv.uar->index);
1625 MLX5_SET(cqc, cqc, log_page_size, cq->wq_ctrl.buf.page_shift -
1626 MLX5_ADAPTER_PAGE_SHIFT);
1627 MLX5_SET64(cqc, cqc, dbr_addr, cq->wq_ctrl.db.dma);
1629 err = mlx5_core_create_cq(mdev, mcq, in, inlen, out, sizeof(out));
1641 static void mlx5e_destroy_cq(struct mlx5e_cq *cq)
1643 mlx5_core_destroy_cq(cq->mdev, &cq->mcq);
1646 int mlx5e_open_cq(struct mlx5e_priv *priv, struct dim_cq_moder moder,
1647 struct mlx5e_cq_param *param, struct mlx5e_create_cq_param *ccp,
1648 struct mlx5e_cq *cq)
1650 struct mlx5_core_dev *mdev = priv->mdev;
1653 err = mlx5e_alloc_cq(priv, param, ccp, cq);
1657 err = mlx5e_create_cq(cq, param);
1661 if (MLX5_CAP_GEN(mdev, cq_moderation))
1662 mlx5_core_modify_cq_moderation(mdev, &cq->mcq, moder.usec, moder.pkts);
1671 void mlx5e_close_cq(struct mlx5e_cq *cq)
1673 mlx5e_destroy_cq(cq);
1677 static int mlx5e_open_tx_cqs(struct mlx5e_channel *c,
1678 struct mlx5e_params *params,
1679 struct mlx5e_create_cq_param *ccp,
1680 struct mlx5e_channel_param *cparam)
1685 for (tc = 0; tc < c->num_tc; tc++) {
1686 err = mlx5e_open_cq(c->priv, params->tx_cq_moderation, &cparam->txq_sq.cqp,
1687 ccp, &c->sq[tc].cq);
1689 goto err_close_tx_cqs;
1695 for (tc--; tc >= 0; tc--)
1696 mlx5e_close_cq(&c->sq[tc].cq);
1701 static void mlx5e_close_tx_cqs(struct mlx5e_channel *c)
1705 for (tc = 0; tc < c->num_tc; tc++)
1706 mlx5e_close_cq(&c->sq[tc].cq);
1709 static int mlx5e_open_sqs(struct mlx5e_channel *c,
1710 struct mlx5e_params *params,
1711 struct mlx5e_channel_param *cparam)
1715 for (tc = 0; tc < params->num_tc; tc++) {
1716 int txq_ix = c->ix + tc * params->num_channels;
1718 err = mlx5e_open_txqsq(c, c->priv->tisn[c->lag_port][tc], txq_ix,
1719 params, &cparam->txq_sq, &c->sq[tc], tc, 0, 0);
1727 for (tc--; tc >= 0; tc--)
1728 mlx5e_close_txqsq(&c->sq[tc]);
1733 static void mlx5e_close_sqs(struct mlx5e_channel *c)
1737 for (tc = 0; tc < c->num_tc; tc++)
1738 mlx5e_close_txqsq(&c->sq[tc]);
1741 static int mlx5e_set_sq_maxrate(struct net_device *dev,
1742 struct mlx5e_txqsq *sq, u32 rate)
1744 struct mlx5e_priv *priv = netdev_priv(dev);
1745 struct mlx5_core_dev *mdev = priv->mdev;
1746 struct mlx5e_modify_sq_param msp = {0};
1747 struct mlx5_rate_limit rl = {0};
1751 if (rate == sq->rate_limit)
1755 if (sq->rate_limit) {
1756 rl.rate = sq->rate_limit;
1757 /* remove current rl index to free space to next ones */
1758 mlx5_rl_remove_rate(mdev, &rl);
1765 err = mlx5_rl_add_rate(mdev, &rl_index, &rl);
1767 netdev_err(dev, "Failed configuring rate %u: %d\n",
1773 msp.curr_state = MLX5_SQC_STATE_RDY;
1774 msp.next_state = MLX5_SQC_STATE_RDY;
1775 msp.rl_index = rl_index;
1776 msp.rl_update = true;
1777 err = mlx5e_modify_sq(mdev, sq->sqn, &msp);
1779 netdev_err(dev, "Failed configuring rate %u: %d\n",
1781 /* remove the rate from the table */
1783 mlx5_rl_remove_rate(mdev, &rl);
1787 sq->rate_limit = rate;
1791 static int mlx5e_set_tx_maxrate(struct net_device *dev, int index, u32 rate)
1793 struct mlx5e_priv *priv = netdev_priv(dev);
1794 struct mlx5_core_dev *mdev = priv->mdev;
1795 struct mlx5e_txqsq *sq = priv->txq2sq[index];
1798 if (!mlx5_rl_is_supported(mdev)) {
1799 netdev_err(dev, "Rate limiting is not supported on this device\n");
1803 /* rate is given in Mb/sec, HW config is in Kb/sec */
1806 /* Check whether rate in valid range, 0 is always valid */
1807 if (rate && !mlx5_rl_is_in_range(mdev, rate)) {
1808 netdev_err(dev, "TX rate %u, is not in range\n", rate);
1812 mutex_lock(&priv->state_lock);
1813 if (test_bit(MLX5E_STATE_OPENED, &priv->state))
1814 err = mlx5e_set_sq_maxrate(dev, sq, rate);
1816 priv->tx_rates[index] = rate;
1817 mutex_unlock(&priv->state_lock);
1822 static int mlx5e_open_rxq_rq(struct mlx5e_channel *c, struct mlx5e_params *params,
1823 struct mlx5e_rq_param *rq_params)
1827 err = mlx5e_init_rxq_rq(c, params, &c->rq);
1831 return mlx5e_open_rq(params, rq_params, NULL, cpu_to_node(c->cpu), &c->rq);
1834 static int mlx5e_open_queues(struct mlx5e_channel *c,
1835 struct mlx5e_params *params,
1836 struct mlx5e_channel_param *cparam)
1838 struct dim_cq_moder icocq_moder = {0, 0};
1839 struct mlx5e_create_cq_param ccp;
1842 mlx5e_build_create_cq_param(&ccp, c);
1844 err = mlx5e_open_cq(c->priv, icocq_moder, &cparam->async_icosq.cqp, &ccp,
1845 &c->async_icosq.cq);
1849 err = mlx5e_open_cq(c->priv, icocq_moder, &cparam->icosq.cqp, &ccp,
1852 goto err_close_async_icosq_cq;
1854 err = mlx5e_open_tx_cqs(c, params, &ccp, cparam);
1856 goto err_close_icosq_cq;
1858 err = mlx5e_open_cq(c->priv, params->tx_cq_moderation, &cparam->xdp_sq.cqp, &ccp,
1861 goto err_close_tx_cqs;
1863 err = mlx5e_open_cq(c->priv, params->rx_cq_moderation, &cparam->rq.cqp, &ccp,
1866 goto err_close_xdp_tx_cqs;
1868 err = c->xdp ? mlx5e_open_cq(c->priv, params->tx_cq_moderation, &cparam->xdp_sq.cqp,
1869 &ccp, &c->rq_xdpsq.cq) : 0;
1871 goto err_close_rx_cq;
1873 spin_lock_init(&c->async_icosq_lock);
1875 err = mlx5e_open_icosq(c, params, &cparam->async_icosq, &c->async_icosq);
1877 goto err_close_xdpsq_cq;
1879 err = mlx5e_open_icosq(c, params, &cparam->icosq, &c->icosq);
1881 goto err_close_async_icosq;
1883 err = mlx5e_open_sqs(c, params, cparam);
1885 goto err_close_icosq;
1888 err = mlx5e_open_xdpsq(c, params, &cparam->xdp_sq, NULL,
1889 &c->rq_xdpsq, false);
1894 err = mlx5e_open_rxq_rq(c, params, &cparam->rq);
1896 goto err_close_xdp_sq;
1898 err = mlx5e_open_xdpsq(c, params, &cparam->xdp_sq, NULL, &c->xdpsq, true);
1905 mlx5e_close_rq(&c->rq);
1909 mlx5e_close_xdpsq(&c->rq_xdpsq);
1915 mlx5e_close_icosq(&c->icosq);
1917 err_close_async_icosq:
1918 mlx5e_close_icosq(&c->async_icosq);
1922 mlx5e_close_cq(&c->rq_xdpsq.cq);
1925 mlx5e_close_cq(&c->rq.cq);
1927 err_close_xdp_tx_cqs:
1928 mlx5e_close_cq(&c->xdpsq.cq);
1931 mlx5e_close_tx_cqs(c);
1934 mlx5e_close_cq(&c->icosq.cq);
1936 err_close_async_icosq_cq:
1937 mlx5e_close_cq(&c->async_icosq.cq);
1942 static void mlx5e_close_queues(struct mlx5e_channel *c)
1944 mlx5e_close_xdpsq(&c->xdpsq);
1945 mlx5e_close_rq(&c->rq);
1947 mlx5e_close_xdpsq(&c->rq_xdpsq);
1949 mlx5e_close_icosq(&c->icosq);
1950 mlx5e_close_icosq(&c->async_icosq);
1952 mlx5e_close_cq(&c->rq_xdpsq.cq);
1953 mlx5e_close_cq(&c->rq.cq);
1954 mlx5e_close_cq(&c->xdpsq.cq);
1955 mlx5e_close_tx_cqs(c);
1956 mlx5e_close_cq(&c->icosq.cq);
1957 mlx5e_close_cq(&c->async_icosq.cq);
1960 static u8 mlx5e_enumerate_lag_port(struct mlx5_core_dev *mdev, int ix)
1962 u16 port_aff_bias = mlx5_core_is_pf(mdev) ? 0 : MLX5_CAP_GEN(mdev, vhca_id);
1964 return (ix + port_aff_bias) % mlx5e_get_num_lag_ports(mdev);
1967 static int mlx5e_open_channel(struct mlx5e_priv *priv, int ix,
1968 struct mlx5e_params *params,
1969 struct mlx5e_channel_param *cparam,
1970 struct xsk_buff_pool *xsk_pool,
1971 struct mlx5e_channel **cp)
1973 int cpu = cpumask_first(mlx5_comp_irq_get_affinity_mask(priv->mdev, ix));
1974 struct net_device *netdev = priv->netdev;
1975 struct mlx5e_xsk_param xsk;
1976 struct mlx5e_channel *c;
1981 err = mlx5_vector2eqn(priv->mdev, ix, &eqn, &irq);
1985 c = kvzalloc_node(sizeof(*c), GFP_KERNEL, cpu_to_node(cpu));
1990 c->mdev = priv->mdev;
1991 c->tstamp = &priv->tstamp;
1994 c->pdev = mlx5_core_dma_dev(priv->mdev);
1995 c->netdev = priv->netdev;
1996 c->mkey_be = cpu_to_be32(priv->mdev->mlx5e_res.hw_objs.mkey.key);
1997 c->num_tc = params->num_tc;
1998 c->xdp = !!params->xdp_prog;
1999 c->stats = &priv->channel_stats[ix].ch;
2000 c->aff_mask = irq_get_effective_affinity_mask(irq);
2001 c->lag_port = mlx5e_enumerate_lag_port(priv->mdev, ix);
2003 netif_napi_add(netdev, &c->napi, mlx5e_napi_poll, 64);
2005 err = mlx5e_open_queues(c, params, cparam);
2010 mlx5e_build_xsk_param(xsk_pool, &xsk);
2011 err = mlx5e_open_xsk(priv, params, &xsk, xsk_pool, c);
2013 goto err_close_queues;
2021 mlx5e_close_queues(c);
2024 netif_napi_del(&c->napi);
2031 static void mlx5e_activate_channel(struct mlx5e_channel *c)
2035 napi_enable(&c->napi);
2037 for (tc = 0; tc < c->num_tc; tc++)
2038 mlx5e_activate_txqsq(&c->sq[tc]);
2039 mlx5e_activate_icosq(&c->icosq);
2040 mlx5e_activate_icosq(&c->async_icosq);
2041 mlx5e_activate_rq(&c->rq);
2043 if (test_bit(MLX5E_CHANNEL_STATE_XSK, c->state))
2044 mlx5e_activate_xsk(c);
2047 static void mlx5e_deactivate_channel(struct mlx5e_channel *c)
2051 if (test_bit(MLX5E_CHANNEL_STATE_XSK, c->state))
2052 mlx5e_deactivate_xsk(c);
2054 mlx5e_deactivate_rq(&c->rq);
2055 mlx5e_deactivate_icosq(&c->async_icosq);
2056 mlx5e_deactivate_icosq(&c->icosq);
2057 for (tc = 0; tc < c->num_tc; tc++)
2058 mlx5e_deactivate_txqsq(&c->sq[tc]);
2059 mlx5e_qos_deactivate_queues(c);
2061 napi_disable(&c->napi);
2064 static void mlx5e_close_channel(struct mlx5e_channel *c)
2066 if (test_bit(MLX5E_CHANNEL_STATE_XSK, c->state))
2068 mlx5e_close_queues(c);
2069 mlx5e_qos_close_queues(c);
2070 netif_napi_del(&c->napi);
2075 int mlx5e_open_channels(struct mlx5e_priv *priv,
2076 struct mlx5e_channels *chs)
2078 struct mlx5e_channel_param *cparam;
2082 chs->num = chs->params.num_channels;
2084 chs->c = kcalloc(chs->num, sizeof(struct mlx5e_channel *), GFP_KERNEL);
2085 cparam = kvzalloc(sizeof(struct mlx5e_channel_param), GFP_KERNEL);
2086 if (!chs->c || !cparam)
2089 err = mlx5e_build_channel_param(priv->mdev, &chs->params, priv->q_counter, cparam);
2093 for (i = 0; i < chs->num; i++) {
2094 struct xsk_buff_pool *xsk_pool = NULL;
2096 if (chs->params.xdp_prog)
2097 xsk_pool = mlx5e_xsk_get_pool(&chs->params, chs->params.xsk, i);
2099 err = mlx5e_open_channel(priv, i, &chs->params, cparam, xsk_pool, &chs->c[i]);
2101 goto err_close_channels;
2104 if (MLX5E_GET_PFLAG(&chs->params, MLX5E_PFLAG_TX_PORT_TS) || chs->params.ptp_rx) {
2105 err = mlx5e_ptp_open(priv, &chs->params, chs->c[0]->lag_port, &chs->ptp);
2107 goto err_close_channels;
2110 err = mlx5e_qos_open_queues(priv, chs);
2114 mlx5e_health_channels_update(priv);
2120 mlx5e_ptp_close(chs->ptp);
2123 for (i--; i >= 0; i--)
2124 mlx5e_close_channel(chs->c[i]);
2133 static void mlx5e_activate_channels(struct mlx5e_channels *chs)
2137 for (i = 0; i < chs->num; i++)
2138 mlx5e_activate_channel(chs->c[i]);
2141 mlx5e_ptp_activate_channel(chs->ptp);
2144 #define MLX5E_RQ_WQES_TIMEOUT 20000 /* msecs */
2146 static int mlx5e_wait_channels_min_rx_wqes(struct mlx5e_channels *chs)
2151 for (i = 0; i < chs->num; i++) {
2152 int timeout = err ? 0 : MLX5E_RQ_WQES_TIMEOUT;
2154 err |= mlx5e_wait_for_min_rx_wqes(&chs->c[i]->rq, timeout);
2156 /* Don't wait on the XSK RQ, because the newer xdpsock sample
2157 * doesn't provide any Fill Ring entries at the setup stage.
2161 return err ? -ETIMEDOUT : 0;
2164 static void mlx5e_deactivate_channels(struct mlx5e_channels *chs)
2169 mlx5e_ptp_deactivate_channel(chs->ptp);
2171 for (i = 0; i < chs->num; i++)
2172 mlx5e_deactivate_channel(chs->c[i]);
2175 void mlx5e_close_channels(struct mlx5e_channels *chs)
2180 mlx5e_ptp_close(chs->ptp);
2183 for (i = 0; i < chs->num; i++)
2184 mlx5e_close_channel(chs->c[i]);
2191 mlx5e_create_rqt(struct mlx5e_priv *priv, int sz, struct mlx5e_rqt *rqt)
2193 struct mlx5_core_dev *mdev = priv->mdev;
2200 inlen = MLX5_ST_SZ_BYTES(create_rqt_in) + sizeof(u32) * sz;
2201 in = kvzalloc(inlen, GFP_KERNEL);
2205 rqtc = MLX5_ADDR_OF(create_rqt_in, in, rqt_context);
2207 MLX5_SET(rqtc, rqtc, rqt_actual_size, sz);
2208 MLX5_SET(rqtc, rqtc, rqt_max_size, sz);
2210 for (i = 0; i < sz; i++)
2211 MLX5_SET(rqtc, rqtc, rq_num[i], priv->drop_rq.rqn);
2213 err = mlx5_core_create_rqt(mdev, in, inlen, &rqt->rqtn);
2215 rqt->enabled = true;
2221 void mlx5e_destroy_rqt(struct mlx5e_priv *priv, struct mlx5e_rqt *rqt)
2223 rqt->enabled = false;
2224 mlx5_core_destroy_rqt(priv->mdev, rqt->rqtn);
2227 int mlx5e_create_indirect_rqt(struct mlx5e_priv *priv)
2229 struct mlx5e_rqt *rqt = &priv->indir_rqt;
2232 err = mlx5e_create_rqt(priv, MLX5E_INDIR_RQT_SIZE, rqt);
2234 mlx5_core_warn(priv->mdev, "create indirect rqts failed, %d\n", err);
2238 int mlx5e_create_direct_rqts(struct mlx5e_priv *priv, struct mlx5e_tir *tirs, int n)
2243 for (ix = 0; ix < n; ix++) {
2244 err = mlx5e_create_rqt(priv, 1 /*size */, &tirs[ix].rqt);
2246 goto err_destroy_rqts;
2252 mlx5_core_warn(priv->mdev, "create rqts failed, %d\n", err);
2253 for (ix--; ix >= 0; ix--)
2254 mlx5e_destroy_rqt(priv, &tirs[ix].rqt);
2259 void mlx5e_destroy_direct_rqts(struct mlx5e_priv *priv, struct mlx5e_tir *tirs, int n)
2263 for (i = 0; i < n; i++)
2264 mlx5e_destroy_rqt(priv, &tirs[i].rqt);
2267 static int mlx5e_rx_hash_fn(int hfunc)
2269 return (hfunc == ETH_RSS_HASH_TOP) ?
2270 MLX5_RX_HASH_FN_TOEPLITZ :
2271 MLX5_RX_HASH_FN_INVERTED_XOR8;
2274 int mlx5e_bits_invert(unsigned long a, int size)
2279 for (i = 0; i < size; i++)
2280 inv |= (test_bit(size - i - 1, &a) ? 1 : 0) << i;
2285 static void mlx5e_fill_rqt_rqns(struct mlx5e_priv *priv, int sz,
2286 struct mlx5e_redirect_rqt_param rrp, void *rqtc)
2290 for (i = 0; i < sz; i++) {
2296 if (rrp.rss.hfunc == ETH_RSS_HASH_XOR)
2297 ix = mlx5e_bits_invert(i, ilog2(sz));
2299 ix = priv->rss_params.indirection_rqt[ix];
2300 rqn = rrp.rss.channels->c[ix]->rq.rqn;
2304 MLX5_SET(rqtc, rqtc, rq_num[i], rqn);
2308 int mlx5e_redirect_rqt(struct mlx5e_priv *priv, u32 rqtn, int sz,
2309 struct mlx5e_redirect_rqt_param rrp)
2311 struct mlx5_core_dev *mdev = priv->mdev;
2317 inlen = MLX5_ST_SZ_BYTES(modify_rqt_in) + sizeof(u32) * sz;
2318 in = kvzalloc(inlen, GFP_KERNEL);
2322 rqtc = MLX5_ADDR_OF(modify_rqt_in, in, ctx);
2324 MLX5_SET(rqtc, rqtc, rqt_actual_size, sz);
2325 MLX5_SET(modify_rqt_in, in, bitmask.rqn_list, 1);
2326 mlx5e_fill_rqt_rqns(priv, sz, rrp, rqtc);
2327 err = mlx5_core_modify_rqt(mdev, rqtn, in, inlen);
2333 static u32 mlx5e_get_direct_rqn(struct mlx5e_priv *priv, int ix,
2334 struct mlx5e_redirect_rqt_param rrp)
2339 if (ix >= rrp.rss.channels->num)
2340 return priv->drop_rq.rqn;
2342 return rrp.rss.channels->c[ix]->rq.rqn;
2345 static void mlx5e_redirect_rqts(struct mlx5e_priv *priv,
2346 struct mlx5e_redirect_rqt_param rrp,
2347 struct mlx5e_redirect_rqt_param *ptp_rrp)
2352 if (priv->indir_rqt.enabled) {
2354 rqtn = priv->indir_rqt.rqtn;
2355 mlx5e_redirect_rqt(priv, rqtn, MLX5E_INDIR_RQT_SIZE, rrp);
2358 for (ix = 0; ix < priv->max_nch; ix++) {
2359 struct mlx5e_redirect_rqt_param direct_rrp = {
2362 .rqn = mlx5e_get_direct_rqn(priv, ix, rrp)
2366 /* Direct RQ Tables */
2367 if (!priv->direct_tir[ix].rqt.enabled)
2370 rqtn = priv->direct_tir[ix].rqt.rqtn;
2371 mlx5e_redirect_rqt(priv, rqtn, 1, direct_rrp);
2374 rqtn = priv->ptp_tir.rqt.rqtn;
2375 mlx5e_redirect_rqt(priv, rqtn, 1, *ptp_rrp);
2379 static void mlx5e_redirect_rqts_to_channels(struct mlx5e_priv *priv,
2380 struct mlx5e_channels *chs)
2382 bool rx_ptp_support = priv->profile->rx_ptp_support;
2383 struct mlx5e_redirect_rqt_param *ptp_rrp_p = NULL;
2384 struct mlx5e_redirect_rqt_param rrp = {
2389 .hfunc = priv->rss_params.hfunc,
2393 struct mlx5e_redirect_rqt_param ptp_rrp;
2395 if (rx_ptp_support) {
2398 ptp_rrp.is_rss = false;
2399 ptp_rrp.rqn = mlx5e_ptp_get_rqn(priv->channels.ptp, &ptp_rqn) ?
2400 priv->drop_rq.rqn : ptp_rqn;
2401 ptp_rrp_p = &ptp_rrp;
2403 mlx5e_redirect_rqts(priv, rrp, ptp_rrp_p);
2406 static void mlx5e_redirect_rqts_to_drop(struct mlx5e_priv *priv)
2408 bool rx_ptp_support = priv->profile->rx_ptp_support;
2409 struct mlx5e_redirect_rqt_param drop_rrp = {
2412 .rqn = priv->drop_rq.rqn,
2416 mlx5e_redirect_rqts(priv, drop_rrp, rx_ptp_support ? &drop_rrp : NULL);
2419 static const struct mlx5e_tirc_config tirc_default_config[MLX5E_NUM_INDIR_TIRS] = {
2420 [MLX5E_TT_IPV4_TCP] = { .l3_prot_type = MLX5_L3_PROT_TYPE_IPV4,
2421 .l4_prot_type = MLX5_L4_PROT_TYPE_TCP,
2422 .rx_hash_fields = MLX5_HASH_IP_L4PORTS,
2424 [MLX5E_TT_IPV6_TCP] = { .l3_prot_type = MLX5_L3_PROT_TYPE_IPV6,
2425 .l4_prot_type = MLX5_L4_PROT_TYPE_TCP,
2426 .rx_hash_fields = MLX5_HASH_IP_L4PORTS,
2428 [MLX5E_TT_IPV4_UDP] = { .l3_prot_type = MLX5_L3_PROT_TYPE_IPV4,
2429 .l4_prot_type = MLX5_L4_PROT_TYPE_UDP,
2430 .rx_hash_fields = MLX5_HASH_IP_L4PORTS,
2432 [MLX5E_TT_IPV6_UDP] = { .l3_prot_type = MLX5_L3_PROT_TYPE_IPV6,
2433 .l4_prot_type = MLX5_L4_PROT_TYPE_UDP,
2434 .rx_hash_fields = MLX5_HASH_IP_L4PORTS,
2436 [MLX5E_TT_IPV4_IPSEC_AH] = { .l3_prot_type = MLX5_L3_PROT_TYPE_IPV4,
2438 .rx_hash_fields = MLX5_HASH_IP_IPSEC_SPI,
2440 [MLX5E_TT_IPV6_IPSEC_AH] = { .l3_prot_type = MLX5_L3_PROT_TYPE_IPV6,
2442 .rx_hash_fields = MLX5_HASH_IP_IPSEC_SPI,
2444 [MLX5E_TT_IPV4_IPSEC_ESP] = { .l3_prot_type = MLX5_L3_PROT_TYPE_IPV4,
2446 .rx_hash_fields = MLX5_HASH_IP_IPSEC_SPI,
2448 [MLX5E_TT_IPV6_IPSEC_ESP] = { .l3_prot_type = MLX5_L3_PROT_TYPE_IPV6,
2450 .rx_hash_fields = MLX5_HASH_IP_IPSEC_SPI,
2452 [MLX5E_TT_IPV4] = { .l3_prot_type = MLX5_L3_PROT_TYPE_IPV4,
2454 .rx_hash_fields = MLX5_HASH_IP,
2456 [MLX5E_TT_IPV6] = { .l3_prot_type = MLX5_L3_PROT_TYPE_IPV6,
2458 .rx_hash_fields = MLX5_HASH_IP,
2462 struct mlx5e_tirc_config mlx5e_tirc_get_default_config(enum mlx5e_traffic_types tt)
2464 return tirc_default_config[tt];
2467 static void mlx5e_build_tir_ctx_lro(struct mlx5e_params *params, void *tirc)
2469 if (!params->lro_en)
2472 #define ROUGH_MAX_L2_L3_HDR_SZ 256
2474 MLX5_SET(tirc, tirc, lro_enable_mask,
2475 MLX5_TIRC_LRO_ENABLE_MASK_IPV4_LRO |
2476 MLX5_TIRC_LRO_ENABLE_MASK_IPV6_LRO);
2477 MLX5_SET(tirc, tirc, lro_max_ip_payload_size,
2478 (MLX5E_PARAMS_DEFAULT_LRO_WQE_SZ - ROUGH_MAX_L2_L3_HDR_SZ) >> 8);
2479 MLX5_SET(tirc, tirc, lro_timeout_period_usecs, params->lro_timeout);
2482 void mlx5e_build_indir_tir_ctx_hash(struct mlx5e_rss_params *rss_params,
2483 const struct mlx5e_tirc_config *ttconfig,
2484 void *tirc, bool inner)
2486 void *hfso = inner ? MLX5_ADDR_OF(tirc, tirc, rx_hash_field_selector_inner) :
2487 MLX5_ADDR_OF(tirc, tirc, rx_hash_field_selector_outer);
2489 MLX5_SET(tirc, tirc, rx_hash_fn, mlx5e_rx_hash_fn(rss_params->hfunc));
2490 if (rss_params->hfunc == ETH_RSS_HASH_TOP) {
2491 void *rss_key = MLX5_ADDR_OF(tirc, tirc,
2492 rx_hash_toeplitz_key);
2493 size_t len = MLX5_FLD_SZ_BYTES(tirc,
2494 rx_hash_toeplitz_key);
2496 MLX5_SET(tirc, tirc, rx_hash_symmetric, 1);
2497 memcpy(rss_key, rss_params->toeplitz_hash_key, len);
2499 MLX5_SET(rx_hash_field_select, hfso, l3_prot_type,
2500 ttconfig->l3_prot_type);
2501 MLX5_SET(rx_hash_field_select, hfso, l4_prot_type,
2502 ttconfig->l4_prot_type);
2503 MLX5_SET(rx_hash_field_select, hfso, selected_fields,
2504 ttconfig->rx_hash_fields);
2507 static void mlx5e_update_rx_hash_fields(struct mlx5e_tirc_config *ttconfig,
2508 enum mlx5e_traffic_types tt,
2511 *ttconfig = tirc_default_config[tt];
2512 ttconfig->rx_hash_fields = rx_hash_fields;
2515 void mlx5e_modify_tirs_hash(struct mlx5e_priv *priv, void *in)
2517 void *tirc = MLX5_ADDR_OF(modify_tir_in, in, ctx);
2518 struct mlx5e_rss_params *rss = &priv->rss_params;
2519 struct mlx5_core_dev *mdev = priv->mdev;
2520 int ctxlen = MLX5_ST_SZ_BYTES(tirc);
2521 struct mlx5e_tirc_config ttconfig;
2524 MLX5_SET(modify_tir_in, in, bitmask.hash, 1);
2526 for (tt = 0; tt < MLX5E_NUM_INDIR_TIRS; tt++) {
2527 memset(tirc, 0, ctxlen);
2528 mlx5e_update_rx_hash_fields(&ttconfig, tt,
2529 rss->rx_hash_fields[tt]);
2530 mlx5e_build_indir_tir_ctx_hash(rss, &ttconfig, tirc, false);
2531 mlx5_core_modify_tir(mdev, priv->indir_tir[tt].tirn, in);
2534 /* Verify inner tirs resources allocated */
2535 if (!priv->inner_indir_tir[0].tirn)
2538 for (tt = 0; tt < MLX5E_NUM_INDIR_TIRS; tt++) {
2539 memset(tirc, 0, ctxlen);
2540 mlx5e_update_rx_hash_fields(&ttconfig, tt,
2541 rss->rx_hash_fields[tt]);
2542 mlx5e_build_indir_tir_ctx_hash(rss, &ttconfig, tirc, true);
2543 mlx5_core_modify_tir(mdev, priv->inner_indir_tir[tt].tirn, in);
2547 static int mlx5e_modify_tirs_lro(struct mlx5e_priv *priv)
2549 struct mlx5_core_dev *mdev = priv->mdev;
2558 inlen = MLX5_ST_SZ_BYTES(modify_tir_in);
2559 in = kvzalloc(inlen, GFP_KERNEL);
2563 MLX5_SET(modify_tir_in, in, bitmask.lro, 1);
2564 tirc = MLX5_ADDR_OF(modify_tir_in, in, ctx);
2566 mlx5e_build_tir_ctx_lro(&priv->channels.params, tirc);
2568 for (tt = 0; tt < MLX5E_NUM_INDIR_TIRS; tt++) {
2569 err = mlx5_core_modify_tir(mdev, priv->indir_tir[tt].tirn, in);
2574 for (ix = 0; ix < priv->max_nch; ix++) {
2575 err = mlx5_core_modify_tir(mdev, priv->direct_tir[ix].tirn, in);
2586 static MLX5E_DEFINE_PREACTIVATE_WRAPPER_CTX(mlx5e_modify_tirs_lro);
2588 static int mlx5e_set_mtu(struct mlx5_core_dev *mdev,
2589 struct mlx5e_params *params, u16 mtu)
2591 u16 hw_mtu = MLX5E_SW2HW_MTU(params, mtu);
2594 err = mlx5_set_port_mtu(mdev, hw_mtu, 1);
2598 /* Update vport context MTU */
2599 mlx5_modify_nic_vport_mtu(mdev, hw_mtu);
2603 static void mlx5e_query_mtu(struct mlx5_core_dev *mdev,
2604 struct mlx5e_params *params, u16 *mtu)
2609 err = mlx5_query_nic_vport_mtu(mdev, &hw_mtu);
2610 if (err || !hw_mtu) /* fallback to port oper mtu */
2611 mlx5_query_port_oper_mtu(mdev, &hw_mtu, 1);
2613 *mtu = MLX5E_HW2SW_MTU(params, hw_mtu);
2616 int mlx5e_set_dev_port_mtu(struct mlx5e_priv *priv)
2618 struct mlx5e_params *params = &priv->channels.params;
2619 struct net_device *netdev = priv->netdev;
2620 struct mlx5_core_dev *mdev = priv->mdev;
2624 err = mlx5e_set_mtu(mdev, params, params->sw_mtu);
2628 mlx5e_query_mtu(mdev, params, &mtu);
2629 if (mtu != params->sw_mtu)
2630 netdev_warn(netdev, "%s: VPort MTU %d is different than netdev mtu %d\n",
2631 __func__, mtu, params->sw_mtu);
2633 params->sw_mtu = mtu;
2637 MLX5E_DEFINE_PREACTIVATE_WRAPPER_CTX(mlx5e_set_dev_port_mtu);
2639 void mlx5e_set_netdev_mtu_boundaries(struct mlx5e_priv *priv)
2641 struct mlx5e_params *params = &priv->channels.params;
2642 struct net_device *netdev = priv->netdev;
2643 struct mlx5_core_dev *mdev = priv->mdev;
2646 /* MTU range: 68 - hw-specific max */
2647 netdev->min_mtu = ETH_MIN_MTU;
2649 mlx5_query_port_max_mtu(mdev, &max_mtu, 1);
2650 netdev->max_mtu = min_t(unsigned int, MLX5E_HW2SW_MTU(params, max_mtu),
2654 static void mlx5e_netdev_set_tcs(struct net_device *netdev, u16 nch, u8 ntc)
2658 netdev_reset_tc(netdev);
2663 netdev_set_num_tc(netdev, ntc);
2665 /* Map netdev TCs to offset 0
2666 * We have our own UP to TXQ mapping for QoS
2668 for (tc = 0; tc < ntc; tc++)
2669 netdev_set_tc_queue(netdev, tc, nch, 0);
2672 int mlx5e_update_tx_netdev_queues(struct mlx5e_priv *priv)
2674 int qos_queues, nch, ntc, num_txqs, err;
2676 qos_queues = mlx5e_qos_cur_leaf_nodes(priv);
2678 nch = priv->channels.params.num_channels;
2679 ntc = priv->channels.params.num_tc;
2680 num_txqs = nch * ntc + qos_queues;
2681 if (MLX5E_GET_PFLAG(&priv->channels.params, MLX5E_PFLAG_TX_PORT_TS))
2684 mlx5e_dbg(DRV, priv, "Setting num_txqs %d\n", num_txqs);
2685 err = netif_set_real_num_tx_queues(priv->netdev, num_txqs);
2687 netdev_warn(priv->netdev, "netif_set_real_num_tx_queues failed, %d\n", err);
2692 static int mlx5e_update_netdev_queues(struct mlx5e_priv *priv)
2694 struct net_device *netdev = priv->netdev;
2695 int old_num_txqs, old_ntc;
2696 int num_rxqs, nch, ntc;
2699 old_num_txqs = netdev->real_num_tx_queues;
2700 old_ntc = netdev->num_tc;
2702 nch = priv->channels.params.num_channels;
2703 ntc = priv->channels.params.num_tc;
2704 num_rxqs = nch * priv->profile->rq_groups;
2705 if (priv->channels.params.ptp_rx)
2708 mlx5e_netdev_set_tcs(netdev, nch, ntc);
2710 err = mlx5e_update_tx_netdev_queues(priv);
2713 err = netif_set_real_num_rx_queues(netdev, num_rxqs);
2715 netdev_warn(netdev, "netif_set_real_num_rx_queues failed, %d\n", err);
2722 /* netif_set_real_num_rx_queues could fail only when nch increased. Only
2723 * one of nch and ntc is changed in this function. That means, the call
2724 * to netif_set_real_num_tx_queues below should not fail, because it
2725 * decreases the number of TX queues.
2727 WARN_ON_ONCE(netif_set_real_num_tx_queues(netdev, old_num_txqs));
2730 mlx5e_netdev_set_tcs(netdev, old_num_txqs / old_ntc, old_ntc);
2734 static void mlx5e_set_default_xps_cpumasks(struct mlx5e_priv *priv,
2735 struct mlx5e_params *params)
2737 struct mlx5_core_dev *mdev = priv->mdev;
2738 int num_comp_vectors, ix, irq;
2740 num_comp_vectors = mlx5_comp_vectors_count(mdev);
2742 for (ix = 0; ix < params->num_channels; ix++) {
2743 cpumask_clear(priv->scratchpad.cpumask);
2745 for (irq = ix; irq < num_comp_vectors; irq += params->num_channels) {
2746 int cpu = cpumask_first(mlx5_comp_irq_get_affinity_mask(mdev, irq));
2748 cpumask_set_cpu(cpu, priv->scratchpad.cpumask);
2751 netif_set_xps_queue(priv->netdev, priv->scratchpad.cpumask, ix);
2755 int mlx5e_num_channels_changed(struct mlx5e_priv *priv)
2757 u16 count = priv->channels.params.num_channels;
2760 err = mlx5e_update_netdev_queues(priv);
2764 mlx5e_set_default_xps_cpumasks(priv, &priv->channels.params);
2766 if (!netif_is_rxfh_configured(priv->netdev))
2767 mlx5e_build_default_indir_rqt(priv->rss_params.indirection_rqt,
2768 MLX5E_INDIR_RQT_SIZE, count);
2773 MLX5E_DEFINE_PREACTIVATE_WRAPPER_CTX(mlx5e_num_channels_changed);
2775 static void mlx5e_build_txq_maps(struct mlx5e_priv *priv)
2777 int i, ch, tc, num_tc;
2779 ch = priv->channels.num;
2780 num_tc = priv->channels.params.num_tc;
2782 for (i = 0; i < ch; i++) {
2783 for (tc = 0; tc < num_tc; tc++) {
2784 struct mlx5e_channel *c = priv->channels.c[i];
2785 struct mlx5e_txqsq *sq = &c->sq[tc];
2787 priv->txq2sq[sq->txq_ix] = sq;
2788 priv->channel_tc2realtxq[i][tc] = i + tc * ch;
2792 if (!priv->channels.ptp)
2795 if (!test_bit(MLX5E_PTP_STATE_TX, priv->channels.ptp->state))
2798 for (tc = 0; tc < num_tc; tc++) {
2799 struct mlx5e_ptp *c = priv->channels.ptp;
2800 struct mlx5e_txqsq *sq = &c->ptpsq[tc].txqsq;
2802 priv->txq2sq[sq->txq_ix] = sq;
2803 priv->port_ptp_tc2realtxq[tc] = priv->num_tc_x_num_ch + tc;
2807 static void mlx5e_update_num_tc_x_num_ch(struct mlx5e_priv *priv)
2809 /* Sync with mlx5e_select_queue. */
2810 WRITE_ONCE(priv->num_tc_x_num_ch,
2811 priv->channels.params.num_tc * priv->channels.num);
2814 void mlx5e_activate_priv_channels(struct mlx5e_priv *priv)
2816 mlx5e_update_num_tc_x_num_ch(priv);
2817 mlx5e_build_txq_maps(priv);
2818 mlx5e_activate_channels(&priv->channels);
2819 mlx5e_qos_activate_queues(priv);
2820 mlx5e_xdp_tx_enable(priv);
2821 netif_tx_start_all_queues(priv->netdev);
2823 if (mlx5e_is_vport_rep(priv))
2824 mlx5e_add_sqs_fwd_rules(priv);
2826 mlx5e_wait_channels_min_rx_wqes(&priv->channels);
2827 mlx5e_redirect_rqts_to_channels(priv, &priv->channels);
2829 mlx5e_xsk_redirect_rqts_to_channels(priv, &priv->channels);
2832 void mlx5e_deactivate_priv_channels(struct mlx5e_priv *priv)
2834 mlx5e_xsk_redirect_rqts_to_drop(priv, &priv->channels);
2836 mlx5e_redirect_rqts_to_drop(priv);
2838 if (mlx5e_is_vport_rep(priv))
2839 mlx5e_remove_sqs_fwd_rules(priv);
2841 /* FIXME: This is a W/A only for tx timeout watch dog false alarm when
2842 * polling for inactive tx queues.
2844 netif_tx_stop_all_queues(priv->netdev);
2845 netif_tx_disable(priv->netdev);
2846 mlx5e_xdp_tx_disable(priv);
2847 mlx5e_deactivate_channels(&priv->channels);
2850 static int mlx5e_switch_priv_params(struct mlx5e_priv *priv,
2851 struct mlx5e_params *new_params,
2852 mlx5e_fp_preactivate preactivate,
2855 struct mlx5e_params old_params;
2857 old_params = priv->channels.params;
2858 priv->channels.params = *new_params;
2863 err = preactivate(priv, context);
2865 priv->channels.params = old_params;
2873 static int mlx5e_switch_priv_channels(struct mlx5e_priv *priv,
2874 struct mlx5e_channels *new_chs,
2875 mlx5e_fp_preactivate preactivate,
2878 struct net_device *netdev = priv->netdev;
2879 struct mlx5e_channels old_chs;
2883 carrier_ok = netif_carrier_ok(netdev);
2884 netif_carrier_off(netdev);
2886 mlx5e_deactivate_priv_channels(priv);
2888 old_chs = priv->channels;
2889 priv->channels = *new_chs;
2891 /* New channels are ready to roll, call the preactivate hook if needed
2892 * to modify HW settings or update kernel parameters.
2895 err = preactivate(priv, context);
2897 priv->channels = old_chs;
2902 mlx5e_close_channels(&old_chs);
2903 priv->profile->update_rx(priv);
2906 mlx5e_activate_priv_channels(priv);
2908 /* return carrier back if needed */
2910 netif_carrier_on(netdev);
2915 int mlx5e_safe_switch_params(struct mlx5e_priv *priv,
2916 struct mlx5e_params *params,
2917 mlx5e_fp_preactivate preactivate,
2918 void *context, bool reset)
2920 struct mlx5e_channels new_chs = {};
2923 reset &= test_bit(MLX5E_STATE_OPENED, &priv->state);
2925 return mlx5e_switch_priv_params(priv, params, preactivate, context);
2927 new_chs.params = *params;
2928 err = mlx5e_open_channels(priv, &new_chs);
2931 err = mlx5e_switch_priv_channels(priv, &new_chs, preactivate, context);
2933 mlx5e_close_channels(&new_chs);
2938 int mlx5e_safe_reopen_channels(struct mlx5e_priv *priv)
2940 return mlx5e_safe_switch_params(priv, &priv->channels.params, NULL, NULL, true);
2943 void mlx5e_timestamp_init(struct mlx5e_priv *priv)
2945 priv->tstamp.tx_type = HWTSTAMP_TX_OFF;
2946 priv->tstamp.rx_filter = HWTSTAMP_FILTER_NONE;
2949 static void mlx5e_modify_admin_state(struct mlx5_core_dev *mdev,
2950 enum mlx5_port_status state)
2952 struct mlx5_eswitch *esw = mdev->priv.eswitch;
2953 int vport_admin_state;
2955 mlx5_set_port_admin_status(mdev, state);
2957 if (mlx5_eswitch_mode(mdev) == MLX5_ESWITCH_OFFLOADS ||
2958 !MLX5_CAP_GEN(mdev, uplink_follow))
2961 if (state == MLX5_PORT_UP)
2962 vport_admin_state = MLX5_VPORT_ADMIN_STATE_AUTO;
2964 vport_admin_state = MLX5_VPORT_ADMIN_STATE_DOWN;
2966 mlx5_eswitch_set_vport_state(esw, MLX5_VPORT_UPLINK, vport_admin_state);
2969 int mlx5e_open_locked(struct net_device *netdev)
2971 struct mlx5e_priv *priv = netdev_priv(netdev);
2974 set_bit(MLX5E_STATE_OPENED, &priv->state);
2976 err = mlx5e_open_channels(priv, &priv->channels);
2978 goto err_clear_state_opened_flag;
2980 priv->profile->update_rx(priv);
2981 mlx5e_activate_priv_channels(priv);
2982 mlx5e_apply_traps(priv, true);
2983 if (priv->profile->update_carrier)
2984 priv->profile->update_carrier(priv);
2986 mlx5e_queue_update_stats(priv);
2989 err_clear_state_opened_flag:
2990 clear_bit(MLX5E_STATE_OPENED, &priv->state);
2994 int mlx5e_open(struct net_device *netdev)
2996 struct mlx5e_priv *priv = netdev_priv(netdev);
2999 mutex_lock(&priv->state_lock);
3000 err = mlx5e_open_locked(netdev);
3002 mlx5e_modify_admin_state(priv->mdev, MLX5_PORT_UP);
3003 mutex_unlock(&priv->state_lock);
3008 int mlx5e_close_locked(struct net_device *netdev)
3010 struct mlx5e_priv *priv = netdev_priv(netdev);
3012 /* May already be CLOSED in case a previous configuration operation
3013 * (e.g RX/TX queue size change) that involves close&open failed.
3015 if (!test_bit(MLX5E_STATE_OPENED, &priv->state))
3018 mlx5e_apply_traps(priv, false);
3019 clear_bit(MLX5E_STATE_OPENED, &priv->state);
3021 netif_carrier_off(priv->netdev);
3022 mlx5e_deactivate_priv_channels(priv);
3023 mlx5e_close_channels(&priv->channels);
3028 int mlx5e_close(struct net_device *netdev)
3030 struct mlx5e_priv *priv = netdev_priv(netdev);
3033 if (!netif_device_present(netdev))
3036 mutex_lock(&priv->state_lock);
3037 mlx5e_modify_admin_state(priv->mdev, MLX5_PORT_DOWN);
3038 err = mlx5e_close_locked(netdev);
3039 mutex_unlock(&priv->state_lock);
3044 static void mlx5e_free_drop_rq(struct mlx5e_rq *rq)
3046 mlx5_wq_destroy(&rq->wq_ctrl);
3049 static int mlx5e_alloc_drop_rq(struct mlx5_core_dev *mdev,
3050 struct mlx5e_rq *rq,
3051 struct mlx5e_rq_param *param)
3053 void *rqc = param->rqc;
3054 void *rqc_wq = MLX5_ADDR_OF(rqc, rqc, wq);
3057 param->wq.db_numa_node = param->wq.buf_numa_node;
3059 err = mlx5_wq_cyc_create(mdev, ¶m->wq, rqc_wq, &rq->wqe.wq,
3064 /* Mark as unused given "Drop-RQ" packets never reach XDP */
3065 xdp_rxq_info_unused(&rq->xdp_rxq);
3072 static int mlx5e_alloc_drop_cq(struct mlx5e_priv *priv,
3073 struct mlx5e_cq *cq,
3074 struct mlx5e_cq_param *param)
3076 struct mlx5_core_dev *mdev = priv->mdev;
3078 param->wq.buf_numa_node = dev_to_node(mlx5_core_dma_dev(mdev));
3079 param->wq.db_numa_node = dev_to_node(mlx5_core_dma_dev(mdev));
3081 return mlx5e_alloc_cq_common(priv, param, cq);
3084 int mlx5e_open_drop_rq(struct mlx5e_priv *priv,
3085 struct mlx5e_rq *drop_rq)
3087 struct mlx5_core_dev *mdev = priv->mdev;
3088 struct mlx5e_cq_param cq_param = {};
3089 struct mlx5e_rq_param rq_param = {};
3090 struct mlx5e_cq *cq = &drop_rq->cq;
3093 mlx5e_build_drop_rq_param(mdev, priv->drop_rq_q_counter, &rq_param);
3095 err = mlx5e_alloc_drop_cq(priv, cq, &cq_param);
3099 err = mlx5e_create_cq(cq, &cq_param);
3103 err = mlx5e_alloc_drop_rq(mdev, drop_rq, &rq_param);
3105 goto err_destroy_cq;
3107 err = mlx5e_create_rq(drop_rq, &rq_param);
3111 err = mlx5e_modify_rq_state(drop_rq, MLX5_RQC_STATE_RST, MLX5_RQC_STATE_RDY);
3113 mlx5_core_warn(priv->mdev, "modify_rq_state failed, rx_if_down_packets won't be counted %d\n", err);
3118 mlx5e_free_drop_rq(drop_rq);
3121 mlx5e_destroy_cq(cq);
3129 void mlx5e_close_drop_rq(struct mlx5e_rq *drop_rq)
3131 mlx5e_destroy_rq(drop_rq);
3132 mlx5e_free_drop_rq(drop_rq);
3133 mlx5e_destroy_cq(&drop_rq->cq);
3134 mlx5e_free_cq(&drop_rq->cq);
3137 int mlx5e_create_tis(struct mlx5_core_dev *mdev, void *in, u32 *tisn)
3139 void *tisc = MLX5_ADDR_OF(create_tis_in, in, ctx);
3141 MLX5_SET(tisc, tisc, transport_domain, mdev->mlx5e_res.hw_objs.td.tdn);
3143 if (MLX5_GET(tisc, tisc, tls_en))
3144 MLX5_SET(tisc, tisc, pd, mdev->mlx5e_res.hw_objs.pdn);
3146 if (mlx5_lag_is_lacp_owner(mdev))
3147 MLX5_SET(tisc, tisc, strict_lag_tx_port_affinity, 1);
3149 return mlx5_core_create_tis(mdev, in, tisn);
3152 void mlx5e_destroy_tis(struct mlx5_core_dev *mdev, u32 tisn)
3154 mlx5_core_destroy_tis(mdev, tisn);
3157 void mlx5e_destroy_tises(struct mlx5e_priv *priv)
3161 for (i = 0; i < mlx5e_get_num_lag_ports(priv->mdev); i++)
3162 for (tc = 0; tc < priv->profile->max_tc; tc++)
3163 mlx5e_destroy_tis(priv->mdev, priv->tisn[i][tc]);
3166 static bool mlx5e_lag_should_assign_affinity(struct mlx5_core_dev *mdev)
3168 return MLX5_CAP_GEN(mdev, lag_tx_port_affinity) && mlx5e_get_num_lag_ports(mdev) > 1;
3171 int mlx5e_create_tises(struct mlx5e_priv *priv)
3176 for (i = 0; i < mlx5e_get_num_lag_ports(priv->mdev); i++) {
3177 for (tc = 0; tc < priv->profile->max_tc; tc++) {
3178 u32 in[MLX5_ST_SZ_DW(create_tis_in)] = {};
3181 tisc = MLX5_ADDR_OF(create_tis_in, in, ctx);
3183 MLX5_SET(tisc, tisc, prio, tc << 1);
3185 if (mlx5e_lag_should_assign_affinity(priv->mdev))
3186 MLX5_SET(tisc, tisc, lag_tx_port_affinity, i + 1);
3188 err = mlx5e_create_tis(priv->mdev, in, &priv->tisn[i][tc]);
3190 goto err_close_tises;
3197 for (; i >= 0; i--) {
3198 for (tc--; tc >= 0; tc--)
3199 mlx5e_destroy_tis(priv->mdev, priv->tisn[i][tc]);
3200 tc = priv->profile->max_tc;
3206 static void mlx5e_cleanup_nic_tx(struct mlx5e_priv *priv)
3208 mlx5e_destroy_tises(priv);
3211 static void mlx5e_build_indir_tir_ctx_common(struct mlx5e_priv *priv,
3212 u32 rqtn, u32 *tirc)
3214 MLX5_SET(tirc, tirc, transport_domain, priv->mdev->mlx5e_res.hw_objs.td.tdn);
3215 MLX5_SET(tirc, tirc, disp_type, MLX5_TIRC_DISP_TYPE_INDIRECT);
3216 MLX5_SET(tirc, tirc, indirect_table, rqtn);
3217 MLX5_SET(tirc, tirc, tunneled_offload_en,
3218 priv->channels.params.tunneled_offload_en);
3220 mlx5e_build_tir_ctx_lro(&priv->channels.params, tirc);
3223 static void mlx5e_build_indir_tir_ctx(struct mlx5e_priv *priv,
3224 enum mlx5e_traffic_types tt,
3227 mlx5e_build_indir_tir_ctx_common(priv, priv->indir_rqt.rqtn, tirc);
3228 mlx5e_build_indir_tir_ctx_hash(&priv->rss_params,
3229 &tirc_default_config[tt], tirc, false);
3232 static void mlx5e_build_direct_tir_ctx(struct mlx5e_priv *priv, u32 rqtn, u32 *tirc)
3234 mlx5e_build_indir_tir_ctx_common(priv, rqtn, tirc);
3235 MLX5_SET(tirc, tirc, rx_hash_fn, MLX5_RX_HASH_FN_INVERTED_XOR8);
3238 static void mlx5e_build_inner_indir_tir_ctx(struct mlx5e_priv *priv,
3239 enum mlx5e_traffic_types tt,
3242 mlx5e_build_indir_tir_ctx_common(priv, priv->indir_rqt.rqtn, tirc);
3243 mlx5e_build_indir_tir_ctx_hash(&priv->rss_params,
3244 &tirc_default_config[tt], tirc, true);
3247 int mlx5e_create_indirect_tirs(struct mlx5e_priv *priv, bool inner_ttc)
3249 struct mlx5e_tir *tir;
3257 inlen = MLX5_ST_SZ_BYTES(create_tir_in);
3258 in = kvzalloc(inlen, GFP_KERNEL);
3262 for (tt = 0; tt < MLX5E_NUM_INDIR_TIRS; tt++) {
3263 memset(in, 0, inlen);
3264 tir = &priv->indir_tir[tt];
3265 tirc = MLX5_ADDR_OF(create_tir_in, in, ctx);
3266 mlx5e_build_indir_tir_ctx(priv, tt, tirc);
3267 err = mlx5e_create_tir(priv->mdev, tir, in);
3269 mlx5_core_warn(priv->mdev, "create indirect tirs failed, %d\n", err);
3270 goto err_destroy_inner_tirs;
3274 if (!inner_ttc || !mlx5e_tunnel_inner_ft_supported(priv->mdev))
3277 for (i = 0; i < MLX5E_NUM_INDIR_TIRS; i++) {
3278 memset(in, 0, inlen);
3279 tir = &priv->inner_indir_tir[i];
3280 tirc = MLX5_ADDR_OF(create_tir_in, in, ctx);
3281 mlx5e_build_inner_indir_tir_ctx(priv, i, tirc);
3282 err = mlx5e_create_tir(priv->mdev, tir, in);
3284 mlx5_core_warn(priv->mdev, "create inner indirect tirs failed, %d\n", err);
3285 goto err_destroy_inner_tirs;
3294 err_destroy_inner_tirs:
3295 for (i--; i >= 0; i--)
3296 mlx5e_destroy_tir(priv->mdev, &priv->inner_indir_tir[i]);
3298 for (tt--; tt >= 0; tt--)
3299 mlx5e_destroy_tir(priv->mdev, &priv->indir_tir[tt]);
3306 int mlx5e_create_direct_tirs(struct mlx5e_priv *priv, struct mlx5e_tir *tirs, int n)
3308 struct mlx5e_tir *tir;
3315 inlen = MLX5_ST_SZ_BYTES(create_tir_in);
3316 in = kvzalloc(inlen, GFP_KERNEL);
3320 for (ix = 0; ix < n; ix++) {
3321 memset(in, 0, inlen);
3323 tirc = MLX5_ADDR_OF(create_tir_in, in, ctx);
3324 mlx5e_build_direct_tir_ctx(priv, tir->rqt.rqtn, tirc);
3325 err = mlx5e_create_tir(priv->mdev, tir, in);
3327 goto err_destroy_ch_tirs;
3332 err_destroy_ch_tirs:
3333 mlx5_core_warn(priv->mdev, "create tirs failed, %d\n", err);
3334 for (ix--; ix >= 0; ix--)
3335 mlx5e_destroy_tir(priv->mdev, &tirs[ix]);
3343 void mlx5e_destroy_indirect_tirs(struct mlx5e_priv *priv)
3347 for (i = 0; i < MLX5E_NUM_INDIR_TIRS; i++)
3348 mlx5e_destroy_tir(priv->mdev, &priv->indir_tir[i]);
3350 /* Verify inner tirs resources allocated */
3351 if (!priv->inner_indir_tir[0].tirn)
3354 for (i = 0; i < MLX5E_NUM_INDIR_TIRS; i++)
3355 mlx5e_destroy_tir(priv->mdev, &priv->inner_indir_tir[i]);
3358 void mlx5e_destroy_direct_tirs(struct mlx5e_priv *priv, struct mlx5e_tir *tirs, int n)
3362 for (i = 0; i < n; i++)
3363 mlx5e_destroy_tir(priv->mdev, &tirs[i]);
3366 static int mlx5e_modify_channels_scatter_fcs(struct mlx5e_channels *chs, bool enable)
3371 for (i = 0; i < chs->num; i++) {
3372 err = mlx5e_modify_rq_scatter_fcs(&chs->c[i]->rq, enable);
3380 static int mlx5e_modify_channels_vsd(struct mlx5e_channels *chs, bool vsd)
3385 for (i = 0; i < chs->num; i++) {
3386 err = mlx5e_modify_rq_vsd(&chs->c[i]->rq, vsd);
3394 static int mlx5e_setup_tc_mqprio(struct mlx5e_priv *priv,
3395 struct tc_mqprio_qopt *mqprio)
3397 struct mlx5e_params new_params;
3398 u8 tc = mqprio->num_tc;
3401 mqprio->hw = TC_MQPRIO_HW_OFFLOAD_TCS;
3403 if (tc && tc != MLX5E_MAX_NUM_TC)
3406 mutex_lock(&priv->state_lock);
3408 /* MQPRIO is another toplevel qdisc that can't be attached
3409 * simultaneously with the offloaded HTB.
3411 if (WARN_ON(priv->htb.maj_id)) {
3416 new_params = priv->channels.params;
3417 new_params.num_tc = tc ? tc : 1;
3419 err = mlx5e_safe_switch_params(priv, &new_params,
3420 mlx5e_num_channels_changed_ctx, NULL, true);
3423 priv->max_opened_tc = max_t(u8, priv->max_opened_tc,
3424 priv->channels.params.num_tc);
3425 mutex_unlock(&priv->state_lock);
3429 static int mlx5e_setup_tc_htb(struct mlx5e_priv *priv, struct tc_htb_qopt_offload *htb)
3433 switch (htb->command) {
3435 return mlx5e_htb_root_add(priv, htb->parent_classid, htb->classid,
3437 case TC_HTB_DESTROY:
3438 return mlx5e_htb_root_del(priv);
3439 case TC_HTB_LEAF_ALLOC_QUEUE:
3440 res = mlx5e_htb_leaf_alloc_queue(priv, htb->classid, htb->parent_classid,
3441 htb->rate, htb->ceil, htb->extack);
3446 case TC_HTB_LEAF_TO_INNER:
3447 return mlx5e_htb_leaf_to_inner(priv, htb->parent_classid, htb->classid,
3448 htb->rate, htb->ceil, htb->extack);
3449 case TC_HTB_LEAF_DEL:
3450 return mlx5e_htb_leaf_del(priv, htb->classid, &htb->moved_qid, &htb->qid,
3452 case TC_HTB_LEAF_DEL_LAST:
3453 case TC_HTB_LEAF_DEL_LAST_FORCE:
3454 return mlx5e_htb_leaf_del_last(priv, htb->classid,
3455 htb->command == TC_HTB_LEAF_DEL_LAST_FORCE,
3457 case TC_HTB_NODE_MODIFY:
3458 return mlx5e_htb_node_modify(priv, htb->classid, htb->rate, htb->ceil,
3460 case TC_HTB_LEAF_QUERY_QUEUE:
3461 res = mlx5e_get_txq_by_classid(priv, htb->classid);
3471 static LIST_HEAD(mlx5e_block_cb_list);
3473 static int mlx5e_setup_tc(struct net_device *dev, enum tc_setup_type type,
3476 struct mlx5e_priv *priv = netdev_priv(dev);
3477 bool tc_unbind = false;
3480 if (type == TC_SETUP_BLOCK &&
3481 ((struct flow_block_offload *)type_data)->command == FLOW_BLOCK_UNBIND)
3484 if (!netif_device_present(dev) && !tc_unbind)
3488 case TC_SETUP_BLOCK: {
3489 struct flow_block_offload *f = type_data;
3491 f->unlocked_driver_cb = true;
3492 return flow_block_cb_setup_simple(type_data,
3493 &mlx5e_block_cb_list,
3494 mlx5e_setup_tc_block_cb,
3497 case TC_SETUP_QDISC_MQPRIO:
3498 return mlx5e_setup_tc_mqprio(priv, type_data);
3499 case TC_SETUP_QDISC_HTB:
3500 mutex_lock(&priv->state_lock);
3501 err = mlx5e_setup_tc_htb(priv, type_data);
3502 mutex_unlock(&priv->state_lock);
3509 void mlx5e_fold_sw_stats64(struct mlx5e_priv *priv, struct rtnl_link_stats64 *s)
3513 for (i = 0; i < priv->max_nch; i++) {
3514 struct mlx5e_channel_stats *channel_stats = &priv->channel_stats[i];
3515 struct mlx5e_rq_stats *xskrq_stats = &channel_stats->xskrq;
3516 struct mlx5e_rq_stats *rq_stats = &channel_stats->rq;
3519 s->rx_packets += rq_stats->packets + xskrq_stats->packets;
3520 s->rx_bytes += rq_stats->bytes + xskrq_stats->bytes;
3521 s->multicast += rq_stats->mcast_packets + xskrq_stats->mcast_packets;
3523 for (j = 0; j < priv->max_opened_tc; j++) {
3524 struct mlx5e_sq_stats *sq_stats = &channel_stats->sq[j];
3526 s->tx_packets += sq_stats->packets;
3527 s->tx_bytes += sq_stats->bytes;
3528 s->tx_dropped += sq_stats->dropped;
3531 if (priv->tx_ptp_opened) {
3532 for (i = 0; i < priv->max_opened_tc; i++) {
3533 struct mlx5e_sq_stats *sq_stats = &priv->ptp_stats.sq[i];
3535 s->tx_packets += sq_stats->packets;
3536 s->tx_bytes += sq_stats->bytes;
3537 s->tx_dropped += sq_stats->dropped;
3540 if (priv->rx_ptp_opened) {
3541 struct mlx5e_rq_stats *rq_stats = &priv->ptp_stats.rq;
3543 s->rx_packets += rq_stats->packets;
3544 s->rx_bytes += rq_stats->bytes;
3545 s->multicast += rq_stats->mcast_packets;
3550 mlx5e_get_stats(struct net_device *dev, struct rtnl_link_stats64 *stats)
3552 struct mlx5e_priv *priv = netdev_priv(dev);
3553 struct mlx5e_pport_stats *pstats = &priv->stats.pport;
3555 if (!netif_device_present(dev))
3558 /* In switchdev mode, monitor counters doesn't monitor
3559 * rx/tx stats of 802_3. The update stats mechanism
3560 * should keep the 802_3 layout counters updated
3562 if (!mlx5e_monitor_counter_supported(priv) ||
3563 mlx5e_is_uplink_rep(priv)) {
3564 /* update HW stats in background for next time */
3565 mlx5e_queue_update_stats(priv);
3568 if (mlx5e_is_uplink_rep(priv)) {
3569 struct mlx5e_vport_stats *vstats = &priv->stats.vport;
3571 stats->rx_packets = PPORT_802_3_GET(pstats, a_frames_received_ok);
3572 stats->rx_bytes = PPORT_802_3_GET(pstats, a_octets_received_ok);
3573 stats->tx_packets = PPORT_802_3_GET(pstats, a_frames_transmitted_ok);
3574 stats->tx_bytes = PPORT_802_3_GET(pstats, a_octets_transmitted_ok);
3576 /* vport multicast also counts packets that are dropped due to steering
3577 * or rx out of buffer
3579 stats->multicast = VPORT_COUNTER_GET(vstats, received_eth_multicast.packets);
3581 mlx5e_fold_sw_stats64(priv, stats);
3584 stats->rx_dropped = priv->stats.qcnt.rx_out_of_buffer;
3586 stats->rx_length_errors =
3587 PPORT_802_3_GET(pstats, a_in_range_length_errors) +
3588 PPORT_802_3_GET(pstats, a_out_of_range_length_field) +
3589 PPORT_802_3_GET(pstats, a_frame_too_long_errors);
3590 stats->rx_crc_errors =
3591 PPORT_802_3_GET(pstats, a_frame_check_sequence_errors);
3592 stats->rx_frame_errors = PPORT_802_3_GET(pstats, a_alignment_errors);
3593 stats->tx_aborted_errors = PPORT_2863_GET(pstats, if_out_discards);
3594 stats->rx_errors = stats->rx_length_errors + stats->rx_crc_errors +
3595 stats->rx_frame_errors;
3596 stats->tx_errors = stats->tx_aborted_errors + stats->tx_carrier_errors;
3599 static void mlx5e_nic_set_rx_mode(struct mlx5e_priv *priv)
3601 if (mlx5e_is_uplink_rep(priv))
3602 return; /* no rx mode for uplink rep */
3604 queue_work(priv->wq, &priv->set_rx_mode_work);
3607 static void mlx5e_set_rx_mode(struct net_device *dev)
3609 struct mlx5e_priv *priv = netdev_priv(dev);
3611 mlx5e_nic_set_rx_mode(priv);
3614 static int mlx5e_set_mac(struct net_device *netdev, void *addr)
3616 struct mlx5e_priv *priv = netdev_priv(netdev);
3617 struct sockaddr *saddr = addr;
3619 if (!is_valid_ether_addr(saddr->sa_data))
3620 return -EADDRNOTAVAIL;
3622 netif_addr_lock_bh(netdev);
3623 ether_addr_copy(netdev->dev_addr, saddr->sa_data);
3624 netif_addr_unlock_bh(netdev);
3626 mlx5e_nic_set_rx_mode(priv);
3631 #define MLX5E_SET_FEATURE(features, feature, enable) \
3634 *features |= feature; \
3636 *features &= ~feature; \
3639 typedef int (*mlx5e_feature_handler)(struct net_device *netdev, bool enable);
3641 static int set_feature_lro(struct net_device *netdev, bool enable)
3643 struct mlx5e_priv *priv = netdev_priv(netdev);
3644 struct mlx5_core_dev *mdev = priv->mdev;
3645 struct mlx5e_params *cur_params;
3646 struct mlx5e_params new_params;
3650 mutex_lock(&priv->state_lock);
3652 if (enable && priv->xsk.refcnt) {
3653 netdev_warn(netdev, "LRO is incompatible with AF_XDP (%u XSKs are active)\n",
3659 cur_params = &priv->channels.params;
3660 if (enable && !MLX5E_GET_PFLAG(cur_params, MLX5E_PFLAG_RX_STRIDING_RQ)) {
3661 netdev_warn(netdev, "can't set LRO with legacy RQ\n");
3666 new_params = *cur_params;
3667 new_params.lro_en = enable;
3669 if (cur_params->rq_wq_type == MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ) {
3670 if (mlx5e_rx_mpwqe_is_linear_skb(mdev, cur_params, NULL) ==
3671 mlx5e_rx_mpwqe_is_linear_skb(mdev, &new_params, NULL))
3675 err = mlx5e_safe_switch_params(priv, &new_params,
3676 mlx5e_modify_tirs_lro_ctx, NULL, reset);
3678 mutex_unlock(&priv->state_lock);
3682 static int set_feature_cvlan_filter(struct net_device *netdev, bool enable)
3684 struct mlx5e_priv *priv = netdev_priv(netdev);
3687 mlx5e_enable_cvlan_filter(priv);
3689 mlx5e_disable_cvlan_filter(priv);
3694 static int set_feature_hw_tc(struct net_device *netdev, bool enable)
3696 struct mlx5e_priv *priv = netdev_priv(netdev);
3698 #if IS_ENABLED(CONFIG_MLX5_CLS_ACT)
3699 if (!enable && mlx5e_tc_num_filters(priv, MLX5_TC_FLAG(NIC_OFFLOAD))) {
3701 "Active offloaded tc filters, can't turn hw_tc_offload off\n");
3706 if (!enable && priv->htb.maj_id) {
3707 netdev_err(netdev, "Active HTB offload, can't turn hw_tc_offload off\n");
3714 static int set_feature_rx_all(struct net_device *netdev, bool enable)
3716 struct mlx5e_priv *priv = netdev_priv(netdev);
3717 struct mlx5_core_dev *mdev = priv->mdev;
3719 return mlx5_set_port_fcs(mdev, !enable);
3722 static int set_feature_rx_fcs(struct net_device *netdev, bool enable)
3724 struct mlx5e_priv *priv = netdev_priv(netdev);
3727 mutex_lock(&priv->state_lock);
3729 priv->channels.params.scatter_fcs_en = enable;
3730 err = mlx5e_modify_channels_scatter_fcs(&priv->channels, enable);
3732 priv->channels.params.scatter_fcs_en = !enable;
3734 mutex_unlock(&priv->state_lock);
3739 static int set_feature_rx_vlan(struct net_device *netdev, bool enable)
3741 struct mlx5e_priv *priv = netdev_priv(netdev);
3744 mutex_lock(&priv->state_lock);
3746 priv->channels.params.vlan_strip_disable = !enable;
3747 if (!test_bit(MLX5E_STATE_OPENED, &priv->state))
3750 err = mlx5e_modify_channels_vsd(&priv->channels, !enable);
3752 priv->channels.params.vlan_strip_disable = enable;
3755 mutex_unlock(&priv->state_lock);
3760 #ifdef CONFIG_MLX5_EN_ARFS
3761 static int set_feature_arfs(struct net_device *netdev, bool enable)
3763 struct mlx5e_priv *priv = netdev_priv(netdev);
3767 err = mlx5e_arfs_enable(priv);
3769 err = mlx5e_arfs_disable(priv);
3775 static int mlx5e_handle_feature(struct net_device *netdev,
3776 netdev_features_t *features,
3777 netdev_features_t wanted_features,
3778 netdev_features_t feature,
3779 mlx5e_feature_handler feature_handler)
3781 netdev_features_t changes = wanted_features ^ netdev->features;
3782 bool enable = !!(wanted_features & feature);
3785 if (!(changes & feature))
3788 err = feature_handler(netdev, enable);
3790 netdev_err(netdev, "%s feature %pNF failed, err %d\n",
3791 enable ? "Enable" : "Disable", &feature, err);
3795 MLX5E_SET_FEATURE(features, feature, enable);
3799 int mlx5e_set_features(struct net_device *netdev, netdev_features_t features)
3801 netdev_features_t oper_features = netdev->features;
3804 #define MLX5E_HANDLE_FEATURE(feature, handler) \
3805 mlx5e_handle_feature(netdev, &oper_features, features, feature, handler)
3807 err |= MLX5E_HANDLE_FEATURE(NETIF_F_LRO, set_feature_lro);
3808 err |= MLX5E_HANDLE_FEATURE(NETIF_F_HW_VLAN_CTAG_FILTER,
3809 set_feature_cvlan_filter);
3810 err |= MLX5E_HANDLE_FEATURE(NETIF_F_HW_TC, set_feature_hw_tc);
3811 err |= MLX5E_HANDLE_FEATURE(NETIF_F_RXALL, set_feature_rx_all);
3812 err |= MLX5E_HANDLE_FEATURE(NETIF_F_RXFCS, set_feature_rx_fcs);
3813 err |= MLX5E_HANDLE_FEATURE(NETIF_F_HW_VLAN_CTAG_RX, set_feature_rx_vlan);
3814 #ifdef CONFIG_MLX5_EN_ARFS
3815 err |= MLX5E_HANDLE_FEATURE(NETIF_F_NTUPLE, set_feature_arfs);
3817 err |= MLX5E_HANDLE_FEATURE(NETIF_F_HW_TLS_RX, mlx5e_ktls_set_feature_rx);
3820 netdev->features = oper_features;
3827 static netdev_features_t mlx5e_fix_features(struct net_device *netdev,
3828 netdev_features_t features)
3830 struct mlx5e_priv *priv = netdev_priv(netdev);
3831 struct mlx5e_params *params;
3833 mutex_lock(&priv->state_lock);
3834 params = &priv->channels.params;
3835 if (!priv->fs.vlan ||
3836 !bitmap_empty(mlx5e_vlan_get_active_svlans(priv->fs.vlan), VLAN_N_VID)) {
3837 /* HW strips the outer C-tag header, this is a problem
3838 * for S-tag traffic.
3840 features &= ~NETIF_F_HW_VLAN_CTAG_RX;
3841 if (!params->vlan_strip_disable)
3842 netdev_warn(netdev, "Dropping C-tag vlan stripping offload due to S-tag vlan\n");
3845 if (!MLX5E_GET_PFLAG(params, MLX5E_PFLAG_RX_STRIDING_RQ)) {
3846 if (features & NETIF_F_LRO) {
3847 netdev_warn(netdev, "Disabling LRO, not supported in legacy RQ\n");
3848 features &= ~NETIF_F_LRO;
3852 if (MLX5E_GET_PFLAG(params, MLX5E_PFLAG_RX_CQE_COMPRESS)) {
3853 features &= ~NETIF_F_RXHASH;
3854 if (netdev->features & NETIF_F_RXHASH)
3855 netdev_warn(netdev, "Disabling rxhash, not supported when CQE compress is active\n");
3858 mutex_unlock(&priv->state_lock);
3863 static bool mlx5e_xsk_validate_mtu(struct net_device *netdev,
3864 struct mlx5e_channels *chs,
3865 struct mlx5e_params *new_params,
3866 struct mlx5_core_dev *mdev)
3870 for (ix = 0; ix < chs->params.num_channels; ix++) {
3871 struct xsk_buff_pool *xsk_pool =
3872 mlx5e_xsk_get_pool(&chs->params, chs->params.xsk, ix);
3873 struct mlx5e_xsk_param xsk;
3878 mlx5e_build_xsk_param(xsk_pool, &xsk);
3880 if (!mlx5e_validate_xsk_param(new_params, &xsk, mdev)) {
3881 u32 hr = mlx5e_get_linear_rq_headroom(new_params, &xsk);
3882 int max_mtu_frame, max_mtu_page, max_mtu;
3884 /* Two criteria must be met:
3885 * 1. HW MTU + all headrooms <= XSK frame size.
3886 * 2. Size of SKBs allocated on XDP_PASS <= PAGE_SIZE.
3888 max_mtu_frame = MLX5E_HW2SW_MTU(new_params, xsk.chunk_size - hr);
3889 max_mtu_page = mlx5e_xdp_max_mtu(new_params, &xsk);
3890 max_mtu = min(max_mtu_frame, max_mtu_page);
3892 netdev_err(netdev, "MTU %d is too big for an XSK running on channel %u. Try MTU <= %d\n",
3893 new_params->sw_mtu, ix, max_mtu);
3901 int mlx5e_change_mtu(struct net_device *netdev, int new_mtu,
3902 mlx5e_fp_preactivate preactivate)
3904 struct mlx5e_priv *priv = netdev_priv(netdev);
3905 struct mlx5e_params new_params;
3906 struct mlx5e_params *params;
3910 mutex_lock(&priv->state_lock);
3912 params = &priv->channels.params;
3914 new_params = *params;
3915 new_params.sw_mtu = new_mtu;
3916 err = mlx5e_validate_params(priv->mdev, &new_params);
3920 if (params->xdp_prog &&
3921 !mlx5e_rx_is_linear_skb(&new_params, NULL)) {
3922 netdev_err(netdev, "MTU(%d) > %d is not allowed while XDP enabled\n",
3923 new_mtu, mlx5e_xdp_max_mtu(params, NULL));
3928 if (priv->xsk.refcnt &&
3929 !mlx5e_xsk_validate_mtu(netdev, &priv->channels,
3930 &new_params, priv->mdev)) {
3938 if (params->rq_wq_type == MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ) {
3939 bool is_linear_old = mlx5e_rx_mpwqe_is_linear_skb(priv->mdev, params, NULL);
3940 bool is_linear_new = mlx5e_rx_mpwqe_is_linear_skb(priv->mdev,
3942 u8 ppw_old = mlx5e_mpwqe_log_pkts_per_wqe(params, NULL);
3943 u8 ppw_new = mlx5e_mpwqe_log_pkts_per_wqe(&new_params, NULL);
3945 /* Always reset in linear mode - hw_mtu is used in data path.
3946 * Check that the mode was non-linear and didn't change.
3947 * If XSK is active, XSK RQs are linear.
3949 if (!is_linear_old && !is_linear_new && !priv->xsk.refcnt &&
3954 err = mlx5e_safe_switch_params(priv, &new_params, preactivate, NULL, reset);
3957 netdev->mtu = params->sw_mtu;
3958 mutex_unlock(&priv->state_lock);
3962 static int mlx5e_change_nic_mtu(struct net_device *netdev, int new_mtu)
3964 return mlx5e_change_mtu(netdev, new_mtu, mlx5e_set_dev_port_mtu_ctx);
3967 int mlx5e_ptp_rx_manage_fs_ctx(struct mlx5e_priv *priv, void *ctx)
3969 bool set = *(bool *)ctx;
3971 return mlx5e_ptp_rx_manage_fs(priv, set);
3974 int mlx5e_hwstamp_set(struct mlx5e_priv *priv, struct ifreq *ifr)
3976 struct mlx5e_params new_params;
3977 struct hwtstamp_config config;
3978 bool rx_cqe_compress_def;
3981 if (!MLX5_CAP_GEN(priv->mdev, device_frequency_khz) ||
3982 (mlx5_clock_get_ptp_index(priv->mdev) == -1))
3985 if (copy_from_user(&config, ifr->ifr_data, sizeof(config)))
3988 /* TX HW timestamp */
3989 switch (config.tx_type) {
3990 case HWTSTAMP_TX_OFF:
3991 case HWTSTAMP_TX_ON:
3997 mutex_lock(&priv->state_lock);
3998 new_params = priv->channels.params;
3999 rx_cqe_compress_def = priv->channels.params.rx_cqe_compress_def;
4001 /* RX HW timestamp */
4002 switch (config.rx_filter) {
4003 case HWTSTAMP_FILTER_NONE:
4004 new_params.ptp_rx = false;
4006 case HWTSTAMP_FILTER_ALL:
4007 case HWTSTAMP_FILTER_SOME:
4008 case HWTSTAMP_FILTER_PTP_V1_L4_EVENT:
4009 case HWTSTAMP_FILTER_PTP_V1_L4_SYNC:
4010 case HWTSTAMP_FILTER_PTP_V1_L4_DELAY_REQ:
4011 case HWTSTAMP_FILTER_PTP_V2_L4_EVENT:
4012 case HWTSTAMP_FILTER_PTP_V2_L4_SYNC:
4013 case HWTSTAMP_FILTER_PTP_V2_L4_DELAY_REQ:
4014 case HWTSTAMP_FILTER_PTP_V2_L2_EVENT:
4015 case HWTSTAMP_FILTER_PTP_V2_L2_SYNC:
4016 case HWTSTAMP_FILTER_PTP_V2_L2_DELAY_REQ:
4017 case HWTSTAMP_FILTER_PTP_V2_EVENT:
4018 case HWTSTAMP_FILTER_PTP_V2_SYNC:
4019 case HWTSTAMP_FILTER_PTP_V2_DELAY_REQ:
4020 case HWTSTAMP_FILTER_NTP_ALL:
4021 new_params.ptp_rx = rx_cqe_compress_def;
4022 config.rx_filter = HWTSTAMP_FILTER_ALL;
4025 mutex_unlock(&priv->state_lock);
4029 if (new_params.ptp_rx == priv->channels.params.ptp_rx)
4032 err = mlx5e_safe_switch_params(priv, &new_params, mlx5e_ptp_rx_manage_fs_ctx,
4033 &new_params.ptp_rx, true);
4035 mutex_unlock(&priv->state_lock);
4039 memcpy(&priv->tstamp, &config, sizeof(config));
4040 mutex_unlock(&priv->state_lock);
4042 /* might need to fix some features */
4043 netdev_update_features(priv->netdev);
4045 return copy_to_user(ifr->ifr_data, &config,
4046 sizeof(config)) ? -EFAULT : 0;
4049 int mlx5e_hwstamp_get(struct mlx5e_priv *priv, struct ifreq *ifr)
4051 struct hwtstamp_config *cfg = &priv->tstamp;
4053 if (!MLX5_CAP_GEN(priv->mdev, device_frequency_khz))
4056 return copy_to_user(ifr->ifr_data, cfg, sizeof(*cfg)) ? -EFAULT : 0;
4059 static int mlx5e_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
4061 struct mlx5e_priv *priv = netdev_priv(dev);
4065 return mlx5e_hwstamp_set(priv, ifr);
4067 return mlx5e_hwstamp_get(priv, ifr);
4073 #ifdef CONFIG_MLX5_ESWITCH
4074 int mlx5e_set_vf_mac(struct net_device *dev, int vf, u8 *mac)
4076 struct mlx5e_priv *priv = netdev_priv(dev);
4077 struct mlx5_core_dev *mdev = priv->mdev;
4079 return mlx5_eswitch_set_vport_mac(mdev->priv.eswitch, vf + 1, mac);
4082 static int mlx5e_set_vf_vlan(struct net_device *dev, int vf, u16 vlan, u8 qos,
4085 struct mlx5e_priv *priv = netdev_priv(dev);
4086 struct mlx5_core_dev *mdev = priv->mdev;
4088 if (vlan_proto != htons(ETH_P_8021Q))
4089 return -EPROTONOSUPPORT;
4091 return mlx5_eswitch_set_vport_vlan(mdev->priv.eswitch, vf + 1,
4095 static int mlx5e_set_vf_spoofchk(struct net_device *dev, int vf, bool setting)
4097 struct mlx5e_priv *priv = netdev_priv(dev);
4098 struct mlx5_core_dev *mdev = priv->mdev;
4100 return mlx5_eswitch_set_vport_spoofchk(mdev->priv.eswitch, vf + 1, setting);
4103 static int mlx5e_set_vf_trust(struct net_device *dev, int vf, bool setting)
4105 struct mlx5e_priv *priv = netdev_priv(dev);
4106 struct mlx5_core_dev *mdev = priv->mdev;
4108 return mlx5_eswitch_set_vport_trust(mdev->priv.eswitch, vf + 1, setting);
4111 int mlx5e_set_vf_rate(struct net_device *dev, int vf, int min_tx_rate,
4114 struct mlx5e_priv *priv = netdev_priv(dev);
4115 struct mlx5_core_dev *mdev = priv->mdev;
4117 return mlx5_eswitch_set_vport_rate(mdev->priv.eswitch, vf + 1,
4118 max_tx_rate, min_tx_rate);
4121 static int mlx5_vport_link2ifla(u8 esw_link)
4124 case MLX5_VPORT_ADMIN_STATE_DOWN:
4125 return IFLA_VF_LINK_STATE_DISABLE;
4126 case MLX5_VPORT_ADMIN_STATE_UP:
4127 return IFLA_VF_LINK_STATE_ENABLE;
4129 return IFLA_VF_LINK_STATE_AUTO;
4132 static int mlx5_ifla_link2vport(u8 ifla_link)
4134 switch (ifla_link) {
4135 case IFLA_VF_LINK_STATE_DISABLE:
4136 return MLX5_VPORT_ADMIN_STATE_DOWN;
4137 case IFLA_VF_LINK_STATE_ENABLE:
4138 return MLX5_VPORT_ADMIN_STATE_UP;
4140 return MLX5_VPORT_ADMIN_STATE_AUTO;
4143 static int mlx5e_set_vf_link_state(struct net_device *dev, int vf,
4146 struct mlx5e_priv *priv = netdev_priv(dev);
4147 struct mlx5_core_dev *mdev = priv->mdev;
4149 if (mlx5e_is_uplink_rep(priv))
4152 return mlx5_eswitch_set_vport_state(mdev->priv.eswitch, vf + 1,
4153 mlx5_ifla_link2vport(link_state));
4156 int mlx5e_get_vf_config(struct net_device *dev,
4157 int vf, struct ifla_vf_info *ivi)
4159 struct mlx5e_priv *priv = netdev_priv(dev);
4160 struct mlx5_core_dev *mdev = priv->mdev;
4163 if (!netif_device_present(dev))
4166 err = mlx5_eswitch_get_vport_config(mdev->priv.eswitch, vf + 1, ivi);
4169 ivi->linkstate = mlx5_vport_link2ifla(ivi->linkstate);
4173 int mlx5e_get_vf_stats(struct net_device *dev,
4174 int vf, struct ifla_vf_stats *vf_stats)
4176 struct mlx5e_priv *priv = netdev_priv(dev);
4177 struct mlx5_core_dev *mdev = priv->mdev;
4179 return mlx5_eswitch_get_vport_stats(mdev->priv.eswitch, vf + 1,
4184 mlx5e_has_offload_stats(const struct net_device *dev, int attr_id)
4186 struct mlx5e_priv *priv = netdev_priv(dev);
4188 if (!netif_device_present(dev))
4191 if (!mlx5e_is_uplink_rep(priv))
4194 return mlx5e_rep_has_offload_stats(dev, attr_id);
4198 mlx5e_get_offload_stats(int attr_id, const struct net_device *dev,
4201 struct mlx5e_priv *priv = netdev_priv(dev);
4203 if (!mlx5e_is_uplink_rep(priv))
4206 return mlx5e_rep_get_offload_stats(attr_id, dev, sp);
4210 static bool mlx5e_tunnel_proto_supported_tx(struct mlx5_core_dev *mdev, u8 proto_type)
4212 switch (proto_type) {
4214 return MLX5_CAP_ETH(mdev, tunnel_stateless_gre);
4217 return (MLX5_CAP_ETH(mdev, tunnel_stateless_ip_over_ip) ||
4218 MLX5_CAP_ETH(mdev, tunnel_stateless_ip_over_ip_tx));
4224 static bool mlx5e_gre_tunnel_inner_proto_offload_supported(struct mlx5_core_dev *mdev,
4225 struct sk_buff *skb)
4227 switch (skb->inner_protocol) {
4228 case htons(ETH_P_IP):
4229 case htons(ETH_P_IPV6):
4230 case htons(ETH_P_TEB):
4232 case htons(ETH_P_MPLS_UC):
4233 case htons(ETH_P_MPLS_MC):
4234 return MLX5_CAP_ETH(mdev, tunnel_stateless_mpls_over_gre);
4239 static netdev_features_t mlx5e_tunnel_features_check(struct mlx5e_priv *priv,
4240 struct sk_buff *skb,
4241 netdev_features_t features)
4243 unsigned int offset = 0;
4244 struct udphdr *udph;
4248 switch (vlan_get_protocol(skb)) {
4249 case htons(ETH_P_IP):
4250 proto = ip_hdr(skb)->protocol;
4252 case htons(ETH_P_IPV6):
4253 proto = ipv6_find_hdr(skb, &offset, -1, NULL, NULL);
4261 if (mlx5e_gre_tunnel_inner_proto_offload_supported(priv->mdev, skb))
4266 if (mlx5e_tunnel_proto_supported_tx(priv->mdev, IPPROTO_IPIP))
4270 udph = udp_hdr(skb);
4271 port = be16_to_cpu(udph->dest);
4273 /* Verify if UDP port is being offloaded by HW */
4274 if (mlx5_vxlan_lookup_port(priv->mdev->vxlan, port))
4277 #if IS_ENABLED(CONFIG_GENEVE)
4278 /* Support Geneve offload for default UDP port */
4279 if (port == GENEVE_UDP_PORT && mlx5_geneve_tx_allowed(priv->mdev))
4285 /* Disable CSUM and GSO if the udp dport is not offloaded by HW */
4286 return features & ~(NETIF_F_CSUM_MASK | NETIF_F_GSO_MASK);
4289 netdev_features_t mlx5e_features_check(struct sk_buff *skb,
4290 struct net_device *netdev,
4291 netdev_features_t features)
4293 struct mlx5e_priv *priv = netdev_priv(netdev);
4295 features = vlan_features_check(skb, features);
4296 features = vxlan_features_check(skb, features);
4298 if (mlx5e_ipsec_feature_check(skb, netdev, features))
4301 /* Validate if the tunneled packet is being offloaded by HW */
4302 if (skb->encapsulation &&
4303 (features & NETIF_F_CSUM_MASK || features & NETIF_F_GSO_MASK))
4304 return mlx5e_tunnel_features_check(priv, skb, features);
4309 static void mlx5e_tx_timeout_work(struct work_struct *work)
4311 struct mlx5e_priv *priv = container_of(work, struct mlx5e_priv,
4313 struct net_device *netdev = priv->netdev;
4317 mutex_lock(&priv->state_lock);
4319 if (!test_bit(MLX5E_STATE_OPENED, &priv->state))
4322 for (i = 0; i < netdev->real_num_tx_queues; i++) {
4323 struct netdev_queue *dev_queue =
4324 netdev_get_tx_queue(netdev, i);
4325 struct mlx5e_txqsq *sq = priv->txq2sq[i];
4327 if (!netif_xmit_stopped(dev_queue))
4330 if (mlx5e_reporter_tx_timeout(sq))
4331 /* break if tried to reopened channels */
4336 mutex_unlock(&priv->state_lock);
4340 static void mlx5e_tx_timeout(struct net_device *dev, unsigned int txqueue)
4342 struct mlx5e_priv *priv = netdev_priv(dev);
4344 netdev_err(dev, "TX timeout detected\n");
4345 queue_work(priv->wq, &priv->tx_timeout_work);
4348 static int mlx5e_xdp_allowed(struct mlx5e_priv *priv, struct bpf_prog *prog)
4350 struct net_device *netdev = priv->netdev;
4351 struct mlx5e_params new_params;
4353 if (priv->channels.params.lro_en) {
4354 netdev_warn(netdev, "can't set XDP while LRO is on, disable LRO first\n");
4358 if (mlx5_fpga_is_ipsec_device(priv->mdev)) {
4360 "XDP is not available on Innova cards with IPsec support\n");
4364 new_params = priv->channels.params;
4365 new_params.xdp_prog = prog;
4367 /* No XSK params: AF_XDP can't be enabled yet at the point of setting
4370 if (!mlx5e_rx_is_linear_skb(&new_params, NULL)) {
4371 netdev_warn(netdev, "XDP is not allowed with MTU(%d) > %d\n",
4373 mlx5e_xdp_max_mtu(&new_params, NULL));
4380 static void mlx5e_rq_replace_xdp_prog(struct mlx5e_rq *rq, struct bpf_prog *prog)
4382 struct bpf_prog *old_prog;
4384 old_prog = rcu_replace_pointer(rq->xdp_prog, prog,
4385 lockdep_is_held(&rq->priv->state_lock));
4387 bpf_prog_put(old_prog);
4390 static int mlx5e_xdp_set(struct net_device *netdev, struct bpf_prog *prog)
4392 struct mlx5e_priv *priv = netdev_priv(netdev);
4393 struct mlx5e_params new_params;
4394 struct bpf_prog *old_prog;
4399 mutex_lock(&priv->state_lock);
4402 err = mlx5e_xdp_allowed(priv, prog);
4407 /* no need for full reset when exchanging programs */
4408 reset = (!priv->channels.params.xdp_prog || !prog);
4410 new_params = priv->channels.params;
4411 new_params.xdp_prog = prog;
4413 mlx5e_set_rq_type(priv->mdev, &new_params);
4414 old_prog = priv->channels.params.xdp_prog;
4416 err = mlx5e_safe_switch_params(priv, &new_params, NULL, NULL, reset);
4421 bpf_prog_put(old_prog);
4423 if (!test_bit(MLX5E_STATE_OPENED, &priv->state) || reset)
4426 /* exchanging programs w/o reset, we update ref counts on behalf
4427 * of the channels RQs here.
4429 bpf_prog_add(prog, priv->channels.num);
4430 for (i = 0; i < priv->channels.num; i++) {
4431 struct mlx5e_channel *c = priv->channels.c[i];
4433 mlx5e_rq_replace_xdp_prog(&c->rq, prog);
4434 if (test_bit(MLX5E_CHANNEL_STATE_XSK, c->state)) {
4436 mlx5e_rq_replace_xdp_prog(&c->xskrq, prog);
4441 mutex_unlock(&priv->state_lock);
4445 static int mlx5e_xdp(struct net_device *dev, struct netdev_bpf *xdp)
4447 switch (xdp->command) {
4448 case XDP_SETUP_PROG:
4449 return mlx5e_xdp_set(dev, xdp->prog);
4450 case XDP_SETUP_XSK_POOL:
4451 return mlx5e_xsk_setup_pool(dev, xdp->xsk.pool,
4458 #ifdef CONFIG_MLX5_ESWITCH
4459 static int mlx5e_bridge_getlink(struct sk_buff *skb, u32 pid, u32 seq,
4460 struct net_device *dev, u32 filter_mask,
4463 struct mlx5e_priv *priv = netdev_priv(dev);
4464 struct mlx5_core_dev *mdev = priv->mdev;
4468 err = mlx5_eswitch_get_vepa(mdev->priv.eswitch, &setting);
4471 mode = setting ? BRIDGE_MODE_VEPA : BRIDGE_MODE_VEB;
4472 return ndo_dflt_bridge_getlink(skb, pid, seq, dev,
4474 0, 0, nlflags, filter_mask, NULL);
4477 static int mlx5e_bridge_setlink(struct net_device *dev, struct nlmsghdr *nlh,
4478 u16 flags, struct netlink_ext_ack *extack)
4480 struct mlx5e_priv *priv = netdev_priv(dev);
4481 struct mlx5_core_dev *mdev = priv->mdev;
4482 struct nlattr *attr, *br_spec;
4483 u16 mode = BRIDGE_MODE_UNDEF;
4487 br_spec = nlmsg_find_attr(nlh, sizeof(struct ifinfomsg), IFLA_AF_SPEC);
4491 nla_for_each_nested(attr, br_spec, rem) {
4492 if (nla_type(attr) != IFLA_BRIDGE_MODE)
4495 if (nla_len(attr) < sizeof(mode))
4498 mode = nla_get_u16(attr);
4499 if (mode > BRIDGE_MODE_VEPA)
4505 if (mode == BRIDGE_MODE_UNDEF)
4508 setting = (mode == BRIDGE_MODE_VEPA) ? 1 : 0;
4509 return mlx5_eswitch_set_vepa(mdev->priv.eswitch, setting);
4513 const struct net_device_ops mlx5e_netdev_ops = {
4514 .ndo_open = mlx5e_open,
4515 .ndo_stop = mlx5e_close,
4516 .ndo_start_xmit = mlx5e_xmit,
4517 .ndo_setup_tc = mlx5e_setup_tc,
4518 .ndo_select_queue = mlx5e_select_queue,
4519 .ndo_get_stats64 = mlx5e_get_stats,
4520 .ndo_set_rx_mode = mlx5e_set_rx_mode,
4521 .ndo_set_mac_address = mlx5e_set_mac,
4522 .ndo_vlan_rx_add_vid = mlx5e_vlan_rx_add_vid,
4523 .ndo_vlan_rx_kill_vid = mlx5e_vlan_rx_kill_vid,
4524 .ndo_set_features = mlx5e_set_features,
4525 .ndo_fix_features = mlx5e_fix_features,
4526 .ndo_change_mtu = mlx5e_change_nic_mtu,
4527 .ndo_do_ioctl = mlx5e_ioctl,
4528 .ndo_set_tx_maxrate = mlx5e_set_tx_maxrate,
4529 .ndo_features_check = mlx5e_features_check,
4530 .ndo_tx_timeout = mlx5e_tx_timeout,
4531 .ndo_bpf = mlx5e_xdp,
4532 .ndo_xdp_xmit = mlx5e_xdp_xmit,
4533 .ndo_xsk_wakeup = mlx5e_xsk_wakeup,
4534 #ifdef CONFIG_MLX5_EN_ARFS
4535 .ndo_rx_flow_steer = mlx5e_rx_flow_steer,
4537 #ifdef CONFIG_MLX5_ESWITCH
4538 .ndo_bridge_setlink = mlx5e_bridge_setlink,
4539 .ndo_bridge_getlink = mlx5e_bridge_getlink,
4541 /* SRIOV E-Switch NDOs */
4542 .ndo_set_vf_mac = mlx5e_set_vf_mac,
4543 .ndo_set_vf_vlan = mlx5e_set_vf_vlan,
4544 .ndo_set_vf_spoofchk = mlx5e_set_vf_spoofchk,
4545 .ndo_set_vf_trust = mlx5e_set_vf_trust,
4546 .ndo_set_vf_rate = mlx5e_set_vf_rate,
4547 .ndo_get_vf_config = mlx5e_get_vf_config,
4548 .ndo_set_vf_link_state = mlx5e_set_vf_link_state,
4549 .ndo_get_vf_stats = mlx5e_get_vf_stats,
4550 .ndo_has_offload_stats = mlx5e_has_offload_stats,
4551 .ndo_get_offload_stats = mlx5e_get_offload_stats,
4553 .ndo_get_devlink_port = mlx5e_get_devlink_port,
4556 void mlx5e_build_default_indir_rqt(u32 *indirection_rqt, int len,
4561 for (i = 0; i < len; i++)
4562 indirection_rqt[i] = i % num_channels;
4565 static u32 mlx5e_choose_lro_timeout(struct mlx5_core_dev *mdev, u32 wanted_timeout)
4569 /* The supported periods are organized in ascending order */
4570 for (i = 0; i < MLX5E_LRO_TIMEOUT_ARR_SIZE - 1; i++)
4571 if (MLX5_CAP_ETH(mdev, lro_timer_supported_periods[i]) >= wanted_timeout)
4574 return MLX5_CAP_ETH(mdev, lro_timer_supported_periods[i]);
4577 void mlx5e_build_rss_params(struct mlx5e_rss_params *rss_params,
4580 enum mlx5e_traffic_types tt;
4582 rss_params->hfunc = ETH_RSS_HASH_TOP;
4583 netdev_rss_key_fill(rss_params->toeplitz_hash_key,
4584 sizeof(rss_params->toeplitz_hash_key));
4585 mlx5e_build_default_indir_rqt(rss_params->indirection_rqt,
4586 MLX5E_INDIR_RQT_SIZE, num_channels);
4587 for (tt = 0; tt < MLX5E_NUM_INDIR_TIRS; tt++)
4588 rss_params->rx_hash_fields[tt] =
4589 tirc_default_config[tt].rx_hash_fields;
4592 void mlx5e_build_nic_params(struct mlx5e_priv *priv, struct mlx5e_xsk *xsk, u16 mtu)
4594 struct mlx5e_rss_params *rss_params = &priv->rss_params;
4595 struct mlx5e_params *params = &priv->channels.params;
4596 struct mlx5_core_dev *mdev = priv->mdev;
4597 u8 rx_cq_period_mode;
4599 priv->max_nch = mlx5e_calc_max_nch(priv, priv->profile);
4601 params->sw_mtu = mtu;
4602 params->hard_mtu = MLX5E_ETH_HARD_MTU;
4603 params->num_channels = min_t(unsigned int, MLX5E_MAX_NUM_CHANNELS / 2,
4607 /* Set an initial non-zero value, so that mlx5e_select_queue won't
4608 * divide by zero if called before first activating channels.
4610 priv->num_tc_x_num_ch = params->num_channels * params->num_tc;
4613 params->log_sq_size = is_kdump_kernel() ?
4614 MLX5E_PARAMS_MINIMUM_LOG_SQ_SIZE :
4615 MLX5E_PARAMS_DEFAULT_LOG_SQ_SIZE;
4616 MLX5E_SET_PFLAG(params, MLX5E_PFLAG_SKB_TX_MPWQE,
4617 MLX5_CAP_ETH(mdev, enhanced_multi_pkt_send_wqe));
4620 MLX5E_SET_PFLAG(params, MLX5E_PFLAG_XDP_TX_MPWQE,
4621 MLX5_CAP_ETH(mdev, enhanced_multi_pkt_send_wqe));
4623 /* set CQE compression */
4624 params->rx_cqe_compress_def = false;
4625 if (MLX5_CAP_GEN(mdev, cqe_compression) &&
4626 MLX5_CAP_GEN(mdev, vport_group_manager))
4627 params->rx_cqe_compress_def = slow_pci_heuristic(mdev);
4629 MLX5E_SET_PFLAG(params, MLX5E_PFLAG_RX_CQE_COMPRESS, params->rx_cqe_compress_def);
4630 MLX5E_SET_PFLAG(params, MLX5E_PFLAG_RX_NO_CSUM_COMPLETE, false);
4633 mlx5e_build_rq_params(mdev, params);
4636 if (MLX5_CAP_ETH(mdev, lro_cap) &&
4637 params->rq_wq_type == MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ) {
4638 /* No XSK params: checking the availability of striding RQ in general. */
4639 if (!mlx5e_rx_mpwqe_is_linear_skb(mdev, params, NULL))
4640 params->lro_en = !slow_pci_heuristic(mdev);
4642 params->lro_timeout = mlx5e_choose_lro_timeout(mdev, MLX5E_DEFAULT_LRO_TIMEOUT);
4644 /* CQ moderation params */
4645 rx_cq_period_mode = MLX5_CAP_GEN(mdev, cq_period_start_from_cqe) ?
4646 MLX5_CQ_PERIOD_MODE_START_FROM_CQE :
4647 MLX5_CQ_PERIOD_MODE_START_FROM_EQE;
4648 params->rx_dim_enabled = MLX5_CAP_GEN(mdev, cq_moderation);
4649 params->tx_dim_enabled = MLX5_CAP_GEN(mdev, cq_moderation);
4650 mlx5e_set_rx_cq_mode_params(params, rx_cq_period_mode);
4651 mlx5e_set_tx_cq_mode_params(params, MLX5_CQ_PERIOD_MODE_START_FROM_EQE);
4654 mlx5_query_min_inline(mdev, ¶ms->tx_min_inline_mode);
4657 mlx5e_build_rss_params(rss_params, params->num_channels);
4658 params->tunneled_offload_en =
4659 mlx5e_tunnel_inner_ft_supported(mdev);
4664 /* Do not update netdev->features directly in here
4665 * on mlx5e_attach_netdev() we will call mlx5e_update_features()
4666 * To update netdev->features please modify mlx5e_fix_features()
4670 static void mlx5e_set_netdev_dev_addr(struct net_device *netdev)
4672 struct mlx5e_priv *priv = netdev_priv(netdev);
4674 mlx5_query_mac_address(priv->mdev, netdev->dev_addr);
4675 if (is_zero_ether_addr(netdev->dev_addr) &&
4676 !MLX5_CAP_GEN(priv->mdev, vport_group_manager)) {
4677 eth_hw_addr_random(netdev);
4678 mlx5_core_info(priv->mdev, "Assigned random MAC address %pM\n", netdev->dev_addr);
4682 static int mlx5e_vxlan_set_port(struct net_device *netdev, unsigned int table,
4683 unsigned int entry, struct udp_tunnel_info *ti)
4685 struct mlx5e_priv *priv = netdev_priv(netdev);
4687 return mlx5_vxlan_add_port(priv->mdev->vxlan, ntohs(ti->port));
4690 static int mlx5e_vxlan_unset_port(struct net_device *netdev, unsigned int table,
4691 unsigned int entry, struct udp_tunnel_info *ti)
4693 struct mlx5e_priv *priv = netdev_priv(netdev);
4695 return mlx5_vxlan_del_port(priv->mdev->vxlan, ntohs(ti->port));
4698 void mlx5e_vxlan_set_netdev_info(struct mlx5e_priv *priv)
4700 if (!mlx5_vxlan_allowed(priv->mdev->vxlan))
4703 priv->nic_info.set_port = mlx5e_vxlan_set_port;
4704 priv->nic_info.unset_port = mlx5e_vxlan_unset_port;
4705 priv->nic_info.flags = UDP_TUNNEL_NIC_INFO_MAY_SLEEP |
4706 UDP_TUNNEL_NIC_INFO_STATIC_IANA_VXLAN;
4707 priv->nic_info.tables[0].tunnel_types = UDP_TUNNEL_TYPE_VXLAN;
4708 /* Don't count the space hard-coded to the IANA port */
4709 priv->nic_info.tables[0].n_entries =
4710 mlx5_vxlan_max_udp_ports(priv->mdev) - 1;
4712 priv->netdev->udp_tunnel_nic_info = &priv->nic_info;
4715 static bool mlx5e_tunnel_any_tx_proto_supported(struct mlx5_core_dev *mdev)
4719 for (tt = 0; tt < MLX5E_NUM_TUNNEL_TT; tt++) {
4720 if (mlx5e_tunnel_proto_supported_tx(mdev, mlx5e_get_proto_by_tunnel_type(tt)))
4723 return (mlx5_vxlan_allowed(mdev->vxlan) || mlx5_geneve_tx_allowed(mdev));
4726 static void mlx5e_build_nic_netdev(struct net_device *netdev)
4728 struct mlx5e_priv *priv = netdev_priv(netdev);
4729 struct mlx5_core_dev *mdev = priv->mdev;
4733 SET_NETDEV_DEV(netdev, mdev->device);
4735 netdev->netdev_ops = &mlx5e_netdev_ops;
4737 mlx5e_dcbnl_build_netdev(netdev);
4739 netdev->watchdog_timeo = 15 * HZ;
4741 netdev->ethtool_ops = &mlx5e_ethtool_ops;
4743 netdev->vlan_features |= NETIF_F_SG;
4744 netdev->vlan_features |= NETIF_F_HW_CSUM;
4745 netdev->vlan_features |= NETIF_F_GRO;
4746 netdev->vlan_features |= NETIF_F_TSO;
4747 netdev->vlan_features |= NETIF_F_TSO6;
4748 netdev->vlan_features |= NETIF_F_RXCSUM;
4749 netdev->vlan_features |= NETIF_F_RXHASH;
4751 netdev->mpls_features |= NETIF_F_SG;
4752 netdev->mpls_features |= NETIF_F_HW_CSUM;
4753 netdev->mpls_features |= NETIF_F_TSO;
4754 netdev->mpls_features |= NETIF_F_TSO6;
4756 netdev->hw_enc_features |= NETIF_F_HW_VLAN_CTAG_TX;
4757 netdev->hw_enc_features |= NETIF_F_HW_VLAN_CTAG_RX;
4759 if (!!MLX5_CAP_ETH(mdev, lro_cap) &&
4760 mlx5e_check_fragmented_striding_rq_cap(mdev))
4761 netdev->vlan_features |= NETIF_F_LRO;
4763 netdev->hw_features = netdev->vlan_features;
4764 netdev->hw_features |= NETIF_F_HW_VLAN_CTAG_TX;
4765 netdev->hw_features |= NETIF_F_HW_VLAN_CTAG_RX;
4766 netdev->hw_features |= NETIF_F_HW_VLAN_CTAG_FILTER;
4767 netdev->hw_features |= NETIF_F_HW_VLAN_STAG_TX;
4769 if (mlx5e_tunnel_any_tx_proto_supported(mdev)) {
4770 netdev->hw_enc_features |= NETIF_F_HW_CSUM;
4771 netdev->hw_enc_features |= NETIF_F_TSO;
4772 netdev->hw_enc_features |= NETIF_F_TSO6;
4773 netdev->hw_enc_features |= NETIF_F_GSO_PARTIAL;
4776 if (mlx5_vxlan_allowed(mdev->vxlan) || mlx5_geneve_tx_allowed(mdev)) {
4777 netdev->hw_features |= NETIF_F_GSO_UDP_TUNNEL |
4778 NETIF_F_GSO_UDP_TUNNEL_CSUM;
4779 netdev->hw_enc_features |= NETIF_F_GSO_UDP_TUNNEL |
4780 NETIF_F_GSO_UDP_TUNNEL_CSUM;
4781 netdev->gso_partial_features = NETIF_F_GSO_UDP_TUNNEL_CSUM;
4782 netdev->vlan_features |= NETIF_F_GSO_UDP_TUNNEL |
4783 NETIF_F_GSO_UDP_TUNNEL_CSUM;
4786 if (mlx5e_tunnel_proto_supported_tx(mdev, IPPROTO_GRE)) {
4787 netdev->hw_features |= NETIF_F_GSO_GRE |
4788 NETIF_F_GSO_GRE_CSUM;
4789 netdev->hw_enc_features |= NETIF_F_GSO_GRE |
4790 NETIF_F_GSO_GRE_CSUM;
4791 netdev->gso_partial_features |= NETIF_F_GSO_GRE |
4792 NETIF_F_GSO_GRE_CSUM;
4795 if (mlx5e_tunnel_proto_supported_tx(mdev, IPPROTO_IPIP)) {
4796 netdev->hw_features |= NETIF_F_GSO_IPXIP4 |
4798 netdev->hw_enc_features |= NETIF_F_GSO_IPXIP4 |
4800 netdev->gso_partial_features |= NETIF_F_GSO_IPXIP4 |
4804 netdev->hw_features |= NETIF_F_GSO_PARTIAL;
4805 netdev->gso_partial_features |= NETIF_F_GSO_UDP_L4;
4806 netdev->hw_features |= NETIF_F_GSO_UDP_L4;
4807 netdev->features |= NETIF_F_GSO_UDP_L4;
4809 mlx5_query_port_fcs(mdev, &fcs_supported, &fcs_enabled);
4812 netdev->hw_features |= NETIF_F_RXALL;
4814 if (MLX5_CAP_ETH(mdev, scatter_fcs))
4815 netdev->hw_features |= NETIF_F_RXFCS;
4817 netdev->features = netdev->hw_features;
4821 netdev->features &= ~NETIF_F_RXALL;
4822 netdev->features &= ~NETIF_F_LRO;
4823 netdev->features &= ~NETIF_F_RXFCS;
4825 #define FT_CAP(f) MLX5_CAP_FLOWTABLE(mdev, flow_table_properties_nic_receive.f)
4826 if (FT_CAP(flow_modify_en) &&
4827 FT_CAP(modify_root) &&
4828 FT_CAP(identified_miss_table_mode) &&
4829 FT_CAP(flow_table_modify)) {
4830 #if IS_ENABLED(CONFIG_MLX5_CLS_ACT)
4831 netdev->hw_features |= NETIF_F_HW_TC;
4833 #ifdef CONFIG_MLX5_EN_ARFS
4834 netdev->hw_features |= NETIF_F_NTUPLE;
4837 if (mlx5_qos_is_supported(mdev))
4838 netdev->features |= NETIF_F_HW_TC;
4840 netdev->features |= NETIF_F_HIGHDMA;
4841 netdev->features |= NETIF_F_HW_VLAN_STAG_FILTER;
4843 netdev->priv_flags |= IFF_UNICAST_FLT;
4845 mlx5e_set_netdev_dev_addr(netdev);
4846 mlx5e_ipsec_build_netdev(priv);
4847 mlx5e_tls_build_netdev(priv);
4850 void mlx5e_create_q_counters(struct mlx5e_priv *priv)
4852 u32 out[MLX5_ST_SZ_DW(alloc_q_counter_out)] = {};
4853 u32 in[MLX5_ST_SZ_DW(alloc_q_counter_in)] = {};
4854 struct mlx5_core_dev *mdev = priv->mdev;
4857 MLX5_SET(alloc_q_counter_in, in, opcode, MLX5_CMD_OP_ALLOC_Q_COUNTER);
4858 err = mlx5_cmd_exec_inout(mdev, alloc_q_counter, in, out);
4861 MLX5_GET(alloc_q_counter_out, out, counter_set_id);
4863 err = mlx5_cmd_exec_inout(mdev, alloc_q_counter, in, out);
4865 priv->drop_rq_q_counter =
4866 MLX5_GET(alloc_q_counter_out, out, counter_set_id);
4869 void mlx5e_destroy_q_counters(struct mlx5e_priv *priv)
4871 u32 in[MLX5_ST_SZ_DW(dealloc_q_counter_in)] = {};
4873 MLX5_SET(dealloc_q_counter_in, in, opcode,
4874 MLX5_CMD_OP_DEALLOC_Q_COUNTER);
4875 if (priv->q_counter) {
4876 MLX5_SET(dealloc_q_counter_in, in, counter_set_id,
4878 mlx5_cmd_exec_in(priv->mdev, dealloc_q_counter, in);
4881 if (priv->drop_rq_q_counter) {
4882 MLX5_SET(dealloc_q_counter_in, in, counter_set_id,
4883 priv->drop_rq_q_counter);
4884 mlx5_cmd_exec_in(priv->mdev, dealloc_q_counter, in);
4888 static int mlx5e_nic_init(struct mlx5_core_dev *mdev,
4889 struct net_device *netdev)
4891 struct mlx5e_priv *priv = netdev_priv(netdev);
4892 struct devlink_port *dl_port;
4895 mlx5e_build_nic_params(priv, &priv->xsk, netdev->mtu);
4896 mlx5e_vxlan_set_netdev_info(priv);
4898 mlx5e_timestamp_init(priv);
4900 err = mlx5e_ipsec_init(priv);
4902 mlx5_core_err(mdev, "IPSec initialization failed, %d\n", err);
4904 err = mlx5e_tls_init(priv);
4906 mlx5_core_err(mdev, "TLS initialization failed, %d\n", err);
4908 dl_port = mlx5e_devlink_get_dl_port(priv);
4909 if (dl_port->registered)
4910 mlx5e_health_create_reporters(priv);
4915 static void mlx5e_nic_cleanup(struct mlx5e_priv *priv)
4917 struct devlink_port *dl_port = mlx5e_devlink_get_dl_port(priv);
4919 if (dl_port->registered)
4920 mlx5e_health_destroy_reporters(priv);
4921 mlx5e_tls_cleanup(priv);
4922 mlx5e_ipsec_cleanup(priv);
4925 static int mlx5e_init_nic_rx(struct mlx5e_priv *priv)
4927 struct mlx5_core_dev *mdev = priv->mdev;
4928 u16 max_nch = priv->max_nch;
4931 mlx5e_create_q_counters(priv);
4933 err = mlx5e_open_drop_rq(priv, &priv->drop_rq);
4935 mlx5_core_err(mdev, "open drop rq failed, %d\n", err);
4936 goto err_destroy_q_counters;
4939 err = mlx5e_create_indirect_rqt(priv);
4941 goto err_close_drop_rq;
4943 err = mlx5e_create_direct_rqts(priv, priv->direct_tir, max_nch);
4945 goto err_destroy_indirect_rqts;
4947 err = mlx5e_create_indirect_tirs(priv, true);
4949 goto err_destroy_direct_rqts;
4951 err = mlx5e_create_direct_tirs(priv, priv->direct_tir, max_nch);
4953 goto err_destroy_indirect_tirs;
4955 err = mlx5e_create_direct_rqts(priv, priv->xsk_tir, max_nch);
4957 goto err_destroy_direct_tirs;
4959 err = mlx5e_create_direct_tirs(priv, priv->xsk_tir, max_nch);
4961 goto err_destroy_xsk_rqts;
4963 err = mlx5e_create_direct_rqts(priv, &priv->ptp_tir, 1);
4965 goto err_destroy_xsk_tirs;
4967 err = mlx5e_create_direct_tirs(priv, &priv->ptp_tir, 1);
4969 goto err_destroy_ptp_rqt;
4971 err = mlx5e_create_flow_steering(priv);
4973 mlx5_core_warn(mdev, "create flow steering failed, %d\n", err);
4974 goto err_destroy_ptp_direct_tir;
4977 err = mlx5e_tc_nic_init(priv);
4979 goto err_destroy_flow_steering;
4981 err = mlx5e_accel_init_rx(priv);
4983 goto err_tc_nic_cleanup;
4985 #ifdef CONFIG_MLX5_EN_ARFS
4986 priv->netdev->rx_cpu_rmap = mlx5_eq_table_get_rmap(priv->mdev);
4992 mlx5e_tc_nic_cleanup(priv);
4993 err_destroy_flow_steering:
4994 mlx5e_destroy_flow_steering(priv);
4995 err_destroy_ptp_direct_tir:
4996 mlx5e_destroy_direct_tirs(priv, &priv->ptp_tir, 1);
4997 err_destroy_ptp_rqt:
4998 mlx5e_destroy_direct_rqts(priv, &priv->ptp_tir, 1);
4999 err_destroy_xsk_tirs:
5000 mlx5e_destroy_direct_tirs(priv, priv->xsk_tir, max_nch);
5001 err_destroy_xsk_rqts:
5002 mlx5e_destroy_direct_rqts(priv, priv->xsk_tir, max_nch);
5003 err_destroy_direct_tirs:
5004 mlx5e_destroy_direct_tirs(priv, priv->direct_tir, max_nch);
5005 err_destroy_indirect_tirs:
5006 mlx5e_destroy_indirect_tirs(priv);
5007 err_destroy_direct_rqts:
5008 mlx5e_destroy_direct_rqts(priv, priv->direct_tir, max_nch);
5009 err_destroy_indirect_rqts:
5010 mlx5e_destroy_rqt(priv, &priv->indir_rqt);
5012 mlx5e_close_drop_rq(&priv->drop_rq);
5013 err_destroy_q_counters:
5014 mlx5e_destroy_q_counters(priv);
5018 static void mlx5e_cleanup_nic_rx(struct mlx5e_priv *priv)
5020 u16 max_nch = priv->max_nch;
5022 mlx5e_accel_cleanup_rx(priv);
5023 mlx5e_tc_nic_cleanup(priv);
5024 mlx5e_destroy_flow_steering(priv);
5025 mlx5e_destroy_direct_tirs(priv, &priv->ptp_tir, 1);
5026 mlx5e_destroy_direct_rqts(priv, &priv->ptp_tir, 1);
5027 mlx5e_destroy_direct_tirs(priv, priv->xsk_tir, max_nch);
5028 mlx5e_destroy_direct_rqts(priv, priv->xsk_tir, max_nch);
5029 mlx5e_destroy_direct_tirs(priv, priv->direct_tir, max_nch);
5030 mlx5e_destroy_indirect_tirs(priv);
5031 mlx5e_destroy_direct_rqts(priv, priv->direct_tir, max_nch);
5032 mlx5e_destroy_rqt(priv, &priv->indir_rqt);
5033 mlx5e_close_drop_rq(&priv->drop_rq);
5034 mlx5e_destroy_q_counters(priv);
5037 static int mlx5e_init_nic_tx(struct mlx5e_priv *priv)
5041 err = mlx5e_create_tises(priv);
5043 mlx5_core_warn(priv->mdev, "create tises failed, %d\n", err);
5047 mlx5e_dcbnl_initialize(priv);
5051 static void mlx5e_nic_enable(struct mlx5e_priv *priv)
5053 struct net_device *netdev = priv->netdev;
5054 struct mlx5_core_dev *mdev = priv->mdev;
5056 mlx5e_init_l2_addr(priv);
5058 /* Marking the link as currently not needed by the Driver */
5059 if (!netif_running(netdev))
5060 mlx5e_modify_admin_state(mdev, MLX5_PORT_DOWN);
5062 mlx5e_set_netdev_mtu_boundaries(priv);
5063 mlx5e_set_dev_port_mtu(priv);
5065 mlx5_lag_add(mdev, netdev);
5067 mlx5e_enable_async_events(priv);
5068 mlx5e_enable_blocking_events(priv);
5069 if (mlx5e_monitor_counter_supported(priv))
5070 mlx5e_monitor_counter_init(priv);
5072 mlx5e_hv_vhca_stats_create(priv);
5073 if (netdev->reg_state != NETREG_REGISTERED)
5075 mlx5e_dcbnl_init_app(priv);
5077 mlx5e_nic_set_rx_mode(priv);
5080 if (netif_running(netdev))
5082 udp_tunnel_nic_reset_ntf(priv->netdev);
5083 netif_device_attach(netdev);
5087 static void mlx5e_nic_disable(struct mlx5e_priv *priv)
5089 struct mlx5_core_dev *mdev = priv->mdev;
5091 if (priv->netdev->reg_state == NETREG_REGISTERED)
5092 mlx5e_dcbnl_delete_app(priv);
5095 if (netif_running(priv->netdev))
5096 mlx5e_close(priv->netdev);
5097 netif_device_detach(priv->netdev);
5100 mlx5e_nic_set_rx_mode(priv);
5102 mlx5e_hv_vhca_stats_destroy(priv);
5103 if (mlx5e_monitor_counter_supported(priv))
5104 mlx5e_monitor_counter_cleanup(priv);
5106 mlx5e_disable_blocking_events(priv);
5107 if (priv->en_trap) {
5108 mlx5e_deactivate_trap(priv);
5109 mlx5e_close_trap(priv->en_trap);
5110 priv->en_trap = NULL;
5112 mlx5e_disable_async_events(priv);
5113 mlx5_lag_remove(mdev);
5114 mlx5_vxlan_reset_to_default(mdev->vxlan);
5117 int mlx5e_update_nic_rx(struct mlx5e_priv *priv)
5119 return mlx5e_refresh_tirs(priv, false, false);
5122 static const struct mlx5e_profile mlx5e_nic_profile = {
5123 .init = mlx5e_nic_init,
5124 .cleanup = mlx5e_nic_cleanup,
5125 .init_rx = mlx5e_init_nic_rx,
5126 .cleanup_rx = mlx5e_cleanup_nic_rx,
5127 .init_tx = mlx5e_init_nic_tx,
5128 .cleanup_tx = mlx5e_cleanup_nic_tx,
5129 .enable = mlx5e_nic_enable,
5130 .disable = mlx5e_nic_disable,
5131 .update_rx = mlx5e_update_nic_rx,
5132 .update_stats = mlx5e_stats_update_ndo_stats,
5133 .update_carrier = mlx5e_update_carrier,
5134 .rx_handlers = &mlx5e_rx_handlers_nic,
5135 .max_tc = MLX5E_MAX_NUM_TC,
5136 .rq_groups = MLX5E_NUM_RQ_GROUPS(XSK),
5137 .stats_grps = mlx5e_nic_stats_grps,
5138 .stats_grps_num = mlx5e_nic_stats_grps_num,
5139 .rx_ptp_support = true,
5142 /* mlx5e generic netdev management API (move to en_common.c) */
5143 int mlx5e_priv_init(struct mlx5e_priv *priv,
5144 struct net_device *netdev,
5145 struct mlx5_core_dev *mdev)
5149 priv->netdev = netdev;
5150 priv->msglevel = MLX5E_MSG_LEVEL;
5151 priv->max_opened_tc = 1;
5153 if (!alloc_cpumask_var(&priv->scratchpad.cpumask, GFP_KERNEL))
5156 mutex_init(&priv->state_lock);
5157 hash_init(priv->htb.qos_tc2node);
5158 INIT_WORK(&priv->update_carrier_work, mlx5e_update_carrier_work);
5159 INIT_WORK(&priv->set_rx_mode_work, mlx5e_set_rx_mode_work);
5160 INIT_WORK(&priv->tx_timeout_work, mlx5e_tx_timeout_work);
5161 INIT_WORK(&priv->update_stats_work, mlx5e_update_stats_work);
5163 priv->wq = create_singlethread_workqueue("mlx5e");
5165 goto err_free_cpumask;
5170 free_cpumask_var(priv->scratchpad.cpumask);
5175 void mlx5e_priv_cleanup(struct mlx5e_priv *priv)
5179 /* bail if change profile failed and also rollback failed */
5183 destroy_workqueue(priv->wq);
5184 free_cpumask_var(priv->scratchpad.cpumask);
5186 for (i = 0; i < priv->htb.max_qos_sqs; i++)
5187 kfree(priv->htb.qos_sq_stats[i]);
5188 kvfree(priv->htb.qos_sq_stats);
5190 memset(priv, 0, sizeof(*priv));
5194 mlx5e_create_netdev(struct mlx5_core_dev *mdev, unsigned int txqs, unsigned int rxqs)
5196 struct net_device *netdev;
5199 netdev = alloc_etherdev_mqs(sizeof(struct mlx5e_priv), txqs, rxqs);
5201 mlx5_core_err(mdev, "alloc_etherdev_mqs() failed\n");
5205 err = mlx5e_priv_init(netdev_priv(netdev), netdev, mdev);
5207 mlx5_core_err(mdev, "mlx5e_priv_init failed, err=%d\n", err);
5208 goto err_free_netdev;
5211 netif_carrier_off(netdev);
5212 dev_net_set(netdev, mlx5_core_net(mdev));
5217 free_netdev(netdev);
5222 static void mlx5e_update_features(struct net_device *netdev)
5224 if (netdev->reg_state != NETREG_REGISTERED)
5225 return; /* features will be updated on netdev registration */
5228 netdev_update_features(netdev);
5232 int mlx5e_attach_netdev(struct mlx5e_priv *priv)
5234 const bool take_rtnl = priv->netdev->reg_state == NETREG_REGISTERED;
5235 const struct mlx5e_profile *profile = priv->profile;
5239 clear_bit(MLX5E_STATE_DESTROYING, &priv->state);
5241 /* max number of channels may have changed */
5242 max_nch = mlx5e_get_max_num_channels(priv->mdev);
5243 if (priv->channels.params.num_channels > max_nch) {
5244 mlx5_core_warn(priv->mdev, "MLX5E: Reducing number of channels to %d\n", max_nch);
5245 /* Reducing the number of channels - RXFH has to be reset, and
5246 * mlx5e_num_channels_changed below will build the RQT.
5248 priv->netdev->priv_flags &= ~IFF_RXFH_CONFIGURED;
5249 priv->channels.params.num_channels = max_nch;
5251 /* 1. Set the real number of queues in the kernel the first time.
5252 * 2. Set our default XPS cpumask.
5255 * rtnl_lock is required by netif_set_real_num_*_queues in case the
5256 * netdev has been registered by this point (if this function was called
5257 * in the reload or resume flow).
5261 err = mlx5e_num_channels_changed(priv);
5267 err = profile->init_tx(priv);
5271 err = profile->init_rx(priv);
5273 goto err_cleanup_tx;
5275 if (profile->enable)
5276 profile->enable(priv);
5278 mlx5e_update_features(priv->netdev);
5283 profile->cleanup_tx(priv);
5286 set_bit(MLX5E_STATE_DESTROYING, &priv->state);
5287 cancel_work_sync(&priv->update_stats_work);
5291 void mlx5e_detach_netdev(struct mlx5e_priv *priv)
5293 const struct mlx5e_profile *profile = priv->profile;
5295 set_bit(MLX5E_STATE_DESTROYING, &priv->state);
5297 if (profile->disable)
5298 profile->disable(priv);
5299 flush_workqueue(priv->wq);
5301 profile->cleanup_rx(priv);
5302 profile->cleanup_tx(priv);
5303 cancel_work_sync(&priv->update_stats_work);
5307 mlx5e_netdev_attach_profile(struct net_device *netdev, struct mlx5_core_dev *mdev,
5308 const struct mlx5e_profile *new_profile, void *new_ppriv)
5310 struct mlx5e_priv *priv = netdev_priv(netdev);
5313 err = mlx5e_priv_init(priv, netdev, mdev);
5315 mlx5_core_err(mdev, "mlx5e_priv_init failed, err=%d\n", err);
5318 netif_carrier_off(netdev);
5319 priv->profile = new_profile;
5320 priv->ppriv = new_ppriv;
5321 err = new_profile->init(priv->mdev, priv->netdev);
5324 err = mlx5e_attach_netdev(priv);
5326 goto profile_cleanup;
5330 new_profile->cleanup(priv);
5332 mlx5e_priv_cleanup(priv);
5336 int mlx5e_netdev_change_profile(struct mlx5e_priv *priv,
5337 const struct mlx5e_profile *new_profile, void *new_ppriv)
5339 unsigned int new_max_nch = mlx5e_calc_max_nch(priv, new_profile);
5340 const struct mlx5e_profile *orig_profile = priv->profile;
5341 struct net_device *netdev = priv->netdev;
5342 struct mlx5_core_dev *mdev = priv->mdev;
5343 void *orig_ppriv = priv->ppriv;
5344 int err, rollback_err;
5347 if (new_max_nch != priv->max_nch) {
5348 netdev_warn(netdev, "%s: Replacing profile with different max channels\n",
5353 /* cleanup old profile */
5354 mlx5e_detach_netdev(priv);
5355 priv->profile->cleanup(priv);
5356 mlx5e_priv_cleanup(priv);
5358 err = mlx5e_netdev_attach_profile(netdev, mdev, new_profile, new_ppriv);
5359 if (err) { /* roll back to original profile */
5360 netdev_warn(netdev, "%s: new profile init failed, %d\n", __func__, err);
5367 rollback_err = mlx5e_netdev_attach_profile(netdev, mdev, orig_profile, orig_ppriv);
5369 netdev_err(netdev, "%s: failed to rollback to orig profile, %d\n",
5370 __func__, rollback_err);
5374 void mlx5e_netdev_attach_nic_profile(struct mlx5e_priv *priv)
5376 mlx5e_netdev_change_profile(priv, &mlx5e_nic_profile, NULL);
5379 void mlx5e_destroy_netdev(struct mlx5e_priv *priv)
5381 struct net_device *netdev = priv->netdev;
5383 mlx5e_priv_cleanup(priv);
5384 free_netdev(netdev);
5387 static int mlx5e_resume(struct auxiliary_device *adev)
5389 struct mlx5_adev *edev = container_of(adev, struct mlx5_adev, adev);
5390 struct mlx5e_priv *priv = dev_get_drvdata(&adev->dev);
5391 struct net_device *netdev = priv->netdev;
5392 struct mlx5_core_dev *mdev = edev->mdev;
5395 if (netif_device_present(netdev))
5398 err = mlx5e_create_mdev_resources(mdev);
5402 err = mlx5e_attach_netdev(priv);
5404 mlx5e_destroy_mdev_resources(mdev);
5411 static int mlx5e_suspend(struct auxiliary_device *adev, pm_message_t state)
5413 struct mlx5e_priv *priv = dev_get_drvdata(&adev->dev);
5414 struct net_device *netdev = priv->netdev;
5415 struct mlx5_core_dev *mdev = priv->mdev;
5417 if (!netif_device_present(netdev))
5420 mlx5e_detach_netdev(priv);
5421 mlx5e_destroy_mdev_resources(mdev);
5425 static int mlx5e_probe(struct auxiliary_device *adev,
5426 const struct auxiliary_device_id *id)
5428 struct mlx5_adev *edev = container_of(adev, struct mlx5_adev, adev);
5429 const struct mlx5e_profile *profile = &mlx5e_nic_profile;
5430 struct mlx5_core_dev *mdev = edev->mdev;
5431 struct net_device *netdev;
5432 pm_message_t state = {};
5433 unsigned int txqs, rxqs, ptp_txqs = 0;
5434 struct mlx5e_priv *priv;
5439 if (MLX5_CAP_GEN(mdev, ts_cqe_to_dest_cqn))
5440 ptp_txqs = profile->max_tc;
5442 if (mlx5_qos_is_supported(mdev))
5443 qos_sqs = mlx5e_qos_max_leaf_nodes(mdev);
5445 nch = mlx5e_get_max_num_channels(mdev);
5446 txqs = nch * profile->max_tc + ptp_txqs + qos_sqs;
5447 rxqs = nch * profile->rq_groups;
5448 netdev = mlx5e_create_netdev(mdev, txqs, rxqs);
5450 mlx5_core_err(mdev, "mlx5e_create_netdev failed\n");
5454 mlx5e_build_nic_netdev(netdev);
5456 priv = netdev_priv(netdev);
5457 dev_set_drvdata(&adev->dev, priv);
5459 priv->profile = profile;
5462 err = mlx5e_devlink_port_register(priv);
5464 mlx5_core_err(mdev, "mlx5e_devlink_port_register failed, %d\n", err);
5465 goto err_destroy_netdev;
5468 err = profile->init(mdev, netdev);
5470 mlx5_core_err(mdev, "mlx5e_nic_profile init failed, %d\n", err);
5471 goto err_devlink_cleanup;
5474 err = mlx5e_resume(adev);
5476 mlx5_core_err(mdev, "mlx5e_resume failed, %d\n", err);
5477 goto err_profile_cleanup;
5480 err = register_netdev(netdev);
5482 mlx5_core_err(mdev, "register_netdev failed, %d\n", err);
5486 mlx5e_devlink_port_type_eth_set(priv);
5488 mlx5e_dcbnl_init_app(priv);
5489 mlx5_uplink_netdev_set(mdev, netdev);
5493 mlx5e_suspend(adev, state);
5494 err_profile_cleanup:
5495 profile->cleanup(priv);
5496 err_devlink_cleanup:
5497 mlx5e_devlink_port_unregister(priv);
5499 mlx5e_destroy_netdev(priv);
5503 static void mlx5e_remove(struct auxiliary_device *adev)
5505 struct mlx5e_priv *priv = dev_get_drvdata(&adev->dev);
5506 pm_message_t state = {};
5508 mlx5e_dcbnl_delete_app(priv);
5509 unregister_netdev(priv->netdev);
5510 mlx5e_suspend(adev, state);
5511 priv->profile->cleanup(priv);
5512 mlx5e_devlink_port_unregister(priv);
5513 mlx5e_destroy_netdev(priv);
5516 static const struct auxiliary_device_id mlx5e_id_table[] = {
5517 { .name = MLX5_ADEV_NAME ".eth", },
5521 MODULE_DEVICE_TABLE(auxiliary, mlx5e_id_table);
5523 static struct auxiliary_driver mlx5e_driver = {
5525 .probe = mlx5e_probe,
5526 .remove = mlx5e_remove,
5527 .suspend = mlx5e_suspend,
5528 .resume = mlx5e_resume,
5529 .id_table = mlx5e_id_table,
5532 int mlx5e_init(void)
5536 mlx5e_ipsec_build_inverse_table();
5537 mlx5e_build_ptys2ethtool_map();
5538 ret = auxiliary_driver_register(&mlx5e_driver);
5542 ret = mlx5e_rep_init();
5544 auxiliary_driver_unregister(&mlx5e_driver);
5548 void mlx5e_cleanup(void)
5550 mlx5e_rep_cleanup();
5551 auxiliary_driver_unregister(&mlx5e_driver);