2 * Copyright (c) 2015-2016, Mellanox Technologies. All rights reserved.
4 * This software is available to you under a choice of one of two
5 * licenses. You may choose to be licensed under the terms of the GNU
6 * General Public License (GPL) Version 2, available from the file
7 * COPYING in the main directory of this source tree, or the
8 * OpenIB.org BSD license below:
10 * Redistribution and use in source and binary forms, with or
11 * without modification, are permitted provided that the following
14 * - Redistributions of source code must retain the above
15 * copyright notice, this list of conditions and the following
18 * - Redistributions in binary form must reproduce the above
19 * copyright notice, this list of conditions and the following
20 * disclaimer in the documentation and/or other materials
21 * provided with the distribution.
23 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
24 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
25 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
26 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
27 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
28 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
29 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
33 #include <net/tc_act/tc_gact.h>
34 #include <net/pkt_cls.h>
35 #include <linux/mlx5/fs.h>
36 #include <net/vxlan.h>
37 #include <linux/bpf.h>
42 #include "en_accel/ipsec.h"
43 #include "en_accel/ipsec_rxtx.h"
44 #include "accel/ipsec.h"
47 struct mlx5e_rq_param {
48 u32 rqc[MLX5_ST_SZ_DW(rqc)];
49 struct mlx5_wq_param wq;
52 struct mlx5e_sq_param {
53 u32 sqc[MLX5_ST_SZ_DW(sqc)];
54 struct mlx5_wq_param wq;
57 struct mlx5e_cq_param {
58 u32 cqc[MLX5_ST_SZ_DW(cqc)];
59 struct mlx5_wq_param wq;
64 struct mlx5e_channel_param {
65 struct mlx5e_rq_param rq;
66 struct mlx5e_sq_param sq;
67 struct mlx5e_sq_param xdp_sq;
68 struct mlx5e_sq_param icosq;
69 struct mlx5e_cq_param rx_cq;
70 struct mlx5e_cq_param tx_cq;
71 struct mlx5e_cq_param icosq_cq;
74 static int mlx5e_get_node(struct mlx5e_priv *priv, int ix)
76 return pci_irq_get_node(priv->mdev->pdev, MLX5_EQ_VEC_COMP_BASE + ix);
79 static bool mlx5e_check_fragmented_striding_rq_cap(struct mlx5_core_dev *mdev)
81 return MLX5_CAP_GEN(mdev, striding_rq) &&
82 MLX5_CAP_GEN(mdev, umr_ptr_rlky) &&
83 MLX5_CAP_ETH(mdev, reg_umr_sq);
86 void mlx5e_set_rq_type_params(struct mlx5_core_dev *mdev,
87 struct mlx5e_params *params, u8 rq_type)
89 params->rq_wq_type = rq_type;
90 params->lro_wqe_sz = MLX5E_PARAMS_DEFAULT_LRO_WQE_SZ;
91 switch (params->rq_wq_type) {
92 case MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ:
93 params->log_rq_size = is_kdump_kernel() ?
94 MLX5E_PARAMS_MINIMUM_LOG_RQ_SIZE_MPW :
95 MLX5E_PARAMS_DEFAULT_LOG_RQ_SIZE_MPW;
96 params->mpwqe_log_stride_sz =
97 MLX5E_GET_PFLAG(params, MLX5E_PFLAG_RX_CQE_COMPRESS) ?
98 MLX5_MPWRQ_CQE_CMPRS_LOG_STRIDE_SZ(mdev) :
99 MLX5_MPWRQ_DEF_LOG_STRIDE_SZ(mdev);
100 params->mpwqe_log_num_strides = MLX5_MPWRQ_LOG_WQE_SZ -
101 params->mpwqe_log_stride_sz;
103 default: /* MLX5_WQ_TYPE_LINKED_LIST */
104 params->log_rq_size = is_kdump_kernel() ?
105 MLX5E_PARAMS_MINIMUM_LOG_RQ_SIZE :
106 MLX5E_PARAMS_DEFAULT_LOG_RQ_SIZE;
107 params->rq_headroom = params->xdp_prog ?
108 XDP_PACKET_HEADROOM : MLX5_RX_HEADROOM;
109 params->rq_headroom += NET_IP_ALIGN;
111 /* Extra room needed for build_skb */
112 params->lro_wqe_sz -= params->rq_headroom +
113 SKB_DATA_ALIGN(sizeof(struct skb_shared_info));
116 mlx5_core_info(mdev, "MLX5E: StrdRq(%d) RqSz(%ld) StrdSz(%ld) RxCqeCmprss(%d)\n",
117 params->rq_wq_type == MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ,
118 BIT(params->log_rq_size),
119 BIT(params->mpwqe_log_stride_sz),
120 MLX5E_GET_PFLAG(params, MLX5E_PFLAG_RX_CQE_COMPRESS));
123 static void mlx5e_set_rq_params(struct mlx5_core_dev *mdev, struct mlx5e_params *params)
125 u8 rq_type = mlx5e_check_fragmented_striding_rq_cap(mdev) &&
126 !params->xdp_prog && !MLX5_IPSEC_DEV(mdev) ?
127 MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ :
128 MLX5_WQ_TYPE_LINKED_LIST;
129 mlx5e_set_rq_type_params(mdev, params, rq_type);
132 static void mlx5e_update_carrier(struct mlx5e_priv *priv)
134 struct mlx5_core_dev *mdev = priv->mdev;
137 port_state = mlx5_query_vport_state(mdev,
138 MLX5_QUERY_VPORT_STATE_IN_OP_MOD_VNIC_VPORT,
141 if (port_state == VPORT_STATE_UP) {
142 netdev_info(priv->netdev, "Link up\n");
143 netif_carrier_on(priv->netdev);
145 netdev_info(priv->netdev, "Link down\n");
146 netif_carrier_off(priv->netdev);
150 static void mlx5e_update_carrier_work(struct work_struct *work)
152 struct mlx5e_priv *priv = container_of(work, struct mlx5e_priv,
153 update_carrier_work);
155 mutex_lock(&priv->state_lock);
156 if (test_bit(MLX5E_STATE_OPENED, &priv->state))
157 if (priv->profile->update_carrier)
158 priv->profile->update_carrier(priv);
159 mutex_unlock(&priv->state_lock);
162 static void mlx5e_tx_timeout_work(struct work_struct *work)
164 struct mlx5e_priv *priv = container_of(work, struct mlx5e_priv,
169 mutex_lock(&priv->state_lock);
170 if (!test_bit(MLX5E_STATE_OPENED, &priv->state))
172 mlx5e_close_locked(priv->netdev);
173 err = mlx5e_open_locked(priv->netdev);
175 netdev_err(priv->netdev, "mlx5e_open_locked failed recovering from a tx_timeout, err(%d).\n",
178 mutex_unlock(&priv->state_lock);
182 static void mlx5e_update_sw_counters(struct mlx5e_priv *priv)
184 struct mlx5e_sw_stats temp, *s = &temp;
185 struct mlx5e_rq_stats *rq_stats;
186 struct mlx5e_sq_stats *sq_stats;
189 memset(s, 0, sizeof(*s));
190 for (i = 0; i < priv->channels.num; i++) {
191 struct mlx5e_channel *c = priv->channels.c[i];
193 rq_stats = &c->rq.stats;
195 s->rx_packets += rq_stats->packets;
196 s->rx_bytes += rq_stats->bytes;
197 s->rx_lro_packets += rq_stats->lro_packets;
198 s->rx_lro_bytes += rq_stats->lro_bytes;
199 s->rx_csum_none += rq_stats->csum_none;
200 s->rx_csum_complete += rq_stats->csum_complete;
201 s->rx_csum_unnecessary += rq_stats->csum_unnecessary;
202 s->rx_csum_unnecessary_inner += rq_stats->csum_unnecessary_inner;
203 s->rx_xdp_drop += rq_stats->xdp_drop;
204 s->rx_xdp_tx += rq_stats->xdp_tx;
205 s->rx_xdp_tx_full += rq_stats->xdp_tx_full;
206 s->rx_wqe_err += rq_stats->wqe_err;
207 s->rx_mpwqe_filler += rq_stats->mpwqe_filler;
208 s->rx_buff_alloc_err += rq_stats->buff_alloc_err;
209 s->rx_cqe_compress_blks += rq_stats->cqe_compress_blks;
210 s->rx_cqe_compress_pkts += rq_stats->cqe_compress_pkts;
211 s->rx_page_reuse += rq_stats->page_reuse;
212 s->rx_cache_reuse += rq_stats->cache_reuse;
213 s->rx_cache_full += rq_stats->cache_full;
214 s->rx_cache_empty += rq_stats->cache_empty;
215 s->rx_cache_busy += rq_stats->cache_busy;
216 s->rx_cache_waive += rq_stats->cache_waive;
218 for (j = 0; j < priv->channels.params.num_tc; j++) {
219 sq_stats = &c->sq[j].stats;
221 s->tx_packets += sq_stats->packets;
222 s->tx_bytes += sq_stats->bytes;
223 s->tx_tso_packets += sq_stats->tso_packets;
224 s->tx_tso_bytes += sq_stats->tso_bytes;
225 s->tx_tso_inner_packets += sq_stats->tso_inner_packets;
226 s->tx_tso_inner_bytes += sq_stats->tso_inner_bytes;
227 s->tx_queue_stopped += sq_stats->stopped;
228 s->tx_queue_wake += sq_stats->wake;
229 s->tx_queue_dropped += sq_stats->dropped;
230 s->tx_xmit_more += sq_stats->xmit_more;
231 s->tx_csum_partial_inner += sq_stats->csum_partial_inner;
232 s->tx_csum_none += sq_stats->csum_none;
233 s->tx_csum_partial += sq_stats->csum_partial;
237 s->link_down_events_phy = MLX5_GET(ppcnt_reg,
238 priv->stats.pport.phy_counters,
239 counter_set.phys_layer_cntrs.link_down_events);
240 memcpy(&priv->stats.sw, s, sizeof(*s));
243 static void mlx5e_update_vport_counters(struct mlx5e_priv *priv)
245 int outlen = MLX5_ST_SZ_BYTES(query_vport_counter_out);
246 u32 *out = (u32 *)priv->stats.vport.query_vport_out;
247 u32 in[MLX5_ST_SZ_DW(query_vport_counter_in)] = {0};
248 struct mlx5_core_dev *mdev = priv->mdev;
250 MLX5_SET(query_vport_counter_in, in, opcode,
251 MLX5_CMD_OP_QUERY_VPORT_COUNTER);
252 MLX5_SET(query_vport_counter_in, in, op_mod, 0);
253 MLX5_SET(query_vport_counter_in, in, other_vport, 0);
255 mlx5_cmd_exec(mdev, in, sizeof(in), out, outlen);
258 static void mlx5e_update_pport_counters(struct mlx5e_priv *priv, bool full)
260 struct mlx5e_pport_stats *pstats = &priv->stats.pport;
261 struct mlx5_core_dev *mdev = priv->mdev;
262 u32 in[MLX5_ST_SZ_DW(ppcnt_reg)] = {0};
263 int sz = MLX5_ST_SZ_BYTES(ppcnt_reg);
267 MLX5_SET(ppcnt_reg, in, local_port, 1);
269 out = pstats->IEEE_802_3_counters;
270 MLX5_SET(ppcnt_reg, in, grp, MLX5_IEEE_802_3_COUNTERS_GROUP);
271 mlx5_core_access_reg(mdev, in, sz, out, sz, MLX5_REG_PPCNT, 0, 0);
276 out = pstats->RFC_2863_counters;
277 MLX5_SET(ppcnt_reg, in, grp, MLX5_RFC_2863_COUNTERS_GROUP);
278 mlx5_core_access_reg(mdev, in, sz, out, sz, MLX5_REG_PPCNT, 0, 0);
280 out = pstats->RFC_2819_counters;
281 MLX5_SET(ppcnt_reg, in, grp, MLX5_RFC_2819_COUNTERS_GROUP);
282 mlx5_core_access_reg(mdev, in, sz, out, sz, MLX5_REG_PPCNT, 0, 0);
284 out = pstats->phy_counters;
285 MLX5_SET(ppcnt_reg, in, grp, MLX5_PHYSICAL_LAYER_COUNTERS_GROUP);
286 mlx5_core_access_reg(mdev, in, sz, out, sz, MLX5_REG_PPCNT, 0, 0);
288 if (MLX5_CAP_PCAM_FEATURE(mdev, ppcnt_statistical_group)) {
289 out = pstats->phy_statistical_counters;
290 MLX5_SET(ppcnt_reg, in, grp, MLX5_PHYSICAL_LAYER_STATISTICAL_GROUP);
291 mlx5_core_access_reg(mdev, in, sz, out, sz, MLX5_REG_PPCNT, 0, 0);
294 if (MLX5_CAP_PCAM_FEATURE(mdev, rx_buffer_fullness_counters)) {
295 out = pstats->eth_ext_counters;
296 MLX5_SET(ppcnt_reg, in, grp, MLX5_ETHERNET_EXTENDED_COUNTERS_GROUP);
297 mlx5_core_access_reg(mdev, in, sz, out, sz, MLX5_REG_PPCNT, 0, 0);
300 MLX5_SET(ppcnt_reg, in, grp, MLX5_PER_PRIORITY_COUNTERS_GROUP);
301 for (prio = 0; prio < NUM_PPORT_PRIO; prio++) {
302 out = pstats->per_prio_counters[prio];
303 MLX5_SET(ppcnt_reg, in, prio_tc, prio);
304 mlx5_core_access_reg(mdev, in, sz, out, sz,
305 MLX5_REG_PPCNT, 0, 0);
309 static void mlx5e_update_q_counter(struct mlx5e_priv *priv)
311 struct mlx5e_qcounter_stats *qcnt = &priv->stats.qcnt;
312 u32 out[MLX5_ST_SZ_DW(query_q_counter_out)];
315 if (!priv->q_counter)
318 err = mlx5_core_query_q_counter(priv->mdev, priv->q_counter, 0, out, sizeof(out));
322 qcnt->rx_out_of_buffer = MLX5_GET(query_q_counter_out, out, out_of_buffer);
325 static void mlx5e_update_pcie_counters(struct mlx5e_priv *priv)
327 struct mlx5e_pcie_stats *pcie_stats = &priv->stats.pcie;
328 struct mlx5_core_dev *mdev = priv->mdev;
329 u32 in[MLX5_ST_SZ_DW(mpcnt_reg)] = {0};
330 int sz = MLX5_ST_SZ_BYTES(mpcnt_reg);
333 if (!MLX5_CAP_MCAM_FEATURE(mdev, pcie_performance_group))
336 out = pcie_stats->pcie_perf_counters;
337 MLX5_SET(mpcnt_reg, in, grp, MLX5_PCIE_PERFORMANCE_COUNTERS_GROUP);
338 mlx5_core_access_reg(mdev, in, sz, out, sz, MLX5_REG_MPCNT, 0, 0);
341 void mlx5e_update_stats(struct mlx5e_priv *priv, bool full)
344 mlx5e_update_pcie_counters(priv);
345 mlx5e_ipsec_update_stats(priv);
347 mlx5e_update_pport_counters(priv, full);
348 mlx5e_update_vport_counters(priv);
349 mlx5e_update_q_counter(priv);
350 mlx5e_update_sw_counters(priv);
353 static void mlx5e_update_ndo_stats(struct mlx5e_priv *priv)
355 mlx5e_update_stats(priv, false);
358 void mlx5e_update_stats_work(struct work_struct *work)
360 struct delayed_work *dwork = to_delayed_work(work);
361 struct mlx5e_priv *priv = container_of(dwork, struct mlx5e_priv,
363 mutex_lock(&priv->state_lock);
364 if (test_bit(MLX5E_STATE_OPENED, &priv->state)) {
365 priv->profile->update_stats(priv);
366 queue_delayed_work(priv->wq, dwork,
367 msecs_to_jiffies(MLX5E_UPDATE_STATS_INTERVAL));
369 mutex_unlock(&priv->state_lock);
372 static void mlx5e_async_event(struct mlx5_core_dev *mdev, void *vpriv,
373 enum mlx5_dev_event event, unsigned long param)
375 struct mlx5e_priv *priv = vpriv;
376 struct ptp_clock_event ptp_event;
377 struct mlx5_eqe *eqe = NULL;
379 if (!test_bit(MLX5E_STATE_ASYNC_EVENTS_ENABLED, &priv->state))
383 case MLX5_DEV_EVENT_PORT_UP:
384 case MLX5_DEV_EVENT_PORT_DOWN:
385 queue_work(priv->wq, &priv->update_carrier_work);
387 case MLX5_DEV_EVENT_PPS:
388 eqe = (struct mlx5_eqe *)param;
389 ptp_event.index = eqe->data.pps.pin;
390 ptp_event.timestamp =
391 timecounter_cyc2time(&priv->tstamp.clock,
392 be64_to_cpu(eqe->data.pps.time_stamp));
393 mlx5e_pps_event_handler(vpriv, &ptp_event);
400 static void mlx5e_enable_async_events(struct mlx5e_priv *priv)
402 set_bit(MLX5E_STATE_ASYNC_EVENTS_ENABLED, &priv->state);
405 static void mlx5e_disable_async_events(struct mlx5e_priv *priv)
407 clear_bit(MLX5E_STATE_ASYNC_EVENTS_ENABLED, &priv->state);
408 synchronize_irq(pci_irq_vector(priv->mdev->pdev, MLX5_EQ_VEC_ASYNC));
411 static inline int mlx5e_get_wqe_mtt_sz(void)
413 /* UMR copies MTTs in units of MLX5_UMR_MTT_ALIGNMENT bytes.
414 * To avoid copying garbage after the mtt array, we allocate
417 return ALIGN(MLX5_MPWRQ_PAGES_PER_WQE * sizeof(__be64),
418 MLX5_UMR_MTT_ALIGNMENT);
421 static inline void mlx5e_build_umr_wqe(struct mlx5e_rq *rq,
422 struct mlx5e_icosq *sq,
423 struct mlx5e_umr_wqe *wqe,
426 struct mlx5_wqe_ctrl_seg *cseg = &wqe->ctrl;
427 struct mlx5_wqe_umr_ctrl_seg *ucseg = &wqe->uctrl;
428 struct mlx5_wqe_data_seg *dseg = &wqe->data;
429 struct mlx5e_mpw_info *wi = &rq->mpwqe.info[ix];
430 u8 ds_cnt = DIV_ROUND_UP(sizeof(*wqe), MLX5_SEND_WQE_DS);
431 u32 umr_wqe_mtt_offset = mlx5e_get_wqe_mtt_offset(rq, ix);
433 cseg->qpn_ds = cpu_to_be32((sq->sqn << MLX5_WQE_CTRL_QPN_SHIFT) |
435 cseg->fm_ce_se = MLX5_WQE_CTRL_CQ_UPDATE;
436 cseg->imm = rq->mkey_be;
438 ucseg->flags = MLX5_UMR_TRANSLATION_OFFSET_EN;
439 ucseg->xlt_octowords =
440 cpu_to_be16(MLX5_MTT_OCTW(MLX5_MPWRQ_PAGES_PER_WQE));
441 ucseg->bsf_octowords =
442 cpu_to_be16(MLX5_MTT_OCTW(umr_wqe_mtt_offset));
443 ucseg->mkey_mask = cpu_to_be64(MLX5_MKEY_MASK_FREE);
445 dseg->lkey = sq->mkey_be;
446 dseg->addr = cpu_to_be64(wi->umr.mtt_addr);
449 static int mlx5e_rq_alloc_mpwqe_info(struct mlx5e_rq *rq,
450 struct mlx5e_channel *c)
452 int wq_sz = mlx5_wq_ll_get_size(&rq->wq);
453 int mtt_sz = mlx5e_get_wqe_mtt_sz();
454 int mtt_alloc = mtt_sz + MLX5_UMR_ALIGN - 1;
455 int node = mlx5e_get_node(c->priv, c->ix);
458 rq->mpwqe.info = kzalloc_node(wq_sz * sizeof(*rq->mpwqe.info),
463 /* We allocate more than mtt_sz as we will align the pointer */
464 rq->mpwqe.mtt_no_align = kzalloc_node(mtt_alloc * wq_sz,
466 if (unlikely(!rq->mpwqe.mtt_no_align))
467 goto err_free_wqe_info;
469 for (i = 0; i < wq_sz; i++) {
470 struct mlx5e_mpw_info *wi = &rq->mpwqe.info[i];
472 wi->umr.mtt = PTR_ALIGN(rq->mpwqe.mtt_no_align + i * mtt_alloc,
474 wi->umr.mtt_addr = dma_map_single(c->pdev, wi->umr.mtt, mtt_sz,
476 if (unlikely(dma_mapping_error(c->pdev, wi->umr.mtt_addr)))
479 mlx5e_build_umr_wqe(rq, &c->icosq, &wi->umr.wqe, i);
486 struct mlx5e_mpw_info *wi = &rq->mpwqe.info[i];
488 dma_unmap_single(c->pdev, wi->umr.mtt_addr, mtt_sz,
491 kfree(rq->mpwqe.mtt_no_align);
493 kfree(rq->mpwqe.info);
499 static void mlx5e_rq_free_mpwqe_info(struct mlx5e_rq *rq)
501 int wq_sz = mlx5_wq_ll_get_size(&rq->wq);
502 int mtt_sz = mlx5e_get_wqe_mtt_sz();
505 for (i = 0; i < wq_sz; i++) {
506 struct mlx5e_mpw_info *wi = &rq->mpwqe.info[i];
508 dma_unmap_single(rq->pdev, wi->umr.mtt_addr, mtt_sz,
511 kfree(rq->mpwqe.mtt_no_align);
512 kfree(rq->mpwqe.info);
515 static int mlx5e_create_umr_mkey(struct mlx5_core_dev *mdev,
516 u64 npages, u8 page_shift,
517 struct mlx5_core_mkey *umr_mkey)
519 int inlen = MLX5_ST_SZ_BYTES(create_mkey_in);
524 if (!MLX5E_VALID_NUM_MTTS(npages))
527 in = kvzalloc(inlen, GFP_KERNEL);
531 mkc = MLX5_ADDR_OF(create_mkey_in, in, memory_key_mkey_entry);
533 MLX5_SET(mkc, mkc, free, 1);
534 MLX5_SET(mkc, mkc, umr_en, 1);
535 MLX5_SET(mkc, mkc, lw, 1);
536 MLX5_SET(mkc, mkc, lr, 1);
537 MLX5_SET(mkc, mkc, access_mode, MLX5_MKC_ACCESS_MODE_MTT);
539 MLX5_SET(mkc, mkc, qpn, 0xffffff);
540 MLX5_SET(mkc, mkc, pd, mdev->mlx5e_res.pdn);
541 MLX5_SET64(mkc, mkc, len, npages << page_shift);
542 MLX5_SET(mkc, mkc, translations_octword_size,
543 MLX5_MTT_OCTW(npages));
544 MLX5_SET(mkc, mkc, log_page_size, page_shift);
546 err = mlx5_core_create_mkey(mdev, umr_mkey, in, inlen);
552 static int mlx5e_create_rq_umr_mkey(struct mlx5_core_dev *mdev, struct mlx5e_rq *rq)
554 u64 num_mtts = MLX5E_REQUIRED_MTTS(mlx5_wq_ll_get_size(&rq->wq));
556 return mlx5e_create_umr_mkey(mdev, num_mtts, PAGE_SHIFT, &rq->umr_mkey);
559 static int mlx5e_alloc_rq(struct mlx5e_channel *c,
560 struct mlx5e_params *params,
561 struct mlx5e_rq_param *rqp,
564 struct mlx5_core_dev *mdev = c->mdev;
565 void *rqc = rqp->rqc;
566 void *rqc_wq = MLX5_ADDR_OF(rqc, rqc, wq);
573 rqp->wq.db_numa_node = mlx5e_get_node(c->priv, c->ix);
575 err = mlx5_wq_ll_create(mdev, &rqp->wq, rqc_wq, &rq->wq,
580 rq->wq.db = &rq->wq.db[MLX5_RCV_DBR];
582 wq_sz = mlx5_wq_ll_get_size(&rq->wq);
584 rq->wq_type = params->rq_wq_type;
586 rq->netdev = c->netdev;
587 rq->tstamp = c->tstamp;
592 rq->xdp_prog = params->xdp_prog ? bpf_prog_inc(params->xdp_prog) : NULL;
593 if (IS_ERR(rq->xdp_prog)) {
594 err = PTR_ERR(rq->xdp_prog);
596 goto err_rq_wq_destroy;
599 rq->buff.map_dir = rq->xdp_prog ? DMA_BIDIRECTIONAL : DMA_FROM_DEVICE;
600 rq->buff.headroom = params->rq_headroom;
602 switch (rq->wq_type) {
603 case MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ:
605 rq->post_wqes = mlx5e_post_rx_mpwqes;
606 rq->dealloc_wqe = mlx5e_dealloc_rx_mpwqe;
608 rq->handle_rx_cqe = c->priv->profile->rx_handlers.handle_rx_cqe_mpwqe;
609 #ifdef CONFIG_MLX5_EN_IPSEC
610 if (MLX5_IPSEC_DEV(mdev)) {
612 netdev_err(c->netdev, "MPWQE RQ with IPSec offload not supported\n");
613 goto err_rq_wq_destroy;
616 if (!rq->handle_rx_cqe) {
618 netdev_err(c->netdev, "RX handler of MPWQE RQ is not set, err %d\n", err);
619 goto err_rq_wq_destroy;
622 rq->mpwqe.log_stride_sz = params->mpwqe_log_stride_sz;
623 rq->mpwqe.num_strides = BIT(params->mpwqe_log_num_strides);
625 byte_count = rq->mpwqe.num_strides << rq->mpwqe.log_stride_sz;
627 err = mlx5e_create_rq_umr_mkey(mdev, rq);
629 goto err_rq_wq_destroy;
630 rq->mkey_be = cpu_to_be32(rq->umr_mkey.key);
632 err = mlx5e_rq_alloc_mpwqe_info(rq, c);
634 goto err_destroy_umr_mkey;
636 default: /* MLX5_WQ_TYPE_LINKED_LIST */
638 kzalloc_node(wq_sz * sizeof(*rq->wqe.frag_info),
640 mlx5e_get_node(c->priv, c->ix));
641 if (!rq->wqe.frag_info) {
643 goto err_rq_wq_destroy;
645 rq->post_wqes = mlx5e_post_rx_wqes;
646 rq->dealloc_wqe = mlx5e_dealloc_rx_wqe;
648 #ifdef CONFIG_MLX5_EN_IPSEC
650 rq->handle_rx_cqe = mlx5e_ipsec_handle_rx_cqe;
653 rq->handle_rx_cqe = c->priv->profile->rx_handlers.handle_rx_cqe;
654 if (!rq->handle_rx_cqe) {
655 kfree(rq->wqe.frag_info);
657 netdev_err(c->netdev, "RX handler of RQ is not set, err %d\n", err);
658 goto err_rq_wq_destroy;
661 byte_count = params->lro_en ?
663 MLX5E_SW2HW_MTU(c->priv, c->netdev->mtu);
664 #ifdef CONFIG_MLX5_EN_IPSEC
665 if (MLX5_IPSEC_DEV(mdev))
666 byte_count += MLX5E_METADATA_ETHER_LEN;
668 rq->wqe.page_reuse = !params->xdp_prog && !params->lro_en;
670 /* calc the required page order */
671 rq->wqe.frag_sz = MLX5_SKB_FRAG_SZ(rq->buff.headroom + byte_count);
672 npages = DIV_ROUND_UP(rq->wqe.frag_sz, PAGE_SIZE);
673 rq->buff.page_order = order_base_2(npages);
675 byte_count |= MLX5_HW_START_PADDING;
676 rq->mkey_be = c->mkey_be;
679 for (i = 0; i < wq_sz; i++) {
680 struct mlx5e_rx_wqe *wqe = mlx5_wq_ll_get_wqe(&rq->wq, i);
682 if (rq->wq_type == MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ) {
683 u64 dma_offset = (u64)mlx5e_get_wqe_mtt_offset(rq, i) << PAGE_SHIFT;
685 wqe->data.addr = cpu_to_be64(dma_offset);
688 wqe->data.byte_count = cpu_to_be32(byte_count);
689 wqe->data.lkey = rq->mkey_be;
692 INIT_WORK(&rq->am.work, mlx5e_rx_am_work);
693 rq->am.mode = params->rx_cq_period_mode;
694 rq->page_cache.head = 0;
695 rq->page_cache.tail = 0;
699 err_destroy_umr_mkey:
700 mlx5_core_destroy_mkey(mdev, &rq->umr_mkey);
704 bpf_prog_put(rq->xdp_prog);
705 mlx5_wq_destroy(&rq->wq_ctrl);
710 static void mlx5e_free_rq(struct mlx5e_rq *rq)
715 bpf_prog_put(rq->xdp_prog);
717 switch (rq->wq_type) {
718 case MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ:
719 mlx5e_rq_free_mpwqe_info(rq);
720 mlx5_core_destroy_mkey(rq->mdev, &rq->umr_mkey);
722 default: /* MLX5_WQ_TYPE_LINKED_LIST */
723 kfree(rq->wqe.frag_info);
726 for (i = rq->page_cache.head; i != rq->page_cache.tail;
727 i = (i + 1) & (MLX5E_CACHE_SIZE - 1)) {
728 struct mlx5e_dma_info *dma_info = &rq->page_cache.page_cache[i];
730 mlx5e_page_release(rq, dma_info, false);
732 mlx5_wq_destroy(&rq->wq_ctrl);
735 static int mlx5e_create_rq(struct mlx5e_rq *rq,
736 struct mlx5e_rq_param *param)
738 struct mlx5_core_dev *mdev = rq->mdev;
746 inlen = MLX5_ST_SZ_BYTES(create_rq_in) +
747 sizeof(u64) * rq->wq_ctrl.buf.npages;
748 in = kvzalloc(inlen, GFP_KERNEL);
752 rqc = MLX5_ADDR_OF(create_rq_in, in, ctx);
753 wq = MLX5_ADDR_OF(rqc, rqc, wq);
755 memcpy(rqc, param->rqc, sizeof(param->rqc));
757 MLX5_SET(rqc, rqc, cqn, rq->cq.mcq.cqn);
758 MLX5_SET(rqc, rqc, state, MLX5_RQC_STATE_RST);
759 MLX5_SET(wq, wq, log_wq_pg_sz, rq->wq_ctrl.buf.page_shift -
760 MLX5_ADAPTER_PAGE_SHIFT);
761 MLX5_SET64(wq, wq, dbr_addr, rq->wq_ctrl.db.dma);
763 mlx5_fill_page_array(&rq->wq_ctrl.buf,
764 (__be64 *)MLX5_ADDR_OF(wq, wq, pas));
766 err = mlx5_core_create_rq(mdev, in, inlen, &rq->rqn);
773 static int mlx5e_modify_rq_state(struct mlx5e_rq *rq, int curr_state,
776 struct mlx5e_channel *c = rq->channel;
777 struct mlx5_core_dev *mdev = c->mdev;
784 inlen = MLX5_ST_SZ_BYTES(modify_rq_in);
785 in = kvzalloc(inlen, GFP_KERNEL);
789 rqc = MLX5_ADDR_OF(modify_rq_in, in, ctx);
791 MLX5_SET(modify_rq_in, in, rq_state, curr_state);
792 MLX5_SET(rqc, rqc, state, next_state);
794 err = mlx5_core_modify_rq(mdev, rq->rqn, in, inlen);
801 static int mlx5e_modify_rq_scatter_fcs(struct mlx5e_rq *rq, bool enable)
803 struct mlx5e_channel *c = rq->channel;
804 struct mlx5e_priv *priv = c->priv;
805 struct mlx5_core_dev *mdev = priv->mdev;
812 inlen = MLX5_ST_SZ_BYTES(modify_rq_in);
813 in = kvzalloc(inlen, GFP_KERNEL);
817 rqc = MLX5_ADDR_OF(modify_rq_in, in, ctx);
819 MLX5_SET(modify_rq_in, in, rq_state, MLX5_RQC_STATE_RDY);
820 MLX5_SET64(modify_rq_in, in, modify_bitmask,
821 MLX5_MODIFY_RQ_IN_MODIFY_BITMASK_SCATTER_FCS);
822 MLX5_SET(rqc, rqc, scatter_fcs, enable);
823 MLX5_SET(rqc, rqc, state, MLX5_RQC_STATE_RDY);
825 err = mlx5_core_modify_rq(mdev, rq->rqn, in, inlen);
832 static int mlx5e_modify_rq_vsd(struct mlx5e_rq *rq, bool vsd)
834 struct mlx5e_channel *c = rq->channel;
835 struct mlx5_core_dev *mdev = c->mdev;
841 inlen = MLX5_ST_SZ_BYTES(modify_rq_in);
842 in = kvzalloc(inlen, GFP_KERNEL);
846 rqc = MLX5_ADDR_OF(modify_rq_in, in, ctx);
848 MLX5_SET(modify_rq_in, in, rq_state, MLX5_RQC_STATE_RDY);
849 MLX5_SET64(modify_rq_in, in, modify_bitmask,
850 MLX5_MODIFY_RQ_IN_MODIFY_BITMASK_VSD);
851 MLX5_SET(rqc, rqc, vsd, vsd);
852 MLX5_SET(rqc, rqc, state, MLX5_RQC_STATE_RDY);
854 err = mlx5_core_modify_rq(mdev, rq->rqn, in, inlen);
861 static void mlx5e_destroy_rq(struct mlx5e_rq *rq)
863 mlx5_core_destroy_rq(rq->mdev, rq->rqn);
866 static int mlx5e_wait_for_min_rx_wqes(struct mlx5e_rq *rq)
868 unsigned long exp_time = jiffies + msecs_to_jiffies(20000);
869 struct mlx5e_channel *c = rq->channel;
871 struct mlx5_wq_ll *wq = &rq->wq;
872 u16 min_wqes = mlx5_min_rx_wqes(rq->wq_type, mlx5_wq_ll_get_size(wq));
874 while (time_before(jiffies, exp_time)) {
875 if (wq->cur_sz >= min_wqes)
881 netdev_warn(c->netdev, "Failed to get min RX wqes on RQN[0x%x] wq cur_sz(%d) min_rx_wqes(%d)\n",
882 rq->rqn, wq->cur_sz, min_wqes);
886 static void mlx5e_free_rx_descs(struct mlx5e_rq *rq)
888 struct mlx5_wq_ll *wq = &rq->wq;
889 struct mlx5e_rx_wqe *wqe;
893 /* UMR WQE (if in progress) is always at wq->head */
894 if (rq->wq_type == MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ &&
895 rq->mpwqe.umr_in_progress)
896 mlx5e_free_rx_mpwqe(rq, &rq->mpwqe.info[wq->head]);
898 while (!mlx5_wq_ll_is_empty(wq)) {
899 wqe_ix_be = *wq->tail_next;
900 wqe_ix = be16_to_cpu(wqe_ix_be);
901 wqe = mlx5_wq_ll_get_wqe(&rq->wq, wqe_ix);
902 rq->dealloc_wqe(rq, wqe_ix);
903 mlx5_wq_ll_pop(&rq->wq, wqe_ix_be,
904 &wqe->next.next_wqe_index);
907 if (rq->wq_type == MLX5_WQ_TYPE_LINKED_LIST && rq->wqe.page_reuse) {
908 /* Clean outstanding pages on handled WQEs that decided to do page-reuse,
909 * but yet to be re-posted.
911 int wq_sz = mlx5_wq_ll_get_size(&rq->wq);
913 for (wqe_ix = 0; wqe_ix < wq_sz; wqe_ix++)
914 rq->dealloc_wqe(rq, wqe_ix);
918 static int mlx5e_open_rq(struct mlx5e_channel *c,
919 struct mlx5e_params *params,
920 struct mlx5e_rq_param *param,
925 err = mlx5e_alloc_rq(c, params, param, rq);
929 err = mlx5e_create_rq(rq, param);
933 err = mlx5e_modify_rq_state(rq, MLX5_RQC_STATE_RST, MLX5_RQC_STATE_RDY);
937 if (params->rx_am_enabled)
938 c->rq.state |= BIT(MLX5E_RQ_STATE_AM);
943 mlx5e_destroy_rq(rq);
950 static void mlx5e_activate_rq(struct mlx5e_rq *rq)
952 struct mlx5e_icosq *sq = &rq->channel->icosq;
953 u16 pi = sq->pc & sq->wq.sz_m1;
954 struct mlx5e_tx_wqe *nopwqe;
956 set_bit(MLX5E_RQ_STATE_ENABLED, &rq->state);
957 sq->db.ico_wqe[pi].opcode = MLX5_OPCODE_NOP;
958 nopwqe = mlx5e_post_nop(&sq->wq, sq->sqn, &sq->pc);
959 mlx5e_notify_hw(&sq->wq, sq->pc, sq->uar_map, &nopwqe->ctrl);
962 static void mlx5e_deactivate_rq(struct mlx5e_rq *rq)
964 clear_bit(MLX5E_RQ_STATE_ENABLED, &rq->state);
965 napi_synchronize(&rq->channel->napi); /* prevent mlx5e_post_rx_wqes */
968 static void mlx5e_close_rq(struct mlx5e_rq *rq)
970 cancel_work_sync(&rq->am.work);
971 mlx5e_destroy_rq(rq);
972 mlx5e_free_rx_descs(rq);
976 static void mlx5e_free_xdpsq_db(struct mlx5e_xdpsq *sq)
981 static int mlx5e_alloc_xdpsq_db(struct mlx5e_xdpsq *sq, int numa)
983 int wq_sz = mlx5_wq_cyc_get_size(&sq->wq);
985 sq->db.di = kzalloc_node(sizeof(*sq->db.di) * wq_sz,
988 mlx5e_free_xdpsq_db(sq);
995 static int mlx5e_alloc_xdpsq(struct mlx5e_channel *c,
996 struct mlx5e_params *params,
997 struct mlx5e_sq_param *param,
998 struct mlx5e_xdpsq *sq)
1000 void *sqc_wq = MLX5_ADDR_OF(sqc, param->sqc, wq);
1001 struct mlx5_core_dev *mdev = c->mdev;
1005 sq->mkey_be = c->mkey_be;
1007 sq->uar_map = mdev->mlx5e_res.bfreg.map;
1008 sq->min_inline_mode = params->tx_min_inline_mode;
1010 param->wq.db_numa_node = mlx5e_get_node(c->priv, c->ix);
1011 err = mlx5_wq_cyc_create(mdev, ¶m->wq, sqc_wq, &sq->wq, &sq->wq_ctrl);
1014 sq->wq.db = &sq->wq.db[MLX5_SND_DBR];
1016 err = mlx5e_alloc_xdpsq_db(sq, mlx5e_get_node(c->priv, c->ix));
1018 goto err_sq_wq_destroy;
1023 mlx5_wq_destroy(&sq->wq_ctrl);
1028 static void mlx5e_free_xdpsq(struct mlx5e_xdpsq *sq)
1030 mlx5e_free_xdpsq_db(sq);
1031 mlx5_wq_destroy(&sq->wq_ctrl);
1034 static void mlx5e_free_icosq_db(struct mlx5e_icosq *sq)
1036 kfree(sq->db.ico_wqe);
1039 static int mlx5e_alloc_icosq_db(struct mlx5e_icosq *sq, int numa)
1041 u8 wq_sz = mlx5_wq_cyc_get_size(&sq->wq);
1043 sq->db.ico_wqe = kzalloc_node(sizeof(*sq->db.ico_wqe) * wq_sz,
1045 if (!sq->db.ico_wqe)
1051 static int mlx5e_alloc_icosq(struct mlx5e_channel *c,
1052 struct mlx5e_sq_param *param,
1053 struct mlx5e_icosq *sq)
1055 void *sqc_wq = MLX5_ADDR_OF(sqc, param->sqc, wq);
1056 struct mlx5_core_dev *mdev = c->mdev;
1059 sq->mkey_be = c->mkey_be;
1061 sq->uar_map = mdev->mlx5e_res.bfreg.map;
1063 param->wq.db_numa_node = mlx5e_get_node(c->priv, c->ix);
1064 err = mlx5_wq_cyc_create(mdev, ¶m->wq, sqc_wq, &sq->wq, &sq->wq_ctrl);
1067 sq->wq.db = &sq->wq.db[MLX5_SND_DBR];
1069 err = mlx5e_alloc_icosq_db(sq, mlx5e_get_node(c->priv, c->ix));
1071 goto err_sq_wq_destroy;
1073 sq->edge = (sq->wq.sz_m1 + 1) - MLX5E_ICOSQ_MAX_WQEBBS;
1078 mlx5_wq_destroy(&sq->wq_ctrl);
1083 static void mlx5e_free_icosq(struct mlx5e_icosq *sq)
1085 mlx5e_free_icosq_db(sq);
1086 mlx5_wq_destroy(&sq->wq_ctrl);
1089 static void mlx5e_free_txqsq_db(struct mlx5e_txqsq *sq)
1091 kfree(sq->db.wqe_info);
1092 kfree(sq->db.dma_fifo);
1095 static int mlx5e_alloc_txqsq_db(struct mlx5e_txqsq *sq, int numa)
1097 int wq_sz = mlx5_wq_cyc_get_size(&sq->wq);
1098 int df_sz = wq_sz * MLX5_SEND_WQEBB_NUM_DS;
1100 sq->db.dma_fifo = kzalloc_node(df_sz * sizeof(*sq->db.dma_fifo),
1102 sq->db.wqe_info = kzalloc_node(wq_sz * sizeof(*sq->db.wqe_info),
1104 if (!sq->db.dma_fifo || !sq->db.wqe_info) {
1105 mlx5e_free_txqsq_db(sq);
1109 sq->dma_fifo_mask = df_sz - 1;
1114 static int mlx5e_alloc_txqsq(struct mlx5e_channel *c,
1116 struct mlx5e_params *params,
1117 struct mlx5e_sq_param *param,
1118 struct mlx5e_txqsq *sq)
1120 void *sqc_wq = MLX5_ADDR_OF(sqc, param->sqc, wq);
1121 struct mlx5_core_dev *mdev = c->mdev;
1125 sq->tstamp = c->tstamp;
1126 sq->mkey_be = c->mkey_be;
1128 sq->txq_ix = txq_ix;
1129 sq->uar_map = mdev->mlx5e_res.bfreg.map;
1130 sq->max_inline = params->tx_max_inline;
1131 sq->min_inline_mode = params->tx_min_inline_mode;
1132 if (MLX5_IPSEC_DEV(c->priv->mdev))
1133 set_bit(MLX5E_SQ_STATE_IPSEC, &sq->state);
1135 param->wq.db_numa_node = mlx5e_get_node(c->priv, c->ix);
1136 err = mlx5_wq_cyc_create(mdev, ¶m->wq, sqc_wq, &sq->wq, &sq->wq_ctrl);
1139 sq->wq.db = &sq->wq.db[MLX5_SND_DBR];
1141 err = mlx5e_alloc_txqsq_db(sq, mlx5e_get_node(c->priv, c->ix));
1143 goto err_sq_wq_destroy;
1145 sq->edge = (sq->wq.sz_m1 + 1) - MLX5_SEND_WQE_MAX_WQEBBS;
1150 mlx5_wq_destroy(&sq->wq_ctrl);
1155 static void mlx5e_free_txqsq(struct mlx5e_txqsq *sq)
1157 mlx5e_free_txqsq_db(sq);
1158 mlx5_wq_destroy(&sq->wq_ctrl);
1161 struct mlx5e_create_sq_param {
1162 struct mlx5_wq_ctrl *wq_ctrl;
1169 static int mlx5e_create_sq(struct mlx5_core_dev *mdev,
1170 struct mlx5e_sq_param *param,
1171 struct mlx5e_create_sq_param *csp,
1180 inlen = MLX5_ST_SZ_BYTES(create_sq_in) +
1181 sizeof(u64) * csp->wq_ctrl->buf.npages;
1182 in = kvzalloc(inlen, GFP_KERNEL);
1186 sqc = MLX5_ADDR_OF(create_sq_in, in, ctx);
1187 wq = MLX5_ADDR_OF(sqc, sqc, wq);
1189 memcpy(sqc, param->sqc, sizeof(param->sqc));
1190 MLX5_SET(sqc, sqc, tis_lst_sz, csp->tis_lst_sz);
1191 MLX5_SET(sqc, sqc, tis_num_0, csp->tisn);
1192 MLX5_SET(sqc, sqc, cqn, csp->cqn);
1194 if (MLX5_CAP_ETH(mdev, wqe_inline_mode) == MLX5_CAP_INLINE_MODE_VPORT_CONTEXT)
1195 MLX5_SET(sqc, sqc, min_wqe_inline_mode, csp->min_inline_mode);
1197 MLX5_SET(sqc, sqc, state, MLX5_SQC_STATE_RST);
1199 MLX5_SET(wq, wq, wq_type, MLX5_WQ_TYPE_CYCLIC);
1200 MLX5_SET(wq, wq, uar_page, mdev->mlx5e_res.bfreg.index);
1201 MLX5_SET(wq, wq, log_wq_pg_sz, csp->wq_ctrl->buf.page_shift -
1202 MLX5_ADAPTER_PAGE_SHIFT);
1203 MLX5_SET64(wq, wq, dbr_addr, csp->wq_ctrl->db.dma);
1205 mlx5_fill_page_array(&csp->wq_ctrl->buf, (__be64 *)MLX5_ADDR_OF(wq, wq, pas));
1207 err = mlx5_core_create_sq(mdev, in, inlen, sqn);
1214 struct mlx5e_modify_sq_param {
1221 static int mlx5e_modify_sq(struct mlx5_core_dev *mdev, u32 sqn,
1222 struct mlx5e_modify_sq_param *p)
1229 inlen = MLX5_ST_SZ_BYTES(modify_sq_in);
1230 in = kvzalloc(inlen, GFP_KERNEL);
1234 sqc = MLX5_ADDR_OF(modify_sq_in, in, ctx);
1236 MLX5_SET(modify_sq_in, in, sq_state, p->curr_state);
1237 MLX5_SET(sqc, sqc, state, p->next_state);
1238 if (p->rl_update && p->next_state == MLX5_SQC_STATE_RDY) {
1239 MLX5_SET64(modify_sq_in, in, modify_bitmask, 1);
1240 MLX5_SET(sqc, sqc, packet_pacing_rate_limit_index, p->rl_index);
1243 err = mlx5_core_modify_sq(mdev, sqn, in, inlen);
1250 static void mlx5e_destroy_sq(struct mlx5_core_dev *mdev, u32 sqn)
1252 mlx5_core_destroy_sq(mdev, sqn);
1255 static int mlx5e_create_sq_rdy(struct mlx5_core_dev *mdev,
1256 struct mlx5e_sq_param *param,
1257 struct mlx5e_create_sq_param *csp,
1260 struct mlx5e_modify_sq_param msp = {0};
1263 err = mlx5e_create_sq(mdev, param, csp, sqn);
1267 msp.curr_state = MLX5_SQC_STATE_RST;
1268 msp.next_state = MLX5_SQC_STATE_RDY;
1269 err = mlx5e_modify_sq(mdev, *sqn, &msp);
1271 mlx5e_destroy_sq(mdev, *sqn);
1276 static int mlx5e_set_sq_maxrate(struct net_device *dev,
1277 struct mlx5e_txqsq *sq, u32 rate);
1279 static int mlx5e_open_txqsq(struct mlx5e_channel *c,
1282 struct mlx5e_params *params,
1283 struct mlx5e_sq_param *param,
1284 struct mlx5e_txqsq *sq)
1286 struct mlx5e_create_sq_param csp = {};
1290 err = mlx5e_alloc_txqsq(c, txq_ix, params, param, sq);
1296 csp.cqn = sq->cq.mcq.cqn;
1297 csp.wq_ctrl = &sq->wq_ctrl;
1298 csp.min_inline_mode = sq->min_inline_mode;
1299 err = mlx5e_create_sq_rdy(c->mdev, param, &csp, &sq->sqn);
1301 goto err_free_txqsq;
1303 tx_rate = c->priv->tx_rates[sq->txq_ix];
1305 mlx5e_set_sq_maxrate(c->netdev, sq, tx_rate);
1310 clear_bit(MLX5E_SQ_STATE_ENABLED, &sq->state);
1311 mlx5e_free_txqsq(sq);
1316 static void mlx5e_activate_txqsq(struct mlx5e_txqsq *sq)
1318 sq->txq = netdev_get_tx_queue(sq->channel->netdev, sq->txq_ix);
1319 set_bit(MLX5E_SQ_STATE_ENABLED, &sq->state);
1320 netdev_tx_reset_queue(sq->txq);
1321 netif_tx_start_queue(sq->txq);
1324 static inline void netif_tx_disable_queue(struct netdev_queue *txq)
1326 __netif_tx_lock_bh(txq);
1327 netif_tx_stop_queue(txq);
1328 __netif_tx_unlock_bh(txq);
1331 static void mlx5e_deactivate_txqsq(struct mlx5e_txqsq *sq)
1333 struct mlx5e_channel *c = sq->channel;
1335 clear_bit(MLX5E_SQ_STATE_ENABLED, &sq->state);
1336 /* prevent netif_tx_wake_queue */
1337 napi_synchronize(&c->napi);
1339 netif_tx_disable_queue(sq->txq);
1341 /* last doorbell out, godspeed .. */
1342 if (mlx5e_wqc_has_room_for(&sq->wq, sq->cc, sq->pc, 1)) {
1343 struct mlx5e_tx_wqe *nop;
1345 sq->db.wqe_info[(sq->pc & sq->wq.sz_m1)].skb = NULL;
1346 nop = mlx5e_post_nop(&sq->wq, sq->sqn, &sq->pc);
1347 mlx5e_notify_hw(&sq->wq, sq->pc, sq->uar_map, &nop->ctrl);
1351 static void mlx5e_close_txqsq(struct mlx5e_txqsq *sq)
1353 struct mlx5e_channel *c = sq->channel;
1354 struct mlx5_core_dev *mdev = c->mdev;
1356 mlx5e_destroy_sq(mdev, sq->sqn);
1358 mlx5_rl_remove_rate(mdev, sq->rate_limit);
1359 mlx5e_free_txqsq_descs(sq);
1360 mlx5e_free_txqsq(sq);
1363 static int mlx5e_open_icosq(struct mlx5e_channel *c,
1364 struct mlx5e_params *params,
1365 struct mlx5e_sq_param *param,
1366 struct mlx5e_icosq *sq)
1368 struct mlx5e_create_sq_param csp = {};
1371 err = mlx5e_alloc_icosq(c, param, sq);
1375 csp.cqn = sq->cq.mcq.cqn;
1376 csp.wq_ctrl = &sq->wq_ctrl;
1377 csp.min_inline_mode = params->tx_min_inline_mode;
1378 set_bit(MLX5E_SQ_STATE_ENABLED, &sq->state);
1379 err = mlx5e_create_sq_rdy(c->mdev, param, &csp, &sq->sqn);
1381 goto err_free_icosq;
1386 clear_bit(MLX5E_SQ_STATE_ENABLED, &sq->state);
1387 mlx5e_free_icosq(sq);
1392 static void mlx5e_close_icosq(struct mlx5e_icosq *sq)
1394 struct mlx5e_channel *c = sq->channel;
1396 clear_bit(MLX5E_SQ_STATE_ENABLED, &sq->state);
1397 napi_synchronize(&c->napi);
1399 mlx5e_destroy_sq(c->mdev, sq->sqn);
1400 mlx5e_free_icosq(sq);
1403 static int mlx5e_open_xdpsq(struct mlx5e_channel *c,
1404 struct mlx5e_params *params,
1405 struct mlx5e_sq_param *param,
1406 struct mlx5e_xdpsq *sq)
1408 unsigned int ds_cnt = MLX5E_XDP_TX_DS_COUNT;
1409 struct mlx5e_create_sq_param csp = {};
1410 unsigned int inline_hdr_sz = 0;
1414 err = mlx5e_alloc_xdpsq(c, params, param, sq);
1419 csp.tisn = c->priv->tisn[0]; /* tc = 0 */
1420 csp.cqn = sq->cq.mcq.cqn;
1421 csp.wq_ctrl = &sq->wq_ctrl;
1422 csp.min_inline_mode = sq->min_inline_mode;
1423 set_bit(MLX5E_SQ_STATE_ENABLED, &sq->state);
1424 err = mlx5e_create_sq_rdy(c->mdev, param, &csp, &sq->sqn);
1426 goto err_free_xdpsq;
1428 if (sq->min_inline_mode != MLX5_INLINE_MODE_NONE) {
1429 inline_hdr_sz = MLX5E_XDP_MIN_INLINE;
1433 /* Pre initialize fixed WQE fields */
1434 for (i = 0; i < mlx5_wq_cyc_get_size(&sq->wq); i++) {
1435 struct mlx5e_tx_wqe *wqe = mlx5_wq_cyc_get_wqe(&sq->wq, i);
1436 struct mlx5_wqe_ctrl_seg *cseg = &wqe->ctrl;
1437 struct mlx5_wqe_eth_seg *eseg = &wqe->eth;
1438 struct mlx5_wqe_data_seg *dseg;
1440 cseg->qpn_ds = cpu_to_be32((sq->sqn << 8) | ds_cnt);
1441 eseg->inline_hdr.sz = cpu_to_be16(inline_hdr_sz);
1443 dseg = (struct mlx5_wqe_data_seg *)cseg + (ds_cnt - 1);
1444 dseg->lkey = sq->mkey_be;
1450 clear_bit(MLX5E_SQ_STATE_ENABLED, &sq->state);
1451 mlx5e_free_xdpsq(sq);
1456 static void mlx5e_close_xdpsq(struct mlx5e_xdpsq *sq)
1458 struct mlx5e_channel *c = sq->channel;
1460 clear_bit(MLX5E_SQ_STATE_ENABLED, &sq->state);
1461 napi_synchronize(&c->napi);
1463 mlx5e_destroy_sq(c->mdev, sq->sqn);
1464 mlx5e_free_xdpsq_descs(sq);
1465 mlx5e_free_xdpsq(sq);
1468 static int mlx5e_alloc_cq_common(struct mlx5_core_dev *mdev,
1469 struct mlx5e_cq_param *param,
1470 struct mlx5e_cq *cq)
1472 struct mlx5_core_cq *mcq = &cq->mcq;
1478 err = mlx5_cqwq_create(mdev, ¶m->wq, param->cqc, &cq->wq,
1483 mlx5_vector2eqn(mdev, param->eq_ix, &eqn_not_used, &irqn);
1486 mcq->set_ci_db = cq->wq_ctrl.db.db;
1487 mcq->arm_db = cq->wq_ctrl.db.db + 1;
1488 *mcq->set_ci_db = 0;
1490 mcq->vector = param->eq_ix;
1491 mcq->comp = mlx5e_completion_event;
1492 mcq->event = mlx5e_cq_error_event;
1495 for (i = 0; i < mlx5_cqwq_get_size(&cq->wq); i++) {
1496 struct mlx5_cqe64 *cqe = mlx5_cqwq_get_wqe(&cq->wq, i);
1506 static int mlx5e_alloc_cq(struct mlx5e_channel *c,
1507 struct mlx5e_cq_param *param,
1508 struct mlx5e_cq *cq)
1510 struct mlx5_core_dev *mdev = c->priv->mdev;
1513 param->wq.buf_numa_node = mlx5e_get_node(c->priv, c->ix);
1514 param->wq.db_numa_node = mlx5e_get_node(c->priv, c->ix);
1515 param->eq_ix = c->ix;
1517 err = mlx5e_alloc_cq_common(mdev, param, cq);
1519 cq->napi = &c->napi;
1525 static void mlx5e_free_cq(struct mlx5e_cq *cq)
1527 mlx5_cqwq_destroy(&cq->wq_ctrl);
1530 static int mlx5e_create_cq(struct mlx5e_cq *cq, struct mlx5e_cq_param *param)
1532 struct mlx5_core_dev *mdev = cq->mdev;
1533 struct mlx5_core_cq *mcq = &cq->mcq;
1538 unsigned int irqn_not_used;
1542 inlen = MLX5_ST_SZ_BYTES(create_cq_in) +
1543 sizeof(u64) * cq->wq_ctrl.frag_buf.npages;
1544 in = kvzalloc(inlen, GFP_KERNEL);
1548 cqc = MLX5_ADDR_OF(create_cq_in, in, cq_context);
1550 memcpy(cqc, param->cqc, sizeof(param->cqc));
1552 mlx5_fill_page_frag_array(&cq->wq_ctrl.frag_buf,
1553 (__be64 *)MLX5_ADDR_OF(create_cq_in, in, pas));
1555 mlx5_vector2eqn(mdev, param->eq_ix, &eqn, &irqn_not_used);
1557 MLX5_SET(cqc, cqc, cq_period_mode, param->cq_period_mode);
1558 MLX5_SET(cqc, cqc, c_eqn, eqn);
1559 MLX5_SET(cqc, cqc, uar_page, mdev->priv.uar->index);
1560 MLX5_SET(cqc, cqc, log_page_size, cq->wq_ctrl.frag_buf.page_shift -
1561 MLX5_ADAPTER_PAGE_SHIFT);
1562 MLX5_SET64(cqc, cqc, dbr_addr, cq->wq_ctrl.db.dma);
1564 err = mlx5_core_create_cq(mdev, mcq, in, inlen);
1576 static void mlx5e_destroy_cq(struct mlx5e_cq *cq)
1578 mlx5_core_destroy_cq(cq->mdev, &cq->mcq);
1581 static int mlx5e_open_cq(struct mlx5e_channel *c,
1582 struct mlx5e_cq_moder moder,
1583 struct mlx5e_cq_param *param,
1584 struct mlx5e_cq *cq)
1586 struct mlx5_core_dev *mdev = c->mdev;
1589 err = mlx5e_alloc_cq(c, param, cq);
1593 err = mlx5e_create_cq(cq, param);
1597 if (MLX5_CAP_GEN(mdev, cq_moderation))
1598 mlx5_core_modify_cq_moderation(mdev, &cq->mcq, moder.usec, moder.pkts);
1607 static void mlx5e_close_cq(struct mlx5e_cq *cq)
1609 mlx5e_destroy_cq(cq);
1613 static int mlx5e_open_tx_cqs(struct mlx5e_channel *c,
1614 struct mlx5e_params *params,
1615 struct mlx5e_channel_param *cparam)
1620 for (tc = 0; tc < c->num_tc; tc++) {
1621 err = mlx5e_open_cq(c, params->tx_cq_moderation,
1622 &cparam->tx_cq, &c->sq[tc].cq);
1624 goto err_close_tx_cqs;
1630 for (tc--; tc >= 0; tc--)
1631 mlx5e_close_cq(&c->sq[tc].cq);
1636 static void mlx5e_close_tx_cqs(struct mlx5e_channel *c)
1640 for (tc = 0; tc < c->num_tc; tc++)
1641 mlx5e_close_cq(&c->sq[tc].cq);
1644 static int mlx5e_open_sqs(struct mlx5e_channel *c,
1645 struct mlx5e_params *params,
1646 struct mlx5e_channel_param *cparam)
1651 for (tc = 0; tc < params->num_tc; tc++) {
1652 int txq_ix = c->ix + tc * params->num_channels;
1654 err = mlx5e_open_txqsq(c, c->priv->tisn[tc], txq_ix,
1655 params, &cparam->sq, &c->sq[tc]);
1663 for (tc--; tc >= 0; tc--)
1664 mlx5e_close_txqsq(&c->sq[tc]);
1669 static void mlx5e_close_sqs(struct mlx5e_channel *c)
1673 for (tc = 0; tc < c->num_tc; tc++)
1674 mlx5e_close_txqsq(&c->sq[tc]);
1677 static int mlx5e_set_sq_maxrate(struct net_device *dev,
1678 struct mlx5e_txqsq *sq, u32 rate)
1680 struct mlx5e_priv *priv = netdev_priv(dev);
1681 struct mlx5_core_dev *mdev = priv->mdev;
1682 struct mlx5e_modify_sq_param msp = {0};
1686 if (rate == sq->rate_limit)
1691 /* remove current rl index to free space to next ones */
1692 mlx5_rl_remove_rate(mdev, sq->rate_limit);
1697 err = mlx5_rl_add_rate(mdev, rate, &rl_index);
1699 netdev_err(dev, "Failed configuring rate %u: %d\n",
1705 msp.curr_state = MLX5_SQC_STATE_RDY;
1706 msp.next_state = MLX5_SQC_STATE_RDY;
1707 msp.rl_index = rl_index;
1708 msp.rl_update = true;
1709 err = mlx5e_modify_sq(mdev, sq->sqn, &msp);
1711 netdev_err(dev, "Failed configuring rate %u: %d\n",
1713 /* remove the rate from the table */
1715 mlx5_rl_remove_rate(mdev, rate);
1719 sq->rate_limit = rate;
1723 static int mlx5e_set_tx_maxrate(struct net_device *dev, int index, u32 rate)
1725 struct mlx5e_priv *priv = netdev_priv(dev);
1726 struct mlx5_core_dev *mdev = priv->mdev;
1727 struct mlx5e_txqsq *sq = priv->txq2sq[index];
1730 if (!mlx5_rl_is_supported(mdev)) {
1731 netdev_err(dev, "Rate limiting is not supported on this device\n");
1735 /* rate is given in Mb/sec, HW config is in Kb/sec */
1738 /* Check whether rate in valid range, 0 is always valid */
1739 if (rate && !mlx5_rl_is_in_range(mdev, rate)) {
1740 netdev_err(dev, "TX rate %u, is not in range\n", rate);
1744 mutex_lock(&priv->state_lock);
1745 if (test_bit(MLX5E_STATE_OPENED, &priv->state))
1746 err = mlx5e_set_sq_maxrate(dev, sq, rate);
1748 priv->tx_rates[index] = rate;
1749 mutex_unlock(&priv->state_lock);
1754 static int mlx5e_open_channel(struct mlx5e_priv *priv, int ix,
1755 struct mlx5e_params *params,
1756 struct mlx5e_channel_param *cparam,
1757 struct mlx5e_channel **cp)
1759 struct mlx5e_cq_moder icocq_moder = {0, 0};
1760 struct net_device *netdev = priv->netdev;
1761 struct mlx5e_channel *c;
1766 c = kzalloc_node(sizeof(*c), GFP_KERNEL, mlx5e_get_node(priv, ix));
1771 c->mdev = priv->mdev;
1772 c->tstamp = &priv->tstamp;
1774 c->pdev = &priv->mdev->pdev->dev;
1775 c->netdev = priv->netdev;
1776 c->mkey_be = cpu_to_be32(priv->mdev->mlx5e_res.mkey.key);
1777 c->num_tc = params->num_tc;
1778 c->xdp = !!params->xdp_prog;
1780 mlx5_vector2eqn(priv->mdev, ix, &eqn, &irq);
1781 c->irq_desc = irq_to_desc(irq);
1783 netif_napi_add(netdev, &c->napi, mlx5e_napi_poll, 64);
1785 err = mlx5e_open_cq(c, icocq_moder, &cparam->icosq_cq, &c->icosq.cq);
1789 err = mlx5e_open_tx_cqs(c, params, cparam);
1791 goto err_close_icosq_cq;
1793 err = mlx5e_open_cq(c, params->rx_cq_moderation, &cparam->rx_cq, &c->rq.cq);
1795 goto err_close_tx_cqs;
1797 /* XDP SQ CQ params are same as normal TXQ sq CQ params */
1798 err = c->xdp ? mlx5e_open_cq(c, params->tx_cq_moderation,
1799 &cparam->tx_cq, &c->rq.xdpsq.cq) : 0;
1801 goto err_close_rx_cq;
1803 napi_enable(&c->napi);
1805 err = mlx5e_open_icosq(c, params, &cparam->icosq, &c->icosq);
1807 goto err_disable_napi;
1809 err = mlx5e_open_sqs(c, params, cparam);
1811 goto err_close_icosq;
1813 err = c->xdp ? mlx5e_open_xdpsq(c, params, &cparam->xdp_sq, &c->rq.xdpsq) : 0;
1817 err = mlx5e_open_rq(c, params, &cparam->rq, &c->rq);
1819 goto err_close_xdp_sq;
1826 mlx5e_close_xdpsq(&c->rq.xdpsq);
1832 mlx5e_close_icosq(&c->icosq);
1835 napi_disable(&c->napi);
1837 mlx5e_close_cq(&c->rq.xdpsq.cq);
1840 mlx5e_close_cq(&c->rq.cq);
1843 mlx5e_close_tx_cqs(c);
1846 mlx5e_close_cq(&c->icosq.cq);
1849 netif_napi_del(&c->napi);
1855 static void mlx5e_activate_channel(struct mlx5e_channel *c)
1859 for (tc = 0; tc < c->num_tc; tc++)
1860 mlx5e_activate_txqsq(&c->sq[tc]);
1861 mlx5e_activate_rq(&c->rq);
1862 netif_set_xps_queue(c->netdev,
1863 mlx5_get_vector_affinity(c->priv->mdev, c->ix), c->ix);
1866 static void mlx5e_deactivate_channel(struct mlx5e_channel *c)
1870 mlx5e_deactivate_rq(&c->rq);
1871 for (tc = 0; tc < c->num_tc; tc++)
1872 mlx5e_deactivate_txqsq(&c->sq[tc]);
1875 static void mlx5e_close_channel(struct mlx5e_channel *c)
1877 mlx5e_close_rq(&c->rq);
1879 mlx5e_close_xdpsq(&c->rq.xdpsq);
1881 mlx5e_close_icosq(&c->icosq);
1882 napi_disable(&c->napi);
1884 mlx5e_close_cq(&c->rq.xdpsq.cq);
1885 mlx5e_close_cq(&c->rq.cq);
1886 mlx5e_close_tx_cqs(c);
1887 mlx5e_close_cq(&c->icosq.cq);
1888 netif_napi_del(&c->napi);
1893 static void mlx5e_build_rq_param(struct mlx5e_priv *priv,
1894 struct mlx5e_params *params,
1895 struct mlx5e_rq_param *param)
1897 void *rqc = param->rqc;
1898 void *wq = MLX5_ADDR_OF(rqc, rqc, wq);
1900 switch (params->rq_wq_type) {
1901 case MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ:
1902 MLX5_SET(wq, wq, log_wqe_num_of_strides, params->mpwqe_log_num_strides - 9);
1903 MLX5_SET(wq, wq, log_wqe_stride_size, params->mpwqe_log_stride_sz - 6);
1904 MLX5_SET(wq, wq, wq_type, MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ);
1906 default: /* MLX5_WQ_TYPE_LINKED_LIST */
1907 MLX5_SET(wq, wq, wq_type, MLX5_WQ_TYPE_LINKED_LIST);
1910 MLX5_SET(wq, wq, end_padding_mode, MLX5_WQ_END_PAD_MODE_ALIGN);
1911 MLX5_SET(wq, wq, log_wq_stride, ilog2(sizeof(struct mlx5e_rx_wqe)));
1912 MLX5_SET(wq, wq, log_wq_sz, params->log_rq_size);
1913 MLX5_SET(wq, wq, pd, priv->mdev->mlx5e_res.pdn);
1914 MLX5_SET(rqc, rqc, counter_set_id, priv->q_counter);
1915 MLX5_SET(rqc, rqc, vsd, params->vlan_strip_disable);
1916 MLX5_SET(rqc, rqc, scatter_fcs, params->scatter_fcs_en);
1918 param->wq.buf_numa_node = dev_to_node(&priv->mdev->pdev->dev);
1919 param->wq.linear = 1;
1922 static void mlx5e_build_drop_rq_param(struct mlx5e_rq_param *param)
1924 void *rqc = param->rqc;
1925 void *wq = MLX5_ADDR_OF(rqc, rqc, wq);
1927 MLX5_SET(wq, wq, wq_type, MLX5_WQ_TYPE_LINKED_LIST);
1928 MLX5_SET(wq, wq, log_wq_stride, ilog2(sizeof(struct mlx5e_rx_wqe)));
1931 static void mlx5e_build_sq_param_common(struct mlx5e_priv *priv,
1932 struct mlx5e_sq_param *param)
1934 void *sqc = param->sqc;
1935 void *wq = MLX5_ADDR_OF(sqc, sqc, wq);
1937 MLX5_SET(wq, wq, log_wq_stride, ilog2(MLX5_SEND_WQE_BB));
1938 MLX5_SET(wq, wq, pd, priv->mdev->mlx5e_res.pdn);
1940 param->wq.buf_numa_node = dev_to_node(&priv->mdev->pdev->dev);
1943 static void mlx5e_build_sq_param(struct mlx5e_priv *priv,
1944 struct mlx5e_params *params,
1945 struct mlx5e_sq_param *param)
1947 void *sqc = param->sqc;
1948 void *wq = MLX5_ADDR_OF(sqc, sqc, wq);
1950 mlx5e_build_sq_param_common(priv, param);
1951 MLX5_SET(wq, wq, log_wq_sz, params->log_sq_size);
1952 MLX5_SET(sqc, sqc, allow_swp, !!MLX5_IPSEC_DEV(priv->mdev));
1955 static void mlx5e_build_common_cq_param(struct mlx5e_priv *priv,
1956 struct mlx5e_cq_param *param)
1958 void *cqc = param->cqc;
1960 MLX5_SET(cqc, cqc, uar_page, priv->mdev->priv.uar->index);
1963 static void mlx5e_build_rx_cq_param(struct mlx5e_priv *priv,
1964 struct mlx5e_params *params,
1965 struct mlx5e_cq_param *param)
1967 void *cqc = param->cqc;
1970 switch (params->rq_wq_type) {
1971 case MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ:
1972 log_cq_size = params->log_rq_size + params->mpwqe_log_num_strides;
1974 default: /* MLX5_WQ_TYPE_LINKED_LIST */
1975 log_cq_size = params->log_rq_size;
1978 MLX5_SET(cqc, cqc, log_cq_size, log_cq_size);
1979 if (MLX5E_GET_PFLAG(params, MLX5E_PFLAG_RX_CQE_COMPRESS)) {
1980 MLX5_SET(cqc, cqc, mini_cqe_res_format, MLX5_CQE_FORMAT_CSUM);
1981 MLX5_SET(cqc, cqc, cqe_comp_en, 1);
1984 mlx5e_build_common_cq_param(priv, param);
1985 param->cq_period_mode = params->rx_cq_period_mode;
1988 static void mlx5e_build_tx_cq_param(struct mlx5e_priv *priv,
1989 struct mlx5e_params *params,
1990 struct mlx5e_cq_param *param)
1992 void *cqc = param->cqc;
1994 MLX5_SET(cqc, cqc, log_cq_size, params->log_sq_size);
1996 mlx5e_build_common_cq_param(priv, param);
1998 param->cq_period_mode = MLX5_CQ_PERIOD_MODE_START_FROM_EQE;
2001 static void mlx5e_build_ico_cq_param(struct mlx5e_priv *priv,
2003 struct mlx5e_cq_param *param)
2005 void *cqc = param->cqc;
2007 MLX5_SET(cqc, cqc, log_cq_size, log_wq_size);
2009 mlx5e_build_common_cq_param(priv, param);
2011 param->cq_period_mode = MLX5_CQ_PERIOD_MODE_START_FROM_EQE;
2014 static void mlx5e_build_icosq_param(struct mlx5e_priv *priv,
2016 struct mlx5e_sq_param *param)
2018 void *sqc = param->sqc;
2019 void *wq = MLX5_ADDR_OF(sqc, sqc, wq);
2021 mlx5e_build_sq_param_common(priv, param);
2023 MLX5_SET(wq, wq, log_wq_sz, log_wq_size);
2024 MLX5_SET(sqc, sqc, reg_umr, MLX5_CAP_ETH(priv->mdev, reg_umr_sq));
2027 static void mlx5e_build_xdpsq_param(struct mlx5e_priv *priv,
2028 struct mlx5e_params *params,
2029 struct mlx5e_sq_param *param)
2031 void *sqc = param->sqc;
2032 void *wq = MLX5_ADDR_OF(sqc, sqc, wq);
2034 mlx5e_build_sq_param_common(priv, param);
2035 MLX5_SET(wq, wq, log_wq_sz, params->log_sq_size);
2038 static void mlx5e_build_channel_param(struct mlx5e_priv *priv,
2039 struct mlx5e_params *params,
2040 struct mlx5e_channel_param *cparam)
2042 u8 icosq_log_wq_sz = MLX5E_PARAMS_MINIMUM_LOG_SQ_SIZE;
2044 mlx5e_build_rq_param(priv, params, &cparam->rq);
2045 mlx5e_build_sq_param(priv, params, &cparam->sq);
2046 mlx5e_build_xdpsq_param(priv, params, &cparam->xdp_sq);
2047 mlx5e_build_icosq_param(priv, icosq_log_wq_sz, &cparam->icosq);
2048 mlx5e_build_rx_cq_param(priv, params, &cparam->rx_cq);
2049 mlx5e_build_tx_cq_param(priv, params, &cparam->tx_cq);
2050 mlx5e_build_ico_cq_param(priv, icosq_log_wq_sz, &cparam->icosq_cq);
2053 int mlx5e_open_channels(struct mlx5e_priv *priv,
2054 struct mlx5e_channels *chs)
2056 struct mlx5e_channel_param *cparam;
2060 chs->num = chs->params.num_channels;
2062 chs->c = kcalloc(chs->num, sizeof(struct mlx5e_channel *), GFP_KERNEL);
2063 cparam = kzalloc(sizeof(struct mlx5e_channel_param), GFP_KERNEL);
2064 if (!chs->c || !cparam)
2067 mlx5e_build_channel_param(priv, &chs->params, cparam);
2068 for (i = 0; i < chs->num; i++) {
2069 err = mlx5e_open_channel(priv, i, &chs->params, cparam, &chs->c[i]);
2071 goto err_close_channels;
2078 for (i--; i >= 0; i--)
2079 mlx5e_close_channel(chs->c[i]);
2088 static void mlx5e_activate_channels(struct mlx5e_channels *chs)
2092 for (i = 0; i < chs->num; i++)
2093 mlx5e_activate_channel(chs->c[i]);
2096 static int mlx5e_wait_channels_min_rx_wqes(struct mlx5e_channels *chs)
2101 for (i = 0; i < chs->num; i++) {
2102 err = mlx5e_wait_for_min_rx_wqes(&chs->c[i]->rq);
2110 static void mlx5e_deactivate_channels(struct mlx5e_channels *chs)
2114 for (i = 0; i < chs->num; i++)
2115 mlx5e_deactivate_channel(chs->c[i]);
2118 void mlx5e_close_channels(struct mlx5e_channels *chs)
2122 for (i = 0; i < chs->num; i++)
2123 mlx5e_close_channel(chs->c[i]);
2130 mlx5e_create_rqt(struct mlx5e_priv *priv, int sz, struct mlx5e_rqt *rqt)
2132 struct mlx5_core_dev *mdev = priv->mdev;
2139 inlen = MLX5_ST_SZ_BYTES(create_rqt_in) + sizeof(u32) * sz;
2140 in = kvzalloc(inlen, GFP_KERNEL);
2144 rqtc = MLX5_ADDR_OF(create_rqt_in, in, rqt_context);
2146 MLX5_SET(rqtc, rqtc, rqt_actual_size, sz);
2147 MLX5_SET(rqtc, rqtc, rqt_max_size, sz);
2149 for (i = 0; i < sz; i++)
2150 MLX5_SET(rqtc, rqtc, rq_num[i], priv->drop_rq.rqn);
2152 err = mlx5_core_create_rqt(mdev, in, inlen, &rqt->rqtn);
2154 rqt->enabled = true;
2160 void mlx5e_destroy_rqt(struct mlx5e_priv *priv, struct mlx5e_rqt *rqt)
2162 rqt->enabled = false;
2163 mlx5_core_destroy_rqt(priv->mdev, rqt->rqtn);
2166 int mlx5e_create_indirect_rqt(struct mlx5e_priv *priv)
2168 struct mlx5e_rqt *rqt = &priv->indir_rqt;
2171 err = mlx5e_create_rqt(priv, MLX5E_INDIR_RQT_SIZE, rqt);
2173 mlx5_core_warn(priv->mdev, "create indirect rqts failed, %d\n", err);
2177 int mlx5e_create_direct_rqts(struct mlx5e_priv *priv)
2179 struct mlx5e_rqt *rqt;
2183 for (ix = 0; ix < priv->profile->max_nch(priv->mdev); ix++) {
2184 rqt = &priv->direct_tir[ix].rqt;
2185 err = mlx5e_create_rqt(priv, 1 /*size */, rqt);
2187 goto err_destroy_rqts;
2193 mlx5_core_warn(priv->mdev, "create direct rqts failed, %d\n", err);
2194 for (ix--; ix >= 0; ix--)
2195 mlx5e_destroy_rqt(priv, &priv->direct_tir[ix].rqt);
2200 void mlx5e_destroy_direct_rqts(struct mlx5e_priv *priv)
2204 for (i = 0; i < priv->profile->max_nch(priv->mdev); i++)
2205 mlx5e_destroy_rqt(priv, &priv->direct_tir[i].rqt);
2208 static int mlx5e_rx_hash_fn(int hfunc)
2210 return (hfunc == ETH_RSS_HASH_TOP) ?
2211 MLX5_RX_HASH_FN_TOEPLITZ :
2212 MLX5_RX_HASH_FN_INVERTED_XOR8;
2215 static int mlx5e_bits_invert(unsigned long a, int size)
2220 for (i = 0; i < size; i++)
2221 inv |= (test_bit(size - i - 1, &a) ? 1 : 0) << i;
2226 static void mlx5e_fill_rqt_rqns(struct mlx5e_priv *priv, int sz,
2227 struct mlx5e_redirect_rqt_param rrp, void *rqtc)
2231 for (i = 0; i < sz; i++) {
2237 if (rrp.rss.hfunc == ETH_RSS_HASH_XOR)
2238 ix = mlx5e_bits_invert(i, ilog2(sz));
2240 ix = priv->channels.params.indirection_rqt[ix];
2241 rqn = rrp.rss.channels->c[ix]->rq.rqn;
2245 MLX5_SET(rqtc, rqtc, rq_num[i], rqn);
2249 int mlx5e_redirect_rqt(struct mlx5e_priv *priv, u32 rqtn, int sz,
2250 struct mlx5e_redirect_rqt_param rrp)
2252 struct mlx5_core_dev *mdev = priv->mdev;
2258 inlen = MLX5_ST_SZ_BYTES(modify_rqt_in) + sizeof(u32) * sz;
2259 in = kvzalloc(inlen, GFP_KERNEL);
2263 rqtc = MLX5_ADDR_OF(modify_rqt_in, in, ctx);
2265 MLX5_SET(rqtc, rqtc, rqt_actual_size, sz);
2266 MLX5_SET(modify_rqt_in, in, bitmask.rqn_list, 1);
2267 mlx5e_fill_rqt_rqns(priv, sz, rrp, rqtc);
2268 err = mlx5_core_modify_rqt(mdev, rqtn, in, inlen);
2274 static u32 mlx5e_get_direct_rqn(struct mlx5e_priv *priv, int ix,
2275 struct mlx5e_redirect_rqt_param rrp)
2280 if (ix >= rrp.rss.channels->num)
2281 return priv->drop_rq.rqn;
2283 return rrp.rss.channels->c[ix]->rq.rqn;
2286 static void mlx5e_redirect_rqts(struct mlx5e_priv *priv,
2287 struct mlx5e_redirect_rqt_param rrp)
2292 if (priv->indir_rqt.enabled) {
2294 rqtn = priv->indir_rqt.rqtn;
2295 mlx5e_redirect_rqt(priv, rqtn, MLX5E_INDIR_RQT_SIZE, rrp);
2298 for (ix = 0; ix < priv->profile->max_nch(priv->mdev); ix++) {
2299 struct mlx5e_redirect_rqt_param direct_rrp = {
2302 .rqn = mlx5e_get_direct_rqn(priv, ix, rrp)
2306 /* Direct RQ Tables */
2307 if (!priv->direct_tir[ix].rqt.enabled)
2310 rqtn = priv->direct_tir[ix].rqt.rqtn;
2311 mlx5e_redirect_rqt(priv, rqtn, 1, direct_rrp);
2315 static void mlx5e_redirect_rqts_to_channels(struct mlx5e_priv *priv,
2316 struct mlx5e_channels *chs)
2318 struct mlx5e_redirect_rqt_param rrp = {
2323 .hfunc = chs->params.rss_hfunc,
2328 mlx5e_redirect_rqts(priv, rrp);
2331 static void mlx5e_redirect_rqts_to_drop(struct mlx5e_priv *priv)
2333 struct mlx5e_redirect_rqt_param drop_rrp = {
2336 .rqn = priv->drop_rq.rqn,
2340 mlx5e_redirect_rqts(priv, drop_rrp);
2343 static void mlx5e_build_tir_ctx_lro(struct mlx5e_params *params, void *tirc)
2345 if (!params->lro_en)
2348 #define ROUGH_MAX_L2_L3_HDR_SZ 256
2350 MLX5_SET(tirc, tirc, lro_enable_mask,
2351 MLX5_TIRC_LRO_ENABLE_MASK_IPV4_LRO |
2352 MLX5_TIRC_LRO_ENABLE_MASK_IPV6_LRO);
2353 MLX5_SET(tirc, tirc, lro_max_ip_payload_size,
2354 (params->lro_wqe_sz - ROUGH_MAX_L2_L3_HDR_SZ) >> 8);
2355 MLX5_SET(tirc, tirc, lro_timeout_period_usecs, params->lro_timeout);
2358 void mlx5e_build_indir_tir_ctx_hash(struct mlx5e_params *params,
2359 enum mlx5e_traffic_types tt,
2360 void *tirc, bool inner)
2362 void *hfso = inner ? MLX5_ADDR_OF(tirc, tirc, rx_hash_field_selector_inner) :
2363 MLX5_ADDR_OF(tirc, tirc, rx_hash_field_selector_outer);
2365 #define MLX5_HASH_IP (MLX5_HASH_FIELD_SEL_SRC_IP |\
2366 MLX5_HASH_FIELD_SEL_DST_IP)
2368 #define MLX5_HASH_IP_L4PORTS (MLX5_HASH_FIELD_SEL_SRC_IP |\
2369 MLX5_HASH_FIELD_SEL_DST_IP |\
2370 MLX5_HASH_FIELD_SEL_L4_SPORT |\
2371 MLX5_HASH_FIELD_SEL_L4_DPORT)
2373 #define MLX5_HASH_IP_IPSEC_SPI (MLX5_HASH_FIELD_SEL_SRC_IP |\
2374 MLX5_HASH_FIELD_SEL_DST_IP |\
2375 MLX5_HASH_FIELD_SEL_IPSEC_SPI)
2377 MLX5_SET(tirc, tirc, rx_hash_fn, mlx5e_rx_hash_fn(params->rss_hfunc));
2378 if (params->rss_hfunc == ETH_RSS_HASH_TOP) {
2379 void *rss_key = MLX5_ADDR_OF(tirc, tirc,
2380 rx_hash_toeplitz_key);
2381 size_t len = MLX5_FLD_SZ_BYTES(tirc,
2382 rx_hash_toeplitz_key);
2384 MLX5_SET(tirc, tirc, rx_hash_symmetric, 1);
2385 memcpy(rss_key, params->toeplitz_hash_key, len);
2389 case MLX5E_TT_IPV4_TCP:
2390 MLX5_SET(rx_hash_field_select, hfso, l3_prot_type,
2391 MLX5_L3_PROT_TYPE_IPV4);
2392 MLX5_SET(rx_hash_field_select, hfso, l4_prot_type,
2393 MLX5_L4_PROT_TYPE_TCP);
2394 MLX5_SET(rx_hash_field_select, hfso, selected_fields,
2395 MLX5_HASH_IP_L4PORTS);
2398 case MLX5E_TT_IPV6_TCP:
2399 MLX5_SET(rx_hash_field_select, hfso, l3_prot_type,
2400 MLX5_L3_PROT_TYPE_IPV6);
2401 MLX5_SET(rx_hash_field_select, hfso, l4_prot_type,
2402 MLX5_L4_PROT_TYPE_TCP);
2403 MLX5_SET(rx_hash_field_select, hfso, selected_fields,
2404 MLX5_HASH_IP_L4PORTS);
2407 case MLX5E_TT_IPV4_UDP:
2408 MLX5_SET(rx_hash_field_select, hfso, l3_prot_type,
2409 MLX5_L3_PROT_TYPE_IPV4);
2410 MLX5_SET(rx_hash_field_select, hfso, l4_prot_type,
2411 MLX5_L4_PROT_TYPE_UDP);
2412 MLX5_SET(rx_hash_field_select, hfso, selected_fields,
2413 MLX5_HASH_IP_L4PORTS);
2416 case MLX5E_TT_IPV6_UDP:
2417 MLX5_SET(rx_hash_field_select, hfso, l3_prot_type,
2418 MLX5_L3_PROT_TYPE_IPV6);
2419 MLX5_SET(rx_hash_field_select, hfso, l4_prot_type,
2420 MLX5_L4_PROT_TYPE_UDP);
2421 MLX5_SET(rx_hash_field_select, hfso, selected_fields,
2422 MLX5_HASH_IP_L4PORTS);
2425 case MLX5E_TT_IPV4_IPSEC_AH:
2426 MLX5_SET(rx_hash_field_select, hfso, l3_prot_type,
2427 MLX5_L3_PROT_TYPE_IPV4);
2428 MLX5_SET(rx_hash_field_select, hfso, selected_fields,
2429 MLX5_HASH_IP_IPSEC_SPI);
2432 case MLX5E_TT_IPV6_IPSEC_AH:
2433 MLX5_SET(rx_hash_field_select, hfso, l3_prot_type,
2434 MLX5_L3_PROT_TYPE_IPV6);
2435 MLX5_SET(rx_hash_field_select, hfso, selected_fields,
2436 MLX5_HASH_IP_IPSEC_SPI);
2439 case MLX5E_TT_IPV4_IPSEC_ESP:
2440 MLX5_SET(rx_hash_field_select, hfso, l3_prot_type,
2441 MLX5_L3_PROT_TYPE_IPV4);
2442 MLX5_SET(rx_hash_field_select, hfso, selected_fields,
2443 MLX5_HASH_IP_IPSEC_SPI);
2446 case MLX5E_TT_IPV6_IPSEC_ESP:
2447 MLX5_SET(rx_hash_field_select, hfso, l3_prot_type,
2448 MLX5_L3_PROT_TYPE_IPV6);
2449 MLX5_SET(rx_hash_field_select, hfso, selected_fields,
2450 MLX5_HASH_IP_IPSEC_SPI);
2454 MLX5_SET(rx_hash_field_select, hfso, l3_prot_type,
2455 MLX5_L3_PROT_TYPE_IPV4);
2456 MLX5_SET(rx_hash_field_select, hfso, selected_fields,
2461 MLX5_SET(rx_hash_field_select, hfso, l3_prot_type,
2462 MLX5_L3_PROT_TYPE_IPV6);
2463 MLX5_SET(rx_hash_field_select, hfso, selected_fields,
2467 WARN_ONCE(true, "%s: bad traffic type!\n", __func__);
2471 static int mlx5e_modify_tirs_lro(struct mlx5e_priv *priv)
2473 struct mlx5_core_dev *mdev = priv->mdev;
2482 inlen = MLX5_ST_SZ_BYTES(modify_tir_in);
2483 in = kvzalloc(inlen, GFP_KERNEL);
2487 MLX5_SET(modify_tir_in, in, bitmask.lro, 1);
2488 tirc = MLX5_ADDR_OF(modify_tir_in, in, ctx);
2490 mlx5e_build_tir_ctx_lro(&priv->channels.params, tirc);
2492 for (tt = 0; tt < MLX5E_NUM_INDIR_TIRS; tt++) {
2493 err = mlx5_core_modify_tir(mdev, priv->indir_tir[tt].tirn, in,
2499 for (ix = 0; ix < priv->profile->max_nch(priv->mdev); ix++) {
2500 err = mlx5_core_modify_tir(mdev, priv->direct_tir[ix].tirn,
2512 static void mlx5e_build_inner_indir_tir_ctx(struct mlx5e_priv *priv,
2513 enum mlx5e_traffic_types tt,
2516 MLX5_SET(tirc, tirc, transport_domain, priv->mdev->mlx5e_res.td.tdn);
2518 mlx5e_build_tir_ctx_lro(&priv->channels.params, tirc);
2520 MLX5_SET(tirc, tirc, disp_type, MLX5_TIRC_DISP_TYPE_INDIRECT);
2521 MLX5_SET(tirc, tirc, indirect_table, priv->indir_rqt.rqtn);
2522 MLX5_SET(tirc, tirc, tunneled_offload_en, 0x1);
2524 mlx5e_build_indir_tir_ctx_hash(&priv->channels.params, tt, tirc, true);
2527 static int mlx5e_set_mtu(struct mlx5e_priv *priv, u16 mtu)
2529 struct mlx5_core_dev *mdev = priv->mdev;
2530 u16 hw_mtu = MLX5E_SW2HW_MTU(priv, mtu);
2533 err = mlx5_set_port_mtu(mdev, hw_mtu, 1);
2537 /* Update vport context MTU */
2538 mlx5_modify_nic_vport_mtu(mdev, hw_mtu);
2542 static void mlx5e_query_mtu(struct mlx5e_priv *priv, u16 *mtu)
2544 struct mlx5_core_dev *mdev = priv->mdev;
2548 err = mlx5_query_nic_vport_mtu(mdev, &hw_mtu);
2549 if (err || !hw_mtu) /* fallback to port oper mtu */
2550 mlx5_query_port_oper_mtu(mdev, &hw_mtu, 1);
2552 *mtu = MLX5E_HW2SW_MTU(priv, hw_mtu);
2555 static int mlx5e_set_dev_port_mtu(struct mlx5e_priv *priv)
2557 struct net_device *netdev = priv->netdev;
2561 err = mlx5e_set_mtu(priv, netdev->mtu);
2565 mlx5e_query_mtu(priv, &mtu);
2566 if (mtu != netdev->mtu)
2567 netdev_warn(netdev, "%s: VPort MTU %d is different than netdev mtu %d\n",
2568 __func__, mtu, netdev->mtu);
2574 static void mlx5e_netdev_set_tcs(struct net_device *netdev)
2576 struct mlx5e_priv *priv = netdev_priv(netdev);
2577 int nch = priv->channels.params.num_channels;
2578 int ntc = priv->channels.params.num_tc;
2581 netdev_reset_tc(netdev);
2586 netdev_set_num_tc(netdev, ntc);
2588 /* Map netdev TCs to offset 0
2589 * We have our own UP to TXQ mapping for QoS
2591 for (tc = 0; tc < ntc; tc++)
2592 netdev_set_tc_queue(netdev, tc, nch, 0);
2595 static void mlx5e_build_channels_tx_maps(struct mlx5e_priv *priv)
2597 struct mlx5e_channel *c;
2598 struct mlx5e_txqsq *sq;
2601 for (i = 0; i < priv->channels.num; i++)
2602 for (tc = 0; tc < priv->profile->max_tc; tc++)
2603 priv->channel_tc2txq[i][tc] = i + tc * priv->channels.num;
2605 for (i = 0; i < priv->channels.num; i++) {
2606 c = priv->channels.c[i];
2607 for (tc = 0; tc < c->num_tc; tc++) {
2609 priv->txq2sq[sq->txq_ix] = sq;
2614 void mlx5e_activate_priv_channels(struct mlx5e_priv *priv)
2616 int num_txqs = priv->channels.num * priv->channels.params.num_tc;
2617 struct net_device *netdev = priv->netdev;
2619 mlx5e_netdev_set_tcs(netdev);
2620 netif_set_real_num_tx_queues(netdev, num_txqs);
2621 netif_set_real_num_rx_queues(netdev, priv->channels.num);
2623 mlx5e_build_channels_tx_maps(priv);
2624 mlx5e_activate_channels(&priv->channels);
2625 netif_tx_start_all_queues(priv->netdev);
2627 if (MLX5_VPORT_MANAGER(priv->mdev))
2628 mlx5e_add_sqs_fwd_rules(priv);
2630 mlx5e_wait_channels_min_rx_wqes(&priv->channels);
2631 mlx5e_redirect_rqts_to_channels(priv, &priv->channels);
2634 void mlx5e_deactivate_priv_channels(struct mlx5e_priv *priv)
2636 mlx5e_redirect_rqts_to_drop(priv);
2638 if (MLX5_VPORT_MANAGER(priv->mdev))
2639 mlx5e_remove_sqs_fwd_rules(priv);
2641 /* FIXME: This is a W/A only for tx timeout watch dog false alarm when
2642 * polling for inactive tx queues.
2644 netif_tx_stop_all_queues(priv->netdev);
2645 netif_tx_disable(priv->netdev);
2646 mlx5e_deactivate_channels(&priv->channels);
2649 void mlx5e_switch_priv_channels(struct mlx5e_priv *priv,
2650 struct mlx5e_channels *new_chs,
2651 mlx5e_fp_hw_modify hw_modify)
2653 struct net_device *netdev = priv->netdev;
2656 new_num_txqs = new_chs->num * new_chs->params.num_tc;
2658 carrier_ok = netif_carrier_ok(netdev);
2659 netif_carrier_off(netdev);
2661 if (new_num_txqs < netdev->real_num_tx_queues)
2662 netif_set_real_num_tx_queues(netdev, new_num_txqs);
2664 mlx5e_deactivate_priv_channels(priv);
2665 mlx5e_close_channels(&priv->channels);
2667 priv->channels = *new_chs;
2669 /* New channels are ready to roll, modify HW settings if needed */
2673 mlx5e_refresh_tirs(priv, false);
2674 mlx5e_activate_priv_channels(priv);
2676 /* return carrier back if needed */
2678 netif_carrier_on(netdev);
2681 int mlx5e_open_locked(struct net_device *netdev)
2683 struct mlx5e_priv *priv = netdev_priv(netdev);
2686 set_bit(MLX5E_STATE_OPENED, &priv->state);
2688 err = mlx5e_open_channels(priv, &priv->channels);
2690 goto err_clear_state_opened_flag;
2692 mlx5e_refresh_tirs(priv, false);
2693 mlx5e_activate_priv_channels(priv);
2694 if (priv->profile->update_carrier)
2695 priv->profile->update_carrier(priv);
2696 mlx5e_timestamp_init(priv);
2698 if (priv->profile->update_stats)
2699 queue_delayed_work(priv->wq, &priv->update_stats_work, 0);
2703 err_clear_state_opened_flag:
2704 clear_bit(MLX5E_STATE_OPENED, &priv->state);
2708 int mlx5e_open(struct net_device *netdev)
2710 struct mlx5e_priv *priv = netdev_priv(netdev);
2713 mutex_lock(&priv->state_lock);
2714 err = mlx5e_open_locked(netdev);
2716 mlx5_set_port_admin_status(priv->mdev, MLX5_PORT_UP);
2717 mutex_unlock(&priv->state_lock);
2722 int mlx5e_close_locked(struct net_device *netdev)
2724 struct mlx5e_priv *priv = netdev_priv(netdev);
2726 /* May already be CLOSED in case a previous configuration operation
2727 * (e.g RX/TX queue size change) that involves close&open failed.
2729 if (!test_bit(MLX5E_STATE_OPENED, &priv->state))
2732 clear_bit(MLX5E_STATE_OPENED, &priv->state);
2734 mlx5e_timestamp_cleanup(priv);
2735 netif_carrier_off(priv->netdev);
2736 mlx5e_deactivate_priv_channels(priv);
2737 mlx5e_close_channels(&priv->channels);
2742 int mlx5e_close(struct net_device *netdev)
2744 struct mlx5e_priv *priv = netdev_priv(netdev);
2747 if (!netif_device_present(netdev))
2750 mutex_lock(&priv->state_lock);
2751 mlx5_set_port_admin_status(priv->mdev, MLX5_PORT_DOWN);
2752 err = mlx5e_close_locked(netdev);
2753 mutex_unlock(&priv->state_lock);
2758 static int mlx5e_alloc_drop_rq(struct mlx5_core_dev *mdev,
2759 struct mlx5e_rq *rq,
2760 struct mlx5e_rq_param *param)
2762 void *rqc = param->rqc;
2763 void *rqc_wq = MLX5_ADDR_OF(rqc, rqc, wq);
2766 param->wq.db_numa_node = param->wq.buf_numa_node;
2768 err = mlx5_wq_ll_create(mdev, ¶m->wq, rqc_wq, &rq->wq,
2778 static int mlx5e_alloc_drop_cq(struct mlx5_core_dev *mdev,
2779 struct mlx5e_cq *cq,
2780 struct mlx5e_cq_param *param)
2782 return mlx5e_alloc_cq_common(mdev, param, cq);
2785 static int mlx5e_open_drop_rq(struct mlx5_core_dev *mdev,
2786 struct mlx5e_rq *drop_rq)
2788 struct mlx5e_cq_param cq_param = {};
2789 struct mlx5e_rq_param rq_param = {};
2790 struct mlx5e_cq *cq = &drop_rq->cq;
2793 mlx5e_build_drop_rq_param(&rq_param);
2795 err = mlx5e_alloc_drop_cq(mdev, cq, &cq_param);
2799 err = mlx5e_create_cq(cq, &cq_param);
2803 err = mlx5e_alloc_drop_rq(mdev, drop_rq, &rq_param);
2805 goto err_destroy_cq;
2807 err = mlx5e_create_rq(drop_rq, &rq_param);
2814 mlx5e_free_rq(drop_rq);
2817 mlx5e_destroy_cq(cq);
2825 static void mlx5e_close_drop_rq(struct mlx5e_rq *drop_rq)
2827 mlx5e_destroy_rq(drop_rq);
2828 mlx5e_free_rq(drop_rq);
2829 mlx5e_destroy_cq(&drop_rq->cq);
2830 mlx5e_free_cq(&drop_rq->cq);
2833 int mlx5e_create_tis(struct mlx5_core_dev *mdev, int tc,
2834 u32 underlay_qpn, u32 *tisn)
2836 u32 in[MLX5_ST_SZ_DW(create_tis_in)] = {0};
2837 void *tisc = MLX5_ADDR_OF(create_tis_in, in, ctx);
2839 MLX5_SET(tisc, tisc, prio, tc << 1);
2840 MLX5_SET(tisc, tisc, underlay_qpn, underlay_qpn);
2841 MLX5_SET(tisc, tisc, transport_domain, mdev->mlx5e_res.td.tdn);
2843 if (mlx5_lag_is_lacp_owner(mdev))
2844 MLX5_SET(tisc, tisc, strict_lag_tx_port_affinity, 1);
2846 return mlx5_core_create_tis(mdev, in, sizeof(in), tisn);
2849 void mlx5e_destroy_tis(struct mlx5_core_dev *mdev, u32 tisn)
2851 mlx5_core_destroy_tis(mdev, tisn);
2854 int mlx5e_create_tises(struct mlx5e_priv *priv)
2859 for (tc = 0; tc < priv->profile->max_tc; tc++) {
2860 err = mlx5e_create_tis(priv->mdev, tc, 0, &priv->tisn[tc]);
2862 goto err_close_tises;
2868 for (tc--; tc >= 0; tc--)
2869 mlx5e_destroy_tis(priv->mdev, priv->tisn[tc]);
2874 void mlx5e_cleanup_nic_tx(struct mlx5e_priv *priv)
2878 for (tc = 0; tc < priv->profile->max_tc; tc++)
2879 mlx5e_destroy_tis(priv->mdev, priv->tisn[tc]);
2882 static void mlx5e_build_indir_tir_ctx(struct mlx5e_priv *priv,
2883 enum mlx5e_traffic_types tt,
2886 MLX5_SET(tirc, tirc, transport_domain, priv->mdev->mlx5e_res.td.tdn);
2888 mlx5e_build_tir_ctx_lro(&priv->channels.params, tirc);
2890 MLX5_SET(tirc, tirc, disp_type, MLX5_TIRC_DISP_TYPE_INDIRECT);
2891 MLX5_SET(tirc, tirc, indirect_table, priv->indir_rqt.rqtn);
2892 mlx5e_build_indir_tir_ctx_hash(&priv->channels.params, tt, tirc, false);
2895 static void mlx5e_build_direct_tir_ctx(struct mlx5e_priv *priv, u32 rqtn, u32 *tirc)
2897 MLX5_SET(tirc, tirc, transport_domain, priv->mdev->mlx5e_res.td.tdn);
2899 mlx5e_build_tir_ctx_lro(&priv->channels.params, tirc);
2901 MLX5_SET(tirc, tirc, disp_type, MLX5_TIRC_DISP_TYPE_INDIRECT);
2902 MLX5_SET(tirc, tirc, indirect_table, rqtn);
2903 MLX5_SET(tirc, tirc, rx_hash_fn, MLX5_RX_HASH_FN_INVERTED_XOR8);
2906 int mlx5e_create_indirect_tirs(struct mlx5e_priv *priv)
2908 struct mlx5e_tir *tir;
2916 inlen = MLX5_ST_SZ_BYTES(create_tir_in);
2917 in = kvzalloc(inlen, GFP_KERNEL);
2921 for (tt = 0; tt < MLX5E_NUM_INDIR_TIRS; tt++) {
2922 memset(in, 0, inlen);
2923 tir = &priv->indir_tir[tt];
2924 tirc = MLX5_ADDR_OF(create_tir_in, in, ctx);
2925 mlx5e_build_indir_tir_ctx(priv, tt, tirc);
2926 err = mlx5e_create_tir(priv->mdev, tir, in, inlen);
2928 mlx5_core_warn(priv->mdev, "create indirect tirs failed, %d\n", err);
2929 goto err_destroy_inner_tirs;
2933 if (!mlx5e_tunnel_inner_ft_supported(priv->mdev))
2936 for (i = 0; i < MLX5E_NUM_INDIR_TIRS; i++) {
2937 memset(in, 0, inlen);
2938 tir = &priv->inner_indir_tir[i];
2939 tirc = MLX5_ADDR_OF(create_tir_in, in, ctx);
2940 mlx5e_build_inner_indir_tir_ctx(priv, i, tirc);
2941 err = mlx5e_create_tir(priv->mdev, tir, in, inlen);
2943 mlx5_core_warn(priv->mdev, "create inner indirect tirs failed, %d\n", err);
2944 goto err_destroy_inner_tirs;
2953 err_destroy_inner_tirs:
2954 for (i--; i >= 0; i--)
2955 mlx5e_destroy_tir(priv->mdev, &priv->inner_indir_tir[i]);
2957 for (tt--; tt >= 0; tt--)
2958 mlx5e_destroy_tir(priv->mdev, &priv->indir_tir[tt]);
2965 int mlx5e_create_direct_tirs(struct mlx5e_priv *priv)
2967 int nch = priv->profile->max_nch(priv->mdev);
2968 struct mlx5e_tir *tir;
2975 inlen = MLX5_ST_SZ_BYTES(create_tir_in);
2976 in = kvzalloc(inlen, GFP_KERNEL);
2980 for (ix = 0; ix < nch; ix++) {
2981 memset(in, 0, inlen);
2982 tir = &priv->direct_tir[ix];
2983 tirc = MLX5_ADDR_OF(create_tir_in, in, ctx);
2984 mlx5e_build_direct_tir_ctx(priv, priv->direct_tir[ix].rqt.rqtn, tirc);
2985 err = mlx5e_create_tir(priv->mdev, tir, in, inlen);
2987 goto err_destroy_ch_tirs;
2994 err_destroy_ch_tirs:
2995 mlx5_core_warn(priv->mdev, "create direct tirs failed, %d\n", err);
2996 for (ix--; ix >= 0; ix--)
2997 mlx5e_destroy_tir(priv->mdev, &priv->direct_tir[ix]);
3004 void mlx5e_destroy_indirect_tirs(struct mlx5e_priv *priv)
3008 for (i = 0; i < MLX5E_NUM_INDIR_TIRS; i++)
3009 mlx5e_destroy_tir(priv->mdev, &priv->indir_tir[i]);
3011 if (!mlx5e_tunnel_inner_ft_supported(priv->mdev))
3014 for (i = 0; i < MLX5E_NUM_INDIR_TIRS; i++)
3015 mlx5e_destroy_tir(priv->mdev, &priv->inner_indir_tir[i]);
3018 void mlx5e_destroy_direct_tirs(struct mlx5e_priv *priv)
3020 int nch = priv->profile->max_nch(priv->mdev);
3023 for (i = 0; i < nch; i++)
3024 mlx5e_destroy_tir(priv->mdev, &priv->direct_tir[i]);
3027 static int mlx5e_modify_channels_scatter_fcs(struct mlx5e_channels *chs, bool enable)
3032 for (i = 0; i < chs->num; i++) {
3033 err = mlx5e_modify_rq_scatter_fcs(&chs->c[i]->rq, enable);
3041 static int mlx5e_modify_channels_vsd(struct mlx5e_channels *chs, bool vsd)
3046 for (i = 0; i < chs->num; i++) {
3047 err = mlx5e_modify_rq_vsd(&chs->c[i]->rq, vsd);
3055 static int mlx5e_setup_tc_mqprio(struct net_device *netdev,
3056 struct tc_mqprio_qopt *mqprio)
3058 struct mlx5e_priv *priv = netdev_priv(netdev);
3059 struct mlx5e_channels new_channels = {};
3060 u8 tc = mqprio->num_tc;
3063 mqprio->hw = TC_MQPRIO_HW_OFFLOAD_TCS;
3065 if (tc && tc != MLX5E_MAX_NUM_TC)
3068 mutex_lock(&priv->state_lock);
3070 new_channels.params = priv->channels.params;
3071 new_channels.params.num_tc = tc ? tc : 1;
3073 if (!test_bit(MLX5E_STATE_OPENED, &priv->state)) {
3074 priv->channels.params = new_channels.params;
3078 err = mlx5e_open_channels(priv, &new_channels);
3082 mlx5e_switch_priv_channels(priv, &new_channels, NULL);
3084 mutex_unlock(&priv->state_lock);
3088 #ifdef CONFIG_MLX5_ESWITCH
3089 static int mlx5e_setup_tc_cls_flower(struct net_device *dev,
3090 struct tc_cls_flower_offload *cls_flower)
3092 struct mlx5e_priv *priv = netdev_priv(dev);
3094 if (!is_classid_clsact_ingress(cls_flower->common.classid) ||
3095 cls_flower->common.chain_index)
3098 switch (cls_flower->command) {
3099 case TC_CLSFLOWER_REPLACE:
3100 return mlx5e_configure_flower(priv, cls_flower);
3101 case TC_CLSFLOWER_DESTROY:
3102 return mlx5e_delete_flower(priv, cls_flower);
3103 case TC_CLSFLOWER_STATS:
3104 return mlx5e_stats_flower(priv, cls_flower);
3111 static int mlx5e_setup_tc(struct net_device *dev, enum tc_setup_type type,
3115 #ifdef CONFIG_MLX5_ESWITCH
3116 case TC_SETUP_CLSFLOWER:
3117 return mlx5e_setup_tc_cls_flower(dev, type_data);
3119 case TC_SETUP_MQPRIO:
3120 return mlx5e_setup_tc_mqprio(dev, type_data);
3127 mlx5e_get_stats(struct net_device *dev, struct rtnl_link_stats64 *stats)
3129 struct mlx5e_priv *priv = netdev_priv(dev);
3130 struct mlx5e_sw_stats *sstats = &priv->stats.sw;
3131 struct mlx5e_vport_stats *vstats = &priv->stats.vport;
3132 struct mlx5e_pport_stats *pstats = &priv->stats.pport;
3134 if (mlx5e_is_uplink_rep(priv)) {
3135 stats->rx_packets = PPORT_802_3_GET(pstats, a_frames_received_ok);
3136 stats->rx_bytes = PPORT_802_3_GET(pstats, a_octets_received_ok);
3137 stats->tx_packets = PPORT_802_3_GET(pstats, a_frames_transmitted_ok);
3138 stats->tx_bytes = PPORT_802_3_GET(pstats, a_octets_transmitted_ok);
3140 stats->rx_packets = sstats->rx_packets;
3141 stats->rx_bytes = sstats->rx_bytes;
3142 stats->tx_packets = sstats->tx_packets;
3143 stats->tx_bytes = sstats->tx_bytes;
3144 stats->tx_dropped = sstats->tx_queue_dropped;
3147 stats->rx_dropped = priv->stats.qcnt.rx_out_of_buffer;
3149 stats->rx_length_errors =
3150 PPORT_802_3_GET(pstats, a_in_range_length_errors) +
3151 PPORT_802_3_GET(pstats, a_out_of_range_length_field) +
3152 PPORT_802_3_GET(pstats, a_frame_too_long_errors);
3153 stats->rx_crc_errors =
3154 PPORT_802_3_GET(pstats, a_frame_check_sequence_errors);
3155 stats->rx_frame_errors = PPORT_802_3_GET(pstats, a_alignment_errors);
3156 stats->tx_aborted_errors = PPORT_2863_GET(pstats, if_out_discards);
3157 stats->rx_errors = stats->rx_length_errors + stats->rx_crc_errors +
3158 stats->rx_frame_errors;
3159 stats->tx_errors = stats->tx_aborted_errors + stats->tx_carrier_errors;
3161 /* vport multicast also counts packets that are dropped due to steering
3162 * or rx out of buffer
3165 VPORT_COUNTER_GET(vstats, received_eth_multicast.packets);
3168 static void mlx5e_set_rx_mode(struct net_device *dev)
3170 struct mlx5e_priv *priv = netdev_priv(dev);
3172 queue_work(priv->wq, &priv->set_rx_mode_work);
3175 static int mlx5e_set_mac(struct net_device *netdev, void *addr)
3177 struct mlx5e_priv *priv = netdev_priv(netdev);
3178 struct sockaddr *saddr = addr;
3180 if (!is_valid_ether_addr(saddr->sa_data))
3181 return -EADDRNOTAVAIL;
3183 netif_addr_lock_bh(netdev);
3184 ether_addr_copy(netdev->dev_addr, saddr->sa_data);
3185 netif_addr_unlock_bh(netdev);
3187 queue_work(priv->wq, &priv->set_rx_mode_work);
3192 #define MLX5E_SET_FEATURE(netdev, feature, enable) \
3195 netdev->features |= feature; \
3197 netdev->features &= ~feature; \
3200 typedef int (*mlx5e_feature_handler)(struct net_device *netdev, bool enable);
3202 static int set_feature_lro(struct net_device *netdev, bool enable)
3204 struct mlx5e_priv *priv = netdev_priv(netdev);
3205 struct mlx5e_channels new_channels = {};
3209 mutex_lock(&priv->state_lock);
3211 reset = (priv->channels.params.rq_wq_type == MLX5_WQ_TYPE_LINKED_LIST);
3212 reset = reset && test_bit(MLX5E_STATE_OPENED, &priv->state);
3214 new_channels.params = priv->channels.params;
3215 new_channels.params.lro_en = enable;
3218 priv->channels.params = new_channels.params;
3219 err = mlx5e_modify_tirs_lro(priv);
3223 err = mlx5e_open_channels(priv, &new_channels);
3227 mlx5e_switch_priv_channels(priv, &new_channels, mlx5e_modify_tirs_lro);
3229 mutex_unlock(&priv->state_lock);
3233 static int set_feature_vlan_filter(struct net_device *netdev, bool enable)
3235 struct mlx5e_priv *priv = netdev_priv(netdev);
3238 mlx5e_enable_vlan_filter(priv);
3240 mlx5e_disable_vlan_filter(priv);
3245 static int set_feature_tc_num_filters(struct net_device *netdev, bool enable)
3247 struct mlx5e_priv *priv = netdev_priv(netdev);
3249 if (!enable && mlx5e_tc_num_filters(priv)) {
3251 "Active offloaded tc filters, can't turn hw_tc_offload off\n");
3258 static int set_feature_rx_all(struct net_device *netdev, bool enable)
3260 struct mlx5e_priv *priv = netdev_priv(netdev);
3261 struct mlx5_core_dev *mdev = priv->mdev;
3263 return mlx5_set_port_fcs(mdev, !enable);
3266 static int set_feature_rx_fcs(struct net_device *netdev, bool enable)
3268 struct mlx5e_priv *priv = netdev_priv(netdev);
3271 mutex_lock(&priv->state_lock);
3273 priv->channels.params.scatter_fcs_en = enable;
3274 err = mlx5e_modify_channels_scatter_fcs(&priv->channels, enable);
3276 priv->channels.params.scatter_fcs_en = !enable;
3278 mutex_unlock(&priv->state_lock);
3283 static int set_feature_rx_vlan(struct net_device *netdev, bool enable)
3285 struct mlx5e_priv *priv = netdev_priv(netdev);
3288 mutex_lock(&priv->state_lock);
3290 priv->channels.params.vlan_strip_disable = !enable;
3291 if (!test_bit(MLX5E_STATE_OPENED, &priv->state))
3294 err = mlx5e_modify_channels_vsd(&priv->channels, !enable);
3296 priv->channels.params.vlan_strip_disable = enable;
3299 mutex_unlock(&priv->state_lock);
3304 #ifdef CONFIG_RFS_ACCEL
3305 static int set_feature_arfs(struct net_device *netdev, bool enable)
3307 struct mlx5e_priv *priv = netdev_priv(netdev);
3311 err = mlx5e_arfs_enable(priv);
3313 err = mlx5e_arfs_disable(priv);
3319 static int mlx5e_handle_feature(struct net_device *netdev,
3320 netdev_features_t wanted_features,
3321 netdev_features_t feature,
3322 mlx5e_feature_handler feature_handler)
3324 netdev_features_t changes = wanted_features ^ netdev->features;
3325 bool enable = !!(wanted_features & feature);
3328 if (!(changes & feature))
3331 err = feature_handler(netdev, enable);
3333 netdev_err(netdev, "%s feature %pNF failed, err %d\n",
3334 enable ? "Enable" : "Disable", &feature, err);
3338 MLX5E_SET_FEATURE(netdev, feature, enable);
3342 static int mlx5e_set_features(struct net_device *netdev,
3343 netdev_features_t features)
3347 err = mlx5e_handle_feature(netdev, features, NETIF_F_LRO,
3349 err |= mlx5e_handle_feature(netdev, features,
3350 NETIF_F_HW_VLAN_CTAG_FILTER,
3351 set_feature_vlan_filter);
3352 err |= mlx5e_handle_feature(netdev, features, NETIF_F_HW_TC,
3353 set_feature_tc_num_filters);
3354 err |= mlx5e_handle_feature(netdev, features, NETIF_F_RXALL,
3355 set_feature_rx_all);
3356 err |= mlx5e_handle_feature(netdev, features, NETIF_F_RXFCS,
3357 set_feature_rx_fcs);
3358 err |= mlx5e_handle_feature(netdev, features, NETIF_F_HW_VLAN_CTAG_RX,
3359 set_feature_rx_vlan);
3360 #ifdef CONFIG_RFS_ACCEL
3361 err |= mlx5e_handle_feature(netdev, features, NETIF_F_NTUPLE,
3365 return err ? -EINVAL : 0;
3368 static int mlx5e_change_mtu(struct net_device *netdev, int new_mtu)
3370 struct mlx5e_priv *priv = netdev_priv(netdev);
3371 struct mlx5e_channels new_channels = {};
3376 mutex_lock(&priv->state_lock);
3378 reset = !priv->channels.params.lro_en &&
3379 (priv->channels.params.rq_wq_type !=
3380 MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ);
3382 reset = reset && test_bit(MLX5E_STATE_OPENED, &priv->state);
3384 curr_mtu = netdev->mtu;
3385 netdev->mtu = new_mtu;
3388 mlx5e_set_dev_port_mtu(priv);
3392 new_channels.params = priv->channels.params;
3393 err = mlx5e_open_channels(priv, &new_channels);
3395 netdev->mtu = curr_mtu;
3399 mlx5e_switch_priv_channels(priv, &new_channels, mlx5e_set_dev_port_mtu);
3402 mutex_unlock(&priv->state_lock);
3406 static int mlx5e_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
3408 struct mlx5e_priv *priv = netdev_priv(dev);
3412 return mlx5e_hwstamp_set(priv, ifr);
3414 return mlx5e_hwstamp_get(priv, ifr);
3420 #ifdef CONFIG_MLX5_ESWITCH
3421 static int mlx5e_set_vf_mac(struct net_device *dev, int vf, u8 *mac)
3423 struct mlx5e_priv *priv = netdev_priv(dev);
3424 struct mlx5_core_dev *mdev = priv->mdev;
3426 return mlx5_eswitch_set_vport_mac(mdev->priv.eswitch, vf + 1, mac);
3429 static int mlx5e_set_vf_vlan(struct net_device *dev, int vf, u16 vlan, u8 qos,
3432 struct mlx5e_priv *priv = netdev_priv(dev);
3433 struct mlx5_core_dev *mdev = priv->mdev;
3435 if (vlan_proto != htons(ETH_P_8021Q))
3436 return -EPROTONOSUPPORT;
3438 return mlx5_eswitch_set_vport_vlan(mdev->priv.eswitch, vf + 1,
3442 static int mlx5e_set_vf_spoofchk(struct net_device *dev, int vf, bool setting)
3444 struct mlx5e_priv *priv = netdev_priv(dev);
3445 struct mlx5_core_dev *mdev = priv->mdev;
3447 return mlx5_eswitch_set_vport_spoofchk(mdev->priv.eswitch, vf + 1, setting);
3450 static int mlx5e_set_vf_trust(struct net_device *dev, int vf, bool setting)
3452 struct mlx5e_priv *priv = netdev_priv(dev);
3453 struct mlx5_core_dev *mdev = priv->mdev;
3455 return mlx5_eswitch_set_vport_trust(mdev->priv.eswitch, vf + 1, setting);
3458 static int mlx5e_set_vf_rate(struct net_device *dev, int vf, int min_tx_rate,
3461 struct mlx5e_priv *priv = netdev_priv(dev);
3462 struct mlx5_core_dev *mdev = priv->mdev;
3464 return mlx5_eswitch_set_vport_rate(mdev->priv.eswitch, vf + 1,
3465 max_tx_rate, min_tx_rate);
3468 static int mlx5_vport_link2ifla(u8 esw_link)
3471 case MLX5_ESW_VPORT_ADMIN_STATE_DOWN:
3472 return IFLA_VF_LINK_STATE_DISABLE;
3473 case MLX5_ESW_VPORT_ADMIN_STATE_UP:
3474 return IFLA_VF_LINK_STATE_ENABLE;
3476 return IFLA_VF_LINK_STATE_AUTO;
3479 static int mlx5_ifla_link2vport(u8 ifla_link)
3481 switch (ifla_link) {
3482 case IFLA_VF_LINK_STATE_DISABLE:
3483 return MLX5_ESW_VPORT_ADMIN_STATE_DOWN;
3484 case IFLA_VF_LINK_STATE_ENABLE:
3485 return MLX5_ESW_VPORT_ADMIN_STATE_UP;
3487 return MLX5_ESW_VPORT_ADMIN_STATE_AUTO;
3490 static int mlx5e_set_vf_link_state(struct net_device *dev, int vf,
3493 struct mlx5e_priv *priv = netdev_priv(dev);
3494 struct mlx5_core_dev *mdev = priv->mdev;
3496 return mlx5_eswitch_set_vport_state(mdev->priv.eswitch, vf + 1,
3497 mlx5_ifla_link2vport(link_state));
3500 static int mlx5e_get_vf_config(struct net_device *dev,
3501 int vf, struct ifla_vf_info *ivi)
3503 struct mlx5e_priv *priv = netdev_priv(dev);
3504 struct mlx5_core_dev *mdev = priv->mdev;
3507 err = mlx5_eswitch_get_vport_config(mdev->priv.eswitch, vf + 1, ivi);
3510 ivi->linkstate = mlx5_vport_link2ifla(ivi->linkstate);
3514 static int mlx5e_get_vf_stats(struct net_device *dev,
3515 int vf, struct ifla_vf_stats *vf_stats)
3517 struct mlx5e_priv *priv = netdev_priv(dev);
3518 struct mlx5_core_dev *mdev = priv->mdev;
3520 return mlx5_eswitch_get_vport_stats(mdev->priv.eswitch, vf + 1,
3525 static void mlx5e_add_vxlan_port(struct net_device *netdev,
3526 struct udp_tunnel_info *ti)
3528 struct mlx5e_priv *priv = netdev_priv(netdev);
3530 if (ti->type != UDP_TUNNEL_TYPE_VXLAN)
3533 if (!mlx5e_vxlan_allowed(priv->mdev))
3536 mlx5e_vxlan_queue_work(priv, ti->sa_family, be16_to_cpu(ti->port), 1);
3539 static void mlx5e_del_vxlan_port(struct net_device *netdev,
3540 struct udp_tunnel_info *ti)
3542 struct mlx5e_priv *priv = netdev_priv(netdev);
3544 if (ti->type != UDP_TUNNEL_TYPE_VXLAN)
3547 if (!mlx5e_vxlan_allowed(priv->mdev))
3550 mlx5e_vxlan_queue_work(priv, ti->sa_family, be16_to_cpu(ti->port), 0);
3553 static netdev_features_t mlx5e_tunnel_features_check(struct mlx5e_priv *priv,
3554 struct sk_buff *skb,
3555 netdev_features_t features)
3557 struct udphdr *udph;
3561 switch (vlan_get_protocol(skb)) {
3562 case htons(ETH_P_IP):
3563 proto = ip_hdr(skb)->protocol;
3565 case htons(ETH_P_IPV6):
3566 proto = ipv6_hdr(skb)->nexthdr;
3576 udph = udp_hdr(skb);
3577 port = be16_to_cpu(udph->dest);
3579 /* Verify if UDP port is being offloaded by HW */
3580 if (mlx5e_vxlan_lookup_port(priv, port))
3585 /* Disable CSUM and GSO if the udp dport is not offloaded by HW */
3586 return features & ~(NETIF_F_CSUM_MASK | NETIF_F_GSO_MASK);
3589 static netdev_features_t mlx5e_features_check(struct sk_buff *skb,
3590 struct net_device *netdev,
3591 netdev_features_t features)
3593 struct mlx5e_priv *priv = netdev_priv(netdev);
3595 features = vlan_features_check(skb, features);
3596 features = vxlan_features_check(skb, features);
3598 #ifdef CONFIG_MLX5_EN_IPSEC
3599 if (mlx5e_ipsec_feature_check(skb, netdev, features))
3603 /* Validate if the tunneled packet is being offloaded by HW */
3604 if (skb->encapsulation &&
3605 (features & NETIF_F_CSUM_MASK || features & NETIF_F_GSO_MASK))
3606 return mlx5e_tunnel_features_check(priv, skb, features);
3611 static void mlx5e_tx_timeout(struct net_device *dev)
3613 struct mlx5e_priv *priv = netdev_priv(dev);
3614 bool sched_work = false;
3617 netdev_err(dev, "TX timeout detected\n");
3619 for (i = 0; i < priv->channels.num * priv->channels.params.num_tc; i++) {
3620 struct mlx5e_txqsq *sq = priv->txq2sq[i];
3622 if (!netif_xmit_stopped(netdev_get_tx_queue(dev, i)))
3625 clear_bit(MLX5E_SQ_STATE_ENABLED, &sq->state);
3626 netdev_err(dev, "TX timeout on queue: %d, SQ: 0x%x, CQ: 0x%x, SQ Cons: 0x%x SQ Prod: 0x%x\n",
3627 i, sq->sqn, sq->cq.mcq.cqn, sq->cc, sq->pc);
3630 if (sched_work && test_bit(MLX5E_STATE_OPENED, &priv->state))
3631 schedule_work(&priv->tx_timeout_work);
3634 static int mlx5e_xdp_set(struct net_device *netdev, struct bpf_prog *prog)
3636 struct mlx5e_priv *priv = netdev_priv(netdev);
3637 struct bpf_prog *old_prog;
3639 bool reset, was_opened;
3642 mutex_lock(&priv->state_lock);
3644 if ((netdev->features & NETIF_F_LRO) && prog) {
3645 netdev_warn(netdev, "can't set XDP while LRO is on, disable LRO first\n");
3650 if ((netdev->features & NETIF_F_HW_ESP) && prog) {
3651 netdev_warn(netdev, "can't set XDP with IPSec offload\n");
3656 was_opened = test_bit(MLX5E_STATE_OPENED, &priv->state);
3657 /* no need for full reset when exchanging programs */
3658 reset = (!priv->channels.params.xdp_prog || !prog);
3660 if (was_opened && reset)
3661 mlx5e_close_locked(netdev);
3662 if (was_opened && !reset) {
3663 /* num_channels is invariant here, so we can take the
3664 * batched reference right upfront.
3666 prog = bpf_prog_add(prog, priv->channels.num);
3668 err = PTR_ERR(prog);
3673 /* exchange programs, extra prog reference we got from caller
3674 * as long as we don't fail from this point onwards.
3676 old_prog = xchg(&priv->channels.params.xdp_prog, prog);
3678 bpf_prog_put(old_prog);
3680 if (reset) /* change RQ type according to priv->xdp_prog */
3681 mlx5e_set_rq_params(priv->mdev, &priv->channels.params);
3683 if (was_opened && reset)
3684 mlx5e_open_locked(netdev);
3686 if (!test_bit(MLX5E_STATE_OPENED, &priv->state) || reset)
3689 /* exchanging programs w/o reset, we update ref counts on behalf
3690 * of the channels RQs here.
3692 for (i = 0; i < priv->channels.num; i++) {
3693 struct mlx5e_channel *c = priv->channels.c[i];
3695 clear_bit(MLX5E_RQ_STATE_ENABLED, &c->rq.state);
3696 napi_synchronize(&c->napi);
3697 /* prevent mlx5e_poll_rx_cq from accessing rq->xdp_prog */
3699 old_prog = xchg(&c->rq.xdp_prog, prog);
3701 set_bit(MLX5E_RQ_STATE_ENABLED, &c->rq.state);
3702 /* napi_schedule in case we have missed anything */
3703 napi_schedule(&c->napi);
3706 bpf_prog_put(old_prog);
3710 mutex_unlock(&priv->state_lock);
3714 static u32 mlx5e_xdp_query(struct net_device *dev)
3716 struct mlx5e_priv *priv = netdev_priv(dev);
3717 const struct bpf_prog *xdp_prog;
3720 mutex_lock(&priv->state_lock);
3721 xdp_prog = priv->channels.params.xdp_prog;
3723 prog_id = xdp_prog->aux->id;
3724 mutex_unlock(&priv->state_lock);
3729 static int mlx5e_xdp(struct net_device *dev, struct netdev_xdp *xdp)
3731 switch (xdp->command) {
3732 case XDP_SETUP_PROG:
3733 return mlx5e_xdp_set(dev, xdp->prog);
3734 case XDP_QUERY_PROG:
3735 xdp->prog_id = mlx5e_xdp_query(dev);
3736 xdp->prog_attached = !!xdp->prog_id;
3743 #ifdef CONFIG_NET_POLL_CONTROLLER
3744 /* Fake "interrupt" called by netpoll (eg netconsole) to send skbs without
3745 * reenabling interrupts.
3747 static void mlx5e_netpoll(struct net_device *dev)
3749 struct mlx5e_priv *priv = netdev_priv(dev);
3750 struct mlx5e_channels *chs = &priv->channels;
3754 for (i = 0; i < chs->num; i++)
3755 napi_schedule(&chs->c[i]->napi);
3759 static const struct net_device_ops mlx5e_netdev_ops = {
3760 .ndo_open = mlx5e_open,
3761 .ndo_stop = mlx5e_close,
3762 .ndo_start_xmit = mlx5e_xmit,
3763 .ndo_setup_tc = mlx5e_setup_tc,
3764 .ndo_select_queue = mlx5e_select_queue,
3765 .ndo_get_stats64 = mlx5e_get_stats,
3766 .ndo_set_rx_mode = mlx5e_set_rx_mode,
3767 .ndo_set_mac_address = mlx5e_set_mac,
3768 .ndo_vlan_rx_add_vid = mlx5e_vlan_rx_add_vid,
3769 .ndo_vlan_rx_kill_vid = mlx5e_vlan_rx_kill_vid,
3770 .ndo_set_features = mlx5e_set_features,
3771 .ndo_change_mtu = mlx5e_change_mtu,
3772 .ndo_do_ioctl = mlx5e_ioctl,
3773 .ndo_set_tx_maxrate = mlx5e_set_tx_maxrate,
3774 .ndo_udp_tunnel_add = mlx5e_add_vxlan_port,
3775 .ndo_udp_tunnel_del = mlx5e_del_vxlan_port,
3776 .ndo_features_check = mlx5e_features_check,
3777 #ifdef CONFIG_RFS_ACCEL
3778 .ndo_rx_flow_steer = mlx5e_rx_flow_steer,
3780 .ndo_tx_timeout = mlx5e_tx_timeout,
3781 .ndo_xdp = mlx5e_xdp,
3782 #ifdef CONFIG_NET_POLL_CONTROLLER
3783 .ndo_poll_controller = mlx5e_netpoll,
3785 #ifdef CONFIG_MLX5_ESWITCH
3786 /* SRIOV E-Switch NDOs */
3787 .ndo_set_vf_mac = mlx5e_set_vf_mac,
3788 .ndo_set_vf_vlan = mlx5e_set_vf_vlan,
3789 .ndo_set_vf_spoofchk = mlx5e_set_vf_spoofchk,
3790 .ndo_set_vf_trust = mlx5e_set_vf_trust,
3791 .ndo_set_vf_rate = mlx5e_set_vf_rate,
3792 .ndo_get_vf_config = mlx5e_get_vf_config,
3793 .ndo_set_vf_link_state = mlx5e_set_vf_link_state,
3794 .ndo_get_vf_stats = mlx5e_get_vf_stats,
3795 .ndo_has_offload_stats = mlx5e_has_offload_stats,
3796 .ndo_get_offload_stats = mlx5e_get_offload_stats,
3800 static int mlx5e_check_required_hca_cap(struct mlx5_core_dev *mdev)
3802 if (MLX5_CAP_GEN(mdev, port_type) != MLX5_CAP_PORT_TYPE_ETH)
3804 if (!MLX5_CAP_GEN(mdev, eth_net_offloads) ||
3805 !MLX5_CAP_GEN(mdev, nic_flow_table) ||
3806 !MLX5_CAP_ETH(mdev, csum_cap) ||
3807 !MLX5_CAP_ETH(mdev, max_lso_cap) ||
3808 !MLX5_CAP_ETH(mdev, vlan_cap) ||
3809 !MLX5_CAP_ETH(mdev, rss_ind_tbl_cap) ||
3810 MLX5_CAP_FLOWTABLE(mdev,
3811 flow_table_properties_nic_receive.max_ft_level)
3813 mlx5_core_warn(mdev,
3814 "Not creating net device, some required device capabilities are missing\n");
3817 if (!MLX5_CAP_ETH(mdev, self_lb_en_modifiable))
3818 mlx5_core_warn(mdev, "Self loop back prevention is not supported\n");
3819 if (!MLX5_CAP_GEN(mdev, cq_moderation))
3820 mlx5_core_warn(mdev, "CQ moderation is not supported\n");
3825 u16 mlx5e_get_max_inline_cap(struct mlx5_core_dev *mdev)
3827 int bf_buf_size = (1 << MLX5_CAP_GEN(mdev, log_bf_reg_size)) / 2;
3829 return bf_buf_size -
3830 sizeof(struct mlx5e_tx_wqe) +
3831 2 /*sizeof(mlx5e_tx_wqe.inline_hdr_start)*/;
3834 void mlx5e_build_default_indir_rqt(u32 *indirection_rqt, int len,
3839 for (i = 0; i < len; i++)
3840 indirection_rqt[i] = i % num_channels;
3843 static int mlx5e_get_pci_bw(struct mlx5_core_dev *mdev, u32 *pci_bw)
3845 enum pcie_link_width width;
3846 enum pci_bus_speed speed;
3849 err = pcie_get_minimum_link(mdev->pdev, &speed, &width);
3853 if (speed == PCI_SPEED_UNKNOWN || width == PCIE_LNK_WIDTH_UNKNOWN)
3857 case PCIE_SPEED_2_5GT:
3858 *pci_bw = 2500 * width;
3860 case PCIE_SPEED_5_0GT:
3861 *pci_bw = 5000 * width;
3863 case PCIE_SPEED_8_0GT:
3864 *pci_bw = 8000 * width;
3873 static bool cqe_compress_heuristic(u32 link_speed, u32 pci_bw)
3875 return (link_speed && pci_bw &&
3876 (pci_bw < 40000) && (pci_bw < link_speed));
3879 static bool hw_lro_heuristic(u32 link_speed, u32 pci_bw)
3881 return !(link_speed && pci_bw &&
3882 (pci_bw <= 16000) && (pci_bw < link_speed));
3885 void mlx5e_set_rx_cq_mode_params(struct mlx5e_params *params, u8 cq_period_mode)
3887 params->rx_cq_period_mode = cq_period_mode;
3889 params->rx_cq_moderation.pkts =
3890 MLX5E_PARAMS_DEFAULT_RX_CQ_MODERATION_PKTS;
3891 params->rx_cq_moderation.usec =
3892 MLX5E_PARAMS_DEFAULT_RX_CQ_MODERATION_USEC;
3894 if (cq_period_mode == MLX5_CQ_PERIOD_MODE_START_FROM_CQE)
3895 params->rx_cq_moderation.usec =
3896 MLX5E_PARAMS_DEFAULT_RX_CQ_MODERATION_USEC_FROM_CQE;
3898 if (params->rx_am_enabled)
3899 params->rx_cq_moderation =
3900 mlx5e_am_get_def_profile(params->rx_cq_period_mode);
3902 MLX5E_SET_PFLAG(params, MLX5E_PFLAG_RX_CQE_BASED_MODER,
3903 params->rx_cq_period_mode == MLX5_CQ_PERIOD_MODE_START_FROM_CQE);
3906 u32 mlx5e_choose_lro_timeout(struct mlx5_core_dev *mdev, u32 wanted_timeout)
3910 /* The supported periods are organized in ascending order */
3911 for (i = 0; i < MLX5E_LRO_TIMEOUT_ARR_SIZE - 1; i++)
3912 if (MLX5_CAP_ETH(mdev, lro_timer_supported_periods[i]) >= wanted_timeout)
3915 return MLX5_CAP_ETH(mdev, lro_timer_supported_periods[i]);
3918 void mlx5e_build_nic_params(struct mlx5_core_dev *mdev,
3919 struct mlx5e_params *params,
3922 u8 cq_period_mode = 0;
3926 params->num_channels = max_channels;
3929 mlx5e_get_max_linkspeed(mdev, &link_speed);
3930 mlx5e_get_pci_bw(mdev, &pci_bw);
3931 mlx5_core_dbg(mdev, "Max link speed = %d, PCI BW = %d\n",
3932 link_speed, pci_bw);
3935 params->log_sq_size = is_kdump_kernel() ?
3936 MLX5E_PARAMS_MINIMUM_LOG_SQ_SIZE :
3937 MLX5E_PARAMS_DEFAULT_LOG_SQ_SIZE;
3939 /* set CQE compression */
3940 params->rx_cqe_compress_def = false;
3941 if (MLX5_CAP_GEN(mdev, cqe_compression) &&
3942 MLX5_CAP_GEN(mdev, vport_group_manager))
3943 params->rx_cqe_compress_def = cqe_compress_heuristic(link_speed, pci_bw);
3945 MLX5E_SET_PFLAG(params, MLX5E_PFLAG_RX_CQE_COMPRESS, params->rx_cqe_compress_def);
3948 mlx5e_set_rq_params(mdev, params);
3952 /* TODO: && MLX5_CAP_ETH(mdev, lro_cap) */
3953 if (params->rq_wq_type == MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ)
3954 params->lro_en = hw_lro_heuristic(link_speed, pci_bw);
3955 params->lro_timeout = mlx5e_choose_lro_timeout(mdev, MLX5E_DEFAULT_LRO_TIMEOUT);
3957 /* CQ moderation params */
3958 cq_period_mode = MLX5_CAP_GEN(mdev, cq_period_start_from_cqe) ?
3959 MLX5_CQ_PERIOD_MODE_START_FROM_CQE :
3960 MLX5_CQ_PERIOD_MODE_START_FROM_EQE;
3961 params->rx_am_enabled = MLX5_CAP_GEN(mdev, cq_moderation);
3962 mlx5e_set_rx_cq_mode_params(params, cq_period_mode);
3964 params->tx_cq_moderation.usec = MLX5E_PARAMS_DEFAULT_TX_CQ_MODERATION_USEC;
3965 params->tx_cq_moderation.pkts = MLX5E_PARAMS_DEFAULT_TX_CQ_MODERATION_PKTS;
3968 params->tx_max_inline = mlx5e_get_max_inline_cap(mdev);
3969 mlx5_query_min_inline(mdev, ¶ms->tx_min_inline_mode);
3970 if (params->tx_min_inline_mode == MLX5_INLINE_MODE_NONE &&
3971 !MLX5_CAP_ETH(mdev, wqe_vlan_insert))
3972 params->tx_min_inline_mode = MLX5_INLINE_MODE_L2;
3975 params->rss_hfunc = ETH_RSS_HASH_XOR;
3976 netdev_rss_key_fill(params->toeplitz_hash_key, sizeof(params->toeplitz_hash_key));
3977 mlx5e_build_default_indir_rqt(params->indirection_rqt,
3978 MLX5E_INDIR_RQT_SIZE, max_channels);
3981 static void mlx5e_build_nic_netdev_priv(struct mlx5_core_dev *mdev,
3982 struct net_device *netdev,
3983 const struct mlx5e_profile *profile,
3986 struct mlx5e_priv *priv = netdev_priv(netdev);
3989 priv->netdev = netdev;
3990 priv->profile = profile;
3991 priv->ppriv = ppriv;
3992 priv->hard_mtu = MLX5E_ETH_HARD_MTU;
3994 mlx5e_build_nic_params(mdev, &priv->channels.params, profile->max_nch(mdev));
3996 mutex_init(&priv->state_lock);
3998 INIT_WORK(&priv->update_carrier_work, mlx5e_update_carrier_work);
3999 INIT_WORK(&priv->set_rx_mode_work, mlx5e_set_rx_mode_work);
4000 INIT_WORK(&priv->tx_timeout_work, mlx5e_tx_timeout_work);
4001 INIT_DELAYED_WORK(&priv->update_stats_work, mlx5e_update_stats_work);
4004 static void mlx5e_set_netdev_dev_addr(struct net_device *netdev)
4006 struct mlx5e_priv *priv = netdev_priv(netdev);
4008 mlx5_query_nic_vport_mac_address(priv->mdev, 0, netdev->dev_addr);
4009 if (is_zero_ether_addr(netdev->dev_addr) &&
4010 !MLX5_CAP_GEN(priv->mdev, vport_group_manager)) {
4011 eth_hw_addr_random(netdev);
4012 mlx5_core_info(priv->mdev, "Assigned random MAC address %pM\n", netdev->dev_addr);
4016 #if IS_ENABLED(CONFIG_NET_SWITCHDEV) && IS_ENABLED(CONFIG_MLX5_ESWITCH)
4017 static const struct switchdev_ops mlx5e_switchdev_ops = {
4018 .switchdev_port_attr_get = mlx5e_attr_get,
4022 static void mlx5e_build_nic_netdev(struct net_device *netdev)
4024 struct mlx5e_priv *priv = netdev_priv(netdev);
4025 struct mlx5_core_dev *mdev = priv->mdev;
4029 SET_NETDEV_DEV(netdev, &mdev->pdev->dev);
4031 netdev->netdev_ops = &mlx5e_netdev_ops;
4033 #ifdef CONFIG_MLX5_CORE_EN_DCB
4034 if (MLX5_CAP_GEN(mdev, vport_group_manager) && MLX5_CAP_GEN(mdev, qos))
4035 netdev->dcbnl_ops = &mlx5e_dcbnl_ops;
4038 netdev->watchdog_timeo = 15 * HZ;
4040 netdev->ethtool_ops = &mlx5e_ethtool_ops;
4042 netdev->vlan_features |= NETIF_F_SG;
4043 netdev->vlan_features |= NETIF_F_IP_CSUM;
4044 netdev->vlan_features |= NETIF_F_IPV6_CSUM;
4045 netdev->vlan_features |= NETIF_F_GRO;
4046 netdev->vlan_features |= NETIF_F_TSO;
4047 netdev->vlan_features |= NETIF_F_TSO6;
4048 netdev->vlan_features |= NETIF_F_RXCSUM;
4049 netdev->vlan_features |= NETIF_F_RXHASH;
4051 if (!!MLX5_CAP_ETH(mdev, lro_cap))
4052 netdev->vlan_features |= NETIF_F_LRO;
4054 netdev->hw_features = netdev->vlan_features;
4055 netdev->hw_features |= NETIF_F_HW_VLAN_CTAG_TX;
4056 netdev->hw_features |= NETIF_F_HW_VLAN_CTAG_RX;
4057 netdev->hw_features |= NETIF_F_HW_VLAN_CTAG_FILTER;
4059 if (mlx5e_vxlan_allowed(mdev) || MLX5_CAP_ETH(mdev, tunnel_stateless_gre)) {
4060 netdev->hw_features |= NETIF_F_GSO_PARTIAL;
4061 netdev->hw_enc_features |= NETIF_F_IP_CSUM;
4062 netdev->hw_enc_features |= NETIF_F_IPV6_CSUM;
4063 netdev->hw_enc_features |= NETIF_F_TSO;
4064 netdev->hw_enc_features |= NETIF_F_TSO6;
4065 netdev->hw_enc_features |= NETIF_F_GSO_PARTIAL;
4068 if (mlx5e_vxlan_allowed(mdev)) {
4069 netdev->hw_features |= NETIF_F_GSO_UDP_TUNNEL |
4070 NETIF_F_GSO_UDP_TUNNEL_CSUM;
4071 netdev->hw_enc_features |= NETIF_F_GSO_UDP_TUNNEL |
4072 NETIF_F_GSO_UDP_TUNNEL_CSUM;
4073 netdev->gso_partial_features = NETIF_F_GSO_UDP_TUNNEL_CSUM;
4076 if (MLX5_CAP_ETH(mdev, tunnel_stateless_gre)) {
4077 netdev->hw_features |= NETIF_F_GSO_GRE |
4078 NETIF_F_GSO_GRE_CSUM;
4079 netdev->hw_enc_features |= NETIF_F_GSO_GRE |
4080 NETIF_F_GSO_GRE_CSUM;
4081 netdev->gso_partial_features |= NETIF_F_GSO_GRE |
4082 NETIF_F_GSO_GRE_CSUM;
4085 mlx5_query_port_fcs(mdev, &fcs_supported, &fcs_enabled);
4088 netdev->hw_features |= NETIF_F_RXALL;
4090 if (MLX5_CAP_ETH(mdev, scatter_fcs))
4091 netdev->hw_features |= NETIF_F_RXFCS;
4093 netdev->features = netdev->hw_features;
4094 if (!priv->channels.params.lro_en)
4095 netdev->features &= ~NETIF_F_LRO;
4098 netdev->features &= ~NETIF_F_RXALL;
4100 if (!priv->channels.params.scatter_fcs_en)
4101 netdev->features &= ~NETIF_F_RXFCS;
4103 #define FT_CAP(f) MLX5_CAP_FLOWTABLE(mdev, flow_table_properties_nic_receive.f)
4104 if (FT_CAP(flow_modify_en) &&
4105 FT_CAP(modify_root) &&
4106 FT_CAP(identified_miss_table_mode) &&
4107 FT_CAP(flow_table_modify)) {
4108 netdev->hw_features |= NETIF_F_HW_TC;
4109 #ifdef CONFIG_RFS_ACCEL
4110 netdev->hw_features |= NETIF_F_NTUPLE;
4114 netdev->features |= NETIF_F_HIGHDMA;
4116 netdev->priv_flags |= IFF_UNICAST_FLT;
4118 mlx5e_set_netdev_dev_addr(netdev);
4120 #if IS_ENABLED(CONFIG_NET_SWITCHDEV) && IS_ENABLED(CONFIG_MLX5_ESWITCH)
4121 if (MLX5_VPORT_MANAGER(mdev))
4122 netdev->switchdev_ops = &mlx5e_switchdev_ops;
4125 mlx5e_ipsec_build_netdev(priv);
4128 static void mlx5e_create_q_counter(struct mlx5e_priv *priv)
4130 struct mlx5_core_dev *mdev = priv->mdev;
4133 err = mlx5_core_alloc_q_counter(mdev, &priv->q_counter);
4135 mlx5_core_warn(mdev, "alloc queue counter failed, %d\n", err);
4136 priv->q_counter = 0;
4140 static void mlx5e_destroy_q_counter(struct mlx5e_priv *priv)
4142 if (!priv->q_counter)
4145 mlx5_core_dealloc_q_counter(priv->mdev, priv->q_counter);
4148 static void mlx5e_nic_init(struct mlx5_core_dev *mdev,
4149 struct net_device *netdev,
4150 const struct mlx5e_profile *profile,
4153 struct mlx5e_priv *priv = netdev_priv(netdev);
4156 mlx5e_build_nic_netdev_priv(mdev, netdev, profile, ppriv);
4157 err = mlx5e_ipsec_init(priv);
4159 mlx5_core_err(mdev, "IPSec initialization failed, %d\n", err);
4160 mlx5e_build_nic_netdev(netdev);
4161 mlx5e_vxlan_init(priv);
4164 static void mlx5e_nic_cleanup(struct mlx5e_priv *priv)
4166 mlx5e_ipsec_cleanup(priv);
4167 mlx5e_vxlan_cleanup(priv);
4169 if (priv->channels.params.xdp_prog)
4170 bpf_prog_put(priv->channels.params.xdp_prog);
4173 static int mlx5e_init_nic_rx(struct mlx5e_priv *priv)
4175 struct mlx5_core_dev *mdev = priv->mdev;
4178 err = mlx5e_create_indirect_rqt(priv);
4182 err = mlx5e_create_direct_rqts(priv);
4184 goto err_destroy_indirect_rqts;
4186 err = mlx5e_create_indirect_tirs(priv);
4188 goto err_destroy_direct_rqts;
4190 err = mlx5e_create_direct_tirs(priv);
4192 goto err_destroy_indirect_tirs;
4194 err = mlx5e_create_flow_steering(priv);
4196 mlx5_core_warn(mdev, "create flow steering failed, %d\n", err);
4197 goto err_destroy_direct_tirs;
4200 err = mlx5e_tc_init(priv);
4202 goto err_destroy_flow_steering;
4206 err_destroy_flow_steering:
4207 mlx5e_destroy_flow_steering(priv);
4208 err_destroy_direct_tirs:
4209 mlx5e_destroy_direct_tirs(priv);
4210 err_destroy_indirect_tirs:
4211 mlx5e_destroy_indirect_tirs(priv);
4212 err_destroy_direct_rqts:
4213 mlx5e_destroy_direct_rqts(priv);
4214 err_destroy_indirect_rqts:
4215 mlx5e_destroy_rqt(priv, &priv->indir_rqt);
4219 static void mlx5e_cleanup_nic_rx(struct mlx5e_priv *priv)
4221 mlx5e_tc_cleanup(priv);
4222 mlx5e_destroy_flow_steering(priv);
4223 mlx5e_destroy_direct_tirs(priv);
4224 mlx5e_destroy_indirect_tirs(priv);
4225 mlx5e_destroy_direct_rqts(priv);
4226 mlx5e_destroy_rqt(priv, &priv->indir_rqt);
4229 static int mlx5e_init_nic_tx(struct mlx5e_priv *priv)
4233 err = mlx5e_create_tises(priv);
4235 mlx5_core_warn(priv->mdev, "create tises failed, %d\n", err);
4239 #ifdef CONFIG_MLX5_CORE_EN_DCB
4240 mlx5e_dcbnl_initialize(priv);
4245 static void mlx5e_nic_enable(struct mlx5e_priv *priv)
4247 struct net_device *netdev = priv->netdev;
4248 struct mlx5_core_dev *mdev = priv->mdev;
4251 mlx5e_init_l2_addr(priv);
4253 /* Marking the link as currently not needed by the Driver */
4254 if (!netif_running(netdev))
4255 mlx5_set_port_admin_status(mdev, MLX5_PORT_DOWN);
4257 /* MTU range: 68 - hw-specific max */
4258 netdev->min_mtu = ETH_MIN_MTU;
4259 mlx5_query_port_max_mtu(priv->mdev, &max_mtu, 1);
4260 netdev->max_mtu = MLX5E_HW2SW_MTU(priv, max_mtu);
4261 mlx5e_set_dev_port_mtu(priv);
4263 mlx5_lag_add(mdev, netdev);
4265 mlx5e_enable_async_events(priv);
4267 if (MLX5_VPORT_MANAGER(priv->mdev))
4268 mlx5e_register_vport_reps(priv);
4270 if (netdev->reg_state != NETREG_REGISTERED)
4273 /* Device already registered: sync netdev system state */
4274 if (mlx5e_vxlan_allowed(mdev)) {
4276 udp_tunnel_get_rx_info(netdev);
4280 queue_work(priv->wq, &priv->set_rx_mode_work);
4283 if (netif_running(netdev))
4285 netif_device_attach(netdev);
4289 static void mlx5e_nic_disable(struct mlx5e_priv *priv)
4291 struct mlx5_core_dev *mdev = priv->mdev;
4294 if (netif_running(priv->netdev))
4295 mlx5e_close(priv->netdev);
4296 netif_device_detach(priv->netdev);
4299 queue_work(priv->wq, &priv->set_rx_mode_work);
4301 if (MLX5_VPORT_MANAGER(priv->mdev))
4302 mlx5e_unregister_vport_reps(priv);
4304 mlx5e_disable_async_events(priv);
4305 mlx5_lag_remove(mdev);
4308 static const struct mlx5e_profile mlx5e_nic_profile = {
4309 .init = mlx5e_nic_init,
4310 .cleanup = mlx5e_nic_cleanup,
4311 .init_rx = mlx5e_init_nic_rx,
4312 .cleanup_rx = mlx5e_cleanup_nic_rx,
4313 .init_tx = mlx5e_init_nic_tx,
4314 .cleanup_tx = mlx5e_cleanup_nic_tx,
4315 .enable = mlx5e_nic_enable,
4316 .disable = mlx5e_nic_disable,
4317 .update_stats = mlx5e_update_ndo_stats,
4318 .max_nch = mlx5e_get_max_num_channels,
4319 .update_carrier = mlx5e_update_carrier,
4320 .rx_handlers.handle_rx_cqe = mlx5e_handle_rx_cqe,
4321 .rx_handlers.handle_rx_cqe_mpwqe = mlx5e_handle_rx_cqe_mpwrq,
4322 .max_tc = MLX5E_MAX_NUM_TC,
4325 /* mlx5e generic netdev management API (move to en_common.c) */
4327 struct net_device *mlx5e_create_netdev(struct mlx5_core_dev *mdev,
4328 const struct mlx5e_profile *profile,
4331 int nch = profile->max_nch(mdev);
4332 struct net_device *netdev;
4333 struct mlx5e_priv *priv;
4335 netdev = alloc_etherdev_mqs(sizeof(struct mlx5e_priv),
4336 nch * profile->max_tc,
4339 mlx5_core_err(mdev, "alloc_etherdev_mqs() failed\n");
4343 #ifdef CONFIG_RFS_ACCEL
4344 netdev->rx_cpu_rmap = mdev->rmap;
4347 profile->init(mdev, netdev, profile, ppriv);
4349 netif_carrier_off(netdev);
4351 priv = netdev_priv(netdev);
4353 priv->wq = create_singlethread_workqueue("mlx5e");
4355 goto err_cleanup_nic;
4360 if (profile->cleanup)
4361 profile->cleanup(priv);
4362 free_netdev(netdev);
4367 int mlx5e_attach_netdev(struct mlx5e_priv *priv)
4369 struct mlx5_core_dev *mdev = priv->mdev;
4370 const struct mlx5e_profile *profile;
4373 profile = priv->profile;
4374 clear_bit(MLX5E_STATE_DESTROYING, &priv->state);
4376 err = profile->init_tx(priv);
4380 err = mlx5e_open_drop_rq(mdev, &priv->drop_rq);
4382 mlx5_core_err(mdev, "open drop rq failed, %d\n", err);
4383 goto err_cleanup_tx;
4386 err = profile->init_rx(priv);
4388 goto err_close_drop_rq;
4390 mlx5e_create_q_counter(priv);
4392 if (profile->enable)
4393 profile->enable(priv);
4398 mlx5e_close_drop_rq(&priv->drop_rq);
4401 profile->cleanup_tx(priv);
4407 void mlx5e_detach_netdev(struct mlx5e_priv *priv)
4409 const struct mlx5e_profile *profile = priv->profile;
4411 set_bit(MLX5E_STATE_DESTROYING, &priv->state);
4413 if (profile->disable)
4414 profile->disable(priv);
4415 flush_workqueue(priv->wq);
4417 mlx5e_destroy_q_counter(priv);
4418 profile->cleanup_rx(priv);
4419 mlx5e_close_drop_rq(&priv->drop_rq);
4420 profile->cleanup_tx(priv);
4421 cancel_delayed_work_sync(&priv->update_stats_work);
4424 void mlx5e_destroy_netdev(struct mlx5e_priv *priv)
4426 const struct mlx5e_profile *profile = priv->profile;
4427 struct net_device *netdev = priv->netdev;
4429 destroy_workqueue(priv->wq);
4430 if (profile->cleanup)
4431 profile->cleanup(priv);
4432 free_netdev(netdev);
4435 /* mlx5e_attach and mlx5e_detach scope should be only creating/destroying
4436 * hardware contexts and to connect it to the current netdev.
4438 static int mlx5e_attach(struct mlx5_core_dev *mdev, void *vpriv)
4440 struct mlx5e_priv *priv = vpriv;
4441 struct net_device *netdev = priv->netdev;
4444 if (netif_device_present(netdev))
4447 err = mlx5e_create_mdev_resources(mdev);
4451 err = mlx5e_attach_netdev(priv);
4453 mlx5e_destroy_mdev_resources(mdev);
4460 static void mlx5e_detach(struct mlx5_core_dev *mdev, void *vpriv)
4462 struct mlx5e_priv *priv = vpriv;
4463 struct net_device *netdev = priv->netdev;
4465 if (!netif_device_present(netdev))
4468 mlx5e_detach_netdev(priv);
4469 mlx5e_destroy_mdev_resources(mdev);
4472 static void *mlx5e_add(struct mlx5_core_dev *mdev)
4474 struct net_device *netdev;
4479 err = mlx5e_check_required_hca_cap(mdev);
4483 #ifdef CONFIG_MLX5_ESWITCH
4484 if (MLX5_VPORT_MANAGER(mdev)) {
4485 rpriv = mlx5e_alloc_nic_rep_priv(mdev);
4487 mlx5_core_warn(mdev, "Failed to alloc NIC rep priv data\n");
4493 netdev = mlx5e_create_netdev(mdev, &mlx5e_nic_profile, rpriv);
4495 mlx5_core_err(mdev, "mlx5e_create_netdev failed\n");
4496 goto err_free_rpriv;
4499 priv = netdev_priv(netdev);
4501 err = mlx5e_attach(mdev, priv);
4503 mlx5_core_err(mdev, "mlx5e_attach failed, %d\n", err);
4504 goto err_destroy_netdev;
4507 err = register_netdev(netdev);
4509 mlx5_core_err(mdev, "register_netdev failed, %d\n", err);
4516 mlx5e_detach(mdev, priv);
4518 mlx5e_destroy_netdev(priv);
4524 static void mlx5e_remove(struct mlx5_core_dev *mdev, void *vpriv)
4526 struct mlx5e_priv *priv = vpriv;
4527 void *ppriv = priv->ppriv;
4529 unregister_netdev(priv->netdev);
4530 mlx5e_detach(mdev, vpriv);
4531 mlx5e_destroy_netdev(priv);
4535 static void *mlx5e_get_netdev(void *vpriv)
4537 struct mlx5e_priv *priv = vpriv;
4539 return priv->netdev;
4542 static struct mlx5_interface mlx5e_interface = {
4544 .remove = mlx5e_remove,
4545 .attach = mlx5e_attach,
4546 .detach = mlx5e_detach,
4547 .event = mlx5e_async_event,
4548 .protocol = MLX5_INTERFACE_PROTOCOL_ETH,
4549 .get_dev = mlx5e_get_netdev,
4552 void mlx5e_init(void)
4554 mlx5e_ipsec_build_inverse_table();
4555 mlx5e_build_ptys2ethtool_map();
4556 mlx5_register_interface(&mlx5e_interface);
4559 void mlx5e_cleanup(void)
4561 mlx5_unregister_interface(&mlx5e_interface);