2 * Copyright (c) 2015-2016, Mellanox Technologies. All rights reserved.
4 * This software is available to you under a choice of one of two
5 * licenses. You may choose to be licensed under the terms of the GNU
6 * General Public License (GPL) Version 2, available from the file
7 * COPYING in the main directory of this source tree, or the
8 * OpenIB.org BSD license below:
10 * Redistribution and use in source and binary forms, with or
11 * without modification, are permitted provided that the following
14 * - Redistributions of source code must retain the above
15 * copyright notice, this list of conditions and the following
18 * - Redistributions in binary form must reproduce the above
19 * copyright notice, this list of conditions and the following
20 * disclaimer in the documentation and/or other materials
21 * provided with the distribution.
23 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
24 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
25 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
26 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
27 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
28 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
29 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
33 #include <net/tc_act/tc_gact.h>
34 #include <net/pkt_cls.h>
35 #include <linux/mlx5/fs.h>
36 #include <net/vxlan.h>
37 #include <net/geneve.h>
38 #include <linux/bpf.h>
39 #include <linux/if_bridge.h>
40 #include <net/page_pool.h>
41 #include <net/xdp_sock_drv.h>
47 #include "en_accel/ipsec.h"
48 #include "en_accel/en_accel.h"
49 #include "en_accel/tls.h"
50 #include "accel/ipsec.h"
51 #include "accel/tls.h"
52 #include "lib/vxlan.h"
53 #include "lib/clock.h"
57 #include "en/monitor_stats.h"
58 #include "en/health.h"
59 #include "en/params.h"
60 #include "en/xsk/pool.h"
61 #include "en/xsk/setup.h"
62 #include "en/xsk/rx.h"
63 #include "en/xsk/tx.h"
64 #include "en/hv_vhca_stats.h"
65 #include "en/devlink.h"
70 #include "fpga/ipsec.h"
72 bool mlx5e_check_fragmented_striding_rq_cap(struct mlx5_core_dev *mdev)
74 bool striding_rq_umr = MLX5_CAP_GEN(mdev, striding_rq) &&
75 MLX5_CAP_GEN(mdev, umr_ptr_rlky) &&
76 MLX5_CAP_ETH(mdev, reg_umr_sq);
77 u16 max_wqe_sz_cap = MLX5_CAP_GEN(mdev, max_wqe_sz_sq);
78 bool inline_umr = MLX5E_UMR_WQE_INLINE_SZ <= max_wqe_sz_cap;
83 mlx5_core_warn(mdev, "Cannot support Striding RQ: UMR WQE size (%d) exceeds maximum supported (%d).\n",
84 (int)MLX5E_UMR_WQE_INLINE_SZ, max_wqe_sz_cap);
90 void mlx5e_update_carrier(struct mlx5e_priv *priv)
92 struct mlx5_core_dev *mdev = priv->mdev;
95 port_state = mlx5_query_vport_state(mdev,
96 MLX5_VPORT_STATE_OP_MOD_VNIC_VPORT,
99 if (port_state == VPORT_STATE_UP) {
100 netdev_info(priv->netdev, "Link up\n");
101 netif_carrier_on(priv->netdev);
103 netdev_info(priv->netdev, "Link down\n");
104 netif_carrier_off(priv->netdev);
108 static void mlx5e_update_carrier_work(struct work_struct *work)
110 struct mlx5e_priv *priv = container_of(work, struct mlx5e_priv,
111 update_carrier_work);
113 mutex_lock(&priv->state_lock);
114 if (test_bit(MLX5E_STATE_OPENED, &priv->state))
115 if (priv->profile->update_carrier)
116 priv->profile->update_carrier(priv);
117 mutex_unlock(&priv->state_lock);
120 static void mlx5e_update_stats_work(struct work_struct *work)
122 struct mlx5e_priv *priv = container_of(work, struct mlx5e_priv,
125 mutex_lock(&priv->state_lock);
126 priv->profile->update_stats(priv);
127 mutex_unlock(&priv->state_lock);
130 void mlx5e_queue_update_stats(struct mlx5e_priv *priv)
132 if (!priv->profile->update_stats)
135 if (unlikely(test_bit(MLX5E_STATE_DESTROYING, &priv->state)))
138 queue_work(priv->wq, &priv->update_stats_work);
141 static int async_event(struct notifier_block *nb, unsigned long event, void *data)
143 struct mlx5e_priv *priv = container_of(nb, struct mlx5e_priv, events_nb);
144 struct mlx5_eqe *eqe = data;
146 if (event != MLX5_EVENT_TYPE_PORT_CHANGE)
149 switch (eqe->sub_type) {
150 case MLX5_PORT_CHANGE_SUBTYPE_DOWN:
151 case MLX5_PORT_CHANGE_SUBTYPE_ACTIVE:
152 queue_work(priv->wq, &priv->update_carrier_work);
161 static void mlx5e_enable_async_events(struct mlx5e_priv *priv)
163 priv->events_nb.notifier_call = async_event;
164 mlx5_notifier_register(priv->mdev, &priv->events_nb);
167 static void mlx5e_disable_async_events(struct mlx5e_priv *priv)
169 mlx5_notifier_unregister(priv->mdev, &priv->events_nb);
172 static int blocking_event(struct notifier_block *nb, unsigned long event, void *data)
174 struct mlx5e_priv *priv = container_of(nb, struct mlx5e_priv, blocking_events_nb);
178 case MLX5_DRIVER_EVENT_TYPE_TRAP:
179 err = mlx5e_handle_trap_event(priv, data);
182 netdev_warn(priv->netdev, "Sync event: Unknown event %ld\n", event);
188 static void mlx5e_enable_blocking_events(struct mlx5e_priv *priv)
190 priv->blocking_events_nb.notifier_call = blocking_event;
191 mlx5_blocking_notifier_register(priv->mdev, &priv->blocking_events_nb);
194 static void mlx5e_disable_blocking_events(struct mlx5e_priv *priv)
196 mlx5_blocking_notifier_unregister(priv->mdev, &priv->blocking_events_nb);
199 static inline void mlx5e_build_umr_wqe(struct mlx5e_rq *rq,
200 struct mlx5e_icosq *sq,
201 struct mlx5e_umr_wqe *wqe)
203 struct mlx5_wqe_ctrl_seg *cseg = &wqe->ctrl;
204 struct mlx5_wqe_umr_ctrl_seg *ucseg = &wqe->uctrl;
205 u8 ds_cnt = DIV_ROUND_UP(MLX5E_UMR_WQE_INLINE_SZ, MLX5_SEND_WQE_DS);
207 cseg->qpn_ds = cpu_to_be32((sq->sqn << MLX5_WQE_CTRL_QPN_SHIFT) |
209 cseg->umr_mkey = rq->mkey_be;
211 ucseg->flags = MLX5_UMR_TRANSLATION_OFFSET_EN | MLX5_UMR_INLINE;
212 ucseg->xlt_octowords =
213 cpu_to_be16(MLX5_MTT_OCTW(MLX5_MPWRQ_PAGES_PER_WQE));
214 ucseg->mkey_mask = cpu_to_be64(MLX5_MKEY_MASK_FREE);
217 static int mlx5e_rq_alloc_mpwqe_info(struct mlx5e_rq *rq, int node)
219 int wq_sz = mlx5_wq_ll_get_size(&rq->mpwqe.wq);
221 rq->mpwqe.info = kvzalloc_node(array_size(wq_sz,
222 sizeof(*rq->mpwqe.info)),
227 mlx5e_build_umr_wqe(rq, rq->icosq, &rq->mpwqe.umr_wqe);
232 static int mlx5e_create_umr_mkey(struct mlx5_core_dev *mdev,
233 u64 npages, u8 page_shift,
234 struct mlx5_core_mkey *umr_mkey,
235 dma_addr_t filler_addr)
237 struct mlx5_mtt *mtt;
244 inlen = MLX5_ST_SZ_BYTES(create_mkey_in) + sizeof(*mtt) * npages;
246 in = kvzalloc(inlen, GFP_KERNEL);
250 mkc = MLX5_ADDR_OF(create_mkey_in, in, memory_key_mkey_entry);
252 MLX5_SET(mkc, mkc, free, 1);
253 MLX5_SET(mkc, mkc, umr_en, 1);
254 MLX5_SET(mkc, mkc, lw, 1);
255 MLX5_SET(mkc, mkc, lr, 1);
256 MLX5_SET(mkc, mkc, access_mode_1_0, MLX5_MKC_ACCESS_MODE_MTT);
257 mlx5e_mkey_set_relaxed_ordering(mdev, mkc);
258 MLX5_SET(mkc, mkc, qpn, 0xffffff);
259 MLX5_SET(mkc, mkc, pd, mdev->mlx5e_res.hw_objs.pdn);
260 MLX5_SET64(mkc, mkc, len, npages << page_shift);
261 MLX5_SET(mkc, mkc, translations_octword_size,
262 MLX5_MTT_OCTW(npages));
263 MLX5_SET(mkc, mkc, log_page_size, page_shift);
264 MLX5_SET(create_mkey_in, in, translations_octword_actual_size,
265 MLX5_MTT_OCTW(npages));
267 /* Initialize the mkey with all MTTs pointing to a default
268 * page (filler_addr). When the channels are activated, UMR
269 * WQEs will redirect the RX WQEs to the actual memory from
270 * the RQ's pool, while the gaps (wqe_overflow) remain mapped
271 * to the default page.
273 mtt = MLX5_ADDR_OF(create_mkey_in, in, klm_pas_mtt);
274 for (i = 0 ; i < npages ; i++)
275 mtt[i].ptag = cpu_to_be64(filler_addr);
277 err = mlx5_core_create_mkey(mdev, umr_mkey, in, inlen);
283 static int mlx5e_create_rq_umr_mkey(struct mlx5_core_dev *mdev, struct mlx5e_rq *rq)
285 u64 num_mtts = MLX5E_REQUIRED_MTTS(mlx5_wq_ll_get_size(&rq->mpwqe.wq));
287 return mlx5e_create_umr_mkey(mdev, num_mtts, PAGE_SHIFT, &rq->umr_mkey,
288 rq->wqe_overflow.addr);
291 static u64 mlx5e_get_mpwqe_offset(u16 wqe_ix)
293 return MLX5E_REQUIRED_MTTS(wqe_ix) << PAGE_SHIFT;
296 static void mlx5e_init_frags_partition(struct mlx5e_rq *rq)
298 struct mlx5e_wqe_frag_info next_frag = {};
299 struct mlx5e_wqe_frag_info *prev = NULL;
302 next_frag.di = &rq->wqe.di[0];
304 for (i = 0; i < mlx5_wq_cyc_get_size(&rq->wqe.wq); i++) {
305 struct mlx5e_rq_frag_info *frag_info = &rq->wqe.info.arr[0];
306 struct mlx5e_wqe_frag_info *frag =
307 &rq->wqe.frags[i << rq->wqe.info.log_num_frags];
310 for (f = 0; f < rq->wqe.info.num_frags; f++, frag++) {
311 if (next_frag.offset + frag_info[f].frag_stride > PAGE_SIZE) {
313 next_frag.offset = 0;
315 prev->last_in_page = true;
320 next_frag.offset += frag_info[f].frag_stride;
326 prev->last_in_page = true;
329 int mlx5e_init_di_list(struct mlx5e_rq *rq, int wq_sz, int node)
331 int len = wq_sz << rq->wqe.info.log_num_frags;
333 rq->wqe.di = kvzalloc_node(array_size(len, sizeof(*rq->wqe.di)), GFP_KERNEL, node);
337 mlx5e_init_frags_partition(rq);
342 void mlx5e_free_di_list(struct mlx5e_rq *rq)
347 static void mlx5e_rq_err_cqe_work(struct work_struct *recover_work)
349 struct mlx5e_rq *rq = container_of(recover_work, struct mlx5e_rq, recover_work);
351 mlx5e_reporter_rq_cqe_err(rq);
354 static int mlx5e_alloc_mpwqe_rq_drop_page(struct mlx5e_rq *rq)
356 rq->wqe_overflow.page = alloc_page(GFP_KERNEL);
357 if (!rq->wqe_overflow.page)
360 rq->wqe_overflow.addr = dma_map_page(rq->pdev, rq->wqe_overflow.page, 0,
361 PAGE_SIZE, rq->buff.map_dir);
362 if (dma_mapping_error(rq->pdev, rq->wqe_overflow.addr)) {
363 __free_page(rq->wqe_overflow.page);
369 static void mlx5e_free_mpwqe_rq_drop_page(struct mlx5e_rq *rq)
371 dma_unmap_page(rq->pdev, rq->wqe_overflow.addr, PAGE_SIZE,
373 __free_page(rq->wqe_overflow.page);
376 static int mlx5e_init_rxq_rq(struct mlx5e_channel *c, struct mlx5e_params *params,
379 struct mlx5_core_dev *mdev = c->mdev;
382 rq->wq_type = params->rq_wq_type;
384 rq->netdev = c->netdev;
386 rq->tstamp = c->tstamp;
387 rq->clock = &mdev->clock;
388 rq->icosq = &c->icosq;
391 rq->hw_mtu = MLX5E_SW2HW_MTU(params, params->sw_mtu);
392 rq->xdpsq = &c->rq_xdpsq;
393 rq->stats = &c->priv->channel_stats[c->ix].rq;
394 rq->ptp_cyc2time = mlx5_rq_ts_translator(mdev);
395 err = mlx5e_rq_set_handlers(rq, params, NULL);
399 return xdp_rxq_info_reg(&rq->xdp_rxq, rq->netdev, rq->ix, 0);
402 static int mlx5e_alloc_rq(struct mlx5e_params *params,
403 struct mlx5e_xsk_param *xsk,
404 struct mlx5e_rq_param *rqp,
405 int node, struct mlx5e_rq *rq)
407 struct page_pool_params pp_params = { 0 };
408 struct mlx5_core_dev *mdev = rq->mdev;
409 void *rqc = rqp->rqc;
410 void *rqc_wq = MLX5_ADDR_OF(rqc, rqc, wq);
416 rqp->wq.db_numa_node = node;
417 INIT_WORK(&rq->recover_work, mlx5e_rq_err_cqe_work);
419 if (params->xdp_prog)
420 bpf_prog_inc(params->xdp_prog);
421 RCU_INIT_POINTER(rq->xdp_prog, params->xdp_prog);
423 rq->buff.map_dir = params->xdp_prog ? DMA_BIDIRECTIONAL : DMA_FROM_DEVICE;
424 rq->buff.headroom = mlx5e_get_rq_headroom(mdev, params, xsk);
425 pool_size = 1 << params->log_rq_mtu_frames;
427 switch (rq->wq_type) {
428 case MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ:
429 err = mlx5_wq_ll_create(mdev, &rqp->wq, rqc_wq, &rq->mpwqe.wq,
432 goto err_rq_xdp_prog;
434 err = mlx5e_alloc_mpwqe_rq_drop_page(rq);
436 goto err_rq_wq_destroy;
438 rq->mpwqe.wq.db = &rq->mpwqe.wq.db[MLX5_RCV_DBR];
440 wq_sz = mlx5_wq_ll_get_size(&rq->mpwqe.wq);
442 pool_size = MLX5_MPWRQ_PAGES_PER_WQE <<
443 mlx5e_mpwqe_get_log_rq_size(params, xsk);
445 rq->mpwqe.log_stride_sz = mlx5e_mpwqe_get_log_stride_size(mdev, params, xsk);
446 rq->mpwqe.num_strides =
447 BIT(mlx5e_mpwqe_get_log_num_strides(mdev, params, xsk));
449 rq->buff.frame0_sz = (1 << rq->mpwqe.log_stride_sz);
451 err = mlx5e_create_rq_umr_mkey(mdev, rq);
453 goto err_rq_drop_page;
454 rq->mkey_be = cpu_to_be32(rq->umr_mkey.key);
456 err = mlx5e_rq_alloc_mpwqe_info(rq, node);
460 default: /* MLX5_WQ_TYPE_CYCLIC */
461 err = mlx5_wq_cyc_create(mdev, &rqp->wq, rqc_wq, &rq->wqe.wq,
464 goto err_rq_xdp_prog;
466 rq->wqe.wq.db = &rq->wqe.wq.db[MLX5_RCV_DBR];
468 wq_sz = mlx5_wq_cyc_get_size(&rq->wqe.wq);
470 rq->wqe.info = rqp->frags_info;
471 rq->buff.frame0_sz = rq->wqe.info.arr[0].frag_stride;
474 kvzalloc_node(array_size(sizeof(*rq->wqe.frags),
475 (wq_sz << rq->wqe.info.log_num_frags)),
477 if (!rq->wqe.frags) {
479 goto err_rq_wq_destroy;
482 err = mlx5e_init_di_list(rq, wq_sz, node);
486 rq->mkey_be = cpu_to_be32(mdev->mlx5e_res.hw_objs.mkey.key);
490 err = xdp_rxq_info_reg_mem_model(&rq->xdp_rxq,
491 MEM_TYPE_XSK_BUFF_POOL, NULL);
492 xsk_pool_set_rxq_info(rq->xsk_pool, &rq->xdp_rxq);
494 /* Create a page_pool and register it with rxq */
496 pp_params.flags = 0; /* No-internal DMA mapping in page_pool */
497 pp_params.pool_size = pool_size;
498 pp_params.nid = node;
499 pp_params.dev = rq->pdev;
500 pp_params.dma_dir = rq->buff.map_dir;
502 /* page_pool can be used even when there is no rq->xdp_prog,
503 * given page_pool does not handle DMA mapping there is no
504 * required state to clear. And page_pool gracefully handle
507 rq->page_pool = page_pool_create(&pp_params);
508 if (IS_ERR(rq->page_pool)) {
509 err = PTR_ERR(rq->page_pool);
510 rq->page_pool = NULL;
511 goto err_free_by_rq_type;
513 if (xdp_rxq_info_is_reg(&rq->xdp_rxq))
514 err = xdp_rxq_info_reg_mem_model(&rq->xdp_rxq,
515 MEM_TYPE_PAGE_POOL, rq->page_pool);
518 goto err_free_by_rq_type;
520 for (i = 0; i < wq_sz; i++) {
521 if (rq->wq_type == MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ) {
522 struct mlx5e_rx_wqe_ll *wqe =
523 mlx5_wq_ll_get_wqe(&rq->mpwqe.wq, i);
525 rq->mpwqe.num_strides << rq->mpwqe.log_stride_sz;
526 u64 dma_offset = mlx5e_get_mpwqe_offset(i);
528 wqe->data[0].addr = cpu_to_be64(dma_offset + rq->buff.headroom);
529 wqe->data[0].byte_count = cpu_to_be32(byte_count);
530 wqe->data[0].lkey = rq->mkey_be;
532 struct mlx5e_rx_wqe_cyc *wqe =
533 mlx5_wq_cyc_get_wqe(&rq->wqe.wq, i);
536 for (f = 0; f < rq->wqe.info.num_frags; f++) {
537 u32 frag_size = rq->wqe.info.arr[f].frag_size |
538 MLX5_HW_START_PADDING;
540 wqe->data[f].byte_count = cpu_to_be32(frag_size);
541 wqe->data[f].lkey = rq->mkey_be;
543 /* check if num_frags is not a pow of two */
544 if (rq->wqe.info.num_frags < (1 << rq->wqe.info.log_num_frags)) {
545 wqe->data[f].byte_count = 0;
546 wqe->data[f].lkey = cpu_to_be32(MLX5_INVALID_LKEY);
547 wqe->data[f].addr = 0;
552 INIT_WORK(&rq->dim.work, mlx5e_rx_dim_work);
554 switch (params->rx_cq_moderation.cq_period_mode) {
555 case MLX5_CQ_PERIOD_MODE_START_FROM_CQE:
556 rq->dim.mode = DIM_CQ_PERIOD_MODE_START_FROM_CQE;
558 case MLX5_CQ_PERIOD_MODE_START_FROM_EQE:
560 rq->dim.mode = DIM_CQ_PERIOD_MODE_START_FROM_EQE;
563 rq->page_cache.head = 0;
564 rq->page_cache.tail = 0;
569 switch (rq->wq_type) {
570 case MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ:
571 kvfree(rq->mpwqe.info);
573 mlx5_core_destroy_mkey(mdev, &rq->umr_mkey);
575 mlx5e_free_mpwqe_rq_drop_page(rq);
577 default: /* MLX5_WQ_TYPE_CYCLIC */
578 mlx5e_free_di_list(rq);
580 kvfree(rq->wqe.frags);
583 mlx5_wq_destroy(&rq->wq_ctrl);
585 if (params->xdp_prog)
586 bpf_prog_put(params->xdp_prog);
591 static void mlx5e_free_rq(struct mlx5e_rq *rq)
593 struct bpf_prog *old_prog;
596 if (xdp_rxq_info_is_reg(&rq->xdp_rxq)) {
597 old_prog = rcu_dereference_protected(rq->xdp_prog,
598 lockdep_is_held(&rq->priv->state_lock));
600 bpf_prog_put(old_prog);
603 switch (rq->wq_type) {
604 case MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ:
605 kvfree(rq->mpwqe.info);
606 mlx5_core_destroy_mkey(rq->mdev, &rq->umr_mkey);
607 mlx5e_free_mpwqe_rq_drop_page(rq);
609 default: /* MLX5_WQ_TYPE_CYCLIC */
610 kvfree(rq->wqe.frags);
611 mlx5e_free_di_list(rq);
614 for (i = rq->page_cache.head; i != rq->page_cache.tail;
615 i = (i + 1) & (MLX5E_CACHE_SIZE - 1)) {
616 struct mlx5e_dma_info *dma_info = &rq->page_cache.page_cache[i];
618 /* With AF_XDP, page_cache is not used, so this loop is not
619 * entered, and it's safe to call mlx5e_page_release_dynamic
622 mlx5e_page_release_dynamic(rq, dma_info, false);
625 xdp_rxq_info_unreg(&rq->xdp_rxq);
626 page_pool_destroy(rq->page_pool);
627 mlx5_wq_destroy(&rq->wq_ctrl);
630 int mlx5e_create_rq(struct mlx5e_rq *rq, struct mlx5e_rq_param *param)
632 struct mlx5_core_dev *mdev = rq->mdev;
640 inlen = MLX5_ST_SZ_BYTES(create_rq_in) +
641 sizeof(u64) * rq->wq_ctrl.buf.npages;
642 in = kvzalloc(inlen, GFP_KERNEL);
646 ts_format = mlx5_is_real_time_rq(mdev) ?
647 MLX5_RQC_TIMESTAMP_FORMAT_REAL_TIME :
648 MLX5_RQC_TIMESTAMP_FORMAT_FREE_RUNNING;
649 rqc = MLX5_ADDR_OF(create_rq_in, in, ctx);
650 wq = MLX5_ADDR_OF(rqc, rqc, wq);
652 memcpy(rqc, param->rqc, sizeof(param->rqc));
654 MLX5_SET(rqc, rqc, cqn, rq->cq.mcq.cqn);
655 MLX5_SET(rqc, rqc, state, MLX5_RQC_STATE_RST);
656 MLX5_SET(rqc, rqc, ts_format, ts_format);
657 MLX5_SET(wq, wq, log_wq_pg_sz, rq->wq_ctrl.buf.page_shift -
658 MLX5_ADAPTER_PAGE_SHIFT);
659 MLX5_SET64(wq, wq, dbr_addr, rq->wq_ctrl.db.dma);
661 mlx5_fill_page_frag_array(&rq->wq_ctrl.buf,
662 (__be64 *)MLX5_ADDR_OF(wq, wq, pas));
664 err = mlx5_core_create_rq(mdev, in, inlen, &rq->rqn);
671 int mlx5e_modify_rq_state(struct mlx5e_rq *rq, int curr_state, int next_state)
673 struct mlx5_core_dev *mdev = rq->mdev;
680 inlen = MLX5_ST_SZ_BYTES(modify_rq_in);
681 in = kvzalloc(inlen, GFP_KERNEL);
685 if (curr_state == MLX5_RQC_STATE_RST && next_state == MLX5_RQC_STATE_RDY)
686 mlx5e_rqwq_reset(rq);
688 rqc = MLX5_ADDR_OF(modify_rq_in, in, ctx);
690 MLX5_SET(modify_rq_in, in, rq_state, curr_state);
691 MLX5_SET(rqc, rqc, state, next_state);
693 err = mlx5_core_modify_rq(mdev, rq->rqn, in);
700 static int mlx5e_modify_rq_scatter_fcs(struct mlx5e_rq *rq, bool enable)
702 struct mlx5_core_dev *mdev = rq->mdev;
709 inlen = MLX5_ST_SZ_BYTES(modify_rq_in);
710 in = kvzalloc(inlen, GFP_KERNEL);
714 rqc = MLX5_ADDR_OF(modify_rq_in, in, ctx);
716 MLX5_SET(modify_rq_in, in, rq_state, MLX5_RQC_STATE_RDY);
717 MLX5_SET64(modify_rq_in, in, modify_bitmask,
718 MLX5_MODIFY_RQ_IN_MODIFY_BITMASK_SCATTER_FCS);
719 MLX5_SET(rqc, rqc, scatter_fcs, enable);
720 MLX5_SET(rqc, rqc, state, MLX5_RQC_STATE_RDY);
722 err = mlx5_core_modify_rq(mdev, rq->rqn, in);
729 static int mlx5e_modify_rq_vsd(struct mlx5e_rq *rq, bool vsd)
731 struct mlx5_core_dev *mdev = rq->mdev;
737 inlen = MLX5_ST_SZ_BYTES(modify_rq_in);
738 in = kvzalloc(inlen, GFP_KERNEL);
742 rqc = MLX5_ADDR_OF(modify_rq_in, in, ctx);
744 MLX5_SET(modify_rq_in, in, rq_state, MLX5_RQC_STATE_RDY);
745 MLX5_SET64(modify_rq_in, in, modify_bitmask,
746 MLX5_MODIFY_RQ_IN_MODIFY_BITMASK_VSD);
747 MLX5_SET(rqc, rqc, vsd, vsd);
748 MLX5_SET(rqc, rqc, state, MLX5_RQC_STATE_RDY);
750 err = mlx5_core_modify_rq(mdev, rq->rqn, in);
757 void mlx5e_destroy_rq(struct mlx5e_rq *rq)
759 mlx5_core_destroy_rq(rq->mdev, rq->rqn);
762 int mlx5e_wait_for_min_rx_wqes(struct mlx5e_rq *rq, int wait_time)
764 unsigned long exp_time = jiffies + msecs_to_jiffies(wait_time);
766 u16 min_wqes = mlx5_min_rx_wqes(rq->wq_type, mlx5e_rqwq_get_size(rq));
769 if (mlx5e_rqwq_get_cur_sz(rq) >= min_wqes)
773 } while (time_before(jiffies, exp_time));
775 netdev_warn(rq->netdev, "Failed to get min RX wqes on Channel[%d] RQN[0x%x] wq cur_sz(%d) min_rx_wqes(%d)\n",
776 rq->ix, rq->rqn, mlx5e_rqwq_get_cur_sz(rq), min_wqes);
778 mlx5e_reporter_rx_timeout(rq);
782 void mlx5e_free_rx_in_progress_descs(struct mlx5e_rq *rq)
784 struct mlx5_wq_ll *wq;
788 if (rq->wq_type != MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ)
794 /* Outstanding UMR WQEs (in progress) start at wq->head */
795 for (i = 0; i < rq->mpwqe.umr_in_progress; i++) {
796 rq->dealloc_wqe(rq, head);
797 head = mlx5_wq_ll_get_wqe_next_ix(wq, head);
800 rq->mpwqe.actual_wq_head = wq->head;
801 rq->mpwqe.umr_in_progress = 0;
802 rq->mpwqe.umr_completed = 0;
805 void mlx5e_free_rx_descs(struct mlx5e_rq *rq)
810 if (rq->wq_type == MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ) {
811 struct mlx5_wq_ll *wq = &rq->mpwqe.wq;
813 mlx5e_free_rx_in_progress_descs(rq);
815 while (!mlx5_wq_ll_is_empty(wq)) {
816 struct mlx5e_rx_wqe_ll *wqe;
818 wqe_ix_be = *wq->tail_next;
819 wqe_ix = be16_to_cpu(wqe_ix_be);
820 wqe = mlx5_wq_ll_get_wqe(wq, wqe_ix);
821 rq->dealloc_wqe(rq, wqe_ix);
822 mlx5_wq_ll_pop(wq, wqe_ix_be,
823 &wqe->next.next_wqe_index);
826 struct mlx5_wq_cyc *wq = &rq->wqe.wq;
828 while (!mlx5_wq_cyc_is_empty(wq)) {
829 wqe_ix = mlx5_wq_cyc_get_tail(wq);
830 rq->dealloc_wqe(rq, wqe_ix);
837 int mlx5e_open_rq(struct mlx5e_params *params, struct mlx5e_rq_param *param,
838 struct mlx5e_xsk_param *xsk, int node,
841 struct mlx5_core_dev *mdev = rq->mdev;
844 err = mlx5e_alloc_rq(params, xsk, param, node, rq);
848 err = mlx5e_create_rq(rq, param);
852 err = mlx5e_modify_rq_state(rq, MLX5_RQC_STATE_RST, MLX5_RQC_STATE_RDY);
856 if (mlx5e_is_tls_on(rq->priv) && !mlx5_accel_is_ktls_device(mdev))
857 __set_bit(MLX5E_RQ_STATE_FPGA_TLS, &rq->state); /* must be FPGA */
859 if (MLX5_CAP_ETH(mdev, cqe_checksum_full))
860 __set_bit(MLX5E_RQ_STATE_CSUM_FULL, &rq->state);
862 if (params->rx_dim_enabled)
863 __set_bit(MLX5E_RQ_STATE_AM, &rq->state);
865 /* We disable csum_complete when XDP is enabled since
866 * XDP programs might manipulate packets which will render
867 * skb->checksum incorrect.
869 if (MLX5E_GET_PFLAG(params, MLX5E_PFLAG_RX_NO_CSUM_COMPLETE) || params->xdp_prog)
870 __set_bit(MLX5E_RQ_STATE_NO_CSUM_COMPLETE, &rq->state);
872 /* For CQE compression on striding RQ, use stride index provided by
873 * HW if capability is supported.
875 if (MLX5E_GET_PFLAG(params, MLX5E_PFLAG_RX_STRIDING_RQ) &&
876 MLX5_CAP_GEN(mdev, mini_cqe_resp_stride_index))
877 __set_bit(MLX5E_RQ_STATE_MINI_CQE_HW_STRIDX, &rq->state);
882 mlx5e_destroy_rq(rq);
889 void mlx5e_activate_rq(struct mlx5e_rq *rq)
891 set_bit(MLX5E_RQ_STATE_ENABLED, &rq->state);
893 mlx5e_trigger_irq(rq->icosq);
896 napi_schedule(rq->cq.napi);
901 void mlx5e_deactivate_rq(struct mlx5e_rq *rq)
903 clear_bit(MLX5E_RQ_STATE_ENABLED, &rq->state);
904 synchronize_net(); /* Sync with NAPI to prevent mlx5e_post_rx_wqes. */
907 void mlx5e_close_rq(struct mlx5e_rq *rq)
909 cancel_work_sync(&rq->dim.work);
911 cancel_work_sync(&rq->icosq->recover_work);
912 cancel_work_sync(&rq->recover_work);
913 mlx5e_destroy_rq(rq);
914 mlx5e_free_rx_descs(rq);
918 static void mlx5e_free_xdpsq_db(struct mlx5e_xdpsq *sq)
920 kvfree(sq->db.xdpi_fifo.xi);
921 kvfree(sq->db.wqe_info);
924 static int mlx5e_alloc_xdpsq_fifo(struct mlx5e_xdpsq *sq, int numa)
926 struct mlx5e_xdp_info_fifo *xdpi_fifo = &sq->db.xdpi_fifo;
927 int wq_sz = mlx5_wq_cyc_get_size(&sq->wq);
928 int dsegs_per_wq = wq_sz * MLX5_SEND_WQEBB_NUM_DS;
930 xdpi_fifo->xi = kvzalloc_node(sizeof(*xdpi_fifo->xi) * dsegs_per_wq,
935 xdpi_fifo->pc = &sq->xdpi_fifo_pc;
936 xdpi_fifo->cc = &sq->xdpi_fifo_cc;
937 xdpi_fifo->mask = dsegs_per_wq - 1;
942 static int mlx5e_alloc_xdpsq_db(struct mlx5e_xdpsq *sq, int numa)
944 int wq_sz = mlx5_wq_cyc_get_size(&sq->wq);
947 sq->db.wqe_info = kvzalloc_node(sizeof(*sq->db.wqe_info) * wq_sz,
949 if (!sq->db.wqe_info)
952 err = mlx5e_alloc_xdpsq_fifo(sq, numa);
954 mlx5e_free_xdpsq_db(sq);
961 static int mlx5e_alloc_xdpsq(struct mlx5e_channel *c,
962 struct mlx5e_params *params,
963 struct xsk_buff_pool *xsk_pool,
964 struct mlx5e_sq_param *param,
965 struct mlx5e_xdpsq *sq,
968 void *sqc_wq = MLX5_ADDR_OF(sqc, param->sqc, wq);
969 struct mlx5_core_dev *mdev = c->mdev;
970 struct mlx5_wq_cyc *wq = &sq->wq;
974 sq->mkey_be = c->mkey_be;
976 sq->uar_map = mdev->mlx5e_res.hw_objs.bfreg.map;
977 sq->min_inline_mode = params->tx_min_inline_mode;
978 sq->hw_mtu = MLX5E_SW2HW_MTU(params, params->sw_mtu);
979 sq->xsk_pool = xsk_pool;
981 sq->stats = sq->xsk_pool ?
982 &c->priv->channel_stats[c->ix].xsksq :
984 &c->priv->channel_stats[c->ix].xdpsq :
985 &c->priv->channel_stats[c->ix].rq_xdpsq;
987 param->wq.db_numa_node = cpu_to_node(c->cpu);
988 err = mlx5_wq_cyc_create(mdev, ¶m->wq, sqc_wq, wq, &sq->wq_ctrl);
991 wq->db = &wq->db[MLX5_SND_DBR];
993 err = mlx5e_alloc_xdpsq_db(sq, cpu_to_node(c->cpu));
995 goto err_sq_wq_destroy;
1000 mlx5_wq_destroy(&sq->wq_ctrl);
1005 static void mlx5e_free_xdpsq(struct mlx5e_xdpsq *sq)
1007 mlx5e_free_xdpsq_db(sq);
1008 mlx5_wq_destroy(&sq->wq_ctrl);
1011 static void mlx5e_free_icosq_db(struct mlx5e_icosq *sq)
1013 kvfree(sq->db.wqe_info);
1016 static int mlx5e_alloc_icosq_db(struct mlx5e_icosq *sq, int numa)
1018 int wq_sz = mlx5_wq_cyc_get_size(&sq->wq);
1021 size = array_size(wq_sz, sizeof(*sq->db.wqe_info));
1022 sq->db.wqe_info = kvzalloc_node(size, GFP_KERNEL, numa);
1023 if (!sq->db.wqe_info)
1029 static void mlx5e_icosq_err_cqe_work(struct work_struct *recover_work)
1031 struct mlx5e_icosq *sq = container_of(recover_work, struct mlx5e_icosq,
1034 mlx5e_reporter_icosq_cqe_err(sq);
1037 static int mlx5e_alloc_icosq(struct mlx5e_channel *c,
1038 struct mlx5e_sq_param *param,
1039 struct mlx5e_icosq *sq)
1041 void *sqc_wq = MLX5_ADDR_OF(sqc, param->sqc, wq);
1042 struct mlx5_core_dev *mdev = c->mdev;
1043 struct mlx5_wq_cyc *wq = &sq->wq;
1047 sq->uar_map = mdev->mlx5e_res.hw_objs.bfreg.map;
1048 sq->reserved_room = param->stop_room;
1050 param->wq.db_numa_node = cpu_to_node(c->cpu);
1051 err = mlx5_wq_cyc_create(mdev, ¶m->wq, sqc_wq, wq, &sq->wq_ctrl);
1054 wq->db = &wq->db[MLX5_SND_DBR];
1056 err = mlx5e_alloc_icosq_db(sq, cpu_to_node(c->cpu));
1058 goto err_sq_wq_destroy;
1060 INIT_WORK(&sq->recover_work, mlx5e_icosq_err_cqe_work);
1065 mlx5_wq_destroy(&sq->wq_ctrl);
1070 static void mlx5e_free_icosq(struct mlx5e_icosq *sq)
1072 mlx5e_free_icosq_db(sq);
1073 mlx5_wq_destroy(&sq->wq_ctrl);
1076 void mlx5e_free_txqsq_db(struct mlx5e_txqsq *sq)
1078 kvfree(sq->db.wqe_info);
1079 kvfree(sq->db.skb_fifo.fifo);
1080 kvfree(sq->db.dma_fifo);
1083 int mlx5e_alloc_txqsq_db(struct mlx5e_txqsq *sq, int numa)
1085 int wq_sz = mlx5_wq_cyc_get_size(&sq->wq);
1086 int df_sz = wq_sz * MLX5_SEND_WQEBB_NUM_DS;
1088 sq->db.dma_fifo = kvzalloc_node(array_size(df_sz,
1089 sizeof(*sq->db.dma_fifo)),
1091 sq->db.skb_fifo.fifo = kvzalloc_node(array_size(df_sz,
1092 sizeof(*sq->db.skb_fifo.fifo)),
1094 sq->db.wqe_info = kvzalloc_node(array_size(wq_sz,
1095 sizeof(*sq->db.wqe_info)),
1097 if (!sq->db.dma_fifo || !sq->db.skb_fifo.fifo || !sq->db.wqe_info) {
1098 mlx5e_free_txqsq_db(sq);
1102 sq->dma_fifo_mask = df_sz - 1;
1104 sq->db.skb_fifo.pc = &sq->skb_fifo_pc;
1105 sq->db.skb_fifo.cc = &sq->skb_fifo_cc;
1106 sq->db.skb_fifo.mask = df_sz - 1;
1111 static int mlx5e_alloc_txqsq(struct mlx5e_channel *c,
1113 struct mlx5e_params *params,
1114 struct mlx5e_sq_param *param,
1115 struct mlx5e_txqsq *sq,
1118 void *sqc_wq = MLX5_ADDR_OF(sqc, param->sqc, wq);
1119 struct mlx5_core_dev *mdev = c->mdev;
1120 struct mlx5_wq_cyc *wq = &sq->wq;
1124 sq->tstamp = c->tstamp;
1125 sq->clock = &mdev->clock;
1126 sq->mkey_be = c->mkey_be;
1127 sq->netdev = c->netdev;
1131 sq->txq_ix = txq_ix;
1132 sq->uar_map = mdev->mlx5e_res.hw_objs.bfreg.map;
1133 sq->min_inline_mode = params->tx_min_inline_mode;
1134 sq->hw_mtu = MLX5E_SW2HW_MTU(params, params->sw_mtu);
1135 INIT_WORK(&sq->recover_work, mlx5e_tx_err_cqe_work);
1136 if (!MLX5_CAP_ETH(mdev, wqe_vlan_insert))
1137 set_bit(MLX5E_SQ_STATE_VLAN_NEED_L2_INLINE, &sq->state);
1138 if (MLX5_IPSEC_DEV(c->priv->mdev))
1139 set_bit(MLX5E_SQ_STATE_IPSEC, &sq->state);
1141 set_bit(MLX5E_SQ_STATE_MPWQE, &sq->state);
1142 sq->stop_room = param->stop_room;
1143 sq->ptp_cyc2time = mlx5_sq_ts_translator(mdev);
1145 param->wq.db_numa_node = cpu_to_node(c->cpu);
1146 err = mlx5_wq_cyc_create(mdev, ¶m->wq, sqc_wq, wq, &sq->wq_ctrl);
1149 wq->db = &wq->db[MLX5_SND_DBR];
1151 err = mlx5e_alloc_txqsq_db(sq, cpu_to_node(c->cpu));
1153 goto err_sq_wq_destroy;
1155 INIT_WORK(&sq->dim.work, mlx5e_tx_dim_work);
1156 sq->dim.mode = params->tx_cq_moderation.cq_period_mode;
1161 mlx5_wq_destroy(&sq->wq_ctrl);
1166 void mlx5e_free_txqsq(struct mlx5e_txqsq *sq)
1168 mlx5e_free_txqsq_db(sq);
1169 mlx5_wq_destroy(&sq->wq_ctrl);
1172 static int mlx5e_create_sq(struct mlx5_core_dev *mdev,
1173 struct mlx5e_sq_param *param,
1174 struct mlx5e_create_sq_param *csp,
1184 inlen = MLX5_ST_SZ_BYTES(create_sq_in) +
1185 sizeof(u64) * csp->wq_ctrl->buf.npages;
1186 in = kvzalloc(inlen, GFP_KERNEL);
1190 ts_format = mlx5_is_real_time_sq(mdev) ?
1191 MLX5_SQC_TIMESTAMP_FORMAT_REAL_TIME :
1192 MLX5_SQC_TIMESTAMP_FORMAT_FREE_RUNNING;
1193 sqc = MLX5_ADDR_OF(create_sq_in, in, ctx);
1194 wq = MLX5_ADDR_OF(sqc, sqc, wq);
1196 memcpy(sqc, param->sqc, sizeof(param->sqc));
1197 MLX5_SET(sqc, sqc, tis_lst_sz, csp->tis_lst_sz);
1198 MLX5_SET(sqc, sqc, tis_num_0, csp->tisn);
1199 MLX5_SET(sqc, sqc, cqn, csp->cqn);
1200 MLX5_SET(sqc, sqc, ts_cqe_to_dest_cqn, csp->ts_cqe_to_dest_cqn);
1201 MLX5_SET(sqc, sqc, ts_format, ts_format);
1204 if (MLX5_CAP_ETH(mdev, wqe_inline_mode) == MLX5_CAP_INLINE_MODE_VPORT_CONTEXT)
1205 MLX5_SET(sqc, sqc, min_wqe_inline_mode, csp->min_inline_mode);
1207 MLX5_SET(sqc, sqc, state, MLX5_SQC_STATE_RST);
1208 MLX5_SET(sqc, sqc, flush_in_error_en, 1);
1210 MLX5_SET(wq, wq, wq_type, MLX5_WQ_TYPE_CYCLIC);
1211 MLX5_SET(wq, wq, uar_page, mdev->mlx5e_res.hw_objs.bfreg.index);
1212 MLX5_SET(wq, wq, log_wq_pg_sz, csp->wq_ctrl->buf.page_shift -
1213 MLX5_ADAPTER_PAGE_SHIFT);
1214 MLX5_SET64(wq, wq, dbr_addr, csp->wq_ctrl->db.dma);
1216 mlx5_fill_page_frag_array(&csp->wq_ctrl->buf,
1217 (__be64 *)MLX5_ADDR_OF(wq, wq, pas));
1219 err = mlx5_core_create_sq(mdev, in, inlen, sqn);
1226 int mlx5e_modify_sq(struct mlx5_core_dev *mdev, u32 sqn,
1227 struct mlx5e_modify_sq_param *p)
1235 inlen = MLX5_ST_SZ_BYTES(modify_sq_in);
1236 in = kvzalloc(inlen, GFP_KERNEL);
1240 sqc = MLX5_ADDR_OF(modify_sq_in, in, ctx);
1242 MLX5_SET(modify_sq_in, in, sq_state, p->curr_state);
1243 MLX5_SET(sqc, sqc, state, p->next_state);
1244 if (p->rl_update && p->next_state == MLX5_SQC_STATE_RDY) {
1246 MLX5_SET(sqc, sqc, packet_pacing_rate_limit_index, p->rl_index);
1248 if (p->qos_update && p->next_state == MLX5_SQC_STATE_RDY) {
1250 MLX5_SET(sqc, sqc, qos_queue_group_id, p->qos_queue_group_id);
1252 MLX5_SET64(modify_sq_in, in, modify_bitmask, bitmask);
1254 err = mlx5_core_modify_sq(mdev, sqn, in);
1261 static void mlx5e_destroy_sq(struct mlx5_core_dev *mdev, u32 sqn)
1263 mlx5_core_destroy_sq(mdev, sqn);
1266 int mlx5e_create_sq_rdy(struct mlx5_core_dev *mdev,
1267 struct mlx5e_sq_param *param,
1268 struct mlx5e_create_sq_param *csp,
1269 u16 qos_queue_group_id,
1272 struct mlx5e_modify_sq_param msp = {0};
1275 err = mlx5e_create_sq(mdev, param, csp, sqn);
1279 msp.curr_state = MLX5_SQC_STATE_RST;
1280 msp.next_state = MLX5_SQC_STATE_RDY;
1281 if (qos_queue_group_id) {
1282 msp.qos_update = true;
1283 msp.qos_queue_group_id = qos_queue_group_id;
1285 err = mlx5e_modify_sq(mdev, *sqn, &msp);
1287 mlx5e_destroy_sq(mdev, *sqn);
1292 static int mlx5e_set_sq_maxrate(struct net_device *dev,
1293 struct mlx5e_txqsq *sq, u32 rate);
1295 int mlx5e_open_txqsq(struct mlx5e_channel *c, u32 tisn, int txq_ix,
1296 struct mlx5e_params *params, struct mlx5e_sq_param *param,
1297 struct mlx5e_txqsq *sq, int tc, u16 qos_queue_group_id, u16 qos_qid)
1299 struct mlx5e_create_sq_param csp = {};
1303 err = mlx5e_alloc_txqsq(c, txq_ix, params, param, sq, tc);
1307 if (qos_queue_group_id)
1308 sq->stats = c->priv->htb.qos_sq_stats[qos_qid];
1310 sq->stats = &c->priv->channel_stats[c->ix].sq[tc];
1314 csp.cqn = sq->cq.mcq.cqn;
1315 csp.wq_ctrl = &sq->wq_ctrl;
1316 csp.min_inline_mode = sq->min_inline_mode;
1317 err = mlx5e_create_sq_rdy(c->mdev, param, &csp, qos_queue_group_id, &sq->sqn);
1319 goto err_free_txqsq;
1321 tx_rate = c->priv->tx_rates[sq->txq_ix];
1323 mlx5e_set_sq_maxrate(c->netdev, sq, tx_rate);
1325 if (params->tx_dim_enabled)
1326 sq->state |= BIT(MLX5E_SQ_STATE_AM);
1331 mlx5e_free_txqsq(sq);
1336 void mlx5e_activate_txqsq(struct mlx5e_txqsq *sq)
1338 sq->txq = netdev_get_tx_queue(sq->netdev, sq->txq_ix);
1339 set_bit(MLX5E_SQ_STATE_ENABLED, &sq->state);
1340 netdev_tx_reset_queue(sq->txq);
1341 netif_tx_start_queue(sq->txq);
1344 void mlx5e_tx_disable_queue(struct netdev_queue *txq)
1346 __netif_tx_lock_bh(txq);
1347 netif_tx_stop_queue(txq);
1348 __netif_tx_unlock_bh(txq);
1351 void mlx5e_deactivate_txqsq(struct mlx5e_txqsq *sq)
1353 struct mlx5_wq_cyc *wq = &sq->wq;
1355 clear_bit(MLX5E_SQ_STATE_ENABLED, &sq->state);
1356 synchronize_net(); /* Sync with NAPI to prevent netif_tx_wake_queue. */
1358 mlx5e_tx_disable_queue(sq->txq);
1360 /* last doorbell out, godspeed .. */
1361 if (mlx5e_wqc_has_room_for(wq, sq->cc, sq->pc, 1)) {
1362 u16 pi = mlx5_wq_cyc_ctr2ix(wq, sq->pc);
1363 struct mlx5e_tx_wqe *nop;
1365 sq->db.wqe_info[pi] = (struct mlx5e_tx_wqe_info) {
1369 nop = mlx5e_post_nop(wq, sq->sqn, &sq->pc);
1370 mlx5e_notify_hw(wq, sq->pc, sq->uar_map, &nop->ctrl);
1374 void mlx5e_close_txqsq(struct mlx5e_txqsq *sq)
1376 struct mlx5_core_dev *mdev = sq->mdev;
1377 struct mlx5_rate_limit rl = {0};
1379 cancel_work_sync(&sq->dim.work);
1380 cancel_work_sync(&sq->recover_work);
1381 mlx5e_destroy_sq(mdev, sq->sqn);
1382 if (sq->rate_limit) {
1383 rl.rate = sq->rate_limit;
1384 mlx5_rl_remove_rate(mdev, &rl);
1386 mlx5e_free_txqsq_descs(sq);
1387 mlx5e_free_txqsq(sq);
1390 void mlx5e_tx_err_cqe_work(struct work_struct *recover_work)
1392 struct mlx5e_txqsq *sq = container_of(recover_work, struct mlx5e_txqsq,
1395 mlx5e_reporter_tx_err_cqe(sq);
1398 int mlx5e_open_icosq(struct mlx5e_channel *c, struct mlx5e_params *params,
1399 struct mlx5e_sq_param *param, struct mlx5e_icosq *sq)
1401 struct mlx5e_create_sq_param csp = {};
1404 err = mlx5e_alloc_icosq(c, param, sq);
1408 csp.cqn = sq->cq.mcq.cqn;
1409 csp.wq_ctrl = &sq->wq_ctrl;
1410 csp.min_inline_mode = params->tx_min_inline_mode;
1411 err = mlx5e_create_sq_rdy(c->mdev, param, &csp, 0, &sq->sqn);
1413 goto err_free_icosq;
1415 if (param->is_tls) {
1416 sq->ktls_resync = mlx5e_ktls_rx_resync_create_resp_list();
1417 if (IS_ERR(sq->ktls_resync)) {
1418 err = PTR_ERR(sq->ktls_resync);
1419 goto err_destroy_icosq;
1425 mlx5e_destroy_sq(c->mdev, sq->sqn);
1427 mlx5e_free_icosq(sq);
1432 void mlx5e_activate_icosq(struct mlx5e_icosq *icosq)
1434 set_bit(MLX5E_SQ_STATE_ENABLED, &icosq->state);
1437 void mlx5e_deactivate_icosq(struct mlx5e_icosq *icosq)
1439 clear_bit(MLX5E_SQ_STATE_ENABLED, &icosq->state);
1440 synchronize_net(); /* Sync with NAPI. */
1443 void mlx5e_close_icosq(struct mlx5e_icosq *sq)
1445 struct mlx5e_channel *c = sq->channel;
1447 if (sq->ktls_resync)
1448 mlx5e_ktls_rx_resync_destroy_resp_list(sq->ktls_resync);
1449 mlx5e_destroy_sq(c->mdev, sq->sqn);
1450 mlx5e_free_icosq_descs(sq);
1451 mlx5e_free_icosq(sq);
1454 int mlx5e_open_xdpsq(struct mlx5e_channel *c, struct mlx5e_params *params,
1455 struct mlx5e_sq_param *param, struct xsk_buff_pool *xsk_pool,
1456 struct mlx5e_xdpsq *sq, bool is_redirect)
1458 struct mlx5e_create_sq_param csp = {};
1461 err = mlx5e_alloc_xdpsq(c, params, xsk_pool, param, sq, is_redirect);
1466 csp.tisn = c->priv->tisn[c->lag_port][0]; /* tc = 0 */
1467 csp.cqn = sq->cq.mcq.cqn;
1468 csp.wq_ctrl = &sq->wq_ctrl;
1469 csp.min_inline_mode = sq->min_inline_mode;
1470 set_bit(MLX5E_SQ_STATE_ENABLED, &sq->state);
1471 err = mlx5e_create_sq_rdy(c->mdev, param, &csp, 0, &sq->sqn);
1473 goto err_free_xdpsq;
1475 mlx5e_set_xmit_fp(sq, param->is_mpw);
1477 if (!param->is_mpw) {
1478 unsigned int ds_cnt = MLX5E_XDP_TX_DS_COUNT;
1479 unsigned int inline_hdr_sz = 0;
1482 if (sq->min_inline_mode != MLX5_INLINE_MODE_NONE) {
1483 inline_hdr_sz = MLX5E_XDP_MIN_INLINE;
1487 /* Pre initialize fixed WQE fields */
1488 for (i = 0; i < mlx5_wq_cyc_get_size(&sq->wq); i++) {
1489 struct mlx5e_tx_wqe *wqe = mlx5_wq_cyc_get_wqe(&sq->wq, i);
1490 struct mlx5_wqe_ctrl_seg *cseg = &wqe->ctrl;
1491 struct mlx5_wqe_eth_seg *eseg = &wqe->eth;
1492 struct mlx5_wqe_data_seg *dseg;
1494 sq->db.wqe_info[i] = (struct mlx5e_xdp_wqe_info) {
1499 cseg->qpn_ds = cpu_to_be32((sq->sqn << 8) | ds_cnt);
1500 eseg->inline_hdr.sz = cpu_to_be16(inline_hdr_sz);
1502 dseg = (struct mlx5_wqe_data_seg *)cseg + (ds_cnt - 1);
1503 dseg->lkey = sq->mkey_be;
1510 clear_bit(MLX5E_SQ_STATE_ENABLED, &sq->state);
1511 mlx5e_free_xdpsq(sq);
1516 void mlx5e_close_xdpsq(struct mlx5e_xdpsq *sq)
1518 struct mlx5e_channel *c = sq->channel;
1520 clear_bit(MLX5E_SQ_STATE_ENABLED, &sq->state);
1521 synchronize_net(); /* Sync with NAPI. */
1523 mlx5e_destroy_sq(c->mdev, sq->sqn);
1524 mlx5e_free_xdpsq_descs(sq);
1525 mlx5e_free_xdpsq(sq);
1528 static int mlx5e_alloc_cq_common(struct mlx5e_priv *priv,
1529 struct mlx5e_cq_param *param,
1530 struct mlx5e_cq *cq)
1532 struct mlx5_core_dev *mdev = priv->mdev;
1533 struct mlx5_core_cq *mcq = &cq->mcq;
1539 err = mlx5_vector2eqn(mdev, param->eq_ix, &eqn_not_used, &irqn);
1543 err = mlx5_cqwq_create(mdev, ¶m->wq, param->cqc, &cq->wq,
1549 mcq->set_ci_db = cq->wq_ctrl.db.db;
1550 mcq->arm_db = cq->wq_ctrl.db.db + 1;
1551 *mcq->set_ci_db = 0;
1553 mcq->vector = param->eq_ix;
1554 mcq->comp = mlx5e_completion_event;
1555 mcq->event = mlx5e_cq_error_event;
1558 for (i = 0; i < mlx5_cqwq_get_size(&cq->wq); i++) {
1559 struct mlx5_cqe64 *cqe = mlx5_cqwq_get_wqe(&cq->wq, i);
1565 cq->netdev = priv->netdev;
1571 static int mlx5e_alloc_cq(struct mlx5e_priv *priv,
1572 struct mlx5e_cq_param *param,
1573 struct mlx5e_create_cq_param *ccp,
1574 struct mlx5e_cq *cq)
1578 param->wq.buf_numa_node = ccp->node;
1579 param->wq.db_numa_node = ccp->node;
1580 param->eq_ix = ccp->ix;
1582 err = mlx5e_alloc_cq_common(priv, param, cq);
1584 cq->napi = ccp->napi;
1585 cq->ch_stats = ccp->ch_stats;
1590 static void mlx5e_free_cq(struct mlx5e_cq *cq)
1592 mlx5_wq_destroy(&cq->wq_ctrl);
1595 static int mlx5e_create_cq(struct mlx5e_cq *cq, struct mlx5e_cq_param *param)
1597 u32 out[MLX5_ST_SZ_DW(create_cq_out)];
1598 struct mlx5_core_dev *mdev = cq->mdev;
1599 struct mlx5_core_cq *mcq = &cq->mcq;
1604 unsigned int irqn_not_used;
1608 err = mlx5_vector2eqn(mdev, param->eq_ix, &eqn, &irqn_not_used);
1612 inlen = MLX5_ST_SZ_BYTES(create_cq_in) +
1613 sizeof(u64) * cq->wq_ctrl.buf.npages;
1614 in = kvzalloc(inlen, GFP_KERNEL);
1618 cqc = MLX5_ADDR_OF(create_cq_in, in, cq_context);
1620 memcpy(cqc, param->cqc, sizeof(param->cqc));
1622 mlx5_fill_page_frag_array(&cq->wq_ctrl.buf,
1623 (__be64 *)MLX5_ADDR_OF(create_cq_in, in, pas));
1625 MLX5_SET(cqc, cqc, cq_period_mode, param->cq_period_mode);
1626 MLX5_SET(cqc, cqc, c_eqn, eqn);
1627 MLX5_SET(cqc, cqc, uar_page, mdev->priv.uar->index);
1628 MLX5_SET(cqc, cqc, log_page_size, cq->wq_ctrl.buf.page_shift -
1629 MLX5_ADAPTER_PAGE_SHIFT);
1630 MLX5_SET64(cqc, cqc, dbr_addr, cq->wq_ctrl.db.dma);
1632 err = mlx5_core_create_cq(mdev, mcq, in, inlen, out, sizeof(out));
1644 static void mlx5e_destroy_cq(struct mlx5e_cq *cq)
1646 mlx5_core_destroy_cq(cq->mdev, &cq->mcq);
1649 int mlx5e_open_cq(struct mlx5e_priv *priv, struct dim_cq_moder moder,
1650 struct mlx5e_cq_param *param, struct mlx5e_create_cq_param *ccp,
1651 struct mlx5e_cq *cq)
1653 struct mlx5_core_dev *mdev = priv->mdev;
1656 err = mlx5e_alloc_cq(priv, param, ccp, cq);
1660 err = mlx5e_create_cq(cq, param);
1664 if (MLX5_CAP_GEN(mdev, cq_moderation))
1665 mlx5_core_modify_cq_moderation(mdev, &cq->mcq, moder.usec, moder.pkts);
1674 void mlx5e_close_cq(struct mlx5e_cq *cq)
1676 mlx5e_destroy_cq(cq);
1680 static int mlx5e_open_tx_cqs(struct mlx5e_channel *c,
1681 struct mlx5e_params *params,
1682 struct mlx5e_create_cq_param *ccp,
1683 struct mlx5e_channel_param *cparam)
1688 for (tc = 0; tc < c->num_tc; tc++) {
1689 err = mlx5e_open_cq(c->priv, params->tx_cq_moderation, &cparam->txq_sq.cqp,
1690 ccp, &c->sq[tc].cq);
1692 goto err_close_tx_cqs;
1698 for (tc--; tc >= 0; tc--)
1699 mlx5e_close_cq(&c->sq[tc].cq);
1704 static void mlx5e_close_tx_cqs(struct mlx5e_channel *c)
1708 for (tc = 0; tc < c->num_tc; tc++)
1709 mlx5e_close_cq(&c->sq[tc].cq);
1712 static int mlx5e_open_sqs(struct mlx5e_channel *c,
1713 struct mlx5e_params *params,
1714 struct mlx5e_channel_param *cparam)
1718 for (tc = 0; tc < params->num_tc; tc++) {
1719 int txq_ix = c->ix + tc * params->num_channels;
1721 err = mlx5e_open_txqsq(c, c->priv->tisn[c->lag_port][tc], txq_ix,
1722 params, &cparam->txq_sq, &c->sq[tc], tc, 0, 0);
1730 for (tc--; tc >= 0; tc--)
1731 mlx5e_close_txqsq(&c->sq[tc]);
1736 static void mlx5e_close_sqs(struct mlx5e_channel *c)
1740 for (tc = 0; tc < c->num_tc; tc++)
1741 mlx5e_close_txqsq(&c->sq[tc]);
1744 static int mlx5e_set_sq_maxrate(struct net_device *dev,
1745 struct mlx5e_txqsq *sq, u32 rate)
1747 struct mlx5e_priv *priv = netdev_priv(dev);
1748 struct mlx5_core_dev *mdev = priv->mdev;
1749 struct mlx5e_modify_sq_param msp = {0};
1750 struct mlx5_rate_limit rl = {0};
1754 if (rate == sq->rate_limit)
1758 if (sq->rate_limit) {
1759 rl.rate = sq->rate_limit;
1760 /* remove current rl index to free space to next ones */
1761 mlx5_rl_remove_rate(mdev, &rl);
1768 err = mlx5_rl_add_rate(mdev, &rl_index, &rl);
1770 netdev_err(dev, "Failed configuring rate %u: %d\n",
1776 msp.curr_state = MLX5_SQC_STATE_RDY;
1777 msp.next_state = MLX5_SQC_STATE_RDY;
1778 msp.rl_index = rl_index;
1779 msp.rl_update = true;
1780 err = mlx5e_modify_sq(mdev, sq->sqn, &msp);
1782 netdev_err(dev, "Failed configuring rate %u: %d\n",
1784 /* remove the rate from the table */
1786 mlx5_rl_remove_rate(mdev, &rl);
1790 sq->rate_limit = rate;
1794 static int mlx5e_set_tx_maxrate(struct net_device *dev, int index, u32 rate)
1796 struct mlx5e_priv *priv = netdev_priv(dev);
1797 struct mlx5_core_dev *mdev = priv->mdev;
1798 struct mlx5e_txqsq *sq = priv->txq2sq[index];
1801 if (!mlx5_rl_is_supported(mdev)) {
1802 netdev_err(dev, "Rate limiting is not supported on this device\n");
1806 /* rate is given in Mb/sec, HW config is in Kb/sec */
1809 /* Check whether rate in valid range, 0 is always valid */
1810 if (rate && !mlx5_rl_is_in_range(mdev, rate)) {
1811 netdev_err(dev, "TX rate %u, is not in range\n", rate);
1815 mutex_lock(&priv->state_lock);
1816 if (test_bit(MLX5E_STATE_OPENED, &priv->state))
1817 err = mlx5e_set_sq_maxrate(dev, sq, rate);
1819 priv->tx_rates[index] = rate;
1820 mutex_unlock(&priv->state_lock);
1825 static int mlx5e_open_rxq_rq(struct mlx5e_channel *c, struct mlx5e_params *params,
1826 struct mlx5e_rq_param *rq_params)
1830 err = mlx5e_init_rxq_rq(c, params, &c->rq);
1834 return mlx5e_open_rq(params, rq_params, NULL, cpu_to_node(c->cpu), &c->rq);
1837 static int mlx5e_open_queues(struct mlx5e_channel *c,
1838 struct mlx5e_params *params,
1839 struct mlx5e_channel_param *cparam)
1841 struct dim_cq_moder icocq_moder = {0, 0};
1842 struct mlx5e_create_cq_param ccp;
1845 mlx5e_build_create_cq_param(&ccp, c);
1847 err = mlx5e_open_cq(c->priv, icocq_moder, &cparam->async_icosq.cqp, &ccp,
1848 &c->async_icosq.cq);
1852 err = mlx5e_open_cq(c->priv, icocq_moder, &cparam->icosq.cqp, &ccp,
1855 goto err_close_async_icosq_cq;
1857 err = mlx5e_open_tx_cqs(c, params, &ccp, cparam);
1859 goto err_close_icosq_cq;
1861 err = mlx5e_open_cq(c->priv, params->tx_cq_moderation, &cparam->xdp_sq.cqp, &ccp,
1864 goto err_close_tx_cqs;
1866 err = mlx5e_open_cq(c->priv, params->rx_cq_moderation, &cparam->rq.cqp, &ccp,
1869 goto err_close_xdp_tx_cqs;
1871 err = c->xdp ? mlx5e_open_cq(c->priv, params->tx_cq_moderation, &cparam->xdp_sq.cqp,
1872 &ccp, &c->rq_xdpsq.cq) : 0;
1874 goto err_close_rx_cq;
1876 spin_lock_init(&c->async_icosq_lock);
1878 err = mlx5e_open_icosq(c, params, &cparam->async_icosq, &c->async_icosq);
1880 goto err_close_xdpsq_cq;
1882 err = mlx5e_open_icosq(c, params, &cparam->icosq, &c->icosq);
1884 goto err_close_async_icosq;
1886 err = mlx5e_open_sqs(c, params, cparam);
1888 goto err_close_icosq;
1891 err = mlx5e_open_xdpsq(c, params, &cparam->xdp_sq, NULL,
1892 &c->rq_xdpsq, false);
1897 err = mlx5e_open_rxq_rq(c, params, &cparam->rq);
1899 goto err_close_xdp_sq;
1901 err = mlx5e_open_xdpsq(c, params, &cparam->xdp_sq, NULL, &c->xdpsq, true);
1908 mlx5e_close_rq(&c->rq);
1912 mlx5e_close_xdpsq(&c->rq_xdpsq);
1918 mlx5e_close_icosq(&c->icosq);
1920 err_close_async_icosq:
1921 mlx5e_close_icosq(&c->async_icosq);
1925 mlx5e_close_cq(&c->rq_xdpsq.cq);
1928 mlx5e_close_cq(&c->rq.cq);
1930 err_close_xdp_tx_cqs:
1931 mlx5e_close_cq(&c->xdpsq.cq);
1934 mlx5e_close_tx_cqs(c);
1937 mlx5e_close_cq(&c->icosq.cq);
1939 err_close_async_icosq_cq:
1940 mlx5e_close_cq(&c->async_icosq.cq);
1945 static void mlx5e_close_queues(struct mlx5e_channel *c)
1947 mlx5e_close_xdpsq(&c->xdpsq);
1948 mlx5e_close_rq(&c->rq);
1950 mlx5e_close_xdpsq(&c->rq_xdpsq);
1952 mlx5e_close_icosq(&c->icosq);
1953 mlx5e_close_icosq(&c->async_icosq);
1955 mlx5e_close_cq(&c->rq_xdpsq.cq);
1956 mlx5e_close_cq(&c->rq.cq);
1957 mlx5e_close_cq(&c->xdpsq.cq);
1958 mlx5e_close_tx_cqs(c);
1959 mlx5e_close_cq(&c->icosq.cq);
1960 mlx5e_close_cq(&c->async_icosq.cq);
1963 static u8 mlx5e_enumerate_lag_port(struct mlx5_core_dev *mdev, int ix)
1965 u16 port_aff_bias = mlx5_core_is_pf(mdev) ? 0 : MLX5_CAP_GEN(mdev, vhca_id);
1967 return (ix + port_aff_bias) % mlx5e_get_num_lag_ports(mdev);
1970 static int mlx5e_open_channel(struct mlx5e_priv *priv, int ix,
1971 struct mlx5e_params *params,
1972 struct mlx5e_channel_param *cparam,
1973 struct xsk_buff_pool *xsk_pool,
1974 struct mlx5e_channel **cp)
1976 int cpu = cpumask_first(mlx5_comp_irq_get_affinity_mask(priv->mdev, ix));
1977 struct net_device *netdev = priv->netdev;
1978 struct mlx5e_xsk_param xsk;
1979 struct mlx5e_channel *c;
1984 err = mlx5_vector2eqn(priv->mdev, ix, &eqn, &irq);
1988 c = kvzalloc_node(sizeof(*c), GFP_KERNEL, cpu_to_node(cpu));
1993 c->mdev = priv->mdev;
1994 c->tstamp = &priv->tstamp;
1997 c->pdev = mlx5_core_dma_dev(priv->mdev);
1998 c->netdev = priv->netdev;
1999 c->mkey_be = cpu_to_be32(priv->mdev->mlx5e_res.hw_objs.mkey.key);
2000 c->num_tc = params->num_tc;
2001 c->xdp = !!params->xdp_prog;
2002 c->stats = &priv->channel_stats[ix].ch;
2003 c->aff_mask = irq_get_effective_affinity_mask(irq);
2004 c->lag_port = mlx5e_enumerate_lag_port(priv->mdev, ix);
2006 netif_napi_add(netdev, &c->napi, mlx5e_napi_poll, 64);
2008 err = mlx5e_open_queues(c, params, cparam);
2013 mlx5e_build_xsk_param(xsk_pool, &xsk);
2014 err = mlx5e_open_xsk(priv, params, &xsk, xsk_pool, c);
2016 goto err_close_queues;
2024 mlx5e_close_queues(c);
2027 netif_napi_del(&c->napi);
2034 static void mlx5e_activate_channel(struct mlx5e_channel *c)
2038 napi_enable(&c->napi);
2040 for (tc = 0; tc < c->num_tc; tc++)
2041 mlx5e_activate_txqsq(&c->sq[tc]);
2042 mlx5e_activate_icosq(&c->icosq);
2043 mlx5e_activate_icosq(&c->async_icosq);
2044 mlx5e_activate_rq(&c->rq);
2046 if (test_bit(MLX5E_CHANNEL_STATE_XSK, c->state))
2047 mlx5e_activate_xsk(c);
2050 static void mlx5e_deactivate_channel(struct mlx5e_channel *c)
2054 if (test_bit(MLX5E_CHANNEL_STATE_XSK, c->state))
2055 mlx5e_deactivate_xsk(c);
2057 mlx5e_deactivate_rq(&c->rq);
2058 mlx5e_deactivate_icosq(&c->async_icosq);
2059 mlx5e_deactivate_icosq(&c->icosq);
2060 for (tc = 0; tc < c->num_tc; tc++)
2061 mlx5e_deactivate_txqsq(&c->sq[tc]);
2062 mlx5e_qos_deactivate_queues(c);
2064 napi_disable(&c->napi);
2067 static void mlx5e_close_channel(struct mlx5e_channel *c)
2069 if (test_bit(MLX5E_CHANNEL_STATE_XSK, c->state))
2071 mlx5e_close_queues(c);
2072 mlx5e_qos_close_queues(c);
2073 netif_napi_del(&c->napi);
2078 int mlx5e_open_channels(struct mlx5e_priv *priv,
2079 struct mlx5e_channels *chs)
2081 struct mlx5e_channel_param *cparam;
2085 chs->num = chs->params.num_channels;
2087 chs->c = kcalloc(chs->num, sizeof(struct mlx5e_channel *), GFP_KERNEL);
2088 cparam = kvzalloc(sizeof(struct mlx5e_channel_param), GFP_KERNEL);
2089 if (!chs->c || !cparam)
2092 err = mlx5e_build_channel_param(priv->mdev, &chs->params, priv->q_counter, cparam);
2096 for (i = 0; i < chs->num; i++) {
2097 struct xsk_buff_pool *xsk_pool = NULL;
2099 if (chs->params.xdp_prog)
2100 xsk_pool = mlx5e_xsk_get_pool(&chs->params, chs->params.xsk, i);
2102 err = mlx5e_open_channel(priv, i, &chs->params, cparam, xsk_pool, &chs->c[i]);
2104 goto err_close_channels;
2107 if (MLX5E_GET_PFLAG(&chs->params, MLX5E_PFLAG_TX_PORT_TS) || chs->params.ptp_rx) {
2108 err = mlx5e_ptp_open(priv, &chs->params, chs->c[0]->lag_port, &chs->ptp);
2110 goto err_close_channels;
2113 err = mlx5e_qos_open_queues(priv, chs);
2117 mlx5e_health_channels_update(priv);
2123 mlx5e_ptp_close(chs->ptp);
2126 for (i--; i >= 0; i--)
2127 mlx5e_close_channel(chs->c[i]);
2136 static void mlx5e_activate_channels(struct mlx5e_channels *chs)
2140 for (i = 0; i < chs->num; i++)
2141 mlx5e_activate_channel(chs->c[i]);
2144 mlx5e_ptp_activate_channel(chs->ptp);
2147 #define MLX5E_RQ_WQES_TIMEOUT 20000 /* msecs */
2149 static int mlx5e_wait_channels_min_rx_wqes(struct mlx5e_channels *chs)
2154 for (i = 0; i < chs->num; i++) {
2155 int timeout = err ? 0 : MLX5E_RQ_WQES_TIMEOUT;
2157 err |= mlx5e_wait_for_min_rx_wqes(&chs->c[i]->rq, timeout);
2159 /* Don't wait on the XSK RQ, because the newer xdpsock sample
2160 * doesn't provide any Fill Ring entries at the setup stage.
2164 return err ? -ETIMEDOUT : 0;
2167 static void mlx5e_deactivate_channels(struct mlx5e_channels *chs)
2172 mlx5e_ptp_deactivate_channel(chs->ptp);
2174 for (i = 0; i < chs->num; i++)
2175 mlx5e_deactivate_channel(chs->c[i]);
2178 void mlx5e_close_channels(struct mlx5e_channels *chs)
2183 mlx5e_ptp_close(chs->ptp);
2186 for (i = 0; i < chs->num; i++)
2187 mlx5e_close_channel(chs->c[i]);
2194 mlx5e_create_rqt(struct mlx5e_priv *priv, int sz, struct mlx5e_rqt *rqt)
2196 struct mlx5_core_dev *mdev = priv->mdev;
2203 inlen = MLX5_ST_SZ_BYTES(create_rqt_in) + sizeof(u32) * sz;
2204 in = kvzalloc(inlen, GFP_KERNEL);
2208 rqtc = MLX5_ADDR_OF(create_rqt_in, in, rqt_context);
2210 MLX5_SET(rqtc, rqtc, rqt_actual_size, sz);
2211 MLX5_SET(rqtc, rqtc, rqt_max_size, sz);
2213 for (i = 0; i < sz; i++)
2214 MLX5_SET(rqtc, rqtc, rq_num[i], priv->drop_rq.rqn);
2216 err = mlx5_core_create_rqt(mdev, in, inlen, &rqt->rqtn);
2218 rqt->enabled = true;
2224 void mlx5e_destroy_rqt(struct mlx5e_priv *priv, struct mlx5e_rqt *rqt)
2226 rqt->enabled = false;
2227 mlx5_core_destroy_rqt(priv->mdev, rqt->rqtn);
2230 int mlx5e_create_indirect_rqt(struct mlx5e_priv *priv)
2232 struct mlx5e_rqt *rqt = &priv->indir_rqt;
2235 err = mlx5e_create_rqt(priv, MLX5E_INDIR_RQT_SIZE, rqt);
2237 mlx5_core_warn(priv->mdev, "create indirect rqts failed, %d\n", err);
2241 int mlx5e_create_direct_rqts(struct mlx5e_priv *priv, struct mlx5e_tir *tirs, int n)
2246 for (ix = 0; ix < n; ix++) {
2247 err = mlx5e_create_rqt(priv, 1 /*size */, &tirs[ix].rqt);
2249 goto err_destroy_rqts;
2255 mlx5_core_warn(priv->mdev, "create rqts failed, %d\n", err);
2256 for (ix--; ix >= 0; ix--)
2257 mlx5e_destroy_rqt(priv, &tirs[ix].rqt);
2262 void mlx5e_destroy_direct_rqts(struct mlx5e_priv *priv, struct mlx5e_tir *tirs, int n)
2266 for (i = 0; i < n; i++)
2267 mlx5e_destroy_rqt(priv, &tirs[i].rqt);
2270 static int mlx5e_rx_hash_fn(int hfunc)
2272 return (hfunc == ETH_RSS_HASH_TOP) ?
2273 MLX5_RX_HASH_FN_TOEPLITZ :
2274 MLX5_RX_HASH_FN_INVERTED_XOR8;
2277 int mlx5e_bits_invert(unsigned long a, int size)
2282 for (i = 0; i < size; i++)
2283 inv |= (test_bit(size - i - 1, &a) ? 1 : 0) << i;
2288 static void mlx5e_fill_rqt_rqns(struct mlx5e_priv *priv, int sz,
2289 struct mlx5e_redirect_rqt_param rrp, void *rqtc)
2293 for (i = 0; i < sz; i++) {
2299 if (rrp.rss.hfunc == ETH_RSS_HASH_XOR)
2300 ix = mlx5e_bits_invert(i, ilog2(sz));
2302 ix = priv->rss_params.indirection_rqt[ix];
2303 rqn = rrp.rss.channels->c[ix]->rq.rqn;
2307 MLX5_SET(rqtc, rqtc, rq_num[i], rqn);
2311 int mlx5e_redirect_rqt(struct mlx5e_priv *priv, u32 rqtn, int sz,
2312 struct mlx5e_redirect_rqt_param rrp)
2314 struct mlx5_core_dev *mdev = priv->mdev;
2320 inlen = MLX5_ST_SZ_BYTES(modify_rqt_in) + sizeof(u32) * sz;
2321 in = kvzalloc(inlen, GFP_KERNEL);
2325 rqtc = MLX5_ADDR_OF(modify_rqt_in, in, ctx);
2327 MLX5_SET(rqtc, rqtc, rqt_actual_size, sz);
2328 MLX5_SET(modify_rqt_in, in, bitmask.rqn_list, 1);
2329 mlx5e_fill_rqt_rqns(priv, sz, rrp, rqtc);
2330 err = mlx5_core_modify_rqt(mdev, rqtn, in, inlen);
2336 static u32 mlx5e_get_direct_rqn(struct mlx5e_priv *priv, int ix,
2337 struct mlx5e_redirect_rqt_param rrp)
2342 if (ix >= rrp.rss.channels->num)
2343 return priv->drop_rq.rqn;
2345 return rrp.rss.channels->c[ix]->rq.rqn;
2348 static void mlx5e_redirect_rqts(struct mlx5e_priv *priv,
2349 struct mlx5e_redirect_rqt_param rrp,
2350 struct mlx5e_redirect_rqt_param *ptp_rrp)
2355 if (priv->indir_rqt.enabled) {
2357 rqtn = priv->indir_rqt.rqtn;
2358 mlx5e_redirect_rqt(priv, rqtn, MLX5E_INDIR_RQT_SIZE, rrp);
2361 for (ix = 0; ix < priv->max_nch; ix++) {
2362 struct mlx5e_redirect_rqt_param direct_rrp = {
2365 .rqn = mlx5e_get_direct_rqn(priv, ix, rrp)
2369 /* Direct RQ Tables */
2370 if (!priv->direct_tir[ix].rqt.enabled)
2373 rqtn = priv->direct_tir[ix].rqt.rqtn;
2374 mlx5e_redirect_rqt(priv, rqtn, 1, direct_rrp);
2377 rqtn = priv->ptp_tir.rqt.rqtn;
2378 mlx5e_redirect_rqt(priv, rqtn, 1, *ptp_rrp);
2382 static void mlx5e_redirect_rqts_to_channels(struct mlx5e_priv *priv,
2383 struct mlx5e_channels *chs)
2385 bool rx_ptp_support = priv->profile->rx_ptp_support;
2386 struct mlx5e_redirect_rqt_param *ptp_rrp_p = NULL;
2387 struct mlx5e_redirect_rqt_param rrp = {
2392 .hfunc = priv->rss_params.hfunc,
2396 struct mlx5e_redirect_rqt_param ptp_rrp;
2398 if (rx_ptp_support) {
2401 ptp_rrp.is_rss = false;
2402 ptp_rrp.rqn = mlx5e_ptp_get_rqn(priv->channels.ptp, &ptp_rqn) ?
2403 priv->drop_rq.rqn : ptp_rqn;
2404 ptp_rrp_p = &ptp_rrp;
2406 mlx5e_redirect_rqts(priv, rrp, ptp_rrp_p);
2409 static void mlx5e_redirect_rqts_to_drop(struct mlx5e_priv *priv)
2411 bool rx_ptp_support = priv->profile->rx_ptp_support;
2412 struct mlx5e_redirect_rqt_param drop_rrp = {
2415 .rqn = priv->drop_rq.rqn,
2419 mlx5e_redirect_rqts(priv, drop_rrp, rx_ptp_support ? &drop_rrp : NULL);
2422 static const struct mlx5e_tirc_config tirc_default_config[MLX5E_NUM_INDIR_TIRS] = {
2423 [MLX5E_TT_IPV4_TCP] = { .l3_prot_type = MLX5_L3_PROT_TYPE_IPV4,
2424 .l4_prot_type = MLX5_L4_PROT_TYPE_TCP,
2425 .rx_hash_fields = MLX5_HASH_IP_L4PORTS,
2427 [MLX5E_TT_IPV6_TCP] = { .l3_prot_type = MLX5_L3_PROT_TYPE_IPV6,
2428 .l4_prot_type = MLX5_L4_PROT_TYPE_TCP,
2429 .rx_hash_fields = MLX5_HASH_IP_L4PORTS,
2431 [MLX5E_TT_IPV4_UDP] = { .l3_prot_type = MLX5_L3_PROT_TYPE_IPV4,
2432 .l4_prot_type = MLX5_L4_PROT_TYPE_UDP,
2433 .rx_hash_fields = MLX5_HASH_IP_L4PORTS,
2435 [MLX5E_TT_IPV6_UDP] = { .l3_prot_type = MLX5_L3_PROT_TYPE_IPV6,
2436 .l4_prot_type = MLX5_L4_PROT_TYPE_UDP,
2437 .rx_hash_fields = MLX5_HASH_IP_L4PORTS,
2439 [MLX5E_TT_IPV4_IPSEC_AH] = { .l3_prot_type = MLX5_L3_PROT_TYPE_IPV4,
2441 .rx_hash_fields = MLX5_HASH_IP_IPSEC_SPI,
2443 [MLX5E_TT_IPV6_IPSEC_AH] = { .l3_prot_type = MLX5_L3_PROT_TYPE_IPV6,
2445 .rx_hash_fields = MLX5_HASH_IP_IPSEC_SPI,
2447 [MLX5E_TT_IPV4_IPSEC_ESP] = { .l3_prot_type = MLX5_L3_PROT_TYPE_IPV4,
2449 .rx_hash_fields = MLX5_HASH_IP_IPSEC_SPI,
2451 [MLX5E_TT_IPV6_IPSEC_ESP] = { .l3_prot_type = MLX5_L3_PROT_TYPE_IPV6,
2453 .rx_hash_fields = MLX5_HASH_IP_IPSEC_SPI,
2455 [MLX5E_TT_IPV4] = { .l3_prot_type = MLX5_L3_PROT_TYPE_IPV4,
2457 .rx_hash_fields = MLX5_HASH_IP,
2459 [MLX5E_TT_IPV6] = { .l3_prot_type = MLX5_L3_PROT_TYPE_IPV6,
2461 .rx_hash_fields = MLX5_HASH_IP,
2465 struct mlx5e_tirc_config mlx5e_tirc_get_default_config(enum mlx5e_traffic_types tt)
2467 return tirc_default_config[tt];
2470 static void mlx5e_build_tir_ctx_lro(struct mlx5e_params *params, void *tirc)
2472 if (!params->lro_en)
2475 #define ROUGH_MAX_L2_L3_HDR_SZ 256
2477 MLX5_SET(tirc, tirc, lro_enable_mask,
2478 MLX5_TIRC_LRO_ENABLE_MASK_IPV4_LRO |
2479 MLX5_TIRC_LRO_ENABLE_MASK_IPV6_LRO);
2480 MLX5_SET(tirc, tirc, lro_max_ip_payload_size,
2481 (MLX5E_PARAMS_DEFAULT_LRO_WQE_SZ - ROUGH_MAX_L2_L3_HDR_SZ) >> 8);
2482 MLX5_SET(tirc, tirc, lro_timeout_period_usecs, params->lro_timeout);
2485 void mlx5e_build_indir_tir_ctx_hash(struct mlx5e_rss_params *rss_params,
2486 const struct mlx5e_tirc_config *ttconfig,
2487 void *tirc, bool inner)
2489 void *hfso = inner ? MLX5_ADDR_OF(tirc, tirc, rx_hash_field_selector_inner) :
2490 MLX5_ADDR_OF(tirc, tirc, rx_hash_field_selector_outer);
2492 MLX5_SET(tirc, tirc, rx_hash_fn, mlx5e_rx_hash_fn(rss_params->hfunc));
2493 if (rss_params->hfunc == ETH_RSS_HASH_TOP) {
2494 void *rss_key = MLX5_ADDR_OF(tirc, tirc,
2495 rx_hash_toeplitz_key);
2496 size_t len = MLX5_FLD_SZ_BYTES(tirc,
2497 rx_hash_toeplitz_key);
2499 MLX5_SET(tirc, tirc, rx_hash_symmetric, 1);
2500 memcpy(rss_key, rss_params->toeplitz_hash_key, len);
2502 MLX5_SET(rx_hash_field_select, hfso, l3_prot_type,
2503 ttconfig->l3_prot_type);
2504 MLX5_SET(rx_hash_field_select, hfso, l4_prot_type,
2505 ttconfig->l4_prot_type);
2506 MLX5_SET(rx_hash_field_select, hfso, selected_fields,
2507 ttconfig->rx_hash_fields);
2510 static void mlx5e_update_rx_hash_fields(struct mlx5e_tirc_config *ttconfig,
2511 enum mlx5e_traffic_types tt,
2514 *ttconfig = tirc_default_config[tt];
2515 ttconfig->rx_hash_fields = rx_hash_fields;
2518 void mlx5e_modify_tirs_hash(struct mlx5e_priv *priv, void *in)
2520 void *tirc = MLX5_ADDR_OF(modify_tir_in, in, ctx);
2521 struct mlx5e_rss_params *rss = &priv->rss_params;
2522 struct mlx5_core_dev *mdev = priv->mdev;
2523 int ctxlen = MLX5_ST_SZ_BYTES(tirc);
2524 struct mlx5e_tirc_config ttconfig;
2527 MLX5_SET(modify_tir_in, in, bitmask.hash, 1);
2529 for (tt = 0; tt < MLX5E_NUM_INDIR_TIRS; tt++) {
2530 memset(tirc, 0, ctxlen);
2531 mlx5e_update_rx_hash_fields(&ttconfig, tt,
2532 rss->rx_hash_fields[tt]);
2533 mlx5e_build_indir_tir_ctx_hash(rss, &ttconfig, tirc, false);
2534 mlx5_core_modify_tir(mdev, priv->indir_tir[tt].tirn, in);
2537 /* Verify inner tirs resources allocated */
2538 if (!priv->inner_indir_tir[0].tirn)
2541 for (tt = 0; tt < MLX5E_NUM_INDIR_TIRS; tt++) {
2542 memset(tirc, 0, ctxlen);
2543 mlx5e_update_rx_hash_fields(&ttconfig, tt,
2544 rss->rx_hash_fields[tt]);
2545 mlx5e_build_indir_tir_ctx_hash(rss, &ttconfig, tirc, true);
2546 mlx5_core_modify_tir(mdev, priv->inner_indir_tir[tt].tirn, in);
2550 static int mlx5e_modify_tirs_lro(struct mlx5e_priv *priv)
2552 struct mlx5_core_dev *mdev = priv->mdev;
2561 inlen = MLX5_ST_SZ_BYTES(modify_tir_in);
2562 in = kvzalloc(inlen, GFP_KERNEL);
2566 MLX5_SET(modify_tir_in, in, bitmask.lro, 1);
2567 tirc = MLX5_ADDR_OF(modify_tir_in, in, ctx);
2569 mlx5e_build_tir_ctx_lro(&priv->channels.params, tirc);
2571 for (tt = 0; tt < MLX5E_NUM_INDIR_TIRS; tt++) {
2572 err = mlx5_core_modify_tir(mdev, priv->indir_tir[tt].tirn, in);
2577 for (ix = 0; ix < priv->max_nch; ix++) {
2578 err = mlx5_core_modify_tir(mdev, priv->direct_tir[ix].tirn, in);
2589 static MLX5E_DEFINE_PREACTIVATE_WRAPPER_CTX(mlx5e_modify_tirs_lro);
2591 static int mlx5e_set_mtu(struct mlx5_core_dev *mdev,
2592 struct mlx5e_params *params, u16 mtu)
2594 u16 hw_mtu = MLX5E_SW2HW_MTU(params, mtu);
2597 err = mlx5_set_port_mtu(mdev, hw_mtu, 1);
2601 /* Update vport context MTU */
2602 mlx5_modify_nic_vport_mtu(mdev, hw_mtu);
2606 static void mlx5e_query_mtu(struct mlx5_core_dev *mdev,
2607 struct mlx5e_params *params, u16 *mtu)
2612 err = mlx5_query_nic_vport_mtu(mdev, &hw_mtu);
2613 if (err || !hw_mtu) /* fallback to port oper mtu */
2614 mlx5_query_port_oper_mtu(mdev, &hw_mtu, 1);
2616 *mtu = MLX5E_HW2SW_MTU(params, hw_mtu);
2619 int mlx5e_set_dev_port_mtu(struct mlx5e_priv *priv)
2621 struct mlx5e_params *params = &priv->channels.params;
2622 struct net_device *netdev = priv->netdev;
2623 struct mlx5_core_dev *mdev = priv->mdev;
2627 err = mlx5e_set_mtu(mdev, params, params->sw_mtu);
2631 mlx5e_query_mtu(mdev, params, &mtu);
2632 if (mtu != params->sw_mtu)
2633 netdev_warn(netdev, "%s: VPort MTU %d is different than netdev mtu %d\n",
2634 __func__, mtu, params->sw_mtu);
2636 params->sw_mtu = mtu;
2640 MLX5E_DEFINE_PREACTIVATE_WRAPPER_CTX(mlx5e_set_dev_port_mtu);
2642 void mlx5e_set_netdev_mtu_boundaries(struct mlx5e_priv *priv)
2644 struct mlx5e_params *params = &priv->channels.params;
2645 struct net_device *netdev = priv->netdev;
2646 struct mlx5_core_dev *mdev = priv->mdev;
2649 /* MTU range: 68 - hw-specific max */
2650 netdev->min_mtu = ETH_MIN_MTU;
2652 mlx5_query_port_max_mtu(mdev, &max_mtu, 1);
2653 netdev->max_mtu = min_t(unsigned int, MLX5E_HW2SW_MTU(params, max_mtu),
2657 static void mlx5e_netdev_set_tcs(struct net_device *netdev, u16 nch, u8 ntc)
2661 netdev_reset_tc(netdev);
2666 netdev_set_num_tc(netdev, ntc);
2668 /* Map netdev TCs to offset 0
2669 * We have our own UP to TXQ mapping for QoS
2671 for (tc = 0; tc < ntc; tc++)
2672 netdev_set_tc_queue(netdev, tc, nch, 0);
2675 int mlx5e_update_tx_netdev_queues(struct mlx5e_priv *priv)
2677 int qos_queues, nch, ntc, num_txqs, err;
2679 qos_queues = mlx5e_qos_cur_leaf_nodes(priv);
2681 nch = priv->channels.params.num_channels;
2682 ntc = priv->channels.params.num_tc;
2683 num_txqs = nch * ntc + qos_queues;
2684 if (MLX5E_GET_PFLAG(&priv->channels.params, MLX5E_PFLAG_TX_PORT_TS))
2687 mlx5e_dbg(DRV, priv, "Setting num_txqs %d\n", num_txqs);
2688 err = netif_set_real_num_tx_queues(priv->netdev, num_txqs);
2690 netdev_warn(priv->netdev, "netif_set_real_num_tx_queues failed, %d\n", err);
2695 static int mlx5e_update_netdev_queues(struct mlx5e_priv *priv)
2697 struct net_device *netdev = priv->netdev;
2698 int old_num_txqs, old_ntc;
2699 int num_rxqs, nch, ntc;
2702 old_num_txqs = netdev->real_num_tx_queues;
2703 old_ntc = netdev->num_tc ? : 1;
2705 nch = priv->channels.params.num_channels;
2706 ntc = priv->channels.params.num_tc;
2707 num_rxqs = nch * priv->profile->rq_groups;
2709 mlx5e_netdev_set_tcs(netdev, nch, ntc);
2711 err = mlx5e_update_tx_netdev_queues(priv);
2714 err = netif_set_real_num_rx_queues(netdev, num_rxqs);
2716 netdev_warn(netdev, "netif_set_real_num_rx_queues failed, %d\n", err);
2723 /* netif_set_real_num_rx_queues could fail only when nch increased. Only
2724 * one of nch and ntc is changed in this function. That means, the call
2725 * to netif_set_real_num_tx_queues below should not fail, because it
2726 * decreases the number of TX queues.
2728 WARN_ON_ONCE(netif_set_real_num_tx_queues(netdev, old_num_txqs));
2731 mlx5e_netdev_set_tcs(netdev, old_num_txqs / old_ntc, old_ntc);
2735 static void mlx5e_set_default_xps_cpumasks(struct mlx5e_priv *priv,
2736 struct mlx5e_params *params)
2738 struct mlx5_core_dev *mdev = priv->mdev;
2739 int num_comp_vectors, ix, irq;
2741 num_comp_vectors = mlx5_comp_vectors_count(mdev);
2743 for (ix = 0; ix < params->num_channels; ix++) {
2744 cpumask_clear(priv->scratchpad.cpumask);
2746 for (irq = ix; irq < num_comp_vectors; irq += params->num_channels) {
2747 int cpu = cpumask_first(mlx5_comp_irq_get_affinity_mask(mdev, irq));
2749 cpumask_set_cpu(cpu, priv->scratchpad.cpumask);
2752 netif_set_xps_queue(priv->netdev, priv->scratchpad.cpumask, ix);
2756 int mlx5e_num_channels_changed(struct mlx5e_priv *priv)
2758 u16 count = priv->channels.params.num_channels;
2761 err = mlx5e_update_netdev_queues(priv);
2765 mlx5e_set_default_xps_cpumasks(priv, &priv->channels.params);
2767 if (!netif_is_rxfh_configured(priv->netdev))
2768 mlx5e_build_default_indir_rqt(priv->rss_params.indirection_rqt,
2769 MLX5E_INDIR_RQT_SIZE, count);
2774 MLX5E_DEFINE_PREACTIVATE_WRAPPER_CTX(mlx5e_num_channels_changed);
2776 static void mlx5e_build_txq_maps(struct mlx5e_priv *priv)
2778 int i, ch, tc, num_tc;
2780 ch = priv->channels.num;
2781 num_tc = priv->channels.params.num_tc;
2783 for (i = 0; i < ch; i++) {
2784 for (tc = 0; tc < num_tc; tc++) {
2785 struct mlx5e_channel *c = priv->channels.c[i];
2786 struct mlx5e_txqsq *sq = &c->sq[tc];
2788 priv->txq2sq[sq->txq_ix] = sq;
2789 priv->channel_tc2realtxq[i][tc] = i + tc * ch;
2793 if (!priv->channels.ptp)
2796 if (!test_bit(MLX5E_PTP_STATE_TX, priv->channels.ptp->state))
2799 for (tc = 0; tc < num_tc; tc++) {
2800 struct mlx5e_ptp *c = priv->channels.ptp;
2801 struct mlx5e_txqsq *sq = &c->ptpsq[tc].txqsq;
2803 priv->txq2sq[sq->txq_ix] = sq;
2804 priv->port_ptp_tc2realtxq[tc] = priv->num_tc_x_num_ch + tc;
2808 static void mlx5e_update_num_tc_x_num_ch(struct mlx5e_priv *priv)
2810 /* Sync with mlx5e_select_queue. */
2811 WRITE_ONCE(priv->num_tc_x_num_ch,
2812 priv->channels.params.num_tc * priv->channels.num);
2815 void mlx5e_activate_priv_channels(struct mlx5e_priv *priv)
2817 mlx5e_update_num_tc_x_num_ch(priv);
2818 mlx5e_build_txq_maps(priv);
2819 mlx5e_activate_channels(&priv->channels);
2820 mlx5e_qos_activate_queues(priv);
2821 mlx5e_xdp_tx_enable(priv);
2822 netif_tx_start_all_queues(priv->netdev);
2824 if (mlx5e_is_vport_rep(priv))
2825 mlx5e_add_sqs_fwd_rules(priv);
2827 mlx5e_wait_channels_min_rx_wqes(&priv->channels);
2828 mlx5e_redirect_rqts_to_channels(priv, &priv->channels);
2830 mlx5e_xsk_redirect_rqts_to_channels(priv, &priv->channels);
2833 void mlx5e_deactivate_priv_channels(struct mlx5e_priv *priv)
2835 mlx5e_xsk_redirect_rqts_to_drop(priv, &priv->channels);
2837 mlx5e_redirect_rqts_to_drop(priv);
2839 if (mlx5e_is_vport_rep(priv))
2840 mlx5e_remove_sqs_fwd_rules(priv);
2842 /* FIXME: This is a W/A only for tx timeout watch dog false alarm when
2843 * polling for inactive tx queues.
2845 netif_tx_stop_all_queues(priv->netdev);
2846 netif_tx_disable(priv->netdev);
2847 mlx5e_xdp_tx_disable(priv);
2848 mlx5e_deactivate_channels(&priv->channels);
2851 static int mlx5e_switch_priv_params(struct mlx5e_priv *priv,
2852 struct mlx5e_params *new_params,
2853 mlx5e_fp_preactivate preactivate,
2856 struct mlx5e_params old_params;
2858 old_params = priv->channels.params;
2859 priv->channels.params = *new_params;
2864 err = preactivate(priv, context);
2866 priv->channels.params = old_params;
2874 static int mlx5e_switch_priv_channels(struct mlx5e_priv *priv,
2875 struct mlx5e_channels *new_chs,
2876 mlx5e_fp_preactivate preactivate,
2879 struct net_device *netdev = priv->netdev;
2880 struct mlx5e_channels old_chs;
2884 carrier_ok = netif_carrier_ok(netdev);
2885 netif_carrier_off(netdev);
2887 mlx5e_deactivate_priv_channels(priv);
2889 old_chs = priv->channels;
2890 priv->channels = *new_chs;
2892 /* New channels are ready to roll, call the preactivate hook if needed
2893 * to modify HW settings or update kernel parameters.
2896 err = preactivate(priv, context);
2898 priv->channels = old_chs;
2903 mlx5e_close_channels(&old_chs);
2904 priv->profile->update_rx(priv);
2907 mlx5e_activate_priv_channels(priv);
2909 /* return carrier back if needed */
2911 netif_carrier_on(netdev);
2916 int mlx5e_safe_switch_params(struct mlx5e_priv *priv,
2917 struct mlx5e_params *params,
2918 mlx5e_fp_preactivate preactivate,
2919 void *context, bool reset)
2921 struct mlx5e_channels new_chs = {};
2924 reset &= test_bit(MLX5E_STATE_OPENED, &priv->state);
2926 return mlx5e_switch_priv_params(priv, params, preactivate, context);
2928 new_chs.params = *params;
2929 err = mlx5e_open_channels(priv, &new_chs);
2932 err = mlx5e_switch_priv_channels(priv, &new_chs, preactivate, context);
2934 mlx5e_close_channels(&new_chs);
2939 int mlx5e_safe_reopen_channels(struct mlx5e_priv *priv)
2941 return mlx5e_safe_switch_params(priv, &priv->channels.params, NULL, NULL, true);
2944 void mlx5e_timestamp_init(struct mlx5e_priv *priv)
2946 priv->tstamp.tx_type = HWTSTAMP_TX_OFF;
2947 priv->tstamp.rx_filter = HWTSTAMP_FILTER_NONE;
2950 static void mlx5e_modify_admin_state(struct mlx5_core_dev *mdev,
2951 enum mlx5_port_status state)
2953 struct mlx5_eswitch *esw = mdev->priv.eswitch;
2954 int vport_admin_state;
2956 mlx5_set_port_admin_status(mdev, state);
2958 if (mlx5_eswitch_mode(mdev) == MLX5_ESWITCH_OFFLOADS ||
2959 !MLX5_CAP_GEN(mdev, uplink_follow))
2962 if (state == MLX5_PORT_UP)
2963 vport_admin_state = MLX5_VPORT_ADMIN_STATE_AUTO;
2965 vport_admin_state = MLX5_VPORT_ADMIN_STATE_DOWN;
2967 mlx5_eswitch_set_vport_state(esw, MLX5_VPORT_UPLINK, vport_admin_state);
2970 int mlx5e_open_locked(struct net_device *netdev)
2972 struct mlx5e_priv *priv = netdev_priv(netdev);
2975 set_bit(MLX5E_STATE_OPENED, &priv->state);
2977 err = mlx5e_open_channels(priv, &priv->channels);
2979 goto err_clear_state_opened_flag;
2981 priv->profile->update_rx(priv);
2982 mlx5e_activate_priv_channels(priv);
2983 mlx5e_apply_traps(priv, true);
2984 if (priv->profile->update_carrier)
2985 priv->profile->update_carrier(priv);
2987 mlx5e_queue_update_stats(priv);
2990 err_clear_state_opened_flag:
2991 clear_bit(MLX5E_STATE_OPENED, &priv->state);
2995 int mlx5e_open(struct net_device *netdev)
2997 struct mlx5e_priv *priv = netdev_priv(netdev);
3000 mutex_lock(&priv->state_lock);
3001 err = mlx5e_open_locked(netdev);
3003 mlx5e_modify_admin_state(priv->mdev, MLX5_PORT_UP);
3004 mutex_unlock(&priv->state_lock);
3009 int mlx5e_close_locked(struct net_device *netdev)
3011 struct mlx5e_priv *priv = netdev_priv(netdev);
3013 /* May already be CLOSED in case a previous configuration operation
3014 * (e.g RX/TX queue size change) that involves close&open failed.
3016 if (!test_bit(MLX5E_STATE_OPENED, &priv->state))
3019 mlx5e_apply_traps(priv, false);
3020 clear_bit(MLX5E_STATE_OPENED, &priv->state);
3022 netif_carrier_off(priv->netdev);
3023 mlx5e_deactivate_priv_channels(priv);
3024 mlx5e_close_channels(&priv->channels);
3029 int mlx5e_close(struct net_device *netdev)
3031 struct mlx5e_priv *priv = netdev_priv(netdev);
3034 if (!netif_device_present(netdev))
3037 mutex_lock(&priv->state_lock);
3038 mlx5e_modify_admin_state(priv->mdev, MLX5_PORT_DOWN);
3039 err = mlx5e_close_locked(netdev);
3040 mutex_unlock(&priv->state_lock);
3045 static void mlx5e_free_drop_rq(struct mlx5e_rq *rq)
3047 mlx5_wq_destroy(&rq->wq_ctrl);
3050 static int mlx5e_alloc_drop_rq(struct mlx5_core_dev *mdev,
3051 struct mlx5e_rq *rq,
3052 struct mlx5e_rq_param *param)
3054 void *rqc = param->rqc;
3055 void *rqc_wq = MLX5_ADDR_OF(rqc, rqc, wq);
3058 param->wq.db_numa_node = param->wq.buf_numa_node;
3060 err = mlx5_wq_cyc_create(mdev, ¶m->wq, rqc_wq, &rq->wqe.wq,
3065 /* Mark as unused given "Drop-RQ" packets never reach XDP */
3066 xdp_rxq_info_unused(&rq->xdp_rxq);
3073 static int mlx5e_alloc_drop_cq(struct mlx5e_priv *priv,
3074 struct mlx5e_cq *cq,
3075 struct mlx5e_cq_param *param)
3077 struct mlx5_core_dev *mdev = priv->mdev;
3079 param->wq.buf_numa_node = dev_to_node(mlx5_core_dma_dev(mdev));
3080 param->wq.db_numa_node = dev_to_node(mlx5_core_dma_dev(mdev));
3082 return mlx5e_alloc_cq_common(priv, param, cq);
3085 int mlx5e_open_drop_rq(struct mlx5e_priv *priv,
3086 struct mlx5e_rq *drop_rq)
3088 struct mlx5_core_dev *mdev = priv->mdev;
3089 struct mlx5e_cq_param cq_param = {};
3090 struct mlx5e_rq_param rq_param = {};
3091 struct mlx5e_cq *cq = &drop_rq->cq;
3094 mlx5e_build_drop_rq_param(mdev, priv->drop_rq_q_counter, &rq_param);
3096 err = mlx5e_alloc_drop_cq(priv, cq, &cq_param);
3100 err = mlx5e_create_cq(cq, &cq_param);
3104 err = mlx5e_alloc_drop_rq(mdev, drop_rq, &rq_param);
3106 goto err_destroy_cq;
3108 err = mlx5e_create_rq(drop_rq, &rq_param);
3112 err = mlx5e_modify_rq_state(drop_rq, MLX5_RQC_STATE_RST, MLX5_RQC_STATE_RDY);
3114 mlx5_core_warn(priv->mdev, "modify_rq_state failed, rx_if_down_packets won't be counted %d\n", err);
3119 mlx5e_free_drop_rq(drop_rq);
3122 mlx5e_destroy_cq(cq);
3130 void mlx5e_close_drop_rq(struct mlx5e_rq *drop_rq)
3132 mlx5e_destroy_rq(drop_rq);
3133 mlx5e_free_drop_rq(drop_rq);
3134 mlx5e_destroy_cq(&drop_rq->cq);
3135 mlx5e_free_cq(&drop_rq->cq);
3138 int mlx5e_create_tis(struct mlx5_core_dev *mdev, void *in, u32 *tisn)
3140 void *tisc = MLX5_ADDR_OF(create_tis_in, in, ctx);
3142 MLX5_SET(tisc, tisc, transport_domain, mdev->mlx5e_res.hw_objs.td.tdn);
3144 if (MLX5_GET(tisc, tisc, tls_en))
3145 MLX5_SET(tisc, tisc, pd, mdev->mlx5e_res.hw_objs.pdn);
3147 if (mlx5_lag_is_lacp_owner(mdev))
3148 MLX5_SET(tisc, tisc, strict_lag_tx_port_affinity, 1);
3150 return mlx5_core_create_tis(mdev, in, tisn);
3153 void mlx5e_destroy_tis(struct mlx5_core_dev *mdev, u32 tisn)
3155 mlx5_core_destroy_tis(mdev, tisn);
3158 void mlx5e_destroy_tises(struct mlx5e_priv *priv)
3162 for (i = 0; i < mlx5e_get_num_lag_ports(priv->mdev); i++)
3163 for (tc = 0; tc < priv->profile->max_tc; tc++)
3164 mlx5e_destroy_tis(priv->mdev, priv->tisn[i][tc]);
3167 static bool mlx5e_lag_should_assign_affinity(struct mlx5_core_dev *mdev)
3169 return MLX5_CAP_GEN(mdev, lag_tx_port_affinity) && mlx5e_get_num_lag_ports(mdev) > 1;
3172 int mlx5e_create_tises(struct mlx5e_priv *priv)
3177 for (i = 0; i < mlx5e_get_num_lag_ports(priv->mdev); i++) {
3178 for (tc = 0; tc < priv->profile->max_tc; tc++) {
3179 u32 in[MLX5_ST_SZ_DW(create_tis_in)] = {};
3182 tisc = MLX5_ADDR_OF(create_tis_in, in, ctx);
3184 MLX5_SET(tisc, tisc, prio, tc << 1);
3186 if (mlx5e_lag_should_assign_affinity(priv->mdev))
3187 MLX5_SET(tisc, tisc, lag_tx_port_affinity, i + 1);
3189 err = mlx5e_create_tis(priv->mdev, in, &priv->tisn[i][tc]);
3191 goto err_close_tises;
3198 for (; i >= 0; i--) {
3199 for (tc--; tc >= 0; tc--)
3200 mlx5e_destroy_tis(priv->mdev, priv->tisn[i][tc]);
3201 tc = priv->profile->max_tc;
3207 static void mlx5e_cleanup_nic_tx(struct mlx5e_priv *priv)
3209 mlx5e_destroy_tises(priv);
3212 static void mlx5e_build_indir_tir_ctx_common(struct mlx5e_priv *priv,
3213 u32 rqtn, u32 *tirc)
3215 MLX5_SET(tirc, tirc, transport_domain, priv->mdev->mlx5e_res.hw_objs.td.tdn);
3216 MLX5_SET(tirc, tirc, disp_type, MLX5_TIRC_DISP_TYPE_INDIRECT);
3217 MLX5_SET(tirc, tirc, indirect_table, rqtn);
3218 MLX5_SET(tirc, tirc, tunneled_offload_en,
3219 priv->channels.params.tunneled_offload_en);
3221 mlx5e_build_tir_ctx_lro(&priv->channels.params, tirc);
3224 static void mlx5e_build_indir_tir_ctx(struct mlx5e_priv *priv,
3225 enum mlx5e_traffic_types tt,
3228 mlx5e_build_indir_tir_ctx_common(priv, priv->indir_rqt.rqtn, tirc);
3229 mlx5e_build_indir_tir_ctx_hash(&priv->rss_params,
3230 &tirc_default_config[tt], tirc, false);
3233 static void mlx5e_build_direct_tir_ctx(struct mlx5e_priv *priv, u32 rqtn, u32 *tirc)
3235 mlx5e_build_indir_tir_ctx_common(priv, rqtn, tirc);
3236 MLX5_SET(tirc, tirc, rx_hash_fn, MLX5_RX_HASH_FN_INVERTED_XOR8);
3239 static void mlx5e_build_inner_indir_tir_ctx(struct mlx5e_priv *priv,
3240 enum mlx5e_traffic_types tt,
3243 mlx5e_build_indir_tir_ctx_common(priv, priv->indir_rqt.rqtn, tirc);
3244 mlx5e_build_indir_tir_ctx_hash(&priv->rss_params,
3245 &tirc_default_config[tt], tirc, true);
3248 int mlx5e_create_indirect_tirs(struct mlx5e_priv *priv, bool inner_ttc)
3250 struct mlx5e_tir *tir;
3258 inlen = MLX5_ST_SZ_BYTES(create_tir_in);
3259 in = kvzalloc(inlen, GFP_KERNEL);
3263 for (tt = 0; tt < MLX5E_NUM_INDIR_TIRS; tt++) {
3264 memset(in, 0, inlen);
3265 tir = &priv->indir_tir[tt];
3266 tirc = MLX5_ADDR_OF(create_tir_in, in, ctx);
3267 mlx5e_build_indir_tir_ctx(priv, tt, tirc);
3268 err = mlx5e_create_tir(priv->mdev, tir, in);
3270 mlx5_core_warn(priv->mdev, "create indirect tirs failed, %d\n", err);
3271 goto err_destroy_inner_tirs;
3275 if (!inner_ttc || !mlx5e_tunnel_inner_ft_supported(priv->mdev))
3278 for (i = 0; i < MLX5E_NUM_INDIR_TIRS; i++) {
3279 memset(in, 0, inlen);
3280 tir = &priv->inner_indir_tir[i];
3281 tirc = MLX5_ADDR_OF(create_tir_in, in, ctx);
3282 mlx5e_build_inner_indir_tir_ctx(priv, i, tirc);
3283 err = mlx5e_create_tir(priv->mdev, tir, in);
3285 mlx5_core_warn(priv->mdev, "create inner indirect tirs failed, %d\n", err);
3286 goto err_destroy_inner_tirs;
3295 err_destroy_inner_tirs:
3296 for (i--; i >= 0; i--)
3297 mlx5e_destroy_tir(priv->mdev, &priv->inner_indir_tir[i]);
3299 for (tt--; tt >= 0; tt--)
3300 mlx5e_destroy_tir(priv->mdev, &priv->indir_tir[tt]);
3307 int mlx5e_create_direct_tirs(struct mlx5e_priv *priv, struct mlx5e_tir *tirs, int n)
3309 struct mlx5e_tir *tir;
3316 inlen = MLX5_ST_SZ_BYTES(create_tir_in);
3317 in = kvzalloc(inlen, GFP_KERNEL);
3321 for (ix = 0; ix < n; ix++) {
3322 memset(in, 0, inlen);
3324 tirc = MLX5_ADDR_OF(create_tir_in, in, ctx);
3325 mlx5e_build_direct_tir_ctx(priv, tir->rqt.rqtn, tirc);
3326 err = mlx5e_create_tir(priv->mdev, tir, in);
3328 goto err_destroy_ch_tirs;
3333 err_destroy_ch_tirs:
3334 mlx5_core_warn(priv->mdev, "create tirs failed, %d\n", err);
3335 for (ix--; ix >= 0; ix--)
3336 mlx5e_destroy_tir(priv->mdev, &tirs[ix]);
3344 void mlx5e_destroy_indirect_tirs(struct mlx5e_priv *priv)
3348 for (i = 0; i < MLX5E_NUM_INDIR_TIRS; i++)
3349 mlx5e_destroy_tir(priv->mdev, &priv->indir_tir[i]);
3351 /* Verify inner tirs resources allocated */
3352 if (!priv->inner_indir_tir[0].tirn)
3355 for (i = 0; i < MLX5E_NUM_INDIR_TIRS; i++)
3356 mlx5e_destroy_tir(priv->mdev, &priv->inner_indir_tir[i]);
3359 void mlx5e_destroy_direct_tirs(struct mlx5e_priv *priv, struct mlx5e_tir *tirs, int n)
3363 for (i = 0; i < n; i++)
3364 mlx5e_destroy_tir(priv->mdev, &tirs[i]);
3367 static int mlx5e_modify_channels_scatter_fcs(struct mlx5e_channels *chs, bool enable)
3372 for (i = 0; i < chs->num; i++) {
3373 err = mlx5e_modify_rq_scatter_fcs(&chs->c[i]->rq, enable);
3381 static int mlx5e_modify_channels_vsd(struct mlx5e_channels *chs, bool vsd)
3386 for (i = 0; i < chs->num; i++) {
3387 err = mlx5e_modify_rq_vsd(&chs->c[i]->rq, vsd);
3395 static int mlx5e_setup_tc_mqprio(struct mlx5e_priv *priv,
3396 struct tc_mqprio_qopt *mqprio)
3398 struct mlx5e_params new_params;
3399 u8 tc = mqprio->num_tc;
3402 mqprio->hw = TC_MQPRIO_HW_OFFLOAD_TCS;
3404 if (tc && tc != MLX5E_MAX_NUM_TC)
3407 mutex_lock(&priv->state_lock);
3409 /* MQPRIO is another toplevel qdisc that can't be attached
3410 * simultaneously with the offloaded HTB.
3412 if (WARN_ON(priv->htb.maj_id)) {
3417 new_params = priv->channels.params;
3418 new_params.num_tc = tc ? tc : 1;
3420 err = mlx5e_safe_switch_params(priv, &new_params,
3421 mlx5e_num_channels_changed_ctx, NULL, true);
3424 priv->max_opened_tc = max_t(u8, priv->max_opened_tc,
3425 priv->channels.params.num_tc);
3426 mutex_unlock(&priv->state_lock);
3430 static int mlx5e_setup_tc_htb(struct mlx5e_priv *priv, struct tc_htb_qopt_offload *htb)
3434 switch (htb->command) {
3436 return mlx5e_htb_root_add(priv, htb->parent_classid, htb->classid,
3438 case TC_HTB_DESTROY:
3439 return mlx5e_htb_root_del(priv);
3440 case TC_HTB_LEAF_ALLOC_QUEUE:
3441 res = mlx5e_htb_leaf_alloc_queue(priv, htb->classid, htb->parent_classid,
3442 htb->rate, htb->ceil, htb->extack);
3447 case TC_HTB_LEAF_TO_INNER:
3448 return mlx5e_htb_leaf_to_inner(priv, htb->parent_classid, htb->classid,
3449 htb->rate, htb->ceil, htb->extack);
3450 case TC_HTB_LEAF_DEL:
3451 return mlx5e_htb_leaf_del(priv, htb->classid, &htb->moved_qid, &htb->qid,
3453 case TC_HTB_LEAF_DEL_LAST:
3454 case TC_HTB_LEAF_DEL_LAST_FORCE:
3455 return mlx5e_htb_leaf_del_last(priv, htb->classid,
3456 htb->command == TC_HTB_LEAF_DEL_LAST_FORCE,
3458 case TC_HTB_NODE_MODIFY:
3459 return mlx5e_htb_node_modify(priv, htb->classid, htb->rate, htb->ceil,
3461 case TC_HTB_LEAF_QUERY_QUEUE:
3462 res = mlx5e_get_txq_by_classid(priv, htb->classid);
3472 static LIST_HEAD(mlx5e_block_cb_list);
3474 static int mlx5e_setup_tc(struct net_device *dev, enum tc_setup_type type,
3477 struct mlx5e_priv *priv = netdev_priv(dev);
3478 bool tc_unbind = false;
3481 if (type == TC_SETUP_BLOCK &&
3482 ((struct flow_block_offload *)type_data)->command == FLOW_BLOCK_UNBIND)
3485 if (!netif_device_present(dev) && !tc_unbind)
3489 case TC_SETUP_BLOCK: {
3490 struct flow_block_offload *f = type_data;
3492 f->unlocked_driver_cb = true;
3493 return flow_block_cb_setup_simple(type_data,
3494 &mlx5e_block_cb_list,
3495 mlx5e_setup_tc_block_cb,
3498 case TC_SETUP_QDISC_MQPRIO:
3499 return mlx5e_setup_tc_mqprio(priv, type_data);
3500 case TC_SETUP_QDISC_HTB:
3501 mutex_lock(&priv->state_lock);
3502 err = mlx5e_setup_tc_htb(priv, type_data);
3503 mutex_unlock(&priv->state_lock);
3510 void mlx5e_fold_sw_stats64(struct mlx5e_priv *priv, struct rtnl_link_stats64 *s)
3514 for (i = 0; i < priv->max_nch; i++) {
3515 struct mlx5e_channel_stats *channel_stats = &priv->channel_stats[i];
3516 struct mlx5e_rq_stats *xskrq_stats = &channel_stats->xskrq;
3517 struct mlx5e_rq_stats *rq_stats = &channel_stats->rq;
3520 s->rx_packets += rq_stats->packets + xskrq_stats->packets;
3521 s->rx_bytes += rq_stats->bytes + xskrq_stats->bytes;
3522 s->multicast += rq_stats->mcast_packets + xskrq_stats->mcast_packets;
3524 for (j = 0; j < priv->max_opened_tc; j++) {
3525 struct mlx5e_sq_stats *sq_stats = &channel_stats->sq[j];
3527 s->tx_packets += sq_stats->packets;
3528 s->tx_bytes += sq_stats->bytes;
3529 s->tx_dropped += sq_stats->dropped;
3532 if (priv->tx_ptp_opened) {
3533 for (i = 0; i < priv->max_opened_tc; i++) {
3534 struct mlx5e_sq_stats *sq_stats = &priv->ptp_stats.sq[i];
3536 s->tx_packets += sq_stats->packets;
3537 s->tx_bytes += sq_stats->bytes;
3538 s->tx_dropped += sq_stats->dropped;
3541 if (priv->rx_ptp_opened) {
3542 struct mlx5e_rq_stats *rq_stats = &priv->ptp_stats.rq;
3544 s->rx_packets += rq_stats->packets;
3545 s->rx_bytes += rq_stats->bytes;
3546 s->multicast += rq_stats->mcast_packets;
3551 mlx5e_get_stats(struct net_device *dev, struct rtnl_link_stats64 *stats)
3553 struct mlx5e_priv *priv = netdev_priv(dev);
3554 struct mlx5e_pport_stats *pstats = &priv->stats.pport;
3556 if (!netif_device_present(dev))
3559 /* In switchdev mode, monitor counters doesn't monitor
3560 * rx/tx stats of 802_3. The update stats mechanism
3561 * should keep the 802_3 layout counters updated
3563 if (!mlx5e_monitor_counter_supported(priv) ||
3564 mlx5e_is_uplink_rep(priv)) {
3565 /* update HW stats in background for next time */
3566 mlx5e_queue_update_stats(priv);
3569 if (mlx5e_is_uplink_rep(priv)) {
3570 struct mlx5e_vport_stats *vstats = &priv->stats.vport;
3572 stats->rx_packets = PPORT_802_3_GET(pstats, a_frames_received_ok);
3573 stats->rx_bytes = PPORT_802_3_GET(pstats, a_octets_received_ok);
3574 stats->tx_packets = PPORT_802_3_GET(pstats, a_frames_transmitted_ok);
3575 stats->tx_bytes = PPORT_802_3_GET(pstats, a_octets_transmitted_ok);
3577 /* vport multicast also counts packets that are dropped due to steering
3578 * or rx out of buffer
3580 stats->multicast = VPORT_COUNTER_GET(vstats, received_eth_multicast.packets);
3582 mlx5e_fold_sw_stats64(priv, stats);
3585 stats->rx_dropped = priv->stats.qcnt.rx_out_of_buffer;
3587 stats->rx_length_errors =
3588 PPORT_802_3_GET(pstats, a_in_range_length_errors) +
3589 PPORT_802_3_GET(pstats, a_out_of_range_length_field) +
3590 PPORT_802_3_GET(pstats, a_frame_too_long_errors);
3591 stats->rx_crc_errors =
3592 PPORT_802_3_GET(pstats, a_frame_check_sequence_errors);
3593 stats->rx_frame_errors = PPORT_802_3_GET(pstats, a_alignment_errors);
3594 stats->tx_aborted_errors = PPORT_2863_GET(pstats, if_out_discards);
3595 stats->rx_errors = stats->rx_length_errors + stats->rx_crc_errors +
3596 stats->rx_frame_errors;
3597 stats->tx_errors = stats->tx_aborted_errors + stats->tx_carrier_errors;
3600 static void mlx5e_nic_set_rx_mode(struct mlx5e_priv *priv)
3602 if (mlx5e_is_uplink_rep(priv))
3603 return; /* no rx mode for uplink rep */
3605 queue_work(priv->wq, &priv->set_rx_mode_work);
3608 static void mlx5e_set_rx_mode(struct net_device *dev)
3610 struct mlx5e_priv *priv = netdev_priv(dev);
3612 mlx5e_nic_set_rx_mode(priv);
3615 static int mlx5e_set_mac(struct net_device *netdev, void *addr)
3617 struct mlx5e_priv *priv = netdev_priv(netdev);
3618 struct sockaddr *saddr = addr;
3620 if (!is_valid_ether_addr(saddr->sa_data))
3621 return -EADDRNOTAVAIL;
3623 netif_addr_lock_bh(netdev);
3624 ether_addr_copy(netdev->dev_addr, saddr->sa_data);
3625 netif_addr_unlock_bh(netdev);
3627 mlx5e_nic_set_rx_mode(priv);
3632 #define MLX5E_SET_FEATURE(features, feature, enable) \
3635 *features |= feature; \
3637 *features &= ~feature; \
3640 typedef int (*mlx5e_feature_handler)(struct net_device *netdev, bool enable);
3642 static int set_feature_lro(struct net_device *netdev, bool enable)
3644 struct mlx5e_priv *priv = netdev_priv(netdev);
3645 struct mlx5_core_dev *mdev = priv->mdev;
3646 struct mlx5e_params *cur_params;
3647 struct mlx5e_params new_params;
3651 mutex_lock(&priv->state_lock);
3653 if (enable && priv->xsk.refcnt) {
3654 netdev_warn(netdev, "LRO is incompatible with AF_XDP (%u XSKs are active)\n",
3660 cur_params = &priv->channels.params;
3661 if (enable && !MLX5E_GET_PFLAG(cur_params, MLX5E_PFLAG_RX_STRIDING_RQ)) {
3662 netdev_warn(netdev, "can't set LRO with legacy RQ\n");
3667 new_params = *cur_params;
3668 new_params.lro_en = enable;
3670 if (cur_params->rq_wq_type == MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ) {
3671 if (mlx5e_rx_mpwqe_is_linear_skb(mdev, cur_params, NULL) ==
3672 mlx5e_rx_mpwqe_is_linear_skb(mdev, &new_params, NULL))
3676 err = mlx5e_safe_switch_params(priv, &new_params,
3677 mlx5e_modify_tirs_lro_ctx, NULL, reset);
3679 mutex_unlock(&priv->state_lock);
3683 static int set_feature_cvlan_filter(struct net_device *netdev, bool enable)
3685 struct mlx5e_priv *priv = netdev_priv(netdev);
3688 mlx5e_enable_cvlan_filter(priv);
3690 mlx5e_disable_cvlan_filter(priv);
3695 static int set_feature_hw_tc(struct net_device *netdev, bool enable)
3697 struct mlx5e_priv *priv = netdev_priv(netdev);
3699 #if IS_ENABLED(CONFIG_MLX5_CLS_ACT)
3700 if (!enable && mlx5e_tc_num_filters(priv, MLX5_TC_FLAG(NIC_OFFLOAD))) {
3702 "Active offloaded tc filters, can't turn hw_tc_offload off\n");
3707 if (!enable && priv->htb.maj_id) {
3708 netdev_err(netdev, "Active HTB offload, can't turn hw_tc_offload off\n");
3715 static int set_feature_rx_all(struct net_device *netdev, bool enable)
3717 struct mlx5e_priv *priv = netdev_priv(netdev);
3718 struct mlx5_core_dev *mdev = priv->mdev;
3720 return mlx5_set_port_fcs(mdev, !enable);
3723 static int set_feature_rx_fcs(struct net_device *netdev, bool enable)
3725 struct mlx5e_priv *priv = netdev_priv(netdev);
3728 mutex_lock(&priv->state_lock);
3730 priv->channels.params.scatter_fcs_en = enable;
3731 err = mlx5e_modify_channels_scatter_fcs(&priv->channels, enable);
3733 priv->channels.params.scatter_fcs_en = !enable;
3735 mutex_unlock(&priv->state_lock);
3740 static int set_feature_rx_vlan(struct net_device *netdev, bool enable)
3742 struct mlx5e_priv *priv = netdev_priv(netdev);
3745 mutex_lock(&priv->state_lock);
3747 priv->channels.params.vlan_strip_disable = !enable;
3748 if (!test_bit(MLX5E_STATE_OPENED, &priv->state))
3751 err = mlx5e_modify_channels_vsd(&priv->channels, !enable);
3753 priv->channels.params.vlan_strip_disable = enable;
3756 mutex_unlock(&priv->state_lock);
3761 #ifdef CONFIG_MLX5_EN_ARFS
3762 static int set_feature_arfs(struct net_device *netdev, bool enable)
3764 struct mlx5e_priv *priv = netdev_priv(netdev);
3768 err = mlx5e_arfs_enable(priv);
3770 err = mlx5e_arfs_disable(priv);
3776 static int mlx5e_handle_feature(struct net_device *netdev,
3777 netdev_features_t *features,
3778 netdev_features_t wanted_features,
3779 netdev_features_t feature,
3780 mlx5e_feature_handler feature_handler)
3782 netdev_features_t changes = wanted_features ^ netdev->features;
3783 bool enable = !!(wanted_features & feature);
3786 if (!(changes & feature))
3789 err = feature_handler(netdev, enable);
3791 netdev_err(netdev, "%s feature %pNF failed, err %d\n",
3792 enable ? "Enable" : "Disable", &feature, err);
3796 MLX5E_SET_FEATURE(features, feature, enable);
3800 int mlx5e_set_features(struct net_device *netdev, netdev_features_t features)
3802 netdev_features_t oper_features = netdev->features;
3805 #define MLX5E_HANDLE_FEATURE(feature, handler) \
3806 mlx5e_handle_feature(netdev, &oper_features, features, feature, handler)
3808 err |= MLX5E_HANDLE_FEATURE(NETIF_F_LRO, set_feature_lro);
3809 err |= MLX5E_HANDLE_FEATURE(NETIF_F_HW_VLAN_CTAG_FILTER,
3810 set_feature_cvlan_filter);
3811 err |= MLX5E_HANDLE_FEATURE(NETIF_F_HW_TC, set_feature_hw_tc);
3812 err |= MLX5E_HANDLE_FEATURE(NETIF_F_RXALL, set_feature_rx_all);
3813 err |= MLX5E_HANDLE_FEATURE(NETIF_F_RXFCS, set_feature_rx_fcs);
3814 err |= MLX5E_HANDLE_FEATURE(NETIF_F_HW_VLAN_CTAG_RX, set_feature_rx_vlan);
3815 #ifdef CONFIG_MLX5_EN_ARFS
3816 err |= MLX5E_HANDLE_FEATURE(NETIF_F_NTUPLE, set_feature_arfs);
3818 err |= MLX5E_HANDLE_FEATURE(NETIF_F_HW_TLS_RX, mlx5e_ktls_set_feature_rx);
3821 netdev->features = oper_features;
3828 static netdev_features_t mlx5e_fix_features(struct net_device *netdev,
3829 netdev_features_t features)
3831 struct mlx5e_priv *priv = netdev_priv(netdev);
3832 struct mlx5e_params *params;
3834 mutex_lock(&priv->state_lock);
3835 params = &priv->channels.params;
3836 if (!priv->fs.vlan ||
3837 !bitmap_empty(mlx5e_vlan_get_active_svlans(priv->fs.vlan), VLAN_N_VID)) {
3838 /* HW strips the outer C-tag header, this is a problem
3839 * for S-tag traffic.
3841 features &= ~NETIF_F_HW_VLAN_CTAG_RX;
3842 if (!params->vlan_strip_disable)
3843 netdev_warn(netdev, "Dropping C-tag vlan stripping offload due to S-tag vlan\n");
3846 if (!MLX5E_GET_PFLAG(params, MLX5E_PFLAG_RX_STRIDING_RQ)) {
3847 if (features & NETIF_F_LRO) {
3848 netdev_warn(netdev, "Disabling LRO, not supported in legacy RQ\n");
3849 features &= ~NETIF_F_LRO;
3853 if (MLX5E_GET_PFLAG(params, MLX5E_PFLAG_RX_CQE_COMPRESS)) {
3854 features &= ~NETIF_F_RXHASH;
3855 if (netdev->features & NETIF_F_RXHASH)
3856 netdev_warn(netdev, "Disabling rxhash, not supported when CQE compress is active\n");
3859 if (mlx5e_is_uplink_rep(priv)) {
3860 features &= ~NETIF_F_HW_TLS_RX;
3861 if (netdev->features & NETIF_F_HW_TLS_RX)
3862 netdev_warn(netdev, "Disabling hw_tls_rx, not supported in switchdev mode\n");
3864 features &= ~NETIF_F_HW_TLS_TX;
3865 if (netdev->features & NETIF_F_HW_TLS_TX)
3866 netdev_warn(netdev, "Disabling hw_tls_tx, not supported in switchdev mode\n");
3869 mutex_unlock(&priv->state_lock);
3874 static bool mlx5e_xsk_validate_mtu(struct net_device *netdev,
3875 struct mlx5e_channels *chs,
3876 struct mlx5e_params *new_params,
3877 struct mlx5_core_dev *mdev)
3881 for (ix = 0; ix < chs->params.num_channels; ix++) {
3882 struct xsk_buff_pool *xsk_pool =
3883 mlx5e_xsk_get_pool(&chs->params, chs->params.xsk, ix);
3884 struct mlx5e_xsk_param xsk;
3889 mlx5e_build_xsk_param(xsk_pool, &xsk);
3891 if (!mlx5e_validate_xsk_param(new_params, &xsk, mdev)) {
3892 u32 hr = mlx5e_get_linear_rq_headroom(new_params, &xsk);
3893 int max_mtu_frame, max_mtu_page, max_mtu;
3895 /* Two criteria must be met:
3896 * 1. HW MTU + all headrooms <= XSK frame size.
3897 * 2. Size of SKBs allocated on XDP_PASS <= PAGE_SIZE.
3899 max_mtu_frame = MLX5E_HW2SW_MTU(new_params, xsk.chunk_size - hr);
3900 max_mtu_page = mlx5e_xdp_max_mtu(new_params, &xsk);
3901 max_mtu = min(max_mtu_frame, max_mtu_page);
3903 netdev_err(netdev, "MTU %d is too big for an XSK running on channel %u. Try MTU <= %d\n",
3904 new_params->sw_mtu, ix, max_mtu);
3912 int mlx5e_change_mtu(struct net_device *netdev, int new_mtu,
3913 mlx5e_fp_preactivate preactivate)
3915 struct mlx5e_priv *priv = netdev_priv(netdev);
3916 struct mlx5e_params new_params;
3917 struct mlx5e_params *params;
3921 mutex_lock(&priv->state_lock);
3923 params = &priv->channels.params;
3925 new_params = *params;
3926 new_params.sw_mtu = new_mtu;
3927 err = mlx5e_validate_params(priv->mdev, &new_params);
3931 if (params->xdp_prog &&
3932 !mlx5e_rx_is_linear_skb(&new_params, NULL)) {
3933 netdev_err(netdev, "MTU(%d) > %d is not allowed while XDP enabled\n",
3934 new_mtu, mlx5e_xdp_max_mtu(params, NULL));
3939 if (priv->xsk.refcnt &&
3940 !mlx5e_xsk_validate_mtu(netdev, &priv->channels,
3941 &new_params, priv->mdev)) {
3949 if (params->rq_wq_type == MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ) {
3950 bool is_linear_old = mlx5e_rx_mpwqe_is_linear_skb(priv->mdev, params, NULL);
3951 bool is_linear_new = mlx5e_rx_mpwqe_is_linear_skb(priv->mdev,
3953 u8 ppw_old = mlx5e_mpwqe_log_pkts_per_wqe(params, NULL);
3954 u8 ppw_new = mlx5e_mpwqe_log_pkts_per_wqe(&new_params, NULL);
3956 /* Always reset in linear mode - hw_mtu is used in data path.
3957 * Check that the mode was non-linear and didn't change.
3958 * If XSK is active, XSK RQs are linear.
3960 if (!is_linear_old && !is_linear_new && !priv->xsk.refcnt &&
3965 err = mlx5e_safe_switch_params(priv, &new_params, preactivate, NULL, reset);
3968 netdev->mtu = params->sw_mtu;
3969 mutex_unlock(&priv->state_lock);
3973 static int mlx5e_change_nic_mtu(struct net_device *netdev, int new_mtu)
3975 return mlx5e_change_mtu(netdev, new_mtu, mlx5e_set_dev_port_mtu_ctx);
3978 int mlx5e_ptp_rx_manage_fs_ctx(struct mlx5e_priv *priv, void *ctx)
3980 bool set = *(bool *)ctx;
3982 return mlx5e_ptp_rx_manage_fs(priv, set);
3985 static int mlx5e_hwstamp_config_no_ptp_rx(struct mlx5e_priv *priv, bool rx_filter)
3987 bool rx_cqe_compress_def = priv->channels.params.rx_cqe_compress_def;
3991 /* Reset CQE compression to Admin default */
3992 return mlx5e_modify_rx_cqe_compression_locked(priv, rx_cqe_compress_def);
3994 if (!MLX5E_GET_PFLAG(&priv->channels.params, MLX5E_PFLAG_RX_CQE_COMPRESS))
3997 /* Disable CQE compression */
3998 netdev_warn(priv->netdev, "Disabling RX cqe compression\n");
3999 err = mlx5e_modify_rx_cqe_compression_locked(priv, false);
4001 netdev_err(priv->netdev, "Failed disabling cqe compression err=%d\n", err);
4006 static int mlx5e_hwstamp_config_ptp_rx(struct mlx5e_priv *priv, bool ptp_rx)
4008 struct mlx5e_params new_params;
4010 if (ptp_rx == priv->channels.params.ptp_rx)
4013 new_params = priv->channels.params;
4014 new_params.ptp_rx = ptp_rx;
4015 return mlx5e_safe_switch_params(priv, &new_params, mlx5e_ptp_rx_manage_fs_ctx,
4016 &new_params.ptp_rx, true);
4019 int mlx5e_hwstamp_set(struct mlx5e_priv *priv, struct ifreq *ifr)
4021 struct hwtstamp_config config;
4022 bool rx_cqe_compress_def;
4026 if (!MLX5_CAP_GEN(priv->mdev, device_frequency_khz) ||
4027 (mlx5_clock_get_ptp_index(priv->mdev) == -1))
4030 if (copy_from_user(&config, ifr->ifr_data, sizeof(config)))
4033 /* TX HW timestamp */
4034 switch (config.tx_type) {
4035 case HWTSTAMP_TX_OFF:
4036 case HWTSTAMP_TX_ON:
4042 mutex_lock(&priv->state_lock);
4043 rx_cqe_compress_def = priv->channels.params.rx_cqe_compress_def;
4045 /* RX HW timestamp */
4046 switch (config.rx_filter) {
4047 case HWTSTAMP_FILTER_NONE:
4050 case HWTSTAMP_FILTER_ALL:
4051 case HWTSTAMP_FILTER_SOME:
4052 case HWTSTAMP_FILTER_PTP_V1_L4_EVENT:
4053 case HWTSTAMP_FILTER_PTP_V1_L4_SYNC:
4054 case HWTSTAMP_FILTER_PTP_V1_L4_DELAY_REQ:
4055 case HWTSTAMP_FILTER_PTP_V2_L4_EVENT:
4056 case HWTSTAMP_FILTER_PTP_V2_L4_SYNC:
4057 case HWTSTAMP_FILTER_PTP_V2_L4_DELAY_REQ:
4058 case HWTSTAMP_FILTER_PTP_V2_L2_EVENT:
4059 case HWTSTAMP_FILTER_PTP_V2_L2_SYNC:
4060 case HWTSTAMP_FILTER_PTP_V2_L2_DELAY_REQ:
4061 case HWTSTAMP_FILTER_PTP_V2_EVENT:
4062 case HWTSTAMP_FILTER_PTP_V2_SYNC:
4063 case HWTSTAMP_FILTER_PTP_V2_DELAY_REQ:
4064 case HWTSTAMP_FILTER_NTP_ALL:
4065 config.rx_filter = HWTSTAMP_FILTER_ALL;
4066 /* ptp_rx is set if both HW TS is set and CQE
4067 * compression is set
4069 ptp_rx = rx_cqe_compress_def;
4076 if (!priv->profile->rx_ptp_support)
4077 err = mlx5e_hwstamp_config_no_ptp_rx(priv,
4078 config.rx_filter != HWTSTAMP_FILTER_NONE);
4080 err = mlx5e_hwstamp_config_ptp_rx(priv, ptp_rx);
4084 memcpy(&priv->tstamp, &config, sizeof(config));
4085 mutex_unlock(&priv->state_lock);
4087 /* might need to fix some features */
4088 netdev_update_features(priv->netdev);
4090 return copy_to_user(ifr->ifr_data, &config,
4091 sizeof(config)) ? -EFAULT : 0;
4093 mutex_unlock(&priv->state_lock);
4097 int mlx5e_hwstamp_get(struct mlx5e_priv *priv, struct ifreq *ifr)
4099 struct hwtstamp_config *cfg = &priv->tstamp;
4101 if (!MLX5_CAP_GEN(priv->mdev, device_frequency_khz))
4104 return copy_to_user(ifr->ifr_data, cfg, sizeof(*cfg)) ? -EFAULT : 0;
4107 static int mlx5e_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
4109 struct mlx5e_priv *priv = netdev_priv(dev);
4113 return mlx5e_hwstamp_set(priv, ifr);
4115 return mlx5e_hwstamp_get(priv, ifr);
4121 #ifdef CONFIG_MLX5_ESWITCH
4122 int mlx5e_set_vf_mac(struct net_device *dev, int vf, u8 *mac)
4124 struct mlx5e_priv *priv = netdev_priv(dev);
4125 struct mlx5_core_dev *mdev = priv->mdev;
4127 return mlx5_eswitch_set_vport_mac(mdev->priv.eswitch, vf + 1, mac);
4130 static int mlx5e_set_vf_vlan(struct net_device *dev, int vf, u16 vlan, u8 qos,
4133 struct mlx5e_priv *priv = netdev_priv(dev);
4134 struct mlx5_core_dev *mdev = priv->mdev;
4136 if (vlan_proto != htons(ETH_P_8021Q))
4137 return -EPROTONOSUPPORT;
4139 return mlx5_eswitch_set_vport_vlan(mdev->priv.eswitch, vf + 1,
4143 static int mlx5e_set_vf_spoofchk(struct net_device *dev, int vf, bool setting)
4145 struct mlx5e_priv *priv = netdev_priv(dev);
4146 struct mlx5_core_dev *mdev = priv->mdev;
4148 return mlx5_eswitch_set_vport_spoofchk(mdev->priv.eswitch, vf + 1, setting);
4151 static int mlx5e_set_vf_trust(struct net_device *dev, int vf, bool setting)
4153 struct mlx5e_priv *priv = netdev_priv(dev);
4154 struct mlx5_core_dev *mdev = priv->mdev;
4156 return mlx5_eswitch_set_vport_trust(mdev->priv.eswitch, vf + 1, setting);
4159 int mlx5e_set_vf_rate(struct net_device *dev, int vf, int min_tx_rate,
4162 struct mlx5e_priv *priv = netdev_priv(dev);
4163 struct mlx5_core_dev *mdev = priv->mdev;
4165 return mlx5_eswitch_set_vport_rate(mdev->priv.eswitch, vf + 1,
4166 max_tx_rate, min_tx_rate);
4169 static int mlx5_vport_link2ifla(u8 esw_link)
4172 case MLX5_VPORT_ADMIN_STATE_DOWN:
4173 return IFLA_VF_LINK_STATE_DISABLE;
4174 case MLX5_VPORT_ADMIN_STATE_UP:
4175 return IFLA_VF_LINK_STATE_ENABLE;
4177 return IFLA_VF_LINK_STATE_AUTO;
4180 static int mlx5_ifla_link2vport(u8 ifla_link)
4182 switch (ifla_link) {
4183 case IFLA_VF_LINK_STATE_DISABLE:
4184 return MLX5_VPORT_ADMIN_STATE_DOWN;
4185 case IFLA_VF_LINK_STATE_ENABLE:
4186 return MLX5_VPORT_ADMIN_STATE_UP;
4188 return MLX5_VPORT_ADMIN_STATE_AUTO;
4191 static int mlx5e_set_vf_link_state(struct net_device *dev, int vf,
4194 struct mlx5e_priv *priv = netdev_priv(dev);
4195 struct mlx5_core_dev *mdev = priv->mdev;
4197 if (mlx5e_is_uplink_rep(priv))
4200 return mlx5_eswitch_set_vport_state(mdev->priv.eswitch, vf + 1,
4201 mlx5_ifla_link2vport(link_state));
4204 int mlx5e_get_vf_config(struct net_device *dev,
4205 int vf, struct ifla_vf_info *ivi)
4207 struct mlx5e_priv *priv = netdev_priv(dev);
4208 struct mlx5_core_dev *mdev = priv->mdev;
4211 if (!netif_device_present(dev))
4214 err = mlx5_eswitch_get_vport_config(mdev->priv.eswitch, vf + 1, ivi);
4217 ivi->linkstate = mlx5_vport_link2ifla(ivi->linkstate);
4221 int mlx5e_get_vf_stats(struct net_device *dev,
4222 int vf, struct ifla_vf_stats *vf_stats)
4224 struct mlx5e_priv *priv = netdev_priv(dev);
4225 struct mlx5_core_dev *mdev = priv->mdev;
4227 return mlx5_eswitch_get_vport_stats(mdev->priv.eswitch, vf + 1,
4232 mlx5e_has_offload_stats(const struct net_device *dev, int attr_id)
4234 struct mlx5e_priv *priv = netdev_priv(dev);
4236 if (!netif_device_present(dev))
4239 if (!mlx5e_is_uplink_rep(priv))
4242 return mlx5e_rep_has_offload_stats(dev, attr_id);
4246 mlx5e_get_offload_stats(int attr_id, const struct net_device *dev,
4249 struct mlx5e_priv *priv = netdev_priv(dev);
4251 if (!mlx5e_is_uplink_rep(priv))
4254 return mlx5e_rep_get_offload_stats(attr_id, dev, sp);
4258 static bool mlx5e_tunnel_proto_supported_tx(struct mlx5_core_dev *mdev, u8 proto_type)
4260 switch (proto_type) {
4262 return MLX5_CAP_ETH(mdev, tunnel_stateless_gre);
4265 return (MLX5_CAP_ETH(mdev, tunnel_stateless_ip_over_ip) ||
4266 MLX5_CAP_ETH(mdev, tunnel_stateless_ip_over_ip_tx));
4272 static bool mlx5e_gre_tunnel_inner_proto_offload_supported(struct mlx5_core_dev *mdev,
4273 struct sk_buff *skb)
4275 switch (skb->inner_protocol) {
4276 case htons(ETH_P_IP):
4277 case htons(ETH_P_IPV6):
4278 case htons(ETH_P_TEB):
4280 case htons(ETH_P_MPLS_UC):
4281 case htons(ETH_P_MPLS_MC):
4282 return MLX5_CAP_ETH(mdev, tunnel_stateless_mpls_over_gre);
4287 static netdev_features_t mlx5e_tunnel_features_check(struct mlx5e_priv *priv,
4288 struct sk_buff *skb,
4289 netdev_features_t features)
4291 unsigned int offset = 0;
4292 struct udphdr *udph;
4296 switch (vlan_get_protocol(skb)) {
4297 case htons(ETH_P_IP):
4298 proto = ip_hdr(skb)->protocol;
4300 case htons(ETH_P_IPV6):
4301 proto = ipv6_find_hdr(skb, &offset, -1, NULL, NULL);
4309 if (mlx5e_gre_tunnel_inner_proto_offload_supported(priv->mdev, skb))
4314 if (mlx5e_tunnel_proto_supported_tx(priv->mdev, IPPROTO_IPIP))
4318 udph = udp_hdr(skb);
4319 port = be16_to_cpu(udph->dest);
4321 /* Verify if UDP port is being offloaded by HW */
4322 if (mlx5_vxlan_lookup_port(priv->mdev->vxlan, port))
4325 #if IS_ENABLED(CONFIG_GENEVE)
4326 /* Support Geneve offload for default UDP port */
4327 if (port == GENEVE_UDP_PORT && mlx5_geneve_tx_allowed(priv->mdev))
4333 /* Disable CSUM and GSO if the udp dport is not offloaded by HW */
4334 return features & ~(NETIF_F_CSUM_MASK | NETIF_F_GSO_MASK);
4337 netdev_features_t mlx5e_features_check(struct sk_buff *skb,
4338 struct net_device *netdev,
4339 netdev_features_t features)
4341 struct mlx5e_priv *priv = netdev_priv(netdev);
4343 features = vlan_features_check(skb, features);
4344 features = vxlan_features_check(skb, features);
4346 if (mlx5e_ipsec_feature_check(skb, netdev, features))
4349 /* Validate if the tunneled packet is being offloaded by HW */
4350 if (skb->encapsulation &&
4351 (features & NETIF_F_CSUM_MASK || features & NETIF_F_GSO_MASK))
4352 return mlx5e_tunnel_features_check(priv, skb, features);
4357 static void mlx5e_tx_timeout_work(struct work_struct *work)
4359 struct mlx5e_priv *priv = container_of(work, struct mlx5e_priv,
4361 struct net_device *netdev = priv->netdev;
4365 mutex_lock(&priv->state_lock);
4367 if (!test_bit(MLX5E_STATE_OPENED, &priv->state))
4370 for (i = 0; i < netdev->real_num_tx_queues; i++) {
4371 struct netdev_queue *dev_queue =
4372 netdev_get_tx_queue(netdev, i);
4373 struct mlx5e_txqsq *sq = priv->txq2sq[i];
4375 if (!netif_xmit_stopped(dev_queue))
4378 if (mlx5e_reporter_tx_timeout(sq))
4379 /* break if tried to reopened channels */
4384 mutex_unlock(&priv->state_lock);
4388 static void mlx5e_tx_timeout(struct net_device *dev, unsigned int txqueue)
4390 struct mlx5e_priv *priv = netdev_priv(dev);
4392 netdev_err(dev, "TX timeout detected\n");
4393 queue_work(priv->wq, &priv->tx_timeout_work);
4396 static int mlx5e_xdp_allowed(struct mlx5e_priv *priv, struct bpf_prog *prog)
4398 struct net_device *netdev = priv->netdev;
4399 struct mlx5e_params new_params;
4401 if (priv->channels.params.lro_en) {
4402 netdev_warn(netdev, "can't set XDP while LRO is on, disable LRO first\n");
4406 if (mlx5_fpga_is_ipsec_device(priv->mdev)) {
4408 "XDP is not available on Innova cards with IPsec support\n");
4412 new_params = priv->channels.params;
4413 new_params.xdp_prog = prog;
4415 /* No XSK params: AF_XDP can't be enabled yet at the point of setting
4418 if (!mlx5e_rx_is_linear_skb(&new_params, NULL)) {
4419 netdev_warn(netdev, "XDP is not allowed with MTU(%d) > %d\n",
4421 mlx5e_xdp_max_mtu(&new_params, NULL));
4428 static void mlx5e_rq_replace_xdp_prog(struct mlx5e_rq *rq, struct bpf_prog *prog)
4430 struct bpf_prog *old_prog;
4432 old_prog = rcu_replace_pointer(rq->xdp_prog, prog,
4433 lockdep_is_held(&rq->priv->state_lock));
4435 bpf_prog_put(old_prog);
4438 static int mlx5e_xdp_set(struct net_device *netdev, struct bpf_prog *prog)
4440 struct mlx5e_priv *priv = netdev_priv(netdev);
4441 struct mlx5e_params new_params;
4442 struct bpf_prog *old_prog;
4447 mutex_lock(&priv->state_lock);
4450 err = mlx5e_xdp_allowed(priv, prog);
4455 /* no need for full reset when exchanging programs */
4456 reset = (!priv->channels.params.xdp_prog || !prog);
4458 new_params = priv->channels.params;
4459 new_params.xdp_prog = prog;
4461 mlx5e_set_rq_type(priv->mdev, &new_params);
4462 old_prog = priv->channels.params.xdp_prog;
4464 err = mlx5e_safe_switch_params(priv, &new_params, NULL, NULL, reset);
4469 bpf_prog_put(old_prog);
4471 if (!test_bit(MLX5E_STATE_OPENED, &priv->state) || reset)
4474 /* exchanging programs w/o reset, we update ref counts on behalf
4475 * of the channels RQs here.
4477 bpf_prog_add(prog, priv->channels.num);
4478 for (i = 0; i < priv->channels.num; i++) {
4479 struct mlx5e_channel *c = priv->channels.c[i];
4481 mlx5e_rq_replace_xdp_prog(&c->rq, prog);
4482 if (test_bit(MLX5E_CHANNEL_STATE_XSK, c->state)) {
4484 mlx5e_rq_replace_xdp_prog(&c->xskrq, prog);
4489 mutex_unlock(&priv->state_lock);
4493 static int mlx5e_xdp(struct net_device *dev, struct netdev_bpf *xdp)
4495 switch (xdp->command) {
4496 case XDP_SETUP_PROG:
4497 return mlx5e_xdp_set(dev, xdp->prog);
4498 case XDP_SETUP_XSK_POOL:
4499 return mlx5e_xsk_setup_pool(dev, xdp->xsk.pool,
4506 #ifdef CONFIG_MLX5_ESWITCH
4507 static int mlx5e_bridge_getlink(struct sk_buff *skb, u32 pid, u32 seq,
4508 struct net_device *dev, u32 filter_mask,
4511 struct mlx5e_priv *priv = netdev_priv(dev);
4512 struct mlx5_core_dev *mdev = priv->mdev;
4516 err = mlx5_eswitch_get_vepa(mdev->priv.eswitch, &setting);
4519 mode = setting ? BRIDGE_MODE_VEPA : BRIDGE_MODE_VEB;
4520 return ndo_dflt_bridge_getlink(skb, pid, seq, dev,
4522 0, 0, nlflags, filter_mask, NULL);
4525 static int mlx5e_bridge_setlink(struct net_device *dev, struct nlmsghdr *nlh,
4526 u16 flags, struct netlink_ext_ack *extack)
4528 struct mlx5e_priv *priv = netdev_priv(dev);
4529 struct mlx5_core_dev *mdev = priv->mdev;
4530 struct nlattr *attr, *br_spec;
4531 u16 mode = BRIDGE_MODE_UNDEF;
4535 br_spec = nlmsg_find_attr(nlh, sizeof(struct ifinfomsg), IFLA_AF_SPEC);
4539 nla_for_each_nested(attr, br_spec, rem) {
4540 if (nla_type(attr) != IFLA_BRIDGE_MODE)
4543 if (nla_len(attr) < sizeof(mode))
4546 mode = nla_get_u16(attr);
4547 if (mode > BRIDGE_MODE_VEPA)
4553 if (mode == BRIDGE_MODE_UNDEF)
4556 setting = (mode == BRIDGE_MODE_VEPA) ? 1 : 0;
4557 return mlx5_eswitch_set_vepa(mdev->priv.eswitch, setting);
4561 const struct net_device_ops mlx5e_netdev_ops = {
4562 .ndo_open = mlx5e_open,
4563 .ndo_stop = mlx5e_close,
4564 .ndo_start_xmit = mlx5e_xmit,
4565 .ndo_setup_tc = mlx5e_setup_tc,
4566 .ndo_select_queue = mlx5e_select_queue,
4567 .ndo_get_stats64 = mlx5e_get_stats,
4568 .ndo_set_rx_mode = mlx5e_set_rx_mode,
4569 .ndo_set_mac_address = mlx5e_set_mac,
4570 .ndo_vlan_rx_add_vid = mlx5e_vlan_rx_add_vid,
4571 .ndo_vlan_rx_kill_vid = mlx5e_vlan_rx_kill_vid,
4572 .ndo_set_features = mlx5e_set_features,
4573 .ndo_fix_features = mlx5e_fix_features,
4574 .ndo_change_mtu = mlx5e_change_nic_mtu,
4575 .ndo_do_ioctl = mlx5e_ioctl,
4576 .ndo_set_tx_maxrate = mlx5e_set_tx_maxrate,
4577 .ndo_features_check = mlx5e_features_check,
4578 .ndo_tx_timeout = mlx5e_tx_timeout,
4579 .ndo_bpf = mlx5e_xdp,
4580 .ndo_xdp_xmit = mlx5e_xdp_xmit,
4581 .ndo_xsk_wakeup = mlx5e_xsk_wakeup,
4582 #ifdef CONFIG_MLX5_EN_ARFS
4583 .ndo_rx_flow_steer = mlx5e_rx_flow_steer,
4585 #ifdef CONFIG_MLX5_ESWITCH
4586 .ndo_bridge_setlink = mlx5e_bridge_setlink,
4587 .ndo_bridge_getlink = mlx5e_bridge_getlink,
4589 /* SRIOV E-Switch NDOs */
4590 .ndo_set_vf_mac = mlx5e_set_vf_mac,
4591 .ndo_set_vf_vlan = mlx5e_set_vf_vlan,
4592 .ndo_set_vf_spoofchk = mlx5e_set_vf_spoofchk,
4593 .ndo_set_vf_trust = mlx5e_set_vf_trust,
4594 .ndo_set_vf_rate = mlx5e_set_vf_rate,
4595 .ndo_get_vf_config = mlx5e_get_vf_config,
4596 .ndo_set_vf_link_state = mlx5e_set_vf_link_state,
4597 .ndo_get_vf_stats = mlx5e_get_vf_stats,
4598 .ndo_has_offload_stats = mlx5e_has_offload_stats,
4599 .ndo_get_offload_stats = mlx5e_get_offload_stats,
4601 .ndo_get_devlink_port = mlx5e_get_devlink_port,
4604 void mlx5e_build_default_indir_rqt(u32 *indirection_rqt, int len,
4609 for (i = 0; i < len; i++)
4610 indirection_rqt[i] = i % num_channels;
4613 static u32 mlx5e_choose_lro_timeout(struct mlx5_core_dev *mdev, u32 wanted_timeout)
4617 /* The supported periods are organized in ascending order */
4618 for (i = 0; i < MLX5E_LRO_TIMEOUT_ARR_SIZE - 1; i++)
4619 if (MLX5_CAP_ETH(mdev, lro_timer_supported_periods[i]) >= wanted_timeout)
4622 return MLX5_CAP_ETH(mdev, lro_timer_supported_periods[i]);
4625 void mlx5e_build_rss_params(struct mlx5e_rss_params *rss_params,
4628 enum mlx5e_traffic_types tt;
4630 rss_params->hfunc = ETH_RSS_HASH_TOP;
4631 netdev_rss_key_fill(rss_params->toeplitz_hash_key,
4632 sizeof(rss_params->toeplitz_hash_key));
4633 mlx5e_build_default_indir_rqt(rss_params->indirection_rqt,
4634 MLX5E_INDIR_RQT_SIZE, num_channels);
4635 for (tt = 0; tt < MLX5E_NUM_INDIR_TIRS; tt++)
4636 rss_params->rx_hash_fields[tt] =
4637 tirc_default_config[tt].rx_hash_fields;
4640 void mlx5e_build_nic_params(struct mlx5e_priv *priv, struct mlx5e_xsk *xsk, u16 mtu)
4642 struct mlx5e_rss_params *rss_params = &priv->rss_params;
4643 struct mlx5e_params *params = &priv->channels.params;
4644 struct mlx5_core_dev *mdev = priv->mdev;
4645 u8 rx_cq_period_mode;
4647 priv->max_nch = mlx5e_calc_max_nch(priv, priv->profile);
4649 params->sw_mtu = mtu;
4650 params->hard_mtu = MLX5E_ETH_HARD_MTU;
4651 params->num_channels = min_t(unsigned int, MLX5E_MAX_NUM_CHANNELS / 2,
4655 /* Set an initial non-zero value, so that mlx5e_select_queue won't
4656 * divide by zero if called before first activating channels.
4658 priv->num_tc_x_num_ch = params->num_channels * params->num_tc;
4661 params->log_sq_size = is_kdump_kernel() ?
4662 MLX5E_PARAMS_MINIMUM_LOG_SQ_SIZE :
4663 MLX5E_PARAMS_DEFAULT_LOG_SQ_SIZE;
4664 MLX5E_SET_PFLAG(params, MLX5E_PFLAG_SKB_TX_MPWQE,
4665 MLX5_CAP_ETH(mdev, enhanced_multi_pkt_send_wqe));
4668 MLX5E_SET_PFLAG(params, MLX5E_PFLAG_XDP_TX_MPWQE,
4669 MLX5_CAP_ETH(mdev, enhanced_multi_pkt_send_wqe));
4671 /* set CQE compression */
4672 params->rx_cqe_compress_def = false;
4673 if (MLX5_CAP_GEN(mdev, cqe_compression) &&
4674 MLX5_CAP_GEN(mdev, vport_group_manager))
4675 params->rx_cqe_compress_def = slow_pci_heuristic(mdev);
4677 MLX5E_SET_PFLAG(params, MLX5E_PFLAG_RX_CQE_COMPRESS, params->rx_cqe_compress_def);
4678 MLX5E_SET_PFLAG(params, MLX5E_PFLAG_RX_NO_CSUM_COMPLETE, false);
4681 mlx5e_build_rq_params(mdev, params);
4684 if (MLX5_CAP_ETH(mdev, lro_cap) &&
4685 params->rq_wq_type == MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ) {
4686 /* No XSK params: checking the availability of striding RQ in general. */
4687 if (!mlx5e_rx_mpwqe_is_linear_skb(mdev, params, NULL))
4688 params->lro_en = !slow_pci_heuristic(mdev);
4690 params->lro_timeout = mlx5e_choose_lro_timeout(mdev, MLX5E_DEFAULT_LRO_TIMEOUT);
4692 /* CQ moderation params */
4693 rx_cq_period_mode = MLX5_CAP_GEN(mdev, cq_period_start_from_cqe) ?
4694 MLX5_CQ_PERIOD_MODE_START_FROM_CQE :
4695 MLX5_CQ_PERIOD_MODE_START_FROM_EQE;
4696 params->rx_dim_enabled = MLX5_CAP_GEN(mdev, cq_moderation);
4697 params->tx_dim_enabled = MLX5_CAP_GEN(mdev, cq_moderation);
4698 mlx5e_set_rx_cq_mode_params(params, rx_cq_period_mode);
4699 mlx5e_set_tx_cq_mode_params(params, MLX5_CQ_PERIOD_MODE_START_FROM_EQE);
4702 mlx5_query_min_inline(mdev, ¶ms->tx_min_inline_mode);
4705 mlx5e_build_rss_params(rss_params, params->num_channels);
4706 params->tunneled_offload_en =
4707 mlx5e_tunnel_inner_ft_supported(mdev);
4712 /* Do not update netdev->features directly in here
4713 * on mlx5e_attach_netdev() we will call mlx5e_update_features()
4714 * To update netdev->features please modify mlx5e_fix_features()
4718 static void mlx5e_set_netdev_dev_addr(struct net_device *netdev)
4720 struct mlx5e_priv *priv = netdev_priv(netdev);
4722 mlx5_query_mac_address(priv->mdev, netdev->dev_addr);
4723 if (is_zero_ether_addr(netdev->dev_addr) &&
4724 !MLX5_CAP_GEN(priv->mdev, vport_group_manager)) {
4725 eth_hw_addr_random(netdev);
4726 mlx5_core_info(priv->mdev, "Assigned random MAC address %pM\n", netdev->dev_addr);
4730 static int mlx5e_vxlan_set_port(struct net_device *netdev, unsigned int table,
4731 unsigned int entry, struct udp_tunnel_info *ti)
4733 struct mlx5e_priv *priv = netdev_priv(netdev);
4735 return mlx5_vxlan_add_port(priv->mdev->vxlan, ntohs(ti->port));
4738 static int mlx5e_vxlan_unset_port(struct net_device *netdev, unsigned int table,
4739 unsigned int entry, struct udp_tunnel_info *ti)
4741 struct mlx5e_priv *priv = netdev_priv(netdev);
4743 return mlx5_vxlan_del_port(priv->mdev->vxlan, ntohs(ti->port));
4746 void mlx5e_vxlan_set_netdev_info(struct mlx5e_priv *priv)
4748 if (!mlx5_vxlan_allowed(priv->mdev->vxlan))
4751 priv->nic_info.set_port = mlx5e_vxlan_set_port;
4752 priv->nic_info.unset_port = mlx5e_vxlan_unset_port;
4753 priv->nic_info.flags = UDP_TUNNEL_NIC_INFO_MAY_SLEEP |
4754 UDP_TUNNEL_NIC_INFO_STATIC_IANA_VXLAN;
4755 priv->nic_info.tables[0].tunnel_types = UDP_TUNNEL_TYPE_VXLAN;
4756 /* Don't count the space hard-coded to the IANA port */
4757 priv->nic_info.tables[0].n_entries =
4758 mlx5_vxlan_max_udp_ports(priv->mdev) - 1;
4760 priv->netdev->udp_tunnel_nic_info = &priv->nic_info;
4763 static bool mlx5e_tunnel_any_tx_proto_supported(struct mlx5_core_dev *mdev)
4767 for (tt = 0; tt < MLX5E_NUM_TUNNEL_TT; tt++) {
4768 if (mlx5e_tunnel_proto_supported_tx(mdev, mlx5e_get_proto_by_tunnel_type(tt)))
4771 return (mlx5_vxlan_allowed(mdev->vxlan) || mlx5_geneve_tx_allowed(mdev));
4774 static void mlx5e_build_nic_netdev(struct net_device *netdev)
4776 struct mlx5e_priv *priv = netdev_priv(netdev);
4777 struct mlx5_core_dev *mdev = priv->mdev;
4781 SET_NETDEV_DEV(netdev, mdev->device);
4783 netdev->netdev_ops = &mlx5e_netdev_ops;
4785 mlx5e_dcbnl_build_netdev(netdev);
4787 netdev->watchdog_timeo = 15 * HZ;
4789 netdev->ethtool_ops = &mlx5e_ethtool_ops;
4791 netdev->vlan_features |= NETIF_F_SG;
4792 netdev->vlan_features |= NETIF_F_HW_CSUM;
4793 netdev->vlan_features |= NETIF_F_GRO;
4794 netdev->vlan_features |= NETIF_F_TSO;
4795 netdev->vlan_features |= NETIF_F_TSO6;
4796 netdev->vlan_features |= NETIF_F_RXCSUM;
4797 netdev->vlan_features |= NETIF_F_RXHASH;
4799 netdev->mpls_features |= NETIF_F_SG;
4800 netdev->mpls_features |= NETIF_F_HW_CSUM;
4801 netdev->mpls_features |= NETIF_F_TSO;
4802 netdev->mpls_features |= NETIF_F_TSO6;
4804 netdev->hw_enc_features |= NETIF_F_HW_VLAN_CTAG_TX;
4805 netdev->hw_enc_features |= NETIF_F_HW_VLAN_CTAG_RX;
4807 if (!!MLX5_CAP_ETH(mdev, lro_cap) &&
4808 mlx5e_check_fragmented_striding_rq_cap(mdev))
4809 netdev->vlan_features |= NETIF_F_LRO;
4811 netdev->hw_features = netdev->vlan_features;
4812 netdev->hw_features |= NETIF_F_HW_VLAN_CTAG_TX;
4813 netdev->hw_features |= NETIF_F_HW_VLAN_CTAG_RX;
4814 netdev->hw_features |= NETIF_F_HW_VLAN_CTAG_FILTER;
4815 netdev->hw_features |= NETIF_F_HW_VLAN_STAG_TX;
4817 if (mlx5e_tunnel_any_tx_proto_supported(mdev)) {
4818 netdev->hw_enc_features |= NETIF_F_HW_CSUM;
4819 netdev->hw_enc_features |= NETIF_F_TSO;
4820 netdev->hw_enc_features |= NETIF_F_TSO6;
4821 netdev->hw_enc_features |= NETIF_F_GSO_PARTIAL;
4824 if (mlx5_vxlan_allowed(mdev->vxlan) || mlx5_geneve_tx_allowed(mdev)) {
4825 netdev->hw_features |= NETIF_F_GSO_UDP_TUNNEL;
4826 netdev->hw_enc_features |= NETIF_F_GSO_UDP_TUNNEL;
4827 netdev->vlan_features |= NETIF_F_GSO_UDP_TUNNEL;
4830 if (mlx5e_tunnel_proto_supported_tx(mdev, IPPROTO_GRE)) {
4831 netdev->hw_features |= NETIF_F_GSO_GRE;
4832 netdev->hw_enc_features |= NETIF_F_GSO_GRE;
4833 netdev->gso_partial_features |= NETIF_F_GSO_GRE;
4836 if (mlx5e_tunnel_proto_supported_tx(mdev, IPPROTO_IPIP)) {
4837 netdev->hw_features |= NETIF_F_GSO_IPXIP4 |
4839 netdev->hw_enc_features |= NETIF_F_GSO_IPXIP4 |
4841 netdev->gso_partial_features |= NETIF_F_GSO_IPXIP4 |
4845 netdev->hw_features |= NETIF_F_GSO_PARTIAL;
4846 netdev->gso_partial_features |= NETIF_F_GSO_UDP_L4;
4847 netdev->hw_features |= NETIF_F_GSO_UDP_L4;
4848 netdev->features |= NETIF_F_GSO_UDP_L4;
4850 mlx5_query_port_fcs(mdev, &fcs_supported, &fcs_enabled);
4853 netdev->hw_features |= NETIF_F_RXALL;
4855 if (MLX5_CAP_ETH(mdev, scatter_fcs))
4856 netdev->hw_features |= NETIF_F_RXFCS;
4858 netdev->features = netdev->hw_features;
4862 netdev->features &= ~NETIF_F_RXALL;
4863 netdev->features &= ~NETIF_F_LRO;
4864 netdev->features &= ~NETIF_F_RXFCS;
4866 #define FT_CAP(f) MLX5_CAP_FLOWTABLE(mdev, flow_table_properties_nic_receive.f)
4867 if (FT_CAP(flow_modify_en) &&
4868 FT_CAP(modify_root) &&
4869 FT_CAP(identified_miss_table_mode) &&
4870 FT_CAP(flow_table_modify)) {
4871 #if IS_ENABLED(CONFIG_MLX5_CLS_ACT)
4872 netdev->hw_features |= NETIF_F_HW_TC;
4874 #ifdef CONFIG_MLX5_EN_ARFS
4875 netdev->hw_features |= NETIF_F_NTUPLE;
4878 if (mlx5_qos_is_supported(mdev))
4879 netdev->features |= NETIF_F_HW_TC;
4881 netdev->features |= NETIF_F_HIGHDMA;
4882 netdev->features |= NETIF_F_HW_VLAN_STAG_FILTER;
4884 netdev->priv_flags |= IFF_UNICAST_FLT;
4886 mlx5e_set_netdev_dev_addr(netdev);
4887 mlx5e_ipsec_build_netdev(priv);
4888 mlx5e_tls_build_netdev(priv);
4891 void mlx5e_create_q_counters(struct mlx5e_priv *priv)
4893 u32 out[MLX5_ST_SZ_DW(alloc_q_counter_out)] = {};
4894 u32 in[MLX5_ST_SZ_DW(alloc_q_counter_in)] = {};
4895 struct mlx5_core_dev *mdev = priv->mdev;
4898 MLX5_SET(alloc_q_counter_in, in, opcode, MLX5_CMD_OP_ALLOC_Q_COUNTER);
4899 err = mlx5_cmd_exec_inout(mdev, alloc_q_counter, in, out);
4902 MLX5_GET(alloc_q_counter_out, out, counter_set_id);
4904 err = mlx5_cmd_exec_inout(mdev, alloc_q_counter, in, out);
4906 priv->drop_rq_q_counter =
4907 MLX5_GET(alloc_q_counter_out, out, counter_set_id);
4910 void mlx5e_destroy_q_counters(struct mlx5e_priv *priv)
4912 u32 in[MLX5_ST_SZ_DW(dealloc_q_counter_in)] = {};
4914 MLX5_SET(dealloc_q_counter_in, in, opcode,
4915 MLX5_CMD_OP_DEALLOC_Q_COUNTER);
4916 if (priv->q_counter) {
4917 MLX5_SET(dealloc_q_counter_in, in, counter_set_id,
4919 mlx5_cmd_exec_in(priv->mdev, dealloc_q_counter, in);
4922 if (priv->drop_rq_q_counter) {
4923 MLX5_SET(dealloc_q_counter_in, in, counter_set_id,
4924 priv->drop_rq_q_counter);
4925 mlx5_cmd_exec_in(priv->mdev, dealloc_q_counter, in);
4929 static int mlx5e_nic_init(struct mlx5_core_dev *mdev,
4930 struct net_device *netdev)
4932 struct mlx5e_priv *priv = netdev_priv(netdev);
4933 struct devlink_port *dl_port;
4936 mlx5e_build_nic_params(priv, &priv->xsk, netdev->mtu);
4937 mlx5e_vxlan_set_netdev_info(priv);
4939 mlx5e_timestamp_init(priv);
4941 err = mlx5e_ipsec_init(priv);
4943 mlx5_core_err(mdev, "IPSec initialization failed, %d\n", err);
4945 err = mlx5e_tls_init(priv);
4947 mlx5_core_err(mdev, "TLS initialization failed, %d\n", err);
4949 dl_port = mlx5e_devlink_get_dl_port(priv);
4950 if (dl_port->registered)
4951 mlx5e_health_create_reporters(priv);
4956 static void mlx5e_nic_cleanup(struct mlx5e_priv *priv)
4958 struct devlink_port *dl_port = mlx5e_devlink_get_dl_port(priv);
4960 if (dl_port->registered)
4961 mlx5e_health_destroy_reporters(priv);
4962 mlx5e_tls_cleanup(priv);
4963 mlx5e_ipsec_cleanup(priv);
4966 static int mlx5e_init_nic_rx(struct mlx5e_priv *priv)
4968 struct mlx5_core_dev *mdev = priv->mdev;
4969 u16 max_nch = priv->max_nch;
4972 mlx5e_create_q_counters(priv);
4974 err = mlx5e_open_drop_rq(priv, &priv->drop_rq);
4976 mlx5_core_err(mdev, "open drop rq failed, %d\n", err);
4977 goto err_destroy_q_counters;
4980 err = mlx5e_create_indirect_rqt(priv);
4982 goto err_close_drop_rq;
4984 err = mlx5e_create_direct_rqts(priv, priv->direct_tir, max_nch);
4986 goto err_destroy_indirect_rqts;
4988 err = mlx5e_create_indirect_tirs(priv, true);
4990 goto err_destroy_direct_rqts;
4992 err = mlx5e_create_direct_tirs(priv, priv->direct_tir, max_nch);
4994 goto err_destroy_indirect_tirs;
4996 err = mlx5e_create_direct_rqts(priv, priv->xsk_tir, max_nch);
4998 goto err_destroy_direct_tirs;
5000 err = mlx5e_create_direct_tirs(priv, priv->xsk_tir, max_nch);
5002 goto err_destroy_xsk_rqts;
5004 err = mlx5e_create_direct_rqts(priv, &priv->ptp_tir, 1);
5006 goto err_destroy_xsk_tirs;
5008 err = mlx5e_create_direct_tirs(priv, &priv->ptp_tir, 1);
5010 goto err_destroy_ptp_rqt;
5012 err = mlx5e_create_flow_steering(priv);
5014 mlx5_core_warn(mdev, "create flow steering failed, %d\n", err);
5015 goto err_destroy_ptp_direct_tir;
5018 err = mlx5e_tc_nic_init(priv);
5020 goto err_destroy_flow_steering;
5022 err = mlx5e_accel_init_rx(priv);
5024 goto err_tc_nic_cleanup;
5026 #ifdef CONFIG_MLX5_EN_ARFS
5027 priv->netdev->rx_cpu_rmap = mlx5_eq_table_get_rmap(priv->mdev);
5033 mlx5e_tc_nic_cleanup(priv);
5034 err_destroy_flow_steering:
5035 mlx5e_destroy_flow_steering(priv);
5036 err_destroy_ptp_direct_tir:
5037 mlx5e_destroy_direct_tirs(priv, &priv->ptp_tir, 1);
5038 err_destroy_ptp_rqt:
5039 mlx5e_destroy_direct_rqts(priv, &priv->ptp_tir, 1);
5040 err_destroy_xsk_tirs:
5041 mlx5e_destroy_direct_tirs(priv, priv->xsk_tir, max_nch);
5042 err_destroy_xsk_rqts:
5043 mlx5e_destroy_direct_rqts(priv, priv->xsk_tir, max_nch);
5044 err_destroy_direct_tirs:
5045 mlx5e_destroy_direct_tirs(priv, priv->direct_tir, max_nch);
5046 err_destroy_indirect_tirs:
5047 mlx5e_destroy_indirect_tirs(priv);
5048 err_destroy_direct_rqts:
5049 mlx5e_destroy_direct_rqts(priv, priv->direct_tir, max_nch);
5050 err_destroy_indirect_rqts:
5051 mlx5e_destroy_rqt(priv, &priv->indir_rqt);
5053 mlx5e_close_drop_rq(&priv->drop_rq);
5054 err_destroy_q_counters:
5055 mlx5e_destroy_q_counters(priv);
5059 static void mlx5e_cleanup_nic_rx(struct mlx5e_priv *priv)
5061 u16 max_nch = priv->max_nch;
5063 mlx5e_accel_cleanup_rx(priv);
5064 mlx5e_tc_nic_cleanup(priv);
5065 mlx5e_destroy_flow_steering(priv);
5066 mlx5e_destroy_direct_tirs(priv, &priv->ptp_tir, 1);
5067 mlx5e_destroy_direct_rqts(priv, &priv->ptp_tir, 1);
5068 mlx5e_destroy_direct_tirs(priv, priv->xsk_tir, max_nch);
5069 mlx5e_destroy_direct_rqts(priv, priv->xsk_tir, max_nch);
5070 mlx5e_destroy_direct_tirs(priv, priv->direct_tir, max_nch);
5071 mlx5e_destroy_indirect_tirs(priv);
5072 mlx5e_destroy_direct_rqts(priv, priv->direct_tir, max_nch);
5073 mlx5e_destroy_rqt(priv, &priv->indir_rqt);
5074 mlx5e_close_drop_rq(&priv->drop_rq);
5075 mlx5e_destroy_q_counters(priv);
5078 static int mlx5e_init_nic_tx(struct mlx5e_priv *priv)
5082 err = mlx5e_create_tises(priv);
5084 mlx5_core_warn(priv->mdev, "create tises failed, %d\n", err);
5088 mlx5e_dcbnl_initialize(priv);
5092 static void mlx5e_nic_enable(struct mlx5e_priv *priv)
5094 struct net_device *netdev = priv->netdev;
5095 struct mlx5_core_dev *mdev = priv->mdev;
5097 mlx5e_init_l2_addr(priv);
5099 /* Marking the link as currently not needed by the Driver */
5100 if (!netif_running(netdev))
5101 mlx5e_modify_admin_state(mdev, MLX5_PORT_DOWN);
5103 mlx5e_set_netdev_mtu_boundaries(priv);
5104 mlx5e_set_dev_port_mtu(priv);
5106 mlx5_lag_add(mdev, netdev);
5108 mlx5e_enable_async_events(priv);
5109 mlx5e_enable_blocking_events(priv);
5110 if (mlx5e_monitor_counter_supported(priv))
5111 mlx5e_monitor_counter_init(priv);
5113 mlx5e_hv_vhca_stats_create(priv);
5114 if (netdev->reg_state != NETREG_REGISTERED)
5116 mlx5e_dcbnl_init_app(priv);
5118 mlx5e_nic_set_rx_mode(priv);
5121 if (netif_running(netdev))
5123 udp_tunnel_nic_reset_ntf(priv->netdev);
5124 netif_device_attach(netdev);
5128 static void mlx5e_nic_disable(struct mlx5e_priv *priv)
5130 struct mlx5_core_dev *mdev = priv->mdev;
5132 if (priv->netdev->reg_state == NETREG_REGISTERED)
5133 mlx5e_dcbnl_delete_app(priv);
5136 if (netif_running(priv->netdev))
5137 mlx5e_close(priv->netdev);
5138 netif_device_detach(priv->netdev);
5141 mlx5e_nic_set_rx_mode(priv);
5143 mlx5e_hv_vhca_stats_destroy(priv);
5144 if (mlx5e_monitor_counter_supported(priv))
5145 mlx5e_monitor_counter_cleanup(priv);
5147 mlx5e_disable_blocking_events(priv);
5148 if (priv->en_trap) {
5149 mlx5e_deactivate_trap(priv);
5150 mlx5e_close_trap(priv->en_trap);
5151 priv->en_trap = NULL;
5153 mlx5e_disable_async_events(priv);
5154 mlx5_lag_remove(mdev);
5155 mlx5_vxlan_reset_to_default(mdev->vxlan);
5158 int mlx5e_update_nic_rx(struct mlx5e_priv *priv)
5160 return mlx5e_refresh_tirs(priv, false, false);
5163 static const struct mlx5e_profile mlx5e_nic_profile = {
5164 .init = mlx5e_nic_init,
5165 .cleanup = mlx5e_nic_cleanup,
5166 .init_rx = mlx5e_init_nic_rx,
5167 .cleanup_rx = mlx5e_cleanup_nic_rx,
5168 .init_tx = mlx5e_init_nic_tx,
5169 .cleanup_tx = mlx5e_cleanup_nic_tx,
5170 .enable = mlx5e_nic_enable,
5171 .disable = mlx5e_nic_disable,
5172 .update_rx = mlx5e_update_nic_rx,
5173 .update_stats = mlx5e_stats_update_ndo_stats,
5174 .update_carrier = mlx5e_update_carrier,
5175 .rx_handlers = &mlx5e_rx_handlers_nic,
5176 .max_tc = MLX5E_MAX_NUM_TC,
5177 .rq_groups = MLX5E_NUM_RQ_GROUPS(XSK),
5178 .stats_grps = mlx5e_nic_stats_grps,
5179 .stats_grps_num = mlx5e_nic_stats_grps_num,
5180 .rx_ptp_support = true,
5183 /* mlx5e generic netdev management API (move to en_common.c) */
5184 int mlx5e_priv_init(struct mlx5e_priv *priv,
5185 struct net_device *netdev,
5186 struct mlx5_core_dev *mdev)
5190 priv->netdev = netdev;
5191 priv->msglevel = MLX5E_MSG_LEVEL;
5192 priv->max_opened_tc = 1;
5194 if (!alloc_cpumask_var(&priv->scratchpad.cpumask, GFP_KERNEL))
5197 mutex_init(&priv->state_lock);
5198 hash_init(priv->htb.qos_tc2node);
5199 INIT_WORK(&priv->update_carrier_work, mlx5e_update_carrier_work);
5200 INIT_WORK(&priv->set_rx_mode_work, mlx5e_set_rx_mode_work);
5201 INIT_WORK(&priv->tx_timeout_work, mlx5e_tx_timeout_work);
5202 INIT_WORK(&priv->update_stats_work, mlx5e_update_stats_work);
5204 priv->wq = create_singlethread_workqueue("mlx5e");
5206 goto err_free_cpumask;
5211 free_cpumask_var(priv->scratchpad.cpumask);
5216 void mlx5e_priv_cleanup(struct mlx5e_priv *priv)
5220 /* bail if change profile failed and also rollback failed */
5224 destroy_workqueue(priv->wq);
5225 free_cpumask_var(priv->scratchpad.cpumask);
5227 for (i = 0; i < priv->htb.max_qos_sqs; i++)
5228 kfree(priv->htb.qos_sq_stats[i]);
5229 kvfree(priv->htb.qos_sq_stats);
5231 memset(priv, 0, sizeof(*priv));
5235 mlx5e_create_netdev(struct mlx5_core_dev *mdev, unsigned int txqs, unsigned int rxqs)
5237 struct net_device *netdev;
5240 netdev = alloc_etherdev_mqs(sizeof(struct mlx5e_priv), txqs, rxqs);
5242 mlx5_core_err(mdev, "alloc_etherdev_mqs() failed\n");
5246 err = mlx5e_priv_init(netdev_priv(netdev), netdev, mdev);
5248 mlx5_core_err(mdev, "mlx5e_priv_init failed, err=%d\n", err);
5249 goto err_free_netdev;
5252 netif_carrier_off(netdev);
5253 dev_net_set(netdev, mlx5_core_net(mdev));
5258 free_netdev(netdev);
5263 static void mlx5e_update_features(struct net_device *netdev)
5265 if (netdev->reg_state != NETREG_REGISTERED)
5266 return; /* features will be updated on netdev registration */
5269 netdev_update_features(netdev);
5273 static void mlx5e_reset_channels(struct net_device *netdev)
5275 netdev_reset_tc(netdev);
5278 int mlx5e_attach_netdev(struct mlx5e_priv *priv)
5280 const bool take_rtnl = priv->netdev->reg_state == NETREG_REGISTERED;
5281 const struct mlx5e_profile *profile = priv->profile;
5285 clear_bit(MLX5E_STATE_DESTROYING, &priv->state);
5287 /* max number of channels may have changed */
5288 max_nch = mlx5e_get_max_num_channels(priv->mdev);
5289 if (priv->channels.params.num_channels > max_nch) {
5290 mlx5_core_warn(priv->mdev, "MLX5E: Reducing number of channels to %d\n", max_nch);
5291 /* Reducing the number of channels - RXFH has to be reset, and
5292 * mlx5e_num_channels_changed below will build the RQT.
5294 priv->netdev->priv_flags &= ~IFF_RXFH_CONFIGURED;
5295 priv->channels.params.num_channels = max_nch;
5297 /* 1. Set the real number of queues in the kernel the first time.
5298 * 2. Set our default XPS cpumask.
5301 * rtnl_lock is required by netif_set_real_num_*_queues in case the
5302 * netdev has been registered by this point (if this function was called
5303 * in the reload or resume flow).
5307 err = mlx5e_num_channels_changed(priv);
5313 err = profile->init_tx(priv);
5317 err = profile->init_rx(priv);
5319 goto err_cleanup_tx;
5321 if (profile->enable)
5322 profile->enable(priv);
5324 mlx5e_update_features(priv->netdev);
5329 profile->cleanup_tx(priv);
5332 mlx5e_reset_channels(priv->netdev);
5333 set_bit(MLX5E_STATE_DESTROYING, &priv->state);
5334 cancel_work_sync(&priv->update_stats_work);
5338 void mlx5e_detach_netdev(struct mlx5e_priv *priv)
5340 const struct mlx5e_profile *profile = priv->profile;
5342 set_bit(MLX5E_STATE_DESTROYING, &priv->state);
5344 if (profile->disable)
5345 profile->disable(priv);
5346 flush_workqueue(priv->wq);
5348 profile->cleanup_rx(priv);
5349 profile->cleanup_tx(priv);
5350 mlx5e_reset_channels(priv->netdev);
5351 cancel_work_sync(&priv->update_stats_work);
5355 mlx5e_netdev_attach_profile(struct net_device *netdev, struct mlx5_core_dev *mdev,
5356 const struct mlx5e_profile *new_profile, void *new_ppriv)
5358 struct mlx5e_priv *priv = netdev_priv(netdev);
5361 err = mlx5e_priv_init(priv, netdev, mdev);
5363 mlx5_core_err(mdev, "mlx5e_priv_init failed, err=%d\n", err);
5366 netif_carrier_off(netdev);
5367 priv->profile = new_profile;
5368 priv->ppriv = new_ppriv;
5369 err = new_profile->init(priv->mdev, priv->netdev);
5372 err = mlx5e_attach_netdev(priv);
5374 goto profile_cleanup;
5378 new_profile->cleanup(priv);
5380 mlx5e_priv_cleanup(priv);
5384 int mlx5e_netdev_change_profile(struct mlx5e_priv *priv,
5385 const struct mlx5e_profile *new_profile, void *new_ppriv)
5387 unsigned int new_max_nch = mlx5e_calc_max_nch(priv, new_profile);
5388 const struct mlx5e_profile *orig_profile = priv->profile;
5389 struct net_device *netdev = priv->netdev;
5390 struct mlx5_core_dev *mdev = priv->mdev;
5391 void *orig_ppriv = priv->ppriv;
5392 int err, rollback_err;
5395 if (new_max_nch != priv->max_nch) {
5396 netdev_warn(netdev, "%s: Replacing profile with different max channels\n",
5401 /* cleanup old profile */
5402 mlx5e_detach_netdev(priv);
5403 priv->profile->cleanup(priv);
5404 mlx5e_priv_cleanup(priv);
5406 err = mlx5e_netdev_attach_profile(netdev, mdev, new_profile, new_ppriv);
5407 if (err) { /* roll back to original profile */
5408 netdev_warn(netdev, "%s: new profile init failed, %d\n", __func__, err);
5415 rollback_err = mlx5e_netdev_attach_profile(netdev, mdev, orig_profile, orig_ppriv);
5417 netdev_err(netdev, "%s: failed to rollback to orig profile, %d\n",
5418 __func__, rollback_err);
5422 void mlx5e_netdev_attach_nic_profile(struct mlx5e_priv *priv)
5424 mlx5e_netdev_change_profile(priv, &mlx5e_nic_profile, NULL);
5427 void mlx5e_destroy_netdev(struct mlx5e_priv *priv)
5429 struct net_device *netdev = priv->netdev;
5431 mlx5e_priv_cleanup(priv);
5432 free_netdev(netdev);
5435 static int mlx5e_resume(struct auxiliary_device *adev)
5437 struct mlx5_adev *edev = container_of(adev, struct mlx5_adev, adev);
5438 struct mlx5e_priv *priv = dev_get_drvdata(&adev->dev);
5439 struct net_device *netdev = priv->netdev;
5440 struct mlx5_core_dev *mdev = edev->mdev;
5443 if (netif_device_present(netdev))
5446 err = mlx5e_create_mdev_resources(mdev);
5450 err = mlx5e_attach_netdev(priv);
5452 mlx5e_destroy_mdev_resources(mdev);
5459 static int mlx5e_suspend(struct auxiliary_device *adev, pm_message_t state)
5461 struct mlx5e_priv *priv = dev_get_drvdata(&adev->dev);
5462 struct net_device *netdev = priv->netdev;
5463 struct mlx5_core_dev *mdev = priv->mdev;
5465 if (!netif_device_present(netdev))
5468 mlx5e_detach_netdev(priv);
5469 mlx5e_destroy_mdev_resources(mdev);
5473 static int mlx5e_probe(struct auxiliary_device *adev,
5474 const struct auxiliary_device_id *id)
5476 struct mlx5_adev *edev = container_of(adev, struct mlx5_adev, adev);
5477 const struct mlx5e_profile *profile = &mlx5e_nic_profile;
5478 struct mlx5_core_dev *mdev = edev->mdev;
5479 struct net_device *netdev;
5480 pm_message_t state = {};
5481 unsigned int txqs, rxqs, ptp_txqs = 0;
5482 struct mlx5e_priv *priv;
5487 if (MLX5_CAP_GEN(mdev, ts_cqe_to_dest_cqn))
5488 ptp_txqs = profile->max_tc;
5490 if (mlx5_qos_is_supported(mdev))
5491 qos_sqs = mlx5e_qos_max_leaf_nodes(mdev);
5493 nch = mlx5e_get_max_num_channels(mdev);
5494 txqs = nch * profile->max_tc + ptp_txqs + qos_sqs;
5495 rxqs = nch * profile->rq_groups;
5496 netdev = mlx5e_create_netdev(mdev, txqs, rxqs);
5498 mlx5_core_err(mdev, "mlx5e_create_netdev failed\n");
5502 mlx5e_build_nic_netdev(netdev);
5504 priv = netdev_priv(netdev);
5505 dev_set_drvdata(&adev->dev, priv);
5507 priv->profile = profile;
5510 err = mlx5e_devlink_port_register(priv);
5512 mlx5_core_err(mdev, "mlx5e_devlink_port_register failed, %d\n", err);
5513 goto err_destroy_netdev;
5516 err = profile->init(mdev, netdev);
5518 mlx5_core_err(mdev, "mlx5e_nic_profile init failed, %d\n", err);
5519 goto err_devlink_cleanup;
5522 err = mlx5e_resume(adev);
5524 mlx5_core_err(mdev, "mlx5e_resume failed, %d\n", err);
5525 goto err_profile_cleanup;
5528 err = register_netdev(netdev);
5530 mlx5_core_err(mdev, "register_netdev failed, %d\n", err);
5534 mlx5e_devlink_port_type_eth_set(priv);
5536 mlx5e_dcbnl_init_app(priv);
5537 mlx5_uplink_netdev_set(mdev, netdev);
5541 mlx5e_suspend(adev, state);
5542 err_profile_cleanup:
5543 profile->cleanup(priv);
5544 err_devlink_cleanup:
5545 mlx5e_devlink_port_unregister(priv);
5547 mlx5e_destroy_netdev(priv);
5551 static void mlx5e_remove(struct auxiliary_device *adev)
5553 struct mlx5e_priv *priv = dev_get_drvdata(&adev->dev);
5554 pm_message_t state = {};
5556 mlx5e_dcbnl_delete_app(priv);
5557 unregister_netdev(priv->netdev);
5558 mlx5e_suspend(adev, state);
5559 priv->profile->cleanup(priv);
5560 mlx5e_devlink_port_unregister(priv);
5561 mlx5e_destroy_netdev(priv);
5564 static const struct auxiliary_device_id mlx5e_id_table[] = {
5565 { .name = MLX5_ADEV_NAME ".eth", },
5569 MODULE_DEVICE_TABLE(auxiliary, mlx5e_id_table);
5571 static struct auxiliary_driver mlx5e_driver = {
5573 .probe = mlx5e_probe,
5574 .remove = mlx5e_remove,
5575 .suspend = mlx5e_suspend,
5576 .resume = mlx5e_resume,
5577 .id_table = mlx5e_id_table,
5580 int mlx5e_init(void)
5584 mlx5e_ipsec_build_inverse_table();
5585 mlx5e_build_ptys2ethtool_map();
5586 ret = auxiliary_driver_register(&mlx5e_driver);
5590 ret = mlx5e_rep_init();
5592 auxiliary_driver_unregister(&mlx5e_driver);
5596 void mlx5e_cleanup(void)
5598 mlx5e_rep_cleanup();
5599 auxiliary_driver_unregister(&mlx5e_driver);