drivers/net/ethernet/mellanox/mlx5/core/en_main.c

   1 /*
   2  * Copyright (c) 2015-2016, Mellanox Technologies. All rights reserved.
   3  *
   4  * This software is available to you under a choice of one of two
   5  * licenses.  You may choose to be licensed under the terms of the GNU
   6  * General Public License (GPL) Version 2, available from the file
   7  * COPYING in the main directory of this source tree, or the
   8  * OpenIB.org BSD license below:
   9  *
  10  *     Redistribution and use in source and binary forms, with or
  11  *     without modification, are permitted provided that the following
  12  *     conditions are met:
  13  *
  14  *      - Redistributions of source code must retain the above
  15  *        copyright notice, this list of conditions and the following
  16  *        disclaimer.
  17  *
  18  *      - Redistributions in binary form must reproduce the above
  19  *        copyright notice, this list of conditions and the following
  20  *        disclaimer in the documentation and/or other materials
  21  *        provided with the distribution.
  22  *
  23  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  24  * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  25  * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
  26  * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
  27  * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
  28  * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
  29  * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
  30  * SOFTWARE.
  31  */
  32
  33 #include <net/tc_act/tc_gact.h>
  34 #include <net/pkt_cls.h>
  35 #include <linux/mlx5/fs.h>
  36 #include <net/vxlan.h>
  37 #include <net/geneve.h>
  38 #include <linux/bpf.h>
  39 #include <linux/if_bridge.h>
  40 #include <net/page_pool.h>
  41 #include <net/xdp_sock_drv.h>
  42 #include "eswitch.h"
  43 #include "en.h"
  44 #include "en/txrx.h"
  45 #include "en_tc.h"
  46 #include "en_rep.h"
  47 #include "en_accel/ipsec.h"
  48 #include "en_accel/en_accel.h"
  49 #include "en_accel/tls.h"
  50 #include "accel/ipsec.h"
  51 #include "accel/tls.h"
  52 #include "lib/vxlan.h"
  53 #include "lib/clock.h"
  54 #include "en/port.h"
  55 #include "en/xdp.h"
  56 #include "lib/eq.h"
  57 #include "en/monitor_stats.h"
  58 #include "en/health.h"
  59 #include "en/params.h"
  60 #include "en/xsk/pool.h"
  61 #include "en/xsk/setup.h"
  62 #include "en/xsk/rx.h"
  63 #include "en/xsk/tx.h"
  64 #include "en/hv_vhca_stats.h"
  65 #include "en/devlink.h"
  66 #include "lib/mlx5.h"
  67 #include "en/ptp.h"
  68 #include "qos.h"
  69 #include "en/trap.h"
  70 #include "fpga/ipsec.h"
  71
  72 bool mlx5e_check_fragmented_striding_rq_cap(struct mlx5_core_dev *mdev)
  73 {
  74         bool striding_rq_umr = MLX5_CAP_GEN(mdev, striding_rq) &&
  75                 MLX5_CAP_GEN(mdev, umr_ptr_rlky) &&
  76                 MLX5_CAP_ETH(mdev, reg_umr_sq);
  77         u16 max_wqe_sz_cap = MLX5_CAP_GEN(mdev, max_wqe_sz_sq);
  78         bool inline_umr = MLX5E_UMR_WQE_INLINE_SZ <= max_wqe_sz_cap;
  79
  80         if (!striding_rq_umr)
  81                 return false;
  82         if (!inline_umr) {
  83                 mlx5_core_warn(mdev, "Cannot support Striding RQ: UMR WQE size (%d) exceeds maximum supported (%d).\n",
  84                                (int)MLX5E_UMR_WQE_INLINE_SZ, max_wqe_sz_cap);
  85                 return false;
  86         }
  87         return true;
  88 }
  89
  90 void mlx5e_update_carrier(struct mlx5e_priv *priv)
  91 {
  92         struct mlx5_core_dev *mdev = priv->mdev;
  93         u8 port_state;
  94
  95         port_state = mlx5_query_vport_state(mdev,
  96                                             MLX5_VPORT_STATE_OP_MOD_VNIC_VPORT,
  97                                             0);
  98
  99         if (port_state == VPORT_STATE_UP) {
 100                 netdev_info(priv->netdev, "Link up\n");
 101                 netif_carrier_on(priv->netdev);
 102         } else {
 103                 netdev_info(priv->netdev, "Link down\n");
 104                 netif_carrier_off(priv->netdev);
 105         }
 106 }
 107
 108 static void mlx5e_update_carrier_work(struct work_struct *work)
 109 {
 110         struct mlx5e_priv *priv = container_of(work, struct mlx5e_priv,
 111                                                update_carrier_work);
 112
 113         mutex_lock(&priv->state_lock);
 114         if (test_bit(MLX5E_STATE_OPENED, &priv->state))
 115                 if (priv->profile->update_carrier)
 116                         priv->profile->update_carrier(priv);
 117         mutex_unlock(&priv->state_lock);
 118 }
 119
 120 static void mlx5e_update_stats_work(struct work_struct *work)
 121 {
 122         struct mlx5e_priv *priv = container_of(work, struct mlx5e_priv,
 123                                                update_stats_work);
 124
 125         mutex_lock(&priv->state_lock);
 126         priv->profile->update_stats(priv);
 127         mutex_unlock(&priv->state_lock);
 128 }
 129
 130 void mlx5e_queue_update_stats(struct mlx5e_priv *priv)
 131 {
 132         if (!priv->profile->update_stats)
 133                 return;
 134
 135         if (unlikely(test_bit(MLX5E_STATE_DESTROYING, &priv->state)))
 136                 return;
 137
 138         queue_work(priv->wq, &priv->update_stats_work);
 139 }
 140
 141 static int async_event(struct notifier_block *nb, unsigned long event, void *data)
 142 {
 143         struct mlx5e_priv *priv = container_of(nb, struct mlx5e_priv, events_nb);
 144         struct mlx5_eqe   *eqe = data;
 145
 146         if (event != MLX5_EVENT_TYPE_PORT_CHANGE)
 147                 return NOTIFY_DONE;
 148
 149         switch (eqe->sub_type) {
 150         case MLX5_PORT_CHANGE_SUBTYPE_DOWN:
 151         case MLX5_PORT_CHANGE_SUBTYPE_ACTIVE:
 152                 queue_work(priv->wq, &priv->update_carrier_work);
 153                 break;
 154         default:
 155                 return NOTIFY_DONE;
 156         }
 157
 158         return NOTIFY_OK;
 159 }
 160
 161 static void mlx5e_enable_async_events(struct mlx5e_priv *priv)
 162 {
 163         priv->events_nb.notifier_call = async_event;
 164         mlx5_notifier_register(priv->mdev, &priv->events_nb);
 165 }
 166
 167 static void mlx5e_disable_async_events(struct mlx5e_priv *priv)
 168 {
 169         mlx5_notifier_unregister(priv->mdev, &priv->events_nb);
 170 }
 171
 172 static int blocking_event(struct notifier_block *nb, unsigned long event, void *data)
 173 {
 174         struct mlx5e_priv *priv = container_of(nb, struct mlx5e_priv, blocking_events_nb);
 175         int err;
 176
 177         switch (event) {
 178         case MLX5_DRIVER_EVENT_TYPE_TRAP:
 179                 err = mlx5e_handle_trap_event(priv, data);
 180                 break;
 181         default:
 182                 netdev_warn(priv->netdev, "Sync event: Unknown event %ld\n", event);
 183                 err = -EINVAL;
 184         }
 185         return err;
 186 }
 187
 188 static void mlx5e_enable_blocking_events(struct mlx5e_priv *priv)
 189 {
 190         priv->blocking_events_nb.notifier_call = blocking_event;
 191         mlx5_blocking_notifier_register(priv->mdev, &priv->blocking_events_nb);
 192 }
 193
 194 static void mlx5e_disable_blocking_events(struct mlx5e_priv *priv)
 195 {
 196         mlx5_blocking_notifier_unregister(priv->mdev, &priv->blocking_events_nb);
 197 }
 198
 199 static inline void mlx5e_build_umr_wqe(struct mlx5e_rq *rq,
 200                                        struct mlx5e_icosq *sq,
 201                                        struct mlx5e_umr_wqe *wqe)
 202 {
 203         struct mlx5_wqe_ctrl_seg      *cseg = &wqe->ctrl;
 204         struct mlx5_wqe_umr_ctrl_seg *ucseg = &wqe->uctrl;
 205         u8 ds_cnt = DIV_ROUND_UP(MLX5E_UMR_WQE_INLINE_SZ, MLX5_SEND_WQE_DS);
 206
 207         cseg->qpn_ds    = cpu_to_be32((sq->sqn << MLX5_WQE_CTRL_QPN_SHIFT) |
 208                                       ds_cnt);
 209         cseg->umr_mkey  = rq->mkey_be;
 210
 211         ucseg->flags = MLX5_UMR_TRANSLATION_OFFSET_EN | MLX5_UMR_INLINE;
 212         ucseg->xlt_octowords =
 213                 cpu_to_be16(MLX5_MTT_OCTW(MLX5_MPWRQ_PAGES_PER_WQE));
 214         ucseg->mkey_mask     = cpu_to_be64(MLX5_MKEY_MASK_FREE);
 215 }
 216
 217 static int mlx5e_rq_alloc_mpwqe_info(struct mlx5e_rq *rq, int node)
 218 {
 219         int wq_sz = mlx5_wq_ll_get_size(&rq->mpwqe.wq);
 220
 221         rq->mpwqe.info = kvzalloc_node(array_size(wq_sz,
 222                                                   sizeof(*rq->mpwqe.info)),
 223                                        GFP_KERNEL, node);
 224         if (!rq->mpwqe.info)
 225                 return -ENOMEM;
 226
 227         mlx5e_build_umr_wqe(rq, rq->icosq, &rq->mpwqe.umr_wqe);
 228
 229         return 0;
 230 }
 231
 232 static int mlx5e_create_umr_mkey(struct mlx5_core_dev *mdev,
 233                                  u64 npages, u8 page_shift,
 234                                  struct mlx5_core_mkey *umr_mkey,
 235                                  dma_addr_t filler_addr)
 236 {
 237         struct mlx5_mtt *mtt;
 238         int inlen;
 239         void *mkc;
 240         u32 *in;
 241         int err;
 242         int i;
 243
 244         inlen = MLX5_ST_SZ_BYTES(create_mkey_in) + sizeof(*mtt) * npages;
 245
 246         in = kvzalloc(inlen, GFP_KERNEL);
 247         if (!in)
 248                 return -ENOMEM;
 249
 250         mkc = MLX5_ADDR_OF(create_mkey_in, in, memory_key_mkey_entry);
 251
 252         MLX5_SET(mkc, mkc, free, 1);
 253         MLX5_SET(mkc, mkc, umr_en, 1);
 254         MLX5_SET(mkc, mkc, lw, 1);
 255         MLX5_SET(mkc, mkc, lr, 1);
 256         MLX5_SET(mkc, mkc, access_mode_1_0, MLX5_MKC_ACCESS_MODE_MTT);
 257         mlx5e_mkey_set_relaxed_ordering(mdev, mkc);
 258         MLX5_SET(mkc, mkc, qpn, 0xffffff);
 259         MLX5_SET(mkc, mkc, pd, mdev->mlx5e_res.hw_objs.pdn);
 260         MLX5_SET64(mkc, mkc, len, npages << page_shift);
 261         MLX5_SET(mkc, mkc, translations_octword_size,
 262                  MLX5_MTT_OCTW(npages));
 263         MLX5_SET(mkc, mkc, log_page_size, page_shift);
 264         MLX5_SET(create_mkey_in, in, translations_octword_actual_size,
 265                  MLX5_MTT_OCTW(npages));
 266
 267         /* Initialize the mkey with all MTTs pointing to a default
 268          * page (filler_addr). When the channels are activated, UMR
 269          * WQEs will redirect the RX WQEs to the actual memory from
 270          * the RQ's pool, while the gaps (wqe_overflow) remain mapped
 271          * to the default page.
 272          */
 273         mtt = MLX5_ADDR_OF(create_mkey_in, in, klm_pas_mtt);
 274         for (i = 0 ; i < npages ; i++)
 275                 mtt[i].ptag = cpu_to_be64(filler_addr);
 276
 277         err = mlx5_core_create_mkey(mdev, umr_mkey, in, inlen);
 278
 279         kvfree(in);
 280         return err;
 281 }
 282
 283 static int mlx5e_create_rq_umr_mkey(struct mlx5_core_dev *mdev, struct mlx5e_rq *rq)
 284 {
 285         u64 num_mtts = MLX5E_REQUIRED_MTTS(mlx5_wq_ll_get_size(&rq->mpwqe.wq));
 286
 287         return mlx5e_create_umr_mkey(mdev, num_mtts, PAGE_SHIFT, &rq->umr_mkey,
 288                                      rq->wqe_overflow.addr);
 289 }
 290
 291 static u64 mlx5e_get_mpwqe_offset(u16 wqe_ix)
 292 {
 293         return MLX5E_REQUIRED_MTTS(wqe_ix) << PAGE_SHIFT;
 294 }
 295
 296 static void mlx5e_init_frags_partition(struct mlx5e_rq *rq)
 297 {
 298         struct mlx5e_wqe_frag_info next_frag = {};
 299         struct mlx5e_wqe_frag_info *prev = NULL;
 300         int i;
 301
 302         next_frag.di = &rq->wqe.di[0];
 303
 304         for (i = 0; i < mlx5_wq_cyc_get_size(&rq->wqe.wq); i++) {
 305                 struct mlx5e_rq_frag_info *frag_info = &rq->wqe.info.arr[0];
 306                 struct mlx5e_wqe_frag_info *frag =
 307                         &rq->wqe.frags[i << rq->wqe.info.log_num_frags];
 308                 int f;
 309
 310                 for (f = 0; f < rq->wqe.info.num_frags; f++, frag++) {
 311                         if (next_frag.offset + frag_info[f].frag_stride > PAGE_SIZE) {
 312                                 next_frag.di++;
 313                                 next_frag.offset = 0;
 314                                 if (prev)
 315                                         prev->last_in_page = true;
 316                         }
 317                         *frag = next_frag;
 318
 319                         /* prepare next */
 320                         next_frag.offset += frag_info[f].frag_stride;
 321                         prev = frag;
 322                 }
 323         }
 324
 325         if (prev)
 326                 prev->last_in_page = true;
 327 }
 328
 329 int mlx5e_init_di_list(struct mlx5e_rq *rq, int wq_sz, int node)
 330 {
 331         int len = wq_sz << rq->wqe.info.log_num_frags;
 332
 333         rq->wqe.di = kvzalloc_node(array_size(len, sizeof(*rq->wqe.di)), GFP_KERNEL, node);
 334         if (!rq->wqe.di)
 335                 return -ENOMEM;
 336
 337         mlx5e_init_frags_partition(rq);
 338
 339         return 0;
 340 }
 341
 342 void mlx5e_free_di_list(struct mlx5e_rq *rq)
 343 {
 344         kvfree(rq->wqe.di);
 345 }
 346
 347 static void mlx5e_rq_err_cqe_work(struct work_struct *recover_work)
 348 {
 349         struct mlx5e_rq *rq = container_of(recover_work, struct mlx5e_rq, recover_work);
 350
 351         mlx5e_reporter_rq_cqe_err(rq);
 352 }
 353
 354 static int mlx5e_alloc_mpwqe_rq_drop_page(struct mlx5e_rq *rq)
 355 {
 356         rq->wqe_overflow.page = alloc_page(GFP_KERNEL);
 357         if (!rq->wqe_overflow.page)
 358                 return -ENOMEM;
 359
 360         rq->wqe_overflow.addr = dma_map_page(rq->pdev, rq->wqe_overflow.page, 0,
 361                                              PAGE_SIZE, rq->buff.map_dir);
 362         if (dma_mapping_error(rq->pdev, rq->wqe_overflow.addr)) {
 363                 __free_page(rq->wqe_overflow.page);
 364                 return -ENOMEM;
 365         }
 366         return 0;
 367 }
 368
 369 static void mlx5e_free_mpwqe_rq_drop_page(struct mlx5e_rq *rq)
 370 {
 371          dma_unmap_page(rq->pdev, rq->wqe_overflow.addr, PAGE_SIZE,
 372                         rq->buff.map_dir);
 373          __free_page(rq->wqe_overflow.page);
 374 }
 375
 376 static int mlx5e_init_rxq_rq(struct mlx5e_channel *c, struct mlx5e_params *params,
 377                              struct mlx5e_rq *rq)
 378 {
 379         struct mlx5_core_dev *mdev = c->mdev;
 380         int err;
 381
 382         rq->wq_type      = params->rq_wq_type;
 383         rq->pdev         = c->pdev;
 384         rq->netdev       = c->netdev;
 385         rq->priv         = c->priv;
 386         rq->tstamp       = c->tstamp;
 387         rq->clock        = &mdev->clock;
 388         rq->icosq        = &c->icosq;
 389         rq->ix           = c->ix;
 390         rq->mdev         = mdev;
 391         rq->hw_mtu       = MLX5E_SW2HW_MTU(params, params->sw_mtu);
 392         rq->xdpsq        = &c->rq_xdpsq;
 393         rq->stats        = &c->priv->channel_stats[c->ix].rq;
 394         rq->ptp_cyc2time = mlx5_rq_ts_translator(mdev);
 395         err = mlx5e_rq_set_handlers(rq, params, NULL);
 396         if (err)
 397                 return err;
 398
 399         return xdp_rxq_info_reg(&rq->xdp_rxq, rq->netdev, rq->ix, 0);
 400 }
 401
 402 static int mlx5e_alloc_rq(struct mlx5e_params *params,
 403                           struct mlx5e_xsk_param *xsk,
 404                           struct mlx5e_rq_param *rqp,
 405                           int node, struct mlx5e_rq *rq)
 406 {
 407         struct page_pool_params pp_params = { 0 };
 408         struct mlx5_core_dev *mdev = rq->mdev;
 409         void *rqc = rqp->rqc;
 410         void *rqc_wq = MLX5_ADDR_OF(rqc, rqc, wq);
 411         u32 pool_size;
 412         int wq_sz;
 413         int err;
 414         int i;
 415
 416         rqp->wq.db_numa_node = node;
 417         INIT_WORK(&rq->recover_work, mlx5e_rq_err_cqe_work);
 418
 419         if (params->xdp_prog)
 420                 bpf_prog_inc(params->xdp_prog);
 421         RCU_INIT_POINTER(rq->xdp_prog, params->xdp_prog);
 422
 423         rq->buff.map_dir = params->xdp_prog ? DMA_BIDIRECTIONAL : DMA_FROM_DEVICE;
 424         rq->buff.headroom = mlx5e_get_rq_headroom(mdev, params, xsk);
 425         pool_size = 1 << params->log_rq_mtu_frames;
 426
 427         switch (rq->wq_type) {
 428         case MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ:
 429                 err = mlx5_wq_ll_create(mdev, &rqp->wq, rqc_wq, &rq->mpwqe.wq,
 430                                         &rq->wq_ctrl);
 431                 if (err)
 432                         goto err_rq_xdp_prog;
 433
 434                 err = mlx5e_alloc_mpwqe_rq_drop_page(rq);
 435                 if (err)
 436                         goto err_rq_wq_destroy;
 437
 438                 rq->mpwqe.wq.db = &rq->mpwqe.wq.db[MLX5_RCV_DBR];
 439
 440                 wq_sz = mlx5_wq_ll_get_size(&rq->mpwqe.wq);
 441
 442                 pool_size = MLX5_MPWRQ_PAGES_PER_WQE <<
 443                         mlx5e_mpwqe_get_log_rq_size(params, xsk);
 444
 445                 rq->mpwqe.log_stride_sz = mlx5e_mpwqe_get_log_stride_size(mdev, params, xsk);
 446                 rq->mpwqe.num_strides =
 447                         BIT(mlx5e_mpwqe_get_log_num_strides(mdev, params, xsk));
 448
 449                 rq->buff.frame0_sz = (1 << rq->mpwqe.log_stride_sz);
 450
 451                 err = mlx5e_create_rq_umr_mkey(mdev, rq);
 452                 if (err)
 453                         goto err_rq_drop_page;
 454                 rq->mkey_be = cpu_to_be32(rq->umr_mkey.key);
 455
 456                 err = mlx5e_rq_alloc_mpwqe_info(rq, node);
 457                 if (err)
 458                         goto err_rq_mkey;
 459                 break;
 460         default: /* MLX5_WQ_TYPE_CYCLIC */
 461                 err = mlx5_wq_cyc_create(mdev, &rqp->wq, rqc_wq, &rq->wqe.wq,
 462                                          &rq->wq_ctrl);
 463                 if (err)
 464                         goto err_rq_xdp_prog;
 465
 466                 rq->wqe.wq.db = &rq->wqe.wq.db[MLX5_RCV_DBR];
 467
 468                 wq_sz = mlx5_wq_cyc_get_size(&rq->wqe.wq);
 469
 470                 rq->wqe.info = rqp->frags_info;
 471                 rq->buff.frame0_sz = rq->wqe.info.arr[0].frag_stride;
 472
 473                 rq->wqe.frags =
 474                         kvzalloc_node(array_size(sizeof(*rq->wqe.frags),
 475                                         (wq_sz << rq->wqe.info.log_num_frags)),
 476                                       GFP_KERNEL, node);
 477                 if (!rq->wqe.frags) {
 478                         err = -ENOMEM;
 479                         goto err_rq_wq_destroy;
 480                 }
 481
 482                 err = mlx5e_init_di_list(rq, wq_sz, node);
 483                 if (err)
 484                         goto err_rq_frags;
 485
 486                 rq->mkey_be = cpu_to_be32(mdev->mlx5e_res.hw_objs.mkey.key);
 487         }
 488
 489         if (xsk) {
 490                 err = xdp_rxq_info_reg_mem_model(&rq->xdp_rxq,
 491                                                  MEM_TYPE_XSK_BUFF_POOL, NULL);
 492                 xsk_pool_set_rxq_info(rq->xsk_pool, &rq->xdp_rxq);
 493         } else {
 494                 /* Create a page_pool and register it with rxq */
 495                 pp_params.order     = 0;
 496                 pp_params.flags     = 0; /* No-internal DMA mapping in page_pool */
 497                 pp_params.pool_size = pool_size;
 498                 pp_params.nid       = node;
 499                 pp_params.dev       = rq->pdev;
 500                 pp_params.dma_dir   = rq->buff.map_dir;
 501
 502                 /* page_pool can be used even when there is no rq->xdp_prog,
 503                  * given page_pool does not handle DMA mapping there is no
 504                  * required state to clear. And page_pool gracefully handle
 505                  * elevated refcnt.
 506                  */
 507                 rq->page_pool = page_pool_create(&pp_params);
 508                 if (IS_ERR(rq->page_pool)) {
 509                         err = PTR_ERR(rq->page_pool);
 510                         rq->page_pool = NULL;
 511                         goto err_free_by_rq_type;
 512                 }
 513                 if (xdp_rxq_info_is_reg(&rq->xdp_rxq))
 514                         err = xdp_rxq_info_reg_mem_model(&rq->xdp_rxq,
 515                                                          MEM_TYPE_PAGE_POOL, rq->page_pool);
 516         }
 517         if (err)
 518                 goto err_free_by_rq_type;
 519
 520         for (i = 0; i < wq_sz; i++) {
 521                 if (rq->wq_type == MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ) {
 522                         struct mlx5e_rx_wqe_ll *wqe =
 523                                 mlx5_wq_ll_get_wqe(&rq->mpwqe.wq, i);
 524                         u32 byte_count =
 525                                 rq->mpwqe.num_strides << rq->mpwqe.log_stride_sz;
 526                         u64 dma_offset = mlx5e_get_mpwqe_offset(i);
 527
 528                         wqe->data[0].addr = cpu_to_be64(dma_offset + rq->buff.headroom);
 529                         wqe->data[0].byte_count = cpu_to_be32(byte_count);
 530                         wqe->data[0].lkey = rq->mkey_be;
 531                 } else {
 532                         struct mlx5e_rx_wqe_cyc *wqe =
 533                                 mlx5_wq_cyc_get_wqe(&rq->wqe.wq, i);
 534                         int f;
 535
 536                         for (f = 0; f < rq->wqe.info.num_frags; f++) {
 537                                 u32 frag_size = rq->wqe.info.arr[f].frag_size |
 538                                         MLX5_HW_START_PADDING;
 539
 540                                 wqe->data[f].byte_count = cpu_to_be32(frag_size);
 541                                 wqe->data[f].lkey = rq->mkey_be;
 542                         }
 543                         /* check if num_frags is not a pow of two */
 544                         if (rq->wqe.info.num_frags < (1 << rq->wqe.info.log_num_frags)) {
 545                                 wqe->data[f].byte_count = 0;
 546                                 wqe->data[f].lkey = cpu_to_be32(MLX5_INVALID_LKEY);
 547                                 wqe->data[f].addr = 0;
 548                         }
 549                 }
 550         }
 551
 552         INIT_WORK(&rq->dim.work, mlx5e_rx_dim_work);
 553
 554         switch (params->rx_cq_moderation.cq_period_mode) {
 555         case MLX5_CQ_PERIOD_MODE_START_FROM_CQE:
 556                 rq->dim.mode = DIM_CQ_PERIOD_MODE_START_FROM_CQE;
 557                 break;
 558         case MLX5_CQ_PERIOD_MODE_START_FROM_EQE:
 559         default:
 560                 rq->dim.mode = DIM_CQ_PERIOD_MODE_START_FROM_EQE;
 561         }
 562
 563         rq->page_cache.head = 0;
 564         rq->page_cache.tail = 0;
 565
 566         return 0;
 567
 568 err_free_by_rq_type:
 569         switch (rq->wq_type) {
 570         case MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ:
 571                 kvfree(rq->mpwqe.info);
 572 err_rq_mkey:
 573                 mlx5_core_destroy_mkey(mdev, &rq->umr_mkey);
 574 err_rq_drop_page:
 575                 mlx5e_free_mpwqe_rq_drop_page(rq);
 576                 break;
 577         default: /* MLX5_WQ_TYPE_CYCLIC */
 578                 mlx5e_free_di_list(rq);
 579 err_rq_frags:
 580                 kvfree(rq->wqe.frags);
 581         }
 582 err_rq_wq_destroy:
 583         mlx5_wq_destroy(&rq->wq_ctrl);
 584 err_rq_xdp_prog:
 585         if (params->xdp_prog)
 586                 bpf_prog_put(params->xdp_prog);
 587
 588         return err;
 589 }
 590
 591 static void mlx5e_free_rq(struct mlx5e_rq *rq)
 592 {
 593         struct bpf_prog *old_prog;
 594         int i;
 595
 596         if (xdp_rxq_info_is_reg(&rq->xdp_rxq)) {
 597                 old_prog = rcu_dereference_protected(rq->xdp_prog,
 598                                                      lockdep_is_held(&rq->priv->state_lock));
 599                 if (old_prog)
 600                         bpf_prog_put(old_prog);
 601         }
 602
 603         switch (rq->wq_type) {
 604         case MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ:
 605                 kvfree(rq->mpwqe.info);
 606                 mlx5_core_destroy_mkey(rq->mdev, &rq->umr_mkey);
 607                 mlx5e_free_mpwqe_rq_drop_page(rq);
 608                 break;
 609         default: /* MLX5_WQ_TYPE_CYCLIC */
 610                 kvfree(rq->wqe.frags);
 611                 mlx5e_free_di_list(rq);
 612         }
 613
 614         for (i = rq->page_cache.head; i != rq->page_cache.tail;
 615              i = (i + 1) & (MLX5E_CACHE_SIZE - 1)) {
 616                 struct mlx5e_dma_info *dma_info = &rq->page_cache.page_cache[i];
 617
 618                 /* With AF_XDP, page_cache is not used, so this loop is not
 619                  * entered, and it's safe to call mlx5e_page_release_dynamic
 620                  * directly.
 621                  */
 622                 mlx5e_page_release_dynamic(rq, dma_info, false);
 623         }
 624
 625         xdp_rxq_info_unreg(&rq->xdp_rxq);
 626         page_pool_destroy(rq->page_pool);
 627         mlx5_wq_destroy(&rq->wq_ctrl);
 628 }
 629
 630 int mlx5e_create_rq(struct mlx5e_rq *rq, struct mlx5e_rq_param *param)
 631 {
 632         struct mlx5_core_dev *mdev = rq->mdev;
 633         u8 ts_format;
 634         void *in;
 635         void *rqc;
 636         void *wq;
 637         int inlen;
 638         int err;
 639
 640         inlen = MLX5_ST_SZ_BYTES(create_rq_in) +
 641                 sizeof(u64) * rq->wq_ctrl.buf.npages;
 642         in = kvzalloc(inlen, GFP_KERNEL);
 643         if (!in)
 644                 return -ENOMEM;
 645
 646         ts_format = mlx5_is_real_time_rq(mdev) ?
 647                     MLX5_RQC_TIMESTAMP_FORMAT_REAL_TIME :
 648                     MLX5_RQC_TIMESTAMP_FORMAT_FREE_RUNNING;
 649         rqc = MLX5_ADDR_OF(create_rq_in, in, ctx);
 650         wq  = MLX5_ADDR_OF(rqc, rqc, wq);
 651
 652         memcpy(rqc, param->rqc, sizeof(param->rqc));
 653
 654         MLX5_SET(rqc,  rqc, cqn,                rq->cq.mcq.cqn);
 655         MLX5_SET(rqc,  rqc, state,              MLX5_RQC_STATE_RST);
 656         MLX5_SET(rqc,  rqc, ts_format,          ts_format);
 657         MLX5_SET(wq,   wq,  log_wq_pg_sz,       rq->wq_ctrl.buf.page_shift -
 658                                                 MLX5_ADAPTER_PAGE_SHIFT);
 659         MLX5_SET64(wq, wq,  dbr_addr,           rq->wq_ctrl.db.dma);
 660
 661         mlx5_fill_page_frag_array(&rq->wq_ctrl.buf,
 662                                   (__be64 *)MLX5_ADDR_OF(wq, wq, pas));
 663
 664         err = mlx5_core_create_rq(mdev, in, inlen, &rq->rqn);
 665
 666         kvfree(in);
 667
 668         return err;
 669 }
 670
 671 int mlx5e_modify_rq_state(struct mlx5e_rq *rq, int curr_state, int next_state)
 672 {
 673         struct mlx5_core_dev *mdev = rq->mdev;
 674
 675         void *in;
 676         void *rqc;
 677         int inlen;
 678         int err;
 679
 680         inlen = MLX5_ST_SZ_BYTES(modify_rq_in);
 681         in = kvzalloc(inlen, GFP_KERNEL);
 682         if (!in)
 683                 return -ENOMEM;
 684
 685         if (curr_state == MLX5_RQC_STATE_RST && next_state == MLX5_RQC_STATE_RDY)
 686                 mlx5e_rqwq_reset(rq);
 687
 688         rqc = MLX5_ADDR_OF(modify_rq_in, in, ctx);
 689
 690         MLX5_SET(modify_rq_in, in, rq_state, curr_state);
 691         MLX5_SET(rqc, rqc, state, next_state);
 692
 693         err = mlx5_core_modify_rq(mdev, rq->rqn, in);
 694
 695         kvfree(in);
 696
 697         return err;
 698 }
 699
 700 static int mlx5e_modify_rq_scatter_fcs(struct mlx5e_rq *rq, bool enable)
 701 {
 702         struct mlx5_core_dev *mdev = rq->mdev;
 703
 704         void *in;
 705         void *rqc;
 706         int inlen;
 707         int err;
 708
 709         inlen = MLX5_ST_SZ_BYTES(modify_rq_in);
 710         in = kvzalloc(inlen, GFP_KERNEL);
 711         if (!in)
 712                 return -ENOMEM;
 713
 714         rqc = MLX5_ADDR_OF(modify_rq_in, in, ctx);
 715
 716         MLX5_SET(modify_rq_in, in, rq_state, MLX5_RQC_STATE_RDY);
 717         MLX5_SET64(modify_rq_in, in, modify_bitmask,
 718                    MLX5_MODIFY_RQ_IN_MODIFY_BITMASK_SCATTER_FCS);
 719         MLX5_SET(rqc, rqc, scatter_fcs, enable);
 720         MLX5_SET(rqc, rqc, state, MLX5_RQC_STATE_RDY);
 721
 722         err = mlx5_core_modify_rq(mdev, rq->rqn, in);
 723
 724         kvfree(in);
 725
 726         return err;
 727 }
 728
 729 static int mlx5e_modify_rq_vsd(struct mlx5e_rq *rq, bool vsd)
 730 {
 731         struct mlx5_core_dev *mdev = rq->mdev;
 732         void *in;
 733         void *rqc;
 734         int inlen;
 735         int err;
 736
 737         inlen = MLX5_ST_SZ_BYTES(modify_rq_in);
 738         in = kvzalloc(inlen, GFP_KERNEL);
 739         if (!in)
 740                 return -ENOMEM;
 741
 742         rqc = MLX5_ADDR_OF(modify_rq_in, in, ctx);
 743
 744         MLX5_SET(modify_rq_in, in, rq_state, MLX5_RQC_STATE_RDY);
 745         MLX5_SET64(modify_rq_in, in, modify_bitmask,
 746                    MLX5_MODIFY_RQ_IN_MODIFY_BITMASK_VSD);
 747         MLX5_SET(rqc, rqc, vsd, vsd);
 748         MLX5_SET(rqc, rqc, state, MLX5_RQC_STATE_RDY);
 749
 750         err = mlx5_core_modify_rq(mdev, rq->rqn, in);
 751
 752         kvfree(in);
 753
 754         return err;
 755 }
 756
 757 void mlx5e_destroy_rq(struct mlx5e_rq *rq)
 758 {
 759         mlx5_core_destroy_rq(rq->mdev, rq->rqn);
 760 }
 761
 762 int mlx5e_wait_for_min_rx_wqes(struct mlx5e_rq *rq, int wait_time)
 763 {
 764         unsigned long exp_time = jiffies + msecs_to_jiffies(wait_time);
 765
 766         u16 min_wqes = mlx5_min_rx_wqes(rq->wq_type, mlx5e_rqwq_get_size(rq));
 767
 768         do {
 769                 if (mlx5e_rqwq_get_cur_sz(rq) >= min_wqes)
 770                         return 0;
 771
 772                 msleep(20);
 773         } while (time_before(jiffies, exp_time));
 774
 775         netdev_warn(rq->netdev, "Failed to get min RX wqes on Channel[%d] RQN[0x%x] wq cur_sz(%d) min_rx_wqes(%d)\n",
 776                     rq->ix, rq->rqn, mlx5e_rqwq_get_cur_sz(rq), min_wqes);
 777
 778         mlx5e_reporter_rx_timeout(rq);
 779         return -ETIMEDOUT;
 780 }
 781
 782 void mlx5e_free_rx_in_progress_descs(struct mlx5e_rq *rq)
 783 {
 784         struct mlx5_wq_ll *wq;
 785         u16 head;
 786         int i;
 787
 788         if (rq->wq_type != MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ)
 789                 return;
 790
 791         wq = &rq->mpwqe.wq;
 792         head = wq->head;
 793
 794         /* Outstanding UMR WQEs (in progress) start at wq->head */
 795         for (i = 0; i < rq->mpwqe.umr_in_progress; i++) {
 796                 rq->dealloc_wqe(rq, head);
 797                 head = mlx5_wq_ll_get_wqe_next_ix(wq, head);
 798         }
 799
 800         rq->mpwqe.actual_wq_head = wq->head;
 801         rq->mpwqe.umr_in_progress = 0;
 802         rq->mpwqe.umr_completed = 0;
 803 }
 804
 805 void mlx5e_free_rx_descs(struct mlx5e_rq *rq)
 806 {
 807         __be16 wqe_ix_be;
 808         u16 wqe_ix;
 809
 810         if (rq->wq_type == MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ) {
 811                 struct mlx5_wq_ll *wq = &rq->mpwqe.wq;
 812
 813                 mlx5e_free_rx_in_progress_descs(rq);
 814
 815                 while (!mlx5_wq_ll_is_empty(wq)) {
 816                         struct mlx5e_rx_wqe_ll *wqe;
 817
 818                         wqe_ix_be = *wq->tail_next;
 819                         wqe_ix    = be16_to_cpu(wqe_ix_be);
 820                         wqe       = mlx5_wq_ll_get_wqe(wq, wqe_ix);
 821                         rq->dealloc_wqe(rq, wqe_ix);
 822                         mlx5_wq_ll_pop(wq, wqe_ix_be,
 823                                        &wqe->next.next_wqe_index);
 824                 }
 825         } else {
 826                 struct mlx5_wq_cyc *wq = &rq->wqe.wq;
 827
 828                 while (!mlx5_wq_cyc_is_empty(wq)) {
 829                         wqe_ix = mlx5_wq_cyc_get_tail(wq);
 830                         rq->dealloc_wqe(rq, wqe_ix);
 831                         mlx5_wq_cyc_pop(wq);
 832                 }
 833         }
 834
 835 }
 836
 837 int mlx5e_open_rq(struct mlx5e_params *params, struct mlx5e_rq_param *param,
 838                   struct mlx5e_xsk_param *xsk, int node,
 839                   struct mlx5e_rq *rq)
 840 {
 841         struct mlx5_core_dev *mdev = rq->mdev;
 842         int err;
 843
 844         err = mlx5e_alloc_rq(params, xsk, param, node, rq);
 845         if (err)
 846                 return err;
 847
 848         err = mlx5e_create_rq(rq, param);
 849         if (err)
 850                 goto err_free_rq;
 851
 852         err = mlx5e_modify_rq_state(rq, MLX5_RQC_STATE_RST, MLX5_RQC_STATE_RDY);
 853         if (err)
 854                 goto err_destroy_rq;
 855
 856         if (mlx5e_is_tls_on(rq->priv) && !mlx5_accel_is_ktls_device(mdev))
 857                 __set_bit(MLX5E_RQ_STATE_FPGA_TLS, &rq->state); /* must be FPGA */
 858
 859         if (MLX5_CAP_ETH(mdev, cqe_checksum_full))
 860                 __set_bit(MLX5E_RQ_STATE_CSUM_FULL, &rq->state);
 861
 862         if (params->rx_dim_enabled)
 863                 __set_bit(MLX5E_RQ_STATE_AM, &rq->state);
 864
 865         /* We disable csum_complete when XDP is enabled since
 866          * XDP programs might manipulate packets which will render
 867          * skb->checksum incorrect.
 868          */
 869         if (MLX5E_GET_PFLAG(params, MLX5E_PFLAG_RX_NO_CSUM_COMPLETE) || params->xdp_prog)
 870                 __set_bit(MLX5E_RQ_STATE_NO_CSUM_COMPLETE, &rq->state);
 871
 872         /* For CQE compression on striding RQ, use stride index provided by
 873          * HW if capability is supported.
 874          */
 875         if (MLX5E_GET_PFLAG(params, MLX5E_PFLAG_RX_STRIDING_RQ) &&
 876             MLX5_CAP_GEN(mdev, mini_cqe_resp_stride_index))
 877                 __set_bit(MLX5E_RQ_STATE_MINI_CQE_HW_STRIDX, &rq->state);
 878
 879         return 0;
 880
 881 err_destroy_rq:
 882         mlx5e_destroy_rq(rq);
 883 err_free_rq:
 884         mlx5e_free_rq(rq);
 885
 886         return err;
 887 }
 888
 889 void mlx5e_activate_rq(struct mlx5e_rq *rq)
 890 {
 891         set_bit(MLX5E_RQ_STATE_ENABLED, &rq->state);
 892         if (rq->icosq) {
 893                 mlx5e_trigger_irq(rq->icosq);
 894         } else {
 895                 local_bh_disable();
 896                 napi_schedule(rq->cq.napi);
 897                 local_bh_enable();
 898         }
 899 }
 900
 901 void mlx5e_deactivate_rq(struct mlx5e_rq *rq)
 902 {
 903         clear_bit(MLX5E_RQ_STATE_ENABLED, &rq->state);
 904         synchronize_net(); /* Sync with NAPI to prevent mlx5e_post_rx_wqes. */
 905 }
 906
 907 void mlx5e_close_rq(struct mlx5e_rq *rq)
 908 {
 909         cancel_work_sync(&rq->dim.work);
 910         if (rq->icosq)
 911                 cancel_work_sync(&rq->icosq->recover_work);
 912         cancel_work_sync(&rq->recover_work);
 913         mlx5e_destroy_rq(rq);
 914         mlx5e_free_rx_descs(rq);
 915         mlx5e_free_rq(rq);
 916 }
 917
 918 static void mlx5e_free_xdpsq_db(struct mlx5e_xdpsq *sq)
 919 {
 920         kvfree(sq->db.xdpi_fifo.xi);
 921         kvfree(sq->db.wqe_info);
 922 }
 923
 924 static int mlx5e_alloc_xdpsq_fifo(struct mlx5e_xdpsq *sq, int numa)
 925 {
 926         struct mlx5e_xdp_info_fifo *xdpi_fifo = &sq->db.xdpi_fifo;
 927         int wq_sz        = mlx5_wq_cyc_get_size(&sq->wq);
 928         int dsegs_per_wq = wq_sz * MLX5_SEND_WQEBB_NUM_DS;
 929
 930         xdpi_fifo->xi = kvzalloc_node(sizeof(*xdpi_fifo->xi) * dsegs_per_wq,
 931                                       GFP_KERNEL, numa);
 932         if (!xdpi_fifo->xi)
 933                 return -ENOMEM;
 934
 935         xdpi_fifo->pc   = &sq->xdpi_fifo_pc;
 936         xdpi_fifo->cc   = &sq->xdpi_fifo_cc;
 937         xdpi_fifo->mask = dsegs_per_wq - 1;
 938
 939         return 0;
 940 }
 941
 942 static int mlx5e_alloc_xdpsq_db(struct mlx5e_xdpsq *sq, int numa)
 943 {
 944         int wq_sz = mlx5_wq_cyc_get_size(&sq->wq);
 945         int err;
 946
 947         sq->db.wqe_info = kvzalloc_node(sizeof(*sq->db.wqe_info) * wq_sz,
 948                                         GFP_KERNEL, numa);
 949         if (!sq->db.wqe_info)
 950                 return -ENOMEM;
 951
 952         err = mlx5e_alloc_xdpsq_fifo(sq, numa);
 953         if (err) {
 954                 mlx5e_free_xdpsq_db(sq);
 955                 return err;
 956         }
 957
 958         return 0;
 959 }
 960
 961 static int mlx5e_alloc_xdpsq(struct mlx5e_channel *c,
 962                              struct mlx5e_params *params,
 963                              struct xsk_buff_pool *xsk_pool,
 964                              struct mlx5e_sq_param *param,
 965                              struct mlx5e_xdpsq *sq,
 966                              bool is_redirect)
 967 {
 968         void *sqc_wq               = MLX5_ADDR_OF(sqc, param->sqc, wq);
 969         struct mlx5_core_dev *mdev = c->mdev;
 970         struct mlx5_wq_cyc *wq = &sq->wq;
 971         int err;
 972
 973         sq->pdev      = c->pdev;
 974         sq->mkey_be   = c->mkey_be;
 975         sq->channel   = c;
 976         sq->uar_map   = mdev->mlx5e_res.hw_objs.bfreg.map;
 977         sq->min_inline_mode = params->tx_min_inline_mode;
 978         sq->hw_mtu    = MLX5E_SW2HW_MTU(params, params->sw_mtu);
 979         sq->xsk_pool  = xsk_pool;
 980
 981         sq->stats = sq->xsk_pool ?
 982                 &c->priv->channel_stats[c->ix].xsksq :
 983                 is_redirect ?
 984                         &c->priv->channel_stats[c->ix].xdpsq :
 985                         &c->priv->channel_stats[c->ix].rq_xdpsq;
 986
 987         param->wq.db_numa_node = cpu_to_node(c->cpu);
 988         err = mlx5_wq_cyc_create(mdev, &param->wq, sqc_wq, wq, &sq->wq_ctrl);
 989         if (err)
 990                 return err;
 991         wq->db = &wq->db[MLX5_SND_DBR];
 992
 993         err = mlx5e_alloc_xdpsq_db(sq, cpu_to_node(c->cpu));
 994         if (err)
 995                 goto err_sq_wq_destroy;
 996
 997         return 0;
 998
 999 err_sq_wq_destroy:
1000         mlx5_wq_destroy(&sq->wq_ctrl);
1001
1002         return err;
1003 }
1004
1005 static void mlx5e_free_xdpsq(struct mlx5e_xdpsq *sq)
1006 {
1007         mlx5e_free_xdpsq_db(sq);
1008         mlx5_wq_destroy(&sq->wq_ctrl);
1009 }
1010
1011 static void mlx5e_free_icosq_db(struct mlx5e_icosq *sq)
1012 {
1013         kvfree(sq->db.wqe_info);
1014 }
1015
1016 static int mlx5e_alloc_icosq_db(struct mlx5e_icosq *sq, int numa)
1017 {
1018         int wq_sz = mlx5_wq_cyc_get_size(&sq->wq);
1019         size_t size;
1020
1021         size = array_size(wq_sz, sizeof(*sq->db.wqe_info));
1022         sq->db.wqe_info = kvzalloc_node(size, GFP_KERNEL, numa);
1023         if (!sq->db.wqe_info)
1024                 return -ENOMEM;
1025
1026         return 0;
1027 }
1028
1029 static void mlx5e_icosq_err_cqe_work(struct work_struct *recover_work)
1030 {
1031         struct mlx5e_icosq *sq = container_of(recover_work, struct mlx5e_icosq,
1032                                               recover_work);
1033
1034         mlx5e_reporter_icosq_cqe_err(sq);
1035 }
1036
1037 static int mlx5e_alloc_icosq(struct mlx5e_channel *c,
1038                              struct mlx5e_sq_param *param,
1039                              struct mlx5e_icosq *sq)
1040 {
1041         void *sqc_wq               = MLX5_ADDR_OF(sqc, param->sqc, wq);
1042         struct mlx5_core_dev *mdev = c->mdev;
1043         struct mlx5_wq_cyc *wq = &sq->wq;
1044         int err;
1045
1046         sq->channel   = c;
1047         sq->uar_map   = mdev->mlx5e_res.hw_objs.bfreg.map;
1048         sq->reserved_room = param->stop_room;
1049
1050         param->wq.db_numa_node = cpu_to_node(c->cpu);
1051         err = mlx5_wq_cyc_create(mdev, &param->wq, sqc_wq, wq, &sq->wq_ctrl);
1052         if (err)
1053                 return err;
1054         wq->db = &wq->db[MLX5_SND_DBR];
1055
1056         err = mlx5e_alloc_icosq_db(sq, cpu_to_node(c->cpu));
1057         if (err)
1058                 goto err_sq_wq_destroy;
1059
1060         INIT_WORK(&sq->recover_work, mlx5e_icosq_err_cqe_work);
1061
1062         return 0;
1063
1064 err_sq_wq_destroy:
1065         mlx5_wq_destroy(&sq->wq_ctrl);
1066
1067         return err;
1068 }
1069
1070 static void mlx5e_free_icosq(struct mlx5e_icosq *sq)
1071 {
1072         mlx5e_free_icosq_db(sq);
1073         mlx5_wq_destroy(&sq->wq_ctrl);
1074 }
1075
1076 void mlx5e_free_txqsq_db(struct mlx5e_txqsq *sq)
1077 {
1078         kvfree(sq->db.wqe_info);
1079         kvfree(sq->db.skb_fifo.fifo);
1080         kvfree(sq->db.dma_fifo);
1081 }
1082
1083 int mlx5e_alloc_txqsq_db(struct mlx5e_txqsq *sq, int numa)
1084 {
1085         int wq_sz = mlx5_wq_cyc_get_size(&sq->wq);
1086         int df_sz = wq_sz * MLX5_SEND_WQEBB_NUM_DS;
1087
1088         sq->db.dma_fifo = kvzalloc_node(array_size(df_sz,
1089                                                    sizeof(*sq->db.dma_fifo)),
1090                                         GFP_KERNEL, numa);
1091         sq->db.skb_fifo.fifo = kvzalloc_node(array_size(df_sz,
1092                                                         sizeof(*sq->db.skb_fifo.fifo)),
1093                                         GFP_KERNEL, numa);
1094         sq->db.wqe_info = kvzalloc_node(array_size(wq_sz,
1095                                                    sizeof(*sq->db.wqe_info)),
1096                                         GFP_KERNEL, numa);
1097         if (!sq->db.dma_fifo || !sq->db.skb_fifo.fifo || !sq->db.wqe_info) {
1098                 mlx5e_free_txqsq_db(sq);
1099                 return -ENOMEM;
1100         }
1101
1102         sq->dma_fifo_mask = df_sz - 1;
1103
1104         sq->db.skb_fifo.pc   = &sq->skb_fifo_pc;
1105         sq->db.skb_fifo.cc   = &sq->skb_fifo_cc;
1106         sq->db.skb_fifo.mask = df_sz - 1;
1107
1108         return 0;
1109 }
1110
1111 static int mlx5e_alloc_txqsq(struct mlx5e_channel *c,
1112                              int txq_ix,
1113                              struct mlx5e_params *params,
1114                              struct mlx5e_sq_param *param,
1115                              struct mlx5e_txqsq *sq,
1116                              int tc)
1117 {
1118         void *sqc_wq               = MLX5_ADDR_OF(sqc, param->sqc, wq);
1119         struct mlx5_core_dev *mdev = c->mdev;
1120         struct mlx5_wq_cyc *wq = &sq->wq;
1121         int err;
1122
1123         sq->pdev      = c->pdev;
1124         sq->tstamp    = c->tstamp;
1125         sq->clock     = &mdev->clock;
1126         sq->mkey_be   = c->mkey_be;
1127         sq->netdev    = c->netdev;
1128         sq->mdev      = c->mdev;
1129         sq->priv      = c->priv;
1130         sq->ch_ix     = c->ix;
1131         sq->txq_ix    = txq_ix;
1132         sq->uar_map   = mdev->mlx5e_res.hw_objs.bfreg.map;
1133         sq->min_inline_mode = params->tx_min_inline_mode;
1134         sq->hw_mtu    = MLX5E_SW2HW_MTU(params, params->sw_mtu);
1135         INIT_WORK(&sq->recover_work, mlx5e_tx_err_cqe_work);
1136         if (!MLX5_CAP_ETH(mdev, wqe_vlan_insert))
1137                 set_bit(MLX5E_SQ_STATE_VLAN_NEED_L2_INLINE, &sq->state);
1138         if (MLX5_IPSEC_DEV(c->priv->mdev))
1139                 set_bit(MLX5E_SQ_STATE_IPSEC, &sq->state);
1140         if (param->is_mpw)
1141                 set_bit(MLX5E_SQ_STATE_MPWQE, &sq->state);
1142         sq->stop_room = param->stop_room;
1143         sq->ptp_cyc2time = mlx5_sq_ts_translator(mdev);
1144
1145         param->wq.db_numa_node = cpu_to_node(c->cpu);
1146         err = mlx5_wq_cyc_create(mdev, &param->wq, sqc_wq, wq, &sq->wq_ctrl);
1147         if (err)
1148                 return err;
1149         wq->db    = &wq->db[MLX5_SND_DBR];
1150
1151         err = mlx5e_alloc_txqsq_db(sq, cpu_to_node(c->cpu));
1152         if (err)
1153                 goto err_sq_wq_destroy;
1154
1155         INIT_WORK(&sq->dim.work, mlx5e_tx_dim_work);
1156         sq->dim.mode = params->tx_cq_moderation.cq_period_mode;
1157
1158         return 0;
1159
1160 err_sq_wq_destroy:
1161         mlx5_wq_destroy(&sq->wq_ctrl);
1162
1163         return err;
1164 }
1165
1166 void mlx5e_free_txqsq(struct mlx5e_txqsq *sq)
1167 {
1168         mlx5e_free_txqsq_db(sq);
1169         mlx5_wq_destroy(&sq->wq_ctrl);
1170 }
1171
1172 static int mlx5e_create_sq(struct mlx5_core_dev *mdev,
1173                            struct mlx5e_sq_param *param,
1174                            struct mlx5e_create_sq_param *csp,
1175                            u32 *sqn)
1176 {
1177         u8 ts_format;
1178         void *in;
1179         void *sqc;
1180         void *wq;
1181         int inlen;
1182         int err;
1183
1184         inlen = MLX5_ST_SZ_BYTES(create_sq_in) +
1185                 sizeof(u64) * csp->wq_ctrl->buf.npages;
1186         in = kvzalloc(inlen, GFP_KERNEL);
1187         if (!in)
1188                 return -ENOMEM;
1189
1190         ts_format = mlx5_is_real_time_sq(mdev) ?
1191                     MLX5_SQC_TIMESTAMP_FORMAT_REAL_TIME :
1192                     MLX5_SQC_TIMESTAMP_FORMAT_FREE_RUNNING;
1193         sqc = MLX5_ADDR_OF(create_sq_in, in, ctx);
1194         wq = MLX5_ADDR_OF(sqc, sqc, wq);
1195
1196         memcpy(sqc, param->sqc, sizeof(param->sqc));
1197         MLX5_SET(sqc,  sqc, tis_lst_sz, csp->tis_lst_sz);
1198         MLX5_SET(sqc,  sqc, tis_num_0, csp->tisn);
1199         MLX5_SET(sqc,  sqc, cqn, csp->cqn);
1200         MLX5_SET(sqc,  sqc, ts_cqe_to_dest_cqn, csp->ts_cqe_to_dest_cqn);
1201         MLX5_SET(sqc,  sqc, ts_format, ts_format);
1202
1203
1204         if (MLX5_CAP_ETH(mdev, wqe_inline_mode) == MLX5_CAP_INLINE_MODE_VPORT_CONTEXT)
1205                 MLX5_SET(sqc,  sqc, min_wqe_inline_mode, csp->min_inline_mode);
1206
1207         MLX5_SET(sqc,  sqc, state, MLX5_SQC_STATE_RST);
1208         MLX5_SET(sqc,  sqc, flush_in_error_en, 1);
1209
1210         MLX5_SET(wq,   wq, wq_type,       MLX5_WQ_TYPE_CYCLIC);
1211         MLX5_SET(wq,   wq, uar_page,      mdev->mlx5e_res.hw_objs.bfreg.index);
1212         MLX5_SET(wq,   wq, log_wq_pg_sz,  csp->wq_ctrl->buf.page_shift -
1213                                           MLX5_ADAPTER_PAGE_SHIFT);
1214         MLX5_SET64(wq, wq, dbr_addr,      csp->wq_ctrl->db.dma);
1215
1216         mlx5_fill_page_frag_array(&csp->wq_ctrl->buf,
1217                                   (__be64 *)MLX5_ADDR_OF(wq, wq, pas));
1218
1219         err = mlx5_core_create_sq(mdev, in, inlen, sqn);
1220
1221         kvfree(in);
1222
1223         return err;
1224 }
1225
1226 int mlx5e_modify_sq(struct mlx5_core_dev *mdev, u32 sqn,
1227                     struct mlx5e_modify_sq_param *p)
1228 {
1229         u64 bitmask = 0;
1230         void *in;
1231         void *sqc;
1232         int inlen;
1233         int err;
1234
1235         inlen = MLX5_ST_SZ_BYTES(modify_sq_in);
1236         in = kvzalloc(inlen, GFP_KERNEL);
1237         if (!in)
1238                 return -ENOMEM;
1239
1240         sqc = MLX5_ADDR_OF(modify_sq_in, in, ctx);
1241
1242         MLX5_SET(modify_sq_in, in, sq_state, p->curr_state);
1243         MLX5_SET(sqc, sqc, state, p->next_state);
1244         if (p->rl_update && p->next_state == MLX5_SQC_STATE_RDY) {
1245                 bitmask |= 1;
1246                 MLX5_SET(sqc, sqc, packet_pacing_rate_limit_index, p->rl_index);
1247         }
1248         if (p->qos_update && p->next_state == MLX5_SQC_STATE_RDY) {
1249                 bitmask |= 1 << 2;
1250                 MLX5_SET(sqc, sqc, qos_queue_group_id, p->qos_queue_group_id);
1251         }
1252         MLX5_SET64(modify_sq_in, in, modify_bitmask, bitmask);
1253
1254         err = mlx5_core_modify_sq(mdev, sqn, in);
1255
1256         kvfree(in);
1257
1258         return err;
1259 }
1260
1261 static void mlx5e_destroy_sq(struct mlx5_core_dev *mdev, u32 sqn)
1262 {
1263         mlx5_core_destroy_sq(mdev, sqn);
1264 }
1265
1266 int mlx5e_create_sq_rdy(struct mlx5_core_dev *mdev,
1267                         struct mlx5e_sq_param *param,
1268                         struct mlx5e_create_sq_param *csp,
1269                         u16 qos_queue_group_id,
1270                         u32 *sqn)
1271 {
1272         struct mlx5e_modify_sq_param msp = {0};
1273         int err;
1274
1275         err = mlx5e_create_sq(mdev, param, csp, sqn);
1276         if (err)
1277                 return err;
1278
1279         msp.curr_state = MLX5_SQC_STATE_RST;
1280         msp.next_state = MLX5_SQC_STATE_RDY;
1281         if (qos_queue_group_id) {
1282                 msp.qos_update = true;
1283                 msp.qos_queue_group_id = qos_queue_group_id;
1284         }
1285         err = mlx5e_modify_sq(mdev, *sqn, &msp);
1286         if (err)
1287                 mlx5e_destroy_sq(mdev, *sqn);
1288
1289         return err;
1290 }
1291
1292 static int mlx5e_set_sq_maxrate(struct net_device *dev,
1293                                 struct mlx5e_txqsq *sq, u32 rate);
1294
1295 int mlx5e_open_txqsq(struct mlx5e_channel *c, u32 tisn, int txq_ix,
1296                      struct mlx5e_params *params, struct mlx5e_sq_param *param,
1297                      struct mlx5e_txqsq *sq, int tc, u16 qos_queue_group_id, u16 qos_qid)
1298 {
1299         struct mlx5e_create_sq_param csp = {};
1300         u32 tx_rate;
1301         int err;
1302
1303         err = mlx5e_alloc_txqsq(c, txq_ix, params, param, sq, tc);
1304         if (err)
1305                 return err;
1306
1307         if (qos_queue_group_id)
1308                 sq->stats = c->priv->htb.qos_sq_stats[qos_qid];
1309         else
1310                 sq->stats = &c->priv->channel_stats[c->ix].sq[tc];
1311
1312         csp.tisn            = tisn;
1313         csp.tis_lst_sz      = 1;
1314         csp.cqn             = sq->cq.mcq.cqn;
1315         csp.wq_ctrl         = &sq->wq_ctrl;
1316         csp.min_inline_mode = sq->min_inline_mode;
1317         err = mlx5e_create_sq_rdy(c->mdev, param, &csp, qos_queue_group_id, &sq->sqn);
1318         if (err)
1319                 goto err_free_txqsq;
1320
1321         tx_rate = c->priv->tx_rates[sq->txq_ix];
1322         if (tx_rate)
1323                 mlx5e_set_sq_maxrate(c->netdev, sq, tx_rate);
1324
1325         if (params->tx_dim_enabled)
1326                 sq->state |= BIT(MLX5E_SQ_STATE_AM);
1327
1328         return 0;
1329
1330 err_free_txqsq:
1331         mlx5e_free_txqsq(sq);
1332
1333         return err;
1334 }
1335
1336 void mlx5e_activate_txqsq(struct mlx5e_txqsq *sq)
1337 {
1338         sq->txq = netdev_get_tx_queue(sq->netdev, sq->txq_ix);
1339         set_bit(MLX5E_SQ_STATE_ENABLED, &sq->state);
1340         netdev_tx_reset_queue(sq->txq);
1341         netif_tx_start_queue(sq->txq);
1342 }
1343
1344 void mlx5e_tx_disable_queue(struct netdev_queue *txq)
1345 {
1346         __netif_tx_lock_bh(txq);
1347         netif_tx_stop_queue(txq);
1348         __netif_tx_unlock_bh(txq);
1349 }
1350
1351 void mlx5e_deactivate_txqsq(struct mlx5e_txqsq *sq)
1352 {
1353         struct mlx5_wq_cyc *wq = &sq->wq;
1354
1355         clear_bit(MLX5E_SQ_STATE_ENABLED, &sq->state);
1356         synchronize_net(); /* Sync with NAPI to prevent netif_tx_wake_queue. */
1357
1358         mlx5e_tx_disable_queue(sq->txq);
1359
1360         /* last doorbell out, godspeed .. */
1361         if (mlx5e_wqc_has_room_for(wq, sq->cc, sq->pc, 1)) {
1362                 u16 pi = mlx5_wq_cyc_ctr2ix(wq, sq->pc);
1363                 struct mlx5e_tx_wqe *nop;
1364
1365                 sq->db.wqe_info[pi] = (struct mlx5e_tx_wqe_info) {
1366                         .num_wqebbs = 1,
1367                 };
1368
1369                 nop = mlx5e_post_nop(wq, sq->sqn, &sq->pc);
1370                 mlx5e_notify_hw(wq, sq->pc, sq->uar_map, &nop->ctrl);
1371         }
1372 }
1373
1374 void mlx5e_close_txqsq(struct mlx5e_txqsq *sq)
1375 {
1376         struct mlx5_core_dev *mdev = sq->mdev;
1377         struct mlx5_rate_limit rl = {0};
1378
1379         cancel_work_sync(&sq->dim.work);
1380         cancel_work_sync(&sq->recover_work);
1381         mlx5e_destroy_sq(mdev, sq->sqn);
1382         if (sq->rate_limit) {
1383                 rl.rate = sq->rate_limit;
1384                 mlx5_rl_remove_rate(mdev, &rl);
1385         }
1386         mlx5e_free_txqsq_descs(sq);
1387         mlx5e_free_txqsq(sq);
1388 }
1389
1390 void mlx5e_tx_err_cqe_work(struct work_struct *recover_work)
1391 {
1392         struct mlx5e_txqsq *sq = container_of(recover_work, struct mlx5e_txqsq,
1393                                               recover_work);
1394
1395         mlx5e_reporter_tx_err_cqe(sq);
1396 }
1397
1398 int mlx5e_open_icosq(struct mlx5e_channel *c, struct mlx5e_params *params,
1399                      struct mlx5e_sq_param *param, struct mlx5e_icosq *sq)
1400 {
1401         struct mlx5e_create_sq_param csp = {};
1402         int err;
1403
1404         err = mlx5e_alloc_icosq(c, param, sq);
1405         if (err)
1406                 return err;
1407
1408         csp.cqn             = sq->cq.mcq.cqn;
1409         csp.wq_ctrl         = &sq->wq_ctrl;
1410         csp.min_inline_mode = params->tx_min_inline_mode;
1411         err = mlx5e_create_sq_rdy(c->mdev, param, &csp, 0, &sq->sqn);
1412         if (err)
1413                 goto err_free_icosq;
1414
1415         if (param->is_tls) {
1416                 sq->ktls_resync = mlx5e_ktls_rx_resync_create_resp_list();
1417                 if (IS_ERR(sq->ktls_resync)) {
1418                         err = PTR_ERR(sq->ktls_resync);
1419                         goto err_destroy_icosq;
1420                 }
1421         }
1422         return 0;
1423
1424 err_destroy_icosq:
1425         mlx5e_destroy_sq(c->mdev, sq->sqn);
1426 err_free_icosq:
1427         mlx5e_free_icosq(sq);
1428
1429         return err;
1430 }
1431
1432 void mlx5e_activate_icosq(struct mlx5e_icosq *icosq)
1433 {
1434         set_bit(MLX5E_SQ_STATE_ENABLED, &icosq->state);
1435 }
1436
1437 void mlx5e_deactivate_icosq(struct mlx5e_icosq *icosq)
1438 {
1439         clear_bit(MLX5E_SQ_STATE_ENABLED, &icosq->state);
1440         synchronize_net(); /* Sync with NAPI. */
1441 }
1442
1443 void mlx5e_close_icosq(struct mlx5e_icosq *sq)
1444 {
1445         struct mlx5e_channel *c = sq->channel;
1446
1447         if (sq->ktls_resync)
1448                 mlx5e_ktls_rx_resync_destroy_resp_list(sq->ktls_resync);
1449         mlx5e_destroy_sq(c->mdev, sq->sqn);
1450         mlx5e_free_icosq_descs(sq);
1451         mlx5e_free_icosq(sq);
1452 }
1453
1454 int mlx5e_open_xdpsq(struct mlx5e_channel *c, struct mlx5e_params *params,
1455                      struct mlx5e_sq_param *param, struct xsk_buff_pool *xsk_pool,
1456                      struct mlx5e_xdpsq *sq, bool is_redirect)
1457 {
1458         struct mlx5e_create_sq_param csp = {};
1459         int err;
1460
1461         err = mlx5e_alloc_xdpsq(c, params, xsk_pool, param, sq, is_redirect);
1462         if (err)
1463                 return err;
1464
1465         csp.tis_lst_sz      = 1;
1466         csp.tisn            = c->priv->tisn[c->lag_port][0]; /* tc = 0 */
1467         csp.cqn             = sq->cq.mcq.cqn;
1468         csp.wq_ctrl         = &sq->wq_ctrl;
1469         csp.min_inline_mode = sq->min_inline_mode;
1470         set_bit(MLX5E_SQ_STATE_ENABLED, &sq->state);
1471         err = mlx5e_create_sq_rdy(c->mdev, param, &csp, 0, &sq->sqn);
1472         if (err)
1473                 goto err_free_xdpsq;
1474
1475         mlx5e_set_xmit_fp(sq, param->is_mpw);
1476
1477         if (!param->is_mpw) {
1478                 unsigned int ds_cnt = MLX5E_XDP_TX_DS_COUNT;
1479                 unsigned int inline_hdr_sz = 0;
1480                 int i;
1481
1482                 if (sq->min_inline_mode != MLX5_INLINE_MODE_NONE) {
1483                         inline_hdr_sz = MLX5E_XDP_MIN_INLINE;
1484                         ds_cnt++;
1485                 }
1486
1487                 /* Pre initialize fixed WQE fields */
1488                 for (i = 0; i < mlx5_wq_cyc_get_size(&sq->wq); i++) {
1489                         struct mlx5e_tx_wqe      *wqe  = mlx5_wq_cyc_get_wqe(&sq->wq, i);
1490                         struct mlx5_wqe_ctrl_seg *cseg = &wqe->ctrl;
1491                         struct mlx5_wqe_eth_seg  *eseg = &wqe->eth;
1492                         struct mlx5_wqe_data_seg *dseg;
1493
1494                         sq->db.wqe_info[i] = (struct mlx5e_xdp_wqe_info) {
1495                                 .num_wqebbs = 1,
1496                                 .num_pkts   = 1,
1497                         };
1498
1499                         cseg->qpn_ds = cpu_to_be32((sq->sqn << 8) | ds_cnt);
1500                         eseg->inline_hdr.sz = cpu_to_be16(inline_hdr_sz);
1501
1502                         dseg = (struct mlx5_wqe_data_seg *)cseg + (ds_cnt - 1);
1503                         dseg->lkey = sq->mkey_be;
1504                 }
1505         }
1506
1507         return 0;
1508
1509 err_free_xdpsq:
1510         clear_bit(MLX5E_SQ_STATE_ENABLED, &sq->state);
1511         mlx5e_free_xdpsq(sq);
1512
1513         return err;
1514 }
1515
1516 void mlx5e_close_xdpsq(struct mlx5e_xdpsq *sq)
1517 {
1518         struct mlx5e_channel *c = sq->channel;
1519
1520         clear_bit(MLX5E_SQ_STATE_ENABLED, &sq->state);
1521         synchronize_net(); /* Sync with NAPI. */
1522
1523         mlx5e_destroy_sq(c->mdev, sq->sqn);
1524         mlx5e_free_xdpsq_descs(sq);
1525         mlx5e_free_xdpsq(sq);
1526 }
1527
1528 static int mlx5e_alloc_cq_common(struct mlx5e_priv *priv,
1529                                  struct mlx5e_cq_param *param,
1530                                  struct mlx5e_cq *cq)
1531 {
1532         struct mlx5_core_dev *mdev = priv->mdev;
1533         struct mlx5_core_cq *mcq = &cq->mcq;
1534         int eqn_not_used;
1535         unsigned int irqn;
1536         int err;
1537         u32 i;
1538
1539         err = mlx5_vector2eqn(mdev, param->eq_ix, &eqn_not_used, &irqn);
1540         if (err)
1541                 return err;
1542
1543         err = mlx5_cqwq_create(mdev, &param->wq, param->cqc, &cq->wq,
1544                                &cq->wq_ctrl);
1545         if (err)
1546                 return err;
1547
1548         mcq->cqe_sz     = 64;
1549         mcq->set_ci_db  = cq->wq_ctrl.db.db;
1550         mcq->arm_db     = cq->wq_ctrl.db.db + 1;
1551         *mcq->set_ci_db = 0;
1552         *mcq->arm_db    = 0;
1553         mcq->vector     = param->eq_ix;
1554         mcq->comp       = mlx5e_completion_event;
1555         mcq->event      = mlx5e_cq_error_event;
1556         mcq->irqn       = irqn;
1557
1558         for (i = 0; i < mlx5_cqwq_get_size(&cq->wq); i++) {
1559                 struct mlx5_cqe64 *cqe = mlx5_cqwq_get_wqe(&cq->wq, i);
1560
1561                 cqe->op_own = 0xf1;
1562         }
1563
1564         cq->mdev = mdev;
1565         cq->netdev = priv->netdev;
1566         cq->priv = priv;
1567
1568         return 0;
1569 }
1570
1571 static int mlx5e_alloc_cq(struct mlx5e_priv *priv,
1572                           struct mlx5e_cq_param *param,
1573                           struct mlx5e_create_cq_param *ccp,
1574                           struct mlx5e_cq *cq)
1575 {
1576         int err;
1577
1578         param->wq.buf_numa_node = ccp->node;
1579         param->wq.db_numa_node  = ccp->node;
1580         param->eq_ix            = ccp->ix;
1581
1582         err = mlx5e_alloc_cq_common(priv, param, cq);
1583
1584         cq->napi     = ccp->napi;
1585         cq->ch_stats = ccp->ch_stats;
1586
1587         return err;
1588 }
1589
1590 static void mlx5e_free_cq(struct mlx5e_cq *cq)
1591 {
1592         mlx5_wq_destroy(&cq->wq_ctrl);
1593 }
1594
1595 static int mlx5e_create_cq(struct mlx5e_cq *cq, struct mlx5e_cq_param *param)
1596 {
1597         u32 out[MLX5_ST_SZ_DW(create_cq_out)];
1598         struct mlx5_core_dev *mdev = cq->mdev;
1599         struct mlx5_core_cq *mcq = &cq->mcq;
1600
1601         void *in;
1602         void *cqc;
1603         int inlen;
1604         unsigned int irqn_not_used;
1605         int eqn;
1606         int err;
1607
1608         err = mlx5_vector2eqn(mdev, param->eq_ix, &eqn, &irqn_not_used);
1609         if (err)
1610                 return err;
1611
1612         inlen = MLX5_ST_SZ_BYTES(create_cq_in) +
1613                 sizeof(u64) * cq->wq_ctrl.buf.npages;
1614         in = kvzalloc(inlen, GFP_KERNEL);
1615         if (!in)
1616                 return -ENOMEM;
1617
1618         cqc = MLX5_ADDR_OF(create_cq_in, in, cq_context);
1619
1620         memcpy(cqc, param->cqc, sizeof(param->cqc));
1621
1622         mlx5_fill_page_frag_array(&cq->wq_ctrl.buf,
1623                                   (__be64 *)MLX5_ADDR_OF(create_cq_in, in, pas));
1624
1625         MLX5_SET(cqc,   cqc, cq_period_mode, param->cq_period_mode);
1626         MLX5_SET(cqc,   cqc, c_eqn,         eqn);
1627         MLX5_SET(cqc,   cqc, uar_page,      mdev->priv.uar->index);
1628         MLX5_SET(cqc,   cqc, log_page_size, cq->wq_ctrl.buf.page_shift -
1629                                             MLX5_ADAPTER_PAGE_SHIFT);
1630         MLX5_SET64(cqc, cqc, dbr_addr,      cq->wq_ctrl.db.dma);
1631
1632         err = mlx5_core_create_cq(mdev, mcq, in, inlen, out, sizeof(out));
1633
1634         kvfree(in);
1635
1636         if (err)
1637                 return err;
1638
1639         mlx5e_cq_arm(cq);
1640
1641         return 0;
1642 }
1643
1644 static void mlx5e_destroy_cq(struct mlx5e_cq *cq)
1645 {
1646         mlx5_core_destroy_cq(cq->mdev, &cq->mcq);
1647 }
1648
1649 int mlx5e_open_cq(struct mlx5e_priv *priv, struct dim_cq_moder moder,
1650                   struct mlx5e_cq_param *param, struct mlx5e_create_cq_param *ccp,
1651                   struct mlx5e_cq *cq)
1652 {
1653         struct mlx5_core_dev *mdev = priv->mdev;
1654         int err;
1655
1656         err = mlx5e_alloc_cq(priv, param, ccp, cq);
1657         if (err)
1658                 return err;
1659
1660         err = mlx5e_create_cq(cq, param);
1661         if (err)
1662                 goto err_free_cq;
1663
1664         if (MLX5_CAP_GEN(mdev, cq_moderation))
1665                 mlx5_core_modify_cq_moderation(mdev, &cq->mcq, moder.usec, moder.pkts);
1666         return 0;
1667
1668 err_free_cq:
1669         mlx5e_free_cq(cq);
1670
1671         return err;
1672 }
1673
1674 void mlx5e_close_cq(struct mlx5e_cq *cq)
1675 {
1676         mlx5e_destroy_cq(cq);
1677         mlx5e_free_cq(cq);
1678 }
1679
1680 static int mlx5e_open_tx_cqs(struct mlx5e_channel *c,
1681                              struct mlx5e_params *params,
1682                              struct mlx5e_create_cq_param *ccp,
1683                              struct mlx5e_channel_param *cparam)
1684 {
1685         int err;
1686         int tc;
1687
1688         for (tc = 0; tc < c->num_tc; tc++) {
1689                 err = mlx5e_open_cq(c->priv, params->tx_cq_moderation, &cparam->txq_sq.cqp,
1690                                     ccp, &c->sq[tc].cq);
1691                 if (err)
1692                         goto err_close_tx_cqs;
1693         }
1694
1695         return 0;
1696
1697 err_close_tx_cqs:
1698         for (tc--; tc >= 0; tc--)
1699                 mlx5e_close_cq(&c->sq[tc].cq);
1700
1701         return err;
1702 }
1703
1704 static void mlx5e_close_tx_cqs(struct mlx5e_channel *c)
1705 {
1706         int tc;
1707
1708         for (tc = 0; tc < c->num_tc; tc++)
1709                 mlx5e_close_cq(&c->sq[tc].cq);
1710 }
1711
1712 static int mlx5e_open_sqs(struct mlx5e_channel *c,
1713                           struct mlx5e_params *params,
1714                           struct mlx5e_channel_param *cparam)
1715 {
1716         int err, tc;
1717
1718         for (tc = 0; tc < params->num_tc; tc++) {
1719                 int txq_ix = c->ix + tc * params->num_channels;
1720
1721                 err = mlx5e_open_txqsq(c, c->priv->tisn[c->lag_port][tc], txq_ix,
1722                                        params, &cparam->txq_sq, &c->sq[tc], tc, 0, 0);
1723                 if (err)
1724                         goto err_close_sqs;
1725         }
1726
1727         return 0;
1728
1729 err_close_sqs:
1730         for (tc--; tc >= 0; tc--)
1731                 mlx5e_close_txqsq(&c->sq[tc]);
1732
1733         return err;
1734 }
1735
1736 static void mlx5e_close_sqs(struct mlx5e_channel *c)
1737 {
1738         int tc;
1739
1740         for (tc = 0; tc < c->num_tc; tc++)
1741                 mlx5e_close_txqsq(&c->sq[tc]);
1742 }
1743
1744 static int mlx5e_set_sq_maxrate(struct net_device *dev,
1745                                 struct mlx5e_txqsq *sq, u32 rate)
1746 {
1747         struct mlx5e_priv *priv = netdev_priv(dev);
1748         struct mlx5_core_dev *mdev = priv->mdev;
1749         struct mlx5e_modify_sq_param msp = {0};
1750         struct mlx5_rate_limit rl = {0};
1751         u16 rl_index = 0;
1752         int err;
1753
1754         if (rate == sq->rate_limit)
1755                 /* nothing to do */
1756                 return 0;
1757
1758         if (sq->rate_limit) {
1759                 rl.rate = sq->rate_limit;
1760                 /* remove current rl index to free space to next ones */
1761                 mlx5_rl_remove_rate(mdev, &rl);
1762         }
1763
1764         sq->rate_limit = 0;
1765
1766         if (rate) {
1767                 rl.rate = rate;
1768                 err = mlx5_rl_add_rate(mdev, &rl_index, &rl);
1769                 if (err) {
1770                         netdev_err(dev, "Failed configuring rate %u: %d\n",
1771                                    rate, err);
1772                         return err;
1773                 }
1774         }
1775
1776         msp.curr_state = MLX5_SQC_STATE_RDY;
1777         msp.next_state = MLX5_SQC_STATE_RDY;
1778         msp.rl_index   = rl_index;
1779         msp.rl_update  = true;
1780         err = mlx5e_modify_sq(mdev, sq->sqn, &msp);
1781         if (err) {
1782                 netdev_err(dev, "Failed configuring rate %u: %d\n",
1783                            rate, err);
1784                 /* remove the rate from the table */
1785                 if (rate)
1786                         mlx5_rl_remove_rate(mdev, &rl);
1787                 return err;
1788         }
1789
1790         sq->rate_limit = rate;
1791         return 0;
1792 }
1793
1794 static int mlx5e_set_tx_maxrate(struct net_device *dev, int index, u32 rate)
1795 {
1796         struct mlx5e_priv *priv = netdev_priv(dev);
1797         struct mlx5_core_dev *mdev = priv->mdev;
1798         struct mlx5e_txqsq *sq = priv->txq2sq[index];
1799         int err = 0;
1800
1801         if (!mlx5_rl_is_supported(mdev)) {
1802                 netdev_err(dev, "Rate limiting is not supported on this device\n");
1803                 return -EINVAL;
1804         }
1805
1806         /* rate is given in Mb/sec, HW config is in Kb/sec */
1807         rate = rate << 10;
1808
1809         /* Check whether rate in valid range, 0 is always valid */
1810         if (rate && !mlx5_rl_is_in_range(mdev, rate)) {
1811                 netdev_err(dev, "TX rate %u, is not in range\n", rate);
1812                 return -ERANGE;
1813         }
1814
1815         mutex_lock(&priv->state_lock);
1816         if (test_bit(MLX5E_STATE_OPENED, &priv->state))
1817                 err = mlx5e_set_sq_maxrate(dev, sq, rate);
1818         if (!err)
1819                 priv->tx_rates[index] = rate;
1820         mutex_unlock(&priv->state_lock);
1821
1822         return err;
1823 }
1824
1825 static int mlx5e_open_rxq_rq(struct mlx5e_channel *c, struct mlx5e_params *params,
1826                              struct mlx5e_rq_param *rq_params)
1827 {
1828         int err;
1829
1830         err = mlx5e_init_rxq_rq(c, params, &c->rq);
1831         if (err)
1832                 return err;
1833
1834         return mlx5e_open_rq(params, rq_params, NULL, cpu_to_node(c->cpu), &c->rq);
1835 }
1836
1837 static int mlx5e_open_queues(struct mlx5e_channel *c,
1838                              struct mlx5e_params *params,
1839                              struct mlx5e_channel_param *cparam)
1840 {
1841         struct dim_cq_moder icocq_moder = {0, 0};
1842         struct mlx5e_create_cq_param ccp;
1843         int err;
1844
1845         mlx5e_build_create_cq_param(&ccp, c);
1846
1847         err = mlx5e_open_cq(c->priv, icocq_moder, &cparam->async_icosq.cqp, &ccp,
1848                             &c->async_icosq.cq);
1849         if (err)
1850                 return err;
1851
1852         err = mlx5e_open_cq(c->priv, icocq_moder, &cparam->icosq.cqp, &ccp,
1853                             &c->icosq.cq);
1854         if (err)
1855                 goto err_close_async_icosq_cq;
1856
1857         err = mlx5e_open_tx_cqs(c, params, &ccp, cparam);
1858         if (err)
1859                 goto err_close_icosq_cq;
1860
1861         err = mlx5e_open_cq(c->priv, params->tx_cq_moderation, &cparam->xdp_sq.cqp, &ccp,
1862                             &c->xdpsq.cq);
1863         if (err)
1864                 goto err_close_tx_cqs;
1865
1866         err = mlx5e_open_cq(c->priv, params->rx_cq_moderation, &cparam->rq.cqp, &ccp,
1867                             &c->rq.cq);
1868         if (err)
1869                 goto err_close_xdp_tx_cqs;
1870
1871         err = c->xdp ? mlx5e_open_cq(c->priv, params->tx_cq_moderation, &cparam->xdp_sq.cqp,
1872                                      &ccp, &c->rq_xdpsq.cq) : 0;
1873         if (err)
1874                 goto err_close_rx_cq;
1875
1876         spin_lock_init(&c->async_icosq_lock);
1877
1878         err = mlx5e_open_icosq(c, params, &cparam->async_icosq, &c->async_icosq);
1879         if (err)
1880                 goto err_close_xdpsq_cq;
1881
1882         err = mlx5e_open_icosq(c, params, &cparam->icosq, &c->icosq);
1883         if (err)
1884                 goto err_close_async_icosq;
1885
1886         err = mlx5e_open_sqs(c, params, cparam);
1887         if (err)
1888                 goto err_close_icosq;
1889
1890         if (c->xdp) {
1891                 err = mlx5e_open_xdpsq(c, params, &cparam->xdp_sq, NULL,
1892                                        &c->rq_xdpsq, false);
1893                 if (err)
1894                         goto err_close_sqs;
1895         }
1896
1897         err = mlx5e_open_rxq_rq(c, params, &cparam->rq);
1898         if (err)
1899                 goto err_close_xdp_sq;
1900
1901         err = mlx5e_open_xdpsq(c, params, &cparam->xdp_sq, NULL, &c->xdpsq, true);
1902         if (err)
1903                 goto err_close_rq;
1904
1905         return 0;
1906
1907 err_close_rq:
1908         mlx5e_close_rq(&c->rq);
1909
1910 err_close_xdp_sq:
1911         if (c->xdp)
1912                 mlx5e_close_xdpsq(&c->rq_xdpsq);
1913
1914 err_close_sqs:
1915         mlx5e_close_sqs(c);
1916
1917 err_close_icosq:
1918         mlx5e_close_icosq(&c->icosq);
1919
1920 err_close_async_icosq:
1921         mlx5e_close_icosq(&c->async_icosq);
1922
1923 err_close_xdpsq_cq:
1924         if (c->xdp)
1925                 mlx5e_close_cq(&c->rq_xdpsq.cq);
1926
1927 err_close_rx_cq:
1928         mlx5e_close_cq(&c->rq.cq);
1929
1930 err_close_xdp_tx_cqs:
1931         mlx5e_close_cq(&c->xdpsq.cq);
1932
1933 err_close_tx_cqs:
1934         mlx5e_close_tx_cqs(c);
1935
1936 err_close_icosq_cq:
1937         mlx5e_close_cq(&c->icosq.cq);
1938
1939 err_close_async_icosq_cq:
1940         mlx5e_close_cq(&c->async_icosq.cq);
1941
1942         return err;
1943 }
1944
1945 static void mlx5e_close_queues(struct mlx5e_channel *c)
1946 {
1947         mlx5e_close_xdpsq(&c->xdpsq);
1948         mlx5e_close_rq(&c->rq);
1949         if (c->xdp)
1950                 mlx5e_close_xdpsq(&c->rq_xdpsq);
1951         mlx5e_close_sqs(c);
1952         mlx5e_close_icosq(&c->icosq);
1953         mlx5e_close_icosq(&c->async_icosq);
1954         if (c->xdp)
1955                 mlx5e_close_cq(&c->rq_xdpsq.cq);
1956         mlx5e_close_cq(&c->rq.cq);
1957         mlx5e_close_cq(&c->xdpsq.cq);
1958         mlx5e_close_tx_cqs(c);
1959         mlx5e_close_cq(&c->icosq.cq);
1960         mlx5e_close_cq(&c->async_icosq.cq);
1961 }
1962
1963 static u8 mlx5e_enumerate_lag_port(struct mlx5_core_dev *mdev, int ix)
1964 {
1965         u16 port_aff_bias = mlx5_core_is_pf(mdev) ? 0 : MLX5_CAP_GEN(mdev, vhca_id);
1966
1967         return (ix + port_aff_bias) % mlx5e_get_num_lag_ports(mdev);
1968 }
1969
1970 static int mlx5e_open_channel(struct mlx5e_priv *priv, int ix,
1971                               struct mlx5e_params *params,
1972                               struct mlx5e_channel_param *cparam,
1973                               struct xsk_buff_pool *xsk_pool,
1974                               struct mlx5e_channel **cp)
1975 {
1976         int cpu = cpumask_first(mlx5_comp_irq_get_affinity_mask(priv->mdev, ix));
1977         struct net_device *netdev = priv->netdev;
1978         struct mlx5e_xsk_param xsk;
1979         struct mlx5e_channel *c;
1980         unsigned int irq;
1981         int err;
1982         int eqn;
1983
1984         err = mlx5_vector2eqn(priv->mdev, ix, &eqn, &irq);
1985         if (err)
1986                 return err;
1987
1988         c = kvzalloc_node(sizeof(*c), GFP_KERNEL, cpu_to_node(cpu));
1989         if (!c)
1990                 return -ENOMEM;
1991
1992         c->priv     = priv;
1993         c->mdev     = priv->mdev;
1994         c->tstamp   = &priv->tstamp;
1995         c->ix       = ix;
1996         c->cpu      = cpu;
1997         c->pdev     = mlx5_core_dma_dev(priv->mdev);
1998         c->netdev   = priv->netdev;
1999         c->mkey_be  = cpu_to_be32(priv->mdev->mlx5e_res.hw_objs.mkey.key);
2000         c->num_tc   = params->num_tc;
2001         c->xdp      = !!params->xdp_prog;
2002         c->stats    = &priv->channel_stats[ix].ch;
2003         c->aff_mask = irq_get_effective_affinity_mask(irq);
2004         c->lag_port = mlx5e_enumerate_lag_port(priv->mdev, ix);
2005
2006         netif_napi_add(netdev, &c->napi, mlx5e_napi_poll, 64);
2007
2008         err = mlx5e_open_queues(c, params, cparam);
2009         if (unlikely(err))
2010                 goto err_napi_del;
2011
2012         if (xsk_pool) {
2013                 mlx5e_build_xsk_param(xsk_pool, &xsk);
2014                 err = mlx5e_open_xsk(priv, params, &xsk, xsk_pool, c);
2015                 if (unlikely(err))
2016                         goto err_close_queues;
2017         }
2018
2019         *cp = c;
2020
2021         return 0;
2022
2023 err_close_queues:
2024         mlx5e_close_queues(c);
2025
2026 err_napi_del:
2027         netif_napi_del(&c->napi);
2028
2029         kvfree(c);
2030
2031         return err;
2032 }
2033
2034 static void mlx5e_activate_channel(struct mlx5e_channel *c)
2035 {
2036         int tc;
2037
2038         napi_enable(&c->napi);
2039
2040         for (tc = 0; tc < c->num_tc; tc++)
2041                 mlx5e_activate_txqsq(&c->sq[tc]);
2042         mlx5e_activate_icosq(&c->icosq);
2043         mlx5e_activate_icosq(&c->async_icosq);
2044         mlx5e_activate_rq(&c->rq);
2045
2046         if (test_bit(MLX5E_CHANNEL_STATE_XSK, c->state))
2047                 mlx5e_activate_xsk(c);
2048 }
2049
2050 static void mlx5e_deactivate_channel(struct mlx5e_channel *c)
2051 {
2052         int tc;
2053
2054         if (test_bit(MLX5E_CHANNEL_STATE_XSK, c->state))
2055                 mlx5e_deactivate_xsk(c);
2056
2057         mlx5e_deactivate_rq(&c->rq);
2058         mlx5e_deactivate_icosq(&c->async_icosq);
2059         mlx5e_deactivate_icosq(&c->icosq);
2060         for (tc = 0; tc < c->num_tc; tc++)
2061                 mlx5e_deactivate_txqsq(&c->sq[tc]);
2062         mlx5e_qos_deactivate_queues(c);
2063
2064         napi_disable(&c->napi);
2065 }
2066
2067 static void mlx5e_close_channel(struct mlx5e_channel *c)
2068 {
2069         if (test_bit(MLX5E_CHANNEL_STATE_XSK, c->state))
2070                 mlx5e_close_xsk(c);
2071         mlx5e_close_queues(c);
2072         mlx5e_qos_close_queues(c);
2073         netif_napi_del(&c->napi);
2074
2075         kvfree(c);
2076 }
2077
2078 int mlx5e_open_channels(struct mlx5e_priv *priv,
2079                         struct mlx5e_channels *chs)
2080 {
2081         struct mlx5e_channel_param *cparam;
2082         int err = -ENOMEM;
2083         int i;
2084
2085         chs->num = chs->params.num_channels;
2086
2087         chs->c = kcalloc(chs->num, sizeof(struct mlx5e_channel *), GFP_KERNEL);
2088         cparam = kvzalloc(sizeof(struct mlx5e_channel_param), GFP_KERNEL);
2089         if (!chs->c || !cparam)
2090                 goto err_free;
2091
2092         err = mlx5e_build_channel_param(priv->mdev, &chs->params, priv->q_counter, cparam);
2093         if (err)
2094                 goto err_free;
2095
2096         for (i = 0; i < chs->num; i++) {
2097                 struct xsk_buff_pool *xsk_pool = NULL;
2098
2099                 if (chs->params.xdp_prog)
2100                         xsk_pool = mlx5e_xsk_get_pool(&chs->params, chs->params.xsk, i);
2101
2102                 err = mlx5e_open_channel(priv, i, &chs->params, cparam, xsk_pool, &chs->c[i]);
2103                 if (err)
2104                         goto err_close_channels;
2105         }
2106
2107         if (MLX5E_GET_PFLAG(&chs->params, MLX5E_PFLAG_TX_PORT_TS) || chs->params.ptp_rx) {
2108                 err = mlx5e_ptp_open(priv, &chs->params, chs->c[0]->lag_port, &chs->ptp);
2109                 if (err)
2110                         goto err_close_channels;
2111         }
2112
2113         err = mlx5e_qos_open_queues(priv, chs);
2114         if (err)
2115                 goto err_close_ptp;
2116
2117         mlx5e_health_channels_update(priv);
2118         kvfree(cparam);
2119         return 0;
2120
2121 err_close_ptp:
2122         if (chs->ptp)
2123                 mlx5e_ptp_close(chs->ptp);
2124
2125 err_close_channels:
2126         for (i--; i >= 0; i--)
2127                 mlx5e_close_channel(chs->c[i]);
2128
2129 err_free:
2130         kfree(chs->c);
2131         kvfree(cparam);
2132         chs->num = 0;
2133         return err;
2134 }
2135
2136 static void mlx5e_activate_channels(struct mlx5e_channels *chs)
2137 {
2138         int i;
2139
2140         for (i = 0; i < chs->num; i++)
2141                 mlx5e_activate_channel(chs->c[i]);
2142
2143         if (chs->ptp)
2144                 mlx5e_ptp_activate_channel(chs->ptp);
2145 }
2146
2147 #define MLX5E_RQ_WQES_TIMEOUT 20000 /* msecs */
2148
2149 static int mlx5e_wait_channels_min_rx_wqes(struct mlx5e_channels *chs)
2150 {
2151         int err = 0;
2152         int i;
2153
2154         for (i = 0; i < chs->num; i++) {
2155                 int timeout = err ? 0 : MLX5E_RQ_WQES_TIMEOUT;
2156
2157                 err |= mlx5e_wait_for_min_rx_wqes(&chs->c[i]->rq, timeout);
2158
2159                 /* Don't wait on the XSK RQ, because the newer xdpsock sample
2160                  * doesn't provide any Fill Ring entries at the setup stage.
2161                  */
2162         }
2163
2164         return err ? -ETIMEDOUT : 0;
2165 }
2166
2167 static void mlx5e_deactivate_channels(struct mlx5e_channels *chs)
2168 {
2169         int i;
2170
2171         if (chs->ptp)
2172                 mlx5e_ptp_deactivate_channel(chs->ptp);
2173
2174         for (i = 0; i < chs->num; i++)
2175                 mlx5e_deactivate_channel(chs->c[i]);
2176 }
2177
2178 void mlx5e_close_channels(struct mlx5e_channels *chs)
2179 {
2180         int i;
2181
2182         if (chs->ptp) {
2183                 mlx5e_ptp_close(chs->ptp);
2184                 chs->ptp = NULL;
2185         }
2186         for (i = 0; i < chs->num; i++)
2187                 mlx5e_close_channel(chs->c[i]);
2188
2189         kfree(chs->c);
2190         chs->num = 0;
2191 }
2192
2193 static int
2194 mlx5e_create_rqt(struct mlx5e_priv *priv, int sz, struct mlx5e_rqt *rqt)
2195 {
2196         struct mlx5_core_dev *mdev = priv->mdev;
2197         void *rqtc;
2198         int inlen;
2199         int err;
2200         u32 *in;
2201         int i;
2202
2203         inlen = MLX5_ST_SZ_BYTES(create_rqt_in) + sizeof(u32) * sz;
2204         in = kvzalloc(inlen, GFP_KERNEL);
2205         if (!in)
2206                 return -ENOMEM;
2207
2208         rqtc = MLX5_ADDR_OF(create_rqt_in, in, rqt_context);
2209
2210         MLX5_SET(rqtc, rqtc, rqt_actual_size, sz);
2211         MLX5_SET(rqtc, rqtc, rqt_max_size, sz);
2212
2213         for (i = 0; i < sz; i++)
2214                 MLX5_SET(rqtc, rqtc, rq_num[i], priv->drop_rq.rqn);
2215
2216         err = mlx5_core_create_rqt(mdev, in, inlen, &rqt->rqtn);
2217         if (!err)
2218                 rqt->enabled = true;
2219
2220         kvfree(in);
2221         return err;
2222 }
2223
2224 void mlx5e_destroy_rqt(struct mlx5e_priv *priv, struct mlx5e_rqt *rqt)
2225 {
2226         rqt->enabled = false;
2227         mlx5_core_destroy_rqt(priv->mdev, rqt->rqtn);
2228 }
2229
2230 int mlx5e_create_indirect_rqt(struct mlx5e_priv *priv)
2231 {
2232         struct mlx5e_rqt *rqt = &priv->indir_rqt;
2233         int err;
2234
2235         err = mlx5e_create_rqt(priv, MLX5E_INDIR_RQT_SIZE, rqt);
2236         if (err)
2237                 mlx5_core_warn(priv->mdev, "create indirect rqts failed, %d\n", err);
2238         return err;
2239 }
2240
2241 int mlx5e_create_direct_rqts(struct mlx5e_priv *priv, struct mlx5e_tir *tirs, int n)
2242 {
2243         int err;
2244         int ix;
2245
2246         for (ix = 0; ix < n; ix++) {
2247                 err = mlx5e_create_rqt(priv, 1 /*size */, &tirs[ix].rqt);
2248                 if (unlikely(err))
2249                         goto err_destroy_rqts;
2250         }
2251
2252         return 0;
2253
2254 err_destroy_rqts:
2255         mlx5_core_warn(priv->mdev, "create rqts failed, %d\n", err);
2256         for (ix--; ix >= 0; ix--)
2257                 mlx5e_destroy_rqt(priv, &tirs[ix].rqt);
2258
2259         return err;
2260 }
2261
2262 void mlx5e_destroy_direct_rqts(struct mlx5e_priv *priv, struct mlx5e_tir *tirs, int n)
2263 {
2264         int i;
2265
2266         for (i = 0; i < n; i++)
2267                 mlx5e_destroy_rqt(priv, &tirs[i].rqt);
2268 }
2269
2270 static int mlx5e_rx_hash_fn(int hfunc)
2271 {
2272         return (hfunc == ETH_RSS_HASH_TOP) ?
2273                MLX5_RX_HASH_FN_TOEPLITZ :
2274                MLX5_RX_HASH_FN_INVERTED_XOR8;
2275 }
2276
2277 int mlx5e_bits_invert(unsigned long a, int size)
2278 {
2279         int inv = 0;
2280         int i;
2281
2282         for (i = 0; i < size; i++)
2283                 inv |= (test_bit(size - i - 1, &a) ? 1 : 0) << i;
2284
2285         return inv;
2286 }
2287
2288 static void mlx5e_fill_rqt_rqns(struct mlx5e_priv *priv, int sz,
2289                                 struct mlx5e_redirect_rqt_param rrp, void *rqtc)
2290 {
2291         int i;
2292
2293         for (i = 0; i < sz; i++) {
2294                 u32 rqn;
2295
2296                 if (rrp.is_rss) {
2297                         int ix = i;
2298
2299                         if (rrp.rss.hfunc == ETH_RSS_HASH_XOR)
2300                                 ix = mlx5e_bits_invert(i, ilog2(sz));
2301
2302                         ix = priv->rss_params.indirection_rqt[ix];
2303                         rqn = rrp.rss.channels->c[ix]->rq.rqn;
2304                 } else {
2305                         rqn = rrp.rqn;
2306                 }
2307                 MLX5_SET(rqtc, rqtc, rq_num[i], rqn);
2308         }
2309 }
2310
2311 int mlx5e_redirect_rqt(struct mlx5e_priv *priv, u32 rqtn, int sz,
2312                        struct mlx5e_redirect_rqt_param rrp)
2313 {
2314         struct mlx5_core_dev *mdev = priv->mdev;
2315         void *rqtc;
2316         int inlen;
2317         u32 *in;
2318         int err;
2319
2320         inlen = MLX5_ST_SZ_BYTES(modify_rqt_in) + sizeof(u32) * sz;
2321         in = kvzalloc(inlen, GFP_KERNEL);
2322         if (!in)
2323                 return -ENOMEM;
2324
2325         rqtc = MLX5_ADDR_OF(modify_rqt_in, in, ctx);
2326
2327         MLX5_SET(rqtc, rqtc, rqt_actual_size, sz);
2328         MLX5_SET(modify_rqt_in, in, bitmask.rqn_list, 1);
2329         mlx5e_fill_rqt_rqns(priv, sz, rrp, rqtc);
2330         err = mlx5_core_modify_rqt(mdev, rqtn, in, inlen);
2331
2332         kvfree(in);
2333         return err;
2334 }
2335
2336 static u32 mlx5e_get_direct_rqn(struct mlx5e_priv *priv, int ix,
2337                                 struct mlx5e_redirect_rqt_param rrp)
2338 {
2339         if (!rrp.is_rss)
2340                 return rrp.rqn;
2341
2342         if (ix >= rrp.rss.channels->num)
2343                 return priv->drop_rq.rqn;
2344
2345         return rrp.rss.channels->c[ix]->rq.rqn;
2346 }
2347
2348 static void mlx5e_redirect_rqts(struct mlx5e_priv *priv,
2349                                 struct mlx5e_redirect_rqt_param rrp,
2350                                 struct mlx5e_redirect_rqt_param *ptp_rrp)
2351 {
2352         u32 rqtn;
2353         int ix;
2354
2355         if (priv->indir_rqt.enabled) {
2356                 /* RSS RQ table */
2357                 rqtn = priv->indir_rqt.rqtn;
2358                 mlx5e_redirect_rqt(priv, rqtn, MLX5E_INDIR_RQT_SIZE, rrp);
2359         }
2360
2361         for (ix = 0; ix < priv->max_nch; ix++) {
2362                 struct mlx5e_redirect_rqt_param direct_rrp = {
2363                         .is_rss = false,
2364                         {
2365                                 .rqn    = mlx5e_get_direct_rqn(priv, ix, rrp)
2366                         },
2367                 };
2368
2369                 /* Direct RQ Tables */
2370                 if (!priv->direct_tir[ix].rqt.enabled)
2371                         continue;
2372
2373                 rqtn = priv->direct_tir[ix].rqt.rqtn;
2374                 mlx5e_redirect_rqt(priv, rqtn, 1, direct_rrp);
2375         }
2376         if (ptp_rrp) {
2377                 rqtn = priv->ptp_tir.rqt.rqtn;
2378                 mlx5e_redirect_rqt(priv, rqtn, 1, *ptp_rrp);
2379         }
2380 }
2381
2382 static void mlx5e_redirect_rqts_to_channels(struct mlx5e_priv *priv,
2383                                             struct mlx5e_channels *chs)
2384 {
2385         bool rx_ptp_support = priv->profile->rx_ptp_support;
2386         struct mlx5e_redirect_rqt_param *ptp_rrp_p = NULL;
2387         struct mlx5e_redirect_rqt_param rrp = {
2388                 .is_rss        = true,
2389                 {
2390                         .rss = {
2391                                 .channels  = chs,
2392                                 .hfunc     = priv->rss_params.hfunc,
2393                         }
2394                 },
2395         };
2396         struct mlx5e_redirect_rqt_param ptp_rrp;
2397
2398         if (rx_ptp_support) {
2399                 u32 ptp_rqn;
2400
2401                 ptp_rrp.is_rss = false;
2402                 ptp_rrp.rqn = mlx5e_ptp_get_rqn(priv->channels.ptp, &ptp_rqn) ?
2403                               priv->drop_rq.rqn : ptp_rqn;
2404                 ptp_rrp_p = &ptp_rrp;
2405         }
2406         mlx5e_redirect_rqts(priv, rrp, ptp_rrp_p);
2407 }
2408
2409 static void mlx5e_redirect_rqts_to_drop(struct mlx5e_priv *priv)
2410 {
2411         bool rx_ptp_support = priv->profile->rx_ptp_support;
2412         struct mlx5e_redirect_rqt_param drop_rrp = {
2413                 .is_rss = false,
2414                 {
2415                         .rqn = priv->drop_rq.rqn,
2416                 },
2417         };
2418
2419         mlx5e_redirect_rqts(priv, drop_rrp, rx_ptp_support ? &drop_rrp : NULL);
2420 }
2421
2422 static const struct mlx5e_tirc_config tirc_default_config[MLX5E_NUM_INDIR_TIRS] = {
2423         [MLX5E_TT_IPV4_TCP] = { .l3_prot_type = MLX5_L3_PROT_TYPE_IPV4,
2424                                 .l4_prot_type = MLX5_L4_PROT_TYPE_TCP,
2425                                 .rx_hash_fields = MLX5_HASH_IP_L4PORTS,
2426         },
2427         [MLX5E_TT_IPV6_TCP] = { .l3_prot_type = MLX5_L3_PROT_TYPE_IPV6,
2428                                 .l4_prot_type = MLX5_L4_PROT_TYPE_TCP,
2429                                 .rx_hash_fields = MLX5_HASH_IP_L4PORTS,
2430         },
2431         [MLX5E_TT_IPV4_UDP] = { .l3_prot_type = MLX5_L3_PROT_TYPE_IPV4,
2432                                 .l4_prot_type = MLX5_L4_PROT_TYPE_UDP,
2433                                 .rx_hash_fields = MLX5_HASH_IP_L4PORTS,
2434         },
2435         [MLX5E_TT_IPV6_UDP] = { .l3_prot_type = MLX5_L3_PROT_TYPE_IPV6,
2436                                 .l4_prot_type = MLX5_L4_PROT_TYPE_UDP,
2437                                 .rx_hash_fields = MLX5_HASH_IP_L4PORTS,
2438         },
2439         [MLX5E_TT_IPV4_IPSEC_AH] = { .l3_prot_type = MLX5_L3_PROT_TYPE_IPV4,
2440                                      .l4_prot_type = 0,
2441                                      .rx_hash_fields = MLX5_HASH_IP_IPSEC_SPI,
2442         },
2443         [MLX5E_TT_IPV6_IPSEC_AH] = { .l3_prot_type = MLX5_L3_PROT_TYPE_IPV6,
2444                                      .l4_prot_type = 0,
2445                                      .rx_hash_fields = MLX5_HASH_IP_IPSEC_SPI,
2446         },
2447         [MLX5E_TT_IPV4_IPSEC_ESP] = { .l3_prot_type = MLX5_L3_PROT_TYPE_IPV4,
2448                                       .l4_prot_type = 0,
2449                                       .rx_hash_fields = MLX5_HASH_IP_IPSEC_SPI,
2450         },
2451         [MLX5E_TT_IPV6_IPSEC_ESP] = { .l3_prot_type = MLX5_L3_PROT_TYPE_IPV6,
2452                                       .l4_prot_type = 0,
2453                                       .rx_hash_fields = MLX5_HASH_IP_IPSEC_SPI,
2454         },
2455         [MLX5E_TT_IPV4] = { .l3_prot_type = MLX5_L3_PROT_TYPE_IPV4,
2456                             .l4_prot_type = 0,
2457                             .rx_hash_fields = MLX5_HASH_IP,
2458         },
2459         [MLX5E_TT_IPV6] = { .l3_prot_type = MLX5_L3_PROT_TYPE_IPV6,
2460                             .l4_prot_type = 0,
2461                             .rx_hash_fields = MLX5_HASH_IP,
2462         },
2463 };
2464
2465 struct mlx5e_tirc_config mlx5e_tirc_get_default_config(enum mlx5e_traffic_types tt)
2466 {
2467         return tirc_default_config[tt];
2468 }
2469
2470 static void mlx5e_build_tir_ctx_lro(struct mlx5e_params *params, void *tirc)
2471 {
2472         if (!params->lro_en)
2473                 return;
2474
2475 #define ROUGH_MAX_L2_L3_HDR_SZ 256
2476
2477         MLX5_SET(tirc, tirc, lro_enable_mask,
2478                  MLX5_TIRC_LRO_ENABLE_MASK_IPV4_LRO |
2479                  MLX5_TIRC_LRO_ENABLE_MASK_IPV6_LRO);
2480         MLX5_SET(tirc, tirc, lro_max_ip_payload_size,
2481                  (MLX5E_PARAMS_DEFAULT_LRO_WQE_SZ - ROUGH_MAX_L2_L3_HDR_SZ) >> 8);
2482         MLX5_SET(tirc, tirc, lro_timeout_period_usecs, params->lro_timeout);
2483 }
2484
2485 void mlx5e_build_indir_tir_ctx_hash(struct mlx5e_rss_params *rss_params,
2486                                     const struct mlx5e_tirc_config *ttconfig,
2487                                     void *tirc, bool inner)
2488 {
2489         void *hfso = inner ? MLX5_ADDR_OF(tirc, tirc, rx_hash_field_selector_inner) :
2490                              MLX5_ADDR_OF(tirc, tirc, rx_hash_field_selector_outer);
2491
2492         MLX5_SET(tirc, tirc, rx_hash_fn, mlx5e_rx_hash_fn(rss_params->hfunc));
2493         if (rss_params->hfunc == ETH_RSS_HASH_TOP) {
2494                 void *rss_key = MLX5_ADDR_OF(tirc, tirc,
2495                                              rx_hash_toeplitz_key);
2496                 size_t len = MLX5_FLD_SZ_BYTES(tirc,
2497                                                rx_hash_toeplitz_key);
2498
2499                 MLX5_SET(tirc, tirc, rx_hash_symmetric, 1);
2500                 memcpy(rss_key, rss_params->toeplitz_hash_key, len);
2501         }
2502         MLX5_SET(rx_hash_field_select, hfso, l3_prot_type,
2503                  ttconfig->l3_prot_type);
2504         MLX5_SET(rx_hash_field_select, hfso, l4_prot_type,
2505                  ttconfig->l4_prot_type);
2506         MLX5_SET(rx_hash_field_select, hfso, selected_fields,
2507                  ttconfig->rx_hash_fields);
2508 }
2509
2510 static void mlx5e_update_rx_hash_fields(struct mlx5e_tirc_config *ttconfig,
2511                                         enum mlx5e_traffic_types tt,
2512                                         u32 rx_hash_fields)
2513 {
2514         *ttconfig                = tirc_default_config[tt];
2515         ttconfig->rx_hash_fields = rx_hash_fields;
2516 }
2517
2518 void mlx5e_modify_tirs_hash(struct mlx5e_priv *priv, void *in)
2519 {
2520         void *tirc = MLX5_ADDR_OF(modify_tir_in, in, ctx);
2521         struct mlx5e_rss_params *rss = &priv->rss_params;
2522         struct mlx5_core_dev *mdev = priv->mdev;
2523         int ctxlen = MLX5_ST_SZ_BYTES(tirc);
2524         struct mlx5e_tirc_config ttconfig;
2525         int tt;
2526
2527         MLX5_SET(modify_tir_in, in, bitmask.hash, 1);
2528
2529         for (tt = 0; tt < MLX5E_NUM_INDIR_TIRS; tt++) {
2530                 memset(tirc, 0, ctxlen);
2531                 mlx5e_update_rx_hash_fields(&ttconfig, tt,
2532                                             rss->rx_hash_fields[tt]);
2533                 mlx5e_build_indir_tir_ctx_hash(rss, &ttconfig, tirc, false);
2534                 mlx5_core_modify_tir(mdev, priv->indir_tir[tt].tirn, in);
2535         }
2536
2537         /* Verify inner tirs resources allocated */
2538         if (!priv->inner_indir_tir[0].tirn)
2539                 return;
2540
2541         for (tt = 0; tt < MLX5E_NUM_INDIR_TIRS; tt++) {
2542                 memset(tirc, 0, ctxlen);
2543                 mlx5e_update_rx_hash_fields(&ttconfig, tt,
2544                                             rss->rx_hash_fields[tt]);
2545                 mlx5e_build_indir_tir_ctx_hash(rss, &ttconfig, tirc, true);
2546                 mlx5_core_modify_tir(mdev, priv->inner_indir_tir[tt].tirn, in);
2547         }
2548 }
2549
2550 static int mlx5e_modify_tirs_lro(struct mlx5e_priv *priv)
2551 {
2552         struct mlx5_core_dev *mdev = priv->mdev;
2553
2554         void *in;
2555         void *tirc;
2556         int inlen;
2557         int err;
2558         int tt;
2559         int ix;
2560
2561         inlen = MLX5_ST_SZ_BYTES(modify_tir_in);
2562         in = kvzalloc(inlen, GFP_KERNEL);
2563         if (!in)
2564                 return -ENOMEM;
2565
2566         MLX5_SET(modify_tir_in, in, bitmask.lro, 1);
2567         tirc = MLX5_ADDR_OF(modify_tir_in, in, ctx);
2568
2569         mlx5e_build_tir_ctx_lro(&priv->channels.params, tirc);
2570
2571         for (tt = 0; tt < MLX5E_NUM_INDIR_TIRS; tt++) {
2572                 err = mlx5_core_modify_tir(mdev, priv->indir_tir[tt].tirn, in);
2573                 if (err)
2574                         goto free_in;
2575         }
2576
2577         for (ix = 0; ix < priv->max_nch; ix++) {
2578                 err = mlx5_core_modify_tir(mdev, priv->direct_tir[ix].tirn, in);
2579                 if (err)
2580                         goto free_in;
2581         }
2582
2583 free_in:
2584         kvfree(in);
2585
2586         return err;
2587 }
2588
2589 static MLX5E_DEFINE_PREACTIVATE_WRAPPER_CTX(mlx5e_modify_tirs_lro);
2590
2591 static int mlx5e_set_mtu(struct mlx5_core_dev *mdev,
2592                          struct mlx5e_params *params, u16 mtu)
2593 {
2594         u16 hw_mtu = MLX5E_SW2HW_MTU(params, mtu);
2595         int err;
2596
2597         err = mlx5_set_port_mtu(mdev, hw_mtu, 1);
2598         if (err)
2599                 return err;
2600
2601         /* Update vport context MTU */
2602         mlx5_modify_nic_vport_mtu(mdev, hw_mtu);
2603         return 0;
2604 }
2605
2606 static void mlx5e_query_mtu(struct mlx5_core_dev *mdev,
2607                             struct mlx5e_params *params, u16 *mtu)
2608 {
2609         u16 hw_mtu = 0;
2610         int err;
2611
2612         err = mlx5_query_nic_vport_mtu(mdev, &hw_mtu);
2613         if (err || !hw_mtu) /* fallback to port oper mtu */
2614                 mlx5_query_port_oper_mtu(mdev, &hw_mtu, 1);
2615
2616         *mtu = MLX5E_HW2SW_MTU(params, hw_mtu);
2617 }
2618
2619 int mlx5e_set_dev_port_mtu(struct mlx5e_priv *priv)
2620 {
2621         struct mlx5e_params *params = &priv->channels.params;
2622         struct net_device *netdev = priv->netdev;
2623         struct mlx5_core_dev *mdev = priv->mdev;
2624         u16 mtu;
2625         int err;
2626
2627         err = mlx5e_set_mtu(mdev, params, params->sw_mtu);
2628         if (err)
2629                 return err;
2630
2631         mlx5e_query_mtu(mdev, params, &mtu);
2632         if (mtu != params->sw_mtu)
2633                 netdev_warn(netdev, "%s: VPort MTU %d is different than netdev mtu %d\n",
2634                             __func__, mtu, params->sw_mtu);
2635
2636         params->sw_mtu = mtu;
2637         return 0;
2638 }
2639
2640 MLX5E_DEFINE_PREACTIVATE_WRAPPER_CTX(mlx5e_set_dev_port_mtu);
2641
2642 void mlx5e_set_netdev_mtu_boundaries(struct mlx5e_priv *priv)
2643 {
2644         struct mlx5e_params *params = &priv->channels.params;
2645         struct net_device *netdev   = priv->netdev;
2646         struct mlx5_core_dev *mdev  = priv->mdev;
2647         u16 max_mtu;
2648
2649         /* MTU range: 68 - hw-specific max */
2650         netdev->min_mtu = ETH_MIN_MTU;
2651
2652         mlx5_query_port_max_mtu(mdev, &max_mtu, 1);
2653         netdev->max_mtu = min_t(unsigned int, MLX5E_HW2SW_MTU(params, max_mtu),
2654                                 ETH_MAX_MTU);
2655 }
2656
2657 static void mlx5e_netdev_set_tcs(struct net_device *netdev, u16 nch, u8 ntc)
2658 {
2659         int tc;
2660
2661         netdev_reset_tc(netdev);
2662
2663         if (ntc == 1)
2664                 return;
2665
2666         netdev_set_num_tc(netdev, ntc);
2667
2668         /* Map netdev TCs to offset 0
2669          * We have our own UP to TXQ mapping for QoS
2670          */
2671         for (tc = 0; tc < ntc; tc++)
2672                 netdev_set_tc_queue(netdev, tc, nch, 0);
2673 }
2674
2675 int mlx5e_update_tx_netdev_queues(struct mlx5e_priv *priv)
2676 {
2677         int qos_queues, nch, ntc, num_txqs, err;
2678
2679         qos_queues = mlx5e_qos_cur_leaf_nodes(priv);
2680
2681         nch = priv->channels.params.num_channels;
2682         ntc = priv->channels.params.num_tc;
2683         num_txqs = nch * ntc + qos_queues;
2684         if (MLX5E_GET_PFLAG(&priv->channels.params, MLX5E_PFLAG_TX_PORT_TS))
2685                 num_txqs += ntc;
2686
2687         mlx5e_dbg(DRV, priv, "Setting num_txqs %d\n", num_txqs);
2688         err = netif_set_real_num_tx_queues(priv->netdev, num_txqs);
2689         if (err)
2690                 netdev_warn(priv->netdev, "netif_set_real_num_tx_queues failed, %d\n", err);
2691
2692         return err;
2693 }
2694
2695 static int mlx5e_update_netdev_queues(struct mlx5e_priv *priv)
2696 {
2697         struct net_device *netdev = priv->netdev;
2698         int old_num_txqs, old_ntc;
2699         int num_rxqs, nch, ntc;
2700         int err;
2701
2702         old_num_txqs = netdev->real_num_tx_queues;
2703         old_ntc = netdev->num_tc ? : 1;
2704
2705         nch = priv->channels.params.num_channels;
2706         ntc = priv->channels.params.num_tc;
2707         num_rxqs = nch * priv->profile->rq_groups;
2708         if (priv->channels.params.ptp_rx)
2709                 num_rxqs++;
2710
2711         mlx5e_netdev_set_tcs(netdev, nch, ntc);
2712
2713         err = mlx5e_update_tx_netdev_queues(priv);
2714         if (err)
2715                 goto err_tcs;
2716         err = netif_set_real_num_rx_queues(netdev, num_rxqs);
2717         if (err) {
2718                 netdev_warn(netdev, "netif_set_real_num_rx_queues failed, %d\n", err);
2719                 goto err_txqs;
2720         }
2721
2722         return 0;
2723
2724 err_txqs:
2725         /* netif_set_real_num_rx_queues could fail only when nch increased. Only
2726          * one of nch and ntc is changed in this function. That means, the call
2727          * to netif_set_real_num_tx_queues below should not fail, because it
2728          * decreases the number of TX queues.
2729          */
2730         WARN_ON_ONCE(netif_set_real_num_tx_queues(netdev, old_num_txqs));
2731
2732 err_tcs:
2733         mlx5e_netdev_set_tcs(netdev, old_num_txqs / old_ntc, old_ntc);
2734         return err;
2735 }
2736
2737 static void mlx5e_set_default_xps_cpumasks(struct mlx5e_priv *priv,
2738                                            struct mlx5e_params *params)
2739 {
2740         struct mlx5_core_dev *mdev = priv->mdev;
2741         int num_comp_vectors, ix, irq;
2742
2743         num_comp_vectors = mlx5_comp_vectors_count(mdev);
2744
2745         for (ix = 0; ix < params->num_channels; ix++) {
2746                 cpumask_clear(priv->scratchpad.cpumask);
2747
2748                 for (irq = ix; irq < num_comp_vectors; irq += params->num_channels) {
2749                         int cpu = cpumask_first(mlx5_comp_irq_get_affinity_mask(mdev, irq));
2750
2751                         cpumask_set_cpu(cpu, priv->scratchpad.cpumask);
2752                 }
2753
2754                 netif_set_xps_queue(priv->netdev, priv->scratchpad.cpumask, ix);
2755         }
2756 }
2757
2758 int mlx5e_num_channels_changed(struct mlx5e_priv *priv)
2759 {
2760         u16 count = priv->channels.params.num_channels;
2761         int err;
2762
2763         err = mlx5e_update_netdev_queues(priv);
2764         if (err)
2765                 return err;
2766
2767         mlx5e_set_default_xps_cpumasks(priv, &priv->channels.params);
2768
2769         if (!netif_is_rxfh_configured(priv->netdev))
2770                 mlx5e_build_default_indir_rqt(priv->rss_params.indirection_rqt,
2771                                               MLX5E_INDIR_RQT_SIZE, count);
2772
2773         return 0;
2774 }
2775
2776 MLX5E_DEFINE_PREACTIVATE_WRAPPER_CTX(mlx5e_num_channels_changed);
2777
2778 static void mlx5e_build_txq_maps(struct mlx5e_priv *priv)
2779 {
2780         int i, ch, tc, num_tc;
2781
2782         ch = priv->channels.num;
2783         num_tc = priv->channels.params.num_tc;
2784
2785         for (i = 0; i < ch; i++) {
2786                 for (tc = 0; tc < num_tc; tc++) {
2787                         struct mlx5e_channel *c = priv->channels.c[i];
2788                         struct mlx5e_txqsq *sq = &c->sq[tc];
2789
2790                         priv->txq2sq[sq->txq_ix] = sq;
2791                         priv->channel_tc2realtxq[i][tc] = i + tc * ch;
2792                 }
2793         }
2794
2795         if (!priv->channels.ptp)
2796                 return;
2797
2798         if (!test_bit(MLX5E_PTP_STATE_TX, priv->channels.ptp->state))
2799                 return;
2800
2801         for (tc = 0; tc < num_tc; tc++) {
2802                 struct mlx5e_ptp *c = priv->channels.ptp;
2803                 struct mlx5e_txqsq *sq = &c->ptpsq[tc].txqsq;
2804
2805                 priv->txq2sq[sq->txq_ix] = sq;
2806                 priv->port_ptp_tc2realtxq[tc] = priv->num_tc_x_num_ch + tc;
2807         }
2808 }
2809
2810 static void mlx5e_update_num_tc_x_num_ch(struct mlx5e_priv *priv)
2811 {
2812         /* Sync with mlx5e_select_queue. */
2813         WRITE_ONCE(priv->num_tc_x_num_ch,
2814                    priv->channels.params.num_tc * priv->channels.num);
2815 }
2816
2817 void mlx5e_activate_priv_channels(struct mlx5e_priv *priv)
2818 {
2819         mlx5e_update_num_tc_x_num_ch(priv);
2820         mlx5e_build_txq_maps(priv);
2821         mlx5e_activate_channels(&priv->channels);
2822         mlx5e_qos_activate_queues(priv);
2823         mlx5e_xdp_tx_enable(priv);
2824         netif_tx_start_all_queues(priv->netdev);
2825
2826         if (mlx5e_is_vport_rep(priv))
2827                 mlx5e_add_sqs_fwd_rules(priv);
2828
2829         mlx5e_wait_channels_min_rx_wqes(&priv->channels);
2830         mlx5e_redirect_rqts_to_channels(priv, &priv->channels);
2831
2832         mlx5e_xsk_redirect_rqts_to_channels(priv, &priv->channels);
2833 }
2834
2835 void mlx5e_deactivate_priv_channels(struct mlx5e_priv *priv)
2836 {
2837         mlx5e_xsk_redirect_rqts_to_drop(priv, &priv->channels);
2838
2839         mlx5e_redirect_rqts_to_drop(priv);
2840
2841         if (mlx5e_is_vport_rep(priv))
2842                 mlx5e_remove_sqs_fwd_rules(priv);
2843
2844         /* FIXME: This is a W/A only for tx timeout watch dog false alarm when
2845          * polling for inactive tx queues.
2846          */
2847         netif_tx_stop_all_queues(priv->netdev);
2848         netif_tx_disable(priv->netdev);
2849         mlx5e_xdp_tx_disable(priv);
2850         mlx5e_deactivate_channels(&priv->channels);
2851 }
2852
2853 static int mlx5e_switch_priv_params(struct mlx5e_priv *priv,
2854                                     struct mlx5e_params *new_params,
2855                                     mlx5e_fp_preactivate preactivate,
2856                                     void *context)
2857 {
2858         struct mlx5e_params old_params;
2859
2860         old_params = priv->channels.params;
2861         priv->channels.params = *new_params;
2862
2863         if (preactivate) {
2864                 int err;
2865
2866                 err = preactivate(priv, context);
2867                 if (err) {
2868                         priv->channels.params = old_params;
2869                         return err;
2870                 }
2871         }
2872
2873         return 0;
2874 }
2875
2876 static int mlx5e_switch_priv_channels(struct mlx5e_priv *priv,
2877                                       struct mlx5e_channels *new_chs,
2878                                       mlx5e_fp_preactivate preactivate,
2879                                       void *context)
2880 {
2881         struct net_device *netdev = priv->netdev;
2882         struct mlx5e_channels old_chs;
2883         int carrier_ok;
2884         int err = 0;
2885
2886         carrier_ok = netif_carrier_ok(netdev);
2887         netif_carrier_off(netdev);
2888
2889         mlx5e_deactivate_priv_channels(priv);
2890
2891         old_chs = priv->channels;
2892         priv->channels = *new_chs;
2893
2894         /* New channels are ready to roll, call the preactivate hook if needed
2895          * to modify HW settings or update kernel parameters.
2896          */
2897         if (preactivate) {
2898                 err = preactivate(priv, context);
2899                 if (err) {
2900                         priv->channels = old_chs;
2901                         goto out;
2902                 }
2903         }
2904
2905         mlx5e_close_channels(&old_chs);
2906         priv->profile->update_rx(priv);
2907
2908 out:
2909         mlx5e_activate_priv_channels(priv);
2910
2911         /* return carrier back if needed */
2912         if (carrier_ok)
2913                 netif_carrier_on(netdev);
2914
2915         return err;
2916 }
2917
2918 int mlx5e_safe_switch_params(struct mlx5e_priv *priv,
2919                              struct mlx5e_params *params,
2920                              mlx5e_fp_preactivate preactivate,
2921                              void *context, bool reset)
2922 {
2923         struct mlx5e_channels new_chs = {};
2924         int err;
2925
2926         reset &= test_bit(MLX5E_STATE_OPENED, &priv->state);
2927         if (!reset)
2928                 return mlx5e_switch_priv_params(priv, params, preactivate, context);
2929
2930         new_chs.params = *params;
2931         err = mlx5e_open_channels(priv, &new_chs);
2932         if (err)
2933                 return err;
2934         err = mlx5e_switch_priv_channels(priv, &new_chs, preactivate, context);
2935         if (err)
2936                 mlx5e_close_channels(&new_chs);
2937
2938         return err;
2939 }
2940
2941 int mlx5e_safe_reopen_channels(struct mlx5e_priv *priv)
2942 {
2943         return mlx5e_safe_switch_params(priv, &priv->channels.params, NULL, NULL, true);
2944 }
2945
2946 void mlx5e_timestamp_init(struct mlx5e_priv *priv)
2947 {
2948         priv->tstamp.tx_type   = HWTSTAMP_TX_OFF;
2949         priv->tstamp.rx_filter = HWTSTAMP_FILTER_NONE;
2950 }
2951
2952 static void mlx5e_modify_admin_state(struct mlx5_core_dev *mdev,
2953                                      enum mlx5_port_status state)
2954 {
2955         struct mlx5_eswitch *esw = mdev->priv.eswitch;
2956         int vport_admin_state;
2957
2958         mlx5_set_port_admin_status(mdev, state);
2959
2960         if (mlx5_eswitch_mode(mdev) == MLX5_ESWITCH_OFFLOADS ||
2961             !MLX5_CAP_GEN(mdev, uplink_follow))
2962                 return;
2963
2964         if (state == MLX5_PORT_UP)
2965                 vport_admin_state = MLX5_VPORT_ADMIN_STATE_AUTO;
2966         else
2967                 vport_admin_state = MLX5_VPORT_ADMIN_STATE_DOWN;
2968
2969         mlx5_eswitch_set_vport_state(esw, MLX5_VPORT_UPLINK, vport_admin_state);
2970 }
2971
2972 int mlx5e_open_locked(struct net_device *netdev)
2973 {
2974         struct mlx5e_priv *priv = netdev_priv(netdev);
2975         int err;
2976
2977         set_bit(MLX5E_STATE_OPENED, &priv->state);
2978
2979         err = mlx5e_open_channels(priv, &priv->channels);
2980         if (err)
2981                 goto err_clear_state_opened_flag;
2982
2983         priv->profile->update_rx(priv);
2984         mlx5e_activate_priv_channels(priv);
2985         mlx5e_apply_traps(priv, true);
2986         if (priv->profile->update_carrier)
2987                 priv->profile->update_carrier(priv);
2988
2989         mlx5e_queue_update_stats(priv);
2990         return 0;
2991
2992 err_clear_state_opened_flag:
2993         clear_bit(MLX5E_STATE_OPENED, &priv->state);
2994         return err;
2995 }
2996
2997 int mlx5e_open(struct net_device *netdev)
2998 {
2999         struct mlx5e_priv *priv = netdev_priv(netdev);
3000         int err;
3001
3002         mutex_lock(&priv->state_lock);
3003         err = mlx5e_open_locked(netdev);
3004         if (!err)
3005                 mlx5e_modify_admin_state(priv->mdev, MLX5_PORT_UP);
3006         mutex_unlock(&priv->state_lock);
3007
3008         return err;
3009 }
3010
3011 int mlx5e_close_locked(struct net_device *netdev)
3012 {
3013         struct mlx5e_priv *priv = netdev_priv(netdev);
3014
3015         /* May already be CLOSED in case a previous configuration operation
3016          * (e.g RX/TX queue size change) that involves close&open failed.
3017          */
3018         if (!test_bit(MLX5E_STATE_OPENED, &priv->state))
3019                 return 0;
3020
3021         mlx5e_apply_traps(priv, false);
3022         clear_bit(MLX5E_STATE_OPENED, &priv->state);
3023
3024         netif_carrier_off(priv->netdev);
3025         mlx5e_deactivate_priv_channels(priv);
3026         mlx5e_close_channels(&priv->channels);
3027
3028         return 0;
3029 }
3030
3031 int mlx5e_close(struct net_device *netdev)
3032 {
3033         struct mlx5e_priv *priv = netdev_priv(netdev);
3034         int err;
3035
3036         if (!netif_device_present(netdev))
3037                 return -ENODEV;
3038
3039         mutex_lock(&priv->state_lock);
3040         mlx5e_modify_admin_state(priv->mdev, MLX5_PORT_DOWN);
3041         err = mlx5e_close_locked(netdev);
3042         mutex_unlock(&priv->state_lock);
3043
3044         return err;
3045 }
3046
3047 static void mlx5e_free_drop_rq(struct mlx5e_rq *rq)
3048 {
3049         mlx5_wq_destroy(&rq->wq_ctrl);
3050 }
3051
3052 static int mlx5e_alloc_drop_rq(struct mlx5_core_dev *mdev,
3053                                struct mlx5e_rq *rq,
3054                                struct mlx5e_rq_param *param)
3055 {
3056         void *rqc = param->rqc;
3057         void *rqc_wq = MLX5_ADDR_OF(rqc, rqc, wq);
3058         int err;
3059
3060         param->wq.db_numa_node = param->wq.buf_numa_node;
3061
3062         err = mlx5_wq_cyc_create(mdev, &param->wq, rqc_wq, &rq->wqe.wq,
3063                                  &rq->wq_ctrl);
3064         if (err)
3065                 return err;
3066
3067         /* Mark as unused given "Drop-RQ" packets never reach XDP */
3068         xdp_rxq_info_unused(&rq->xdp_rxq);
3069
3070         rq->mdev = mdev;
3071
3072         return 0;
3073 }
3074
3075 static int mlx5e_alloc_drop_cq(struct mlx5e_priv *priv,
3076                                struct mlx5e_cq *cq,
3077                                struct mlx5e_cq_param *param)
3078 {
3079         struct mlx5_core_dev *mdev = priv->mdev;
3080
3081         param->wq.buf_numa_node = dev_to_node(mlx5_core_dma_dev(mdev));
3082         param->wq.db_numa_node  = dev_to_node(mlx5_core_dma_dev(mdev));
3083
3084         return mlx5e_alloc_cq_common(priv, param, cq);
3085 }
3086
3087 int mlx5e_open_drop_rq(struct mlx5e_priv *priv,
3088                        struct mlx5e_rq *drop_rq)
3089 {
3090         struct mlx5_core_dev *mdev = priv->mdev;
3091         struct mlx5e_cq_param cq_param = {};
3092         struct mlx5e_rq_param rq_param = {};
3093         struct mlx5e_cq *cq = &drop_rq->cq;
3094         int err;
3095
3096         mlx5e_build_drop_rq_param(mdev, priv->drop_rq_q_counter, &rq_param);
3097
3098         err = mlx5e_alloc_drop_cq(priv, cq, &cq_param);
3099         if (err)
3100                 return err;
3101
3102         err = mlx5e_create_cq(cq, &cq_param);
3103         if (err)
3104                 goto err_free_cq;
3105
3106         err = mlx5e_alloc_drop_rq(mdev, drop_rq, &rq_param);
3107         if (err)
3108                 goto err_destroy_cq;
3109
3110         err = mlx5e_create_rq(drop_rq, &rq_param);
3111         if (err)
3112                 goto err_free_rq;
3113
3114         err = mlx5e_modify_rq_state(drop_rq, MLX5_RQC_STATE_RST, MLX5_RQC_STATE_RDY);
3115         if (err)
3116                 mlx5_core_warn(priv->mdev, "modify_rq_state failed, rx_if_down_packets won't be counted %d\n", err);
3117
3118         return 0;
3119
3120 err_free_rq:
3121         mlx5e_free_drop_rq(drop_rq);
3122
3123 err_destroy_cq:
3124         mlx5e_destroy_cq(cq);
3125
3126 err_free_cq:
3127         mlx5e_free_cq(cq);
3128
3129         return err;
3130 }
3131
3132 void mlx5e_close_drop_rq(struct mlx5e_rq *drop_rq)
3133 {
3134         mlx5e_destroy_rq(drop_rq);
3135         mlx5e_free_drop_rq(drop_rq);
3136         mlx5e_destroy_cq(&drop_rq->cq);
3137         mlx5e_free_cq(&drop_rq->cq);
3138 }
3139
3140 int mlx5e_create_tis(struct mlx5_core_dev *mdev, void *in, u32 *tisn)
3141 {
3142         void *tisc = MLX5_ADDR_OF(create_tis_in, in, ctx);
3143
3144         MLX5_SET(tisc, tisc, transport_domain, mdev->mlx5e_res.hw_objs.td.tdn);
3145
3146         if (MLX5_GET(tisc, tisc, tls_en))
3147                 MLX5_SET(tisc, tisc, pd, mdev->mlx5e_res.hw_objs.pdn);
3148
3149         if (mlx5_lag_is_lacp_owner(mdev))
3150                 MLX5_SET(tisc, tisc, strict_lag_tx_port_affinity, 1);
3151
3152         return mlx5_core_create_tis(mdev, in, tisn);
3153 }
3154
3155 void mlx5e_destroy_tis(struct mlx5_core_dev *mdev, u32 tisn)
3156 {
3157         mlx5_core_destroy_tis(mdev, tisn);
3158 }
3159
3160 void mlx5e_destroy_tises(struct mlx5e_priv *priv)
3161 {
3162         int tc, i;
3163
3164         for (i = 0; i < mlx5e_get_num_lag_ports(priv->mdev); i++)
3165                 for (tc = 0; tc < priv->profile->max_tc; tc++)
3166                         mlx5e_destroy_tis(priv->mdev, priv->tisn[i][tc]);
3167 }
3168
3169 static bool mlx5e_lag_should_assign_affinity(struct mlx5_core_dev *mdev)
3170 {
3171         return MLX5_CAP_GEN(mdev, lag_tx_port_affinity) && mlx5e_get_num_lag_ports(mdev) > 1;
3172 }
3173
3174 int mlx5e_create_tises(struct mlx5e_priv *priv)
3175 {
3176         int tc, i;
3177         int err;
3178
3179         for (i = 0; i < mlx5e_get_num_lag_ports(priv->mdev); i++) {
3180                 for (tc = 0; tc < priv->profile->max_tc; tc++) {
3181                         u32 in[MLX5_ST_SZ_DW(create_tis_in)] = {};
3182                         void *tisc;
3183
3184                         tisc = MLX5_ADDR_OF(create_tis_in, in, ctx);
3185
3186                         MLX5_SET(tisc, tisc, prio, tc << 1);
3187
3188                         if (mlx5e_lag_should_assign_affinity(priv->mdev))
3189                                 MLX5_SET(tisc, tisc, lag_tx_port_affinity, i + 1);
3190
3191                         err = mlx5e_create_tis(priv->mdev, in, &priv->tisn[i][tc]);
3192                         if (err)
3193                                 goto err_close_tises;
3194                 }
3195         }
3196
3197         return 0;
3198
3199 err_close_tises:
3200         for (; i >= 0; i--) {
3201                 for (tc--; tc >= 0; tc--)
3202                         mlx5e_destroy_tis(priv->mdev, priv->tisn[i][tc]);
3203                 tc = priv->profile->max_tc;
3204         }
3205
3206         return err;
3207 }
3208
3209 static void mlx5e_cleanup_nic_tx(struct mlx5e_priv *priv)
3210 {
3211         mlx5e_destroy_tises(priv);
3212 }
3213
3214 static void mlx5e_build_indir_tir_ctx_common(struct mlx5e_priv *priv,
3215                                              u32 rqtn, u32 *tirc)
3216 {
3217         MLX5_SET(tirc, tirc, transport_domain, priv->mdev->mlx5e_res.hw_objs.td.tdn);
3218         MLX5_SET(tirc, tirc, disp_type, MLX5_TIRC_DISP_TYPE_INDIRECT);
3219         MLX5_SET(tirc, tirc, indirect_table, rqtn);
3220         MLX5_SET(tirc, tirc, tunneled_offload_en,
3221                  priv->channels.params.tunneled_offload_en);
3222
3223         mlx5e_build_tir_ctx_lro(&priv->channels.params, tirc);
3224 }
3225
3226 static void mlx5e_build_indir_tir_ctx(struct mlx5e_priv *priv,
3227                                       enum mlx5e_traffic_types tt,
3228                                       u32 *tirc)
3229 {
3230         mlx5e_build_indir_tir_ctx_common(priv, priv->indir_rqt.rqtn, tirc);
3231         mlx5e_build_indir_tir_ctx_hash(&priv->rss_params,
3232                                        &tirc_default_config[tt], tirc, false);
3233 }
3234
3235 static void mlx5e_build_direct_tir_ctx(struct mlx5e_priv *priv, u32 rqtn, u32 *tirc)
3236 {
3237         mlx5e_build_indir_tir_ctx_common(priv, rqtn, tirc);
3238         MLX5_SET(tirc, tirc, rx_hash_fn, MLX5_RX_HASH_FN_INVERTED_XOR8);
3239 }
3240
3241 static void mlx5e_build_inner_indir_tir_ctx(struct mlx5e_priv *priv,
3242                                             enum mlx5e_traffic_types tt,
3243                                             u32 *tirc)
3244 {
3245         mlx5e_build_indir_tir_ctx_common(priv, priv->indir_rqt.rqtn, tirc);
3246         mlx5e_build_indir_tir_ctx_hash(&priv->rss_params,
3247                                        &tirc_default_config[tt], tirc, true);
3248 }
3249
3250 int mlx5e_create_indirect_tirs(struct mlx5e_priv *priv, bool inner_ttc)
3251 {
3252         struct mlx5e_tir *tir;
3253         void *tirc;
3254         int inlen;
3255         int i = 0;
3256         int err;
3257         u32 *in;
3258         int tt;
3259
3260         inlen = MLX5_ST_SZ_BYTES(create_tir_in);
3261         in = kvzalloc(inlen, GFP_KERNEL);
3262         if (!in)
3263                 return -ENOMEM;
3264
3265         for (tt = 0; tt < MLX5E_NUM_INDIR_TIRS; tt++) {
3266                 memset(in, 0, inlen);
3267                 tir = &priv->indir_tir[tt];
3268                 tirc = MLX5_ADDR_OF(create_tir_in, in, ctx);
3269                 mlx5e_build_indir_tir_ctx(priv, tt, tirc);
3270                 err = mlx5e_create_tir(priv->mdev, tir, in);
3271                 if (err) {
3272                         mlx5_core_warn(priv->mdev, "create indirect tirs failed, %d\n", err);
3273                         goto err_destroy_inner_tirs;
3274                 }
3275         }
3276
3277         if (!inner_ttc || !mlx5e_tunnel_inner_ft_supported(priv->mdev))
3278                 goto out;
3279
3280         for (i = 0; i < MLX5E_NUM_INDIR_TIRS; i++) {
3281                 memset(in, 0, inlen);
3282                 tir = &priv->inner_indir_tir[i];
3283                 tirc = MLX5_ADDR_OF(create_tir_in, in, ctx);
3284                 mlx5e_build_inner_indir_tir_ctx(priv, i, tirc);
3285                 err = mlx5e_create_tir(priv->mdev, tir, in);
3286                 if (err) {
3287                         mlx5_core_warn(priv->mdev, "create inner indirect tirs failed, %d\n", err);
3288                         goto err_destroy_inner_tirs;
3289                 }
3290         }
3291
3292 out:
3293         kvfree(in);
3294
3295         return 0;
3296
3297 err_destroy_inner_tirs:
3298         for (i--; i >= 0; i--)
3299                 mlx5e_destroy_tir(priv->mdev, &priv->inner_indir_tir[i]);
3300
3301         for (tt--; tt >= 0; tt--)
3302                 mlx5e_destroy_tir(priv->mdev, &priv->indir_tir[tt]);
3303
3304         kvfree(in);
3305
3306         return err;
3307 }
3308
3309 int mlx5e_create_direct_tirs(struct mlx5e_priv *priv, struct mlx5e_tir *tirs, int n)
3310 {
3311         struct mlx5e_tir *tir;
3312         void *tirc;
3313         int inlen;
3314         int err = 0;
3315         u32 *in;
3316         int ix;
3317
3318         inlen = MLX5_ST_SZ_BYTES(create_tir_in);
3319         in = kvzalloc(inlen, GFP_KERNEL);
3320         if (!in)
3321                 return -ENOMEM;
3322
3323         for (ix = 0; ix < n; ix++) {
3324                 memset(in, 0, inlen);
3325                 tir = &tirs[ix];
3326                 tirc = MLX5_ADDR_OF(create_tir_in, in, ctx);
3327                 mlx5e_build_direct_tir_ctx(priv, tir->rqt.rqtn, tirc);
3328                 err = mlx5e_create_tir(priv->mdev, tir, in);
3329                 if (unlikely(err))
3330                         goto err_destroy_ch_tirs;
3331         }
3332
3333         goto out;
3334
3335 err_destroy_ch_tirs:
3336         mlx5_core_warn(priv->mdev, "create tirs failed, %d\n", err);
3337         for (ix--; ix >= 0; ix--)
3338                 mlx5e_destroy_tir(priv->mdev, &tirs[ix]);
3339
3340 out:
3341         kvfree(in);
3342
3343         return err;
3344 }
3345
3346 void mlx5e_destroy_indirect_tirs(struct mlx5e_priv *priv)
3347 {
3348         int i;
3349
3350         for (i = 0; i < MLX5E_NUM_INDIR_TIRS; i++)
3351                 mlx5e_destroy_tir(priv->mdev, &priv->indir_tir[i]);
3352
3353         /* Verify inner tirs resources allocated */
3354         if (!priv->inner_indir_tir[0].tirn)
3355                 return;
3356
3357         for (i = 0; i < MLX5E_NUM_INDIR_TIRS; i++)
3358                 mlx5e_destroy_tir(priv->mdev, &priv->inner_indir_tir[i]);
3359 }
3360
3361 void mlx5e_destroy_direct_tirs(struct mlx5e_priv *priv, struct mlx5e_tir *tirs, int n)
3362 {
3363         int i;
3364
3365         for (i = 0; i < n; i++)
3366                 mlx5e_destroy_tir(priv->mdev, &tirs[i]);
3367 }
3368
3369 static int mlx5e_modify_channels_scatter_fcs(struct mlx5e_channels *chs, bool enable)
3370 {
3371         int err = 0;
3372         int i;
3373
3374         for (i = 0; i < chs->num; i++) {
3375                 err = mlx5e_modify_rq_scatter_fcs(&chs->c[i]->rq, enable);
3376                 if (err)
3377                         return err;
3378         }
3379
3380         return 0;
3381 }
3382
3383 static int mlx5e_modify_channels_vsd(struct mlx5e_channels *chs, bool vsd)
3384 {
3385         int err = 0;
3386         int i;
3387
3388         for (i = 0; i < chs->num; i++) {
3389                 err = mlx5e_modify_rq_vsd(&chs->c[i]->rq, vsd);
3390                 if (err)
3391                         return err;
3392         }
3393
3394         return 0;
3395 }
3396
3397 static int mlx5e_setup_tc_mqprio(struct mlx5e_priv *priv,
3398                                  struct tc_mqprio_qopt *mqprio)
3399 {
3400         struct mlx5e_params new_params;
3401         u8 tc = mqprio->num_tc;
3402         int err = 0;
3403
3404         mqprio->hw = TC_MQPRIO_HW_OFFLOAD_TCS;
3405
3406         if (tc && tc != MLX5E_MAX_NUM_TC)
3407                 return -EINVAL;
3408
3409         mutex_lock(&priv->state_lock);
3410
3411         /* MQPRIO is another toplevel qdisc that can't be attached
3412          * simultaneously with the offloaded HTB.
3413          */
3414         if (WARN_ON(priv->htb.maj_id)) {
3415                 err = -EINVAL;
3416                 goto out;
3417         }
3418
3419         new_params = priv->channels.params;
3420         new_params.num_tc = tc ? tc : 1;
3421
3422         err = mlx5e_safe_switch_params(priv, &new_params,
3423                                        mlx5e_num_channels_changed_ctx, NULL, true);
3424
3425 out:
3426         priv->max_opened_tc = max_t(u8, priv->max_opened_tc,
3427                                     priv->channels.params.num_tc);
3428         mutex_unlock(&priv->state_lock);
3429         return err;
3430 }
3431
3432 static int mlx5e_setup_tc_htb(struct mlx5e_priv *priv, struct tc_htb_qopt_offload *htb)
3433 {
3434         int res;
3435
3436         switch (htb->command) {
3437         case TC_HTB_CREATE:
3438                 return mlx5e_htb_root_add(priv, htb->parent_classid, htb->classid,
3439                                           htb->extack);
3440         case TC_HTB_DESTROY:
3441                 return mlx5e_htb_root_del(priv);
3442         case TC_HTB_LEAF_ALLOC_QUEUE:
3443                 res = mlx5e_htb_leaf_alloc_queue(priv, htb->classid, htb->parent_classid,
3444                                                  htb->rate, htb->ceil, htb->extack);
3445                 if (res < 0)
3446                         return res;
3447                 htb->qid = res;
3448                 return 0;
3449         case TC_HTB_LEAF_TO_INNER:
3450                 return mlx5e_htb_leaf_to_inner(priv, htb->parent_classid, htb->classid,
3451                                                htb->rate, htb->ceil, htb->extack);
3452         case TC_HTB_LEAF_DEL:
3453                 return mlx5e_htb_leaf_del(priv, htb->classid, &htb->moved_qid, &htb->qid,
3454                                           htb->extack);
3455         case TC_HTB_LEAF_DEL_LAST:
3456         case TC_HTB_LEAF_DEL_LAST_FORCE:
3457                 return mlx5e_htb_leaf_del_last(priv, htb->classid,
3458                                                htb->command == TC_HTB_LEAF_DEL_LAST_FORCE,
3459                                                htb->extack);
3460         case TC_HTB_NODE_MODIFY:
3461                 return mlx5e_htb_node_modify(priv, htb->classid, htb->rate, htb->ceil,
3462                                              htb->extack);
3463         case TC_HTB_LEAF_QUERY_QUEUE:
3464                 res = mlx5e_get_txq_by_classid(priv, htb->classid);
3465                 if (res < 0)
3466                         return res;
3467                 htb->qid = res;
3468                 return 0;
3469         default:
3470                 return -EOPNOTSUPP;
3471         }
3472 }
3473
3474 static LIST_HEAD(mlx5e_block_cb_list);
3475
3476 static int mlx5e_setup_tc(struct net_device *dev, enum tc_setup_type type,
3477                           void *type_data)
3478 {
3479         struct mlx5e_priv *priv = netdev_priv(dev);
3480         bool tc_unbind = false;
3481         int err;
3482
3483         if (type == TC_SETUP_BLOCK &&
3484             ((struct flow_block_offload *)type_data)->command == FLOW_BLOCK_UNBIND)
3485                 tc_unbind = true;
3486
3487         if (!netif_device_present(dev) && !tc_unbind)
3488                 return -ENODEV;
3489
3490         switch (type) {
3491         case TC_SETUP_BLOCK: {
3492                 struct flow_block_offload *f = type_data;
3493
3494                 f->unlocked_driver_cb = true;
3495                 return flow_block_cb_setup_simple(type_data,
3496                                                   &mlx5e_block_cb_list,
3497                                                   mlx5e_setup_tc_block_cb,
3498                                                   priv, priv, true);
3499         }
3500         case TC_SETUP_QDISC_MQPRIO:
3501                 return mlx5e_setup_tc_mqprio(priv, type_data);
3502         case TC_SETUP_QDISC_HTB:
3503                 mutex_lock(&priv->state_lock);
3504                 err = mlx5e_setup_tc_htb(priv, type_data);
3505                 mutex_unlock(&priv->state_lock);
3506                 return err;
3507         default:
3508                 return -EOPNOTSUPP;
3509         }
3510 }
3511
3512 void mlx5e_fold_sw_stats64(struct mlx5e_priv *priv, struct rtnl_link_stats64 *s)
3513 {
3514         int i;
3515
3516         for (i = 0; i < priv->max_nch; i++) {
3517                 struct mlx5e_channel_stats *channel_stats = &priv->channel_stats[i];
3518                 struct mlx5e_rq_stats *xskrq_stats = &channel_stats->xskrq;
3519                 struct mlx5e_rq_stats *rq_stats = &channel_stats->rq;
3520                 int j;
3521
3522                 s->rx_packets   += rq_stats->packets + xskrq_stats->packets;
3523                 s->rx_bytes     += rq_stats->bytes + xskrq_stats->bytes;
3524                 s->multicast    += rq_stats->mcast_packets + xskrq_stats->mcast_packets;
3525
3526                 for (j = 0; j < priv->max_opened_tc; j++) {
3527                         struct mlx5e_sq_stats *sq_stats = &channel_stats->sq[j];
3528
3529                         s->tx_packets    += sq_stats->packets;
3530                         s->tx_bytes      += sq_stats->bytes;
3531                         s->tx_dropped    += sq_stats->dropped;
3532                 }
3533         }
3534         if (priv->tx_ptp_opened) {
3535                 for (i = 0; i < priv->max_opened_tc; i++) {
3536                         struct mlx5e_sq_stats *sq_stats = &priv->ptp_stats.sq[i];
3537
3538                         s->tx_packets    += sq_stats->packets;
3539                         s->tx_bytes      += sq_stats->bytes;
3540                         s->tx_dropped    += sq_stats->dropped;
3541                 }
3542         }
3543         if (priv->rx_ptp_opened) {
3544                 struct mlx5e_rq_stats *rq_stats = &priv->ptp_stats.rq;
3545
3546                 s->rx_packets   += rq_stats->packets;
3547                 s->rx_bytes     += rq_stats->bytes;
3548                 s->multicast    += rq_stats->mcast_packets;
3549         }
3550 }
3551
3552 void
3553 mlx5e_get_stats(struct net_device *dev, struct rtnl_link_stats64 *stats)
3554 {
3555         struct mlx5e_priv *priv = netdev_priv(dev);
3556         struct mlx5e_pport_stats *pstats = &priv->stats.pport;
3557
3558         if (!netif_device_present(dev))
3559                 return;
3560
3561         /* In switchdev mode, monitor counters doesn't monitor
3562          * rx/tx stats of 802_3. The update stats mechanism
3563          * should keep the 802_3 layout counters updated
3564          */
3565         if (!mlx5e_monitor_counter_supported(priv) ||
3566             mlx5e_is_uplink_rep(priv)) {
3567                 /* update HW stats in background for next time */
3568                 mlx5e_queue_update_stats(priv);
3569         }
3570
3571         if (mlx5e_is_uplink_rep(priv)) {
3572                 struct mlx5e_vport_stats *vstats = &priv->stats.vport;
3573
3574                 stats->rx_packets = PPORT_802_3_GET(pstats, a_frames_received_ok);
3575                 stats->rx_bytes   = PPORT_802_3_GET(pstats, a_octets_received_ok);
3576                 stats->tx_packets = PPORT_802_3_GET(pstats, a_frames_transmitted_ok);
3577                 stats->tx_bytes   = PPORT_802_3_GET(pstats, a_octets_transmitted_ok);
3578
3579                 /* vport multicast also counts packets that are dropped due to steering
3580                  * or rx out of buffer
3581                  */
3582                 stats->multicast = VPORT_COUNTER_GET(vstats, received_eth_multicast.packets);
3583         } else {
3584                 mlx5e_fold_sw_stats64(priv, stats);
3585         }
3586
3587         stats->rx_dropped = priv->stats.qcnt.rx_out_of_buffer;
3588
3589         stats->rx_length_errors =
3590                 PPORT_802_3_GET(pstats, a_in_range_length_errors) +
3591                 PPORT_802_3_GET(pstats, a_out_of_range_length_field) +
3592                 PPORT_802_3_GET(pstats, a_frame_too_long_errors);
3593         stats->rx_crc_errors =
3594                 PPORT_802_3_GET(pstats, a_frame_check_sequence_errors);
3595         stats->rx_frame_errors = PPORT_802_3_GET(pstats, a_alignment_errors);
3596         stats->tx_aborted_errors = PPORT_2863_GET(pstats, if_out_discards);
3597         stats->rx_errors = stats->rx_length_errors + stats->rx_crc_errors +
3598                            stats->rx_frame_errors;
3599         stats->tx_errors = stats->tx_aborted_errors + stats->tx_carrier_errors;
3600 }
3601
3602 static void mlx5e_nic_set_rx_mode(struct mlx5e_priv *priv)
3603 {
3604         if (mlx5e_is_uplink_rep(priv))
3605                 return; /* no rx mode for uplink rep */
3606
3607         queue_work(priv->wq, &priv->set_rx_mode_work);
3608 }
3609
3610 static void mlx5e_set_rx_mode(struct net_device *dev)
3611 {
3612         struct mlx5e_priv *priv = netdev_priv(dev);
3613
3614         mlx5e_nic_set_rx_mode(priv);
3615 }
3616
3617 static int mlx5e_set_mac(struct net_device *netdev, void *addr)
3618 {
3619         struct mlx5e_priv *priv = netdev_priv(netdev);
3620         struct sockaddr *saddr = addr;
3621
3622         if (!is_valid_ether_addr(saddr->sa_data))
3623                 return -EADDRNOTAVAIL;
3624
3625         netif_addr_lock_bh(netdev);
3626         ether_addr_copy(netdev->dev_addr, saddr->sa_data);
3627         netif_addr_unlock_bh(netdev);
3628
3629         mlx5e_nic_set_rx_mode(priv);
3630
3631         return 0;
3632 }
3633
3634 #define MLX5E_SET_FEATURE(features, feature, enable)    \
3635         do {                                            \
3636                 if (enable)                             \
3637                         *features |= feature;           \
3638                 else                                    \
3639                         *features &= ~feature;          \
3640         } while (0)
3641
3642 typedef int (*mlx5e_feature_handler)(struct net_device *netdev, bool enable);
3643
3644 static int set_feature_lro(struct net_device *netdev, bool enable)
3645 {
3646         struct mlx5e_priv *priv = netdev_priv(netdev);
3647         struct mlx5_core_dev *mdev = priv->mdev;
3648         struct mlx5e_params *cur_params;
3649         struct mlx5e_params new_params;
3650         bool reset = true;
3651         int err = 0;
3652
3653         mutex_lock(&priv->state_lock);
3654
3655         if (enable && priv->xsk.refcnt) {
3656                 netdev_warn(netdev, "LRO is incompatible with AF_XDP (%u XSKs are active)\n",
3657                             priv->xsk.refcnt);
3658                 err = -EINVAL;
3659                 goto out;
3660         }
3661
3662         cur_params = &priv->channels.params;
3663         if (enable && !MLX5E_GET_PFLAG(cur_params, MLX5E_PFLAG_RX_STRIDING_RQ)) {
3664                 netdev_warn(netdev, "can't set LRO with legacy RQ\n");
3665                 err = -EINVAL;
3666                 goto out;
3667         }
3668
3669         new_params = *cur_params;
3670         new_params.lro_en = enable;
3671
3672         if (cur_params->rq_wq_type == MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ) {
3673                 if (mlx5e_rx_mpwqe_is_linear_skb(mdev, cur_params, NULL) ==
3674                     mlx5e_rx_mpwqe_is_linear_skb(mdev, &new_params, NULL))
3675                         reset = false;
3676         }
3677
3678         err = mlx5e_safe_switch_params(priv, &new_params,
3679                                        mlx5e_modify_tirs_lro_ctx, NULL, reset);
3680 out:
3681         mutex_unlock(&priv->state_lock);
3682         return err;
3683 }
3684
3685 static int set_feature_cvlan_filter(struct net_device *netdev, bool enable)
3686 {
3687         struct mlx5e_priv *priv = netdev_priv(netdev);
3688
3689         if (enable)
3690                 mlx5e_enable_cvlan_filter(priv);
3691         else
3692                 mlx5e_disable_cvlan_filter(priv);
3693
3694         return 0;
3695 }
3696
3697 static int set_feature_hw_tc(struct net_device *netdev, bool enable)
3698 {
3699         struct mlx5e_priv *priv = netdev_priv(netdev);
3700
3701 #if IS_ENABLED(CONFIG_MLX5_CLS_ACT)
3702         if (!enable && mlx5e_tc_num_filters(priv, MLX5_TC_FLAG(NIC_OFFLOAD))) {
3703                 netdev_err(netdev,
3704                            "Active offloaded tc filters, can't turn hw_tc_offload off\n");
3705                 return -EINVAL;
3706         }
3707 #endif
3708
3709         if (!enable && priv->htb.maj_id) {
3710                 netdev_err(netdev, "Active HTB offload, can't turn hw_tc_offload off\n");
3711                 return -EINVAL;
3712         }
3713
3714         return 0;
3715 }
3716
3717 static int set_feature_rx_all(struct net_device *netdev, bool enable)
3718 {
3719         struct mlx5e_priv *priv = netdev_priv(netdev);
3720         struct mlx5_core_dev *mdev = priv->mdev;
3721
3722         return mlx5_set_port_fcs(mdev, !enable);
3723 }
3724
3725 static int set_feature_rx_fcs(struct net_device *netdev, bool enable)
3726 {
3727         struct mlx5e_priv *priv = netdev_priv(netdev);
3728         int err;
3729
3730         mutex_lock(&priv->state_lock);
3731
3732         priv->channels.params.scatter_fcs_en = enable;
3733         err = mlx5e_modify_channels_scatter_fcs(&priv->channels, enable);
3734         if (err)
3735                 priv->channels.params.scatter_fcs_en = !enable;
3736
3737         mutex_unlock(&priv->state_lock);
3738
3739         return err;
3740 }
3741
3742 static int set_feature_rx_vlan(struct net_device *netdev, bool enable)
3743 {
3744         struct mlx5e_priv *priv = netdev_priv(netdev);
3745         int err = 0;
3746
3747         mutex_lock(&priv->state_lock);
3748
3749         priv->channels.params.vlan_strip_disable = !enable;
3750         if (!test_bit(MLX5E_STATE_OPENED, &priv->state))
3751                 goto unlock;
3752
3753         err = mlx5e_modify_channels_vsd(&priv->channels, !enable);
3754         if (err)
3755                 priv->channels.params.vlan_strip_disable = enable;
3756
3757 unlock:
3758         mutex_unlock(&priv->state_lock);
3759
3760         return err;
3761 }
3762
3763 #ifdef CONFIG_MLX5_EN_ARFS
3764 static int set_feature_arfs(struct net_device *netdev, bool enable)
3765 {
3766         struct mlx5e_priv *priv = netdev_priv(netdev);
3767         int err;
3768
3769         if (enable)
3770                 err = mlx5e_arfs_enable(priv);
3771         else
3772                 err = mlx5e_arfs_disable(priv);
3773
3774         return err;
3775 }
3776 #endif
3777
3778 static int mlx5e_handle_feature(struct net_device *netdev,
3779                                 netdev_features_t *features,
3780                                 netdev_features_t wanted_features,
3781                                 netdev_features_t feature,
3782                                 mlx5e_feature_handler feature_handler)
3783 {
3784         netdev_features_t changes = wanted_features ^ netdev->features;
3785         bool enable = !!(wanted_features & feature);
3786         int err;
3787
3788         if (!(changes & feature))
3789                 return 0;
3790
3791         err = feature_handler(netdev, enable);
3792         if (err) {
3793                 netdev_err(netdev, "%s feature %pNF failed, err %d\n",
3794                            enable ? "Enable" : "Disable", &feature, err);
3795                 return err;
3796         }
3797
3798         MLX5E_SET_FEATURE(features, feature, enable);
3799         return 0;
3800 }
3801
3802 int mlx5e_set_features(struct net_device *netdev, netdev_features_t features)
3803 {
3804         netdev_features_t oper_features = netdev->features;
3805         int err = 0;
3806
3807 #define MLX5E_HANDLE_FEATURE(feature, handler) \
3808         mlx5e_handle_feature(netdev, &oper_features, features, feature, handler)
3809
3810         err |= MLX5E_HANDLE_FEATURE(NETIF_F_LRO, set_feature_lro);
3811         err |= MLX5E_HANDLE_FEATURE(NETIF_F_HW_VLAN_CTAG_FILTER,
3812                                     set_feature_cvlan_filter);
3813         err |= MLX5E_HANDLE_FEATURE(NETIF_F_HW_TC, set_feature_hw_tc);
3814         err |= MLX5E_HANDLE_FEATURE(NETIF_F_RXALL, set_feature_rx_all);
3815         err |= MLX5E_HANDLE_FEATURE(NETIF_F_RXFCS, set_feature_rx_fcs);
3816         err |= MLX5E_HANDLE_FEATURE(NETIF_F_HW_VLAN_CTAG_RX, set_feature_rx_vlan);
3817 #ifdef CONFIG_MLX5_EN_ARFS
3818         err |= MLX5E_HANDLE_FEATURE(NETIF_F_NTUPLE, set_feature_arfs);
3819 #endif
3820         err |= MLX5E_HANDLE_FEATURE(NETIF_F_HW_TLS_RX, mlx5e_ktls_set_feature_rx);
3821
3822         if (err) {
3823                 netdev->features = oper_features;
3824                 return -EINVAL;
3825         }
3826
3827         return 0;
3828 }
3829
3830 static netdev_features_t mlx5e_fix_features(struct net_device *netdev,
3831                                             netdev_features_t features)
3832 {
3833         struct mlx5e_priv *priv = netdev_priv(netdev);
3834         struct mlx5e_params *params;
3835
3836         mutex_lock(&priv->state_lock);
3837         params = &priv->channels.params;
3838         if (!priv->fs.vlan ||
3839             !bitmap_empty(mlx5e_vlan_get_active_svlans(priv->fs.vlan), VLAN_N_VID)) {
3840                 /* HW strips the outer C-tag header, this is a problem
3841                  * for S-tag traffic.
3842                  */
3843                 features &= ~NETIF_F_HW_VLAN_CTAG_RX;
3844                 if (!params->vlan_strip_disable)
3845                         netdev_warn(netdev, "Dropping C-tag vlan stripping offload due to S-tag vlan\n");
3846         }
3847
3848         if (!MLX5E_GET_PFLAG(params, MLX5E_PFLAG_RX_STRIDING_RQ)) {
3849                 if (features & NETIF_F_LRO) {
3850                         netdev_warn(netdev, "Disabling LRO, not supported in legacy RQ\n");
3851                         features &= ~NETIF_F_LRO;
3852                 }
3853         }
3854
3855         if (MLX5E_GET_PFLAG(params, MLX5E_PFLAG_RX_CQE_COMPRESS)) {
3856                 features &= ~NETIF_F_RXHASH;
3857                 if (netdev->features & NETIF_F_RXHASH)
3858                         netdev_warn(netdev, "Disabling rxhash, not supported when CQE compress is active\n");
3859         }
3860
3861         if (mlx5e_is_uplink_rep(priv)) {
3862                 features &= ~NETIF_F_HW_TLS_RX;
3863                 if (netdev->features & NETIF_F_HW_TLS_RX)
3864                         netdev_warn(netdev, "Disabling hw_tls_rx, not supported in switchdev mode\n");
3865
3866                 features &= ~NETIF_F_HW_TLS_TX;
3867                 if (netdev->features & NETIF_F_HW_TLS_TX)
3868                         netdev_warn(netdev, "Disabling hw_tls_tx, not supported in switchdev mode\n");
3869         }
3870
3871         mutex_unlock(&priv->state_lock);
3872
3873         return features;
3874 }
3875
3876 static bool mlx5e_xsk_validate_mtu(struct net_device *netdev,
3877                                    struct mlx5e_channels *chs,
3878                                    struct mlx5e_params *new_params,
3879                                    struct mlx5_core_dev *mdev)
3880 {
3881         u16 ix;
3882
3883         for (ix = 0; ix < chs->params.num_channels; ix++) {
3884                 struct xsk_buff_pool *xsk_pool =
3885                         mlx5e_xsk_get_pool(&chs->params, chs->params.xsk, ix);
3886                 struct mlx5e_xsk_param xsk;
3887
3888                 if (!xsk_pool)
3889                         continue;
3890
3891                 mlx5e_build_xsk_param(xsk_pool, &xsk);
3892
3893                 if (!mlx5e_validate_xsk_param(new_params, &xsk, mdev)) {
3894                         u32 hr = mlx5e_get_linear_rq_headroom(new_params, &xsk);
3895                         int max_mtu_frame, max_mtu_page, max_mtu;
3896
3897                         /* Two criteria must be met:
3898                          * 1. HW MTU + all headrooms <= XSK frame size.
3899                          * 2. Size of SKBs allocated on XDP_PASS <= PAGE_SIZE.
3900                          */
3901                         max_mtu_frame = MLX5E_HW2SW_MTU(new_params, xsk.chunk_size - hr);
3902                         max_mtu_page = mlx5e_xdp_max_mtu(new_params, &xsk);
3903                         max_mtu = min(max_mtu_frame, max_mtu_page);
3904
3905                         netdev_err(netdev, "MTU %d is too big for an XSK running on channel %u. Try MTU <= %d\n",
3906                                    new_params->sw_mtu, ix, max_mtu);
3907                         return false;
3908                 }
3909         }
3910
3911         return true;
3912 }
3913
3914 int mlx5e_change_mtu(struct net_device *netdev, int new_mtu,
3915                      mlx5e_fp_preactivate preactivate)
3916 {
3917         struct mlx5e_priv *priv = netdev_priv(netdev);
3918         struct mlx5e_params new_params;
3919         struct mlx5e_params *params;
3920         bool reset = true;
3921         int err = 0;
3922
3923         mutex_lock(&priv->state_lock);
3924
3925         params = &priv->channels.params;
3926
3927         new_params = *params;
3928         new_params.sw_mtu = new_mtu;
3929         err = mlx5e_validate_params(priv->mdev, &new_params);
3930         if (err)
3931                 goto out;
3932
3933         if (params->xdp_prog &&
3934             !mlx5e_rx_is_linear_skb(&new_params, NULL)) {
3935                 netdev_err(netdev, "MTU(%d) > %d is not allowed while XDP enabled\n",
3936                            new_mtu, mlx5e_xdp_max_mtu(params, NULL));
3937                 err = -EINVAL;
3938                 goto out;
3939         }
3940
3941         if (priv->xsk.refcnt &&
3942             !mlx5e_xsk_validate_mtu(netdev, &priv->channels,
3943                                     &new_params, priv->mdev)) {
3944                 err = -EINVAL;
3945                 goto out;
3946         }
3947
3948         if (params->lro_en)
3949                 reset = false;
3950
3951         if (params->rq_wq_type == MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ) {
3952                 bool is_linear_old = mlx5e_rx_mpwqe_is_linear_skb(priv->mdev, params, NULL);
3953                 bool is_linear_new = mlx5e_rx_mpwqe_is_linear_skb(priv->mdev,
3954                                                                   &new_params, NULL);
3955                 u8 ppw_old = mlx5e_mpwqe_log_pkts_per_wqe(params, NULL);
3956                 u8 ppw_new = mlx5e_mpwqe_log_pkts_per_wqe(&new_params, NULL);
3957
3958                 /* Always reset in linear mode - hw_mtu is used in data path.
3959                  * Check that the mode was non-linear and didn't change.
3960                  * If XSK is active, XSK RQs are linear.
3961                  */
3962                 if (!is_linear_old && !is_linear_new && !priv->xsk.refcnt &&
3963                     ppw_old == ppw_new)
3964                         reset = false;
3965         }
3966
3967         err = mlx5e_safe_switch_params(priv, &new_params, preactivate, NULL, reset);
3968
3969 out:
3970         netdev->mtu = params->sw_mtu;
3971         mutex_unlock(&priv->state_lock);
3972         return err;
3973 }
3974
3975 static int mlx5e_change_nic_mtu(struct net_device *netdev, int new_mtu)
3976 {
3977         return mlx5e_change_mtu(netdev, new_mtu, mlx5e_set_dev_port_mtu_ctx);
3978 }
3979
3980 int mlx5e_ptp_rx_manage_fs_ctx(struct mlx5e_priv *priv, void *ctx)
3981 {
3982         bool set  = *(bool *)ctx;
3983
3984         return mlx5e_ptp_rx_manage_fs(priv, set);
3985 }
3986
3987 static int mlx5e_hwstamp_config_no_ptp_rx(struct mlx5e_priv *priv, bool rx_filter)
3988 {
3989         bool rx_cqe_compress_def = priv->channels.params.rx_cqe_compress_def;
3990         int err;
3991
3992         if (!rx_filter)
3993                 /* Reset CQE compression to Admin default */
3994                 return mlx5e_modify_rx_cqe_compression_locked(priv, rx_cqe_compress_def);
3995
3996         if (!MLX5E_GET_PFLAG(&priv->channels.params, MLX5E_PFLAG_RX_CQE_COMPRESS))
3997                 return 0;
3998
3999         /* Disable CQE compression */
4000         netdev_warn(priv->netdev, "Disabling RX cqe compression\n");
4001         err = mlx5e_modify_rx_cqe_compression_locked(priv, false);
4002         if (err)
4003                 netdev_err(priv->netdev, "Failed disabling cqe compression err=%d\n", err);
4004
4005         return err;
4006 }
4007
4008 static int mlx5e_hwstamp_config_ptp_rx(struct mlx5e_priv *priv, bool ptp_rx)
4009 {
4010         struct mlx5e_params new_params;
4011
4012         if (ptp_rx == priv->channels.params.ptp_rx)
4013                 return 0;
4014
4015         new_params = priv->channels.params;
4016         new_params.ptp_rx = ptp_rx;
4017         return mlx5e_safe_switch_params(priv, &new_params, mlx5e_ptp_rx_manage_fs_ctx,
4018                                         &new_params.ptp_rx, true);
4019 }
4020
4021 int mlx5e_hwstamp_set(struct mlx5e_priv *priv, struct ifreq *ifr)
4022 {
4023         struct hwtstamp_config config;
4024         bool rx_cqe_compress_def;
4025         bool ptp_rx;
4026         int err;
4027
4028         if (!MLX5_CAP_GEN(priv->mdev, device_frequency_khz) ||
4029             (mlx5_clock_get_ptp_index(priv->mdev) == -1))
4030                 return -EOPNOTSUPP;
4031
4032         if (copy_from_user(&config, ifr->ifr_data, sizeof(config)))
4033                 return -EFAULT;
4034
4035         /* TX HW timestamp */
4036         switch (config.tx_type) {
4037         case HWTSTAMP_TX_OFF:
4038         case HWTSTAMP_TX_ON:
4039                 break;
4040         default:
4041                 return -ERANGE;
4042         }
4043
4044         mutex_lock(&priv->state_lock);
4045         rx_cqe_compress_def = priv->channels.params.rx_cqe_compress_def;
4046
4047         /* RX HW timestamp */
4048         switch (config.rx_filter) {
4049         case HWTSTAMP_FILTER_NONE:
4050                 ptp_rx = false;
4051                 break;
4052         case HWTSTAMP_FILTER_ALL:
4053         case HWTSTAMP_FILTER_SOME:
4054         case HWTSTAMP_FILTER_PTP_V1_L4_EVENT:
4055         case HWTSTAMP_FILTER_PTP_V1_L4_SYNC:
4056         case HWTSTAMP_FILTER_PTP_V1_L4_DELAY_REQ:
4057         case HWTSTAMP_FILTER_PTP_V2_L4_EVENT:
4058         case HWTSTAMP_FILTER_PTP_V2_L4_SYNC:
4059         case HWTSTAMP_FILTER_PTP_V2_L4_DELAY_REQ:
4060         case HWTSTAMP_FILTER_PTP_V2_L2_EVENT:
4061         case HWTSTAMP_FILTER_PTP_V2_L2_SYNC:
4062         case HWTSTAMP_FILTER_PTP_V2_L2_DELAY_REQ:
4063         case HWTSTAMP_FILTER_PTP_V2_EVENT:
4064         case HWTSTAMP_FILTER_PTP_V2_SYNC:
4065         case HWTSTAMP_FILTER_PTP_V2_DELAY_REQ:
4066         case HWTSTAMP_FILTER_NTP_ALL:
4067                 config.rx_filter = HWTSTAMP_FILTER_ALL;
4068                 /* ptp_rx is set if both HW TS is set and CQE
4069                  * compression is set
4070                  */
4071                 ptp_rx = rx_cqe_compress_def;
4072                 break;
4073         default:
4074                 err = -ERANGE;
4075                 goto err_unlock;
4076         }
4077
4078         if (!priv->profile->rx_ptp_support)
4079                 err = mlx5e_hwstamp_config_no_ptp_rx(priv,
4080                                                      config.rx_filter != HWTSTAMP_FILTER_NONE);
4081         else
4082                 err = mlx5e_hwstamp_config_ptp_rx(priv, ptp_rx);
4083         if (err)
4084                 goto err_unlock;
4085
4086         memcpy(&priv->tstamp, &config, sizeof(config));
4087         mutex_unlock(&priv->state_lock);
4088
4089         /* might need to fix some features */
4090         netdev_update_features(priv->netdev);
4091
4092         return copy_to_user(ifr->ifr_data, &config,
4093                             sizeof(config)) ? -EFAULT : 0;
4094 err_unlock:
4095         mutex_unlock(&priv->state_lock);
4096         return err;
4097 }
4098
4099 int mlx5e_hwstamp_get(struct mlx5e_priv *priv, struct ifreq *ifr)
4100 {
4101         struct hwtstamp_config *cfg = &priv->tstamp;
4102
4103         if (!MLX5_CAP_GEN(priv->mdev, device_frequency_khz))
4104                 return -EOPNOTSUPP;
4105
4106         return copy_to_user(ifr->ifr_data, cfg, sizeof(*cfg)) ? -EFAULT : 0;
4107 }
4108
4109 static int mlx5e_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
4110 {
4111         struct mlx5e_priv *priv = netdev_priv(dev);
4112
4113         switch (cmd) {
4114         case SIOCSHWTSTAMP:
4115                 return mlx5e_hwstamp_set(priv, ifr);
4116         case SIOCGHWTSTAMP:
4117                 return mlx5e_hwstamp_get(priv, ifr);
4118         default:
4119                 return -EOPNOTSUPP;
4120         }
4121 }
4122
4123 #ifdef CONFIG_MLX5_ESWITCH
4124 int mlx5e_set_vf_mac(struct net_device *dev, int vf, u8 *mac)
4125 {
4126         struct mlx5e_priv *priv = netdev_priv(dev);
4127         struct mlx5_core_dev *mdev = priv->mdev;
4128
4129         return mlx5_eswitch_set_vport_mac(mdev->priv.eswitch, vf + 1, mac);
4130 }
4131
4132 static int mlx5e_set_vf_vlan(struct net_device *dev, int vf, u16 vlan, u8 qos,
4133                              __be16 vlan_proto)
4134 {
4135         struct mlx5e_priv *priv = netdev_priv(dev);
4136         struct mlx5_core_dev *mdev = priv->mdev;
4137
4138         if (vlan_proto != htons(ETH_P_8021Q))
4139                 return -EPROTONOSUPPORT;
4140
4141         return mlx5_eswitch_set_vport_vlan(mdev->priv.eswitch, vf + 1,
4142                                            vlan, qos);
4143 }
4144
4145 static int mlx5e_set_vf_spoofchk(struct net_device *dev, int vf, bool setting)
4146 {
4147         struct mlx5e_priv *priv = netdev_priv(dev);
4148         struct mlx5_core_dev *mdev = priv->mdev;
4149
4150         return mlx5_eswitch_set_vport_spoofchk(mdev->priv.eswitch, vf + 1, setting);
4151 }
4152
4153 static int mlx5e_set_vf_trust(struct net_device *dev, int vf, bool setting)
4154 {
4155         struct mlx5e_priv *priv = netdev_priv(dev);
4156         struct mlx5_core_dev *mdev = priv->mdev;
4157
4158         return mlx5_eswitch_set_vport_trust(mdev->priv.eswitch, vf + 1, setting);
4159 }
4160
4161 int mlx5e_set_vf_rate(struct net_device *dev, int vf, int min_tx_rate,
4162                       int max_tx_rate)
4163 {
4164         struct mlx5e_priv *priv = netdev_priv(dev);
4165         struct mlx5_core_dev *mdev = priv->mdev;
4166
4167         return mlx5_eswitch_set_vport_rate(mdev->priv.eswitch, vf + 1,
4168                                            max_tx_rate, min_tx_rate);
4169 }
4170
4171 static int mlx5_vport_link2ifla(u8 esw_link)
4172 {
4173         switch (esw_link) {
4174         case MLX5_VPORT_ADMIN_STATE_DOWN:
4175                 return IFLA_VF_LINK_STATE_DISABLE;
4176         case MLX5_VPORT_ADMIN_STATE_UP:
4177                 return IFLA_VF_LINK_STATE_ENABLE;
4178         }
4179         return IFLA_VF_LINK_STATE_AUTO;
4180 }
4181
4182 static int mlx5_ifla_link2vport(u8 ifla_link)
4183 {
4184         switch (ifla_link) {
4185         case IFLA_VF_LINK_STATE_DISABLE:
4186                 return MLX5_VPORT_ADMIN_STATE_DOWN;
4187         case IFLA_VF_LINK_STATE_ENABLE:
4188                 return MLX5_VPORT_ADMIN_STATE_UP;
4189         }
4190         return MLX5_VPORT_ADMIN_STATE_AUTO;
4191 }
4192
4193 static int mlx5e_set_vf_link_state(struct net_device *dev, int vf,
4194                                    int link_state)
4195 {
4196         struct mlx5e_priv *priv = netdev_priv(dev);
4197         struct mlx5_core_dev *mdev = priv->mdev;
4198
4199         if (mlx5e_is_uplink_rep(priv))
4200                 return -EOPNOTSUPP;
4201
4202         return mlx5_eswitch_set_vport_state(mdev->priv.eswitch, vf + 1,
4203                                             mlx5_ifla_link2vport(link_state));
4204 }
4205
4206 int mlx5e_get_vf_config(struct net_device *dev,
4207                         int vf, struct ifla_vf_info *ivi)
4208 {
4209         struct mlx5e_priv *priv = netdev_priv(dev);
4210         struct mlx5_core_dev *mdev = priv->mdev;
4211         int err;
4212
4213         if (!netif_device_present(dev))
4214                 return -EOPNOTSUPP;
4215
4216         err = mlx5_eswitch_get_vport_config(mdev->priv.eswitch, vf + 1, ivi);
4217         if (err)
4218                 return err;
4219         ivi->linkstate = mlx5_vport_link2ifla(ivi->linkstate);
4220         return 0;
4221 }
4222
4223 int mlx5e_get_vf_stats(struct net_device *dev,
4224                        int vf, struct ifla_vf_stats *vf_stats)
4225 {
4226         struct mlx5e_priv *priv = netdev_priv(dev);
4227         struct mlx5_core_dev *mdev = priv->mdev;
4228
4229         return mlx5_eswitch_get_vport_stats(mdev->priv.eswitch, vf + 1,
4230                                             vf_stats);
4231 }
4232
4233 static bool
4234 mlx5e_has_offload_stats(const struct net_device *dev, int attr_id)
4235 {
4236         struct mlx5e_priv *priv = netdev_priv(dev);
4237
4238         if (!netif_device_present(dev))
4239                 return false;
4240
4241         if (!mlx5e_is_uplink_rep(priv))
4242                 return false;
4243
4244         return mlx5e_rep_has_offload_stats(dev, attr_id);
4245 }
4246
4247 static int
4248 mlx5e_get_offload_stats(int attr_id, const struct net_device *dev,
4249                         void *sp)
4250 {
4251         struct mlx5e_priv *priv = netdev_priv(dev);
4252
4253         if (!mlx5e_is_uplink_rep(priv))
4254                 return -EOPNOTSUPP;
4255
4256         return mlx5e_rep_get_offload_stats(attr_id, dev, sp);
4257 }
4258 #endif
4259
4260 static bool mlx5e_tunnel_proto_supported_tx(struct mlx5_core_dev *mdev, u8 proto_type)
4261 {
4262         switch (proto_type) {
4263         case IPPROTO_GRE:
4264                 return MLX5_CAP_ETH(mdev, tunnel_stateless_gre);
4265         case IPPROTO_IPIP:
4266         case IPPROTO_IPV6:
4267                 return (MLX5_CAP_ETH(mdev, tunnel_stateless_ip_over_ip) ||
4268                         MLX5_CAP_ETH(mdev, tunnel_stateless_ip_over_ip_tx));
4269         default:
4270                 return false;
4271         }
4272 }
4273
4274 static bool mlx5e_gre_tunnel_inner_proto_offload_supported(struct mlx5_core_dev *mdev,
4275                                                            struct sk_buff *skb)
4276 {
4277         switch (skb->inner_protocol) {
4278         case htons(ETH_P_IP):
4279         case htons(ETH_P_IPV6):
4280         case htons(ETH_P_TEB):
4281                 return true;
4282         case htons(ETH_P_MPLS_UC):
4283         case htons(ETH_P_MPLS_MC):
4284                 return MLX5_CAP_ETH(mdev, tunnel_stateless_mpls_over_gre);
4285         }
4286         return false;
4287 }
4288
4289 static netdev_features_t mlx5e_tunnel_features_check(struct mlx5e_priv *priv,
4290                                                      struct sk_buff *skb,
4291                                                      netdev_features_t features)
4292 {
4293         unsigned int offset = 0;
4294         struct udphdr *udph;
4295         u8 proto;
4296         u16 port;
4297
4298         switch (vlan_get_protocol(skb)) {
4299         case htons(ETH_P_IP):
4300                 proto = ip_hdr(skb)->protocol;
4301                 break;
4302         case htons(ETH_P_IPV6):
4303                 proto = ipv6_find_hdr(skb, &offset, -1, NULL, NULL);
4304                 break;
4305         default:
4306                 goto out;
4307         }
4308
4309         switch (proto) {
4310         case IPPROTO_GRE:
4311                 if (mlx5e_gre_tunnel_inner_proto_offload_supported(priv->mdev, skb))
4312                         return features;
4313                 break;
4314         case IPPROTO_IPIP:
4315         case IPPROTO_IPV6:
4316                 if (mlx5e_tunnel_proto_supported_tx(priv->mdev, IPPROTO_IPIP))
4317                         return features;
4318                 break;
4319         case IPPROTO_UDP:
4320                 udph = udp_hdr(skb);
4321                 port = be16_to_cpu(udph->dest);
4322
4323                 /* Verify if UDP port is being offloaded by HW */
4324                 if (mlx5_vxlan_lookup_port(priv->mdev->vxlan, port))
4325                         return features;
4326
4327 #if IS_ENABLED(CONFIG_GENEVE)
4328                 /* Support Geneve offload for default UDP port */
4329                 if (port == GENEVE_UDP_PORT && mlx5_geneve_tx_allowed(priv->mdev))
4330                         return features;
4331 #endif
4332         }
4333
4334 out:
4335         /* Disable CSUM and GSO if the udp dport is not offloaded by HW */
4336         return features & ~(NETIF_F_CSUM_MASK | NETIF_F_GSO_MASK);
4337 }
4338
4339 netdev_features_t mlx5e_features_check(struct sk_buff *skb,
4340                                        struct net_device *netdev,
4341                                        netdev_features_t features)
4342 {
4343         struct mlx5e_priv *priv = netdev_priv(netdev);
4344
4345         features = vlan_features_check(skb, features);
4346         features = vxlan_features_check(skb, features);
4347
4348         if (mlx5e_ipsec_feature_check(skb, netdev, features))
4349                 return features;
4350
4351         /* Validate if the tunneled packet is being offloaded by HW */
4352         if (skb->encapsulation &&
4353             (features & NETIF_F_CSUM_MASK || features & NETIF_F_GSO_MASK))
4354                 return mlx5e_tunnel_features_check(priv, skb, features);
4355
4356         return features;
4357 }
4358
4359 static void mlx5e_tx_timeout_work(struct work_struct *work)
4360 {
4361         struct mlx5e_priv *priv = container_of(work, struct mlx5e_priv,
4362                                                tx_timeout_work);
4363         struct net_device *netdev = priv->netdev;
4364         int i;
4365
4366         rtnl_lock();
4367         mutex_lock(&priv->state_lock);
4368
4369         if (!test_bit(MLX5E_STATE_OPENED, &priv->state))
4370                 goto unlock;
4371
4372         for (i = 0; i < netdev->real_num_tx_queues; i++) {
4373                 struct netdev_queue *dev_queue =
4374                         netdev_get_tx_queue(netdev, i);
4375                 struct mlx5e_txqsq *sq = priv->txq2sq[i];
4376
4377                 if (!netif_xmit_stopped(dev_queue))
4378                         continue;
4379
4380                 if (mlx5e_reporter_tx_timeout(sq))
4381                 /* break if tried to reopened channels */
4382                         break;
4383         }
4384
4385 unlock:
4386         mutex_unlock(&priv->state_lock);
4387         rtnl_unlock();
4388 }
4389
4390 static void mlx5e_tx_timeout(struct net_device *dev, unsigned int txqueue)
4391 {
4392         struct mlx5e_priv *priv = netdev_priv(dev);
4393
4394         netdev_err(dev, "TX timeout detected\n");
4395         queue_work(priv->wq, &priv->tx_timeout_work);
4396 }
4397
4398 static int mlx5e_xdp_allowed(struct mlx5e_priv *priv, struct bpf_prog *prog)
4399 {
4400         struct net_device *netdev = priv->netdev;
4401         struct mlx5e_params new_params;
4402
4403         if (priv->channels.params.lro_en) {
4404                 netdev_warn(netdev, "can't set XDP while LRO is on, disable LRO first\n");
4405                 return -EINVAL;
4406         }
4407
4408         if (mlx5_fpga_is_ipsec_device(priv->mdev)) {
4409                 netdev_warn(netdev,
4410                             "XDP is not available on Innova cards with IPsec support\n");
4411                 return -EINVAL;
4412         }
4413
4414         new_params = priv->channels.params;
4415         new_params.xdp_prog = prog;
4416
4417         /* No XSK params: AF_XDP can't be enabled yet at the point of setting
4418          * the XDP program.
4419          */
4420         if (!mlx5e_rx_is_linear_skb(&new_params, NULL)) {
4421                 netdev_warn(netdev, "XDP is not allowed with MTU(%d) > %d\n",
4422                             new_params.sw_mtu,
4423                             mlx5e_xdp_max_mtu(&new_params, NULL));
4424                 return -EINVAL;
4425         }
4426
4427         return 0;
4428 }
4429
4430 static void mlx5e_rq_replace_xdp_prog(struct mlx5e_rq *rq, struct bpf_prog *prog)
4431 {
4432         struct bpf_prog *old_prog;
4433
4434         old_prog = rcu_replace_pointer(rq->xdp_prog, prog,
4435                                        lockdep_is_held(&rq->priv->state_lock));
4436         if (old_prog)
4437                 bpf_prog_put(old_prog);
4438 }
4439
4440 static int mlx5e_xdp_set(struct net_device *netdev, struct bpf_prog *prog)
4441 {
4442         struct mlx5e_priv *priv = netdev_priv(netdev);
4443         struct mlx5e_params new_params;
4444         struct bpf_prog *old_prog;
4445         int err = 0;
4446         bool reset;
4447         int i;
4448
4449         mutex_lock(&priv->state_lock);
4450
4451         if (prog) {
4452                 err = mlx5e_xdp_allowed(priv, prog);
4453                 if (err)
4454                         goto unlock;
4455         }
4456
4457         /* no need for full reset when exchanging programs */
4458         reset = (!priv->channels.params.xdp_prog || !prog);
4459
4460         new_params = priv->channels.params;
4461         new_params.xdp_prog = prog;
4462         if (reset)
4463                 mlx5e_set_rq_type(priv->mdev, &new_params);
4464         old_prog = priv->channels.params.xdp_prog;
4465
4466         err = mlx5e_safe_switch_params(priv, &new_params, NULL, NULL, reset);
4467         if (err)
4468                 goto unlock;
4469
4470         if (old_prog)
4471                 bpf_prog_put(old_prog);
4472
4473         if (!test_bit(MLX5E_STATE_OPENED, &priv->state) || reset)
4474                 goto unlock;
4475
4476         /* exchanging programs w/o reset, we update ref counts on behalf
4477          * of the channels RQs here.
4478          */
4479         bpf_prog_add(prog, priv->channels.num);
4480         for (i = 0; i < priv->channels.num; i++) {
4481                 struct mlx5e_channel *c = priv->channels.c[i];
4482
4483                 mlx5e_rq_replace_xdp_prog(&c->rq, prog);
4484                 if (test_bit(MLX5E_CHANNEL_STATE_XSK, c->state)) {
4485                         bpf_prog_inc(prog);
4486                         mlx5e_rq_replace_xdp_prog(&c->xskrq, prog);
4487                 }
4488         }
4489
4490 unlock:
4491         mutex_unlock(&priv->state_lock);
4492         return err;
4493 }
4494
4495 static int mlx5e_xdp(struct net_device *dev, struct netdev_bpf *xdp)
4496 {
4497         switch (xdp->command) {
4498         case XDP_SETUP_PROG:
4499                 return mlx5e_xdp_set(dev, xdp->prog);
4500         case XDP_SETUP_XSK_POOL:
4501                 return mlx5e_xsk_setup_pool(dev, xdp->xsk.pool,
4502                                             xdp->xsk.queue_id);
4503         default:
4504                 return -EINVAL;
4505         }
4506 }
4507
4508 #ifdef CONFIG_MLX5_ESWITCH
4509 static int mlx5e_bridge_getlink(struct sk_buff *skb, u32 pid, u32 seq,
4510                                 struct net_device *dev, u32 filter_mask,
4511                                 int nlflags)
4512 {
4513         struct mlx5e_priv *priv = netdev_priv(dev);
4514         struct mlx5_core_dev *mdev = priv->mdev;
4515         u8 mode, setting;
4516         int err;
4517
4518         err = mlx5_eswitch_get_vepa(mdev->priv.eswitch, &setting);
4519         if (err)
4520                 return err;
4521         mode = setting ? BRIDGE_MODE_VEPA : BRIDGE_MODE_VEB;
4522         return ndo_dflt_bridge_getlink(skb, pid, seq, dev,
4523                                        mode,
4524                                        0, 0, nlflags, filter_mask, NULL);
4525 }
4526
4527 static int mlx5e_bridge_setlink(struct net_device *dev, struct nlmsghdr *nlh,
4528                                 u16 flags, struct netlink_ext_ack *extack)
4529 {
4530         struct mlx5e_priv *priv = netdev_priv(dev);
4531         struct mlx5_core_dev *mdev = priv->mdev;
4532         struct nlattr *attr, *br_spec;
4533         u16 mode = BRIDGE_MODE_UNDEF;
4534         u8 setting;
4535         int rem;
4536
4537         br_spec = nlmsg_find_attr(nlh, sizeof(struct ifinfomsg), IFLA_AF_SPEC);
4538         if (!br_spec)
4539                 return -EINVAL;
4540
4541         nla_for_each_nested(attr, br_spec, rem) {
4542                 if (nla_type(attr) != IFLA_BRIDGE_MODE)
4543                         continue;
4544
4545                 if (nla_len(attr) < sizeof(mode))
4546                         return -EINVAL;
4547
4548                 mode = nla_get_u16(attr);
4549                 if (mode > BRIDGE_MODE_VEPA)
4550                         return -EINVAL;
4551
4552                 break;
4553         }
4554
4555         if (mode == BRIDGE_MODE_UNDEF)
4556                 return -EINVAL;
4557
4558         setting = (mode == BRIDGE_MODE_VEPA) ?  1 : 0;
4559         return mlx5_eswitch_set_vepa(mdev->priv.eswitch, setting);
4560 }
4561 #endif
4562
4563 const struct net_device_ops mlx5e_netdev_ops = {
4564         .ndo_open                = mlx5e_open,
4565         .ndo_stop                = mlx5e_close,
4566         .ndo_start_xmit          = mlx5e_xmit,
4567         .ndo_setup_tc            = mlx5e_setup_tc,
4568         .ndo_select_queue        = mlx5e_select_queue,
4569         .ndo_get_stats64         = mlx5e_get_stats,
4570         .ndo_set_rx_mode         = mlx5e_set_rx_mode,
4571         .ndo_set_mac_address     = mlx5e_set_mac,
4572         .ndo_vlan_rx_add_vid     = mlx5e_vlan_rx_add_vid,
4573         .ndo_vlan_rx_kill_vid    = mlx5e_vlan_rx_kill_vid,
4574         .ndo_set_features        = mlx5e_set_features,
4575         .ndo_fix_features        = mlx5e_fix_features,
4576         .ndo_change_mtu          = mlx5e_change_nic_mtu,
4577         .ndo_do_ioctl            = mlx5e_ioctl,
4578         .ndo_set_tx_maxrate      = mlx5e_set_tx_maxrate,
4579         .ndo_features_check      = mlx5e_features_check,
4580         .ndo_tx_timeout          = mlx5e_tx_timeout,
4581         .ndo_bpf                 = mlx5e_xdp,
4582         .ndo_xdp_xmit            = mlx5e_xdp_xmit,
4583         .ndo_xsk_wakeup          = mlx5e_xsk_wakeup,
4584 #ifdef CONFIG_MLX5_EN_ARFS
4585         .ndo_rx_flow_steer       = mlx5e_rx_flow_steer,
4586 #endif
4587 #ifdef CONFIG_MLX5_ESWITCH
4588         .ndo_bridge_setlink      = mlx5e_bridge_setlink,
4589         .ndo_bridge_getlink      = mlx5e_bridge_getlink,
4590
4591         /* SRIOV E-Switch NDOs */
4592         .ndo_set_vf_mac          = mlx5e_set_vf_mac,
4593         .ndo_set_vf_vlan         = mlx5e_set_vf_vlan,
4594         .ndo_set_vf_spoofchk     = mlx5e_set_vf_spoofchk,
4595         .ndo_set_vf_trust        = mlx5e_set_vf_trust,
4596         .ndo_set_vf_rate         = mlx5e_set_vf_rate,
4597         .ndo_get_vf_config       = mlx5e_get_vf_config,
4598         .ndo_set_vf_link_state   = mlx5e_set_vf_link_state,
4599         .ndo_get_vf_stats        = mlx5e_get_vf_stats,
4600         .ndo_has_offload_stats   = mlx5e_has_offload_stats,
4601         .ndo_get_offload_stats   = mlx5e_get_offload_stats,
4602 #endif
4603         .ndo_get_devlink_port    = mlx5e_get_devlink_port,
4604 };
4605
4606 void mlx5e_build_default_indir_rqt(u32 *indirection_rqt, int len,
4607                                    int num_channels)
4608 {
4609         int i;
4610
4611         for (i = 0; i < len; i++)
4612                 indirection_rqt[i] = i % num_channels;
4613 }
4614
4615 static u32 mlx5e_choose_lro_timeout(struct mlx5_core_dev *mdev, u32 wanted_timeout)
4616 {
4617         int i;
4618
4619         /* The supported periods are organized in ascending order */
4620         for (i = 0; i < MLX5E_LRO_TIMEOUT_ARR_SIZE - 1; i++)
4621                 if (MLX5_CAP_ETH(mdev, lro_timer_supported_periods[i]) >= wanted_timeout)
4622                         break;
4623
4624         return MLX5_CAP_ETH(mdev, lro_timer_supported_periods[i]);
4625 }
4626
4627 void mlx5e_build_rss_params(struct mlx5e_rss_params *rss_params,
4628                             u16 num_channels)
4629 {
4630         enum mlx5e_traffic_types tt;
4631
4632         rss_params->hfunc = ETH_RSS_HASH_TOP;
4633         netdev_rss_key_fill(rss_params->toeplitz_hash_key,
4634                             sizeof(rss_params->toeplitz_hash_key));
4635         mlx5e_build_default_indir_rqt(rss_params->indirection_rqt,
4636                                       MLX5E_INDIR_RQT_SIZE, num_channels);
4637         for (tt = 0; tt < MLX5E_NUM_INDIR_TIRS; tt++)
4638                 rss_params->rx_hash_fields[tt] =
4639                         tirc_default_config[tt].rx_hash_fields;
4640 }
4641
4642 void mlx5e_build_nic_params(struct mlx5e_priv *priv, struct mlx5e_xsk *xsk, u16 mtu)
4643 {
4644         struct mlx5e_rss_params *rss_params = &priv->rss_params;
4645         struct mlx5e_params *params = &priv->channels.params;
4646         struct mlx5_core_dev *mdev = priv->mdev;
4647         u8 rx_cq_period_mode;
4648
4649         priv->max_nch = mlx5e_calc_max_nch(priv, priv->profile);
4650
4651         params->sw_mtu = mtu;
4652         params->hard_mtu = MLX5E_ETH_HARD_MTU;
4653         params->num_channels = min_t(unsigned int, MLX5E_MAX_NUM_CHANNELS / 2,
4654                                      priv->max_nch);
4655         params->num_tc       = 1;
4656
4657         /* Set an initial non-zero value, so that mlx5e_select_queue won't
4658          * divide by zero if called before first activating channels.
4659          */
4660         priv->num_tc_x_num_ch = params->num_channels * params->num_tc;
4661
4662         /* SQ */
4663         params->log_sq_size = is_kdump_kernel() ?
4664                 MLX5E_PARAMS_MINIMUM_LOG_SQ_SIZE :
4665                 MLX5E_PARAMS_DEFAULT_LOG_SQ_SIZE;
4666         MLX5E_SET_PFLAG(params, MLX5E_PFLAG_SKB_TX_MPWQE,
4667                         MLX5_CAP_ETH(mdev, enhanced_multi_pkt_send_wqe));
4668
4669         /* XDP SQ */
4670         MLX5E_SET_PFLAG(params, MLX5E_PFLAG_XDP_TX_MPWQE,
4671                         MLX5_CAP_ETH(mdev, enhanced_multi_pkt_send_wqe));
4672
4673         /* set CQE compression */
4674         params->rx_cqe_compress_def = false;
4675         if (MLX5_CAP_GEN(mdev, cqe_compression) &&
4676             MLX5_CAP_GEN(mdev, vport_group_manager))
4677                 params->rx_cqe_compress_def = slow_pci_heuristic(mdev);
4678
4679         MLX5E_SET_PFLAG(params, MLX5E_PFLAG_RX_CQE_COMPRESS, params->rx_cqe_compress_def);
4680         MLX5E_SET_PFLAG(params, MLX5E_PFLAG_RX_NO_CSUM_COMPLETE, false);
4681
4682         /* RQ */
4683         mlx5e_build_rq_params(mdev, params);
4684
4685         /* HW LRO */
4686         if (MLX5_CAP_ETH(mdev, lro_cap) &&
4687             params->rq_wq_type == MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ) {
4688                 /* No XSK params: checking the availability of striding RQ in general. */
4689                 if (!mlx5e_rx_mpwqe_is_linear_skb(mdev, params, NULL))
4690                         params->lro_en = !slow_pci_heuristic(mdev);
4691         }
4692         params->lro_timeout = mlx5e_choose_lro_timeout(mdev, MLX5E_DEFAULT_LRO_TIMEOUT);
4693
4694         /* CQ moderation params */
4695         rx_cq_period_mode = MLX5_CAP_GEN(mdev, cq_period_start_from_cqe) ?
4696                         MLX5_CQ_PERIOD_MODE_START_FROM_CQE :
4697                         MLX5_CQ_PERIOD_MODE_START_FROM_EQE;
4698         params->rx_dim_enabled = MLX5_CAP_GEN(mdev, cq_moderation);
4699         params->tx_dim_enabled = MLX5_CAP_GEN(mdev, cq_moderation);
4700         mlx5e_set_rx_cq_mode_params(params, rx_cq_period_mode);
4701         mlx5e_set_tx_cq_mode_params(params, MLX5_CQ_PERIOD_MODE_START_FROM_EQE);
4702
4703         /* TX inline */
4704         mlx5_query_min_inline(mdev, &params->tx_min_inline_mode);
4705
4706         /* RSS */
4707         mlx5e_build_rss_params(rss_params, params->num_channels);
4708         params->tunneled_offload_en =
4709                 mlx5e_tunnel_inner_ft_supported(mdev);
4710
4711         /* AF_XDP */
4712         params->xsk = xsk;
4713
4714         /* Do not update netdev->features directly in here
4715          * on mlx5e_attach_netdev() we will call mlx5e_update_features()
4716          * To update netdev->features please modify mlx5e_fix_features()
4717          */
4718 }
4719
4720 static void mlx5e_set_netdev_dev_addr(struct net_device *netdev)
4721 {
4722         struct mlx5e_priv *priv = netdev_priv(netdev);
4723
4724         mlx5_query_mac_address(priv->mdev, netdev->dev_addr);
4725         if (is_zero_ether_addr(netdev->dev_addr) &&
4726             !MLX5_CAP_GEN(priv->mdev, vport_group_manager)) {
4727                 eth_hw_addr_random(netdev);
4728                 mlx5_core_info(priv->mdev, "Assigned random MAC address %pM\n", netdev->dev_addr);
4729         }
4730 }
4731
4732 static int mlx5e_vxlan_set_port(struct net_device *netdev, unsigned int table,
4733                                 unsigned int entry, struct udp_tunnel_info *ti)
4734 {
4735         struct mlx5e_priv *priv = netdev_priv(netdev);
4736
4737         return mlx5_vxlan_add_port(priv->mdev->vxlan, ntohs(ti->port));
4738 }
4739
4740 static int mlx5e_vxlan_unset_port(struct net_device *netdev, unsigned int table,
4741                                   unsigned int entry, struct udp_tunnel_info *ti)
4742 {
4743         struct mlx5e_priv *priv = netdev_priv(netdev);
4744
4745         return mlx5_vxlan_del_port(priv->mdev->vxlan, ntohs(ti->port));
4746 }
4747
4748 void mlx5e_vxlan_set_netdev_info(struct mlx5e_priv *priv)
4749 {
4750         if (!mlx5_vxlan_allowed(priv->mdev->vxlan))
4751                 return;
4752
4753         priv->nic_info.set_port = mlx5e_vxlan_set_port;
4754         priv->nic_info.unset_port = mlx5e_vxlan_unset_port;
4755         priv->nic_info.flags = UDP_TUNNEL_NIC_INFO_MAY_SLEEP |
4756                                 UDP_TUNNEL_NIC_INFO_STATIC_IANA_VXLAN;
4757         priv->nic_info.tables[0].tunnel_types = UDP_TUNNEL_TYPE_VXLAN;
4758         /* Don't count the space hard-coded to the IANA port */
4759         priv->nic_info.tables[0].n_entries =
4760                 mlx5_vxlan_max_udp_ports(priv->mdev) - 1;
4761
4762         priv->netdev->udp_tunnel_nic_info = &priv->nic_info;
4763 }
4764
4765 static bool mlx5e_tunnel_any_tx_proto_supported(struct mlx5_core_dev *mdev)
4766 {
4767         int tt;
4768
4769         for (tt = 0; tt < MLX5E_NUM_TUNNEL_TT; tt++) {
4770                 if (mlx5e_tunnel_proto_supported_tx(mdev, mlx5e_get_proto_by_tunnel_type(tt)))
4771                         return true;
4772         }
4773         return (mlx5_vxlan_allowed(mdev->vxlan) || mlx5_geneve_tx_allowed(mdev));
4774 }
4775
4776 static void mlx5e_build_nic_netdev(struct net_device *netdev)
4777 {
4778         struct mlx5e_priv *priv = netdev_priv(netdev);
4779         struct mlx5_core_dev *mdev = priv->mdev;
4780         bool fcs_supported;
4781         bool fcs_enabled;
4782
4783         SET_NETDEV_DEV(netdev, mdev->device);
4784
4785         netdev->netdev_ops = &mlx5e_netdev_ops;
4786
4787         mlx5e_dcbnl_build_netdev(netdev);
4788
4789         netdev->watchdog_timeo    = 15 * HZ;
4790
4791         netdev->ethtool_ops       = &mlx5e_ethtool_ops;
4792
4793         netdev->vlan_features    |= NETIF_F_SG;
4794         netdev->vlan_features    |= NETIF_F_HW_CSUM;
4795         netdev->vlan_features    |= NETIF_F_GRO;
4796         netdev->vlan_features    |= NETIF_F_TSO;
4797         netdev->vlan_features    |= NETIF_F_TSO6;
4798         netdev->vlan_features    |= NETIF_F_RXCSUM;
4799         netdev->vlan_features    |= NETIF_F_RXHASH;
4800
4801         netdev->mpls_features    |= NETIF_F_SG;
4802         netdev->mpls_features    |= NETIF_F_HW_CSUM;
4803         netdev->mpls_features    |= NETIF_F_TSO;
4804         netdev->mpls_features    |= NETIF_F_TSO6;
4805
4806         netdev->hw_enc_features  |= NETIF_F_HW_VLAN_CTAG_TX;
4807         netdev->hw_enc_features  |= NETIF_F_HW_VLAN_CTAG_RX;
4808
4809         if (!!MLX5_CAP_ETH(mdev, lro_cap) &&
4810             mlx5e_check_fragmented_striding_rq_cap(mdev))
4811                 netdev->vlan_features    |= NETIF_F_LRO;
4812
4813         netdev->hw_features       = netdev->vlan_features;
4814         netdev->hw_features      |= NETIF_F_HW_VLAN_CTAG_TX;
4815         netdev->hw_features      |= NETIF_F_HW_VLAN_CTAG_RX;
4816         netdev->hw_features      |= NETIF_F_HW_VLAN_CTAG_FILTER;
4817         netdev->hw_features      |= NETIF_F_HW_VLAN_STAG_TX;
4818
4819         if (mlx5e_tunnel_any_tx_proto_supported(mdev)) {
4820                 netdev->hw_enc_features |= NETIF_F_HW_CSUM;
4821                 netdev->hw_enc_features |= NETIF_F_TSO;
4822                 netdev->hw_enc_features |= NETIF_F_TSO6;
4823                 netdev->hw_enc_features |= NETIF_F_GSO_PARTIAL;
4824         }
4825
4826         if (mlx5_vxlan_allowed(mdev->vxlan) || mlx5_geneve_tx_allowed(mdev)) {
4827                 netdev->hw_features     |= NETIF_F_GSO_UDP_TUNNEL |
4828                                            NETIF_F_GSO_UDP_TUNNEL_CSUM;
4829                 netdev->hw_enc_features |= NETIF_F_GSO_UDP_TUNNEL |
4830                                            NETIF_F_GSO_UDP_TUNNEL_CSUM;
4831                 netdev->gso_partial_features = NETIF_F_GSO_UDP_TUNNEL_CSUM;
4832                 netdev->vlan_features |= NETIF_F_GSO_UDP_TUNNEL |
4833                                          NETIF_F_GSO_UDP_TUNNEL_CSUM;
4834         }
4835
4836         if (mlx5e_tunnel_proto_supported_tx(mdev, IPPROTO_GRE)) {
4837                 netdev->hw_features     |= NETIF_F_GSO_GRE |
4838                                            NETIF_F_GSO_GRE_CSUM;
4839                 netdev->hw_enc_features |= NETIF_F_GSO_GRE |
4840                                            NETIF_F_GSO_GRE_CSUM;
4841                 netdev->gso_partial_features |= NETIF_F_GSO_GRE |
4842                                                 NETIF_F_GSO_GRE_CSUM;
4843         }
4844
4845         if (mlx5e_tunnel_proto_supported_tx(mdev, IPPROTO_IPIP)) {
4846                 netdev->hw_features |= NETIF_F_GSO_IPXIP4 |
4847                                        NETIF_F_GSO_IPXIP6;
4848                 netdev->hw_enc_features |= NETIF_F_GSO_IPXIP4 |
4849                                            NETIF_F_GSO_IPXIP6;
4850                 netdev->gso_partial_features |= NETIF_F_GSO_IPXIP4 |
4851                                                 NETIF_F_GSO_IPXIP6;
4852         }
4853
4854         netdev->hw_features                      |= NETIF_F_GSO_PARTIAL;
4855         netdev->gso_partial_features             |= NETIF_F_GSO_UDP_L4;
4856         netdev->hw_features                      |= NETIF_F_GSO_UDP_L4;
4857         netdev->features                         |= NETIF_F_GSO_UDP_L4;
4858
4859         mlx5_query_port_fcs(mdev, &fcs_supported, &fcs_enabled);
4860
4861         if (fcs_supported)
4862                 netdev->hw_features |= NETIF_F_RXALL;
4863
4864         if (MLX5_CAP_ETH(mdev, scatter_fcs))
4865                 netdev->hw_features |= NETIF_F_RXFCS;
4866
4867         netdev->features          = netdev->hw_features;
4868
4869         /* Defaults */
4870         if (fcs_enabled)
4871                 netdev->features  &= ~NETIF_F_RXALL;
4872         netdev->features  &= ~NETIF_F_LRO;
4873         netdev->features  &= ~NETIF_F_RXFCS;
4874
4875 #define FT_CAP(f) MLX5_CAP_FLOWTABLE(mdev, flow_table_properties_nic_receive.f)
4876         if (FT_CAP(flow_modify_en) &&
4877             FT_CAP(modify_root) &&
4878             FT_CAP(identified_miss_table_mode) &&
4879             FT_CAP(flow_table_modify)) {
4880 #if IS_ENABLED(CONFIG_MLX5_CLS_ACT)
4881                 netdev->hw_features      |= NETIF_F_HW_TC;
4882 #endif
4883 #ifdef CONFIG_MLX5_EN_ARFS
4884                 netdev->hw_features      |= NETIF_F_NTUPLE;
4885 #endif
4886         }
4887         if (mlx5_qos_is_supported(mdev))
4888                 netdev->features |= NETIF_F_HW_TC;
4889
4890         netdev->features         |= NETIF_F_HIGHDMA;
4891         netdev->features         |= NETIF_F_HW_VLAN_STAG_FILTER;
4892
4893         netdev->priv_flags       |= IFF_UNICAST_FLT;
4894
4895         mlx5e_set_netdev_dev_addr(netdev);
4896         mlx5e_ipsec_build_netdev(priv);
4897         mlx5e_tls_build_netdev(priv);
4898 }
4899
4900 void mlx5e_create_q_counters(struct mlx5e_priv *priv)
4901 {
4902         u32 out[MLX5_ST_SZ_DW(alloc_q_counter_out)] = {};
4903         u32 in[MLX5_ST_SZ_DW(alloc_q_counter_in)] = {};
4904         struct mlx5_core_dev *mdev = priv->mdev;
4905         int err;
4906
4907         MLX5_SET(alloc_q_counter_in, in, opcode, MLX5_CMD_OP_ALLOC_Q_COUNTER);
4908         err = mlx5_cmd_exec_inout(mdev, alloc_q_counter, in, out);
4909         if (!err)
4910                 priv->q_counter =
4911                         MLX5_GET(alloc_q_counter_out, out, counter_set_id);
4912
4913         err = mlx5_cmd_exec_inout(mdev, alloc_q_counter, in, out);
4914         if (!err)
4915                 priv->drop_rq_q_counter =
4916                         MLX5_GET(alloc_q_counter_out, out, counter_set_id);
4917 }
4918
4919 void mlx5e_destroy_q_counters(struct mlx5e_priv *priv)
4920 {
4921         u32 in[MLX5_ST_SZ_DW(dealloc_q_counter_in)] = {};
4922
4923         MLX5_SET(dealloc_q_counter_in, in, opcode,
4924                  MLX5_CMD_OP_DEALLOC_Q_COUNTER);
4925         if (priv->q_counter) {
4926                 MLX5_SET(dealloc_q_counter_in, in, counter_set_id,
4927                          priv->q_counter);
4928                 mlx5_cmd_exec_in(priv->mdev, dealloc_q_counter, in);
4929         }
4930
4931         if (priv->drop_rq_q_counter) {
4932                 MLX5_SET(dealloc_q_counter_in, in, counter_set_id,
4933                          priv->drop_rq_q_counter);
4934                 mlx5_cmd_exec_in(priv->mdev, dealloc_q_counter, in);
4935         }
4936 }
4937
4938 static int mlx5e_nic_init(struct mlx5_core_dev *mdev,
4939                           struct net_device *netdev)
4940 {
4941         struct mlx5e_priv *priv = netdev_priv(netdev);
4942         struct devlink_port *dl_port;
4943         int err;
4944
4945         mlx5e_build_nic_params(priv, &priv->xsk, netdev->mtu);
4946         mlx5e_vxlan_set_netdev_info(priv);
4947
4948         mlx5e_timestamp_init(priv);
4949
4950         err = mlx5e_ipsec_init(priv);
4951         if (err)
4952                 mlx5_core_err(mdev, "IPSec initialization failed, %d\n", err);
4953
4954         err = mlx5e_tls_init(priv);
4955         if (err)
4956                 mlx5_core_err(mdev, "TLS initialization failed, %d\n", err);
4957
4958         dl_port = mlx5e_devlink_get_dl_port(priv);
4959         if (dl_port->registered)
4960                 mlx5e_health_create_reporters(priv);
4961
4962         return 0;
4963 }
4964
4965 static void mlx5e_nic_cleanup(struct mlx5e_priv *priv)
4966 {
4967         struct devlink_port *dl_port = mlx5e_devlink_get_dl_port(priv);
4968
4969         if (dl_port->registered)
4970                 mlx5e_health_destroy_reporters(priv);
4971         mlx5e_tls_cleanup(priv);
4972         mlx5e_ipsec_cleanup(priv);
4973 }
4974
4975 static int mlx5e_init_nic_rx(struct mlx5e_priv *priv)
4976 {
4977         struct mlx5_core_dev *mdev = priv->mdev;
4978         u16 max_nch = priv->max_nch;
4979         int err;
4980
4981         mlx5e_create_q_counters(priv);
4982
4983         err = mlx5e_open_drop_rq(priv, &priv->drop_rq);
4984         if (err) {
4985                 mlx5_core_err(mdev, "open drop rq failed, %d\n", err);
4986                 goto err_destroy_q_counters;
4987         }
4988
4989         err = mlx5e_create_indirect_rqt(priv);
4990         if (err)
4991                 goto err_close_drop_rq;
4992
4993         err = mlx5e_create_direct_rqts(priv, priv->direct_tir, max_nch);
4994         if (err)
4995                 goto err_destroy_indirect_rqts;
4996
4997         err = mlx5e_create_indirect_tirs(priv, true);
4998         if (err)
4999                 goto err_destroy_direct_rqts;
5000
5001         err = mlx5e_create_direct_tirs(priv, priv->direct_tir, max_nch);
5002         if (err)
5003                 goto err_destroy_indirect_tirs;
5004
5005         err = mlx5e_create_direct_rqts(priv, priv->xsk_tir, max_nch);
5006         if (unlikely(err))
5007                 goto err_destroy_direct_tirs;
5008
5009         err = mlx5e_create_direct_tirs(priv, priv->xsk_tir, max_nch);
5010         if (unlikely(err))
5011                 goto err_destroy_xsk_rqts;
5012
5013         err = mlx5e_create_direct_rqts(priv, &priv->ptp_tir, 1);
5014         if (err)
5015                 goto err_destroy_xsk_tirs;
5016
5017         err = mlx5e_create_direct_tirs(priv, &priv->ptp_tir, 1);
5018         if (err)
5019                 goto err_destroy_ptp_rqt;
5020
5021         err = mlx5e_create_flow_steering(priv);
5022         if (err) {
5023                 mlx5_core_warn(mdev, "create flow steering failed, %d\n", err);
5024                 goto err_destroy_ptp_direct_tir;
5025         }
5026
5027         err = mlx5e_tc_nic_init(priv);
5028         if (err)
5029                 goto err_destroy_flow_steering;
5030
5031         err = mlx5e_accel_init_rx(priv);
5032         if (err)
5033                 goto err_tc_nic_cleanup;
5034
5035 #ifdef CONFIG_MLX5_EN_ARFS
5036         priv->netdev->rx_cpu_rmap =  mlx5_eq_table_get_rmap(priv->mdev);
5037 #endif
5038
5039         return 0;
5040
5041 err_tc_nic_cleanup:
5042         mlx5e_tc_nic_cleanup(priv);
5043 err_destroy_flow_steering:
5044         mlx5e_destroy_flow_steering(priv);
5045 err_destroy_ptp_direct_tir:
5046         mlx5e_destroy_direct_tirs(priv, &priv->ptp_tir, 1);
5047 err_destroy_ptp_rqt:
5048         mlx5e_destroy_direct_rqts(priv, &priv->ptp_tir, 1);
5049 err_destroy_xsk_tirs:
5050         mlx5e_destroy_direct_tirs(priv, priv->xsk_tir, max_nch);
5051 err_destroy_xsk_rqts:
5052         mlx5e_destroy_direct_rqts(priv, priv->xsk_tir, max_nch);
5053 err_destroy_direct_tirs:
5054         mlx5e_destroy_direct_tirs(priv, priv->direct_tir, max_nch);
5055 err_destroy_indirect_tirs:
5056         mlx5e_destroy_indirect_tirs(priv);
5057 err_destroy_direct_rqts:
5058         mlx5e_destroy_direct_rqts(priv, priv->direct_tir, max_nch);
5059 err_destroy_indirect_rqts:
5060         mlx5e_destroy_rqt(priv, &priv->indir_rqt);
5061 err_close_drop_rq:
5062         mlx5e_close_drop_rq(&priv->drop_rq);
5063 err_destroy_q_counters:
5064         mlx5e_destroy_q_counters(priv);
5065         return err;
5066 }
5067
5068 static void mlx5e_cleanup_nic_rx(struct mlx5e_priv *priv)
5069 {
5070         u16 max_nch = priv->max_nch;
5071
5072         mlx5e_accel_cleanup_rx(priv);
5073         mlx5e_tc_nic_cleanup(priv);
5074         mlx5e_destroy_flow_steering(priv);
5075         mlx5e_destroy_direct_tirs(priv, &priv->ptp_tir, 1);
5076         mlx5e_destroy_direct_rqts(priv, &priv->ptp_tir, 1);
5077         mlx5e_destroy_direct_tirs(priv, priv->xsk_tir, max_nch);
5078         mlx5e_destroy_direct_rqts(priv, priv->xsk_tir, max_nch);
5079         mlx5e_destroy_direct_tirs(priv, priv->direct_tir, max_nch);
5080         mlx5e_destroy_indirect_tirs(priv);
5081         mlx5e_destroy_direct_rqts(priv, priv->direct_tir, max_nch);
5082         mlx5e_destroy_rqt(priv, &priv->indir_rqt);
5083         mlx5e_close_drop_rq(&priv->drop_rq);
5084         mlx5e_destroy_q_counters(priv);
5085 }
5086
5087 static int mlx5e_init_nic_tx(struct mlx5e_priv *priv)
5088 {
5089         int err;
5090
5091         err = mlx5e_create_tises(priv);
5092         if (err) {
5093                 mlx5_core_warn(priv->mdev, "create tises failed, %d\n", err);
5094                 return err;
5095         }
5096
5097         mlx5e_dcbnl_initialize(priv);
5098         return 0;
5099 }
5100
5101 static void mlx5e_nic_enable(struct mlx5e_priv *priv)
5102 {
5103         struct net_device *netdev = priv->netdev;
5104         struct mlx5_core_dev *mdev = priv->mdev;
5105
5106         mlx5e_init_l2_addr(priv);
5107
5108         /* Marking the link as currently not needed by the Driver */
5109         if (!netif_running(netdev))
5110                 mlx5e_modify_admin_state(mdev, MLX5_PORT_DOWN);
5111
5112         mlx5e_set_netdev_mtu_boundaries(priv);
5113         mlx5e_set_dev_port_mtu(priv);
5114
5115         mlx5_lag_add(mdev, netdev);
5116
5117         mlx5e_enable_async_events(priv);
5118         mlx5e_enable_blocking_events(priv);
5119         if (mlx5e_monitor_counter_supported(priv))
5120                 mlx5e_monitor_counter_init(priv);
5121
5122         mlx5e_hv_vhca_stats_create(priv);
5123         if (netdev->reg_state != NETREG_REGISTERED)
5124                 return;
5125         mlx5e_dcbnl_init_app(priv);
5126
5127         mlx5e_nic_set_rx_mode(priv);
5128
5129         rtnl_lock();
5130         if (netif_running(netdev))
5131                 mlx5e_open(netdev);
5132         udp_tunnel_nic_reset_ntf(priv->netdev);
5133         netif_device_attach(netdev);
5134         rtnl_unlock();
5135 }
5136
5137 static void mlx5e_nic_disable(struct mlx5e_priv *priv)
5138 {
5139         struct mlx5_core_dev *mdev = priv->mdev;
5140
5141         if (priv->netdev->reg_state == NETREG_REGISTERED)
5142                 mlx5e_dcbnl_delete_app(priv);
5143
5144         rtnl_lock();
5145         if (netif_running(priv->netdev))
5146                 mlx5e_close(priv->netdev);
5147         netif_device_detach(priv->netdev);
5148         rtnl_unlock();
5149
5150         mlx5e_nic_set_rx_mode(priv);
5151
5152         mlx5e_hv_vhca_stats_destroy(priv);
5153         if (mlx5e_monitor_counter_supported(priv))
5154                 mlx5e_monitor_counter_cleanup(priv);
5155
5156         mlx5e_disable_blocking_events(priv);
5157         if (priv->en_trap) {
5158                 mlx5e_deactivate_trap(priv);
5159                 mlx5e_close_trap(priv->en_trap);
5160                 priv->en_trap = NULL;
5161         }
5162         mlx5e_disable_async_events(priv);
5163         mlx5_lag_remove(mdev);
5164         mlx5_vxlan_reset_to_default(mdev->vxlan);
5165 }
5166
5167 int mlx5e_update_nic_rx(struct mlx5e_priv *priv)
5168 {
5169         return mlx5e_refresh_tirs(priv, false, false);
5170 }
5171
5172 static const struct mlx5e_profile mlx5e_nic_profile = {
5173         .init              = mlx5e_nic_init,
5174         .cleanup           = mlx5e_nic_cleanup,
5175         .init_rx           = mlx5e_init_nic_rx,
5176         .cleanup_rx        = mlx5e_cleanup_nic_rx,
5177         .init_tx           = mlx5e_init_nic_tx,
5178         .cleanup_tx        = mlx5e_cleanup_nic_tx,
5179         .enable            = mlx5e_nic_enable,
5180         .disable           = mlx5e_nic_disable,
5181         .update_rx         = mlx5e_update_nic_rx,
5182         .update_stats      = mlx5e_stats_update_ndo_stats,
5183         .update_carrier    = mlx5e_update_carrier,
5184         .rx_handlers       = &mlx5e_rx_handlers_nic,
5185         .max_tc            = MLX5E_MAX_NUM_TC,
5186         .rq_groups         = MLX5E_NUM_RQ_GROUPS(XSK),
5187         .stats_grps        = mlx5e_nic_stats_grps,
5188         .stats_grps_num    = mlx5e_nic_stats_grps_num,
5189         .rx_ptp_support    = true,
5190 };
5191
5192 /* mlx5e generic netdev management API (move to en_common.c) */
5193 int mlx5e_priv_init(struct mlx5e_priv *priv,
5194                     struct net_device *netdev,
5195                     struct mlx5_core_dev *mdev)
5196 {
5197         /* priv init */
5198         priv->mdev        = mdev;
5199         priv->netdev      = netdev;
5200         priv->msglevel    = MLX5E_MSG_LEVEL;
5201         priv->max_opened_tc = 1;
5202
5203         if (!alloc_cpumask_var(&priv->scratchpad.cpumask, GFP_KERNEL))
5204                 return -ENOMEM;
5205
5206         mutex_init(&priv->state_lock);
5207         hash_init(priv->htb.qos_tc2node);
5208         INIT_WORK(&priv->update_carrier_work, mlx5e_update_carrier_work);
5209         INIT_WORK(&priv->set_rx_mode_work, mlx5e_set_rx_mode_work);
5210         INIT_WORK(&priv->tx_timeout_work, mlx5e_tx_timeout_work);
5211         INIT_WORK(&priv->update_stats_work, mlx5e_update_stats_work);
5212
5213         priv->wq = create_singlethread_workqueue("mlx5e");
5214         if (!priv->wq)
5215                 goto err_free_cpumask;
5216
5217         return 0;
5218
5219 err_free_cpumask:
5220         free_cpumask_var(priv->scratchpad.cpumask);
5221
5222         return -ENOMEM;
5223 }
5224
5225 void mlx5e_priv_cleanup(struct mlx5e_priv *priv)
5226 {
5227         int i;
5228
5229         /* bail if change profile failed and also rollback failed */
5230         if (!priv->mdev)
5231                 return;
5232
5233         destroy_workqueue(priv->wq);
5234         free_cpumask_var(priv->scratchpad.cpumask);
5235
5236         for (i = 0; i < priv->htb.max_qos_sqs; i++)
5237                 kfree(priv->htb.qos_sq_stats[i]);
5238         kvfree(priv->htb.qos_sq_stats);
5239
5240         memset(priv, 0, sizeof(*priv));
5241 }
5242
5243 struct net_device *
5244 mlx5e_create_netdev(struct mlx5_core_dev *mdev, unsigned int txqs, unsigned int rxqs)
5245 {
5246         struct net_device *netdev;
5247         int err;
5248
5249         netdev = alloc_etherdev_mqs(sizeof(struct mlx5e_priv), txqs, rxqs);
5250         if (!netdev) {
5251                 mlx5_core_err(mdev, "alloc_etherdev_mqs() failed\n");
5252                 return NULL;
5253         }
5254
5255         err = mlx5e_priv_init(netdev_priv(netdev), netdev, mdev);
5256         if (err) {
5257                 mlx5_core_err(mdev, "mlx5e_priv_init failed, err=%d\n", err);
5258                 goto err_free_netdev;
5259         }
5260
5261         netif_carrier_off(netdev);
5262         dev_net_set(netdev, mlx5_core_net(mdev));
5263
5264         return netdev;
5265
5266 err_free_netdev:
5267         free_netdev(netdev);
5268
5269         return NULL;
5270 }
5271
5272 static void mlx5e_update_features(struct net_device *netdev)
5273 {
5274         if (netdev->reg_state != NETREG_REGISTERED)
5275                 return; /* features will be updated on netdev registration */
5276
5277         rtnl_lock();
5278         netdev_update_features(netdev);
5279         rtnl_unlock();
5280 }
5281
5282 static void mlx5e_reset_channels(struct net_device *netdev)
5283 {
5284         netdev_reset_tc(netdev);
5285 }
5286
5287 int mlx5e_attach_netdev(struct mlx5e_priv *priv)
5288 {
5289         const bool take_rtnl = priv->netdev->reg_state == NETREG_REGISTERED;
5290         const struct mlx5e_profile *profile = priv->profile;
5291         int max_nch;
5292         int err;
5293
5294         clear_bit(MLX5E_STATE_DESTROYING, &priv->state);
5295
5296         /* max number of channels may have changed */
5297         max_nch = mlx5e_get_max_num_channels(priv->mdev);
5298         if (priv->channels.params.num_channels > max_nch) {
5299                 mlx5_core_warn(priv->mdev, "MLX5E: Reducing number of channels to %d\n", max_nch);
5300                 /* Reducing the number of channels - RXFH has to be reset, and
5301                  * mlx5e_num_channels_changed below will build the RQT.
5302                  */
5303                 priv->netdev->priv_flags &= ~IFF_RXFH_CONFIGURED;
5304                 priv->channels.params.num_channels = max_nch;
5305         }
5306         /* 1. Set the real number of queues in the kernel the first time.
5307          * 2. Set our default XPS cpumask.
5308          * 3. Build the RQT.
5309          *
5310          * rtnl_lock is required by netif_set_real_num_*_queues in case the
5311          * netdev has been registered by this point (if this function was called
5312          * in the reload or resume flow).
5313          */
5314         if (take_rtnl)
5315                 rtnl_lock();
5316         err = mlx5e_num_channels_changed(priv);
5317         if (take_rtnl)
5318                 rtnl_unlock();
5319         if (err)
5320                 goto out;
5321
5322         err = profile->init_tx(priv);
5323         if (err)
5324                 goto out;
5325
5326         err = profile->init_rx(priv);
5327         if (err)
5328                 goto err_cleanup_tx;
5329
5330         if (profile->enable)
5331                 profile->enable(priv);
5332
5333         mlx5e_update_features(priv->netdev);
5334
5335         return 0;
5336
5337 err_cleanup_tx:
5338         profile->cleanup_tx(priv);
5339
5340 out:
5341         mlx5e_reset_channels(priv->netdev);
5342         set_bit(MLX5E_STATE_DESTROYING, &priv->state);
5343         cancel_work_sync(&priv->update_stats_work);
5344         return err;
5345 }
5346
5347 void mlx5e_detach_netdev(struct mlx5e_priv *priv)
5348 {
5349         const struct mlx5e_profile *profile = priv->profile;
5350
5351         set_bit(MLX5E_STATE_DESTROYING, &priv->state);
5352
5353         if (profile->disable)
5354                 profile->disable(priv);
5355         flush_workqueue(priv->wq);
5356
5357         profile->cleanup_rx(priv);
5358         profile->cleanup_tx(priv);
5359         mlx5e_reset_channels(priv->netdev);
5360         cancel_work_sync(&priv->update_stats_work);
5361 }
5362
5363 static int
5364 mlx5e_netdev_attach_profile(struct net_device *netdev, struct mlx5_core_dev *mdev,
5365                             const struct mlx5e_profile *new_profile, void *new_ppriv)
5366 {
5367         struct mlx5e_priv *priv = netdev_priv(netdev);
5368         int err;
5369
5370         err = mlx5e_priv_init(priv, netdev, mdev);
5371         if (err) {
5372                 mlx5_core_err(mdev, "mlx5e_priv_init failed, err=%d\n", err);
5373                 return err;
5374         }
5375         netif_carrier_off(netdev);
5376         priv->profile = new_profile;
5377         priv->ppriv = new_ppriv;
5378         err = new_profile->init(priv->mdev, priv->netdev);
5379         if (err)
5380                 goto priv_cleanup;
5381         err = mlx5e_attach_netdev(priv);
5382         if (err)
5383                 goto profile_cleanup;
5384         return err;
5385
5386 profile_cleanup:
5387         new_profile->cleanup(priv);
5388 priv_cleanup:
5389         mlx5e_priv_cleanup(priv);
5390         return err;
5391 }
5392
5393 int mlx5e_netdev_change_profile(struct mlx5e_priv *priv,
5394                                 const struct mlx5e_profile *new_profile, void *new_ppriv)
5395 {
5396         unsigned int new_max_nch = mlx5e_calc_max_nch(priv, new_profile);
5397         const struct mlx5e_profile *orig_profile = priv->profile;
5398         struct net_device *netdev = priv->netdev;
5399         struct mlx5_core_dev *mdev = priv->mdev;
5400         void *orig_ppriv = priv->ppriv;
5401         int err, rollback_err;
5402
5403         /* sanity */
5404         if (new_max_nch != priv->max_nch) {
5405                 netdev_warn(netdev, "%s: Replacing profile with different max channels\n",
5406                             __func__);
5407                 return -EINVAL;
5408         }
5409
5410         /* cleanup old profile */
5411         mlx5e_detach_netdev(priv);
5412         priv->profile->cleanup(priv);
5413         mlx5e_priv_cleanup(priv);
5414
5415         err = mlx5e_netdev_attach_profile(netdev, mdev, new_profile, new_ppriv);
5416         if (err) { /* roll back to original profile */
5417                 netdev_warn(netdev, "%s: new profile init failed, %d\n", __func__, err);
5418                 goto rollback;
5419         }
5420
5421         return 0;
5422
5423 rollback:
5424         rollback_err = mlx5e_netdev_attach_profile(netdev, mdev, orig_profile, orig_ppriv);
5425         if (rollback_err)
5426                 netdev_err(netdev, "%s: failed to rollback to orig profile, %d\n",
5427                            __func__, rollback_err);
5428         return err;
5429 }
5430
5431 void mlx5e_netdev_attach_nic_profile(struct mlx5e_priv *priv)
5432 {
5433         mlx5e_netdev_change_profile(priv, &mlx5e_nic_profile, NULL);
5434 }
5435
5436 void mlx5e_destroy_netdev(struct mlx5e_priv *priv)
5437 {
5438         struct net_device *netdev = priv->netdev;
5439
5440         mlx5e_priv_cleanup(priv);
5441         free_netdev(netdev);
5442 }
5443
5444 static int mlx5e_resume(struct auxiliary_device *adev)
5445 {
5446         struct mlx5_adev *edev = container_of(adev, struct mlx5_adev, adev);
5447         struct mlx5e_priv *priv = dev_get_drvdata(&adev->dev);
5448         struct net_device *netdev = priv->netdev;
5449         struct mlx5_core_dev *mdev = edev->mdev;
5450         int err;
5451
5452         if (netif_device_present(netdev))
5453                 return 0;
5454
5455         err = mlx5e_create_mdev_resources(mdev);
5456         if (err)
5457                 return err;
5458
5459         err = mlx5e_attach_netdev(priv);
5460         if (err) {
5461                 mlx5e_destroy_mdev_resources(mdev);
5462                 return err;
5463         }
5464
5465         return 0;
5466 }
5467
5468 static int mlx5e_suspend(struct auxiliary_device *adev, pm_message_t state)
5469 {
5470         struct mlx5e_priv *priv = dev_get_drvdata(&adev->dev);
5471         struct net_device *netdev = priv->netdev;
5472         struct mlx5_core_dev *mdev = priv->mdev;
5473
5474         if (!netif_device_present(netdev))
5475                 return -ENODEV;
5476
5477         mlx5e_detach_netdev(priv);
5478         mlx5e_destroy_mdev_resources(mdev);
5479         return 0;
5480 }
5481
5482 static int mlx5e_probe(struct auxiliary_device *adev,
5483                        const struct auxiliary_device_id *id)
5484 {
5485         struct mlx5_adev *edev = container_of(adev, struct mlx5_adev, adev);
5486         const struct mlx5e_profile *profile = &mlx5e_nic_profile;
5487         struct mlx5_core_dev *mdev = edev->mdev;
5488         struct net_device *netdev;
5489         pm_message_t state = {};
5490         unsigned int txqs, rxqs, ptp_txqs = 0;
5491         struct mlx5e_priv *priv;
5492         int qos_sqs = 0;
5493         int err;
5494         int nch;
5495
5496         if (MLX5_CAP_GEN(mdev, ts_cqe_to_dest_cqn))
5497                 ptp_txqs = profile->max_tc;
5498
5499         if (mlx5_qos_is_supported(mdev))
5500                 qos_sqs = mlx5e_qos_max_leaf_nodes(mdev);
5501
5502         nch = mlx5e_get_max_num_channels(mdev);
5503         txqs = nch * profile->max_tc + ptp_txqs + qos_sqs;
5504         rxqs = nch * profile->rq_groups;
5505         netdev = mlx5e_create_netdev(mdev, txqs, rxqs);
5506         if (!netdev) {
5507                 mlx5_core_err(mdev, "mlx5e_create_netdev failed\n");
5508                 return -ENOMEM;
5509         }
5510
5511         mlx5e_build_nic_netdev(netdev);
5512
5513         priv = netdev_priv(netdev);
5514         dev_set_drvdata(&adev->dev, priv);
5515
5516         priv->profile = profile;
5517         priv->ppriv = NULL;
5518
5519         err = mlx5e_devlink_port_register(priv);
5520         if (err) {
5521                 mlx5_core_err(mdev, "mlx5e_devlink_port_register failed, %d\n", err);
5522                 goto err_destroy_netdev;
5523         }
5524
5525         err = profile->init(mdev, netdev);
5526         if (err) {
5527                 mlx5_core_err(mdev, "mlx5e_nic_profile init failed, %d\n", err);
5528                 goto err_devlink_cleanup;
5529         }
5530
5531         err = mlx5e_resume(adev);
5532         if (err) {
5533                 mlx5_core_err(mdev, "mlx5e_resume failed, %d\n", err);
5534                 goto err_profile_cleanup;
5535         }
5536
5537         err = register_netdev(netdev);
5538         if (err) {
5539                 mlx5_core_err(mdev, "register_netdev failed, %d\n", err);
5540                 goto err_resume;
5541         }
5542
5543         mlx5e_devlink_port_type_eth_set(priv);
5544
5545         mlx5e_dcbnl_init_app(priv);
5546         mlx5_uplink_netdev_set(mdev, netdev);
5547         return 0;
5548
5549 err_resume:
5550         mlx5e_suspend(adev, state);
5551 err_profile_cleanup:
5552         profile->cleanup(priv);
5553 err_devlink_cleanup:
5554         mlx5e_devlink_port_unregister(priv);
5555 err_destroy_netdev:
5556         mlx5e_destroy_netdev(priv);
5557         return err;
5558 }
5559
5560 static void mlx5e_remove(struct auxiliary_device *adev)
5561 {
5562         struct mlx5e_priv *priv = dev_get_drvdata(&adev->dev);
5563         pm_message_t state = {};
5564
5565         mlx5e_dcbnl_delete_app(priv);
5566         unregister_netdev(priv->netdev);
5567         mlx5e_suspend(adev, state);
5568         priv->profile->cleanup(priv);
5569         mlx5e_devlink_port_unregister(priv);
5570         mlx5e_destroy_netdev(priv);
5571 }
5572
5573 static const struct auxiliary_device_id mlx5e_id_table[] = {
5574         { .name = MLX5_ADEV_NAME ".eth", },
5575         {},
5576 };
5577
5578 MODULE_DEVICE_TABLE(auxiliary, mlx5e_id_table);
5579
5580 static struct auxiliary_driver mlx5e_driver = {
5581         .name = "eth",
5582         .probe = mlx5e_probe,
5583         .remove = mlx5e_remove,
5584         .suspend = mlx5e_suspend,
5585         .resume = mlx5e_resume,
5586         .id_table = mlx5e_id_table,
5587 };
5588
5589 int mlx5e_init(void)
5590 {
5591         int ret;
5592
5593         mlx5e_ipsec_build_inverse_table();
5594         mlx5e_build_ptys2ethtool_map();
5595         ret = auxiliary_driver_register(&mlx5e_driver);
5596         if (ret)
5597                 return ret;
5598
5599         ret = mlx5e_rep_init();
5600         if (ret)
5601                 auxiliary_driver_unregister(&mlx5e_driver);
5602         return ret;
5603 }
5604
5605 void mlx5e_cleanup(void)
5606 {
5607         mlx5e_rep_cleanup();
5608         auxiliary_driver_unregister(&mlx5e_driver);
5609 }