2 * Copyright (c) 2015-2016, Mellanox Technologies. All rights reserved.
4 * This software is available to you under a choice of one of two
5 * licenses. You may choose to be licensed under the terms of the GNU
6 * General Public License (GPL) Version 2, available from the file
7 * COPYING in the main directory of this source tree, or the
8 * OpenIB.org BSD license below:
10 * Redistribution and use in source and binary forms, with or
11 * without modification, are permitted provided that the following
14 * - Redistributions of source code must retain the above
15 * copyright notice, this list of conditions and the following
18 * - Redistributions in binary form must reproduce the above
19 * copyright notice, this list of conditions and the following
20 * disclaimer in the documentation and/or other materials
21 * provided with the distribution.
23 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
24 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
25 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
26 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
27 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
28 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
29 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
33 #include <net/tc_act/tc_gact.h>
34 #include <net/pkt_cls.h>
35 #include <linux/mlx5/fs.h>
36 #include <net/vxlan.h>
37 #include <net/geneve.h>
38 #include <linux/bpf.h>
39 #include <linux/if_bridge.h>
40 #include <net/page_pool.h>
41 #include <net/xdp_sock_drv.h>
47 #include "en_accel/ipsec.h"
48 #include "en_accel/en_accel.h"
49 #include "en_accel/tls.h"
50 #include "accel/ipsec.h"
51 #include "accel/tls.h"
52 #include "lib/vxlan.h"
53 #include "lib/clock.h"
57 #include "en/monitor_stats.h"
58 #include "en/health.h"
59 #include "en/params.h"
60 #include "en/xsk/umem.h"
61 #include "en/xsk/setup.h"
62 #include "en/xsk/rx.h"
63 #include "en/xsk/tx.h"
64 #include "en/hv_vhca_stats.h"
65 #include "en/devlink.h"
68 bool mlx5e_check_fragmented_striding_rq_cap(struct mlx5_core_dev *mdev)
70 bool striding_rq_umr = MLX5_CAP_GEN(mdev, striding_rq) &&
71 MLX5_CAP_GEN(mdev, umr_ptr_rlky) &&
72 MLX5_CAP_ETH(mdev, reg_umr_sq);
73 u16 max_wqe_sz_cap = MLX5_CAP_GEN(mdev, max_wqe_sz_sq);
74 bool inline_umr = MLX5E_UMR_WQE_INLINE_SZ <= max_wqe_sz_cap;
79 mlx5_core_warn(mdev, "Cannot support Striding RQ: UMR WQE size (%d) exceeds maximum supported (%d).\n",
80 (int)MLX5E_UMR_WQE_INLINE_SZ, max_wqe_sz_cap);
86 void mlx5e_init_rq_type_params(struct mlx5_core_dev *mdev,
87 struct mlx5e_params *params)
89 params->log_rq_mtu_frames = is_kdump_kernel() ?
90 MLX5E_PARAMS_MINIMUM_LOG_RQ_SIZE :
91 MLX5E_PARAMS_DEFAULT_LOG_RQ_SIZE;
93 mlx5_core_info(mdev, "MLX5E: StrdRq(%d) RqSz(%ld) StrdSz(%ld) RxCqeCmprss(%d)\n",
94 params->rq_wq_type == MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ,
95 params->rq_wq_type == MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ ?
96 BIT(mlx5e_mpwqe_get_log_rq_size(params, NULL)) :
97 BIT(params->log_rq_mtu_frames),
98 BIT(mlx5e_mpwqe_get_log_stride_size(mdev, params, NULL)),
99 MLX5E_GET_PFLAG(params, MLX5E_PFLAG_RX_CQE_COMPRESS));
102 bool mlx5e_striding_rq_possible(struct mlx5_core_dev *mdev,
103 struct mlx5e_params *params)
105 if (!mlx5e_check_fragmented_striding_rq_cap(mdev))
108 if (MLX5_IPSEC_DEV(mdev))
111 if (params->xdp_prog) {
112 /* XSK params are not considered here. If striding RQ is in use,
113 * and an XSK is being opened, mlx5e_rx_mpwqe_is_linear_skb will
114 * be called with the known XSK params.
116 if (!mlx5e_rx_mpwqe_is_linear_skb(mdev, params, NULL))
123 void mlx5e_set_rq_type(struct mlx5_core_dev *mdev, struct mlx5e_params *params)
125 params->rq_wq_type = mlx5e_striding_rq_possible(mdev, params) &&
126 MLX5E_GET_PFLAG(params, MLX5E_PFLAG_RX_STRIDING_RQ) ?
127 MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ :
131 void mlx5e_update_carrier(struct mlx5e_priv *priv)
133 struct mlx5_core_dev *mdev = priv->mdev;
136 port_state = mlx5_query_vport_state(mdev,
137 MLX5_VPORT_STATE_OP_MOD_VNIC_VPORT,
140 if (port_state == VPORT_STATE_UP) {
141 netdev_info(priv->netdev, "Link up\n");
142 netif_carrier_on(priv->netdev);
144 netdev_info(priv->netdev, "Link down\n");
145 netif_carrier_off(priv->netdev);
149 static void mlx5e_update_carrier_work(struct work_struct *work)
151 struct mlx5e_priv *priv = container_of(work, struct mlx5e_priv,
152 update_carrier_work);
154 mutex_lock(&priv->state_lock);
155 if (test_bit(MLX5E_STATE_OPENED, &priv->state))
156 if (priv->profile->update_carrier)
157 priv->profile->update_carrier(priv);
158 mutex_unlock(&priv->state_lock);
161 void mlx5e_update_ndo_stats(struct mlx5e_priv *priv)
165 for (i = mlx5e_nic_stats_grps_num(priv) - 1; i >= 0; i--)
166 if (mlx5e_nic_stats_grps[i]->update_stats_mask &
167 MLX5E_NDO_UPDATE_STATS)
168 mlx5e_nic_stats_grps[i]->update_stats(priv);
171 static void mlx5e_update_stats_work(struct work_struct *work)
173 struct mlx5e_priv *priv = container_of(work, struct mlx5e_priv,
176 mutex_lock(&priv->state_lock);
177 priv->profile->update_stats(priv);
178 mutex_unlock(&priv->state_lock);
181 void mlx5e_queue_update_stats(struct mlx5e_priv *priv)
183 if (!priv->profile->update_stats)
186 if (unlikely(test_bit(MLX5E_STATE_DESTROYING, &priv->state)))
189 queue_work(priv->wq, &priv->update_stats_work);
192 static int async_event(struct notifier_block *nb, unsigned long event, void *data)
194 struct mlx5e_priv *priv = container_of(nb, struct mlx5e_priv, events_nb);
195 struct mlx5_eqe *eqe = data;
197 if (event != MLX5_EVENT_TYPE_PORT_CHANGE)
200 switch (eqe->sub_type) {
201 case MLX5_PORT_CHANGE_SUBTYPE_DOWN:
202 case MLX5_PORT_CHANGE_SUBTYPE_ACTIVE:
203 queue_work(priv->wq, &priv->update_carrier_work);
212 static void mlx5e_enable_async_events(struct mlx5e_priv *priv)
214 priv->events_nb.notifier_call = async_event;
215 mlx5_notifier_register(priv->mdev, &priv->events_nb);
218 static void mlx5e_disable_async_events(struct mlx5e_priv *priv)
220 mlx5_notifier_unregister(priv->mdev, &priv->events_nb);
223 static inline void mlx5e_build_umr_wqe(struct mlx5e_rq *rq,
224 struct mlx5e_icosq *sq,
225 struct mlx5e_umr_wqe *wqe)
227 struct mlx5_wqe_ctrl_seg *cseg = &wqe->ctrl;
228 struct mlx5_wqe_umr_ctrl_seg *ucseg = &wqe->uctrl;
229 u8 ds_cnt = DIV_ROUND_UP(MLX5E_UMR_WQE_INLINE_SZ, MLX5_SEND_WQE_DS);
231 cseg->qpn_ds = cpu_to_be32((sq->sqn << MLX5_WQE_CTRL_QPN_SHIFT) |
233 cseg->umr_mkey = rq->mkey_be;
235 ucseg->flags = MLX5_UMR_TRANSLATION_OFFSET_EN | MLX5_UMR_INLINE;
236 ucseg->xlt_octowords =
237 cpu_to_be16(MLX5_MTT_OCTW(MLX5_MPWRQ_PAGES_PER_WQE));
238 ucseg->mkey_mask = cpu_to_be64(MLX5_MKEY_MASK_FREE);
241 static int mlx5e_rq_alloc_mpwqe_info(struct mlx5e_rq *rq,
242 struct mlx5e_channel *c)
244 int wq_sz = mlx5_wq_ll_get_size(&rq->mpwqe.wq);
246 rq->mpwqe.info = kvzalloc_node(array_size(wq_sz,
247 sizeof(*rq->mpwqe.info)),
248 GFP_KERNEL, cpu_to_node(c->cpu));
252 mlx5e_build_umr_wqe(rq, &c->icosq, &rq->mpwqe.umr_wqe);
257 static int mlx5e_create_umr_mkey(struct mlx5_core_dev *mdev,
258 u64 npages, u8 page_shift,
259 struct mlx5_core_mkey *umr_mkey)
261 int inlen = MLX5_ST_SZ_BYTES(create_mkey_in);
266 in = kvzalloc(inlen, GFP_KERNEL);
270 mkc = MLX5_ADDR_OF(create_mkey_in, in, memory_key_mkey_entry);
272 MLX5_SET(mkc, mkc, free, 1);
273 MLX5_SET(mkc, mkc, umr_en, 1);
274 MLX5_SET(mkc, mkc, lw, 1);
275 MLX5_SET(mkc, mkc, lr, 1);
276 MLX5_SET(mkc, mkc, access_mode_1_0, MLX5_MKC_ACCESS_MODE_MTT);
277 mlx5e_mkey_set_relaxed_ordering(mdev, mkc);
278 MLX5_SET(mkc, mkc, qpn, 0xffffff);
279 MLX5_SET(mkc, mkc, pd, mdev->mlx5e_res.pdn);
280 MLX5_SET64(mkc, mkc, len, npages << page_shift);
281 MLX5_SET(mkc, mkc, translations_octword_size,
282 MLX5_MTT_OCTW(npages));
283 MLX5_SET(mkc, mkc, log_page_size, page_shift);
285 err = mlx5_core_create_mkey(mdev, umr_mkey, in, inlen);
291 static int mlx5e_create_rq_umr_mkey(struct mlx5_core_dev *mdev, struct mlx5e_rq *rq)
293 u64 num_mtts = MLX5E_REQUIRED_MTTS(mlx5_wq_ll_get_size(&rq->mpwqe.wq));
295 return mlx5e_create_umr_mkey(mdev, num_mtts, PAGE_SHIFT, &rq->umr_mkey);
298 static inline u64 mlx5e_get_mpwqe_offset(struct mlx5e_rq *rq, u16 wqe_ix)
300 return (wqe_ix << MLX5E_LOG_ALIGNED_MPWQE_PPW) << PAGE_SHIFT;
303 static void mlx5e_init_frags_partition(struct mlx5e_rq *rq)
305 struct mlx5e_wqe_frag_info next_frag = {};
306 struct mlx5e_wqe_frag_info *prev = NULL;
309 next_frag.di = &rq->wqe.di[0];
311 for (i = 0; i < mlx5_wq_cyc_get_size(&rq->wqe.wq); i++) {
312 struct mlx5e_rq_frag_info *frag_info = &rq->wqe.info.arr[0];
313 struct mlx5e_wqe_frag_info *frag =
314 &rq->wqe.frags[i << rq->wqe.info.log_num_frags];
317 for (f = 0; f < rq->wqe.info.num_frags; f++, frag++) {
318 if (next_frag.offset + frag_info[f].frag_stride > PAGE_SIZE) {
320 next_frag.offset = 0;
322 prev->last_in_page = true;
327 next_frag.offset += frag_info[f].frag_stride;
333 prev->last_in_page = true;
336 static int mlx5e_init_di_list(struct mlx5e_rq *rq,
339 int len = wq_sz << rq->wqe.info.log_num_frags;
341 rq->wqe.di = kvzalloc_node(array_size(len, sizeof(*rq->wqe.di)),
342 GFP_KERNEL, cpu_to_node(cpu));
346 mlx5e_init_frags_partition(rq);
351 static void mlx5e_free_di_list(struct mlx5e_rq *rq)
356 static void mlx5e_rq_err_cqe_work(struct work_struct *recover_work)
358 struct mlx5e_rq *rq = container_of(recover_work, struct mlx5e_rq, recover_work);
360 mlx5e_reporter_rq_cqe_err(rq);
363 static int mlx5e_alloc_rq(struct mlx5e_channel *c,
364 struct mlx5e_params *params,
365 struct mlx5e_xsk_param *xsk,
366 struct xdp_umem *umem,
367 struct mlx5e_rq_param *rqp,
370 struct page_pool_params pp_params = { 0 };
371 struct mlx5_core_dev *mdev = c->mdev;
372 void *rqc = rqp->rqc;
373 void *rqc_wq = MLX5_ADDR_OF(rqc, rqc, wq);
380 rqp->wq.db_numa_node = cpu_to_node(c->cpu);
382 rq->wq_type = params->rq_wq_type;
384 rq->netdev = c->netdev;
385 rq->tstamp = c->tstamp;
386 rq->clock = &mdev->clock;
390 rq->hw_mtu = MLX5E_SW2HW_MTU(params, params->sw_mtu);
391 rq->xdpsq = &c->rq_xdpsq;
395 rq->stats = &c->priv->channel_stats[c->ix].xskrq;
397 rq->stats = &c->priv->channel_stats[c->ix].rq;
398 INIT_WORK(&rq->recover_work, mlx5e_rq_err_cqe_work);
400 if (params->xdp_prog)
401 bpf_prog_inc(params->xdp_prog);
402 rq->xdp_prog = params->xdp_prog;
406 rq_xdp_ix += params->num_channels * MLX5E_RQ_GROUP_XSK;
407 err = xdp_rxq_info_reg(&rq->xdp_rxq, rq->netdev, rq_xdp_ix);
409 goto err_rq_wq_destroy;
411 rq->buff.map_dir = rq->xdp_prog ? DMA_BIDIRECTIONAL : DMA_FROM_DEVICE;
412 rq->buff.headroom = mlx5e_get_rq_headroom(mdev, params, xsk);
413 pool_size = 1 << params->log_rq_mtu_frames;
415 switch (rq->wq_type) {
416 case MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ:
417 err = mlx5_wq_ll_create(mdev, &rqp->wq, rqc_wq, &rq->mpwqe.wq,
422 rq->mpwqe.wq.db = &rq->mpwqe.wq.db[MLX5_RCV_DBR];
424 wq_sz = mlx5_wq_ll_get_size(&rq->mpwqe.wq);
426 pool_size = MLX5_MPWRQ_PAGES_PER_WQE <<
427 mlx5e_mpwqe_get_log_rq_size(params, xsk);
429 rq->mpwqe.log_stride_sz = mlx5e_mpwqe_get_log_stride_size(mdev, params, xsk);
430 rq->mpwqe.num_strides =
431 BIT(mlx5e_mpwqe_get_log_num_strides(mdev, params, xsk));
433 rq->buff.frame0_sz = (1 << rq->mpwqe.log_stride_sz);
435 err = mlx5e_create_rq_umr_mkey(mdev, rq);
437 goto err_rq_wq_destroy;
438 rq->mkey_be = cpu_to_be32(rq->umr_mkey.key);
440 err = mlx5e_rq_alloc_mpwqe_info(rq, c);
444 default: /* MLX5_WQ_TYPE_CYCLIC */
445 err = mlx5_wq_cyc_create(mdev, &rqp->wq, rqc_wq, &rq->wqe.wq,
450 rq->wqe.wq.db = &rq->wqe.wq.db[MLX5_RCV_DBR];
452 wq_sz = mlx5_wq_cyc_get_size(&rq->wqe.wq);
454 rq->wqe.info = rqp->frags_info;
455 rq->buff.frame0_sz = rq->wqe.info.arr[0].frag_stride;
458 kvzalloc_node(array_size(sizeof(*rq->wqe.frags),
459 (wq_sz << rq->wqe.info.log_num_frags)),
460 GFP_KERNEL, cpu_to_node(c->cpu));
461 if (!rq->wqe.frags) {
466 err = mlx5e_init_di_list(rq, wq_sz, c->cpu);
470 rq->mkey_be = c->mkey_be;
473 err = mlx5e_rq_set_handlers(rq, params, xsk);
478 err = xdp_rxq_info_reg_mem_model(&rq->xdp_rxq,
479 MEM_TYPE_XSK_BUFF_POOL, NULL);
480 xsk_buff_set_rxq_info(rq->umem, &rq->xdp_rxq);
482 /* Create a page_pool and register it with rxq */
484 pp_params.flags = 0; /* No-internal DMA mapping in page_pool */
485 pp_params.pool_size = pool_size;
486 pp_params.nid = cpu_to_node(c->cpu);
487 pp_params.dev = c->pdev;
488 pp_params.dma_dir = rq->buff.map_dir;
490 /* page_pool can be used even when there is no rq->xdp_prog,
491 * given page_pool does not handle DMA mapping there is no
492 * required state to clear. And page_pool gracefully handle
495 rq->page_pool = page_pool_create(&pp_params);
496 if (IS_ERR(rq->page_pool)) {
497 err = PTR_ERR(rq->page_pool);
498 rq->page_pool = NULL;
501 err = xdp_rxq_info_reg_mem_model(&rq->xdp_rxq,
502 MEM_TYPE_PAGE_POOL, rq->page_pool);
507 for (i = 0; i < wq_sz; i++) {
508 if (rq->wq_type == MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ) {
509 struct mlx5e_rx_wqe_ll *wqe =
510 mlx5_wq_ll_get_wqe(&rq->mpwqe.wq, i);
512 rq->mpwqe.num_strides << rq->mpwqe.log_stride_sz;
513 u64 dma_offset = mlx5e_get_mpwqe_offset(rq, i);
515 wqe->data[0].addr = cpu_to_be64(dma_offset + rq->buff.headroom);
516 wqe->data[0].byte_count = cpu_to_be32(byte_count);
517 wqe->data[0].lkey = rq->mkey_be;
519 struct mlx5e_rx_wqe_cyc *wqe =
520 mlx5_wq_cyc_get_wqe(&rq->wqe.wq, i);
523 for (f = 0; f < rq->wqe.info.num_frags; f++) {
524 u32 frag_size = rq->wqe.info.arr[f].frag_size |
525 MLX5_HW_START_PADDING;
527 wqe->data[f].byte_count = cpu_to_be32(frag_size);
528 wqe->data[f].lkey = rq->mkey_be;
530 /* check if num_frags is not a pow of two */
531 if (rq->wqe.info.num_frags < (1 << rq->wqe.info.log_num_frags)) {
532 wqe->data[f].byte_count = 0;
533 wqe->data[f].lkey = cpu_to_be32(MLX5_INVALID_LKEY);
534 wqe->data[f].addr = 0;
539 INIT_WORK(&rq->dim.work, mlx5e_rx_dim_work);
541 switch (params->rx_cq_moderation.cq_period_mode) {
542 case MLX5_CQ_PERIOD_MODE_START_FROM_CQE:
543 rq->dim.mode = DIM_CQ_PERIOD_MODE_START_FROM_CQE;
545 case MLX5_CQ_PERIOD_MODE_START_FROM_EQE:
547 rq->dim.mode = DIM_CQ_PERIOD_MODE_START_FROM_EQE;
550 rq->page_cache.head = 0;
551 rq->page_cache.tail = 0;
556 switch (rq->wq_type) {
557 case MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ:
558 kvfree(rq->mpwqe.info);
559 mlx5_core_destroy_mkey(mdev, &rq->umr_mkey);
561 default: /* MLX5_WQ_TYPE_CYCLIC */
562 kvfree(rq->wqe.frags);
563 mlx5e_free_di_list(rq);
568 bpf_prog_put(rq->xdp_prog);
569 xdp_rxq_info_unreg(&rq->xdp_rxq);
570 page_pool_destroy(rq->page_pool);
571 mlx5_wq_destroy(&rq->wq_ctrl);
576 static void mlx5e_free_rq(struct mlx5e_rq *rq)
581 bpf_prog_put(rq->xdp_prog);
583 switch (rq->wq_type) {
584 case MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ:
585 kvfree(rq->mpwqe.info);
586 mlx5_core_destroy_mkey(rq->mdev, &rq->umr_mkey);
588 default: /* MLX5_WQ_TYPE_CYCLIC */
589 kvfree(rq->wqe.frags);
590 mlx5e_free_di_list(rq);
593 for (i = rq->page_cache.head; i != rq->page_cache.tail;
594 i = (i + 1) & (MLX5E_CACHE_SIZE - 1)) {
595 struct mlx5e_dma_info *dma_info = &rq->page_cache.page_cache[i];
597 /* With AF_XDP, page_cache is not used, so this loop is not
598 * entered, and it's safe to call mlx5e_page_release_dynamic
601 mlx5e_page_release_dynamic(rq, dma_info, false);
604 xdp_rxq_info_unreg(&rq->xdp_rxq);
605 page_pool_destroy(rq->page_pool);
606 mlx5_wq_destroy(&rq->wq_ctrl);
609 static int mlx5e_create_rq(struct mlx5e_rq *rq,
610 struct mlx5e_rq_param *param)
612 struct mlx5_core_dev *mdev = rq->mdev;
620 inlen = MLX5_ST_SZ_BYTES(create_rq_in) +
621 sizeof(u64) * rq->wq_ctrl.buf.npages;
622 in = kvzalloc(inlen, GFP_KERNEL);
626 rqc = MLX5_ADDR_OF(create_rq_in, in, ctx);
627 wq = MLX5_ADDR_OF(rqc, rqc, wq);
629 memcpy(rqc, param->rqc, sizeof(param->rqc));
631 MLX5_SET(rqc, rqc, cqn, rq->cq.mcq.cqn);
632 MLX5_SET(rqc, rqc, state, MLX5_RQC_STATE_RST);
633 MLX5_SET(wq, wq, log_wq_pg_sz, rq->wq_ctrl.buf.page_shift -
634 MLX5_ADAPTER_PAGE_SHIFT);
635 MLX5_SET64(wq, wq, dbr_addr, rq->wq_ctrl.db.dma);
637 mlx5_fill_page_frag_array(&rq->wq_ctrl.buf,
638 (__be64 *)MLX5_ADDR_OF(wq, wq, pas));
640 err = mlx5_core_create_rq(mdev, in, inlen, &rq->rqn);
647 int mlx5e_modify_rq_state(struct mlx5e_rq *rq, int curr_state, int next_state)
649 struct mlx5_core_dev *mdev = rq->mdev;
656 inlen = MLX5_ST_SZ_BYTES(modify_rq_in);
657 in = kvzalloc(inlen, GFP_KERNEL);
661 if (curr_state == MLX5_RQC_STATE_RST && next_state == MLX5_RQC_STATE_RDY)
662 mlx5e_rqwq_reset(rq);
664 rqc = MLX5_ADDR_OF(modify_rq_in, in, ctx);
666 MLX5_SET(modify_rq_in, in, rq_state, curr_state);
667 MLX5_SET(rqc, rqc, state, next_state);
669 err = mlx5_core_modify_rq(mdev, rq->rqn, in);
676 static int mlx5e_modify_rq_scatter_fcs(struct mlx5e_rq *rq, bool enable)
678 struct mlx5e_channel *c = rq->channel;
679 struct mlx5e_priv *priv = c->priv;
680 struct mlx5_core_dev *mdev = priv->mdev;
687 inlen = MLX5_ST_SZ_BYTES(modify_rq_in);
688 in = kvzalloc(inlen, GFP_KERNEL);
692 rqc = MLX5_ADDR_OF(modify_rq_in, in, ctx);
694 MLX5_SET(modify_rq_in, in, rq_state, MLX5_RQC_STATE_RDY);
695 MLX5_SET64(modify_rq_in, in, modify_bitmask,
696 MLX5_MODIFY_RQ_IN_MODIFY_BITMASK_SCATTER_FCS);
697 MLX5_SET(rqc, rqc, scatter_fcs, enable);
698 MLX5_SET(rqc, rqc, state, MLX5_RQC_STATE_RDY);
700 err = mlx5_core_modify_rq(mdev, rq->rqn, in);
707 static int mlx5e_modify_rq_vsd(struct mlx5e_rq *rq, bool vsd)
709 struct mlx5e_channel *c = rq->channel;
710 struct mlx5_core_dev *mdev = c->mdev;
716 inlen = MLX5_ST_SZ_BYTES(modify_rq_in);
717 in = kvzalloc(inlen, GFP_KERNEL);
721 rqc = MLX5_ADDR_OF(modify_rq_in, in, ctx);
723 MLX5_SET(modify_rq_in, in, rq_state, MLX5_RQC_STATE_RDY);
724 MLX5_SET64(modify_rq_in, in, modify_bitmask,
725 MLX5_MODIFY_RQ_IN_MODIFY_BITMASK_VSD);
726 MLX5_SET(rqc, rqc, vsd, vsd);
727 MLX5_SET(rqc, rqc, state, MLX5_RQC_STATE_RDY);
729 err = mlx5_core_modify_rq(mdev, rq->rqn, in);
736 static void mlx5e_destroy_rq(struct mlx5e_rq *rq)
738 mlx5_core_destroy_rq(rq->mdev, rq->rqn);
741 int mlx5e_wait_for_min_rx_wqes(struct mlx5e_rq *rq, int wait_time)
743 unsigned long exp_time = jiffies + msecs_to_jiffies(wait_time);
744 struct mlx5e_channel *c = rq->channel;
746 u16 min_wqes = mlx5_min_rx_wqes(rq->wq_type, mlx5e_rqwq_get_size(rq));
749 if (mlx5e_rqwq_get_cur_sz(rq) >= min_wqes)
753 } while (time_before(jiffies, exp_time));
755 netdev_warn(c->netdev, "Failed to get min RX wqes on Channel[%d] RQN[0x%x] wq cur_sz(%d) min_rx_wqes(%d)\n",
756 c->ix, rq->rqn, mlx5e_rqwq_get_cur_sz(rq), min_wqes);
758 mlx5e_reporter_rx_timeout(rq);
762 void mlx5e_free_rx_in_progress_descs(struct mlx5e_rq *rq)
764 struct mlx5_wq_ll *wq;
768 if (rq->wq_type != MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ)
774 /* Outstanding UMR WQEs (in progress) start at wq->head */
775 for (i = 0; i < rq->mpwqe.umr_in_progress; i++) {
776 rq->dealloc_wqe(rq, head);
777 head = mlx5_wq_ll_get_wqe_next_ix(wq, head);
780 rq->mpwqe.actual_wq_head = wq->head;
781 rq->mpwqe.umr_in_progress = 0;
782 rq->mpwqe.umr_completed = 0;
785 void mlx5e_free_rx_descs(struct mlx5e_rq *rq)
790 if (rq->wq_type == MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ) {
791 struct mlx5_wq_ll *wq = &rq->mpwqe.wq;
793 mlx5e_free_rx_in_progress_descs(rq);
795 while (!mlx5_wq_ll_is_empty(wq)) {
796 struct mlx5e_rx_wqe_ll *wqe;
798 wqe_ix_be = *wq->tail_next;
799 wqe_ix = be16_to_cpu(wqe_ix_be);
800 wqe = mlx5_wq_ll_get_wqe(wq, wqe_ix);
801 rq->dealloc_wqe(rq, wqe_ix);
802 mlx5_wq_ll_pop(wq, wqe_ix_be,
803 &wqe->next.next_wqe_index);
806 struct mlx5_wq_cyc *wq = &rq->wqe.wq;
808 while (!mlx5_wq_cyc_is_empty(wq)) {
809 wqe_ix = mlx5_wq_cyc_get_tail(wq);
810 rq->dealloc_wqe(rq, wqe_ix);
817 int mlx5e_open_rq(struct mlx5e_channel *c, struct mlx5e_params *params,
818 struct mlx5e_rq_param *param, struct mlx5e_xsk_param *xsk,
819 struct xdp_umem *umem, struct mlx5e_rq *rq)
823 err = mlx5e_alloc_rq(c, params, xsk, umem, param, rq);
827 err = mlx5e_create_rq(rq, param);
831 err = mlx5e_modify_rq_state(rq, MLX5_RQC_STATE_RST, MLX5_RQC_STATE_RDY);
835 if (mlx5e_is_tls_on(c->priv) && !mlx5_accel_is_ktls_device(c->mdev))
836 __set_bit(MLX5E_RQ_STATE_FPGA_TLS, &c->rq.state); /* must be FPGA */
838 if (MLX5_CAP_ETH(c->mdev, cqe_checksum_full))
839 __set_bit(MLX5E_RQ_STATE_CSUM_FULL, &c->rq.state);
841 if (params->rx_dim_enabled)
842 __set_bit(MLX5E_RQ_STATE_AM, &c->rq.state);
844 /* We disable csum_complete when XDP is enabled since
845 * XDP programs might manipulate packets which will render
846 * skb->checksum incorrect.
848 if (MLX5E_GET_PFLAG(params, MLX5E_PFLAG_RX_NO_CSUM_COMPLETE) || c->xdp)
849 __set_bit(MLX5E_RQ_STATE_NO_CSUM_COMPLETE, &c->rq.state);
854 mlx5e_destroy_rq(rq);
861 void mlx5e_activate_rq(struct mlx5e_rq *rq)
863 set_bit(MLX5E_RQ_STATE_ENABLED, &rq->state);
864 mlx5e_trigger_irq(&rq->channel->icosq);
867 void mlx5e_deactivate_rq(struct mlx5e_rq *rq)
869 clear_bit(MLX5E_RQ_STATE_ENABLED, &rq->state);
870 napi_synchronize(&rq->channel->napi); /* prevent mlx5e_post_rx_wqes */
873 void mlx5e_close_rq(struct mlx5e_rq *rq)
875 cancel_work_sync(&rq->dim.work);
876 cancel_work_sync(&rq->channel->icosq.recover_work);
877 cancel_work_sync(&rq->recover_work);
878 mlx5e_destroy_rq(rq);
879 mlx5e_free_rx_descs(rq);
883 static void mlx5e_free_xdpsq_db(struct mlx5e_xdpsq *sq)
885 kvfree(sq->db.xdpi_fifo.xi);
886 kvfree(sq->db.wqe_info);
889 static int mlx5e_alloc_xdpsq_fifo(struct mlx5e_xdpsq *sq, int numa)
891 struct mlx5e_xdp_info_fifo *xdpi_fifo = &sq->db.xdpi_fifo;
892 int wq_sz = mlx5_wq_cyc_get_size(&sq->wq);
893 int dsegs_per_wq = wq_sz * MLX5_SEND_WQEBB_NUM_DS;
895 xdpi_fifo->xi = kvzalloc_node(sizeof(*xdpi_fifo->xi) * dsegs_per_wq,
900 xdpi_fifo->pc = &sq->xdpi_fifo_pc;
901 xdpi_fifo->cc = &sq->xdpi_fifo_cc;
902 xdpi_fifo->mask = dsegs_per_wq - 1;
907 static int mlx5e_alloc_xdpsq_db(struct mlx5e_xdpsq *sq, int numa)
909 int wq_sz = mlx5_wq_cyc_get_size(&sq->wq);
912 sq->db.wqe_info = kvzalloc_node(sizeof(*sq->db.wqe_info) * wq_sz,
914 if (!sq->db.wqe_info)
917 err = mlx5e_alloc_xdpsq_fifo(sq, numa);
919 mlx5e_free_xdpsq_db(sq);
926 static int mlx5e_alloc_xdpsq(struct mlx5e_channel *c,
927 struct mlx5e_params *params,
928 struct xdp_umem *umem,
929 struct mlx5e_sq_param *param,
930 struct mlx5e_xdpsq *sq,
933 void *sqc_wq = MLX5_ADDR_OF(sqc, param->sqc, wq);
934 struct mlx5_core_dev *mdev = c->mdev;
935 struct mlx5_wq_cyc *wq = &sq->wq;
939 sq->mkey_be = c->mkey_be;
941 sq->uar_map = mdev->mlx5e_res.bfreg.map;
942 sq->min_inline_mode = params->tx_min_inline_mode;
943 sq->hw_mtu = MLX5E_SW2HW_MTU(params, params->sw_mtu);
946 sq->stats = sq->umem ?
947 &c->priv->channel_stats[c->ix].xsksq :
949 &c->priv->channel_stats[c->ix].xdpsq :
950 &c->priv->channel_stats[c->ix].rq_xdpsq;
952 param->wq.db_numa_node = cpu_to_node(c->cpu);
953 err = mlx5_wq_cyc_create(mdev, ¶m->wq, sqc_wq, wq, &sq->wq_ctrl);
956 wq->db = &wq->db[MLX5_SND_DBR];
958 err = mlx5e_alloc_xdpsq_db(sq, cpu_to_node(c->cpu));
960 goto err_sq_wq_destroy;
965 mlx5_wq_destroy(&sq->wq_ctrl);
970 static void mlx5e_free_xdpsq(struct mlx5e_xdpsq *sq)
972 mlx5e_free_xdpsq_db(sq);
973 mlx5_wq_destroy(&sq->wq_ctrl);
976 static void mlx5e_free_icosq_db(struct mlx5e_icosq *sq)
978 kvfree(sq->db.wqe_info);
981 static int mlx5e_alloc_icosq_db(struct mlx5e_icosq *sq, int numa)
983 int wq_sz = mlx5_wq_cyc_get_size(&sq->wq);
986 size = array_size(wq_sz, sizeof(*sq->db.wqe_info));
987 sq->db.wqe_info = kvzalloc_node(size, GFP_KERNEL, numa);
988 if (!sq->db.wqe_info)
994 static void mlx5e_icosq_err_cqe_work(struct work_struct *recover_work)
996 struct mlx5e_icosq *sq = container_of(recover_work, struct mlx5e_icosq,
999 mlx5e_reporter_icosq_cqe_err(sq);
1002 static int mlx5e_alloc_icosq(struct mlx5e_channel *c,
1003 struct mlx5e_sq_param *param,
1004 struct mlx5e_icosq *sq)
1006 void *sqc_wq = MLX5_ADDR_OF(sqc, param->sqc, wq);
1007 struct mlx5_core_dev *mdev = c->mdev;
1008 struct mlx5_wq_cyc *wq = &sq->wq;
1012 sq->uar_map = mdev->mlx5e_res.bfreg.map;
1014 param->wq.db_numa_node = cpu_to_node(c->cpu);
1015 err = mlx5_wq_cyc_create(mdev, ¶m->wq, sqc_wq, wq, &sq->wq_ctrl);
1018 wq->db = &wq->db[MLX5_SND_DBR];
1020 err = mlx5e_alloc_icosq_db(sq, cpu_to_node(c->cpu));
1022 goto err_sq_wq_destroy;
1024 INIT_WORK(&sq->recover_work, mlx5e_icosq_err_cqe_work);
1029 mlx5_wq_destroy(&sq->wq_ctrl);
1034 static void mlx5e_free_icosq(struct mlx5e_icosq *sq)
1036 mlx5e_free_icosq_db(sq);
1037 mlx5_wq_destroy(&sq->wq_ctrl);
1040 static void mlx5e_free_txqsq_db(struct mlx5e_txqsq *sq)
1042 kvfree(sq->db.wqe_info);
1043 kvfree(sq->db.dma_fifo);
1046 static int mlx5e_alloc_txqsq_db(struct mlx5e_txqsq *sq, int numa)
1048 int wq_sz = mlx5_wq_cyc_get_size(&sq->wq);
1049 int df_sz = wq_sz * MLX5_SEND_WQEBB_NUM_DS;
1051 sq->db.dma_fifo = kvzalloc_node(array_size(df_sz,
1052 sizeof(*sq->db.dma_fifo)),
1054 sq->db.wqe_info = kvzalloc_node(array_size(wq_sz,
1055 sizeof(*sq->db.wqe_info)),
1057 if (!sq->db.dma_fifo || !sq->db.wqe_info) {
1058 mlx5e_free_txqsq_db(sq);
1062 sq->dma_fifo_mask = df_sz - 1;
1067 static int mlx5e_calc_sq_stop_room(struct mlx5e_txqsq *sq, u8 log_sq_size)
1069 int sq_size = 1 << log_sq_size;
1071 sq->stop_room = mlx5e_tls_get_stop_room(sq);
1072 sq->stop_room += mlx5e_stop_room_for_wqe(MLX5_SEND_WQE_MAX_WQEBBS);
1074 if (WARN_ON(sq->stop_room >= sq_size)) {
1075 netdev_err(sq->channel->netdev, "Stop room %hu is bigger than the SQ size %d\n",
1076 sq->stop_room, sq_size);
1083 static void mlx5e_tx_err_cqe_work(struct work_struct *recover_work);
1084 static int mlx5e_alloc_txqsq(struct mlx5e_channel *c,
1086 struct mlx5e_params *params,
1087 struct mlx5e_sq_param *param,
1088 struct mlx5e_txqsq *sq,
1091 void *sqc_wq = MLX5_ADDR_OF(sqc, param->sqc, wq);
1092 struct mlx5_core_dev *mdev = c->mdev;
1093 struct mlx5_wq_cyc *wq = &sq->wq;
1097 sq->tstamp = c->tstamp;
1098 sq->clock = &mdev->clock;
1099 sq->mkey_be = c->mkey_be;
1102 sq->txq_ix = txq_ix;
1103 sq->uar_map = mdev->mlx5e_res.bfreg.map;
1104 sq->min_inline_mode = params->tx_min_inline_mode;
1105 sq->hw_mtu = MLX5E_SW2HW_MTU(params, params->sw_mtu);
1106 sq->stats = &c->priv->channel_stats[c->ix].sq[tc];
1107 INIT_WORK(&sq->recover_work, mlx5e_tx_err_cqe_work);
1108 if (!MLX5_CAP_ETH(mdev, wqe_vlan_insert))
1109 set_bit(MLX5E_SQ_STATE_VLAN_NEED_L2_INLINE, &sq->state);
1110 if (MLX5_IPSEC_DEV(c->priv->mdev))
1111 set_bit(MLX5E_SQ_STATE_IPSEC, &sq->state);
1112 if (mlx5_accel_is_tls_device(c->priv->mdev))
1113 set_bit(MLX5E_SQ_STATE_TLS, &sq->state);
1114 err = mlx5e_calc_sq_stop_room(sq, params->log_sq_size);
1118 param->wq.db_numa_node = cpu_to_node(c->cpu);
1119 err = mlx5_wq_cyc_create(mdev, ¶m->wq, sqc_wq, wq, &sq->wq_ctrl);
1122 wq->db = &wq->db[MLX5_SND_DBR];
1124 err = mlx5e_alloc_txqsq_db(sq, cpu_to_node(c->cpu));
1126 goto err_sq_wq_destroy;
1128 INIT_WORK(&sq->dim.work, mlx5e_tx_dim_work);
1129 sq->dim.mode = params->tx_cq_moderation.cq_period_mode;
1134 mlx5_wq_destroy(&sq->wq_ctrl);
1139 static void mlx5e_free_txqsq(struct mlx5e_txqsq *sq)
1141 mlx5e_free_txqsq_db(sq);
1142 mlx5_wq_destroy(&sq->wq_ctrl);
1145 struct mlx5e_create_sq_param {
1146 struct mlx5_wq_ctrl *wq_ctrl;
1153 static int mlx5e_create_sq(struct mlx5_core_dev *mdev,
1154 struct mlx5e_sq_param *param,
1155 struct mlx5e_create_sq_param *csp,
1164 inlen = MLX5_ST_SZ_BYTES(create_sq_in) +
1165 sizeof(u64) * csp->wq_ctrl->buf.npages;
1166 in = kvzalloc(inlen, GFP_KERNEL);
1170 sqc = MLX5_ADDR_OF(create_sq_in, in, ctx);
1171 wq = MLX5_ADDR_OF(sqc, sqc, wq);
1173 memcpy(sqc, param->sqc, sizeof(param->sqc));
1174 MLX5_SET(sqc, sqc, tis_lst_sz, csp->tis_lst_sz);
1175 MLX5_SET(sqc, sqc, tis_num_0, csp->tisn);
1176 MLX5_SET(sqc, sqc, cqn, csp->cqn);
1178 if (MLX5_CAP_ETH(mdev, wqe_inline_mode) == MLX5_CAP_INLINE_MODE_VPORT_CONTEXT)
1179 MLX5_SET(sqc, sqc, min_wqe_inline_mode, csp->min_inline_mode);
1181 MLX5_SET(sqc, sqc, state, MLX5_SQC_STATE_RST);
1182 MLX5_SET(sqc, sqc, flush_in_error_en, 1);
1184 MLX5_SET(wq, wq, wq_type, MLX5_WQ_TYPE_CYCLIC);
1185 MLX5_SET(wq, wq, uar_page, mdev->mlx5e_res.bfreg.index);
1186 MLX5_SET(wq, wq, log_wq_pg_sz, csp->wq_ctrl->buf.page_shift -
1187 MLX5_ADAPTER_PAGE_SHIFT);
1188 MLX5_SET64(wq, wq, dbr_addr, csp->wq_ctrl->db.dma);
1190 mlx5_fill_page_frag_array(&csp->wq_ctrl->buf,
1191 (__be64 *)MLX5_ADDR_OF(wq, wq, pas));
1193 err = mlx5_core_create_sq(mdev, in, inlen, sqn);
1200 int mlx5e_modify_sq(struct mlx5_core_dev *mdev, u32 sqn,
1201 struct mlx5e_modify_sq_param *p)
1208 inlen = MLX5_ST_SZ_BYTES(modify_sq_in);
1209 in = kvzalloc(inlen, GFP_KERNEL);
1213 sqc = MLX5_ADDR_OF(modify_sq_in, in, ctx);
1215 MLX5_SET(modify_sq_in, in, sq_state, p->curr_state);
1216 MLX5_SET(sqc, sqc, state, p->next_state);
1217 if (p->rl_update && p->next_state == MLX5_SQC_STATE_RDY) {
1218 MLX5_SET64(modify_sq_in, in, modify_bitmask, 1);
1219 MLX5_SET(sqc, sqc, packet_pacing_rate_limit_index, p->rl_index);
1222 err = mlx5_core_modify_sq(mdev, sqn, in);
1229 static void mlx5e_destroy_sq(struct mlx5_core_dev *mdev, u32 sqn)
1231 mlx5_core_destroy_sq(mdev, sqn);
1234 static int mlx5e_create_sq_rdy(struct mlx5_core_dev *mdev,
1235 struct mlx5e_sq_param *param,
1236 struct mlx5e_create_sq_param *csp,
1239 struct mlx5e_modify_sq_param msp = {0};
1242 err = mlx5e_create_sq(mdev, param, csp, sqn);
1246 msp.curr_state = MLX5_SQC_STATE_RST;
1247 msp.next_state = MLX5_SQC_STATE_RDY;
1248 err = mlx5e_modify_sq(mdev, *sqn, &msp);
1250 mlx5e_destroy_sq(mdev, *sqn);
1255 static int mlx5e_set_sq_maxrate(struct net_device *dev,
1256 struct mlx5e_txqsq *sq, u32 rate);
1258 static int mlx5e_open_txqsq(struct mlx5e_channel *c,
1261 struct mlx5e_params *params,
1262 struct mlx5e_sq_param *param,
1263 struct mlx5e_txqsq *sq,
1266 struct mlx5e_create_sq_param csp = {};
1270 err = mlx5e_alloc_txqsq(c, txq_ix, params, param, sq, tc);
1276 csp.cqn = sq->cq.mcq.cqn;
1277 csp.wq_ctrl = &sq->wq_ctrl;
1278 csp.min_inline_mode = sq->min_inline_mode;
1279 err = mlx5e_create_sq_rdy(c->mdev, param, &csp, &sq->sqn);
1281 goto err_free_txqsq;
1283 tx_rate = c->priv->tx_rates[sq->txq_ix];
1285 mlx5e_set_sq_maxrate(c->netdev, sq, tx_rate);
1287 if (params->tx_dim_enabled)
1288 sq->state |= BIT(MLX5E_SQ_STATE_AM);
1293 mlx5e_free_txqsq(sq);
1298 void mlx5e_activate_txqsq(struct mlx5e_txqsq *sq)
1300 sq->txq = netdev_get_tx_queue(sq->channel->netdev, sq->txq_ix);
1301 set_bit(MLX5E_SQ_STATE_ENABLED, &sq->state);
1302 netdev_tx_reset_queue(sq->txq);
1303 netif_tx_start_queue(sq->txq);
1306 void mlx5e_tx_disable_queue(struct netdev_queue *txq)
1308 __netif_tx_lock_bh(txq);
1309 netif_tx_stop_queue(txq);
1310 __netif_tx_unlock_bh(txq);
1313 static void mlx5e_deactivate_txqsq(struct mlx5e_txqsq *sq)
1315 struct mlx5e_channel *c = sq->channel;
1316 struct mlx5_wq_cyc *wq = &sq->wq;
1318 clear_bit(MLX5E_SQ_STATE_ENABLED, &sq->state);
1319 /* prevent netif_tx_wake_queue */
1320 napi_synchronize(&c->napi);
1322 mlx5e_tx_disable_queue(sq->txq);
1324 /* last doorbell out, godspeed .. */
1325 if (mlx5e_wqc_has_room_for(wq, sq->cc, sq->pc, 1)) {
1326 u16 pi = mlx5_wq_cyc_ctr2ix(wq, sq->pc);
1327 struct mlx5e_tx_wqe *nop;
1329 sq->db.wqe_info[pi] = (struct mlx5e_tx_wqe_info) {
1333 nop = mlx5e_post_nop(wq, sq->sqn, &sq->pc);
1334 mlx5e_notify_hw(wq, sq->pc, sq->uar_map, &nop->ctrl);
1338 static void mlx5e_close_txqsq(struct mlx5e_txqsq *sq)
1340 struct mlx5e_channel *c = sq->channel;
1341 struct mlx5_core_dev *mdev = c->mdev;
1342 struct mlx5_rate_limit rl = {0};
1344 cancel_work_sync(&sq->dim.work);
1345 cancel_work_sync(&sq->recover_work);
1346 mlx5e_destroy_sq(mdev, sq->sqn);
1347 if (sq->rate_limit) {
1348 rl.rate = sq->rate_limit;
1349 mlx5_rl_remove_rate(mdev, &rl);
1351 mlx5e_free_txqsq_descs(sq);
1352 mlx5e_free_txqsq(sq);
1355 static void mlx5e_tx_err_cqe_work(struct work_struct *recover_work)
1357 struct mlx5e_txqsq *sq = container_of(recover_work, struct mlx5e_txqsq,
1360 mlx5e_reporter_tx_err_cqe(sq);
1363 int mlx5e_open_icosq(struct mlx5e_channel *c, struct mlx5e_params *params,
1364 struct mlx5e_sq_param *param, struct mlx5e_icosq *sq)
1366 struct mlx5e_create_sq_param csp = {};
1369 err = mlx5e_alloc_icosq(c, param, sq);
1373 csp.cqn = sq->cq.mcq.cqn;
1374 csp.wq_ctrl = &sq->wq_ctrl;
1375 csp.min_inline_mode = params->tx_min_inline_mode;
1376 err = mlx5e_create_sq_rdy(c->mdev, param, &csp, &sq->sqn);
1378 goto err_free_icosq;
1383 mlx5e_free_icosq(sq);
1388 void mlx5e_activate_icosq(struct mlx5e_icosq *icosq)
1390 set_bit(MLX5E_SQ_STATE_ENABLED, &icosq->state);
1393 void mlx5e_deactivate_icosq(struct mlx5e_icosq *icosq)
1395 struct mlx5e_channel *c = icosq->channel;
1397 clear_bit(MLX5E_SQ_STATE_ENABLED, &icosq->state);
1398 napi_synchronize(&c->napi);
1401 void mlx5e_close_icosq(struct mlx5e_icosq *sq)
1403 struct mlx5e_channel *c = sq->channel;
1405 mlx5e_destroy_sq(c->mdev, sq->sqn);
1406 mlx5e_free_icosq_descs(sq);
1407 mlx5e_free_icosq(sq);
1410 int mlx5e_open_xdpsq(struct mlx5e_channel *c, struct mlx5e_params *params,
1411 struct mlx5e_sq_param *param, struct xdp_umem *umem,
1412 struct mlx5e_xdpsq *sq, bool is_redirect)
1414 struct mlx5e_create_sq_param csp = {};
1417 err = mlx5e_alloc_xdpsq(c, params, umem, param, sq, is_redirect);
1422 csp.tisn = c->priv->tisn[c->lag_port][0]; /* tc = 0 */
1423 csp.cqn = sq->cq.mcq.cqn;
1424 csp.wq_ctrl = &sq->wq_ctrl;
1425 csp.min_inline_mode = sq->min_inline_mode;
1426 set_bit(MLX5E_SQ_STATE_ENABLED, &sq->state);
1427 err = mlx5e_create_sq_rdy(c->mdev, param, &csp, &sq->sqn);
1429 goto err_free_xdpsq;
1431 mlx5e_set_xmit_fp(sq, param->is_mpw);
1433 if (!param->is_mpw) {
1434 unsigned int ds_cnt = MLX5E_XDP_TX_DS_COUNT;
1435 unsigned int inline_hdr_sz = 0;
1438 if (sq->min_inline_mode != MLX5_INLINE_MODE_NONE) {
1439 inline_hdr_sz = MLX5E_XDP_MIN_INLINE;
1443 /* Pre initialize fixed WQE fields */
1444 for (i = 0; i < mlx5_wq_cyc_get_size(&sq->wq); i++) {
1445 struct mlx5e_tx_wqe *wqe = mlx5_wq_cyc_get_wqe(&sq->wq, i);
1446 struct mlx5_wqe_ctrl_seg *cseg = &wqe->ctrl;
1447 struct mlx5_wqe_eth_seg *eseg = &wqe->eth;
1448 struct mlx5_wqe_data_seg *dseg;
1450 sq->db.wqe_info[i] = (struct mlx5e_xdp_wqe_info) {
1455 cseg->qpn_ds = cpu_to_be32((sq->sqn << 8) | ds_cnt);
1456 eseg->inline_hdr.sz = cpu_to_be16(inline_hdr_sz);
1458 dseg = (struct mlx5_wqe_data_seg *)cseg + (ds_cnt - 1);
1459 dseg->lkey = sq->mkey_be;
1466 clear_bit(MLX5E_SQ_STATE_ENABLED, &sq->state);
1467 mlx5e_free_xdpsq(sq);
1472 void mlx5e_close_xdpsq(struct mlx5e_xdpsq *sq)
1474 struct mlx5e_channel *c = sq->channel;
1476 clear_bit(MLX5E_SQ_STATE_ENABLED, &sq->state);
1477 napi_synchronize(&c->napi);
1479 mlx5e_destroy_sq(c->mdev, sq->sqn);
1480 mlx5e_free_xdpsq_descs(sq);
1481 mlx5e_free_xdpsq(sq);
1484 static int mlx5e_alloc_cq_common(struct mlx5_core_dev *mdev,
1485 struct mlx5e_cq_param *param,
1486 struct mlx5e_cq *cq)
1488 struct mlx5_core_cq *mcq = &cq->mcq;
1494 err = mlx5_vector2eqn(mdev, param->eq_ix, &eqn_not_used, &irqn);
1498 err = mlx5_cqwq_create(mdev, ¶m->wq, param->cqc, &cq->wq,
1504 mcq->set_ci_db = cq->wq_ctrl.db.db;
1505 mcq->arm_db = cq->wq_ctrl.db.db + 1;
1506 *mcq->set_ci_db = 0;
1508 mcq->vector = param->eq_ix;
1509 mcq->comp = mlx5e_completion_event;
1510 mcq->event = mlx5e_cq_error_event;
1513 for (i = 0; i < mlx5_cqwq_get_size(&cq->wq); i++) {
1514 struct mlx5_cqe64 *cqe = mlx5_cqwq_get_wqe(&cq->wq, i);
1524 static int mlx5e_alloc_cq(struct mlx5e_channel *c,
1525 struct mlx5e_cq_param *param,
1526 struct mlx5e_cq *cq)
1528 struct mlx5_core_dev *mdev = c->priv->mdev;
1531 param->wq.buf_numa_node = cpu_to_node(c->cpu);
1532 param->wq.db_numa_node = cpu_to_node(c->cpu);
1533 param->eq_ix = c->ix;
1535 err = mlx5e_alloc_cq_common(mdev, param, cq);
1537 cq->napi = &c->napi;
1543 static void mlx5e_free_cq(struct mlx5e_cq *cq)
1545 mlx5_wq_destroy(&cq->wq_ctrl);
1548 static int mlx5e_create_cq(struct mlx5e_cq *cq, struct mlx5e_cq_param *param)
1550 u32 out[MLX5_ST_SZ_DW(create_cq_out)];
1551 struct mlx5_core_dev *mdev = cq->mdev;
1552 struct mlx5_core_cq *mcq = &cq->mcq;
1557 unsigned int irqn_not_used;
1561 err = mlx5_vector2eqn(mdev, param->eq_ix, &eqn, &irqn_not_used);
1565 inlen = MLX5_ST_SZ_BYTES(create_cq_in) +
1566 sizeof(u64) * cq->wq_ctrl.buf.npages;
1567 in = kvzalloc(inlen, GFP_KERNEL);
1571 cqc = MLX5_ADDR_OF(create_cq_in, in, cq_context);
1573 memcpy(cqc, param->cqc, sizeof(param->cqc));
1575 mlx5_fill_page_frag_array(&cq->wq_ctrl.buf,
1576 (__be64 *)MLX5_ADDR_OF(create_cq_in, in, pas));
1578 MLX5_SET(cqc, cqc, cq_period_mode, param->cq_period_mode);
1579 MLX5_SET(cqc, cqc, c_eqn, eqn);
1580 MLX5_SET(cqc, cqc, uar_page, mdev->priv.uar->index);
1581 MLX5_SET(cqc, cqc, log_page_size, cq->wq_ctrl.buf.page_shift -
1582 MLX5_ADAPTER_PAGE_SHIFT);
1583 MLX5_SET64(cqc, cqc, dbr_addr, cq->wq_ctrl.db.dma);
1585 err = mlx5_core_create_cq(mdev, mcq, in, inlen, out, sizeof(out));
1597 static void mlx5e_destroy_cq(struct mlx5e_cq *cq)
1599 mlx5_core_destroy_cq(cq->mdev, &cq->mcq);
1602 int mlx5e_open_cq(struct mlx5e_channel *c, struct dim_cq_moder moder,
1603 struct mlx5e_cq_param *param, struct mlx5e_cq *cq)
1605 struct mlx5_core_dev *mdev = c->mdev;
1608 err = mlx5e_alloc_cq(c, param, cq);
1612 err = mlx5e_create_cq(cq, param);
1616 if (MLX5_CAP_GEN(mdev, cq_moderation))
1617 mlx5_core_modify_cq_moderation(mdev, &cq->mcq, moder.usec, moder.pkts);
1626 void mlx5e_close_cq(struct mlx5e_cq *cq)
1628 mlx5e_destroy_cq(cq);
1632 static int mlx5e_open_tx_cqs(struct mlx5e_channel *c,
1633 struct mlx5e_params *params,
1634 struct mlx5e_channel_param *cparam)
1639 for (tc = 0; tc < c->num_tc; tc++) {
1640 err = mlx5e_open_cq(c, params->tx_cq_moderation,
1641 &cparam->txq_sq.cqp, &c->sq[tc].cq);
1643 goto err_close_tx_cqs;
1649 for (tc--; tc >= 0; tc--)
1650 mlx5e_close_cq(&c->sq[tc].cq);
1655 static void mlx5e_close_tx_cqs(struct mlx5e_channel *c)
1659 for (tc = 0; tc < c->num_tc; tc++)
1660 mlx5e_close_cq(&c->sq[tc].cq);
1663 static int mlx5e_open_sqs(struct mlx5e_channel *c,
1664 struct mlx5e_params *params,
1665 struct mlx5e_channel_param *cparam)
1669 for (tc = 0; tc < params->num_tc; tc++) {
1670 int txq_ix = c->ix + tc * params->num_channels;
1672 err = mlx5e_open_txqsq(c, c->priv->tisn[c->lag_port][tc], txq_ix,
1673 params, &cparam->txq_sq, &c->sq[tc], tc);
1681 for (tc--; tc >= 0; tc--)
1682 mlx5e_close_txqsq(&c->sq[tc]);
1687 static void mlx5e_close_sqs(struct mlx5e_channel *c)
1691 for (tc = 0; tc < c->num_tc; tc++)
1692 mlx5e_close_txqsq(&c->sq[tc]);
1695 static int mlx5e_set_sq_maxrate(struct net_device *dev,
1696 struct mlx5e_txqsq *sq, u32 rate)
1698 struct mlx5e_priv *priv = netdev_priv(dev);
1699 struct mlx5_core_dev *mdev = priv->mdev;
1700 struct mlx5e_modify_sq_param msp = {0};
1701 struct mlx5_rate_limit rl = {0};
1705 if (rate == sq->rate_limit)
1709 if (sq->rate_limit) {
1710 rl.rate = sq->rate_limit;
1711 /* remove current rl index to free space to next ones */
1712 mlx5_rl_remove_rate(mdev, &rl);
1719 err = mlx5_rl_add_rate(mdev, &rl_index, &rl);
1721 netdev_err(dev, "Failed configuring rate %u: %d\n",
1727 msp.curr_state = MLX5_SQC_STATE_RDY;
1728 msp.next_state = MLX5_SQC_STATE_RDY;
1729 msp.rl_index = rl_index;
1730 msp.rl_update = true;
1731 err = mlx5e_modify_sq(mdev, sq->sqn, &msp);
1733 netdev_err(dev, "Failed configuring rate %u: %d\n",
1735 /* remove the rate from the table */
1737 mlx5_rl_remove_rate(mdev, &rl);
1741 sq->rate_limit = rate;
1745 static int mlx5e_set_tx_maxrate(struct net_device *dev, int index, u32 rate)
1747 struct mlx5e_priv *priv = netdev_priv(dev);
1748 struct mlx5_core_dev *mdev = priv->mdev;
1749 struct mlx5e_txqsq *sq = priv->txq2sq[index];
1752 if (!mlx5_rl_is_supported(mdev)) {
1753 netdev_err(dev, "Rate limiting is not supported on this device\n");
1757 /* rate is given in Mb/sec, HW config is in Kb/sec */
1760 /* Check whether rate in valid range, 0 is always valid */
1761 if (rate && !mlx5_rl_is_in_range(mdev, rate)) {
1762 netdev_err(dev, "TX rate %u, is not in range\n", rate);
1766 mutex_lock(&priv->state_lock);
1767 if (test_bit(MLX5E_STATE_OPENED, &priv->state))
1768 err = mlx5e_set_sq_maxrate(dev, sq, rate);
1770 priv->tx_rates[index] = rate;
1771 mutex_unlock(&priv->state_lock);
1776 static int mlx5e_open_queues(struct mlx5e_channel *c,
1777 struct mlx5e_params *params,
1778 struct mlx5e_channel_param *cparam)
1780 struct dim_cq_moder icocq_moder = {0, 0};
1783 err = mlx5e_open_cq(c, icocq_moder, &cparam->icosq.cqp, &c->async_icosq.cq);
1787 err = mlx5e_open_cq(c, icocq_moder, &cparam->async_icosq.cqp, &c->icosq.cq);
1789 goto err_close_async_icosq_cq;
1791 err = mlx5e_open_tx_cqs(c, params, cparam);
1793 goto err_close_icosq_cq;
1795 err = mlx5e_open_cq(c, params->tx_cq_moderation, &cparam->xdp_sq.cqp, &c->xdpsq.cq);
1797 goto err_close_tx_cqs;
1799 err = mlx5e_open_cq(c, params->rx_cq_moderation, &cparam->rq.cqp, &c->rq.cq);
1801 goto err_close_xdp_tx_cqs;
1803 err = c->xdp ? mlx5e_open_cq(c, params->tx_cq_moderation,
1804 &cparam->xdp_sq.cqp, &c->rq_xdpsq.cq) : 0;
1806 goto err_close_rx_cq;
1808 napi_enable(&c->napi);
1810 spin_lock_init(&c->async_icosq_lock);
1812 err = mlx5e_open_icosq(c, params, &cparam->async_icosq, &c->async_icosq);
1814 goto err_disable_napi;
1816 err = mlx5e_open_icosq(c, params, &cparam->icosq, &c->icosq);
1818 goto err_close_async_icosq;
1820 err = mlx5e_open_sqs(c, params, cparam);
1822 goto err_close_icosq;
1825 err = mlx5e_open_xdpsq(c, params, &cparam->xdp_sq, NULL,
1826 &c->rq_xdpsq, false);
1831 err = mlx5e_open_rq(c, params, &cparam->rq, NULL, NULL, &c->rq);
1833 goto err_close_xdp_sq;
1835 err = mlx5e_open_xdpsq(c, params, &cparam->xdp_sq, NULL, &c->xdpsq, true);
1842 mlx5e_close_rq(&c->rq);
1846 mlx5e_close_xdpsq(&c->rq_xdpsq);
1852 mlx5e_close_icosq(&c->icosq);
1854 err_close_async_icosq:
1855 mlx5e_close_icosq(&c->async_icosq);
1858 napi_disable(&c->napi);
1861 mlx5e_close_cq(&c->rq_xdpsq.cq);
1864 mlx5e_close_cq(&c->rq.cq);
1866 err_close_xdp_tx_cqs:
1867 mlx5e_close_cq(&c->xdpsq.cq);
1870 mlx5e_close_tx_cqs(c);
1873 mlx5e_close_cq(&c->icosq.cq);
1875 err_close_async_icosq_cq:
1876 mlx5e_close_cq(&c->async_icosq.cq);
1881 static void mlx5e_close_queues(struct mlx5e_channel *c)
1883 mlx5e_close_xdpsq(&c->xdpsq);
1884 mlx5e_close_rq(&c->rq);
1886 mlx5e_close_xdpsq(&c->rq_xdpsq);
1888 mlx5e_close_icosq(&c->icosq);
1889 mlx5e_close_icosq(&c->async_icosq);
1890 napi_disable(&c->napi);
1892 mlx5e_close_cq(&c->rq_xdpsq.cq);
1893 mlx5e_close_cq(&c->rq.cq);
1894 mlx5e_close_cq(&c->xdpsq.cq);
1895 mlx5e_close_tx_cqs(c);
1896 mlx5e_close_cq(&c->icosq.cq);
1897 mlx5e_close_cq(&c->async_icosq.cq);
1900 static u8 mlx5e_enumerate_lag_port(struct mlx5_core_dev *mdev, int ix)
1902 u16 port_aff_bias = mlx5_core_is_pf(mdev) ? 0 : MLX5_CAP_GEN(mdev, vhca_id);
1904 return (ix + port_aff_bias) % mlx5e_get_num_lag_ports(mdev);
1907 static int mlx5e_open_channel(struct mlx5e_priv *priv, int ix,
1908 struct mlx5e_params *params,
1909 struct mlx5e_channel_param *cparam,
1910 struct xdp_umem *umem,
1911 struct mlx5e_channel **cp)
1913 int cpu = cpumask_first(mlx5_comp_irq_get_affinity_mask(priv->mdev, ix));
1914 struct net_device *netdev = priv->netdev;
1915 struct mlx5e_xsk_param xsk;
1916 struct mlx5e_channel *c;
1921 err = mlx5_vector2eqn(priv->mdev, ix, &eqn, &irq);
1925 c = kvzalloc_node(sizeof(*c), GFP_KERNEL, cpu_to_node(cpu));
1930 c->mdev = priv->mdev;
1931 c->tstamp = &priv->tstamp;
1934 c->pdev = priv->mdev->device;
1935 c->netdev = priv->netdev;
1936 c->mkey_be = cpu_to_be32(priv->mdev->mlx5e_res.mkey.key);
1937 c->num_tc = params->num_tc;
1938 c->xdp = !!params->xdp_prog;
1939 c->stats = &priv->channel_stats[ix].ch;
1940 c->irq_desc = irq_to_desc(irq);
1941 c->lag_port = mlx5e_enumerate_lag_port(priv->mdev, ix);
1943 netif_napi_add(netdev, &c->napi, mlx5e_napi_poll, 64);
1945 err = mlx5e_open_queues(c, params, cparam);
1950 mlx5e_build_xsk_param(umem, &xsk);
1951 err = mlx5e_open_xsk(priv, params, &xsk, umem, c);
1953 goto err_close_queues;
1961 mlx5e_close_queues(c);
1964 netif_napi_del(&c->napi);
1971 static void mlx5e_activate_channel(struct mlx5e_channel *c)
1975 for (tc = 0; tc < c->num_tc; tc++)
1976 mlx5e_activate_txqsq(&c->sq[tc]);
1977 mlx5e_activate_icosq(&c->icosq);
1978 mlx5e_activate_icosq(&c->async_icosq);
1979 mlx5e_activate_rq(&c->rq);
1981 if (test_bit(MLX5E_CHANNEL_STATE_XSK, c->state))
1982 mlx5e_activate_xsk(c);
1985 static void mlx5e_deactivate_channel(struct mlx5e_channel *c)
1989 if (test_bit(MLX5E_CHANNEL_STATE_XSK, c->state))
1990 mlx5e_deactivate_xsk(c);
1992 mlx5e_deactivate_rq(&c->rq);
1993 mlx5e_deactivate_icosq(&c->async_icosq);
1994 mlx5e_deactivate_icosq(&c->icosq);
1995 for (tc = 0; tc < c->num_tc; tc++)
1996 mlx5e_deactivate_txqsq(&c->sq[tc]);
1999 static void mlx5e_close_channel(struct mlx5e_channel *c)
2001 if (test_bit(MLX5E_CHANNEL_STATE_XSK, c->state))
2003 mlx5e_close_queues(c);
2004 netif_napi_del(&c->napi);
2009 #define DEFAULT_FRAG_SIZE (2048)
2011 static void mlx5e_build_rq_frags_info(struct mlx5_core_dev *mdev,
2012 struct mlx5e_params *params,
2013 struct mlx5e_xsk_param *xsk,
2014 struct mlx5e_rq_frags_info *info)
2016 u32 byte_count = MLX5E_SW2HW_MTU(params, params->sw_mtu);
2017 int frag_size_max = DEFAULT_FRAG_SIZE;
2021 #ifdef CONFIG_MLX5_EN_IPSEC
2022 if (MLX5_IPSEC_DEV(mdev))
2023 byte_count += MLX5E_METADATA_ETHER_LEN;
2026 if (mlx5e_rx_is_linear_skb(params, xsk)) {
2029 frag_stride = mlx5e_rx_get_linear_frag_sz(params, xsk);
2030 frag_stride = roundup_pow_of_two(frag_stride);
2032 info->arr[0].frag_size = byte_count;
2033 info->arr[0].frag_stride = frag_stride;
2034 info->num_frags = 1;
2035 info->wqe_bulk = PAGE_SIZE / frag_stride;
2039 if (byte_count > PAGE_SIZE +
2040 (MLX5E_MAX_RX_FRAGS - 1) * frag_size_max)
2041 frag_size_max = PAGE_SIZE;
2044 while (buf_size < byte_count) {
2045 int frag_size = byte_count - buf_size;
2047 if (i < MLX5E_MAX_RX_FRAGS - 1)
2048 frag_size = min(frag_size, frag_size_max);
2050 info->arr[i].frag_size = frag_size;
2051 info->arr[i].frag_stride = roundup_pow_of_two(frag_size);
2053 buf_size += frag_size;
2056 info->num_frags = i;
2057 /* number of different wqes sharing a page */
2058 info->wqe_bulk = 1 + (info->num_frags % 2);
2061 info->wqe_bulk = max_t(u8, info->wqe_bulk, 8);
2062 info->log_num_frags = order_base_2(info->num_frags);
2065 static inline u8 mlx5e_get_rqwq_log_stride(u8 wq_type, int ndsegs)
2067 int sz = sizeof(struct mlx5_wqe_data_seg) * ndsegs;
2070 case MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ:
2071 sz += sizeof(struct mlx5e_rx_wqe_ll);
2073 default: /* MLX5_WQ_TYPE_CYCLIC */
2074 sz += sizeof(struct mlx5e_rx_wqe_cyc);
2077 return order_base_2(sz);
2080 static u8 mlx5e_get_rq_log_wq_sz(void *rqc)
2082 void *wq = MLX5_ADDR_OF(rqc, rqc, wq);
2084 return MLX5_GET(wq, wq, log_wq_sz);
2087 void mlx5e_build_rq_param(struct mlx5e_priv *priv,
2088 struct mlx5e_params *params,
2089 struct mlx5e_xsk_param *xsk,
2090 struct mlx5e_rq_param *param)
2092 struct mlx5_core_dev *mdev = priv->mdev;
2093 void *rqc = param->rqc;
2094 void *wq = MLX5_ADDR_OF(rqc, rqc, wq);
2097 switch (params->rq_wq_type) {
2098 case MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ:
2099 MLX5_SET(wq, wq, log_wqe_num_of_strides,
2100 mlx5e_mpwqe_get_log_num_strides(mdev, params, xsk) -
2101 MLX5_MPWQE_LOG_NUM_STRIDES_BASE);
2102 MLX5_SET(wq, wq, log_wqe_stride_size,
2103 mlx5e_mpwqe_get_log_stride_size(mdev, params, xsk) -
2104 MLX5_MPWQE_LOG_STRIDE_SZ_BASE);
2105 MLX5_SET(wq, wq, log_wq_sz, mlx5e_mpwqe_get_log_rq_size(params, xsk));
2107 default: /* MLX5_WQ_TYPE_CYCLIC */
2108 MLX5_SET(wq, wq, log_wq_sz, params->log_rq_mtu_frames);
2109 mlx5e_build_rq_frags_info(mdev, params, xsk, ¶m->frags_info);
2110 ndsegs = param->frags_info.num_frags;
2113 MLX5_SET(wq, wq, wq_type, params->rq_wq_type);
2114 MLX5_SET(wq, wq, end_padding_mode, MLX5_WQ_END_PAD_MODE_ALIGN);
2115 MLX5_SET(wq, wq, log_wq_stride,
2116 mlx5e_get_rqwq_log_stride(params->rq_wq_type, ndsegs));
2117 MLX5_SET(wq, wq, pd, mdev->mlx5e_res.pdn);
2118 MLX5_SET(rqc, rqc, counter_set_id, priv->q_counter);
2119 MLX5_SET(rqc, rqc, vsd, params->vlan_strip_disable);
2120 MLX5_SET(rqc, rqc, scatter_fcs, params->scatter_fcs_en);
2122 param->wq.buf_numa_node = dev_to_node(mdev->device);
2123 mlx5e_build_rx_cq_param(priv, params, xsk, ¶m->cqp);
2126 static void mlx5e_build_drop_rq_param(struct mlx5e_priv *priv,
2127 struct mlx5e_rq_param *param)
2129 struct mlx5_core_dev *mdev = priv->mdev;
2130 void *rqc = param->rqc;
2131 void *wq = MLX5_ADDR_OF(rqc, rqc, wq);
2133 MLX5_SET(wq, wq, wq_type, MLX5_WQ_TYPE_CYCLIC);
2134 MLX5_SET(wq, wq, log_wq_stride,
2135 mlx5e_get_rqwq_log_stride(MLX5_WQ_TYPE_CYCLIC, 1));
2136 MLX5_SET(rqc, rqc, counter_set_id, priv->drop_rq_q_counter);
2138 param->wq.buf_numa_node = dev_to_node(mdev->device);
2141 void mlx5e_build_sq_param_common(struct mlx5e_priv *priv,
2142 struct mlx5e_sq_param *param)
2144 void *sqc = param->sqc;
2145 void *wq = MLX5_ADDR_OF(sqc, sqc, wq);
2147 MLX5_SET(wq, wq, log_wq_stride, ilog2(MLX5_SEND_WQE_BB));
2148 MLX5_SET(wq, wq, pd, priv->mdev->mlx5e_res.pdn);
2150 param->wq.buf_numa_node = dev_to_node(priv->mdev->device);
2153 static void mlx5e_build_sq_param(struct mlx5e_priv *priv,
2154 struct mlx5e_params *params,
2155 struct mlx5e_sq_param *param)
2157 void *sqc = param->sqc;
2158 void *wq = MLX5_ADDR_OF(sqc, sqc, wq);
2161 allow_swp = mlx5_geneve_tx_allowed(priv->mdev) ||
2162 !!MLX5_IPSEC_DEV(priv->mdev);
2163 mlx5e_build_sq_param_common(priv, param);
2164 MLX5_SET(wq, wq, log_wq_sz, params->log_sq_size);
2165 MLX5_SET(sqc, sqc, allow_swp, allow_swp);
2166 mlx5e_build_tx_cq_param(priv, params, ¶m->cqp);
2169 static void mlx5e_build_common_cq_param(struct mlx5e_priv *priv,
2170 struct mlx5e_cq_param *param)
2172 void *cqc = param->cqc;
2174 MLX5_SET(cqc, cqc, uar_page, priv->mdev->priv.uar->index);
2175 if (MLX5_CAP_GEN(priv->mdev, cqe_128_always) && cache_line_size() >= 128)
2176 MLX5_SET(cqc, cqc, cqe_sz, CQE_STRIDE_128_PAD);
2179 void mlx5e_build_rx_cq_param(struct mlx5e_priv *priv,
2180 struct mlx5e_params *params,
2181 struct mlx5e_xsk_param *xsk,
2182 struct mlx5e_cq_param *param)
2184 struct mlx5_core_dev *mdev = priv->mdev;
2185 void *cqc = param->cqc;
2188 switch (params->rq_wq_type) {
2189 case MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ:
2190 log_cq_size = mlx5e_mpwqe_get_log_rq_size(params, xsk) +
2191 mlx5e_mpwqe_get_log_num_strides(mdev, params, xsk);
2193 default: /* MLX5_WQ_TYPE_CYCLIC */
2194 log_cq_size = params->log_rq_mtu_frames;
2197 MLX5_SET(cqc, cqc, log_cq_size, log_cq_size);
2198 if (MLX5E_GET_PFLAG(params, MLX5E_PFLAG_RX_CQE_COMPRESS)) {
2199 MLX5_SET(cqc, cqc, mini_cqe_res_format, MLX5_CQE_FORMAT_CSUM);
2200 MLX5_SET(cqc, cqc, cqe_comp_en, 1);
2203 mlx5e_build_common_cq_param(priv, param);
2204 param->cq_period_mode = params->rx_cq_moderation.cq_period_mode;
2207 void mlx5e_build_tx_cq_param(struct mlx5e_priv *priv,
2208 struct mlx5e_params *params,
2209 struct mlx5e_cq_param *param)
2211 void *cqc = param->cqc;
2213 MLX5_SET(cqc, cqc, log_cq_size, params->log_sq_size);
2215 mlx5e_build_common_cq_param(priv, param);
2216 param->cq_period_mode = params->tx_cq_moderation.cq_period_mode;
2219 void mlx5e_build_ico_cq_param(struct mlx5e_priv *priv,
2221 struct mlx5e_cq_param *param)
2223 void *cqc = param->cqc;
2225 MLX5_SET(cqc, cqc, log_cq_size, log_wq_size);
2227 mlx5e_build_common_cq_param(priv, param);
2229 param->cq_period_mode = DIM_CQ_PERIOD_MODE_START_FROM_EQE;
2232 void mlx5e_build_icosq_param(struct mlx5e_priv *priv,
2234 struct mlx5e_sq_param *param)
2236 void *sqc = param->sqc;
2237 void *wq = MLX5_ADDR_OF(sqc, sqc, wq);
2239 mlx5e_build_sq_param_common(priv, param);
2241 MLX5_SET(wq, wq, log_wq_sz, log_wq_size);
2242 MLX5_SET(sqc, sqc, reg_umr, MLX5_CAP_ETH(priv->mdev, reg_umr_sq));
2243 mlx5e_build_ico_cq_param(priv, log_wq_size, ¶m->cqp);
2246 void mlx5e_build_xdpsq_param(struct mlx5e_priv *priv,
2247 struct mlx5e_params *params,
2248 struct mlx5e_sq_param *param)
2250 void *sqc = param->sqc;
2251 void *wq = MLX5_ADDR_OF(sqc, sqc, wq);
2253 mlx5e_build_sq_param_common(priv, param);
2254 MLX5_SET(wq, wq, log_wq_sz, params->log_sq_size);
2255 param->is_mpw = MLX5E_GET_PFLAG(params, MLX5E_PFLAG_XDP_TX_MPWQE);
2256 mlx5e_build_tx_cq_param(priv, params, ¶m->cqp);
2259 static u8 mlx5e_build_icosq_log_wq_sz(struct mlx5e_params *params,
2260 struct mlx5e_rq_param *rqp)
2262 switch (params->rq_wq_type) {
2263 case MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ:
2264 return order_base_2(MLX5E_UMR_WQEBBS) +
2265 mlx5e_get_rq_log_wq_sz(rqp->rqc);
2266 default: /* MLX5_WQ_TYPE_CYCLIC */
2267 return MLX5E_PARAMS_MINIMUM_LOG_SQ_SIZE;
2271 static u8 mlx5e_build_async_icosq_log_wq_sz(struct net_device *netdev)
2273 if (netdev->hw_features & NETIF_F_HW_TLS_RX)
2274 return MLX5E_PARAMS_DEFAULT_LOG_SQ_SIZE;
2276 return MLX5E_PARAMS_MINIMUM_LOG_SQ_SIZE;
2279 static void mlx5e_build_channel_param(struct mlx5e_priv *priv,
2280 struct mlx5e_params *params,
2281 struct mlx5e_channel_param *cparam)
2283 u8 icosq_log_wq_sz, async_icosq_log_wq_sz;
2285 mlx5e_build_rq_param(priv, params, NULL, &cparam->rq);
2287 icosq_log_wq_sz = mlx5e_build_icosq_log_wq_sz(params, &cparam->rq);
2288 async_icosq_log_wq_sz = mlx5e_build_async_icosq_log_wq_sz(priv->netdev);
2290 mlx5e_build_sq_param(priv, params, &cparam->txq_sq);
2291 mlx5e_build_xdpsq_param(priv, params, &cparam->xdp_sq);
2292 mlx5e_build_icosq_param(priv, icosq_log_wq_sz, &cparam->icosq);
2293 mlx5e_build_icosq_param(priv, async_icosq_log_wq_sz, &cparam->async_icosq);
2296 int mlx5e_open_channels(struct mlx5e_priv *priv,
2297 struct mlx5e_channels *chs)
2299 struct mlx5e_channel_param *cparam;
2303 chs->num = chs->params.num_channels;
2305 chs->c = kcalloc(chs->num, sizeof(struct mlx5e_channel *), GFP_KERNEL);
2306 cparam = kvzalloc(sizeof(struct mlx5e_channel_param), GFP_KERNEL);
2307 if (!chs->c || !cparam)
2310 mlx5e_build_channel_param(priv, &chs->params, cparam);
2311 for (i = 0; i < chs->num; i++) {
2312 struct xdp_umem *umem = NULL;
2314 if (chs->params.xdp_prog)
2315 umem = mlx5e_xsk_get_umem(&chs->params, chs->params.xsk, i);
2317 err = mlx5e_open_channel(priv, i, &chs->params, cparam, umem, &chs->c[i]);
2319 goto err_close_channels;
2322 mlx5e_health_channels_update(priv);
2327 for (i--; i >= 0; i--)
2328 mlx5e_close_channel(chs->c[i]);
2337 static void mlx5e_activate_channels(struct mlx5e_channels *chs)
2341 for (i = 0; i < chs->num; i++)
2342 mlx5e_activate_channel(chs->c[i]);
2345 #define MLX5E_RQ_WQES_TIMEOUT 20000 /* msecs */
2347 static int mlx5e_wait_channels_min_rx_wqes(struct mlx5e_channels *chs)
2352 for (i = 0; i < chs->num; i++) {
2353 int timeout = err ? 0 : MLX5E_RQ_WQES_TIMEOUT;
2355 err |= mlx5e_wait_for_min_rx_wqes(&chs->c[i]->rq, timeout);
2357 /* Don't wait on the XSK RQ, because the newer xdpsock sample
2358 * doesn't provide any Fill Ring entries at the setup stage.
2362 return err ? -ETIMEDOUT : 0;
2365 static void mlx5e_deactivate_channels(struct mlx5e_channels *chs)
2369 for (i = 0; i < chs->num; i++)
2370 mlx5e_deactivate_channel(chs->c[i]);
2373 void mlx5e_close_channels(struct mlx5e_channels *chs)
2377 for (i = 0; i < chs->num; i++)
2378 mlx5e_close_channel(chs->c[i]);
2385 mlx5e_create_rqt(struct mlx5e_priv *priv, int sz, struct mlx5e_rqt *rqt)
2387 struct mlx5_core_dev *mdev = priv->mdev;
2394 inlen = MLX5_ST_SZ_BYTES(create_rqt_in) + sizeof(u32) * sz;
2395 in = kvzalloc(inlen, GFP_KERNEL);
2399 rqtc = MLX5_ADDR_OF(create_rqt_in, in, rqt_context);
2401 MLX5_SET(rqtc, rqtc, rqt_actual_size, sz);
2402 MLX5_SET(rqtc, rqtc, rqt_max_size, sz);
2404 for (i = 0; i < sz; i++)
2405 MLX5_SET(rqtc, rqtc, rq_num[i], priv->drop_rq.rqn);
2407 err = mlx5_core_create_rqt(mdev, in, inlen, &rqt->rqtn);
2409 rqt->enabled = true;
2415 void mlx5e_destroy_rqt(struct mlx5e_priv *priv, struct mlx5e_rqt *rqt)
2417 rqt->enabled = false;
2418 mlx5_core_destroy_rqt(priv->mdev, rqt->rqtn);
2421 int mlx5e_create_indirect_rqt(struct mlx5e_priv *priv)
2423 struct mlx5e_rqt *rqt = &priv->indir_rqt;
2426 err = mlx5e_create_rqt(priv, MLX5E_INDIR_RQT_SIZE, rqt);
2428 mlx5_core_warn(priv->mdev, "create indirect rqts failed, %d\n", err);
2432 int mlx5e_create_direct_rqts(struct mlx5e_priv *priv, struct mlx5e_tir *tirs)
2437 for (ix = 0; ix < priv->max_nch; ix++) {
2438 err = mlx5e_create_rqt(priv, 1 /*size */, &tirs[ix].rqt);
2440 goto err_destroy_rqts;
2446 mlx5_core_warn(priv->mdev, "create rqts failed, %d\n", err);
2447 for (ix--; ix >= 0; ix--)
2448 mlx5e_destroy_rqt(priv, &tirs[ix].rqt);
2453 void mlx5e_destroy_direct_rqts(struct mlx5e_priv *priv, struct mlx5e_tir *tirs)
2457 for (i = 0; i < priv->max_nch; i++)
2458 mlx5e_destroy_rqt(priv, &tirs[i].rqt);
2461 static int mlx5e_rx_hash_fn(int hfunc)
2463 return (hfunc == ETH_RSS_HASH_TOP) ?
2464 MLX5_RX_HASH_FN_TOEPLITZ :
2465 MLX5_RX_HASH_FN_INVERTED_XOR8;
2468 int mlx5e_bits_invert(unsigned long a, int size)
2473 for (i = 0; i < size; i++)
2474 inv |= (test_bit(size - i - 1, &a) ? 1 : 0) << i;
2479 static void mlx5e_fill_rqt_rqns(struct mlx5e_priv *priv, int sz,
2480 struct mlx5e_redirect_rqt_param rrp, void *rqtc)
2484 for (i = 0; i < sz; i++) {
2490 if (rrp.rss.hfunc == ETH_RSS_HASH_XOR)
2491 ix = mlx5e_bits_invert(i, ilog2(sz));
2493 ix = priv->rss_params.indirection_rqt[ix];
2494 rqn = rrp.rss.channels->c[ix]->rq.rqn;
2498 MLX5_SET(rqtc, rqtc, rq_num[i], rqn);
2502 int mlx5e_redirect_rqt(struct mlx5e_priv *priv, u32 rqtn, int sz,
2503 struct mlx5e_redirect_rqt_param rrp)
2505 struct mlx5_core_dev *mdev = priv->mdev;
2511 inlen = MLX5_ST_SZ_BYTES(modify_rqt_in) + sizeof(u32) * sz;
2512 in = kvzalloc(inlen, GFP_KERNEL);
2516 rqtc = MLX5_ADDR_OF(modify_rqt_in, in, ctx);
2518 MLX5_SET(rqtc, rqtc, rqt_actual_size, sz);
2519 MLX5_SET(modify_rqt_in, in, bitmask.rqn_list, 1);
2520 mlx5e_fill_rqt_rqns(priv, sz, rrp, rqtc);
2521 err = mlx5_core_modify_rqt(mdev, rqtn, in, inlen);
2527 static u32 mlx5e_get_direct_rqn(struct mlx5e_priv *priv, int ix,
2528 struct mlx5e_redirect_rqt_param rrp)
2533 if (ix >= rrp.rss.channels->num)
2534 return priv->drop_rq.rqn;
2536 return rrp.rss.channels->c[ix]->rq.rqn;
2539 static void mlx5e_redirect_rqts(struct mlx5e_priv *priv,
2540 struct mlx5e_redirect_rqt_param rrp)
2545 if (priv->indir_rqt.enabled) {
2547 rqtn = priv->indir_rqt.rqtn;
2548 mlx5e_redirect_rqt(priv, rqtn, MLX5E_INDIR_RQT_SIZE, rrp);
2551 for (ix = 0; ix < priv->max_nch; ix++) {
2552 struct mlx5e_redirect_rqt_param direct_rrp = {
2555 .rqn = mlx5e_get_direct_rqn(priv, ix, rrp)
2559 /* Direct RQ Tables */
2560 if (!priv->direct_tir[ix].rqt.enabled)
2563 rqtn = priv->direct_tir[ix].rqt.rqtn;
2564 mlx5e_redirect_rqt(priv, rqtn, 1, direct_rrp);
2568 static void mlx5e_redirect_rqts_to_channels(struct mlx5e_priv *priv,
2569 struct mlx5e_channels *chs)
2571 struct mlx5e_redirect_rqt_param rrp = {
2576 .hfunc = priv->rss_params.hfunc,
2581 mlx5e_redirect_rqts(priv, rrp);
2584 static void mlx5e_redirect_rqts_to_drop(struct mlx5e_priv *priv)
2586 struct mlx5e_redirect_rqt_param drop_rrp = {
2589 .rqn = priv->drop_rq.rqn,
2593 mlx5e_redirect_rqts(priv, drop_rrp);
2596 static const struct mlx5e_tirc_config tirc_default_config[MLX5E_NUM_INDIR_TIRS] = {
2597 [MLX5E_TT_IPV4_TCP] = { .l3_prot_type = MLX5_L3_PROT_TYPE_IPV4,
2598 .l4_prot_type = MLX5_L4_PROT_TYPE_TCP,
2599 .rx_hash_fields = MLX5_HASH_IP_L4PORTS,
2601 [MLX5E_TT_IPV6_TCP] = { .l3_prot_type = MLX5_L3_PROT_TYPE_IPV6,
2602 .l4_prot_type = MLX5_L4_PROT_TYPE_TCP,
2603 .rx_hash_fields = MLX5_HASH_IP_L4PORTS,
2605 [MLX5E_TT_IPV4_UDP] = { .l3_prot_type = MLX5_L3_PROT_TYPE_IPV4,
2606 .l4_prot_type = MLX5_L4_PROT_TYPE_UDP,
2607 .rx_hash_fields = MLX5_HASH_IP_L4PORTS,
2609 [MLX5E_TT_IPV6_UDP] = { .l3_prot_type = MLX5_L3_PROT_TYPE_IPV6,
2610 .l4_prot_type = MLX5_L4_PROT_TYPE_UDP,
2611 .rx_hash_fields = MLX5_HASH_IP_L4PORTS,
2613 [MLX5E_TT_IPV4_IPSEC_AH] = { .l3_prot_type = MLX5_L3_PROT_TYPE_IPV4,
2615 .rx_hash_fields = MLX5_HASH_IP_IPSEC_SPI,
2617 [MLX5E_TT_IPV6_IPSEC_AH] = { .l3_prot_type = MLX5_L3_PROT_TYPE_IPV6,
2619 .rx_hash_fields = MLX5_HASH_IP_IPSEC_SPI,
2621 [MLX5E_TT_IPV4_IPSEC_ESP] = { .l3_prot_type = MLX5_L3_PROT_TYPE_IPV4,
2623 .rx_hash_fields = MLX5_HASH_IP_IPSEC_SPI,
2625 [MLX5E_TT_IPV6_IPSEC_ESP] = { .l3_prot_type = MLX5_L3_PROT_TYPE_IPV6,
2627 .rx_hash_fields = MLX5_HASH_IP_IPSEC_SPI,
2629 [MLX5E_TT_IPV4] = { .l3_prot_type = MLX5_L3_PROT_TYPE_IPV4,
2631 .rx_hash_fields = MLX5_HASH_IP,
2633 [MLX5E_TT_IPV6] = { .l3_prot_type = MLX5_L3_PROT_TYPE_IPV6,
2635 .rx_hash_fields = MLX5_HASH_IP,
2639 struct mlx5e_tirc_config mlx5e_tirc_get_default_config(enum mlx5e_traffic_types tt)
2641 return tirc_default_config[tt];
2644 static void mlx5e_build_tir_ctx_lro(struct mlx5e_params *params, void *tirc)
2646 if (!params->lro_en)
2649 #define ROUGH_MAX_L2_L3_HDR_SZ 256
2651 MLX5_SET(tirc, tirc, lro_enable_mask,
2652 MLX5_TIRC_LRO_ENABLE_MASK_IPV4_LRO |
2653 MLX5_TIRC_LRO_ENABLE_MASK_IPV6_LRO);
2654 MLX5_SET(tirc, tirc, lro_max_ip_payload_size,
2655 (MLX5E_PARAMS_DEFAULT_LRO_WQE_SZ - ROUGH_MAX_L2_L3_HDR_SZ) >> 8);
2656 MLX5_SET(tirc, tirc, lro_timeout_period_usecs, params->lro_timeout);
2659 void mlx5e_build_indir_tir_ctx_hash(struct mlx5e_rss_params *rss_params,
2660 const struct mlx5e_tirc_config *ttconfig,
2661 void *tirc, bool inner)
2663 void *hfso = inner ? MLX5_ADDR_OF(tirc, tirc, rx_hash_field_selector_inner) :
2664 MLX5_ADDR_OF(tirc, tirc, rx_hash_field_selector_outer);
2666 MLX5_SET(tirc, tirc, rx_hash_fn, mlx5e_rx_hash_fn(rss_params->hfunc));
2667 if (rss_params->hfunc == ETH_RSS_HASH_TOP) {
2668 void *rss_key = MLX5_ADDR_OF(tirc, tirc,
2669 rx_hash_toeplitz_key);
2670 size_t len = MLX5_FLD_SZ_BYTES(tirc,
2671 rx_hash_toeplitz_key);
2673 MLX5_SET(tirc, tirc, rx_hash_symmetric, 1);
2674 memcpy(rss_key, rss_params->toeplitz_hash_key, len);
2676 MLX5_SET(rx_hash_field_select, hfso, l3_prot_type,
2677 ttconfig->l3_prot_type);
2678 MLX5_SET(rx_hash_field_select, hfso, l4_prot_type,
2679 ttconfig->l4_prot_type);
2680 MLX5_SET(rx_hash_field_select, hfso, selected_fields,
2681 ttconfig->rx_hash_fields);
2684 static void mlx5e_update_rx_hash_fields(struct mlx5e_tirc_config *ttconfig,
2685 enum mlx5e_traffic_types tt,
2688 *ttconfig = tirc_default_config[tt];
2689 ttconfig->rx_hash_fields = rx_hash_fields;
2692 void mlx5e_modify_tirs_hash(struct mlx5e_priv *priv, void *in)
2694 void *tirc = MLX5_ADDR_OF(modify_tir_in, in, ctx);
2695 struct mlx5e_rss_params *rss = &priv->rss_params;
2696 struct mlx5_core_dev *mdev = priv->mdev;
2697 int ctxlen = MLX5_ST_SZ_BYTES(tirc);
2698 struct mlx5e_tirc_config ttconfig;
2701 MLX5_SET(modify_tir_in, in, bitmask.hash, 1);
2703 for (tt = 0; tt < MLX5E_NUM_INDIR_TIRS; tt++) {
2704 memset(tirc, 0, ctxlen);
2705 mlx5e_update_rx_hash_fields(&ttconfig, tt,
2706 rss->rx_hash_fields[tt]);
2707 mlx5e_build_indir_tir_ctx_hash(rss, &ttconfig, tirc, false);
2708 mlx5_core_modify_tir(mdev, priv->indir_tir[tt].tirn, in);
2711 /* Verify inner tirs resources allocated */
2712 if (!priv->inner_indir_tir[0].tirn)
2715 for (tt = 0; tt < MLX5E_NUM_INDIR_TIRS; tt++) {
2716 memset(tirc, 0, ctxlen);
2717 mlx5e_update_rx_hash_fields(&ttconfig, tt,
2718 rss->rx_hash_fields[tt]);
2719 mlx5e_build_indir_tir_ctx_hash(rss, &ttconfig, tirc, true);
2720 mlx5_core_modify_tir(mdev, priv->inner_indir_tir[tt].tirn, in);
2724 static int mlx5e_modify_tirs_lro(struct mlx5e_priv *priv)
2726 struct mlx5_core_dev *mdev = priv->mdev;
2735 inlen = MLX5_ST_SZ_BYTES(modify_tir_in);
2736 in = kvzalloc(inlen, GFP_KERNEL);
2740 MLX5_SET(modify_tir_in, in, bitmask.lro, 1);
2741 tirc = MLX5_ADDR_OF(modify_tir_in, in, ctx);
2743 mlx5e_build_tir_ctx_lro(&priv->channels.params, tirc);
2745 for (tt = 0; tt < MLX5E_NUM_INDIR_TIRS; tt++) {
2746 err = mlx5_core_modify_tir(mdev, priv->indir_tir[tt].tirn, in);
2751 for (ix = 0; ix < priv->max_nch; ix++) {
2752 err = mlx5_core_modify_tir(mdev, priv->direct_tir[ix].tirn, in);
2763 static MLX5E_DEFINE_PREACTIVATE_WRAPPER_CTX(mlx5e_modify_tirs_lro);
2765 static int mlx5e_set_mtu(struct mlx5_core_dev *mdev,
2766 struct mlx5e_params *params, u16 mtu)
2768 u16 hw_mtu = MLX5E_SW2HW_MTU(params, mtu);
2771 err = mlx5_set_port_mtu(mdev, hw_mtu, 1);
2775 /* Update vport context MTU */
2776 mlx5_modify_nic_vport_mtu(mdev, hw_mtu);
2780 static void mlx5e_query_mtu(struct mlx5_core_dev *mdev,
2781 struct mlx5e_params *params, u16 *mtu)
2786 err = mlx5_query_nic_vport_mtu(mdev, &hw_mtu);
2787 if (err || !hw_mtu) /* fallback to port oper mtu */
2788 mlx5_query_port_oper_mtu(mdev, &hw_mtu, 1);
2790 *mtu = MLX5E_HW2SW_MTU(params, hw_mtu);
2793 int mlx5e_set_dev_port_mtu(struct mlx5e_priv *priv)
2795 struct mlx5e_params *params = &priv->channels.params;
2796 struct net_device *netdev = priv->netdev;
2797 struct mlx5_core_dev *mdev = priv->mdev;
2801 err = mlx5e_set_mtu(mdev, params, params->sw_mtu);
2805 mlx5e_query_mtu(mdev, params, &mtu);
2806 if (mtu != params->sw_mtu)
2807 netdev_warn(netdev, "%s: VPort MTU %d is different than netdev mtu %d\n",
2808 __func__, mtu, params->sw_mtu);
2810 params->sw_mtu = mtu;
2814 MLX5E_DEFINE_PREACTIVATE_WRAPPER_CTX(mlx5e_set_dev_port_mtu);
2816 void mlx5e_set_netdev_mtu_boundaries(struct mlx5e_priv *priv)
2818 struct mlx5e_params *params = &priv->channels.params;
2819 struct net_device *netdev = priv->netdev;
2820 struct mlx5_core_dev *mdev = priv->mdev;
2823 /* MTU range: 68 - hw-specific max */
2824 netdev->min_mtu = ETH_MIN_MTU;
2826 mlx5_query_port_max_mtu(mdev, &max_mtu, 1);
2827 netdev->max_mtu = min_t(unsigned int, MLX5E_HW2SW_MTU(params, max_mtu),
2831 static void mlx5e_netdev_set_tcs(struct net_device *netdev, u16 nch, u8 ntc)
2835 netdev_reset_tc(netdev);
2840 netdev_set_num_tc(netdev, ntc);
2842 /* Map netdev TCs to offset 0
2843 * We have our own UP to TXQ mapping for QoS
2845 for (tc = 0; tc < ntc; tc++)
2846 netdev_set_tc_queue(netdev, tc, nch, 0);
2849 static int mlx5e_update_netdev_queues(struct mlx5e_priv *priv)
2851 struct net_device *netdev = priv->netdev;
2852 int num_txqs, num_rxqs, nch, ntc;
2853 int old_num_txqs, old_ntc;
2856 old_num_txqs = netdev->real_num_tx_queues;
2857 old_ntc = netdev->num_tc;
2859 nch = priv->channels.params.num_channels;
2860 ntc = priv->channels.params.num_tc;
2861 num_txqs = nch * ntc;
2862 num_rxqs = nch * priv->profile->rq_groups;
2864 mlx5e_netdev_set_tcs(netdev, nch, ntc);
2866 err = netif_set_real_num_tx_queues(netdev, num_txqs);
2868 netdev_warn(netdev, "netif_set_real_num_tx_queues failed, %d\n", err);
2871 err = netif_set_real_num_rx_queues(netdev, num_rxqs);
2873 netdev_warn(netdev, "netif_set_real_num_rx_queues failed, %d\n", err);
2880 /* netif_set_real_num_rx_queues could fail only when nch increased. Only
2881 * one of nch and ntc is changed in this function. That means, the call
2882 * to netif_set_real_num_tx_queues below should not fail, because it
2883 * decreases the number of TX queues.
2885 WARN_ON_ONCE(netif_set_real_num_tx_queues(netdev, old_num_txqs));
2888 mlx5e_netdev_set_tcs(netdev, old_num_txqs / old_ntc, old_ntc);
2892 static void mlx5e_set_default_xps_cpumasks(struct mlx5e_priv *priv,
2893 struct mlx5e_params *params)
2895 struct mlx5_core_dev *mdev = priv->mdev;
2896 int num_comp_vectors, ix, irq;
2898 num_comp_vectors = mlx5_comp_vectors_count(mdev);
2900 for (ix = 0; ix < params->num_channels; ix++) {
2901 cpumask_clear(priv->scratchpad.cpumask);
2903 for (irq = ix; irq < num_comp_vectors; irq += params->num_channels) {
2904 int cpu = cpumask_first(mlx5_comp_irq_get_affinity_mask(mdev, irq));
2906 cpumask_set_cpu(cpu, priv->scratchpad.cpumask);
2909 netif_set_xps_queue(priv->netdev, priv->scratchpad.cpumask, ix);
2913 int mlx5e_num_channels_changed(struct mlx5e_priv *priv)
2915 u16 count = priv->channels.params.num_channels;
2918 err = mlx5e_update_netdev_queues(priv);
2922 mlx5e_set_default_xps_cpumasks(priv, &priv->channels.params);
2924 if (!netif_is_rxfh_configured(priv->netdev))
2925 mlx5e_build_default_indir_rqt(priv->rss_params.indirection_rqt,
2926 MLX5E_INDIR_RQT_SIZE, count);
2931 MLX5E_DEFINE_PREACTIVATE_WRAPPER_CTX(mlx5e_num_channels_changed);
2933 static void mlx5e_build_txq_maps(struct mlx5e_priv *priv)
2937 ch = priv->channels.num;
2939 for (i = 0; i < ch; i++) {
2942 for (tc = 0; tc < priv->channels.params.num_tc; tc++) {
2943 struct mlx5e_channel *c = priv->channels.c[i];
2944 struct mlx5e_txqsq *sq = &c->sq[tc];
2946 priv->txq2sq[sq->txq_ix] = sq;
2947 priv->channel_tc2realtxq[i][tc] = i + tc * ch;
2952 void mlx5e_activate_priv_channels(struct mlx5e_priv *priv)
2954 mlx5e_build_txq_maps(priv);
2955 mlx5e_activate_channels(&priv->channels);
2956 mlx5e_xdp_tx_enable(priv);
2957 netif_tx_start_all_queues(priv->netdev);
2959 if (mlx5e_is_vport_rep(priv))
2960 mlx5e_add_sqs_fwd_rules(priv);
2962 mlx5e_wait_channels_min_rx_wqes(&priv->channels);
2963 mlx5e_redirect_rqts_to_channels(priv, &priv->channels);
2965 mlx5e_xsk_redirect_rqts_to_channels(priv, &priv->channels);
2968 void mlx5e_deactivate_priv_channels(struct mlx5e_priv *priv)
2970 mlx5e_xsk_redirect_rqts_to_drop(priv, &priv->channels);
2972 mlx5e_redirect_rqts_to_drop(priv);
2974 if (mlx5e_is_vport_rep(priv))
2975 mlx5e_remove_sqs_fwd_rules(priv);
2977 /* FIXME: This is a W/A only for tx timeout watch dog false alarm when
2978 * polling for inactive tx queues.
2980 netif_tx_stop_all_queues(priv->netdev);
2981 netif_tx_disable(priv->netdev);
2982 mlx5e_xdp_tx_disable(priv);
2983 mlx5e_deactivate_channels(&priv->channels);
2986 static int mlx5e_switch_priv_channels(struct mlx5e_priv *priv,
2987 struct mlx5e_channels *new_chs,
2988 mlx5e_fp_preactivate preactivate,
2991 struct net_device *netdev = priv->netdev;
2992 struct mlx5e_channels old_chs;
2996 carrier_ok = netif_carrier_ok(netdev);
2997 netif_carrier_off(netdev);
2999 mlx5e_deactivate_priv_channels(priv);
3001 old_chs = priv->channels;
3002 priv->channels = *new_chs;
3004 /* New channels are ready to roll, call the preactivate hook if needed
3005 * to modify HW settings or update kernel parameters.
3008 err = preactivate(priv, context);
3010 priv->channels = old_chs;
3015 mlx5e_close_channels(&old_chs);
3016 priv->profile->update_rx(priv);
3019 mlx5e_activate_priv_channels(priv);
3021 /* return carrier back if needed */
3023 netif_carrier_on(netdev);
3028 int mlx5e_safe_switch_channels(struct mlx5e_priv *priv,
3029 struct mlx5e_channels *new_chs,
3030 mlx5e_fp_preactivate preactivate,
3035 err = mlx5e_open_channels(priv, new_chs);
3039 err = mlx5e_switch_priv_channels(priv, new_chs, preactivate, context);
3046 mlx5e_close_channels(new_chs);
3051 int mlx5e_safe_reopen_channels(struct mlx5e_priv *priv)
3053 struct mlx5e_channels new_channels = {};
3055 new_channels.params = priv->channels.params;
3056 return mlx5e_safe_switch_channels(priv, &new_channels, NULL, NULL);
3059 void mlx5e_timestamp_init(struct mlx5e_priv *priv)
3061 priv->tstamp.tx_type = HWTSTAMP_TX_OFF;
3062 priv->tstamp.rx_filter = HWTSTAMP_FILTER_NONE;
3065 int mlx5e_open_locked(struct net_device *netdev)
3067 struct mlx5e_priv *priv = netdev_priv(netdev);
3070 set_bit(MLX5E_STATE_OPENED, &priv->state);
3072 err = mlx5e_open_channels(priv, &priv->channels);
3074 goto err_clear_state_opened_flag;
3076 priv->profile->update_rx(priv);
3077 mlx5e_activate_priv_channels(priv);
3078 if (priv->profile->update_carrier)
3079 priv->profile->update_carrier(priv);
3081 mlx5e_queue_update_stats(priv);
3084 err_clear_state_opened_flag:
3085 clear_bit(MLX5E_STATE_OPENED, &priv->state);
3089 int mlx5e_open(struct net_device *netdev)
3091 struct mlx5e_priv *priv = netdev_priv(netdev);
3094 mutex_lock(&priv->state_lock);
3095 err = mlx5e_open_locked(netdev);
3097 mlx5_set_port_admin_status(priv->mdev, MLX5_PORT_UP);
3098 mutex_unlock(&priv->state_lock);
3103 int mlx5e_close_locked(struct net_device *netdev)
3105 struct mlx5e_priv *priv = netdev_priv(netdev);
3107 /* May already be CLOSED in case a previous configuration operation
3108 * (e.g RX/TX queue size change) that involves close&open failed.
3110 if (!test_bit(MLX5E_STATE_OPENED, &priv->state))
3113 clear_bit(MLX5E_STATE_OPENED, &priv->state);
3115 netif_carrier_off(priv->netdev);
3116 mlx5e_deactivate_priv_channels(priv);
3117 mlx5e_close_channels(&priv->channels);
3122 int mlx5e_close(struct net_device *netdev)
3124 struct mlx5e_priv *priv = netdev_priv(netdev);
3127 if (!netif_device_present(netdev))
3130 mutex_lock(&priv->state_lock);
3131 mlx5_set_port_admin_status(priv->mdev, MLX5_PORT_DOWN);
3132 err = mlx5e_close_locked(netdev);
3133 mutex_unlock(&priv->state_lock);
3138 static int mlx5e_alloc_drop_rq(struct mlx5_core_dev *mdev,
3139 struct mlx5e_rq *rq,
3140 struct mlx5e_rq_param *param)
3142 void *rqc = param->rqc;
3143 void *rqc_wq = MLX5_ADDR_OF(rqc, rqc, wq);
3146 param->wq.db_numa_node = param->wq.buf_numa_node;
3148 err = mlx5_wq_cyc_create(mdev, ¶m->wq, rqc_wq, &rq->wqe.wq,
3153 /* Mark as unused given "Drop-RQ" packets never reach XDP */
3154 xdp_rxq_info_unused(&rq->xdp_rxq);
3161 static int mlx5e_alloc_drop_cq(struct mlx5_core_dev *mdev,
3162 struct mlx5e_cq *cq,
3163 struct mlx5e_cq_param *param)
3165 param->wq.buf_numa_node = dev_to_node(mdev->device);
3166 param->wq.db_numa_node = dev_to_node(mdev->device);
3168 return mlx5e_alloc_cq_common(mdev, param, cq);
3171 int mlx5e_open_drop_rq(struct mlx5e_priv *priv,
3172 struct mlx5e_rq *drop_rq)
3174 struct mlx5_core_dev *mdev = priv->mdev;
3175 struct mlx5e_cq_param cq_param = {};
3176 struct mlx5e_rq_param rq_param = {};
3177 struct mlx5e_cq *cq = &drop_rq->cq;
3180 mlx5e_build_drop_rq_param(priv, &rq_param);
3182 err = mlx5e_alloc_drop_cq(mdev, cq, &cq_param);
3186 err = mlx5e_create_cq(cq, &cq_param);
3190 err = mlx5e_alloc_drop_rq(mdev, drop_rq, &rq_param);
3192 goto err_destroy_cq;
3194 err = mlx5e_create_rq(drop_rq, &rq_param);
3198 err = mlx5e_modify_rq_state(drop_rq, MLX5_RQC_STATE_RST, MLX5_RQC_STATE_RDY);
3200 mlx5_core_warn(priv->mdev, "modify_rq_state failed, rx_if_down_packets won't be counted %d\n", err);
3205 mlx5e_free_rq(drop_rq);
3208 mlx5e_destroy_cq(cq);
3216 void mlx5e_close_drop_rq(struct mlx5e_rq *drop_rq)
3218 mlx5e_destroy_rq(drop_rq);
3219 mlx5e_free_rq(drop_rq);
3220 mlx5e_destroy_cq(&drop_rq->cq);
3221 mlx5e_free_cq(&drop_rq->cq);
3224 int mlx5e_create_tis(struct mlx5_core_dev *mdev, void *in, u32 *tisn)
3226 void *tisc = MLX5_ADDR_OF(create_tis_in, in, ctx);
3228 MLX5_SET(tisc, tisc, transport_domain, mdev->mlx5e_res.td.tdn);
3230 if (MLX5_GET(tisc, tisc, tls_en))
3231 MLX5_SET(tisc, tisc, pd, mdev->mlx5e_res.pdn);
3233 if (mlx5_lag_is_lacp_owner(mdev))
3234 MLX5_SET(tisc, tisc, strict_lag_tx_port_affinity, 1);
3236 return mlx5_core_create_tis(mdev, in, tisn);
3239 void mlx5e_destroy_tis(struct mlx5_core_dev *mdev, u32 tisn)
3241 mlx5_core_destroy_tis(mdev, tisn);
3244 void mlx5e_destroy_tises(struct mlx5e_priv *priv)
3248 for (i = 0; i < mlx5e_get_num_lag_ports(priv->mdev); i++)
3249 for (tc = 0; tc < priv->profile->max_tc; tc++)
3250 mlx5e_destroy_tis(priv->mdev, priv->tisn[i][tc]);
3253 static bool mlx5e_lag_should_assign_affinity(struct mlx5_core_dev *mdev)
3255 return MLX5_CAP_GEN(mdev, lag_tx_port_affinity) && mlx5e_get_num_lag_ports(mdev) > 1;
3258 int mlx5e_create_tises(struct mlx5e_priv *priv)
3263 for (i = 0; i < mlx5e_get_num_lag_ports(priv->mdev); i++) {
3264 for (tc = 0; tc < priv->profile->max_tc; tc++) {
3265 u32 in[MLX5_ST_SZ_DW(create_tis_in)] = {};
3268 tisc = MLX5_ADDR_OF(create_tis_in, in, ctx);
3270 MLX5_SET(tisc, tisc, prio, tc << 1);
3272 if (mlx5e_lag_should_assign_affinity(priv->mdev))
3273 MLX5_SET(tisc, tisc, lag_tx_port_affinity, i + 1);
3275 err = mlx5e_create_tis(priv->mdev, in, &priv->tisn[i][tc]);
3277 goto err_close_tises;
3284 for (; i >= 0; i--) {
3285 for (tc--; tc >= 0; tc--)
3286 mlx5e_destroy_tis(priv->mdev, priv->tisn[i][tc]);
3287 tc = priv->profile->max_tc;
3293 static void mlx5e_cleanup_nic_tx(struct mlx5e_priv *priv)
3295 mlx5e_destroy_tises(priv);
3298 static void mlx5e_build_indir_tir_ctx_common(struct mlx5e_priv *priv,
3299 u32 rqtn, u32 *tirc)
3301 MLX5_SET(tirc, tirc, transport_domain, priv->mdev->mlx5e_res.td.tdn);
3302 MLX5_SET(tirc, tirc, disp_type, MLX5_TIRC_DISP_TYPE_INDIRECT);
3303 MLX5_SET(tirc, tirc, indirect_table, rqtn);
3304 MLX5_SET(tirc, tirc, tunneled_offload_en,
3305 priv->channels.params.tunneled_offload_en);
3307 mlx5e_build_tir_ctx_lro(&priv->channels.params, tirc);
3310 static void mlx5e_build_indir_tir_ctx(struct mlx5e_priv *priv,
3311 enum mlx5e_traffic_types tt,
3314 mlx5e_build_indir_tir_ctx_common(priv, priv->indir_rqt.rqtn, tirc);
3315 mlx5e_build_indir_tir_ctx_hash(&priv->rss_params,
3316 &tirc_default_config[tt], tirc, false);
3319 static void mlx5e_build_direct_tir_ctx(struct mlx5e_priv *priv, u32 rqtn, u32 *tirc)
3321 mlx5e_build_indir_tir_ctx_common(priv, rqtn, tirc);
3322 MLX5_SET(tirc, tirc, rx_hash_fn, MLX5_RX_HASH_FN_INVERTED_XOR8);
3325 static void mlx5e_build_inner_indir_tir_ctx(struct mlx5e_priv *priv,
3326 enum mlx5e_traffic_types tt,
3329 mlx5e_build_indir_tir_ctx_common(priv, priv->indir_rqt.rqtn, tirc);
3330 mlx5e_build_indir_tir_ctx_hash(&priv->rss_params,
3331 &tirc_default_config[tt], tirc, true);
3334 int mlx5e_create_indirect_tirs(struct mlx5e_priv *priv, bool inner_ttc)
3336 struct mlx5e_tir *tir;
3344 inlen = MLX5_ST_SZ_BYTES(create_tir_in);
3345 in = kvzalloc(inlen, GFP_KERNEL);
3349 for (tt = 0; tt < MLX5E_NUM_INDIR_TIRS; tt++) {
3350 memset(in, 0, inlen);
3351 tir = &priv->indir_tir[tt];
3352 tirc = MLX5_ADDR_OF(create_tir_in, in, ctx);
3353 mlx5e_build_indir_tir_ctx(priv, tt, tirc);
3354 err = mlx5e_create_tir(priv->mdev, tir, in);
3356 mlx5_core_warn(priv->mdev, "create indirect tirs failed, %d\n", err);
3357 goto err_destroy_inner_tirs;
3361 if (!inner_ttc || !mlx5e_tunnel_inner_ft_supported(priv->mdev))
3364 for (i = 0; i < MLX5E_NUM_INDIR_TIRS; i++) {
3365 memset(in, 0, inlen);
3366 tir = &priv->inner_indir_tir[i];
3367 tirc = MLX5_ADDR_OF(create_tir_in, in, ctx);
3368 mlx5e_build_inner_indir_tir_ctx(priv, i, tirc);
3369 err = mlx5e_create_tir(priv->mdev, tir, in);
3371 mlx5_core_warn(priv->mdev, "create inner indirect tirs failed, %d\n", err);
3372 goto err_destroy_inner_tirs;
3381 err_destroy_inner_tirs:
3382 for (i--; i >= 0; i--)
3383 mlx5e_destroy_tir(priv->mdev, &priv->inner_indir_tir[i]);
3385 for (tt--; tt >= 0; tt--)
3386 mlx5e_destroy_tir(priv->mdev, &priv->indir_tir[tt]);
3393 int mlx5e_create_direct_tirs(struct mlx5e_priv *priv, struct mlx5e_tir *tirs)
3395 struct mlx5e_tir *tir;
3402 inlen = MLX5_ST_SZ_BYTES(create_tir_in);
3403 in = kvzalloc(inlen, GFP_KERNEL);
3407 for (ix = 0; ix < priv->max_nch; ix++) {
3408 memset(in, 0, inlen);
3410 tirc = MLX5_ADDR_OF(create_tir_in, in, ctx);
3411 mlx5e_build_direct_tir_ctx(priv, tir->rqt.rqtn, tirc);
3412 err = mlx5e_create_tir(priv->mdev, tir, in);
3414 goto err_destroy_ch_tirs;
3419 err_destroy_ch_tirs:
3420 mlx5_core_warn(priv->mdev, "create tirs failed, %d\n", err);
3421 for (ix--; ix >= 0; ix--)
3422 mlx5e_destroy_tir(priv->mdev, &tirs[ix]);
3430 void mlx5e_destroy_indirect_tirs(struct mlx5e_priv *priv)
3434 for (i = 0; i < MLX5E_NUM_INDIR_TIRS; i++)
3435 mlx5e_destroy_tir(priv->mdev, &priv->indir_tir[i]);
3437 /* Verify inner tirs resources allocated */
3438 if (!priv->inner_indir_tir[0].tirn)
3441 for (i = 0; i < MLX5E_NUM_INDIR_TIRS; i++)
3442 mlx5e_destroy_tir(priv->mdev, &priv->inner_indir_tir[i]);
3445 void mlx5e_destroy_direct_tirs(struct mlx5e_priv *priv, struct mlx5e_tir *tirs)
3449 for (i = 0; i < priv->max_nch; i++)
3450 mlx5e_destroy_tir(priv->mdev, &tirs[i]);
3453 static int mlx5e_modify_channels_scatter_fcs(struct mlx5e_channels *chs, bool enable)
3458 for (i = 0; i < chs->num; i++) {
3459 err = mlx5e_modify_rq_scatter_fcs(&chs->c[i]->rq, enable);
3467 static int mlx5e_modify_channels_vsd(struct mlx5e_channels *chs, bool vsd)
3472 for (i = 0; i < chs->num; i++) {
3473 err = mlx5e_modify_rq_vsd(&chs->c[i]->rq, vsd);
3481 static int mlx5e_setup_tc_mqprio(struct mlx5e_priv *priv,
3482 struct tc_mqprio_qopt *mqprio)
3484 struct mlx5e_channels new_channels = {};
3485 u8 tc = mqprio->num_tc;
3488 mqprio->hw = TC_MQPRIO_HW_OFFLOAD_TCS;
3490 if (tc && tc != MLX5E_MAX_NUM_TC)
3493 mutex_lock(&priv->state_lock);
3495 new_channels.params = priv->channels.params;
3496 new_channels.params.num_tc = tc ? tc : 1;
3498 if (!test_bit(MLX5E_STATE_OPENED, &priv->state)) {
3499 priv->channels.params = new_channels.params;
3503 err = mlx5e_safe_switch_channels(priv, &new_channels,
3504 mlx5e_num_channels_changed_ctx, NULL);
3508 priv->max_opened_tc = max_t(u8, priv->max_opened_tc,
3509 new_channels.params.num_tc);
3511 mutex_unlock(&priv->state_lock);
3515 static LIST_HEAD(mlx5e_block_cb_list);
3517 static int mlx5e_setup_tc(struct net_device *dev, enum tc_setup_type type,
3520 struct mlx5e_priv *priv = netdev_priv(dev);
3523 case TC_SETUP_BLOCK: {
3524 struct flow_block_offload *f = type_data;
3526 f->unlocked_driver_cb = true;
3527 return flow_block_cb_setup_simple(type_data,
3528 &mlx5e_block_cb_list,
3529 mlx5e_setup_tc_block_cb,
3532 case TC_SETUP_QDISC_MQPRIO:
3533 return mlx5e_setup_tc_mqprio(priv, type_data);
3539 void mlx5e_fold_sw_stats64(struct mlx5e_priv *priv, struct rtnl_link_stats64 *s)
3543 for (i = 0; i < priv->max_nch; i++) {
3544 struct mlx5e_channel_stats *channel_stats = &priv->channel_stats[i];
3545 struct mlx5e_rq_stats *xskrq_stats = &channel_stats->xskrq;
3546 struct mlx5e_rq_stats *rq_stats = &channel_stats->rq;
3549 s->rx_packets += rq_stats->packets + xskrq_stats->packets;
3550 s->rx_bytes += rq_stats->bytes + xskrq_stats->bytes;
3552 for (j = 0; j < priv->max_opened_tc; j++) {
3553 struct mlx5e_sq_stats *sq_stats = &channel_stats->sq[j];
3555 s->tx_packets += sq_stats->packets;
3556 s->tx_bytes += sq_stats->bytes;
3557 s->tx_dropped += sq_stats->dropped;
3563 mlx5e_get_stats(struct net_device *dev, struct rtnl_link_stats64 *stats)
3565 struct mlx5e_priv *priv = netdev_priv(dev);
3566 struct mlx5e_vport_stats *vstats = &priv->stats.vport;
3567 struct mlx5e_pport_stats *pstats = &priv->stats.pport;
3569 /* In switchdev mode, monitor counters doesn't monitor
3570 * rx/tx stats of 802_3. The update stats mechanism
3571 * should keep the 802_3 layout counters updated
3573 if (!mlx5e_monitor_counter_supported(priv) ||
3574 mlx5e_is_uplink_rep(priv)) {
3575 /* update HW stats in background for next time */
3576 mlx5e_queue_update_stats(priv);
3579 if (mlx5e_is_uplink_rep(priv)) {
3580 stats->rx_packets = PPORT_802_3_GET(pstats, a_frames_received_ok);
3581 stats->rx_bytes = PPORT_802_3_GET(pstats, a_octets_received_ok);
3582 stats->tx_packets = PPORT_802_3_GET(pstats, a_frames_transmitted_ok);
3583 stats->tx_bytes = PPORT_802_3_GET(pstats, a_octets_transmitted_ok);
3585 mlx5e_fold_sw_stats64(priv, stats);
3588 stats->rx_dropped = priv->stats.qcnt.rx_out_of_buffer;
3590 stats->rx_length_errors =
3591 PPORT_802_3_GET(pstats, a_in_range_length_errors) +
3592 PPORT_802_3_GET(pstats, a_out_of_range_length_field) +
3593 PPORT_802_3_GET(pstats, a_frame_too_long_errors);
3594 stats->rx_crc_errors =
3595 PPORT_802_3_GET(pstats, a_frame_check_sequence_errors);
3596 stats->rx_frame_errors = PPORT_802_3_GET(pstats, a_alignment_errors);
3597 stats->tx_aborted_errors = PPORT_2863_GET(pstats, if_out_discards);
3598 stats->rx_errors = stats->rx_length_errors + stats->rx_crc_errors +
3599 stats->rx_frame_errors;
3600 stats->tx_errors = stats->tx_aborted_errors + stats->tx_carrier_errors;
3602 /* vport multicast also counts packets that are dropped due to steering
3603 * or rx out of buffer
3606 VPORT_COUNTER_GET(vstats, received_eth_multicast.packets);
3609 static void mlx5e_set_rx_mode(struct net_device *dev)
3611 struct mlx5e_priv *priv = netdev_priv(dev);
3613 queue_work(priv->wq, &priv->set_rx_mode_work);
3616 static int mlx5e_set_mac(struct net_device *netdev, void *addr)
3618 struct mlx5e_priv *priv = netdev_priv(netdev);
3619 struct sockaddr *saddr = addr;
3621 if (!is_valid_ether_addr(saddr->sa_data))
3622 return -EADDRNOTAVAIL;
3624 netif_addr_lock_bh(netdev);
3625 ether_addr_copy(netdev->dev_addr, saddr->sa_data);
3626 netif_addr_unlock_bh(netdev);
3628 queue_work(priv->wq, &priv->set_rx_mode_work);
3633 #define MLX5E_SET_FEATURE(features, feature, enable) \
3636 *features |= feature; \
3638 *features &= ~feature; \
3641 typedef int (*mlx5e_feature_handler)(struct net_device *netdev, bool enable);
3643 static int set_feature_lro(struct net_device *netdev, bool enable)
3645 struct mlx5e_priv *priv = netdev_priv(netdev);
3646 struct mlx5_core_dev *mdev = priv->mdev;
3647 struct mlx5e_channels new_channels = {};
3648 struct mlx5e_params *old_params;
3652 mutex_lock(&priv->state_lock);
3654 if (enable && priv->xsk.refcnt) {
3655 netdev_warn(netdev, "LRO is incompatible with AF_XDP (%hu XSKs are active)\n",
3661 old_params = &priv->channels.params;
3662 if (enable && !MLX5E_GET_PFLAG(old_params, MLX5E_PFLAG_RX_STRIDING_RQ)) {
3663 netdev_warn(netdev, "can't set LRO with legacy RQ\n");
3668 reset = test_bit(MLX5E_STATE_OPENED, &priv->state);
3670 new_channels.params = *old_params;
3671 new_channels.params.lro_en = enable;
3673 if (old_params->rq_wq_type != MLX5_WQ_TYPE_CYCLIC) {
3674 if (mlx5e_rx_mpwqe_is_linear_skb(mdev, old_params, NULL) ==
3675 mlx5e_rx_mpwqe_is_linear_skb(mdev, &new_channels.params, NULL))
3680 *old_params = new_channels.params;
3681 err = mlx5e_modify_tirs_lro(priv);
3685 err = mlx5e_safe_switch_channels(priv, &new_channels,
3686 mlx5e_modify_tirs_lro_ctx, NULL);
3688 mutex_unlock(&priv->state_lock);
3692 static int set_feature_cvlan_filter(struct net_device *netdev, bool enable)
3694 struct mlx5e_priv *priv = netdev_priv(netdev);
3697 mlx5e_enable_cvlan_filter(priv);
3699 mlx5e_disable_cvlan_filter(priv);
3704 #if IS_ENABLED(CONFIG_MLX5_CLS_ACT)
3705 static int set_feature_tc_num_filters(struct net_device *netdev, bool enable)
3707 struct mlx5e_priv *priv = netdev_priv(netdev);
3709 if (!enable && mlx5e_tc_num_filters(priv, MLX5_TC_FLAG(NIC_OFFLOAD))) {
3711 "Active offloaded tc filters, can't turn hw_tc_offload off\n");
3719 static int set_feature_rx_all(struct net_device *netdev, bool enable)
3721 struct mlx5e_priv *priv = netdev_priv(netdev);
3722 struct mlx5_core_dev *mdev = priv->mdev;
3724 return mlx5_set_port_fcs(mdev, !enable);
3727 static int set_feature_rx_fcs(struct net_device *netdev, bool enable)
3729 struct mlx5e_priv *priv = netdev_priv(netdev);
3732 mutex_lock(&priv->state_lock);
3734 priv->channels.params.scatter_fcs_en = enable;
3735 err = mlx5e_modify_channels_scatter_fcs(&priv->channels, enable);
3737 priv->channels.params.scatter_fcs_en = !enable;
3739 mutex_unlock(&priv->state_lock);
3744 static int set_feature_rx_vlan(struct net_device *netdev, bool enable)
3746 struct mlx5e_priv *priv = netdev_priv(netdev);
3749 mutex_lock(&priv->state_lock);
3751 priv->channels.params.vlan_strip_disable = !enable;
3752 if (!test_bit(MLX5E_STATE_OPENED, &priv->state))
3755 err = mlx5e_modify_channels_vsd(&priv->channels, !enable);
3757 priv->channels.params.vlan_strip_disable = enable;
3760 mutex_unlock(&priv->state_lock);
3765 #ifdef CONFIG_MLX5_EN_ARFS
3766 static int set_feature_arfs(struct net_device *netdev, bool enable)
3768 struct mlx5e_priv *priv = netdev_priv(netdev);
3772 err = mlx5e_arfs_enable(priv);
3774 err = mlx5e_arfs_disable(priv);
3780 static int mlx5e_handle_feature(struct net_device *netdev,
3781 netdev_features_t *features,
3782 netdev_features_t wanted_features,
3783 netdev_features_t feature,
3784 mlx5e_feature_handler feature_handler)
3786 netdev_features_t changes = wanted_features ^ netdev->features;
3787 bool enable = !!(wanted_features & feature);
3790 if (!(changes & feature))
3793 err = feature_handler(netdev, enable);
3795 netdev_err(netdev, "%s feature %pNF failed, err %d\n",
3796 enable ? "Enable" : "Disable", &feature, err);
3800 MLX5E_SET_FEATURE(features, feature, enable);
3804 int mlx5e_set_features(struct net_device *netdev, netdev_features_t features)
3806 netdev_features_t oper_features = netdev->features;
3809 #define MLX5E_HANDLE_FEATURE(feature, handler) \
3810 mlx5e_handle_feature(netdev, &oper_features, features, feature, handler)
3812 err |= MLX5E_HANDLE_FEATURE(NETIF_F_LRO, set_feature_lro);
3813 err |= MLX5E_HANDLE_FEATURE(NETIF_F_HW_VLAN_CTAG_FILTER,
3814 set_feature_cvlan_filter);
3815 #if IS_ENABLED(CONFIG_MLX5_CLS_ACT)
3816 err |= MLX5E_HANDLE_FEATURE(NETIF_F_HW_TC, set_feature_tc_num_filters);
3818 err |= MLX5E_HANDLE_FEATURE(NETIF_F_RXALL, set_feature_rx_all);
3819 err |= MLX5E_HANDLE_FEATURE(NETIF_F_RXFCS, set_feature_rx_fcs);
3820 err |= MLX5E_HANDLE_FEATURE(NETIF_F_HW_VLAN_CTAG_RX, set_feature_rx_vlan);
3821 #ifdef CONFIG_MLX5_EN_ARFS
3822 err |= MLX5E_HANDLE_FEATURE(NETIF_F_NTUPLE, set_feature_arfs);
3824 err |= MLX5E_HANDLE_FEATURE(NETIF_F_HW_TLS_RX, mlx5e_ktls_set_feature_rx);
3827 netdev->features = oper_features;
3834 static netdev_features_t mlx5e_fix_features(struct net_device *netdev,
3835 netdev_features_t features)
3837 struct mlx5e_priv *priv = netdev_priv(netdev);
3838 struct mlx5e_params *params;
3840 mutex_lock(&priv->state_lock);
3841 params = &priv->channels.params;
3842 if (!bitmap_empty(priv->fs.vlan.active_svlans, VLAN_N_VID)) {
3843 /* HW strips the outer C-tag header, this is a problem
3844 * for S-tag traffic.
3846 features &= ~NETIF_F_HW_VLAN_CTAG_RX;
3847 if (!params->vlan_strip_disable)
3848 netdev_warn(netdev, "Dropping C-tag vlan stripping offload due to S-tag vlan\n");
3850 if (!MLX5E_GET_PFLAG(params, MLX5E_PFLAG_RX_STRIDING_RQ)) {
3851 if (features & NETIF_F_LRO) {
3852 netdev_warn(netdev, "Disabling LRO, not supported in legacy RQ\n");
3853 features &= ~NETIF_F_LRO;
3857 if (MLX5E_GET_PFLAG(params, MLX5E_PFLAG_RX_CQE_COMPRESS)) {
3858 features &= ~NETIF_F_RXHASH;
3859 if (netdev->features & NETIF_F_RXHASH)
3860 netdev_warn(netdev, "Disabling rxhash, not supported when CQE compress is active\n");
3863 mutex_unlock(&priv->state_lock);
3868 static bool mlx5e_xsk_validate_mtu(struct net_device *netdev,
3869 struct mlx5e_channels *chs,
3870 struct mlx5e_params *new_params,
3871 struct mlx5_core_dev *mdev)
3875 for (ix = 0; ix < chs->params.num_channels; ix++) {
3876 struct xdp_umem *umem = mlx5e_xsk_get_umem(&chs->params, chs->params.xsk, ix);
3877 struct mlx5e_xsk_param xsk;
3882 mlx5e_build_xsk_param(umem, &xsk);
3884 if (!mlx5e_validate_xsk_param(new_params, &xsk, mdev)) {
3885 u32 hr = mlx5e_get_linear_rq_headroom(new_params, &xsk);
3886 int max_mtu_frame, max_mtu_page, max_mtu;
3888 /* Two criteria must be met:
3889 * 1. HW MTU + all headrooms <= XSK frame size.
3890 * 2. Size of SKBs allocated on XDP_PASS <= PAGE_SIZE.
3892 max_mtu_frame = MLX5E_HW2SW_MTU(new_params, xsk.chunk_size - hr);
3893 max_mtu_page = mlx5e_xdp_max_mtu(new_params, &xsk);
3894 max_mtu = min(max_mtu_frame, max_mtu_page);
3896 netdev_err(netdev, "MTU %d is too big for an XSK running on channel %hu. Try MTU <= %d\n",
3897 new_params->sw_mtu, ix, max_mtu);
3905 int mlx5e_change_mtu(struct net_device *netdev, int new_mtu,
3906 mlx5e_fp_preactivate preactivate)
3908 struct mlx5e_priv *priv = netdev_priv(netdev);
3909 struct mlx5e_channels new_channels = {};
3910 struct mlx5e_params *params;
3914 mutex_lock(&priv->state_lock);
3916 params = &priv->channels.params;
3918 reset = !params->lro_en;
3919 reset = reset && test_bit(MLX5E_STATE_OPENED, &priv->state);
3921 new_channels.params = *params;
3922 new_channels.params.sw_mtu = new_mtu;
3924 if (params->xdp_prog &&
3925 !mlx5e_rx_is_linear_skb(&new_channels.params, NULL)) {
3926 netdev_err(netdev, "MTU(%d) > %d is not allowed while XDP enabled\n",
3927 new_mtu, mlx5e_xdp_max_mtu(params, NULL));
3932 if (priv->xsk.refcnt &&
3933 !mlx5e_xsk_validate_mtu(netdev, &priv->channels,
3934 &new_channels.params, priv->mdev)) {
3939 if (params->rq_wq_type == MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ) {
3940 bool is_linear = mlx5e_rx_mpwqe_is_linear_skb(priv->mdev,
3941 &new_channels.params,
3943 u8 ppw_old = mlx5e_mpwqe_log_pkts_per_wqe(params, NULL);
3944 u8 ppw_new = mlx5e_mpwqe_log_pkts_per_wqe(&new_channels.params, NULL);
3946 /* If XSK is active, XSK RQs are linear. */
3947 is_linear |= priv->xsk.refcnt;
3949 /* Always reset in linear mode - hw_mtu is used in data path. */
3950 reset = reset && (is_linear || (ppw_old != ppw_new));
3954 params->sw_mtu = new_mtu;
3956 preactivate(priv, NULL);
3957 netdev->mtu = params->sw_mtu;
3961 err = mlx5e_safe_switch_channels(priv, &new_channels, preactivate, NULL);
3965 netdev->mtu = new_channels.params.sw_mtu;
3968 mutex_unlock(&priv->state_lock);
3972 static int mlx5e_change_nic_mtu(struct net_device *netdev, int new_mtu)
3974 return mlx5e_change_mtu(netdev, new_mtu, mlx5e_set_dev_port_mtu_ctx);
3977 int mlx5e_hwstamp_set(struct mlx5e_priv *priv, struct ifreq *ifr)
3979 struct hwtstamp_config config;
3982 if (!MLX5_CAP_GEN(priv->mdev, device_frequency_khz) ||
3983 (mlx5_clock_get_ptp_index(priv->mdev) == -1))
3986 if (copy_from_user(&config, ifr->ifr_data, sizeof(config)))
3989 /* TX HW timestamp */
3990 switch (config.tx_type) {
3991 case HWTSTAMP_TX_OFF:
3992 case HWTSTAMP_TX_ON:
3998 mutex_lock(&priv->state_lock);
3999 /* RX HW timestamp */
4000 switch (config.rx_filter) {
4001 case HWTSTAMP_FILTER_NONE:
4002 /* Reset CQE compression to Admin default */
4003 mlx5e_modify_rx_cqe_compression_locked(priv, priv->channels.params.rx_cqe_compress_def);
4005 case HWTSTAMP_FILTER_ALL:
4006 case HWTSTAMP_FILTER_SOME:
4007 case HWTSTAMP_FILTER_PTP_V1_L4_EVENT:
4008 case HWTSTAMP_FILTER_PTP_V1_L4_SYNC:
4009 case HWTSTAMP_FILTER_PTP_V1_L4_DELAY_REQ:
4010 case HWTSTAMP_FILTER_PTP_V2_L4_EVENT:
4011 case HWTSTAMP_FILTER_PTP_V2_L4_SYNC:
4012 case HWTSTAMP_FILTER_PTP_V2_L4_DELAY_REQ:
4013 case HWTSTAMP_FILTER_PTP_V2_L2_EVENT:
4014 case HWTSTAMP_FILTER_PTP_V2_L2_SYNC:
4015 case HWTSTAMP_FILTER_PTP_V2_L2_DELAY_REQ:
4016 case HWTSTAMP_FILTER_PTP_V2_EVENT:
4017 case HWTSTAMP_FILTER_PTP_V2_SYNC:
4018 case HWTSTAMP_FILTER_PTP_V2_DELAY_REQ:
4019 case HWTSTAMP_FILTER_NTP_ALL:
4020 /* Disable CQE compression */
4021 if (MLX5E_GET_PFLAG(&priv->channels.params, MLX5E_PFLAG_RX_CQE_COMPRESS))
4022 netdev_warn(priv->netdev, "Disabling RX cqe compression\n");
4023 err = mlx5e_modify_rx_cqe_compression_locked(priv, false);
4025 netdev_err(priv->netdev, "Failed disabling cqe compression err=%d\n", err);
4026 mutex_unlock(&priv->state_lock);
4029 config.rx_filter = HWTSTAMP_FILTER_ALL;
4032 mutex_unlock(&priv->state_lock);
4036 memcpy(&priv->tstamp, &config, sizeof(config));
4037 mutex_unlock(&priv->state_lock);
4039 /* might need to fix some features */
4040 netdev_update_features(priv->netdev);
4042 return copy_to_user(ifr->ifr_data, &config,
4043 sizeof(config)) ? -EFAULT : 0;
4046 int mlx5e_hwstamp_get(struct mlx5e_priv *priv, struct ifreq *ifr)
4048 struct hwtstamp_config *cfg = &priv->tstamp;
4050 if (!MLX5_CAP_GEN(priv->mdev, device_frequency_khz))
4053 return copy_to_user(ifr->ifr_data, cfg, sizeof(*cfg)) ? -EFAULT : 0;
4056 static int mlx5e_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
4058 struct mlx5e_priv *priv = netdev_priv(dev);
4062 return mlx5e_hwstamp_set(priv, ifr);
4064 return mlx5e_hwstamp_get(priv, ifr);
4070 #ifdef CONFIG_MLX5_ESWITCH
4071 int mlx5e_set_vf_mac(struct net_device *dev, int vf, u8 *mac)
4073 struct mlx5e_priv *priv = netdev_priv(dev);
4074 struct mlx5_core_dev *mdev = priv->mdev;
4076 return mlx5_eswitch_set_vport_mac(mdev->priv.eswitch, vf + 1, mac);
4079 static int mlx5e_set_vf_vlan(struct net_device *dev, int vf, u16 vlan, u8 qos,
4082 struct mlx5e_priv *priv = netdev_priv(dev);
4083 struct mlx5_core_dev *mdev = priv->mdev;
4085 if (vlan_proto != htons(ETH_P_8021Q))
4086 return -EPROTONOSUPPORT;
4088 return mlx5_eswitch_set_vport_vlan(mdev->priv.eswitch, vf + 1,
4092 static int mlx5e_set_vf_spoofchk(struct net_device *dev, int vf, bool setting)
4094 struct mlx5e_priv *priv = netdev_priv(dev);
4095 struct mlx5_core_dev *mdev = priv->mdev;
4097 return mlx5_eswitch_set_vport_spoofchk(mdev->priv.eswitch, vf + 1, setting);
4100 static int mlx5e_set_vf_trust(struct net_device *dev, int vf, bool setting)
4102 struct mlx5e_priv *priv = netdev_priv(dev);
4103 struct mlx5_core_dev *mdev = priv->mdev;
4105 return mlx5_eswitch_set_vport_trust(mdev->priv.eswitch, vf + 1, setting);
4108 int mlx5e_set_vf_rate(struct net_device *dev, int vf, int min_tx_rate,
4111 struct mlx5e_priv *priv = netdev_priv(dev);
4112 struct mlx5_core_dev *mdev = priv->mdev;
4114 return mlx5_eswitch_set_vport_rate(mdev->priv.eswitch, vf + 1,
4115 max_tx_rate, min_tx_rate);
4118 static int mlx5_vport_link2ifla(u8 esw_link)
4121 case MLX5_VPORT_ADMIN_STATE_DOWN:
4122 return IFLA_VF_LINK_STATE_DISABLE;
4123 case MLX5_VPORT_ADMIN_STATE_UP:
4124 return IFLA_VF_LINK_STATE_ENABLE;
4126 return IFLA_VF_LINK_STATE_AUTO;
4129 static int mlx5_ifla_link2vport(u8 ifla_link)
4131 switch (ifla_link) {
4132 case IFLA_VF_LINK_STATE_DISABLE:
4133 return MLX5_VPORT_ADMIN_STATE_DOWN;
4134 case IFLA_VF_LINK_STATE_ENABLE:
4135 return MLX5_VPORT_ADMIN_STATE_UP;
4137 return MLX5_VPORT_ADMIN_STATE_AUTO;
4140 static int mlx5e_set_vf_link_state(struct net_device *dev, int vf,
4143 struct mlx5e_priv *priv = netdev_priv(dev);
4144 struct mlx5_core_dev *mdev = priv->mdev;
4146 return mlx5_eswitch_set_vport_state(mdev->priv.eswitch, vf + 1,
4147 mlx5_ifla_link2vport(link_state));
4150 int mlx5e_get_vf_config(struct net_device *dev,
4151 int vf, struct ifla_vf_info *ivi)
4153 struct mlx5e_priv *priv = netdev_priv(dev);
4154 struct mlx5_core_dev *mdev = priv->mdev;
4157 err = mlx5_eswitch_get_vport_config(mdev->priv.eswitch, vf + 1, ivi);
4160 ivi->linkstate = mlx5_vport_link2ifla(ivi->linkstate);
4164 int mlx5e_get_vf_stats(struct net_device *dev,
4165 int vf, struct ifla_vf_stats *vf_stats)
4167 struct mlx5e_priv *priv = netdev_priv(dev);
4168 struct mlx5_core_dev *mdev = priv->mdev;
4170 return mlx5_eswitch_get_vport_stats(mdev->priv.eswitch, vf + 1,
4175 struct mlx5e_vxlan_work {
4176 struct work_struct work;
4177 struct mlx5e_priv *priv;
4181 static void mlx5e_vxlan_add_work(struct work_struct *work)
4183 struct mlx5e_vxlan_work *vxlan_work =
4184 container_of(work, struct mlx5e_vxlan_work, work);
4185 struct mlx5e_priv *priv = vxlan_work->priv;
4186 u16 port = vxlan_work->port;
4188 mutex_lock(&priv->state_lock);
4189 mlx5_vxlan_add_port(priv->mdev->vxlan, port);
4190 mutex_unlock(&priv->state_lock);
4195 static void mlx5e_vxlan_del_work(struct work_struct *work)
4197 struct mlx5e_vxlan_work *vxlan_work =
4198 container_of(work, struct mlx5e_vxlan_work, work);
4199 struct mlx5e_priv *priv = vxlan_work->priv;
4200 u16 port = vxlan_work->port;
4202 mutex_lock(&priv->state_lock);
4203 mlx5_vxlan_del_port(priv->mdev->vxlan, port);
4204 mutex_unlock(&priv->state_lock);
4208 static void mlx5e_vxlan_queue_work(struct mlx5e_priv *priv, u16 port, int add)
4210 struct mlx5e_vxlan_work *vxlan_work;
4212 vxlan_work = kmalloc(sizeof(*vxlan_work), GFP_ATOMIC);
4217 INIT_WORK(&vxlan_work->work, mlx5e_vxlan_add_work);
4219 INIT_WORK(&vxlan_work->work, mlx5e_vxlan_del_work);
4221 vxlan_work->priv = priv;
4222 vxlan_work->port = port;
4223 queue_work(priv->wq, &vxlan_work->work);
4226 void mlx5e_add_vxlan_port(struct net_device *netdev, struct udp_tunnel_info *ti)
4228 struct mlx5e_priv *priv = netdev_priv(netdev);
4230 if (ti->type != UDP_TUNNEL_TYPE_VXLAN)
4233 if (!mlx5_vxlan_allowed(priv->mdev->vxlan))
4236 mlx5e_vxlan_queue_work(priv, be16_to_cpu(ti->port), 1);
4239 void mlx5e_del_vxlan_port(struct net_device *netdev, struct udp_tunnel_info *ti)
4241 struct mlx5e_priv *priv = netdev_priv(netdev);
4243 if (ti->type != UDP_TUNNEL_TYPE_VXLAN)
4246 if (!mlx5_vxlan_allowed(priv->mdev->vxlan))
4249 mlx5e_vxlan_queue_work(priv, be16_to_cpu(ti->port), 0);
4252 static netdev_features_t mlx5e_tunnel_features_check(struct mlx5e_priv *priv,
4253 struct sk_buff *skb,
4254 netdev_features_t features)
4256 unsigned int offset = 0;
4257 struct udphdr *udph;
4261 switch (vlan_get_protocol(skb)) {
4262 case htons(ETH_P_IP):
4263 proto = ip_hdr(skb)->protocol;
4265 case htons(ETH_P_IPV6):
4266 proto = ipv6_find_hdr(skb, &offset, -1, NULL, NULL);
4277 if (mlx5e_tunnel_proto_supported(priv->mdev, IPPROTO_IPIP))
4281 udph = udp_hdr(skb);
4282 port = be16_to_cpu(udph->dest);
4284 /* Verify if UDP port is being offloaded by HW */
4285 if (mlx5_vxlan_lookup_port(priv->mdev->vxlan, port))
4288 #if IS_ENABLED(CONFIG_GENEVE)
4289 /* Support Geneve offload for default UDP port */
4290 if (port == GENEVE_UDP_PORT && mlx5_geneve_tx_allowed(priv->mdev))
4296 /* Disable CSUM and GSO if the udp dport is not offloaded by HW */
4297 return features & ~(NETIF_F_CSUM_MASK | NETIF_F_GSO_MASK);
4300 netdev_features_t mlx5e_features_check(struct sk_buff *skb,
4301 struct net_device *netdev,
4302 netdev_features_t features)
4304 struct mlx5e_priv *priv = netdev_priv(netdev);
4306 features = vlan_features_check(skb, features);
4307 features = vxlan_features_check(skb, features);
4309 #ifdef CONFIG_MLX5_EN_IPSEC
4310 if (mlx5e_ipsec_feature_check(skb, netdev, features))
4314 /* Validate if the tunneled packet is being offloaded by HW */
4315 if (skb->encapsulation &&
4316 (features & NETIF_F_CSUM_MASK || features & NETIF_F_GSO_MASK))
4317 return mlx5e_tunnel_features_check(priv, skb, features);
4322 static void mlx5e_tx_timeout_work(struct work_struct *work)
4324 struct mlx5e_priv *priv = container_of(work, struct mlx5e_priv,
4329 mutex_lock(&priv->state_lock);
4331 if (!test_bit(MLX5E_STATE_OPENED, &priv->state))
4334 for (i = 0; i < priv->channels.num * priv->channels.params.num_tc; i++) {
4335 struct netdev_queue *dev_queue =
4336 netdev_get_tx_queue(priv->netdev, i);
4337 struct mlx5e_txqsq *sq = priv->txq2sq[i];
4339 if (!netif_xmit_stopped(dev_queue))
4342 if (mlx5e_reporter_tx_timeout(sq))
4343 /* break if tried to reopened channels */
4348 mutex_unlock(&priv->state_lock);
4352 static void mlx5e_tx_timeout(struct net_device *dev, unsigned int txqueue)
4354 struct mlx5e_priv *priv = netdev_priv(dev);
4356 netdev_err(dev, "TX timeout detected\n");
4357 queue_work(priv->wq, &priv->tx_timeout_work);
4360 static int mlx5e_xdp_allowed(struct mlx5e_priv *priv, struct bpf_prog *prog)
4362 struct net_device *netdev = priv->netdev;
4363 struct mlx5e_channels new_channels = {};
4365 if (priv->channels.params.lro_en) {
4366 netdev_warn(netdev, "can't set XDP while LRO is on, disable LRO first\n");
4370 if (MLX5_IPSEC_DEV(priv->mdev)) {
4371 netdev_warn(netdev, "can't set XDP with IPSec offload\n");
4375 new_channels.params = priv->channels.params;
4376 new_channels.params.xdp_prog = prog;
4378 /* No XSK params: AF_XDP can't be enabled yet at the point of setting
4381 if (!mlx5e_rx_is_linear_skb(&new_channels.params, NULL)) {
4382 netdev_warn(netdev, "XDP is not allowed with MTU(%d) > %d\n",
4383 new_channels.params.sw_mtu,
4384 mlx5e_xdp_max_mtu(&new_channels.params, NULL));
4391 static int mlx5e_xdp_set(struct net_device *netdev, struct bpf_prog *prog)
4393 struct mlx5e_priv *priv = netdev_priv(netdev);
4394 struct bpf_prog *old_prog;
4395 bool reset, was_opened;
4399 mutex_lock(&priv->state_lock);
4402 err = mlx5e_xdp_allowed(priv, prog);
4407 was_opened = test_bit(MLX5E_STATE_OPENED, &priv->state);
4408 /* no need for full reset when exchanging programs */
4409 reset = (!priv->channels.params.xdp_prog || !prog);
4411 if (was_opened && !reset)
4412 /* num_channels is invariant here, so we can take the
4413 * batched reference right upfront.
4415 bpf_prog_add(prog, priv->channels.num);
4417 if (was_opened && reset) {
4418 struct mlx5e_channels new_channels = {};
4420 new_channels.params = priv->channels.params;
4421 new_channels.params.xdp_prog = prog;
4422 mlx5e_set_rq_type(priv->mdev, &new_channels.params);
4423 old_prog = priv->channels.params.xdp_prog;
4425 err = mlx5e_safe_switch_channels(priv, &new_channels, NULL, NULL);
4429 /* exchange programs, extra prog reference we got from caller
4430 * as long as we don't fail from this point onwards.
4432 old_prog = xchg(&priv->channels.params.xdp_prog, prog);
4436 bpf_prog_put(old_prog);
4438 if (!was_opened && reset) /* change RQ type according to priv->xdp_prog */
4439 mlx5e_set_rq_type(priv->mdev, &priv->channels.params);
4441 if (!was_opened || reset)
4444 /* exchanging programs w/o reset, we update ref counts on behalf
4445 * of the channels RQs here.
4447 for (i = 0; i < priv->channels.num; i++) {
4448 struct mlx5e_channel *c = priv->channels.c[i];
4449 bool xsk_open = test_bit(MLX5E_CHANNEL_STATE_XSK, c->state);
4451 clear_bit(MLX5E_RQ_STATE_ENABLED, &c->rq.state);
4453 clear_bit(MLX5E_RQ_STATE_ENABLED, &c->xskrq.state);
4454 napi_synchronize(&c->napi);
4455 /* prevent mlx5e_poll_rx_cq from accessing rq->xdp_prog */
4457 old_prog = xchg(&c->rq.xdp_prog, prog);
4459 bpf_prog_put(old_prog);
4462 old_prog = xchg(&c->xskrq.xdp_prog, prog);
4464 bpf_prog_put(old_prog);
4467 set_bit(MLX5E_RQ_STATE_ENABLED, &c->rq.state);
4469 set_bit(MLX5E_RQ_STATE_ENABLED, &c->xskrq.state);
4470 /* napi_schedule in case we have missed anything */
4471 napi_schedule(&c->napi);
4475 mutex_unlock(&priv->state_lock);
4479 static u32 mlx5e_xdp_query(struct net_device *dev)
4481 struct mlx5e_priv *priv = netdev_priv(dev);
4482 const struct bpf_prog *xdp_prog;
4485 mutex_lock(&priv->state_lock);
4486 xdp_prog = priv->channels.params.xdp_prog;
4488 prog_id = xdp_prog->aux->id;
4489 mutex_unlock(&priv->state_lock);
4494 static int mlx5e_xdp(struct net_device *dev, struct netdev_bpf *xdp)
4496 switch (xdp->command) {
4497 case XDP_SETUP_PROG:
4498 return mlx5e_xdp_set(dev, xdp->prog);
4499 case XDP_QUERY_PROG:
4500 xdp->prog_id = mlx5e_xdp_query(dev);
4502 case XDP_SETUP_XSK_UMEM:
4503 return mlx5e_xsk_setup_umem(dev, xdp->xsk.umem,
4510 #ifdef CONFIG_MLX5_ESWITCH
4511 static int mlx5e_bridge_getlink(struct sk_buff *skb, u32 pid, u32 seq,
4512 struct net_device *dev, u32 filter_mask,
4515 struct mlx5e_priv *priv = netdev_priv(dev);
4516 struct mlx5_core_dev *mdev = priv->mdev;
4520 err = mlx5_eswitch_get_vepa(mdev->priv.eswitch, &setting);
4523 mode = setting ? BRIDGE_MODE_VEPA : BRIDGE_MODE_VEB;
4524 return ndo_dflt_bridge_getlink(skb, pid, seq, dev,
4526 0, 0, nlflags, filter_mask, NULL);
4529 static int mlx5e_bridge_setlink(struct net_device *dev, struct nlmsghdr *nlh,
4530 u16 flags, struct netlink_ext_ack *extack)
4532 struct mlx5e_priv *priv = netdev_priv(dev);
4533 struct mlx5_core_dev *mdev = priv->mdev;
4534 struct nlattr *attr, *br_spec;
4535 u16 mode = BRIDGE_MODE_UNDEF;
4539 br_spec = nlmsg_find_attr(nlh, sizeof(struct ifinfomsg), IFLA_AF_SPEC);
4543 nla_for_each_nested(attr, br_spec, rem) {
4544 if (nla_type(attr) != IFLA_BRIDGE_MODE)
4547 if (nla_len(attr) < sizeof(mode))
4550 mode = nla_get_u16(attr);
4551 if (mode > BRIDGE_MODE_VEPA)
4557 if (mode == BRIDGE_MODE_UNDEF)
4560 setting = (mode == BRIDGE_MODE_VEPA) ? 1 : 0;
4561 return mlx5_eswitch_set_vepa(mdev->priv.eswitch, setting);
4565 const struct net_device_ops mlx5e_netdev_ops = {
4566 .ndo_open = mlx5e_open,
4567 .ndo_stop = mlx5e_close,
4568 .ndo_start_xmit = mlx5e_xmit,
4569 .ndo_setup_tc = mlx5e_setup_tc,
4570 .ndo_select_queue = mlx5e_select_queue,
4571 .ndo_get_stats64 = mlx5e_get_stats,
4572 .ndo_set_rx_mode = mlx5e_set_rx_mode,
4573 .ndo_set_mac_address = mlx5e_set_mac,
4574 .ndo_vlan_rx_add_vid = mlx5e_vlan_rx_add_vid,
4575 .ndo_vlan_rx_kill_vid = mlx5e_vlan_rx_kill_vid,
4576 .ndo_set_features = mlx5e_set_features,
4577 .ndo_fix_features = mlx5e_fix_features,
4578 .ndo_change_mtu = mlx5e_change_nic_mtu,
4579 .ndo_do_ioctl = mlx5e_ioctl,
4580 .ndo_set_tx_maxrate = mlx5e_set_tx_maxrate,
4581 .ndo_udp_tunnel_add = mlx5e_add_vxlan_port,
4582 .ndo_udp_tunnel_del = mlx5e_del_vxlan_port,
4583 .ndo_features_check = mlx5e_features_check,
4584 .ndo_tx_timeout = mlx5e_tx_timeout,
4585 .ndo_bpf = mlx5e_xdp,
4586 .ndo_xdp_xmit = mlx5e_xdp_xmit,
4587 .ndo_xsk_wakeup = mlx5e_xsk_wakeup,
4588 #ifdef CONFIG_MLX5_EN_ARFS
4589 .ndo_rx_flow_steer = mlx5e_rx_flow_steer,
4591 #ifdef CONFIG_MLX5_ESWITCH
4592 .ndo_bridge_setlink = mlx5e_bridge_setlink,
4593 .ndo_bridge_getlink = mlx5e_bridge_getlink,
4595 /* SRIOV E-Switch NDOs */
4596 .ndo_set_vf_mac = mlx5e_set_vf_mac,
4597 .ndo_set_vf_vlan = mlx5e_set_vf_vlan,
4598 .ndo_set_vf_spoofchk = mlx5e_set_vf_spoofchk,
4599 .ndo_set_vf_trust = mlx5e_set_vf_trust,
4600 .ndo_set_vf_rate = mlx5e_set_vf_rate,
4601 .ndo_get_vf_config = mlx5e_get_vf_config,
4602 .ndo_set_vf_link_state = mlx5e_set_vf_link_state,
4603 .ndo_get_vf_stats = mlx5e_get_vf_stats,
4605 .ndo_get_devlink_port = mlx5e_get_devlink_port,
4608 static int mlx5e_check_required_hca_cap(struct mlx5_core_dev *mdev)
4610 if (MLX5_CAP_GEN(mdev, port_type) != MLX5_CAP_PORT_TYPE_ETH)
4612 if (!MLX5_CAP_GEN(mdev, eth_net_offloads) ||
4613 !MLX5_CAP_GEN(mdev, nic_flow_table) ||
4614 !MLX5_CAP_ETH(mdev, csum_cap) ||
4615 !MLX5_CAP_ETH(mdev, max_lso_cap) ||
4616 !MLX5_CAP_ETH(mdev, vlan_cap) ||
4617 !MLX5_CAP_ETH(mdev, rss_ind_tbl_cap) ||
4618 MLX5_CAP_FLOWTABLE(mdev,
4619 flow_table_properties_nic_receive.max_ft_level)
4621 mlx5_core_warn(mdev,
4622 "Not creating net device, some required device capabilities are missing\n");
4625 if (!MLX5_CAP_ETH(mdev, self_lb_en_modifiable))
4626 mlx5_core_warn(mdev, "Self loop back prevention is not supported\n");
4627 if (!MLX5_CAP_GEN(mdev, cq_moderation))
4628 mlx5_core_warn(mdev, "CQ moderation is not supported\n");
4633 void mlx5e_build_default_indir_rqt(u32 *indirection_rqt, int len,
4638 for (i = 0; i < len; i++)
4639 indirection_rqt[i] = i % num_channels;
4642 static bool slow_pci_heuristic(struct mlx5_core_dev *mdev)
4647 mlx5e_port_max_linkspeed(mdev, &link_speed);
4648 pci_bw = pcie_bandwidth_available(mdev->pdev, NULL, NULL, NULL);
4649 mlx5_core_dbg_once(mdev, "Max link speed = %d, PCI BW = %d\n",
4650 link_speed, pci_bw);
4652 #define MLX5E_SLOW_PCI_RATIO (2)
4654 return link_speed && pci_bw &&
4655 link_speed > MLX5E_SLOW_PCI_RATIO * pci_bw;
4658 static struct dim_cq_moder mlx5e_get_def_tx_moderation(u8 cq_period_mode)
4660 struct dim_cq_moder moder;
4662 moder.cq_period_mode = cq_period_mode;
4663 moder.pkts = MLX5E_PARAMS_DEFAULT_TX_CQ_MODERATION_PKTS;
4664 moder.usec = MLX5E_PARAMS_DEFAULT_TX_CQ_MODERATION_USEC;
4665 if (cq_period_mode == MLX5_CQ_PERIOD_MODE_START_FROM_CQE)
4666 moder.usec = MLX5E_PARAMS_DEFAULT_TX_CQ_MODERATION_USEC_FROM_CQE;
4671 static struct dim_cq_moder mlx5e_get_def_rx_moderation(u8 cq_period_mode)
4673 struct dim_cq_moder moder;
4675 moder.cq_period_mode = cq_period_mode;
4676 moder.pkts = MLX5E_PARAMS_DEFAULT_RX_CQ_MODERATION_PKTS;
4677 moder.usec = MLX5E_PARAMS_DEFAULT_RX_CQ_MODERATION_USEC;
4678 if (cq_period_mode == MLX5_CQ_PERIOD_MODE_START_FROM_CQE)
4679 moder.usec = MLX5E_PARAMS_DEFAULT_RX_CQ_MODERATION_USEC_FROM_CQE;
4684 static u8 mlx5_to_net_dim_cq_period_mode(u8 cq_period_mode)
4686 return cq_period_mode == MLX5_CQ_PERIOD_MODE_START_FROM_CQE ?
4687 DIM_CQ_PERIOD_MODE_START_FROM_CQE :
4688 DIM_CQ_PERIOD_MODE_START_FROM_EQE;
4691 void mlx5e_reset_tx_moderation(struct mlx5e_params *params, u8 cq_period_mode)
4693 if (params->tx_dim_enabled) {
4694 u8 dim_period_mode = mlx5_to_net_dim_cq_period_mode(cq_period_mode);
4696 params->tx_cq_moderation = net_dim_get_def_tx_moderation(dim_period_mode);
4698 params->tx_cq_moderation = mlx5e_get_def_tx_moderation(cq_period_mode);
4702 void mlx5e_reset_rx_moderation(struct mlx5e_params *params, u8 cq_period_mode)
4704 if (params->rx_dim_enabled) {
4705 u8 dim_period_mode = mlx5_to_net_dim_cq_period_mode(cq_period_mode);
4707 params->rx_cq_moderation = net_dim_get_def_rx_moderation(dim_period_mode);
4709 params->rx_cq_moderation = mlx5e_get_def_rx_moderation(cq_period_mode);
4713 void mlx5e_set_tx_cq_mode_params(struct mlx5e_params *params, u8 cq_period_mode)
4715 mlx5e_reset_tx_moderation(params, cq_period_mode);
4716 MLX5E_SET_PFLAG(params, MLX5E_PFLAG_TX_CQE_BASED_MODER,
4717 params->tx_cq_moderation.cq_period_mode ==
4718 MLX5_CQ_PERIOD_MODE_START_FROM_CQE);
4721 void mlx5e_set_rx_cq_mode_params(struct mlx5e_params *params, u8 cq_period_mode)
4723 mlx5e_reset_rx_moderation(params, cq_period_mode);
4724 MLX5E_SET_PFLAG(params, MLX5E_PFLAG_RX_CQE_BASED_MODER,
4725 params->rx_cq_moderation.cq_period_mode ==
4726 MLX5_CQ_PERIOD_MODE_START_FROM_CQE);
4729 static u32 mlx5e_choose_lro_timeout(struct mlx5_core_dev *mdev, u32 wanted_timeout)
4733 /* The supported periods are organized in ascending order */
4734 for (i = 0; i < MLX5E_LRO_TIMEOUT_ARR_SIZE - 1; i++)
4735 if (MLX5_CAP_ETH(mdev, lro_timer_supported_periods[i]) >= wanted_timeout)
4738 return MLX5_CAP_ETH(mdev, lro_timer_supported_periods[i]);
4741 void mlx5e_build_rq_params(struct mlx5_core_dev *mdev,
4742 struct mlx5e_params *params)
4744 /* Prefer Striding RQ, unless any of the following holds:
4745 * - Striding RQ configuration is not possible/supported.
4746 * - Slow PCI heuristic.
4747 * - Legacy RQ would use linear SKB while Striding RQ would use non-linear.
4749 * No XSK params: checking the availability of striding RQ in general.
4751 if (!slow_pci_heuristic(mdev) &&
4752 mlx5e_striding_rq_possible(mdev, params) &&
4753 (mlx5e_rx_mpwqe_is_linear_skb(mdev, params, NULL) ||
4754 !mlx5e_rx_is_linear_skb(params, NULL)))
4755 MLX5E_SET_PFLAG(params, MLX5E_PFLAG_RX_STRIDING_RQ, true);
4756 mlx5e_set_rq_type(mdev, params);
4757 mlx5e_init_rq_type_params(mdev, params);
4760 void mlx5e_build_rss_params(struct mlx5e_rss_params *rss_params,
4763 enum mlx5e_traffic_types tt;
4765 rss_params->hfunc = ETH_RSS_HASH_TOP;
4766 netdev_rss_key_fill(rss_params->toeplitz_hash_key,
4767 sizeof(rss_params->toeplitz_hash_key));
4768 mlx5e_build_default_indir_rqt(rss_params->indirection_rqt,
4769 MLX5E_INDIR_RQT_SIZE, num_channels);
4770 for (tt = 0; tt < MLX5E_NUM_INDIR_TIRS; tt++)
4771 rss_params->rx_hash_fields[tt] =
4772 tirc_default_config[tt].rx_hash_fields;
4775 void mlx5e_build_nic_params(struct mlx5e_priv *priv,
4776 struct mlx5e_xsk *xsk,
4777 struct mlx5e_rss_params *rss_params,
4778 struct mlx5e_params *params,
4781 struct mlx5_core_dev *mdev = priv->mdev;
4782 u8 rx_cq_period_mode;
4784 params->sw_mtu = mtu;
4785 params->hard_mtu = MLX5E_ETH_HARD_MTU;
4786 params->num_channels = min_t(unsigned int, MLX5E_MAX_NUM_CHANNELS / 2,
4791 params->log_sq_size = is_kdump_kernel() ?
4792 MLX5E_PARAMS_MINIMUM_LOG_SQ_SIZE :
4793 MLX5E_PARAMS_DEFAULT_LOG_SQ_SIZE;
4796 MLX5E_SET_PFLAG(params, MLX5E_PFLAG_XDP_TX_MPWQE,
4797 MLX5_CAP_ETH(mdev, enhanced_multi_pkt_send_wqe));
4799 /* set CQE compression */
4800 params->rx_cqe_compress_def = false;
4801 if (MLX5_CAP_GEN(mdev, cqe_compression) &&
4802 MLX5_CAP_GEN(mdev, vport_group_manager))
4803 params->rx_cqe_compress_def = slow_pci_heuristic(mdev);
4805 MLX5E_SET_PFLAG(params, MLX5E_PFLAG_RX_CQE_COMPRESS, params->rx_cqe_compress_def);
4806 MLX5E_SET_PFLAG(params, MLX5E_PFLAG_RX_NO_CSUM_COMPLETE, false);
4809 mlx5e_build_rq_params(mdev, params);
4812 if (MLX5_CAP_ETH(mdev, lro_cap) &&
4813 params->rq_wq_type == MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ) {
4814 /* No XSK params: checking the availability of striding RQ in general. */
4815 if (!mlx5e_rx_mpwqe_is_linear_skb(mdev, params, NULL))
4816 params->lro_en = !slow_pci_heuristic(mdev);
4818 params->lro_timeout = mlx5e_choose_lro_timeout(mdev, MLX5E_DEFAULT_LRO_TIMEOUT);
4820 /* CQ moderation params */
4821 rx_cq_period_mode = MLX5_CAP_GEN(mdev, cq_period_start_from_cqe) ?
4822 MLX5_CQ_PERIOD_MODE_START_FROM_CQE :
4823 MLX5_CQ_PERIOD_MODE_START_FROM_EQE;
4824 params->rx_dim_enabled = MLX5_CAP_GEN(mdev, cq_moderation);
4825 params->tx_dim_enabled = MLX5_CAP_GEN(mdev, cq_moderation);
4826 mlx5e_set_rx_cq_mode_params(params, rx_cq_period_mode);
4827 mlx5e_set_tx_cq_mode_params(params, MLX5_CQ_PERIOD_MODE_START_FROM_EQE);
4830 mlx5_query_min_inline(mdev, ¶ms->tx_min_inline_mode);
4833 mlx5e_build_rss_params(rss_params, params->num_channels);
4834 params->tunneled_offload_en =
4835 mlx5e_tunnel_inner_ft_supported(mdev);
4841 static void mlx5e_set_netdev_dev_addr(struct net_device *netdev)
4843 struct mlx5e_priv *priv = netdev_priv(netdev);
4845 mlx5_query_mac_address(priv->mdev, netdev->dev_addr);
4846 if (is_zero_ether_addr(netdev->dev_addr) &&
4847 !MLX5_CAP_GEN(priv->mdev, vport_group_manager)) {
4848 eth_hw_addr_random(netdev);
4849 mlx5_core_info(priv->mdev, "Assigned random MAC address %pM\n", netdev->dev_addr);
4853 static void mlx5e_build_nic_netdev(struct net_device *netdev)
4855 struct mlx5e_priv *priv = netdev_priv(netdev);
4856 struct mlx5_core_dev *mdev = priv->mdev;
4860 SET_NETDEV_DEV(netdev, mdev->device);
4862 netdev->netdev_ops = &mlx5e_netdev_ops;
4864 mlx5e_dcbnl_build_netdev(netdev);
4866 netdev->watchdog_timeo = 15 * HZ;
4868 netdev->ethtool_ops = &mlx5e_ethtool_ops;
4870 netdev->vlan_features |= NETIF_F_SG;
4871 netdev->vlan_features |= NETIF_F_HW_CSUM;
4872 netdev->vlan_features |= NETIF_F_GRO;
4873 netdev->vlan_features |= NETIF_F_TSO;
4874 netdev->vlan_features |= NETIF_F_TSO6;
4875 netdev->vlan_features |= NETIF_F_RXCSUM;
4876 netdev->vlan_features |= NETIF_F_RXHASH;
4878 netdev->mpls_features |= NETIF_F_SG;
4879 netdev->mpls_features |= NETIF_F_HW_CSUM;
4880 netdev->mpls_features |= NETIF_F_TSO;
4881 netdev->mpls_features |= NETIF_F_TSO6;
4883 netdev->hw_enc_features |= NETIF_F_HW_VLAN_CTAG_TX;
4884 netdev->hw_enc_features |= NETIF_F_HW_VLAN_CTAG_RX;
4886 if (!!MLX5_CAP_ETH(mdev, lro_cap) &&
4887 mlx5e_check_fragmented_striding_rq_cap(mdev))
4888 netdev->vlan_features |= NETIF_F_LRO;
4890 netdev->hw_features = netdev->vlan_features;
4891 netdev->hw_features |= NETIF_F_HW_VLAN_CTAG_TX;
4892 netdev->hw_features |= NETIF_F_HW_VLAN_CTAG_RX;
4893 netdev->hw_features |= NETIF_F_HW_VLAN_CTAG_FILTER;
4894 netdev->hw_features |= NETIF_F_HW_VLAN_STAG_TX;
4896 if (mlx5_vxlan_allowed(mdev->vxlan) || mlx5_geneve_tx_allowed(mdev) ||
4897 mlx5e_any_tunnel_proto_supported(mdev)) {
4898 netdev->hw_enc_features |= NETIF_F_HW_CSUM;
4899 netdev->hw_enc_features |= NETIF_F_TSO;
4900 netdev->hw_enc_features |= NETIF_F_TSO6;
4901 netdev->hw_enc_features |= NETIF_F_GSO_PARTIAL;
4904 if (mlx5_vxlan_allowed(mdev->vxlan) || mlx5_geneve_tx_allowed(mdev)) {
4905 netdev->hw_features |= NETIF_F_GSO_UDP_TUNNEL |
4906 NETIF_F_GSO_UDP_TUNNEL_CSUM;
4907 netdev->hw_enc_features |= NETIF_F_GSO_UDP_TUNNEL |
4908 NETIF_F_GSO_UDP_TUNNEL_CSUM;
4909 netdev->gso_partial_features = NETIF_F_GSO_UDP_TUNNEL_CSUM;
4910 netdev->vlan_features |= NETIF_F_GSO_UDP_TUNNEL |
4911 NETIF_F_GSO_UDP_TUNNEL_CSUM;
4914 if (mlx5e_tunnel_proto_supported(mdev, IPPROTO_GRE)) {
4915 netdev->hw_features |= NETIF_F_GSO_GRE |
4916 NETIF_F_GSO_GRE_CSUM;
4917 netdev->hw_enc_features |= NETIF_F_GSO_GRE |
4918 NETIF_F_GSO_GRE_CSUM;
4919 netdev->gso_partial_features |= NETIF_F_GSO_GRE |
4920 NETIF_F_GSO_GRE_CSUM;
4923 if (mlx5e_tunnel_proto_supported(mdev, IPPROTO_IPIP)) {
4924 netdev->hw_features |= NETIF_F_GSO_IPXIP4 |
4926 netdev->hw_enc_features |= NETIF_F_GSO_IPXIP4 |
4928 netdev->gso_partial_features |= NETIF_F_GSO_IPXIP4 |
4932 netdev->hw_features |= NETIF_F_GSO_PARTIAL;
4933 netdev->gso_partial_features |= NETIF_F_GSO_UDP_L4;
4934 netdev->hw_features |= NETIF_F_GSO_UDP_L4;
4935 netdev->features |= NETIF_F_GSO_UDP_L4;
4937 mlx5_query_port_fcs(mdev, &fcs_supported, &fcs_enabled);
4940 netdev->hw_features |= NETIF_F_RXALL;
4942 if (MLX5_CAP_ETH(mdev, scatter_fcs))
4943 netdev->hw_features |= NETIF_F_RXFCS;
4945 netdev->features = netdev->hw_features;
4946 if (!priv->channels.params.lro_en)
4947 netdev->features &= ~NETIF_F_LRO;
4950 netdev->features &= ~NETIF_F_RXALL;
4952 if (!priv->channels.params.scatter_fcs_en)
4953 netdev->features &= ~NETIF_F_RXFCS;
4955 /* prefere CQE compression over rxhash */
4956 if (MLX5E_GET_PFLAG(&priv->channels.params, MLX5E_PFLAG_RX_CQE_COMPRESS))
4957 netdev->features &= ~NETIF_F_RXHASH;
4959 #define FT_CAP(f) MLX5_CAP_FLOWTABLE(mdev, flow_table_properties_nic_receive.f)
4960 if (FT_CAP(flow_modify_en) &&
4961 FT_CAP(modify_root) &&
4962 FT_CAP(identified_miss_table_mode) &&
4963 FT_CAP(flow_table_modify)) {
4964 #ifdef CONFIG_MLX5_ESWITCH
4965 netdev->hw_features |= NETIF_F_HW_TC;
4967 #ifdef CONFIG_MLX5_EN_ARFS
4968 netdev->hw_features |= NETIF_F_NTUPLE;
4972 netdev->features |= NETIF_F_HIGHDMA;
4973 netdev->features |= NETIF_F_HW_VLAN_STAG_FILTER;
4975 netdev->priv_flags |= IFF_UNICAST_FLT;
4977 mlx5e_set_netdev_dev_addr(netdev);
4978 mlx5e_ipsec_build_netdev(priv);
4979 mlx5e_tls_build_netdev(priv);
4982 void mlx5e_create_q_counters(struct mlx5e_priv *priv)
4984 u32 out[MLX5_ST_SZ_DW(alloc_q_counter_out)] = {};
4985 u32 in[MLX5_ST_SZ_DW(alloc_q_counter_in)] = {};
4986 struct mlx5_core_dev *mdev = priv->mdev;
4989 MLX5_SET(alloc_q_counter_in, in, opcode, MLX5_CMD_OP_ALLOC_Q_COUNTER);
4990 err = mlx5_cmd_exec_inout(mdev, alloc_q_counter, in, out);
4993 MLX5_GET(alloc_q_counter_out, out, counter_set_id);
4995 err = mlx5_cmd_exec_inout(mdev, alloc_q_counter, in, out);
4997 priv->drop_rq_q_counter =
4998 MLX5_GET(alloc_q_counter_out, out, counter_set_id);
5001 void mlx5e_destroy_q_counters(struct mlx5e_priv *priv)
5003 u32 in[MLX5_ST_SZ_DW(dealloc_q_counter_in)] = {};
5005 MLX5_SET(dealloc_q_counter_in, in, opcode,
5006 MLX5_CMD_OP_DEALLOC_Q_COUNTER);
5007 if (priv->q_counter) {
5008 MLX5_SET(dealloc_q_counter_in, in, counter_set_id,
5010 mlx5_cmd_exec_in(priv->mdev, dealloc_q_counter, in);
5013 if (priv->drop_rq_q_counter) {
5014 MLX5_SET(dealloc_q_counter_in, in, counter_set_id,
5015 priv->drop_rq_q_counter);
5016 mlx5_cmd_exec_in(priv->mdev, dealloc_q_counter, in);
5020 static int mlx5e_nic_init(struct mlx5_core_dev *mdev,
5021 struct net_device *netdev,
5022 const struct mlx5e_profile *profile,
5025 struct mlx5e_priv *priv = netdev_priv(netdev);
5026 struct mlx5e_rss_params *rss = &priv->rss_params;
5029 err = mlx5e_netdev_init(netdev, priv, mdev, profile, ppriv);
5033 mlx5e_build_nic_params(priv, &priv->xsk, rss, &priv->channels.params,
5036 mlx5e_timestamp_init(priv);
5038 err = mlx5e_ipsec_init(priv);
5040 mlx5_core_err(mdev, "IPSec initialization failed, %d\n", err);
5041 err = mlx5e_tls_init(priv);
5043 mlx5_core_err(mdev, "TLS initialization failed, %d\n", err);
5044 mlx5e_build_nic_netdev(netdev);
5045 err = mlx5e_devlink_port_register(priv);
5047 mlx5_core_err(mdev, "mlx5e_devlink_port_register failed, %d\n", err);
5048 mlx5e_health_create_reporters(priv);
5053 static void mlx5e_nic_cleanup(struct mlx5e_priv *priv)
5055 mlx5e_health_destroy_reporters(priv);
5056 mlx5e_devlink_port_unregister(priv);
5057 mlx5e_tls_cleanup(priv);
5058 mlx5e_ipsec_cleanup(priv);
5059 mlx5e_netdev_cleanup(priv->netdev, priv);
5062 static int mlx5e_init_nic_rx(struct mlx5e_priv *priv)
5064 struct mlx5_core_dev *mdev = priv->mdev;
5067 mlx5e_create_q_counters(priv);
5069 err = mlx5e_open_drop_rq(priv, &priv->drop_rq);
5071 mlx5_core_err(mdev, "open drop rq failed, %d\n", err);
5072 goto err_destroy_q_counters;
5075 err = mlx5e_create_indirect_rqt(priv);
5077 goto err_close_drop_rq;
5079 err = mlx5e_create_direct_rqts(priv, priv->direct_tir);
5081 goto err_destroy_indirect_rqts;
5083 err = mlx5e_create_indirect_tirs(priv, true);
5085 goto err_destroy_direct_rqts;
5087 err = mlx5e_create_direct_tirs(priv, priv->direct_tir);
5089 goto err_destroy_indirect_tirs;
5091 err = mlx5e_create_direct_rqts(priv, priv->xsk_tir);
5093 goto err_destroy_direct_tirs;
5095 err = mlx5e_create_direct_tirs(priv, priv->xsk_tir);
5097 goto err_destroy_xsk_rqts;
5099 err = mlx5e_create_flow_steering(priv);
5101 mlx5_core_warn(mdev, "create flow steering failed, %d\n", err);
5102 goto err_destroy_xsk_tirs;
5105 err = mlx5e_tc_nic_init(priv);
5107 goto err_destroy_flow_steering;
5109 err = mlx5e_accel_init_rx(priv);
5111 goto err_tc_nic_cleanup;
5113 #ifdef CONFIG_MLX5_EN_ARFS
5114 priv->netdev->rx_cpu_rmap = mlx5_eq_table_get_rmap(priv->mdev);
5120 mlx5e_tc_nic_cleanup(priv);
5121 err_destroy_flow_steering:
5122 mlx5e_destroy_flow_steering(priv);
5123 err_destroy_xsk_tirs:
5124 mlx5e_destroy_direct_tirs(priv, priv->xsk_tir);
5125 err_destroy_xsk_rqts:
5126 mlx5e_destroy_direct_rqts(priv, priv->xsk_tir);
5127 err_destroy_direct_tirs:
5128 mlx5e_destroy_direct_tirs(priv, priv->direct_tir);
5129 err_destroy_indirect_tirs:
5130 mlx5e_destroy_indirect_tirs(priv);
5131 err_destroy_direct_rqts:
5132 mlx5e_destroy_direct_rqts(priv, priv->direct_tir);
5133 err_destroy_indirect_rqts:
5134 mlx5e_destroy_rqt(priv, &priv->indir_rqt);
5136 mlx5e_close_drop_rq(&priv->drop_rq);
5137 err_destroy_q_counters:
5138 mlx5e_destroy_q_counters(priv);
5142 static void mlx5e_cleanup_nic_rx(struct mlx5e_priv *priv)
5144 mlx5e_accel_cleanup_rx(priv);
5145 mlx5e_tc_nic_cleanup(priv);
5146 mlx5e_destroy_flow_steering(priv);
5147 mlx5e_destroy_direct_tirs(priv, priv->xsk_tir);
5148 mlx5e_destroy_direct_rqts(priv, priv->xsk_tir);
5149 mlx5e_destroy_direct_tirs(priv, priv->direct_tir);
5150 mlx5e_destroy_indirect_tirs(priv);
5151 mlx5e_destroy_direct_rqts(priv, priv->direct_tir);
5152 mlx5e_destroy_rqt(priv, &priv->indir_rqt);
5153 mlx5e_close_drop_rq(&priv->drop_rq);
5154 mlx5e_destroy_q_counters(priv);
5157 static int mlx5e_init_nic_tx(struct mlx5e_priv *priv)
5161 err = mlx5e_create_tises(priv);
5163 mlx5_core_warn(priv->mdev, "create tises failed, %d\n", err);
5167 mlx5e_dcbnl_initialize(priv);
5171 static void mlx5e_nic_enable(struct mlx5e_priv *priv)
5173 struct net_device *netdev = priv->netdev;
5174 struct mlx5_core_dev *mdev = priv->mdev;
5176 mlx5e_init_l2_addr(priv);
5178 /* Marking the link as currently not needed by the Driver */
5179 if (!netif_running(netdev))
5180 mlx5_set_port_admin_status(mdev, MLX5_PORT_DOWN);
5182 mlx5e_set_netdev_mtu_boundaries(priv);
5183 mlx5e_set_dev_port_mtu(priv);
5185 mlx5_lag_add(mdev, netdev);
5187 mlx5e_enable_async_events(priv);
5188 if (mlx5e_monitor_counter_supported(priv))
5189 mlx5e_monitor_counter_init(priv);
5191 mlx5e_hv_vhca_stats_create(priv);
5192 if (netdev->reg_state != NETREG_REGISTERED)
5194 mlx5e_dcbnl_init_app(priv);
5196 queue_work(priv->wq, &priv->set_rx_mode_work);
5199 if (netif_running(netdev))
5201 if (mlx5_vxlan_allowed(priv->mdev->vxlan))
5202 udp_tunnel_get_rx_info(netdev);
5203 netif_device_attach(netdev);
5207 static void mlx5e_nic_disable(struct mlx5e_priv *priv)
5209 struct mlx5_core_dev *mdev = priv->mdev;
5211 if (priv->netdev->reg_state == NETREG_REGISTERED)
5212 mlx5e_dcbnl_delete_app(priv);
5215 if (netif_running(priv->netdev))
5216 mlx5e_close(priv->netdev);
5217 if (mlx5_vxlan_allowed(priv->mdev->vxlan))
5218 udp_tunnel_drop_rx_info(priv->netdev);
5219 netif_device_detach(priv->netdev);
5222 queue_work(priv->wq, &priv->set_rx_mode_work);
5224 mlx5e_hv_vhca_stats_destroy(priv);
5225 if (mlx5e_monitor_counter_supported(priv))
5226 mlx5e_monitor_counter_cleanup(priv);
5228 mlx5e_disable_async_events(priv);
5229 mlx5_lag_remove(mdev);
5232 int mlx5e_update_nic_rx(struct mlx5e_priv *priv)
5234 return mlx5e_refresh_tirs(priv, false, false);
5237 static const struct mlx5e_profile mlx5e_nic_profile = {
5238 .init = mlx5e_nic_init,
5239 .cleanup = mlx5e_nic_cleanup,
5240 .init_rx = mlx5e_init_nic_rx,
5241 .cleanup_rx = mlx5e_cleanup_nic_rx,
5242 .init_tx = mlx5e_init_nic_tx,
5243 .cleanup_tx = mlx5e_cleanup_nic_tx,
5244 .enable = mlx5e_nic_enable,
5245 .disable = mlx5e_nic_disable,
5246 .update_rx = mlx5e_update_nic_rx,
5247 .update_stats = mlx5e_update_ndo_stats,
5248 .update_carrier = mlx5e_update_carrier,
5249 .rx_handlers = &mlx5e_rx_handlers_nic,
5250 .max_tc = MLX5E_MAX_NUM_TC,
5251 .rq_groups = MLX5E_NUM_RQ_GROUPS(XSK),
5252 .stats_grps = mlx5e_nic_stats_grps,
5253 .stats_grps_num = mlx5e_nic_stats_grps_num,
5256 /* mlx5e generic netdev management API (move to en_common.c) */
5258 /* mlx5e_netdev_init/cleanup must be called from profile->init/cleanup callbacks */
5259 int mlx5e_netdev_init(struct net_device *netdev,
5260 struct mlx5e_priv *priv,
5261 struct mlx5_core_dev *mdev,
5262 const struct mlx5e_profile *profile,
5267 priv->netdev = netdev;
5268 priv->profile = profile;
5269 priv->ppriv = ppriv;
5270 priv->msglevel = MLX5E_MSG_LEVEL;
5271 priv->max_nch = netdev->num_rx_queues / max_t(u8, profile->rq_groups, 1);
5272 priv->max_opened_tc = 1;
5274 if (!alloc_cpumask_var(&priv->scratchpad.cpumask, GFP_KERNEL))
5277 mutex_init(&priv->state_lock);
5278 INIT_WORK(&priv->update_carrier_work, mlx5e_update_carrier_work);
5279 INIT_WORK(&priv->set_rx_mode_work, mlx5e_set_rx_mode_work);
5280 INIT_WORK(&priv->tx_timeout_work, mlx5e_tx_timeout_work);
5281 INIT_WORK(&priv->update_stats_work, mlx5e_update_stats_work);
5283 priv->wq = create_singlethread_workqueue("mlx5e");
5285 goto err_free_cpumask;
5288 netif_carrier_off(netdev);
5293 free_cpumask_var(priv->scratchpad.cpumask);
5298 void mlx5e_netdev_cleanup(struct net_device *netdev, struct mlx5e_priv *priv)
5300 destroy_workqueue(priv->wq);
5301 free_cpumask_var(priv->scratchpad.cpumask);
5304 struct net_device *mlx5e_create_netdev(struct mlx5_core_dev *mdev,
5305 const struct mlx5e_profile *profile,
5309 struct net_device *netdev;
5312 netdev = alloc_etherdev_mqs(sizeof(struct mlx5e_priv),
5313 nch * profile->max_tc,
5314 nch * profile->rq_groups);
5316 mlx5_core_err(mdev, "alloc_etherdev_mqs() failed\n");
5320 err = profile->init(mdev, netdev, profile, ppriv);
5322 mlx5_core_err(mdev, "failed to init mlx5e profile %d\n", err);
5323 goto err_free_netdev;
5329 free_netdev(netdev);
5334 int mlx5e_attach_netdev(struct mlx5e_priv *priv)
5336 const bool take_rtnl = priv->netdev->reg_state == NETREG_REGISTERED;
5337 const struct mlx5e_profile *profile;
5341 profile = priv->profile;
5342 clear_bit(MLX5E_STATE_DESTROYING, &priv->state);
5344 /* max number of channels may have changed */
5345 max_nch = mlx5e_get_max_num_channels(priv->mdev);
5346 if (priv->channels.params.num_channels > max_nch) {
5347 mlx5_core_warn(priv->mdev, "MLX5E: Reducing number of channels to %d\n", max_nch);
5348 /* Reducing the number of channels - RXFH has to be reset, and
5349 * mlx5e_num_channels_changed below will build the RQT.
5351 priv->netdev->priv_flags &= ~IFF_RXFH_CONFIGURED;
5352 priv->channels.params.num_channels = max_nch;
5354 /* 1. Set the real number of queues in the kernel the first time.
5355 * 2. Set our default XPS cpumask.
5358 * rtnl_lock is required by netif_set_real_num_*_queues in case the
5359 * netdev has been registered by this point (if this function was called
5360 * in the reload or resume flow).
5364 err = mlx5e_num_channels_changed(priv);
5370 err = profile->init_tx(priv);
5374 err = profile->init_rx(priv);
5376 goto err_cleanup_tx;
5378 if (profile->enable)
5379 profile->enable(priv);
5384 profile->cleanup_tx(priv);
5390 void mlx5e_detach_netdev(struct mlx5e_priv *priv)
5392 const struct mlx5e_profile *profile = priv->profile;
5394 set_bit(MLX5E_STATE_DESTROYING, &priv->state);
5396 if (profile->disable)
5397 profile->disable(priv);
5398 flush_workqueue(priv->wq);
5400 profile->cleanup_rx(priv);
5401 profile->cleanup_tx(priv);
5402 cancel_work_sync(&priv->update_stats_work);
5405 void mlx5e_destroy_netdev(struct mlx5e_priv *priv)
5407 const struct mlx5e_profile *profile = priv->profile;
5408 struct net_device *netdev = priv->netdev;
5410 if (profile->cleanup)
5411 profile->cleanup(priv);
5412 free_netdev(netdev);
5415 /* mlx5e_attach and mlx5e_detach scope should be only creating/destroying
5416 * hardware contexts and to connect it to the current netdev.
5418 static int mlx5e_attach(struct mlx5_core_dev *mdev, void *vpriv)
5420 struct mlx5e_priv *priv = vpriv;
5421 struct net_device *netdev = priv->netdev;
5424 if (netif_device_present(netdev))
5427 err = mlx5e_create_mdev_resources(mdev);
5431 err = mlx5e_attach_netdev(priv);
5433 mlx5e_destroy_mdev_resources(mdev);
5440 static void mlx5e_detach(struct mlx5_core_dev *mdev, void *vpriv)
5442 struct mlx5e_priv *priv = vpriv;
5443 struct net_device *netdev = priv->netdev;
5445 #ifdef CONFIG_MLX5_ESWITCH
5446 if (MLX5_ESWITCH_MANAGER(mdev) && vpriv == mdev)
5450 if (!netif_device_present(netdev))
5453 mlx5e_detach_netdev(priv);
5454 mlx5e_destroy_mdev_resources(mdev);
5457 static void *mlx5e_add(struct mlx5_core_dev *mdev)
5459 struct net_device *netdev;
5464 err = mlx5e_check_required_hca_cap(mdev);
5468 #ifdef CONFIG_MLX5_ESWITCH
5469 if (MLX5_ESWITCH_MANAGER(mdev) &&
5470 mlx5_eswitch_mode(mdev->priv.eswitch) == MLX5_ESWITCH_OFFLOADS) {
5471 mlx5e_rep_register_vport_reps(mdev);
5476 nch = mlx5e_get_max_num_channels(mdev);
5477 netdev = mlx5e_create_netdev(mdev, &mlx5e_nic_profile, nch, NULL);
5479 mlx5_core_err(mdev, "mlx5e_create_netdev failed\n");
5483 dev_net_set(netdev, mlx5_core_net(mdev));
5484 priv = netdev_priv(netdev);
5486 err = mlx5e_attach(mdev, priv);
5488 mlx5_core_err(mdev, "mlx5e_attach failed, %d\n", err);
5489 goto err_destroy_netdev;
5492 err = register_netdev(netdev);
5494 mlx5_core_err(mdev, "register_netdev failed, %d\n", err);
5498 mlx5e_devlink_port_type_eth_set(priv);
5500 mlx5e_dcbnl_init_app(priv);
5504 mlx5e_detach(mdev, priv);
5506 mlx5e_destroy_netdev(priv);
5510 static void mlx5e_remove(struct mlx5_core_dev *mdev, void *vpriv)
5512 struct mlx5e_priv *priv;
5514 #ifdef CONFIG_MLX5_ESWITCH
5515 if (MLX5_ESWITCH_MANAGER(mdev) && vpriv == mdev) {
5516 mlx5e_rep_unregister_vport_reps(mdev);
5521 mlx5e_dcbnl_delete_app(priv);
5522 unregister_netdev(priv->netdev);
5523 mlx5e_detach(mdev, vpriv);
5524 mlx5e_destroy_netdev(priv);
5527 static struct mlx5_interface mlx5e_interface = {
5529 .remove = mlx5e_remove,
5530 .attach = mlx5e_attach,
5531 .detach = mlx5e_detach,
5532 .protocol = MLX5_INTERFACE_PROTOCOL_ETH,
5535 void mlx5e_init(void)
5537 mlx5e_ipsec_build_inverse_table();
5538 mlx5e_build_ptys2ethtool_map();
5539 mlx5_register_interface(&mlx5e_interface);
5542 void mlx5e_cleanup(void)
5544 mlx5_unregister_interface(&mlx5e_interface);