drivers/net/ethernet/mellanox/mlx5/core/en_main.c

   1 /*
   2  * Copyright (c) 2015-2016, Mellanox Technologies. All rights reserved.
   3  *
   4  * This software is available to you under a choice of one of two
   5  * licenses.  You may choose to be licensed under the terms of the GNU
   6  * General Public License (GPL) Version 2, available from the file
   7  * COPYING in the main directory of this source tree, or the
   8  * OpenIB.org BSD license below:
   9  *
  10  *     Redistribution and use in source and binary forms, with or
  11  *     without modification, are permitted provided that the following
  12  *     conditions are met:
  13  *
  14  *      - Redistributions of source code must retain the above
  15  *        copyright notice, this list of conditions and the following
  16  *        disclaimer.
  17  *
  18  *      - Redistributions in binary form must reproduce the above
  19  *        copyright notice, this list of conditions and the following
  20  *        disclaimer in the documentation and/or other materials
  21  *        provided with the distribution.
  22  *
  23  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  24  * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  25  * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
  26  * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
  27  * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
  28  * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
  29  * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
  30  * SOFTWARE.
  31  */
  32
  33 #include <net/tc_act/tc_gact.h>
  34 #include <net/pkt_cls.h>
  35 #include <linux/mlx5/fs.h>
  36 #include <net/vxlan.h>
  37 #include <net/geneve.h>
  38 #include <linux/bpf.h>
  39 #include <linux/if_bridge.h>
  40 #include <net/page_pool.h>
  41 #include <net/xdp_sock.h>
  42 #include "eswitch.h"
  43 #include "en.h"
  44 #include "en/txrx.h"
  45 #include "en_tc.h"
  46 #include "en_rep.h"
  47 #include "en_accel/ipsec.h"
  48 #include "en_accel/ipsec_rxtx.h"
  49 #include "en_accel/en_accel.h"
  50 #include "en_accel/tls.h"
  51 #include "accel/ipsec.h"
  52 #include "accel/tls.h"
  53 #include "lib/vxlan.h"
  54 #include "lib/clock.h"
  55 #include "en/port.h"
  56 #include "en/xdp.h"
  57 #include "lib/eq.h"
  58 #include "en/monitor_stats.h"
  59 #include "en/reporter.h"
  60 #include "en/params.h"
  61 #include "en/xsk/umem.h"
  62 #include "en/xsk/setup.h"
  63 #include "en/xsk/rx.h"
  64 #include "en/xsk/tx.h"
  65
  66
  67 bool mlx5e_check_fragmented_striding_rq_cap(struct mlx5_core_dev *mdev)
  68 {
  69         bool striding_rq_umr = MLX5_CAP_GEN(mdev, striding_rq) &&
  70                 MLX5_CAP_GEN(mdev, umr_ptr_rlky) &&
  71                 MLX5_CAP_ETH(mdev, reg_umr_sq);
  72         u16 max_wqe_sz_cap = MLX5_CAP_GEN(mdev, max_wqe_sz_sq);
  73         bool inline_umr = MLX5E_UMR_WQE_INLINE_SZ <= max_wqe_sz_cap;
  74
  75         if (!striding_rq_umr)
  76                 return false;
  77         if (!inline_umr) {
  78                 mlx5_core_warn(mdev, "Cannot support Striding RQ: UMR WQE size (%d) exceeds maximum supported (%d).\n",
  79                                (int)MLX5E_UMR_WQE_INLINE_SZ, max_wqe_sz_cap);
  80                 return false;
  81         }
  82         return true;
  83 }
  84
  85 void mlx5e_init_rq_type_params(struct mlx5_core_dev *mdev,
  86                                struct mlx5e_params *params)
  87 {
  88         params->log_rq_mtu_frames = is_kdump_kernel() ?
  89                 MLX5E_PARAMS_MINIMUM_LOG_RQ_SIZE :
  90                 MLX5E_PARAMS_DEFAULT_LOG_RQ_SIZE;
  91
  92         mlx5_core_info(mdev, "MLX5E: StrdRq(%d) RqSz(%ld) StrdSz(%ld) RxCqeCmprss(%d)\n",
  93                        params->rq_wq_type == MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ,
  94                        params->rq_wq_type == MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ ?
  95                        BIT(mlx5e_mpwqe_get_log_rq_size(params, NULL)) :
  96                        BIT(params->log_rq_mtu_frames),
  97                        BIT(mlx5e_mpwqe_get_log_stride_size(mdev, params, NULL)),
  98                        MLX5E_GET_PFLAG(params, MLX5E_PFLAG_RX_CQE_COMPRESS));
  99 }
 100
 101 bool mlx5e_striding_rq_possible(struct mlx5_core_dev *mdev,
 102                                 struct mlx5e_params *params)
 103 {
 104         if (!mlx5e_check_fragmented_striding_rq_cap(mdev))
 105                 return false;
 106
 107         if (MLX5_IPSEC_DEV(mdev))
 108                 return false;
 109
 110         if (params->xdp_prog) {
 111                 /* XSK params are not considered here. If striding RQ is in use,
 112                  * and an XSK is being opened, mlx5e_rx_mpwqe_is_linear_skb will
 113                  * be called with the known XSK params.
 114                  */
 115                 if (!mlx5e_rx_mpwqe_is_linear_skb(mdev, params, NULL))
 116                         return false;
 117         }
 118
 119         return true;
 120 }
 121
 122 void mlx5e_set_rq_type(struct mlx5_core_dev *mdev, struct mlx5e_params *params)
 123 {
 124         params->rq_wq_type = mlx5e_striding_rq_possible(mdev, params) &&
 125                 MLX5E_GET_PFLAG(params, MLX5E_PFLAG_RX_STRIDING_RQ) ?
 126                 MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ :
 127                 MLX5_WQ_TYPE_CYCLIC;
 128 }
 129
 130 void mlx5e_update_carrier(struct mlx5e_priv *priv)
 131 {
 132         struct mlx5_core_dev *mdev = priv->mdev;
 133         u8 port_state;
 134
 135         port_state = mlx5_query_vport_state(mdev,
 136                                             MLX5_VPORT_STATE_OP_MOD_VNIC_VPORT,
 137                                             0);
 138
 139         if (port_state == VPORT_STATE_UP) {
 140                 netdev_info(priv->netdev, "Link up\n");
 141                 netif_carrier_on(priv->netdev);
 142         } else {
 143                 netdev_info(priv->netdev, "Link down\n");
 144                 netif_carrier_off(priv->netdev);
 145         }
 146 }
 147
 148 static void mlx5e_update_carrier_work(struct work_struct *work)
 149 {
 150         struct mlx5e_priv *priv = container_of(work, struct mlx5e_priv,
 151                                                update_carrier_work);
 152
 153         mutex_lock(&priv->state_lock);
 154         if (test_bit(MLX5E_STATE_OPENED, &priv->state))
 155                 if (priv->profile->update_carrier)
 156                         priv->profile->update_carrier(priv);
 157         mutex_unlock(&priv->state_lock);
 158 }
 159
 160 void mlx5e_update_stats(struct mlx5e_priv *priv)
 161 {
 162         int i;
 163
 164         for (i = mlx5e_num_stats_grps - 1; i >= 0; i--)
 165                 if (mlx5e_stats_grps[i].update_stats)
 166                         mlx5e_stats_grps[i].update_stats(priv);
 167 }
 168
 169 void mlx5e_update_ndo_stats(struct mlx5e_priv *priv)
 170 {
 171         int i;
 172
 173         for (i = mlx5e_num_stats_grps - 1; i >= 0; i--)
 174                 if (mlx5e_stats_grps[i].update_stats_mask &
 175                     MLX5E_NDO_UPDATE_STATS)
 176                         mlx5e_stats_grps[i].update_stats(priv);
 177 }
 178
 179 static void mlx5e_update_stats_work(struct work_struct *work)
 180 {
 181         struct mlx5e_priv *priv = container_of(work, struct mlx5e_priv,
 182                                                update_stats_work);
 183
 184         mutex_lock(&priv->state_lock);
 185         priv->profile->update_stats(priv);
 186         mutex_unlock(&priv->state_lock);
 187 }
 188
 189 void mlx5e_queue_update_stats(struct mlx5e_priv *priv)
 190 {
 191         if (!priv->profile->update_stats)
 192                 return;
 193
 194         if (unlikely(test_bit(MLX5E_STATE_DESTROYING, &priv->state)))
 195                 return;
 196
 197         queue_work(priv->wq, &priv->update_stats_work);
 198 }
 199
 200 static int async_event(struct notifier_block *nb, unsigned long event, void *data)
 201 {
 202         struct mlx5e_priv *priv = container_of(nb, struct mlx5e_priv, events_nb);
 203         struct mlx5_eqe   *eqe = data;
 204
 205         if (event != MLX5_EVENT_TYPE_PORT_CHANGE)
 206                 return NOTIFY_DONE;
 207
 208         switch (eqe->sub_type) {
 209         case MLX5_PORT_CHANGE_SUBTYPE_DOWN:
 210         case MLX5_PORT_CHANGE_SUBTYPE_ACTIVE:
 211                 queue_work(priv->wq, &priv->update_carrier_work);
 212                 break;
 213         default:
 214                 return NOTIFY_DONE;
 215         }
 216
 217         return NOTIFY_OK;
 218 }
 219
 220 static void mlx5e_enable_async_events(struct mlx5e_priv *priv)
 221 {
 222         priv->events_nb.notifier_call = async_event;
 223         mlx5_notifier_register(priv->mdev, &priv->events_nb);
 224 }
 225
 226 static void mlx5e_disable_async_events(struct mlx5e_priv *priv)
 227 {
 228         mlx5_notifier_unregister(priv->mdev, &priv->events_nb);
 229 }
 230
 231 static inline void mlx5e_build_umr_wqe(struct mlx5e_rq *rq,
 232                                        struct mlx5e_icosq *sq,
 233                                        struct mlx5e_umr_wqe *wqe)
 234 {
 235         struct mlx5_wqe_ctrl_seg      *cseg = &wqe->ctrl;
 236         struct mlx5_wqe_umr_ctrl_seg *ucseg = &wqe->uctrl;
 237         u8 ds_cnt = DIV_ROUND_UP(MLX5E_UMR_WQE_INLINE_SZ, MLX5_SEND_WQE_DS);
 238
 239         cseg->qpn_ds    = cpu_to_be32((sq->sqn << MLX5_WQE_CTRL_QPN_SHIFT) |
 240                                       ds_cnt);
 241         cseg->fm_ce_se  = MLX5_WQE_CTRL_CQ_UPDATE;
 242         cseg->imm       = rq->mkey_be;
 243
 244         ucseg->flags = MLX5_UMR_TRANSLATION_OFFSET_EN | MLX5_UMR_INLINE;
 245         ucseg->xlt_octowords =
 246                 cpu_to_be16(MLX5_MTT_OCTW(MLX5_MPWRQ_PAGES_PER_WQE));
 247         ucseg->mkey_mask     = cpu_to_be64(MLX5_MKEY_MASK_FREE);
 248 }
 249
 250 static u32 mlx5e_rqwq_get_size(struct mlx5e_rq *rq)
 251 {
 252         switch (rq->wq_type) {
 253         case MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ:
 254                 return mlx5_wq_ll_get_size(&rq->mpwqe.wq);
 255         default:
 256                 return mlx5_wq_cyc_get_size(&rq->wqe.wq);
 257         }
 258 }
 259
 260 static u32 mlx5e_rqwq_get_cur_sz(struct mlx5e_rq *rq)
 261 {
 262         switch (rq->wq_type) {
 263         case MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ:
 264                 return rq->mpwqe.wq.cur_sz;
 265         default:
 266                 return rq->wqe.wq.cur_sz;
 267         }
 268 }
 269
 270 static int mlx5e_rq_alloc_mpwqe_info(struct mlx5e_rq *rq,
 271                                      struct mlx5e_channel *c)
 272 {
 273         int wq_sz = mlx5_wq_ll_get_size(&rq->mpwqe.wq);
 274
 275         rq->mpwqe.info = kvzalloc_node(array_size(wq_sz,
 276                                                   sizeof(*rq->mpwqe.info)),
 277                                        GFP_KERNEL, cpu_to_node(c->cpu));
 278         if (!rq->mpwqe.info)
 279                 return -ENOMEM;
 280
 281         mlx5e_build_umr_wqe(rq, &c->icosq, &rq->mpwqe.umr_wqe);
 282
 283         return 0;
 284 }
 285
 286 static int mlx5e_create_umr_mkey(struct mlx5_core_dev *mdev,
 287                                  u64 npages, u8 page_shift,
 288                                  struct mlx5_core_mkey *umr_mkey)
 289 {
 290         int inlen = MLX5_ST_SZ_BYTES(create_mkey_in);
 291         void *mkc;
 292         u32 *in;
 293         int err;
 294
 295         in = kvzalloc(inlen, GFP_KERNEL);
 296         if (!in)
 297                 return -ENOMEM;
 298
 299         mkc = MLX5_ADDR_OF(create_mkey_in, in, memory_key_mkey_entry);
 300
 301         MLX5_SET(mkc, mkc, free, 1);
 302         MLX5_SET(mkc, mkc, umr_en, 1);
 303         MLX5_SET(mkc, mkc, lw, 1);
 304         MLX5_SET(mkc, mkc, lr, 1);
 305         MLX5_SET(mkc, mkc, access_mode_1_0, MLX5_MKC_ACCESS_MODE_MTT);
 306
 307         MLX5_SET(mkc, mkc, qpn, 0xffffff);
 308         MLX5_SET(mkc, mkc, pd, mdev->mlx5e_res.pdn);
 309         MLX5_SET64(mkc, mkc, len, npages << page_shift);
 310         MLX5_SET(mkc, mkc, translations_octword_size,
 311                  MLX5_MTT_OCTW(npages));
 312         MLX5_SET(mkc, mkc, log_page_size, page_shift);
 313
 314         err = mlx5_core_create_mkey(mdev, umr_mkey, in, inlen);
 315
 316         kvfree(in);
 317         return err;
 318 }
 319
 320 static int mlx5e_create_rq_umr_mkey(struct mlx5_core_dev *mdev, struct mlx5e_rq *rq)
 321 {
 322         u64 num_mtts = MLX5E_REQUIRED_MTTS(mlx5_wq_ll_get_size(&rq->mpwqe.wq));
 323
 324         return mlx5e_create_umr_mkey(mdev, num_mtts, PAGE_SHIFT, &rq->umr_mkey);
 325 }
 326
 327 static inline u64 mlx5e_get_mpwqe_offset(struct mlx5e_rq *rq, u16 wqe_ix)
 328 {
 329         return (wqe_ix << MLX5E_LOG_ALIGNED_MPWQE_PPW) << PAGE_SHIFT;
 330 }
 331
 332 static void mlx5e_init_frags_partition(struct mlx5e_rq *rq)
 333 {
 334         struct mlx5e_wqe_frag_info next_frag, *prev;
 335         int i;
 336
 337         next_frag.di = &rq->wqe.di[0];
 338         next_frag.offset = 0;
 339         prev = NULL;
 340
 341         for (i = 0; i < mlx5_wq_cyc_get_size(&rq->wqe.wq); i++) {
 342                 struct mlx5e_rq_frag_info *frag_info = &rq->wqe.info.arr[0];
 343                 struct mlx5e_wqe_frag_info *frag =
 344                         &rq->wqe.frags[i << rq->wqe.info.log_num_frags];
 345                 int f;
 346
 347                 for (f = 0; f < rq->wqe.info.num_frags; f++, frag++) {
 348                         if (next_frag.offset + frag_info[f].frag_stride > PAGE_SIZE) {
 349                                 next_frag.di++;
 350                                 next_frag.offset = 0;
 351                                 if (prev)
 352                                         prev->last_in_page = true;
 353                         }
 354                         *frag = next_frag;
 355
 356                         /* prepare next */
 357                         next_frag.offset += frag_info[f].frag_stride;
 358                         prev = frag;
 359                 }
 360         }
 361
 362         if (prev)
 363                 prev->last_in_page = true;
 364 }
 365
 366 static int mlx5e_init_di_list(struct mlx5e_rq *rq,
 367                               int wq_sz, int cpu)
 368 {
 369         int len = wq_sz << rq->wqe.info.log_num_frags;
 370
 371         rq->wqe.di = kvzalloc_node(array_size(len, sizeof(*rq->wqe.di)),
 372                                    GFP_KERNEL, cpu_to_node(cpu));
 373         if (!rq->wqe.di)
 374                 return -ENOMEM;
 375
 376         mlx5e_init_frags_partition(rq);
 377
 378         return 0;
 379 }
 380
 381 static void mlx5e_free_di_list(struct mlx5e_rq *rq)
 382 {
 383         kvfree(rq->wqe.di);
 384 }
 385
 386 static int mlx5e_alloc_rq(struct mlx5e_channel *c,
 387                           struct mlx5e_params *params,
 388                           struct mlx5e_xsk_param *xsk,
 389                           struct xdp_umem *umem,
 390                           struct mlx5e_rq_param *rqp,
 391                           struct mlx5e_rq *rq)
 392 {
 393         struct page_pool_params pp_params = { 0 };
 394         struct mlx5_core_dev *mdev = c->mdev;
 395         void *rqc = rqp->rqc;
 396         void *rqc_wq = MLX5_ADDR_OF(rqc, rqc, wq);
 397         u32 num_xsk_frames = 0;
 398         u32 rq_xdp_ix;
 399         u32 pool_size;
 400         int wq_sz;
 401         int err;
 402         int i;
 403
 404         rqp->wq.db_numa_node = cpu_to_node(c->cpu);
 405
 406         rq->wq_type = params->rq_wq_type;
 407         rq->pdev    = c->pdev;
 408         rq->netdev  = c->netdev;
 409         rq->tstamp  = c->tstamp;
 410         rq->clock   = &mdev->clock;
 411         rq->channel = c;
 412         rq->ix      = c->ix;
 413         rq->mdev    = mdev;
 414         rq->hw_mtu  = MLX5E_SW2HW_MTU(params, params->sw_mtu);
 415         rq->xdpsq   = &c->rq_xdpsq;
 416         rq->umem    = umem;
 417
 418         if (rq->umem)
 419                 rq->stats = &c->priv->channel_stats[c->ix].xskrq;
 420         else
 421                 rq->stats = &c->priv->channel_stats[c->ix].rq;
 422
 423         rq->xdp_prog = params->xdp_prog ? bpf_prog_inc(params->xdp_prog) : NULL;
 424         if (IS_ERR(rq->xdp_prog)) {
 425                 err = PTR_ERR(rq->xdp_prog);
 426                 rq->xdp_prog = NULL;
 427                 goto err_rq_wq_destroy;
 428         }
 429
 430         rq_xdp_ix = rq->ix;
 431         if (xsk)
 432                 rq_xdp_ix += params->num_channels * MLX5E_RQ_GROUP_XSK;
 433         err = xdp_rxq_info_reg(&rq->xdp_rxq, rq->netdev, rq_xdp_ix);
 434         if (err < 0)
 435                 goto err_rq_wq_destroy;
 436
 437         rq->buff.map_dir = rq->xdp_prog ? DMA_BIDIRECTIONAL : DMA_FROM_DEVICE;
 438         rq->buff.headroom = mlx5e_get_rq_headroom(mdev, params, xsk);
 439         rq->buff.umem_headroom = xsk ? xsk->headroom : 0;
 440         pool_size = 1 << params->log_rq_mtu_frames;
 441
 442         switch (rq->wq_type) {
 443         case MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ:
 444                 err = mlx5_wq_ll_create(mdev, &rqp->wq, rqc_wq, &rq->mpwqe.wq,
 445                                         &rq->wq_ctrl);
 446                 if (err)
 447                         return err;
 448
 449                 rq->mpwqe.wq.db = &rq->mpwqe.wq.db[MLX5_RCV_DBR];
 450
 451                 wq_sz = mlx5_wq_ll_get_size(&rq->mpwqe.wq);
 452
 453                 if (xsk)
 454                         num_xsk_frames = wq_sz <<
 455                                 mlx5e_mpwqe_get_log_num_strides(mdev, params, xsk);
 456
 457                 pool_size = MLX5_MPWRQ_PAGES_PER_WQE <<
 458                         mlx5e_mpwqe_get_log_rq_size(params, xsk);
 459
 460                 rq->post_wqes = mlx5e_post_rx_mpwqes;
 461                 rq->dealloc_wqe = mlx5e_dealloc_rx_mpwqe;
 462
 463                 rq->handle_rx_cqe = c->priv->profile->rx_handlers.handle_rx_cqe_mpwqe;
 464 #ifdef CONFIG_MLX5_EN_IPSEC
 465                 if (MLX5_IPSEC_DEV(mdev)) {
 466                         err = -EINVAL;
 467                         netdev_err(c->netdev, "MPWQE RQ with IPSec offload not supported\n");
 468                         goto err_rq_wq_destroy;
 469                 }
 470 #endif
 471                 if (!rq->handle_rx_cqe) {
 472                         err = -EINVAL;
 473                         netdev_err(c->netdev, "RX handler of MPWQE RQ is not set, err %d\n", err);
 474                         goto err_rq_wq_destroy;
 475                 }
 476
 477                 rq->mpwqe.skb_from_cqe_mpwrq = xsk ?
 478                         mlx5e_xsk_skb_from_cqe_mpwrq_linear :
 479                         mlx5e_rx_mpwqe_is_linear_skb(mdev, params, NULL) ?
 480                                 mlx5e_skb_from_cqe_mpwrq_linear :
 481                                 mlx5e_skb_from_cqe_mpwrq_nonlinear;
 482
 483                 rq->mpwqe.log_stride_sz = mlx5e_mpwqe_get_log_stride_size(mdev, params, xsk);
 484                 rq->mpwqe.num_strides =
 485                         BIT(mlx5e_mpwqe_get_log_num_strides(mdev, params, xsk));
 486
 487                 err = mlx5e_create_rq_umr_mkey(mdev, rq);
 488                 if (err)
 489                         goto err_rq_wq_destroy;
 490                 rq->mkey_be = cpu_to_be32(rq->umr_mkey.key);
 491
 492                 err = mlx5e_rq_alloc_mpwqe_info(rq, c);
 493                 if (err)
 494                         goto err_free;
 495                 break;
 496         default: /* MLX5_WQ_TYPE_CYCLIC */
 497                 err = mlx5_wq_cyc_create(mdev, &rqp->wq, rqc_wq, &rq->wqe.wq,
 498                                          &rq->wq_ctrl);
 499                 if (err)
 500                         return err;
 501
 502                 rq->wqe.wq.db = &rq->wqe.wq.db[MLX5_RCV_DBR];
 503
 504                 wq_sz = mlx5_wq_cyc_get_size(&rq->wqe.wq);
 505
 506                 if (xsk)
 507                         num_xsk_frames = wq_sz << rq->wqe.info.log_num_frags;
 508
 509                 rq->wqe.info = rqp->frags_info;
 510                 rq->wqe.frags =
 511                         kvzalloc_node(array_size(sizeof(*rq->wqe.frags),
 512                                         (wq_sz << rq->wqe.info.log_num_frags)),
 513                                       GFP_KERNEL, cpu_to_node(c->cpu));
 514                 if (!rq->wqe.frags) {
 515                         err = -ENOMEM;
 516                         goto err_free;
 517                 }
 518
 519                 err = mlx5e_init_di_list(rq, wq_sz, c->cpu);
 520                 if (err)
 521                         goto err_free;
 522
 523                 rq->post_wqes = mlx5e_post_rx_wqes;
 524                 rq->dealloc_wqe = mlx5e_dealloc_rx_wqe;
 525
 526 #ifdef CONFIG_MLX5_EN_IPSEC
 527                 if (c->priv->ipsec)
 528                         rq->handle_rx_cqe = mlx5e_ipsec_handle_rx_cqe;
 529                 else
 530 #endif
 531                         rq->handle_rx_cqe = c->priv->profile->rx_handlers.handle_rx_cqe;
 532                 if (!rq->handle_rx_cqe) {
 533                         err = -EINVAL;
 534                         netdev_err(c->netdev, "RX handler of RQ is not set, err %d\n", err);
 535                         goto err_free;
 536                 }
 537
 538                 rq->wqe.skb_from_cqe = xsk ?
 539                         mlx5e_xsk_skb_from_cqe_linear :
 540                         mlx5e_rx_is_linear_skb(params, NULL) ?
 541                                 mlx5e_skb_from_cqe_linear :
 542                                 mlx5e_skb_from_cqe_nonlinear;
 543                 rq->mkey_be = c->mkey_be;
 544         }
 545
 546         if (xsk) {
 547                 err = mlx5e_xsk_resize_reuseq(umem, num_xsk_frames);
 548                 if (unlikely(err)) {
 549                         mlx5_core_err(mdev, "Unable to allocate the Reuse Ring for %u frames\n",
 550                                       num_xsk_frames);
 551                         goto err_free;
 552                 }
 553
 554                 rq->zca.free = mlx5e_xsk_zca_free;
 555                 err = xdp_rxq_info_reg_mem_model(&rq->xdp_rxq,
 556                                                  MEM_TYPE_ZERO_COPY,
 557                                                  &rq->zca);
 558         } else {
 559                 /* Create a page_pool and register it with rxq */
 560                 pp_params.order     = 0;
 561                 pp_params.flags     = 0; /* No-internal DMA mapping in page_pool */
 562                 pp_params.pool_size = pool_size;
 563                 pp_params.nid       = cpu_to_node(c->cpu);
 564                 pp_params.dev       = c->pdev;
 565                 pp_params.dma_dir   = rq->buff.map_dir;
 566
 567                 /* page_pool can be used even when there is no rq->xdp_prog,
 568                  * given page_pool does not handle DMA mapping there is no
 569                  * required state to clear. And page_pool gracefully handle
 570                  * elevated refcnt.
 571                  */
 572                 rq->page_pool = page_pool_create(&pp_params);
 573                 if (IS_ERR(rq->page_pool)) {
 574                         err = PTR_ERR(rq->page_pool);
 575                         rq->page_pool = NULL;
 576                         goto err_free;
 577                 }
 578                 err = xdp_rxq_info_reg_mem_model(&rq->xdp_rxq,
 579                                                  MEM_TYPE_PAGE_POOL, rq->page_pool);
 580         }
 581         if (err)
 582                 goto err_free;
 583
 584         for (i = 0; i < wq_sz; i++) {
 585                 if (rq->wq_type == MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ) {
 586                         struct mlx5e_rx_wqe_ll *wqe =
 587                                 mlx5_wq_ll_get_wqe(&rq->mpwqe.wq, i);
 588                         u32 byte_count =
 589                                 rq->mpwqe.num_strides << rq->mpwqe.log_stride_sz;
 590                         u64 dma_offset = mlx5e_get_mpwqe_offset(rq, i);
 591
 592                         wqe->data[0].addr = cpu_to_be64(dma_offset + rq->buff.headroom);
 593                         wqe->data[0].byte_count = cpu_to_be32(byte_count);
 594                         wqe->data[0].lkey = rq->mkey_be;
 595                 } else {
 596                         struct mlx5e_rx_wqe_cyc *wqe =
 597                                 mlx5_wq_cyc_get_wqe(&rq->wqe.wq, i);
 598                         int f;
 599
 600                         for (f = 0; f < rq->wqe.info.num_frags; f++) {
 601                                 u32 frag_size = rq->wqe.info.arr[f].frag_size |
 602                                         MLX5_HW_START_PADDING;
 603
 604                                 wqe->data[f].byte_count = cpu_to_be32(frag_size);
 605                                 wqe->data[f].lkey = rq->mkey_be;
 606                         }
 607                         /* check if num_frags is not a pow of two */
 608                         if (rq->wqe.info.num_frags < (1 << rq->wqe.info.log_num_frags)) {
 609                                 wqe->data[f].byte_count = 0;
 610                                 wqe->data[f].lkey = cpu_to_be32(MLX5_INVALID_LKEY);
 611                                 wqe->data[f].addr = 0;
 612                         }
 613                 }
 614         }
 615
 616         INIT_WORK(&rq->dim.work, mlx5e_rx_dim_work);
 617
 618         switch (params->rx_cq_moderation.cq_period_mode) {
 619         case MLX5_CQ_PERIOD_MODE_START_FROM_CQE:
 620                 rq->dim.mode = DIM_CQ_PERIOD_MODE_START_FROM_CQE;
 621                 break;
 622         case MLX5_CQ_PERIOD_MODE_START_FROM_EQE:
 623         default:
 624                 rq->dim.mode = DIM_CQ_PERIOD_MODE_START_FROM_EQE;
 625         }
 626
 627         rq->page_cache.head = 0;
 628         rq->page_cache.tail = 0;
 629
 630         return 0;
 631
 632 err_free:
 633         switch (rq->wq_type) {
 634         case MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ:
 635                 kvfree(rq->mpwqe.info);
 636                 mlx5_core_destroy_mkey(mdev, &rq->umr_mkey);
 637                 break;
 638         default: /* MLX5_WQ_TYPE_CYCLIC */
 639                 kvfree(rq->wqe.frags);
 640                 mlx5e_free_di_list(rq);
 641         }
 642
 643 err_rq_wq_destroy:
 644         if (rq->xdp_prog)
 645                 bpf_prog_put(rq->xdp_prog);
 646         xdp_rxq_info_unreg(&rq->xdp_rxq);
 647         page_pool_destroy(rq->page_pool);
 648         mlx5_wq_destroy(&rq->wq_ctrl);
 649
 650         return err;
 651 }
 652
 653 static void mlx5e_free_rq(struct mlx5e_rq *rq)
 654 {
 655         int i;
 656
 657         if (rq->xdp_prog)
 658                 bpf_prog_put(rq->xdp_prog);
 659
 660         switch (rq->wq_type) {
 661         case MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ:
 662                 kvfree(rq->mpwqe.info);
 663                 mlx5_core_destroy_mkey(rq->mdev, &rq->umr_mkey);
 664                 break;
 665         default: /* MLX5_WQ_TYPE_CYCLIC */
 666                 kvfree(rq->wqe.frags);
 667                 mlx5e_free_di_list(rq);
 668         }
 669
 670         for (i = rq->page_cache.head; i != rq->page_cache.tail;
 671              i = (i + 1) & (MLX5E_CACHE_SIZE - 1)) {
 672                 struct mlx5e_dma_info *dma_info = &rq->page_cache.page_cache[i];
 673
 674                 /* With AF_XDP, page_cache is not used, so this loop is not
 675                  * entered, and it's safe to call mlx5e_page_release_dynamic
 676                  * directly.
 677                  */
 678                 mlx5e_page_release_dynamic(rq, dma_info, false);
 679         }
 680
 681         xdp_rxq_info_unreg(&rq->xdp_rxq);
 682         page_pool_destroy(rq->page_pool);
 683         mlx5_wq_destroy(&rq->wq_ctrl);
 684 }
 685
 686 static int mlx5e_create_rq(struct mlx5e_rq *rq,
 687                            struct mlx5e_rq_param *param)
 688 {
 689         struct mlx5_core_dev *mdev = rq->mdev;
 690
 691         void *in;
 692         void *rqc;
 693         void *wq;
 694         int inlen;
 695         int err;
 696
 697         inlen = MLX5_ST_SZ_BYTES(create_rq_in) +
 698                 sizeof(u64) * rq->wq_ctrl.buf.npages;
 699         in = kvzalloc(inlen, GFP_KERNEL);
 700         if (!in)
 701                 return -ENOMEM;
 702
 703         rqc = MLX5_ADDR_OF(create_rq_in, in, ctx);
 704         wq  = MLX5_ADDR_OF(rqc, rqc, wq);
 705
 706         memcpy(rqc, param->rqc, sizeof(param->rqc));
 707
 708         MLX5_SET(rqc,  rqc, cqn,                rq->cq.mcq.cqn);
 709         MLX5_SET(rqc,  rqc, state,              MLX5_RQC_STATE_RST);
 710         MLX5_SET(wq,   wq,  log_wq_pg_sz,       rq->wq_ctrl.buf.page_shift -
 711                                                 MLX5_ADAPTER_PAGE_SHIFT);
 712         MLX5_SET64(wq, wq,  dbr_addr,           rq->wq_ctrl.db.dma);
 713
 714         mlx5_fill_page_frag_array(&rq->wq_ctrl.buf,
 715                                   (__be64 *)MLX5_ADDR_OF(wq, wq, pas));
 716
 717         err = mlx5_core_create_rq(mdev, in, inlen, &rq->rqn);
 718
 719         kvfree(in);
 720
 721         return err;
 722 }
 723
 724 static int mlx5e_modify_rq_state(struct mlx5e_rq *rq, int curr_state,
 725                                  int next_state)
 726 {
 727         struct mlx5_core_dev *mdev = rq->mdev;
 728
 729         void *in;
 730         void *rqc;
 731         int inlen;
 732         int err;
 733
 734         inlen = MLX5_ST_SZ_BYTES(modify_rq_in);
 735         in = kvzalloc(inlen, GFP_KERNEL);
 736         if (!in)
 737                 return -ENOMEM;
 738
 739         rqc = MLX5_ADDR_OF(modify_rq_in, in, ctx);
 740
 741         MLX5_SET(modify_rq_in, in, rq_state, curr_state);
 742         MLX5_SET(rqc, rqc, state, next_state);
 743
 744         err = mlx5_core_modify_rq(mdev, rq->rqn, in, inlen);
 745
 746         kvfree(in);
 747
 748         return err;
 749 }
 750
 751 static int mlx5e_modify_rq_scatter_fcs(struct mlx5e_rq *rq, bool enable)
 752 {
 753         struct mlx5e_channel *c = rq->channel;
 754         struct mlx5e_priv *priv = c->priv;
 755         struct mlx5_core_dev *mdev = priv->mdev;
 756
 757         void *in;
 758         void *rqc;
 759         int inlen;
 760         int err;
 761
 762         inlen = MLX5_ST_SZ_BYTES(modify_rq_in);
 763         in = kvzalloc(inlen, GFP_KERNEL);
 764         if (!in)
 765                 return -ENOMEM;
 766
 767         rqc = MLX5_ADDR_OF(modify_rq_in, in, ctx);
 768
 769         MLX5_SET(modify_rq_in, in, rq_state, MLX5_RQC_STATE_RDY);
 770         MLX5_SET64(modify_rq_in, in, modify_bitmask,
 771                    MLX5_MODIFY_RQ_IN_MODIFY_BITMASK_SCATTER_FCS);
 772         MLX5_SET(rqc, rqc, scatter_fcs, enable);
 773         MLX5_SET(rqc, rqc, state, MLX5_RQC_STATE_RDY);
 774
 775         err = mlx5_core_modify_rq(mdev, rq->rqn, in, inlen);
 776
 777         kvfree(in);
 778
 779         return err;
 780 }
 781
 782 static int mlx5e_modify_rq_vsd(struct mlx5e_rq *rq, bool vsd)
 783 {
 784         struct mlx5e_channel *c = rq->channel;
 785         struct mlx5_core_dev *mdev = c->mdev;
 786         void *in;
 787         void *rqc;
 788         int inlen;
 789         int err;
 790
 791         inlen = MLX5_ST_SZ_BYTES(modify_rq_in);
 792         in = kvzalloc(inlen, GFP_KERNEL);
 793         if (!in)
 794                 return -ENOMEM;
 795
 796         rqc = MLX5_ADDR_OF(modify_rq_in, in, ctx);
 797
 798         MLX5_SET(modify_rq_in, in, rq_state, MLX5_RQC_STATE_RDY);
 799         MLX5_SET64(modify_rq_in, in, modify_bitmask,
 800                    MLX5_MODIFY_RQ_IN_MODIFY_BITMASK_VSD);
 801         MLX5_SET(rqc, rqc, vsd, vsd);
 802         MLX5_SET(rqc, rqc, state, MLX5_RQC_STATE_RDY);
 803
 804         err = mlx5_core_modify_rq(mdev, rq->rqn, in, inlen);
 805
 806         kvfree(in);
 807
 808         return err;
 809 }
 810
 811 static void mlx5e_destroy_rq(struct mlx5e_rq *rq)
 812 {
 813         mlx5_core_destroy_rq(rq->mdev, rq->rqn);
 814 }
 815
 816 int mlx5e_wait_for_min_rx_wqes(struct mlx5e_rq *rq, int wait_time)
 817 {
 818         unsigned long exp_time = jiffies + msecs_to_jiffies(wait_time);
 819         struct mlx5e_channel *c = rq->channel;
 820
 821         u16 min_wqes = mlx5_min_rx_wqes(rq->wq_type, mlx5e_rqwq_get_size(rq));
 822
 823         do {
 824                 if (mlx5e_rqwq_get_cur_sz(rq) >= min_wqes)
 825                         return 0;
 826
 827                 msleep(20);
 828         } while (time_before(jiffies, exp_time));
 829
 830         netdev_warn(c->netdev, "Failed to get min RX wqes on Channel[%d] RQN[0x%x] wq cur_sz(%d) min_rx_wqes(%d)\n",
 831                     c->ix, rq->rqn, mlx5e_rqwq_get_cur_sz(rq), min_wqes);
 832
 833         return -ETIMEDOUT;
 834 }
 835
 836 static void mlx5e_free_rx_descs(struct mlx5e_rq *rq)
 837 {
 838         __be16 wqe_ix_be;
 839         u16 wqe_ix;
 840
 841         if (rq->wq_type == MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ) {
 842                 struct mlx5_wq_ll *wq = &rq->mpwqe.wq;
 843                 u16 head = wq->head;
 844                 int i;
 845
 846                 /* Outstanding UMR WQEs (in progress) start at wq->head */
 847                 for (i = 0; i < rq->mpwqe.umr_in_progress; i++) {
 848                         rq->dealloc_wqe(rq, head);
 849                         head = mlx5_wq_ll_get_wqe_next_ix(wq, head);
 850                 }
 851
 852                 while (!mlx5_wq_ll_is_empty(wq)) {
 853                         struct mlx5e_rx_wqe_ll *wqe;
 854
 855                         wqe_ix_be = *wq->tail_next;
 856                         wqe_ix    = be16_to_cpu(wqe_ix_be);
 857                         wqe       = mlx5_wq_ll_get_wqe(wq, wqe_ix);
 858                         rq->dealloc_wqe(rq, wqe_ix);
 859                         mlx5_wq_ll_pop(wq, wqe_ix_be,
 860                                        &wqe->next.next_wqe_index);
 861                 }
 862         } else {
 863                 struct mlx5_wq_cyc *wq = &rq->wqe.wq;
 864
 865                 while (!mlx5_wq_cyc_is_empty(wq)) {
 866                         wqe_ix = mlx5_wq_cyc_get_tail(wq);
 867                         rq->dealloc_wqe(rq, wqe_ix);
 868                         mlx5_wq_cyc_pop(wq);
 869                 }
 870         }
 871
 872 }
 873
 874 int mlx5e_open_rq(struct mlx5e_channel *c, struct mlx5e_params *params,
 875                   struct mlx5e_rq_param *param, struct mlx5e_xsk_param *xsk,
 876                   struct xdp_umem *umem, struct mlx5e_rq *rq)
 877 {
 878         int err;
 879
 880         err = mlx5e_alloc_rq(c, params, xsk, umem, param, rq);
 881         if (err)
 882                 return err;
 883
 884         err = mlx5e_create_rq(rq, param);
 885         if (err)
 886                 goto err_free_rq;
 887
 888         err = mlx5e_modify_rq_state(rq, MLX5_RQC_STATE_RST, MLX5_RQC_STATE_RDY);
 889         if (err)
 890                 goto err_destroy_rq;
 891
 892         if (MLX5_CAP_ETH(c->mdev, cqe_checksum_full))
 893                 __set_bit(MLX5E_RQ_STATE_CSUM_FULL, &c->rq.state);
 894
 895         if (params->rx_dim_enabled)
 896                 __set_bit(MLX5E_RQ_STATE_AM, &c->rq.state);
 897
 898         /* We disable csum_complete when XDP is enabled since
 899          * XDP programs might manipulate packets which will render
 900          * skb->checksum incorrect.
 901          */
 902         if (MLX5E_GET_PFLAG(params, MLX5E_PFLAG_RX_NO_CSUM_COMPLETE) || c->xdp)
 903                 __set_bit(MLX5E_RQ_STATE_NO_CSUM_COMPLETE, &c->rq.state);
 904
 905         return 0;
 906
 907 err_destroy_rq:
 908         mlx5e_destroy_rq(rq);
 909 err_free_rq:
 910         mlx5e_free_rq(rq);
 911
 912         return err;
 913 }
 914
 915 static void mlx5e_activate_rq(struct mlx5e_rq *rq)
 916 {
 917         set_bit(MLX5E_RQ_STATE_ENABLED, &rq->state);
 918         mlx5e_trigger_irq(&rq->channel->icosq);
 919 }
 920
 921 void mlx5e_deactivate_rq(struct mlx5e_rq *rq)
 922 {
 923         clear_bit(MLX5E_RQ_STATE_ENABLED, &rq->state);
 924         napi_synchronize(&rq->channel->napi); /* prevent mlx5e_post_rx_wqes */
 925 }
 926
 927 void mlx5e_close_rq(struct mlx5e_rq *rq)
 928 {
 929         cancel_work_sync(&rq->dim.work);
 930         mlx5e_destroy_rq(rq);
 931         mlx5e_free_rx_descs(rq);
 932         mlx5e_free_rq(rq);
 933 }
 934
 935 static void mlx5e_free_xdpsq_db(struct mlx5e_xdpsq *sq)
 936 {
 937         kvfree(sq->db.xdpi_fifo.xi);
 938         kvfree(sq->db.wqe_info);
 939 }
 940
 941 static int mlx5e_alloc_xdpsq_fifo(struct mlx5e_xdpsq *sq, int numa)
 942 {
 943         struct mlx5e_xdp_info_fifo *xdpi_fifo = &sq->db.xdpi_fifo;
 944         int wq_sz        = mlx5_wq_cyc_get_size(&sq->wq);
 945         int dsegs_per_wq = wq_sz * MLX5_SEND_WQEBB_NUM_DS;
 946
 947         xdpi_fifo->xi = kvzalloc_node(sizeof(*xdpi_fifo->xi) * dsegs_per_wq,
 948                                       GFP_KERNEL, numa);
 949         if (!xdpi_fifo->xi)
 950                 return -ENOMEM;
 951
 952         xdpi_fifo->pc   = &sq->xdpi_fifo_pc;
 953         xdpi_fifo->cc   = &sq->xdpi_fifo_cc;
 954         xdpi_fifo->mask = dsegs_per_wq - 1;
 955
 956         return 0;
 957 }
 958
 959 static int mlx5e_alloc_xdpsq_db(struct mlx5e_xdpsq *sq, int numa)
 960 {
 961         int wq_sz = mlx5_wq_cyc_get_size(&sq->wq);
 962         int err;
 963
 964         sq->db.wqe_info = kvzalloc_node(sizeof(*sq->db.wqe_info) * wq_sz,
 965                                         GFP_KERNEL, numa);
 966         if (!sq->db.wqe_info)
 967                 return -ENOMEM;
 968
 969         err = mlx5e_alloc_xdpsq_fifo(sq, numa);
 970         if (err) {
 971                 mlx5e_free_xdpsq_db(sq);
 972                 return err;
 973         }
 974
 975         return 0;
 976 }
 977
 978 static int mlx5e_alloc_xdpsq(struct mlx5e_channel *c,
 979                              struct mlx5e_params *params,
 980                              struct xdp_umem *umem,
 981                              struct mlx5e_sq_param *param,
 982                              struct mlx5e_xdpsq *sq,
 983                              bool is_redirect)
 984 {
 985         void *sqc_wq               = MLX5_ADDR_OF(sqc, param->sqc, wq);
 986         struct mlx5_core_dev *mdev = c->mdev;
 987         struct mlx5_wq_cyc *wq = &sq->wq;
 988         int err;
 989
 990         sq->pdev      = c->pdev;
 991         sq->mkey_be   = c->mkey_be;
 992         sq->channel   = c;
 993         sq->uar_map   = mdev->mlx5e_res.bfreg.map;
 994         sq->min_inline_mode = params->tx_min_inline_mode;
 995         sq->hw_mtu    = MLX5E_SW2HW_MTU(params, params->sw_mtu);
 996         sq->umem      = umem;
 997
 998         sq->stats = sq->umem ?
 999                 &c->priv->channel_stats[c->ix].xsksq :
1000                 is_redirect ?
1001                         &c->priv->channel_stats[c->ix].xdpsq :
1002                         &c->priv->channel_stats[c->ix].rq_xdpsq;
1003
1004         param->wq.db_numa_node = cpu_to_node(c->cpu);
1005         err = mlx5_wq_cyc_create(mdev, &param->wq, sqc_wq, wq, &sq->wq_ctrl);
1006         if (err)
1007                 return err;
1008         wq->db = &wq->db[MLX5_SND_DBR];
1009
1010         err = mlx5e_alloc_xdpsq_db(sq, cpu_to_node(c->cpu));
1011         if (err)
1012                 goto err_sq_wq_destroy;
1013
1014         return 0;
1015
1016 err_sq_wq_destroy:
1017         mlx5_wq_destroy(&sq->wq_ctrl);
1018
1019         return err;
1020 }
1021
1022 static void mlx5e_free_xdpsq(struct mlx5e_xdpsq *sq)
1023 {
1024         mlx5e_free_xdpsq_db(sq);
1025         mlx5_wq_destroy(&sq->wq_ctrl);
1026 }
1027
1028 static void mlx5e_free_icosq_db(struct mlx5e_icosq *sq)
1029 {
1030         kvfree(sq->db.ico_wqe);
1031 }
1032
1033 static int mlx5e_alloc_icosq_db(struct mlx5e_icosq *sq, int numa)
1034 {
1035         int wq_sz = mlx5_wq_cyc_get_size(&sq->wq);
1036
1037         sq->db.ico_wqe = kvzalloc_node(array_size(wq_sz,
1038                                                   sizeof(*sq->db.ico_wqe)),
1039                                        GFP_KERNEL, numa);
1040         if (!sq->db.ico_wqe)
1041                 return -ENOMEM;
1042
1043         return 0;
1044 }
1045
1046 static int mlx5e_alloc_icosq(struct mlx5e_channel *c,
1047                              struct mlx5e_sq_param *param,
1048                              struct mlx5e_icosq *sq)
1049 {
1050         void *sqc_wq               = MLX5_ADDR_OF(sqc, param->sqc, wq);
1051         struct mlx5_core_dev *mdev = c->mdev;
1052         struct mlx5_wq_cyc *wq = &sq->wq;
1053         int err;
1054
1055         sq->channel   = c;
1056         sq->uar_map   = mdev->mlx5e_res.bfreg.map;
1057
1058         param->wq.db_numa_node = cpu_to_node(c->cpu);
1059         err = mlx5_wq_cyc_create(mdev, &param->wq, sqc_wq, wq, &sq->wq_ctrl);
1060         if (err)
1061                 return err;
1062         wq->db = &wq->db[MLX5_SND_DBR];
1063
1064         err = mlx5e_alloc_icosq_db(sq, cpu_to_node(c->cpu));
1065         if (err)
1066                 goto err_sq_wq_destroy;
1067
1068         return 0;
1069
1070 err_sq_wq_destroy:
1071         mlx5_wq_destroy(&sq->wq_ctrl);
1072
1073         return err;
1074 }
1075
1076 static void mlx5e_free_icosq(struct mlx5e_icosq *sq)
1077 {
1078         mlx5e_free_icosq_db(sq);
1079         mlx5_wq_destroy(&sq->wq_ctrl);
1080 }
1081
1082 static void mlx5e_free_txqsq_db(struct mlx5e_txqsq *sq)
1083 {
1084         kvfree(sq->db.wqe_info);
1085         kvfree(sq->db.dma_fifo);
1086 }
1087
1088 static int mlx5e_alloc_txqsq_db(struct mlx5e_txqsq *sq, int numa)
1089 {
1090         int wq_sz = mlx5_wq_cyc_get_size(&sq->wq);
1091         int df_sz = wq_sz * MLX5_SEND_WQEBB_NUM_DS;
1092
1093         sq->db.dma_fifo = kvzalloc_node(array_size(df_sz,
1094                                                    sizeof(*sq->db.dma_fifo)),
1095                                         GFP_KERNEL, numa);
1096         sq->db.wqe_info = kvzalloc_node(array_size(wq_sz,
1097                                                    sizeof(*sq->db.wqe_info)),
1098                                         GFP_KERNEL, numa);
1099         if (!sq->db.dma_fifo || !sq->db.wqe_info) {
1100                 mlx5e_free_txqsq_db(sq);
1101                 return -ENOMEM;
1102         }
1103
1104         sq->dma_fifo_mask = df_sz - 1;
1105
1106         return 0;
1107 }
1108
1109 static void mlx5e_tx_err_cqe_work(struct work_struct *recover_work);
1110 static int mlx5e_alloc_txqsq(struct mlx5e_channel *c,
1111                              int txq_ix,
1112                              struct mlx5e_params *params,
1113                              struct mlx5e_sq_param *param,
1114                              struct mlx5e_txqsq *sq,
1115                              int tc)
1116 {
1117         void *sqc_wq               = MLX5_ADDR_OF(sqc, param->sqc, wq);
1118         struct mlx5_core_dev *mdev = c->mdev;
1119         struct mlx5_wq_cyc *wq = &sq->wq;
1120         int err;
1121
1122         sq->pdev      = c->pdev;
1123         sq->tstamp    = c->tstamp;
1124         sq->clock     = &mdev->clock;
1125         sq->mkey_be   = c->mkey_be;
1126         sq->channel   = c;
1127         sq->ch_ix     = c->ix;
1128         sq->txq_ix    = txq_ix;
1129         sq->uar_map   = mdev->mlx5e_res.bfreg.map;
1130         sq->min_inline_mode = params->tx_min_inline_mode;
1131         sq->stats     = &c->priv->channel_stats[c->ix].sq[tc];
1132         sq->stop_room = MLX5E_SQ_STOP_ROOM;
1133         INIT_WORK(&sq->recover_work, mlx5e_tx_err_cqe_work);
1134         if (!MLX5_CAP_ETH(mdev, wqe_vlan_insert))
1135                 set_bit(MLX5E_SQ_STATE_VLAN_NEED_L2_INLINE, &sq->state);
1136         if (MLX5_IPSEC_DEV(c->priv->mdev))
1137                 set_bit(MLX5E_SQ_STATE_IPSEC, &sq->state);
1138         if (mlx5_accel_is_tls_device(c->priv->mdev)) {
1139                 set_bit(MLX5E_SQ_STATE_TLS, &sq->state);
1140                 sq->stop_room += MLX5E_SQ_TLS_ROOM;
1141         }
1142
1143         param->wq.db_numa_node = cpu_to_node(c->cpu);
1144         err = mlx5_wq_cyc_create(mdev, &param->wq, sqc_wq, wq, &sq->wq_ctrl);
1145         if (err)
1146                 return err;
1147         wq->db    = &wq->db[MLX5_SND_DBR];
1148
1149         err = mlx5e_alloc_txqsq_db(sq, cpu_to_node(c->cpu));
1150         if (err)
1151                 goto err_sq_wq_destroy;
1152
1153         INIT_WORK(&sq->dim.work, mlx5e_tx_dim_work);
1154         sq->dim.mode = params->tx_cq_moderation.cq_period_mode;
1155
1156         return 0;
1157
1158 err_sq_wq_destroy:
1159         mlx5_wq_destroy(&sq->wq_ctrl);
1160
1161         return err;
1162 }
1163
1164 static void mlx5e_free_txqsq(struct mlx5e_txqsq *sq)
1165 {
1166         mlx5e_free_txqsq_db(sq);
1167         mlx5_wq_destroy(&sq->wq_ctrl);
1168 }
1169
1170 struct mlx5e_create_sq_param {
1171         struct mlx5_wq_ctrl        *wq_ctrl;
1172         u32                         cqn;
1173         u32                         tisn;
1174         u8                          tis_lst_sz;
1175         u8                          min_inline_mode;
1176 };
1177
1178 static int mlx5e_create_sq(struct mlx5_core_dev *mdev,
1179                            struct mlx5e_sq_param *param,
1180                            struct mlx5e_create_sq_param *csp,
1181                            u32 *sqn)
1182 {
1183         void *in;
1184         void *sqc;
1185         void *wq;
1186         int inlen;
1187         int err;
1188
1189         inlen = MLX5_ST_SZ_BYTES(create_sq_in) +
1190                 sizeof(u64) * csp->wq_ctrl->buf.npages;
1191         in = kvzalloc(inlen, GFP_KERNEL);
1192         if (!in)
1193                 return -ENOMEM;
1194
1195         sqc = MLX5_ADDR_OF(create_sq_in, in, ctx);
1196         wq = MLX5_ADDR_OF(sqc, sqc, wq);
1197
1198         memcpy(sqc, param->sqc, sizeof(param->sqc));
1199         MLX5_SET(sqc,  sqc, tis_lst_sz, csp->tis_lst_sz);
1200         MLX5_SET(sqc,  sqc, tis_num_0, csp->tisn);
1201         MLX5_SET(sqc,  sqc, cqn, csp->cqn);
1202
1203         if (MLX5_CAP_ETH(mdev, wqe_inline_mode) == MLX5_CAP_INLINE_MODE_VPORT_CONTEXT)
1204                 MLX5_SET(sqc,  sqc, min_wqe_inline_mode, csp->min_inline_mode);
1205
1206         MLX5_SET(sqc,  sqc, state, MLX5_SQC_STATE_RST);
1207         MLX5_SET(sqc,  sqc, flush_in_error_en, 1);
1208
1209         MLX5_SET(wq,   wq, wq_type,       MLX5_WQ_TYPE_CYCLIC);
1210         MLX5_SET(wq,   wq, uar_page,      mdev->mlx5e_res.bfreg.index);
1211         MLX5_SET(wq,   wq, log_wq_pg_sz,  csp->wq_ctrl->buf.page_shift -
1212                                           MLX5_ADAPTER_PAGE_SHIFT);
1213         MLX5_SET64(wq, wq, dbr_addr,      csp->wq_ctrl->db.dma);
1214
1215         mlx5_fill_page_frag_array(&csp->wq_ctrl->buf,
1216                                   (__be64 *)MLX5_ADDR_OF(wq, wq, pas));
1217
1218         err = mlx5_core_create_sq(mdev, in, inlen, sqn);
1219
1220         kvfree(in);
1221
1222         return err;
1223 }
1224
1225 int mlx5e_modify_sq(struct mlx5_core_dev *mdev, u32 sqn,
1226                     struct mlx5e_modify_sq_param *p)
1227 {
1228         void *in;
1229         void *sqc;
1230         int inlen;
1231         int err;
1232
1233         inlen = MLX5_ST_SZ_BYTES(modify_sq_in);
1234         in = kvzalloc(inlen, GFP_KERNEL);
1235         if (!in)
1236                 return -ENOMEM;
1237
1238         sqc = MLX5_ADDR_OF(modify_sq_in, in, ctx);
1239
1240         MLX5_SET(modify_sq_in, in, sq_state, p->curr_state);
1241         MLX5_SET(sqc, sqc, state, p->next_state);
1242         if (p->rl_update && p->next_state == MLX5_SQC_STATE_RDY) {
1243                 MLX5_SET64(modify_sq_in, in, modify_bitmask, 1);
1244                 MLX5_SET(sqc,  sqc, packet_pacing_rate_limit_index, p->rl_index);
1245         }
1246
1247         err = mlx5_core_modify_sq(mdev, sqn, in, inlen);
1248
1249         kvfree(in);
1250
1251         return err;
1252 }
1253
1254 static void mlx5e_destroy_sq(struct mlx5_core_dev *mdev, u32 sqn)
1255 {
1256         mlx5_core_destroy_sq(mdev, sqn);
1257 }
1258
1259 static int mlx5e_create_sq_rdy(struct mlx5_core_dev *mdev,
1260                                struct mlx5e_sq_param *param,
1261                                struct mlx5e_create_sq_param *csp,
1262                                u32 *sqn)
1263 {
1264         struct mlx5e_modify_sq_param msp = {0};
1265         int err;
1266
1267         err = mlx5e_create_sq(mdev, param, csp, sqn);
1268         if (err)
1269                 return err;
1270
1271         msp.curr_state = MLX5_SQC_STATE_RST;
1272         msp.next_state = MLX5_SQC_STATE_RDY;
1273         err = mlx5e_modify_sq(mdev, *sqn, &msp);
1274         if (err)
1275                 mlx5e_destroy_sq(mdev, *sqn);
1276
1277         return err;
1278 }
1279
1280 static int mlx5e_set_sq_maxrate(struct net_device *dev,
1281                                 struct mlx5e_txqsq *sq, u32 rate);
1282
1283 static int mlx5e_open_txqsq(struct mlx5e_channel *c,
1284                             u32 tisn,
1285                             int txq_ix,
1286                             struct mlx5e_params *params,
1287                             struct mlx5e_sq_param *param,
1288                             struct mlx5e_txqsq *sq,
1289                             int tc)
1290 {
1291         struct mlx5e_create_sq_param csp = {};
1292         u32 tx_rate;
1293         int err;
1294
1295         err = mlx5e_alloc_txqsq(c, txq_ix, params, param, sq, tc);
1296         if (err)
1297                 return err;
1298
1299         csp.tisn            = tisn;
1300         csp.tis_lst_sz      = 1;
1301         csp.cqn             = sq->cq.mcq.cqn;
1302         csp.wq_ctrl         = &sq->wq_ctrl;
1303         csp.min_inline_mode = sq->min_inline_mode;
1304         err = mlx5e_create_sq_rdy(c->mdev, param, &csp, &sq->sqn);
1305         if (err)
1306                 goto err_free_txqsq;
1307
1308         tx_rate = c->priv->tx_rates[sq->txq_ix];
1309         if (tx_rate)
1310                 mlx5e_set_sq_maxrate(c->netdev, sq, tx_rate);
1311
1312         if (params->tx_dim_enabled)
1313                 sq->state |= BIT(MLX5E_SQ_STATE_AM);
1314
1315         return 0;
1316
1317 err_free_txqsq:
1318         clear_bit(MLX5E_SQ_STATE_ENABLED, &sq->state);
1319         mlx5e_free_txqsq(sq);
1320
1321         return err;
1322 }
1323
1324 void mlx5e_activate_txqsq(struct mlx5e_txqsq *sq)
1325 {
1326         sq->txq = netdev_get_tx_queue(sq->channel->netdev, sq->txq_ix);
1327         clear_bit(MLX5E_SQ_STATE_RECOVERING, &sq->state);
1328         set_bit(MLX5E_SQ_STATE_ENABLED, &sq->state);
1329         netdev_tx_reset_queue(sq->txq);
1330         netif_tx_start_queue(sq->txq);
1331 }
1332
1333 void mlx5e_tx_disable_queue(struct netdev_queue *txq)
1334 {
1335         __netif_tx_lock_bh(txq);
1336         netif_tx_stop_queue(txq);
1337         __netif_tx_unlock_bh(txq);
1338 }
1339
1340 static void mlx5e_deactivate_txqsq(struct mlx5e_txqsq *sq)
1341 {
1342         struct mlx5e_channel *c = sq->channel;
1343         struct mlx5_wq_cyc *wq = &sq->wq;
1344
1345         clear_bit(MLX5E_SQ_STATE_ENABLED, &sq->state);
1346         /* prevent netif_tx_wake_queue */
1347         napi_synchronize(&c->napi);
1348
1349         mlx5e_tx_disable_queue(sq->txq);
1350
1351         /* last doorbell out, godspeed .. */
1352         if (mlx5e_wqc_has_room_for(wq, sq->cc, sq->pc, 1)) {
1353                 u16 pi = mlx5_wq_cyc_ctr2ix(wq, sq->pc);
1354                 struct mlx5e_tx_wqe *nop;
1355
1356                 sq->db.wqe_info[pi].skb = NULL;
1357                 nop = mlx5e_post_nop(wq, sq->sqn, &sq->pc);
1358                 mlx5e_notify_hw(wq, sq->pc, sq->uar_map, &nop->ctrl);
1359         }
1360 }
1361
1362 static void mlx5e_close_txqsq(struct mlx5e_txqsq *sq)
1363 {
1364         struct mlx5e_channel *c = sq->channel;
1365         struct mlx5_core_dev *mdev = c->mdev;
1366         struct mlx5_rate_limit rl = {0};
1367
1368         cancel_work_sync(&sq->dim.work);
1369         cancel_work_sync(&sq->recover_work);
1370         mlx5e_destroy_sq(mdev, sq->sqn);
1371         if (sq->rate_limit) {
1372                 rl.rate = sq->rate_limit;
1373                 mlx5_rl_remove_rate(mdev, &rl);
1374         }
1375         mlx5e_free_txqsq_descs(sq);
1376         mlx5e_free_txqsq(sq);
1377 }
1378
1379 static void mlx5e_tx_err_cqe_work(struct work_struct *recover_work)
1380 {
1381         struct mlx5e_txqsq *sq = container_of(recover_work, struct mlx5e_txqsq,
1382                                               recover_work);
1383
1384         mlx5e_tx_reporter_err_cqe(sq);
1385 }
1386
1387 int mlx5e_open_icosq(struct mlx5e_channel *c, struct mlx5e_params *params,
1388                      struct mlx5e_sq_param *param, struct mlx5e_icosq *sq)
1389 {
1390         struct mlx5e_create_sq_param csp = {};
1391         int err;
1392
1393         err = mlx5e_alloc_icosq(c, param, sq);
1394         if (err)
1395                 return err;
1396
1397         csp.cqn             = sq->cq.mcq.cqn;
1398         csp.wq_ctrl         = &sq->wq_ctrl;
1399         csp.min_inline_mode = params->tx_min_inline_mode;
1400         set_bit(MLX5E_SQ_STATE_ENABLED, &sq->state);
1401         err = mlx5e_create_sq_rdy(c->mdev, param, &csp, &sq->sqn);
1402         if (err)
1403                 goto err_free_icosq;
1404
1405         return 0;
1406
1407 err_free_icosq:
1408         clear_bit(MLX5E_SQ_STATE_ENABLED, &sq->state);
1409         mlx5e_free_icosq(sq);
1410
1411         return err;
1412 }
1413
1414 void mlx5e_close_icosq(struct mlx5e_icosq *sq)
1415 {
1416         struct mlx5e_channel *c = sq->channel;
1417
1418         clear_bit(MLX5E_SQ_STATE_ENABLED, &sq->state);
1419         napi_synchronize(&c->napi);
1420
1421         mlx5e_destroy_sq(c->mdev, sq->sqn);
1422         mlx5e_free_icosq(sq);
1423 }
1424
1425 int mlx5e_open_xdpsq(struct mlx5e_channel *c, struct mlx5e_params *params,
1426                      struct mlx5e_sq_param *param, struct xdp_umem *umem,
1427                      struct mlx5e_xdpsq *sq, bool is_redirect)
1428 {
1429         struct mlx5e_create_sq_param csp = {};
1430         int err;
1431
1432         err = mlx5e_alloc_xdpsq(c, params, umem, param, sq, is_redirect);
1433         if (err)
1434                 return err;
1435
1436         csp.tis_lst_sz      = 1;
1437         csp.tisn            = c->priv->tisn[0]; /* tc = 0 */
1438         csp.cqn             = sq->cq.mcq.cqn;
1439         csp.wq_ctrl         = &sq->wq_ctrl;
1440         csp.min_inline_mode = sq->min_inline_mode;
1441         set_bit(MLX5E_SQ_STATE_ENABLED, &sq->state);
1442         err = mlx5e_create_sq_rdy(c->mdev, param, &csp, &sq->sqn);
1443         if (err)
1444                 goto err_free_xdpsq;
1445
1446         mlx5e_set_xmit_fp(sq, param->is_mpw);
1447
1448         if (!param->is_mpw) {
1449                 unsigned int ds_cnt = MLX5E_XDP_TX_DS_COUNT;
1450                 unsigned int inline_hdr_sz = 0;
1451                 int i;
1452
1453                 if (sq->min_inline_mode != MLX5_INLINE_MODE_NONE) {
1454                         inline_hdr_sz = MLX5E_XDP_MIN_INLINE;
1455                         ds_cnt++;
1456                 }
1457
1458                 /* Pre initialize fixed WQE fields */
1459                 for (i = 0; i < mlx5_wq_cyc_get_size(&sq->wq); i++) {
1460                         struct mlx5e_xdp_wqe_info *wi  = &sq->db.wqe_info[i];
1461                         struct mlx5e_tx_wqe      *wqe  = mlx5_wq_cyc_get_wqe(&sq->wq, i);
1462                         struct mlx5_wqe_ctrl_seg *cseg = &wqe->ctrl;
1463                         struct mlx5_wqe_eth_seg  *eseg = &wqe->eth;
1464                         struct mlx5_wqe_data_seg *dseg;
1465
1466                         cseg->qpn_ds = cpu_to_be32((sq->sqn << 8) | ds_cnt);
1467                         eseg->inline_hdr.sz = cpu_to_be16(inline_hdr_sz);
1468
1469                         dseg = (struct mlx5_wqe_data_seg *)cseg + (ds_cnt - 1);
1470                         dseg->lkey = sq->mkey_be;
1471
1472                         wi->num_wqebbs = 1;
1473                         wi->num_pkts   = 1;
1474                 }
1475         }
1476
1477         return 0;
1478
1479 err_free_xdpsq:
1480         clear_bit(MLX5E_SQ_STATE_ENABLED, &sq->state);
1481         mlx5e_free_xdpsq(sq);
1482
1483         return err;
1484 }
1485
1486 void mlx5e_close_xdpsq(struct mlx5e_xdpsq *sq)
1487 {
1488         struct mlx5e_channel *c = sq->channel;
1489
1490         clear_bit(MLX5E_SQ_STATE_ENABLED, &sq->state);
1491         napi_synchronize(&c->napi);
1492
1493         mlx5e_destroy_sq(c->mdev, sq->sqn);
1494         mlx5e_free_xdpsq_descs(sq);
1495         mlx5e_free_xdpsq(sq);
1496 }
1497
1498 static int mlx5e_alloc_cq_common(struct mlx5_core_dev *mdev,
1499                                  struct mlx5e_cq_param *param,
1500                                  struct mlx5e_cq *cq)
1501 {
1502         struct mlx5_core_cq *mcq = &cq->mcq;
1503         int eqn_not_used;
1504         unsigned int irqn;
1505         int err;
1506         u32 i;
1507
1508         err = mlx5_vector2eqn(mdev, param->eq_ix, &eqn_not_used, &irqn);
1509         if (err)
1510                 return err;
1511
1512         err = mlx5_cqwq_create(mdev, &param->wq, param->cqc, &cq->wq,
1513                                &cq->wq_ctrl);
1514         if (err)
1515                 return err;
1516
1517         mcq->cqe_sz     = 64;
1518         mcq->set_ci_db  = cq->wq_ctrl.db.db;
1519         mcq->arm_db     = cq->wq_ctrl.db.db + 1;
1520         *mcq->set_ci_db = 0;
1521         *mcq->arm_db    = 0;
1522         mcq->vector     = param->eq_ix;
1523         mcq->comp       = mlx5e_completion_event;
1524         mcq->event      = mlx5e_cq_error_event;
1525         mcq->irqn       = irqn;
1526
1527         for (i = 0; i < mlx5_cqwq_get_size(&cq->wq); i++) {
1528                 struct mlx5_cqe64 *cqe = mlx5_cqwq_get_wqe(&cq->wq, i);
1529
1530                 cqe->op_own = 0xf1;
1531         }
1532
1533         cq->mdev = mdev;
1534
1535         return 0;
1536 }
1537
1538 static int mlx5e_alloc_cq(struct mlx5e_channel *c,
1539                           struct mlx5e_cq_param *param,
1540                           struct mlx5e_cq *cq)
1541 {
1542         struct mlx5_core_dev *mdev = c->priv->mdev;
1543         int err;
1544
1545         param->wq.buf_numa_node = cpu_to_node(c->cpu);
1546         param->wq.db_numa_node  = cpu_to_node(c->cpu);
1547         param->eq_ix   = c->ix;
1548
1549         err = mlx5e_alloc_cq_common(mdev, param, cq);
1550
1551         cq->napi    = &c->napi;
1552         cq->channel = c;
1553
1554         return err;
1555 }
1556
1557 static void mlx5e_free_cq(struct mlx5e_cq *cq)
1558 {
1559         mlx5_wq_destroy(&cq->wq_ctrl);
1560 }
1561
1562 static int mlx5e_create_cq(struct mlx5e_cq *cq, struct mlx5e_cq_param *param)
1563 {
1564         u32 out[MLX5_ST_SZ_DW(create_cq_out)];
1565         struct mlx5_core_dev *mdev = cq->mdev;
1566         struct mlx5_core_cq *mcq = &cq->mcq;
1567
1568         void *in;
1569         void *cqc;
1570         int inlen;
1571         unsigned int irqn_not_used;
1572         int eqn;
1573         int err;
1574
1575         err = mlx5_vector2eqn(mdev, param->eq_ix, &eqn, &irqn_not_used);
1576         if (err)
1577                 return err;
1578
1579         inlen = MLX5_ST_SZ_BYTES(create_cq_in) +
1580                 sizeof(u64) * cq->wq_ctrl.buf.npages;
1581         in = kvzalloc(inlen, GFP_KERNEL);
1582         if (!in)
1583                 return -ENOMEM;
1584
1585         cqc = MLX5_ADDR_OF(create_cq_in, in, cq_context);
1586
1587         memcpy(cqc, param->cqc, sizeof(param->cqc));
1588
1589         mlx5_fill_page_frag_array(&cq->wq_ctrl.buf,
1590                                   (__be64 *)MLX5_ADDR_OF(create_cq_in, in, pas));
1591
1592         MLX5_SET(cqc,   cqc, cq_period_mode, param->cq_period_mode);
1593         MLX5_SET(cqc,   cqc, c_eqn,         eqn);
1594         MLX5_SET(cqc,   cqc, uar_page,      mdev->priv.uar->index);
1595         MLX5_SET(cqc,   cqc, log_page_size, cq->wq_ctrl.buf.page_shift -
1596                                             MLX5_ADAPTER_PAGE_SHIFT);
1597         MLX5_SET64(cqc, cqc, dbr_addr,      cq->wq_ctrl.db.dma);
1598
1599         err = mlx5_core_create_cq(mdev, mcq, in, inlen, out, sizeof(out));
1600
1601         kvfree(in);
1602
1603         if (err)
1604                 return err;
1605
1606         mlx5e_cq_arm(cq);
1607
1608         return 0;
1609 }
1610
1611 static void mlx5e_destroy_cq(struct mlx5e_cq *cq)
1612 {
1613         mlx5_core_destroy_cq(cq->mdev, &cq->mcq);
1614 }
1615
1616 int mlx5e_open_cq(struct mlx5e_channel *c, struct dim_cq_moder moder,
1617                   struct mlx5e_cq_param *param, struct mlx5e_cq *cq)
1618 {
1619         struct mlx5_core_dev *mdev = c->mdev;
1620         int err;
1621
1622         err = mlx5e_alloc_cq(c, param, cq);
1623         if (err)
1624                 return err;
1625
1626         err = mlx5e_create_cq(cq, param);
1627         if (err)
1628                 goto err_free_cq;
1629
1630         if (MLX5_CAP_GEN(mdev, cq_moderation))
1631                 mlx5_core_modify_cq_moderation(mdev, &cq->mcq, moder.usec, moder.pkts);
1632         return 0;
1633
1634 err_free_cq:
1635         mlx5e_free_cq(cq);
1636
1637         return err;
1638 }
1639
1640 void mlx5e_close_cq(struct mlx5e_cq *cq)
1641 {
1642         mlx5e_destroy_cq(cq);
1643         mlx5e_free_cq(cq);
1644 }
1645
1646 static int mlx5e_open_tx_cqs(struct mlx5e_channel *c,
1647                              struct mlx5e_params *params,
1648                              struct mlx5e_channel_param *cparam)
1649 {
1650         int err;
1651         int tc;
1652
1653         for (tc = 0; tc < c->num_tc; tc++) {
1654                 err = mlx5e_open_cq(c, params->tx_cq_moderation,
1655                                     &cparam->tx_cq, &c->sq[tc].cq);
1656                 if (err)
1657                         goto err_close_tx_cqs;
1658         }
1659
1660         return 0;
1661
1662 err_close_tx_cqs:
1663         for (tc--; tc >= 0; tc--)
1664                 mlx5e_close_cq(&c->sq[tc].cq);
1665
1666         return err;
1667 }
1668
1669 static void mlx5e_close_tx_cqs(struct mlx5e_channel *c)
1670 {
1671         int tc;
1672
1673         for (tc = 0; tc < c->num_tc; tc++)
1674                 mlx5e_close_cq(&c->sq[tc].cq);
1675 }
1676
1677 static int mlx5e_open_sqs(struct mlx5e_channel *c,
1678                           struct mlx5e_params *params,
1679                           struct mlx5e_channel_param *cparam)
1680 {
1681         struct mlx5e_priv *priv = c->priv;
1682         int err, tc, max_nch = mlx5e_get_netdev_max_channels(priv->netdev);
1683
1684         for (tc = 0; tc < params->num_tc; tc++) {
1685                 int txq_ix = c->ix + tc * max_nch;
1686
1687                 err = mlx5e_open_txqsq(c, c->priv->tisn[tc], txq_ix,
1688                                        params, &cparam->sq, &c->sq[tc], tc);
1689                 if (err)
1690                         goto err_close_sqs;
1691         }
1692
1693         return 0;
1694
1695 err_close_sqs:
1696         for (tc--; tc >= 0; tc--)
1697                 mlx5e_close_txqsq(&c->sq[tc]);
1698
1699         return err;
1700 }
1701
1702 static void mlx5e_close_sqs(struct mlx5e_channel *c)
1703 {
1704         int tc;
1705
1706         for (tc = 0; tc < c->num_tc; tc++)
1707                 mlx5e_close_txqsq(&c->sq[tc]);
1708 }
1709
1710 static int mlx5e_set_sq_maxrate(struct net_device *dev,
1711                                 struct mlx5e_txqsq *sq, u32 rate)
1712 {
1713         struct mlx5e_priv *priv = netdev_priv(dev);
1714         struct mlx5_core_dev *mdev = priv->mdev;
1715         struct mlx5e_modify_sq_param msp = {0};
1716         struct mlx5_rate_limit rl = {0};
1717         u16 rl_index = 0;
1718         int err;
1719
1720         if (rate == sq->rate_limit)
1721                 /* nothing to do */
1722                 return 0;
1723
1724         if (sq->rate_limit) {
1725                 rl.rate = sq->rate_limit;
1726                 /* remove current rl index to free space to next ones */
1727                 mlx5_rl_remove_rate(mdev, &rl);
1728         }
1729
1730         sq->rate_limit = 0;
1731
1732         if (rate) {
1733                 rl.rate = rate;
1734                 err = mlx5_rl_add_rate(mdev, &rl_index, &rl);
1735                 if (err) {
1736                         netdev_err(dev, "Failed configuring rate %u: %d\n",
1737                                    rate, err);
1738                         return err;
1739                 }
1740         }
1741
1742         msp.curr_state = MLX5_SQC_STATE_RDY;
1743         msp.next_state = MLX5_SQC_STATE_RDY;
1744         msp.rl_index   = rl_index;
1745         msp.rl_update  = true;
1746         err = mlx5e_modify_sq(mdev, sq->sqn, &msp);
1747         if (err) {
1748                 netdev_err(dev, "Failed configuring rate %u: %d\n",
1749                            rate, err);
1750                 /* remove the rate from the table */
1751                 if (rate)
1752                         mlx5_rl_remove_rate(mdev, &rl);
1753                 return err;
1754         }
1755
1756         sq->rate_limit = rate;
1757         return 0;
1758 }
1759
1760 static int mlx5e_set_tx_maxrate(struct net_device *dev, int index, u32 rate)
1761 {
1762         struct mlx5e_priv *priv = netdev_priv(dev);
1763         struct mlx5_core_dev *mdev = priv->mdev;
1764         struct mlx5e_txqsq *sq = priv->txq2sq[index];
1765         int err = 0;
1766
1767         if (!mlx5_rl_is_supported(mdev)) {
1768                 netdev_err(dev, "Rate limiting is not supported on this device\n");
1769                 return -EINVAL;
1770         }
1771
1772         /* rate is given in Mb/sec, HW config is in Kb/sec */
1773         rate = rate << 10;
1774
1775         /* Check whether rate in valid range, 0 is always valid */
1776         if (rate && !mlx5_rl_is_in_range(mdev, rate)) {
1777                 netdev_err(dev, "TX rate %u, is not in range\n", rate);
1778                 return -ERANGE;
1779         }
1780
1781         mutex_lock(&priv->state_lock);
1782         if (test_bit(MLX5E_STATE_OPENED, &priv->state))
1783                 err = mlx5e_set_sq_maxrate(dev, sq, rate);
1784         if (!err)
1785                 priv->tx_rates[index] = rate;
1786         mutex_unlock(&priv->state_lock);
1787
1788         return err;
1789 }
1790
1791 static int mlx5e_alloc_xps_cpumask(struct mlx5e_channel *c,
1792                                    struct mlx5e_params *params)
1793 {
1794         int num_comp_vectors = mlx5_comp_vectors_count(c->mdev);
1795         int irq;
1796
1797         if (!zalloc_cpumask_var(&c->xps_cpumask, GFP_KERNEL))
1798                 return -ENOMEM;
1799
1800         for (irq = c->ix; irq < num_comp_vectors; irq += params->num_channels) {
1801                 int cpu = cpumask_first(mlx5_comp_irq_get_affinity_mask(c->mdev, irq));
1802
1803                 cpumask_set_cpu(cpu, c->xps_cpumask);
1804         }
1805
1806         return 0;
1807 }
1808
1809 static void mlx5e_free_xps_cpumask(struct mlx5e_channel *c)
1810 {
1811         free_cpumask_var(c->xps_cpumask);
1812 }
1813
1814 static int mlx5e_open_queues(struct mlx5e_channel *c,
1815                              struct mlx5e_params *params,
1816                              struct mlx5e_channel_param *cparam)
1817 {
1818         struct dim_cq_moder icocq_moder = {0, 0};
1819         int err;
1820
1821         err = mlx5e_open_cq(c, icocq_moder, &cparam->icosq_cq, &c->icosq.cq);
1822         if (err)
1823                 return err;
1824
1825         err = mlx5e_open_tx_cqs(c, params, cparam);
1826         if (err)
1827                 goto err_close_icosq_cq;
1828
1829         err = mlx5e_open_cq(c, params->tx_cq_moderation, &cparam->tx_cq, &c->xdpsq.cq);
1830         if (err)
1831                 goto err_close_tx_cqs;
1832
1833         err = mlx5e_open_cq(c, params->rx_cq_moderation, &cparam->rx_cq, &c->rq.cq);
1834         if (err)
1835                 goto err_close_xdp_tx_cqs;
1836
1837         /* XDP SQ CQ params are same as normal TXQ sq CQ params */
1838         err = c->xdp ? mlx5e_open_cq(c, params->tx_cq_moderation,
1839                                      &cparam->tx_cq, &c->rq_xdpsq.cq) : 0;
1840         if (err)
1841                 goto err_close_rx_cq;
1842
1843         napi_enable(&c->napi);
1844
1845         err = mlx5e_open_icosq(c, params, &cparam->icosq, &c->icosq);
1846         if (err)
1847                 goto err_disable_napi;
1848
1849         err = mlx5e_open_sqs(c, params, cparam);
1850         if (err)
1851                 goto err_close_icosq;
1852
1853         if (c->xdp) {
1854                 err = mlx5e_open_xdpsq(c, params, &cparam->xdp_sq, NULL,
1855                                        &c->rq_xdpsq, false);
1856                 if (err)
1857                         goto err_close_sqs;
1858         }
1859
1860         err = mlx5e_open_rq(c, params, &cparam->rq, NULL, NULL, &c->rq);
1861         if (err)
1862                 goto err_close_xdp_sq;
1863
1864         err = mlx5e_open_xdpsq(c, params, &cparam->xdp_sq, NULL, &c->xdpsq, true);
1865         if (err)
1866                 goto err_close_rq;
1867
1868         return 0;
1869
1870 err_close_rq:
1871         mlx5e_close_rq(&c->rq);
1872
1873 err_close_xdp_sq:
1874         if (c->xdp)
1875                 mlx5e_close_xdpsq(&c->rq_xdpsq);
1876
1877 err_close_sqs:
1878         mlx5e_close_sqs(c);
1879
1880 err_close_icosq:
1881         mlx5e_close_icosq(&c->icosq);
1882
1883 err_disable_napi:
1884         napi_disable(&c->napi);
1885
1886         if (c->xdp)
1887                 mlx5e_close_cq(&c->rq_xdpsq.cq);
1888
1889 err_close_rx_cq:
1890         mlx5e_close_cq(&c->rq.cq);
1891
1892 err_close_xdp_tx_cqs:
1893         mlx5e_close_cq(&c->xdpsq.cq);
1894
1895 err_close_tx_cqs:
1896         mlx5e_close_tx_cqs(c);
1897
1898 err_close_icosq_cq:
1899         mlx5e_close_cq(&c->icosq.cq);
1900
1901         return err;
1902 }
1903
1904 static void mlx5e_close_queues(struct mlx5e_channel *c)
1905 {
1906         mlx5e_close_xdpsq(&c->xdpsq);
1907         mlx5e_close_rq(&c->rq);
1908         if (c->xdp)
1909                 mlx5e_close_xdpsq(&c->rq_xdpsq);
1910         mlx5e_close_sqs(c);
1911         mlx5e_close_icosq(&c->icosq);
1912         napi_disable(&c->napi);
1913         if (c->xdp)
1914                 mlx5e_close_cq(&c->rq_xdpsq.cq);
1915         mlx5e_close_cq(&c->rq.cq);
1916         mlx5e_close_cq(&c->xdpsq.cq);
1917         mlx5e_close_tx_cqs(c);
1918         mlx5e_close_cq(&c->icosq.cq);
1919 }
1920
1921 static int mlx5e_open_channel(struct mlx5e_priv *priv, int ix,
1922                               struct mlx5e_params *params,
1923                               struct mlx5e_channel_param *cparam,
1924                               struct xdp_umem *umem,
1925                               struct mlx5e_channel **cp)
1926 {
1927         int cpu = cpumask_first(mlx5_comp_irq_get_affinity_mask(priv->mdev, ix));
1928         struct net_device *netdev = priv->netdev;
1929         struct mlx5e_xsk_param xsk;
1930         struct mlx5e_channel *c;
1931         unsigned int irq;
1932         int err;
1933         int eqn;
1934
1935         err = mlx5_vector2eqn(priv->mdev, ix, &eqn, &irq);
1936         if (err)
1937                 return err;
1938
1939         c = kvzalloc_node(sizeof(*c), GFP_KERNEL, cpu_to_node(cpu));
1940         if (!c)
1941                 return -ENOMEM;
1942
1943         c->priv     = priv;
1944         c->mdev     = priv->mdev;
1945         c->tstamp   = &priv->tstamp;
1946         c->ix       = ix;
1947         c->cpu      = cpu;
1948         c->pdev     = priv->mdev->device;
1949         c->netdev   = priv->netdev;
1950         c->mkey_be  = cpu_to_be32(priv->mdev->mlx5e_res.mkey.key);
1951         c->num_tc   = params->num_tc;
1952         c->xdp      = !!params->xdp_prog;
1953         c->stats    = &priv->channel_stats[ix].ch;
1954         c->irq_desc = irq_to_desc(irq);
1955
1956         err = mlx5e_alloc_xps_cpumask(c, params);
1957         if (err)
1958                 goto err_free_channel;
1959
1960         netif_napi_add(netdev, &c->napi, mlx5e_napi_poll, 64);
1961
1962         err = mlx5e_open_queues(c, params, cparam);
1963         if (unlikely(err))
1964                 goto err_napi_del;
1965
1966         if (umem) {
1967                 mlx5e_build_xsk_param(umem, &xsk);
1968                 err = mlx5e_open_xsk(priv, params, &xsk, umem, c);
1969                 if (unlikely(err))
1970                         goto err_close_queues;
1971         }
1972
1973         *cp = c;
1974
1975         return 0;
1976
1977 err_close_queues:
1978         mlx5e_close_queues(c);
1979
1980 err_napi_del:
1981         netif_napi_del(&c->napi);
1982         mlx5e_free_xps_cpumask(c);
1983
1984 err_free_channel:
1985         kvfree(c);
1986
1987         return err;
1988 }
1989
1990 static void mlx5e_activate_channel(struct mlx5e_channel *c)
1991 {
1992         int tc;
1993
1994         for (tc = 0; tc < c->num_tc; tc++)
1995                 mlx5e_activate_txqsq(&c->sq[tc]);
1996         mlx5e_activate_rq(&c->rq);
1997         netif_set_xps_queue(c->netdev, c->xps_cpumask, c->ix);
1998
1999         if (test_bit(MLX5E_CHANNEL_STATE_XSK, c->state))
2000                 mlx5e_activate_xsk(c);
2001 }
2002
2003 static void mlx5e_deactivate_channel(struct mlx5e_channel *c)
2004 {
2005         int tc;
2006
2007         if (test_bit(MLX5E_CHANNEL_STATE_XSK, c->state))
2008                 mlx5e_deactivate_xsk(c);
2009
2010         mlx5e_deactivate_rq(&c->rq);
2011         for (tc = 0; tc < c->num_tc; tc++)
2012                 mlx5e_deactivate_txqsq(&c->sq[tc]);
2013 }
2014
2015 static void mlx5e_close_channel(struct mlx5e_channel *c)
2016 {
2017         if (test_bit(MLX5E_CHANNEL_STATE_XSK, c->state))
2018                 mlx5e_close_xsk(c);
2019         mlx5e_close_queues(c);
2020         netif_napi_del(&c->napi);
2021         mlx5e_free_xps_cpumask(c);
2022
2023         kvfree(c);
2024 }
2025
2026 #define DEFAULT_FRAG_SIZE (2048)
2027
2028 static void mlx5e_build_rq_frags_info(struct mlx5_core_dev *mdev,
2029                                       struct mlx5e_params *params,
2030                                       struct mlx5e_xsk_param *xsk,
2031                                       struct mlx5e_rq_frags_info *info)
2032 {
2033         u32 byte_count = MLX5E_SW2HW_MTU(params, params->sw_mtu);
2034         int frag_size_max = DEFAULT_FRAG_SIZE;
2035         u32 buf_size = 0;
2036         int i;
2037
2038 #ifdef CONFIG_MLX5_EN_IPSEC
2039         if (MLX5_IPSEC_DEV(mdev))
2040                 byte_count += MLX5E_METADATA_ETHER_LEN;
2041 #endif
2042
2043         if (mlx5e_rx_is_linear_skb(params, xsk)) {
2044                 int frag_stride;
2045
2046                 frag_stride = mlx5e_rx_get_linear_frag_sz(params, xsk);
2047                 frag_stride = roundup_pow_of_two(frag_stride);
2048
2049                 info->arr[0].frag_size = byte_count;
2050                 info->arr[0].frag_stride = frag_stride;
2051                 info->num_frags = 1;
2052                 info->wqe_bulk = PAGE_SIZE / frag_stride;
2053                 goto out;
2054         }
2055
2056         if (byte_count > PAGE_SIZE +
2057             (MLX5E_MAX_RX_FRAGS - 1) * frag_size_max)
2058                 frag_size_max = PAGE_SIZE;
2059
2060         i = 0;
2061         while (buf_size < byte_count) {
2062                 int frag_size = byte_count - buf_size;
2063
2064                 if (i < MLX5E_MAX_RX_FRAGS - 1)
2065                         frag_size = min(frag_size, frag_size_max);
2066
2067                 info->arr[i].frag_size = frag_size;
2068                 info->arr[i].frag_stride = roundup_pow_of_two(frag_size);
2069
2070                 buf_size += frag_size;
2071                 i++;
2072         }
2073         info->num_frags = i;
2074         /* number of different wqes sharing a page */
2075         info->wqe_bulk = 1 + (info->num_frags % 2);
2076
2077 out:
2078         info->wqe_bulk = max_t(u8, info->wqe_bulk, 8);
2079         info->log_num_frags = order_base_2(info->num_frags);
2080 }
2081
2082 static inline u8 mlx5e_get_rqwq_log_stride(u8 wq_type, int ndsegs)
2083 {
2084         int sz = sizeof(struct mlx5_wqe_data_seg) * ndsegs;
2085
2086         switch (wq_type) {
2087         case MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ:
2088                 sz += sizeof(struct mlx5e_rx_wqe_ll);
2089                 break;
2090         default: /* MLX5_WQ_TYPE_CYCLIC */
2091                 sz += sizeof(struct mlx5e_rx_wqe_cyc);
2092         }
2093
2094         return order_base_2(sz);
2095 }
2096
2097 static u8 mlx5e_get_rq_log_wq_sz(void *rqc)
2098 {
2099         void *wq = MLX5_ADDR_OF(rqc, rqc, wq);
2100
2101         return MLX5_GET(wq, wq, log_wq_sz);
2102 }
2103
2104 void mlx5e_build_rq_param(struct mlx5e_priv *priv,
2105                           struct mlx5e_params *params,
2106                           struct mlx5e_xsk_param *xsk,
2107                           struct mlx5e_rq_param *param)
2108 {
2109         struct mlx5_core_dev *mdev = priv->mdev;
2110         void *rqc = param->rqc;
2111         void *wq = MLX5_ADDR_OF(rqc, rqc, wq);
2112         int ndsegs = 1;
2113
2114         switch (params->rq_wq_type) {
2115         case MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ:
2116                 MLX5_SET(wq, wq, log_wqe_num_of_strides,
2117                          mlx5e_mpwqe_get_log_num_strides(mdev, params, xsk) -
2118                          MLX5_MPWQE_LOG_NUM_STRIDES_BASE);
2119                 MLX5_SET(wq, wq, log_wqe_stride_size,
2120                          mlx5e_mpwqe_get_log_stride_size(mdev, params, xsk) -
2121                          MLX5_MPWQE_LOG_STRIDE_SZ_BASE);
2122                 MLX5_SET(wq, wq, log_wq_sz, mlx5e_mpwqe_get_log_rq_size(params, xsk));
2123                 break;
2124         default: /* MLX5_WQ_TYPE_CYCLIC */
2125                 MLX5_SET(wq, wq, log_wq_sz, params->log_rq_mtu_frames);
2126                 mlx5e_build_rq_frags_info(mdev, params, xsk, &param->frags_info);
2127                 ndsegs = param->frags_info.num_frags;
2128         }
2129
2130         MLX5_SET(wq, wq, wq_type,          params->rq_wq_type);
2131         MLX5_SET(wq, wq, end_padding_mode, MLX5_WQ_END_PAD_MODE_ALIGN);
2132         MLX5_SET(wq, wq, log_wq_stride,
2133                  mlx5e_get_rqwq_log_stride(params->rq_wq_type, ndsegs));
2134         MLX5_SET(wq, wq, pd,               mdev->mlx5e_res.pdn);
2135         MLX5_SET(rqc, rqc, counter_set_id, priv->q_counter);
2136         MLX5_SET(rqc, rqc, vsd,            params->vlan_strip_disable);
2137         MLX5_SET(rqc, rqc, scatter_fcs,    params->scatter_fcs_en);
2138
2139         param->wq.buf_numa_node = dev_to_node(mdev->device);
2140 }
2141
2142 static void mlx5e_build_drop_rq_param(struct mlx5e_priv *priv,
2143                                       struct mlx5e_rq_param *param)
2144 {
2145         struct mlx5_core_dev *mdev = priv->mdev;
2146         void *rqc = param->rqc;
2147         void *wq = MLX5_ADDR_OF(rqc, rqc, wq);
2148
2149         MLX5_SET(wq, wq, wq_type, MLX5_WQ_TYPE_CYCLIC);
2150         MLX5_SET(wq, wq, log_wq_stride,
2151                  mlx5e_get_rqwq_log_stride(MLX5_WQ_TYPE_CYCLIC, 1));
2152         MLX5_SET(rqc, rqc, counter_set_id, priv->drop_rq_q_counter);
2153
2154         param->wq.buf_numa_node = dev_to_node(mdev->device);
2155 }
2156
2157 void mlx5e_build_sq_param_common(struct mlx5e_priv *priv,
2158                                  struct mlx5e_sq_param *param)
2159 {
2160         void *sqc = param->sqc;
2161         void *wq = MLX5_ADDR_OF(sqc, sqc, wq);
2162
2163         MLX5_SET(wq, wq, log_wq_stride, ilog2(MLX5_SEND_WQE_BB));
2164         MLX5_SET(wq, wq, pd,            priv->mdev->mlx5e_res.pdn);
2165
2166         param->wq.buf_numa_node = dev_to_node(priv->mdev->device);
2167 }
2168
2169 static void mlx5e_build_sq_param(struct mlx5e_priv *priv,
2170                                  struct mlx5e_params *params,
2171                                  struct mlx5e_sq_param *param)
2172 {
2173         void *sqc = param->sqc;
2174         void *wq = MLX5_ADDR_OF(sqc, sqc, wq);
2175         bool allow_swp;
2176
2177         allow_swp = mlx5_geneve_tx_allowed(priv->mdev) ||
2178                     !!MLX5_IPSEC_DEV(priv->mdev);
2179         mlx5e_build_sq_param_common(priv, param);
2180         MLX5_SET(wq, wq, log_wq_sz, params->log_sq_size);
2181         MLX5_SET(sqc, sqc, allow_swp, allow_swp);
2182 }
2183
2184 static void mlx5e_build_common_cq_param(struct mlx5e_priv *priv,
2185                                         struct mlx5e_cq_param *param)
2186 {
2187         void *cqc = param->cqc;
2188
2189         MLX5_SET(cqc, cqc, uar_page, priv->mdev->priv.uar->index);
2190         if (MLX5_CAP_GEN(priv->mdev, cqe_128_always) && cache_line_size() >= 128)
2191                 MLX5_SET(cqc, cqc, cqe_sz, CQE_STRIDE_128_PAD);
2192 }
2193
2194 void mlx5e_build_rx_cq_param(struct mlx5e_priv *priv,
2195                              struct mlx5e_params *params,
2196                              struct mlx5e_xsk_param *xsk,
2197                              struct mlx5e_cq_param *param)
2198 {
2199         struct mlx5_core_dev *mdev = priv->mdev;
2200         void *cqc = param->cqc;
2201         u8 log_cq_size;
2202
2203         switch (params->rq_wq_type) {
2204         case MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ:
2205                 log_cq_size = mlx5e_mpwqe_get_log_rq_size(params, xsk) +
2206                         mlx5e_mpwqe_get_log_num_strides(mdev, params, xsk);
2207                 break;
2208         default: /* MLX5_WQ_TYPE_CYCLIC */
2209                 log_cq_size = params->log_rq_mtu_frames;
2210         }
2211
2212         MLX5_SET(cqc, cqc, log_cq_size, log_cq_size);
2213         if (MLX5E_GET_PFLAG(params, MLX5E_PFLAG_RX_CQE_COMPRESS)) {
2214                 MLX5_SET(cqc, cqc, mini_cqe_res_format, MLX5_CQE_FORMAT_CSUM);
2215                 MLX5_SET(cqc, cqc, cqe_comp_en, 1);
2216         }
2217
2218         mlx5e_build_common_cq_param(priv, param);
2219         param->cq_period_mode = params->rx_cq_moderation.cq_period_mode;
2220 }
2221
2222 void mlx5e_build_tx_cq_param(struct mlx5e_priv *priv,
2223                              struct mlx5e_params *params,
2224                              struct mlx5e_cq_param *param)
2225 {
2226         void *cqc = param->cqc;
2227
2228         MLX5_SET(cqc, cqc, log_cq_size, params->log_sq_size);
2229
2230         mlx5e_build_common_cq_param(priv, param);
2231         param->cq_period_mode = params->tx_cq_moderation.cq_period_mode;
2232 }
2233
2234 void mlx5e_build_ico_cq_param(struct mlx5e_priv *priv,
2235                               u8 log_wq_size,
2236                               struct mlx5e_cq_param *param)
2237 {
2238         void *cqc = param->cqc;
2239
2240         MLX5_SET(cqc, cqc, log_cq_size, log_wq_size);
2241
2242         mlx5e_build_common_cq_param(priv, param);
2243
2244         param->cq_period_mode = DIM_CQ_PERIOD_MODE_START_FROM_EQE;
2245 }
2246
2247 void mlx5e_build_icosq_param(struct mlx5e_priv *priv,
2248                              u8 log_wq_size,
2249                              struct mlx5e_sq_param *param)
2250 {
2251         void *sqc = param->sqc;
2252         void *wq = MLX5_ADDR_OF(sqc, sqc, wq);
2253
2254         mlx5e_build_sq_param_common(priv, param);
2255
2256         MLX5_SET(wq, wq, log_wq_sz, log_wq_size);
2257         MLX5_SET(sqc, sqc, reg_umr, MLX5_CAP_ETH(priv->mdev, reg_umr_sq));
2258 }
2259
2260 void mlx5e_build_xdpsq_param(struct mlx5e_priv *priv,
2261                              struct mlx5e_params *params,
2262                              struct mlx5e_sq_param *param)
2263 {
2264         void *sqc = param->sqc;
2265         void *wq = MLX5_ADDR_OF(sqc, sqc, wq);
2266
2267         mlx5e_build_sq_param_common(priv, param);
2268         MLX5_SET(wq, wq, log_wq_sz, params->log_sq_size);
2269         param->is_mpw = MLX5E_GET_PFLAG(params, MLX5E_PFLAG_XDP_TX_MPWQE);
2270 }
2271
2272 static u8 mlx5e_build_icosq_log_wq_sz(struct mlx5e_params *params,
2273                                       struct mlx5e_rq_param *rqp)
2274 {
2275         switch (params->rq_wq_type) {
2276         case MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ:
2277                 return order_base_2(MLX5E_UMR_WQEBBS) +
2278                         mlx5e_get_rq_log_wq_sz(rqp->rqc);
2279         default: /* MLX5_WQ_TYPE_CYCLIC */
2280                 return MLX5E_PARAMS_MINIMUM_LOG_SQ_SIZE;
2281         }
2282 }
2283
2284 static void mlx5e_build_channel_param(struct mlx5e_priv *priv,
2285                                       struct mlx5e_params *params,
2286                                       struct mlx5e_channel_param *cparam)
2287 {
2288         u8 icosq_log_wq_sz;
2289
2290         mlx5e_build_rq_param(priv, params, NULL, &cparam->rq);
2291
2292         icosq_log_wq_sz = mlx5e_build_icosq_log_wq_sz(params, &cparam->rq);
2293
2294         mlx5e_build_sq_param(priv, params, &cparam->sq);
2295         mlx5e_build_xdpsq_param(priv, params, &cparam->xdp_sq);
2296         mlx5e_build_icosq_param(priv, icosq_log_wq_sz, &cparam->icosq);
2297         mlx5e_build_rx_cq_param(priv, params, NULL, &cparam->rx_cq);
2298         mlx5e_build_tx_cq_param(priv, params, &cparam->tx_cq);
2299         mlx5e_build_ico_cq_param(priv, icosq_log_wq_sz, &cparam->icosq_cq);
2300 }
2301
2302 int mlx5e_open_channels(struct mlx5e_priv *priv,
2303                         struct mlx5e_channels *chs)
2304 {
2305         struct mlx5e_channel_param *cparam;
2306         int err = -ENOMEM;
2307         int i;
2308
2309         chs->num = chs->params.num_channels;
2310
2311         chs->c = kcalloc(chs->num, sizeof(struct mlx5e_channel *), GFP_KERNEL);
2312         cparam = kvzalloc(sizeof(struct mlx5e_channel_param), GFP_KERNEL);
2313         if (!chs->c || !cparam)
2314                 goto err_free;
2315
2316         mlx5e_build_channel_param(priv, &chs->params, cparam);
2317         for (i = 0; i < chs->num; i++) {
2318                 struct xdp_umem *umem = NULL;
2319
2320                 if (chs->params.xdp_prog)
2321                         umem = mlx5e_xsk_get_umem(&chs->params, chs->params.xsk, i);
2322
2323                 err = mlx5e_open_channel(priv, i, &chs->params, cparam, umem, &chs->c[i]);
2324                 if (err)
2325                         goto err_close_channels;
2326         }
2327
2328         if (!IS_ERR_OR_NULL(priv->tx_reporter))
2329                 devlink_health_reporter_state_update(priv->tx_reporter,
2330                                                      DEVLINK_HEALTH_REPORTER_STATE_HEALTHY);
2331
2332         kvfree(cparam);
2333         return 0;
2334
2335 err_close_channels:
2336         for (i--; i >= 0; i--)
2337                 mlx5e_close_channel(chs->c[i]);
2338
2339 err_free:
2340         kfree(chs->c);
2341         kvfree(cparam);
2342         chs->num = 0;
2343         return err;
2344 }
2345
2346 static void mlx5e_activate_channels(struct mlx5e_channels *chs)
2347 {
2348         int i;
2349
2350         for (i = 0; i < chs->num; i++)
2351                 mlx5e_activate_channel(chs->c[i]);
2352 }
2353
2354 #define MLX5E_RQ_WQES_TIMEOUT 20000 /* msecs */
2355
2356 static int mlx5e_wait_channels_min_rx_wqes(struct mlx5e_channels *chs)
2357 {
2358         int err = 0;
2359         int i;
2360
2361         for (i = 0; i < chs->num; i++) {
2362                 int timeout = err ? 0 : MLX5E_RQ_WQES_TIMEOUT;
2363
2364                 err |= mlx5e_wait_for_min_rx_wqes(&chs->c[i]->rq, timeout);
2365
2366                 /* Don't wait on the XSK RQ, because the newer xdpsock sample
2367                  * doesn't provide any Fill Ring entries at the setup stage.
2368                  */
2369         }
2370
2371         return err ? -ETIMEDOUT : 0;
2372 }
2373
2374 static void mlx5e_deactivate_channels(struct mlx5e_channels *chs)
2375 {
2376         int i;
2377
2378         for (i = 0; i < chs->num; i++)
2379                 mlx5e_deactivate_channel(chs->c[i]);
2380 }
2381
2382 void mlx5e_close_channels(struct mlx5e_channels *chs)
2383 {
2384         int i;
2385
2386         for (i = 0; i < chs->num; i++)
2387                 mlx5e_close_channel(chs->c[i]);
2388
2389         kfree(chs->c);
2390         chs->num = 0;
2391 }
2392
2393 static int
2394 mlx5e_create_rqt(struct mlx5e_priv *priv, int sz, struct mlx5e_rqt *rqt)
2395 {
2396         struct mlx5_core_dev *mdev = priv->mdev;
2397         void *rqtc;
2398         int inlen;
2399         int err;
2400         u32 *in;
2401         int i;
2402
2403         inlen = MLX5_ST_SZ_BYTES(create_rqt_in) + sizeof(u32) * sz;
2404         in = kvzalloc(inlen, GFP_KERNEL);
2405         if (!in)
2406                 return -ENOMEM;
2407
2408         rqtc = MLX5_ADDR_OF(create_rqt_in, in, rqt_context);
2409
2410         MLX5_SET(rqtc, rqtc, rqt_actual_size, sz);
2411         MLX5_SET(rqtc, rqtc, rqt_max_size, sz);
2412
2413         for (i = 0; i < sz; i++)
2414                 MLX5_SET(rqtc, rqtc, rq_num[i], priv->drop_rq.rqn);
2415
2416         err = mlx5_core_create_rqt(mdev, in, inlen, &rqt->rqtn);
2417         if (!err)
2418                 rqt->enabled = true;
2419
2420         kvfree(in);
2421         return err;
2422 }
2423
2424 void mlx5e_destroy_rqt(struct mlx5e_priv *priv, struct mlx5e_rqt *rqt)
2425 {
2426         rqt->enabled = false;
2427         mlx5_core_destroy_rqt(priv->mdev, rqt->rqtn);
2428 }
2429
2430 int mlx5e_create_indirect_rqt(struct mlx5e_priv *priv)
2431 {
2432         struct mlx5e_rqt *rqt = &priv->indir_rqt;
2433         int err;
2434
2435         err = mlx5e_create_rqt(priv, MLX5E_INDIR_RQT_SIZE, rqt);
2436         if (err)
2437                 mlx5_core_warn(priv->mdev, "create indirect rqts failed, %d\n", err);
2438         return err;
2439 }
2440
2441 int mlx5e_create_direct_rqts(struct mlx5e_priv *priv, struct mlx5e_tir *tirs)
2442 {
2443         const int max_nch = mlx5e_get_netdev_max_channels(priv->netdev);
2444         int err;
2445         int ix;
2446
2447         for (ix = 0; ix < max_nch; ix++) {
2448                 err = mlx5e_create_rqt(priv, 1 /*size */, &tirs[ix].rqt);
2449                 if (unlikely(err))
2450                         goto err_destroy_rqts;
2451         }
2452
2453         return 0;
2454
2455 err_destroy_rqts:
2456         mlx5_core_warn(priv->mdev, "create rqts failed, %d\n", err);
2457         for (ix--; ix >= 0; ix--)
2458                 mlx5e_destroy_rqt(priv, &tirs[ix].rqt);
2459
2460         return err;
2461 }
2462
2463 void mlx5e_destroy_direct_rqts(struct mlx5e_priv *priv, struct mlx5e_tir *tirs)
2464 {
2465         const int max_nch = mlx5e_get_netdev_max_channels(priv->netdev);
2466         int i;
2467
2468         for (i = 0; i < max_nch; i++)
2469                 mlx5e_destroy_rqt(priv, &tirs[i].rqt);
2470 }
2471
2472 static int mlx5e_rx_hash_fn(int hfunc)
2473 {
2474         return (hfunc == ETH_RSS_HASH_TOP) ?
2475                MLX5_RX_HASH_FN_TOEPLITZ :
2476                MLX5_RX_HASH_FN_INVERTED_XOR8;
2477 }
2478
2479 int mlx5e_bits_invert(unsigned long a, int size)
2480 {
2481         int inv = 0;
2482         int i;
2483
2484         for (i = 0; i < size; i++)
2485                 inv |= (test_bit(size - i - 1, &a) ? 1 : 0) << i;
2486
2487         return inv;
2488 }
2489
2490 static void mlx5e_fill_rqt_rqns(struct mlx5e_priv *priv, int sz,
2491                                 struct mlx5e_redirect_rqt_param rrp, void *rqtc)
2492 {
2493         int i;
2494
2495         for (i = 0; i < sz; i++) {
2496                 u32 rqn;
2497
2498                 if (rrp.is_rss) {
2499                         int ix = i;
2500
2501                         if (rrp.rss.hfunc == ETH_RSS_HASH_XOR)
2502                                 ix = mlx5e_bits_invert(i, ilog2(sz));
2503
2504                         ix = priv->rss_params.indirection_rqt[ix];
2505                         rqn = rrp.rss.channels->c[ix]->rq.rqn;
2506                 } else {
2507                         rqn = rrp.rqn;
2508                 }
2509                 MLX5_SET(rqtc, rqtc, rq_num[i], rqn);
2510         }
2511 }
2512
2513 int mlx5e_redirect_rqt(struct mlx5e_priv *priv, u32 rqtn, int sz,
2514                        struct mlx5e_redirect_rqt_param rrp)
2515 {
2516         struct mlx5_core_dev *mdev = priv->mdev;
2517         void *rqtc;
2518         int inlen;
2519         u32 *in;
2520         int err;
2521
2522         inlen = MLX5_ST_SZ_BYTES(modify_rqt_in) + sizeof(u32) * sz;
2523         in = kvzalloc(inlen, GFP_KERNEL);
2524         if (!in)
2525                 return -ENOMEM;
2526
2527         rqtc = MLX5_ADDR_OF(modify_rqt_in, in, ctx);
2528
2529         MLX5_SET(rqtc, rqtc, rqt_actual_size, sz);
2530         MLX5_SET(modify_rqt_in, in, bitmask.rqn_list, 1);
2531         mlx5e_fill_rqt_rqns(priv, sz, rrp, rqtc);
2532         err = mlx5_core_modify_rqt(mdev, rqtn, in, inlen);
2533
2534         kvfree(in);
2535         return err;
2536 }
2537
2538 static u32 mlx5e_get_direct_rqn(struct mlx5e_priv *priv, int ix,
2539                                 struct mlx5e_redirect_rqt_param rrp)
2540 {
2541         if (!rrp.is_rss)
2542                 return rrp.rqn;
2543
2544         if (ix >= rrp.rss.channels->num)
2545                 return priv->drop_rq.rqn;
2546
2547         return rrp.rss.channels->c[ix]->rq.rqn;
2548 }
2549
2550 static void mlx5e_redirect_rqts(struct mlx5e_priv *priv,
2551                                 struct mlx5e_redirect_rqt_param rrp)
2552 {
2553         u32 rqtn;
2554         int ix;
2555
2556         if (priv->indir_rqt.enabled) {
2557                 /* RSS RQ table */
2558                 rqtn = priv->indir_rqt.rqtn;
2559                 mlx5e_redirect_rqt(priv, rqtn, MLX5E_INDIR_RQT_SIZE, rrp);
2560         }
2561
2562         for (ix = 0; ix < mlx5e_get_netdev_max_channels(priv->netdev); ix++) {
2563                 struct mlx5e_redirect_rqt_param direct_rrp = {
2564                         .is_rss = false,
2565                         {
2566                                 .rqn    = mlx5e_get_direct_rqn(priv, ix, rrp)
2567                         },
2568                 };
2569
2570                 /* Direct RQ Tables */
2571                 if (!priv->direct_tir[ix].rqt.enabled)
2572                         continue;
2573
2574                 rqtn = priv->direct_tir[ix].rqt.rqtn;
2575                 mlx5e_redirect_rqt(priv, rqtn, 1, direct_rrp);
2576         }
2577 }
2578
2579 static void mlx5e_redirect_rqts_to_channels(struct mlx5e_priv *priv,
2580                                             struct mlx5e_channels *chs)
2581 {
2582         struct mlx5e_redirect_rqt_param rrp = {
2583                 .is_rss        = true,
2584                 {
2585                         .rss = {
2586                                 .channels  = chs,
2587                                 .hfunc     = priv->rss_params.hfunc,
2588                         }
2589                 },
2590         };
2591
2592         mlx5e_redirect_rqts(priv, rrp);
2593 }
2594
2595 static void mlx5e_redirect_rqts_to_drop(struct mlx5e_priv *priv)
2596 {
2597         struct mlx5e_redirect_rqt_param drop_rrp = {
2598                 .is_rss = false,
2599                 {
2600                         .rqn = priv->drop_rq.rqn,
2601                 },
2602         };
2603
2604         mlx5e_redirect_rqts(priv, drop_rrp);
2605 }
2606
2607 static const struct mlx5e_tirc_config tirc_default_config[MLX5E_NUM_INDIR_TIRS] = {
2608         [MLX5E_TT_IPV4_TCP] = { .l3_prot_type = MLX5_L3_PROT_TYPE_IPV4,
2609                                 .l4_prot_type = MLX5_L4_PROT_TYPE_TCP,
2610                                 .rx_hash_fields = MLX5_HASH_IP_L4PORTS,
2611         },
2612         [MLX5E_TT_IPV6_TCP] = { .l3_prot_type = MLX5_L3_PROT_TYPE_IPV6,
2613                                 .l4_prot_type = MLX5_L4_PROT_TYPE_TCP,
2614                                 .rx_hash_fields = MLX5_HASH_IP_L4PORTS,
2615         },
2616         [MLX5E_TT_IPV4_UDP] = { .l3_prot_type = MLX5_L3_PROT_TYPE_IPV4,
2617                                 .l4_prot_type = MLX5_L4_PROT_TYPE_UDP,
2618                                 .rx_hash_fields = MLX5_HASH_IP_L4PORTS,
2619         },
2620         [MLX5E_TT_IPV6_UDP] = { .l3_prot_type = MLX5_L3_PROT_TYPE_IPV6,
2621                                 .l4_prot_type = MLX5_L4_PROT_TYPE_UDP,
2622                                 .rx_hash_fields = MLX5_HASH_IP_L4PORTS,
2623         },
2624         [MLX5E_TT_IPV4_IPSEC_AH] = { .l3_prot_type = MLX5_L3_PROT_TYPE_IPV4,
2625                                      .l4_prot_type = 0,
2626                                      .rx_hash_fields = MLX5_HASH_IP_IPSEC_SPI,
2627         },
2628         [MLX5E_TT_IPV6_IPSEC_AH] = { .l3_prot_type = MLX5_L3_PROT_TYPE_IPV6,
2629                                      .l4_prot_type = 0,
2630                                      .rx_hash_fields = MLX5_HASH_IP_IPSEC_SPI,
2631         },
2632         [MLX5E_TT_IPV4_IPSEC_ESP] = { .l3_prot_type = MLX5_L3_PROT_TYPE_IPV4,
2633                                       .l4_prot_type = 0,
2634                                       .rx_hash_fields = MLX5_HASH_IP_IPSEC_SPI,
2635         },
2636         [MLX5E_TT_IPV6_IPSEC_ESP] = { .l3_prot_type = MLX5_L3_PROT_TYPE_IPV6,
2637                                       .l4_prot_type = 0,
2638                                       .rx_hash_fields = MLX5_HASH_IP_IPSEC_SPI,
2639         },
2640         [MLX5E_TT_IPV4] = { .l3_prot_type = MLX5_L3_PROT_TYPE_IPV4,
2641                             .l4_prot_type = 0,
2642                             .rx_hash_fields = MLX5_HASH_IP,
2643         },
2644         [MLX5E_TT_IPV6] = { .l3_prot_type = MLX5_L3_PROT_TYPE_IPV6,
2645                             .l4_prot_type = 0,
2646                             .rx_hash_fields = MLX5_HASH_IP,
2647         },
2648 };
2649
2650 struct mlx5e_tirc_config mlx5e_tirc_get_default_config(enum mlx5e_traffic_types tt)
2651 {
2652         return tirc_default_config[tt];
2653 }
2654
2655 static void mlx5e_build_tir_ctx_lro(struct mlx5e_params *params, void *tirc)
2656 {
2657         if (!params->lro_en)
2658                 return;
2659
2660 #define ROUGH_MAX_L2_L3_HDR_SZ 256
2661
2662         MLX5_SET(tirc, tirc, lro_enable_mask,
2663                  MLX5_TIRC_LRO_ENABLE_MASK_IPV4_LRO |
2664                  MLX5_TIRC_LRO_ENABLE_MASK_IPV6_LRO);
2665         MLX5_SET(tirc, tirc, lro_max_ip_payload_size,
2666                  (MLX5E_PARAMS_DEFAULT_LRO_WQE_SZ - ROUGH_MAX_L2_L3_HDR_SZ) >> 8);
2667         MLX5_SET(tirc, tirc, lro_timeout_period_usecs, params->lro_timeout);
2668 }
2669
2670 void mlx5e_build_indir_tir_ctx_hash(struct mlx5e_rss_params *rss_params,
2671                                     const struct mlx5e_tirc_config *ttconfig,
2672                                     void *tirc, bool inner)
2673 {
2674         void *hfso = inner ? MLX5_ADDR_OF(tirc, tirc, rx_hash_field_selector_inner) :
2675                              MLX5_ADDR_OF(tirc, tirc, rx_hash_field_selector_outer);
2676
2677         MLX5_SET(tirc, tirc, rx_hash_fn, mlx5e_rx_hash_fn(rss_params->hfunc));
2678         if (rss_params->hfunc == ETH_RSS_HASH_TOP) {
2679                 void *rss_key = MLX5_ADDR_OF(tirc, tirc,
2680                                              rx_hash_toeplitz_key);
2681                 size_t len = MLX5_FLD_SZ_BYTES(tirc,
2682                                                rx_hash_toeplitz_key);
2683
2684                 MLX5_SET(tirc, tirc, rx_hash_symmetric, 1);
2685                 memcpy(rss_key, rss_params->toeplitz_hash_key, len);
2686         }
2687         MLX5_SET(rx_hash_field_select, hfso, l3_prot_type,
2688                  ttconfig->l3_prot_type);
2689         MLX5_SET(rx_hash_field_select, hfso, l4_prot_type,
2690                  ttconfig->l4_prot_type);
2691         MLX5_SET(rx_hash_field_select, hfso, selected_fields,
2692                  ttconfig->rx_hash_fields);
2693 }
2694
2695 static void mlx5e_update_rx_hash_fields(struct mlx5e_tirc_config *ttconfig,
2696                                         enum mlx5e_traffic_types tt,
2697                                         u32 rx_hash_fields)
2698 {
2699         *ttconfig                = tirc_default_config[tt];
2700         ttconfig->rx_hash_fields = rx_hash_fields;
2701 }
2702
2703 void mlx5e_modify_tirs_hash(struct mlx5e_priv *priv, void *in, int inlen)
2704 {
2705         void *tirc = MLX5_ADDR_OF(modify_tir_in, in, ctx);
2706         struct mlx5e_rss_params *rss = &priv->rss_params;
2707         struct mlx5_core_dev *mdev = priv->mdev;
2708         int ctxlen = MLX5_ST_SZ_BYTES(tirc);
2709         struct mlx5e_tirc_config ttconfig;
2710         int tt;
2711
2712         MLX5_SET(modify_tir_in, in, bitmask.hash, 1);
2713
2714         for (tt = 0; tt < MLX5E_NUM_INDIR_TIRS; tt++) {
2715                 memset(tirc, 0, ctxlen);
2716                 mlx5e_update_rx_hash_fields(&ttconfig, tt,
2717                                             rss->rx_hash_fields[tt]);
2718                 mlx5e_build_indir_tir_ctx_hash(rss, &ttconfig, tirc, false);
2719                 mlx5_core_modify_tir(mdev, priv->indir_tir[tt].tirn, in, inlen);
2720         }
2721
2722         if (!mlx5e_tunnel_inner_ft_supported(priv->mdev))
2723                 return;
2724
2725         for (tt = 0; tt < MLX5E_NUM_INDIR_TIRS; tt++) {
2726                 memset(tirc, 0, ctxlen);
2727                 mlx5e_update_rx_hash_fields(&ttconfig, tt,
2728                                             rss->rx_hash_fields[tt]);
2729                 mlx5e_build_indir_tir_ctx_hash(rss, &ttconfig, tirc, true);
2730                 mlx5_core_modify_tir(mdev, priv->inner_indir_tir[tt].tirn, in,
2731                                      inlen);
2732         }
2733 }
2734
2735 static int mlx5e_modify_tirs_lro(struct mlx5e_priv *priv)
2736 {
2737         struct mlx5_core_dev *mdev = priv->mdev;
2738
2739         void *in;
2740         void *tirc;
2741         int inlen;
2742         int err;
2743         int tt;
2744         int ix;
2745
2746         inlen = MLX5_ST_SZ_BYTES(modify_tir_in);
2747         in = kvzalloc(inlen, GFP_KERNEL);
2748         if (!in)
2749                 return -ENOMEM;
2750
2751         MLX5_SET(modify_tir_in, in, bitmask.lro, 1);
2752         tirc = MLX5_ADDR_OF(modify_tir_in, in, ctx);
2753
2754         mlx5e_build_tir_ctx_lro(&priv->channels.params, tirc);
2755
2756         for (tt = 0; tt < MLX5E_NUM_INDIR_TIRS; tt++) {
2757                 err = mlx5_core_modify_tir(mdev, priv->indir_tir[tt].tirn, in,
2758                                            inlen);
2759                 if (err)
2760                         goto free_in;
2761         }
2762
2763         for (ix = 0; ix < mlx5e_get_netdev_max_channels(priv->netdev); ix++) {
2764                 err = mlx5_core_modify_tir(mdev, priv->direct_tir[ix].tirn,
2765                                            in, inlen);
2766                 if (err)
2767                         goto free_in;
2768         }
2769
2770 free_in:
2771         kvfree(in);
2772
2773         return err;
2774 }
2775
2776 static int mlx5e_set_mtu(struct mlx5_core_dev *mdev,
2777                          struct mlx5e_params *params, u16 mtu)
2778 {
2779         u16 hw_mtu = MLX5E_SW2HW_MTU(params, mtu);
2780         int err;
2781
2782         err = mlx5_set_port_mtu(mdev, hw_mtu, 1);
2783         if (err)
2784                 return err;
2785
2786         /* Update vport context MTU */
2787         mlx5_modify_nic_vport_mtu(mdev, hw_mtu);
2788         return 0;
2789 }
2790
2791 static void mlx5e_query_mtu(struct mlx5_core_dev *mdev,
2792                             struct mlx5e_params *params, u16 *mtu)
2793 {
2794         u16 hw_mtu = 0;
2795         int err;
2796
2797         err = mlx5_query_nic_vport_mtu(mdev, &hw_mtu);
2798         if (err || !hw_mtu) /* fallback to port oper mtu */
2799                 mlx5_query_port_oper_mtu(mdev, &hw_mtu, 1);
2800
2801         *mtu = MLX5E_HW2SW_MTU(params, hw_mtu);
2802 }
2803
2804 int mlx5e_set_dev_port_mtu(struct mlx5e_priv *priv)
2805 {
2806         struct mlx5e_params *params = &priv->channels.params;
2807         struct net_device *netdev = priv->netdev;
2808         struct mlx5_core_dev *mdev = priv->mdev;
2809         u16 mtu;
2810         int err;
2811
2812         err = mlx5e_set_mtu(mdev, params, params->sw_mtu);
2813         if (err)
2814                 return err;
2815
2816         mlx5e_query_mtu(mdev, params, &mtu);
2817         if (mtu != params->sw_mtu)
2818                 netdev_warn(netdev, "%s: VPort MTU %d is different than netdev mtu %d\n",
2819                             __func__, mtu, params->sw_mtu);
2820
2821         params->sw_mtu = mtu;
2822         return 0;
2823 }
2824
2825 void mlx5e_set_netdev_mtu_boundaries(struct mlx5e_priv *priv)
2826 {
2827         struct mlx5e_params *params = &priv->channels.params;
2828         struct net_device *netdev   = priv->netdev;
2829         struct mlx5_core_dev *mdev  = priv->mdev;
2830         u16 max_mtu;
2831
2832         /* MTU range: 68 - hw-specific max */
2833         netdev->min_mtu = ETH_MIN_MTU;
2834
2835         mlx5_query_port_max_mtu(mdev, &max_mtu, 1);
2836         netdev->max_mtu = min_t(unsigned int, MLX5E_HW2SW_MTU(params, max_mtu),
2837                                 ETH_MAX_MTU);
2838 }
2839
2840 static void mlx5e_netdev_set_tcs(struct net_device *netdev)
2841 {
2842         struct mlx5e_priv *priv = netdev_priv(netdev);
2843         int nch = priv->channels.params.num_channels;
2844         int ntc = priv->channels.params.num_tc;
2845         int tc;
2846
2847         netdev_reset_tc(netdev);
2848
2849         if (ntc == 1)
2850                 return;
2851
2852         netdev_set_num_tc(netdev, ntc);
2853
2854         /* Map netdev TCs to offset 0
2855          * We have our own UP to TXQ mapping for QoS
2856          */
2857         for (tc = 0; tc < ntc; tc++)
2858                 netdev_set_tc_queue(netdev, tc, nch, 0);
2859 }
2860
2861 static void mlx5e_build_tc2txq_maps(struct mlx5e_priv *priv)
2862 {
2863         int max_nch = mlx5e_get_netdev_max_channels(priv->netdev);
2864         int i, tc;
2865
2866         for (i = 0; i < max_nch; i++)
2867                 for (tc = 0; tc < priv->profile->max_tc; tc++)
2868                         priv->channel_tc2txq[i][tc] = i + tc * max_nch;
2869 }
2870
2871 static void mlx5e_build_tx2sq_maps(struct mlx5e_priv *priv)
2872 {
2873         struct mlx5e_channel *c;
2874         struct mlx5e_txqsq *sq;
2875         int i, tc;
2876
2877         for (i = 0; i < priv->channels.num; i++) {
2878                 c = priv->channels.c[i];
2879                 for (tc = 0; tc < c->num_tc; tc++) {
2880                         sq = &c->sq[tc];
2881                         priv->txq2sq[sq->txq_ix] = sq;
2882                 }
2883         }
2884 }
2885
2886 void mlx5e_activate_priv_channels(struct mlx5e_priv *priv)
2887 {
2888         int num_txqs = priv->channels.num * priv->channels.params.num_tc;
2889         int num_rxqs = priv->channels.num * MLX5E_NUM_RQ_GROUPS;
2890         struct net_device *netdev = priv->netdev;
2891
2892         mlx5e_netdev_set_tcs(netdev);
2893         netif_set_real_num_tx_queues(netdev, num_txqs);
2894         netif_set_real_num_rx_queues(netdev, num_rxqs);
2895
2896         mlx5e_build_tx2sq_maps(priv);
2897         mlx5e_activate_channels(&priv->channels);
2898         mlx5e_xdp_tx_enable(priv);
2899         netif_tx_start_all_queues(priv->netdev);
2900
2901         if (mlx5e_is_vport_rep(priv))
2902                 mlx5e_add_sqs_fwd_rules(priv);
2903
2904         mlx5e_wait_channels_min_rx_wqes(&priv->channels);
2905         mlx5e_redirect_rqts_to_channels(priv, &priv->channels);
2906
2907         mlx5e_xsk_redirect_rqts_to_channels(priv, &priv->channels);
2908 }
2909
2910 void mlx5e_deactivate_priv_channels(struct mlx5e_priv *priv)
2911 {
2912         mlx5e_xsk_redirect_rqts_to_drop(priv, &priv->channels);
2913
2914         mlx5e_redirect_rqts_to_drop(priv);
2915
2916         if (mlx5e_is_vport_rep(priv))
2917                 mlx5e_remove_sqs_fwd_rules(priv);
2918
2919         /* FIXME: This is a W/A only for tx timeout watch dog false alarm when
2920          * polling for inactive tx queues.
2921          */
2922         netif_tx_stop_all_queues(priv->netdev);
2923         netif_tx_disable(priv->netdev);
2924         mlx5e_xdp_tx_disable(priv);
2925         mlx5e_deactivate_channels(&priv->channels);
2926 }
2927
2928 static void mlx5e_switch_priv_channels(struct mlx5e_priv *priv,
2929                                        struct mlx5e_channels *new_chs,
2930                                        mlx5e_fp_hw_modify hw_modify)
2931 {
2932         struct net_device *netdev = priv->netdev;
2933         int new_num_txqs;
2934         int carrier_ok;
2935
2936         new_num_txqs = new_chs->num * new_chs->params.num_tc;
2937
2938         carrier_ok = netif_carrier_ok(netdev);
2939         netif_carrier_off(netdev);
2940
2941         if (new_num_txqs < netdev->real_num_tx_queues)
2942                 netif_set_real_num_tx_queues(netdev, new_num_txqs);
2943
2944         mlx5e_deactivate_priv_channels(priv);
2945         mlx5e_close_channels(&priv->channels);
2946
2947         priv->channels = *new_chs;
2948
2949         /* New channels are ready to roll, modify HW settings if needed */
2950         if (hw_modify)
2951                 hw_modify(priv);
2952
2953         priv->profile->update_rx(priv);
2954         mlx5e_activate_priv_channels(priv);
2955
2956         /* return carrier back if needed */
2957         if (carrier_ok)
2958                 netif_carrier_on(netdev);
2959 }
2960
2961 int mlx5e_safe_switch_channels(struct mlx5e_priv *priv,
2962                                struct mlx5e_channels *new_chs,
2963                                mlx5e_fp_hw_modify hw_modify)
2964 {
2965         int err;
2966
2967         err = mlx5e_open_channels(priv, new_chs);
2968         if (err)
2969                 return err;
2970
2971         mlx5e_switch_priv_channels(priv, new_chs, hw_modify);
2972         return 0;
2973 }
2974
2975 int mlx5e_safe_reopen_channels(struct mlx5e_priv *priv)
2976 {
2977         struct mlx5e_channels new_channels = {};
2978
2979         new_channels.params = priv->channels.params;
2980         return mlx5e_safe_switch_channels(priv, &new_channels, NULL);
2981 }
2982
2983 void mlx5e_timestamp_init(struct mlx5e_priv *priv)
2984 {
2985         priv->tstamp.tx_type   = HWTSTAMP_TX_OFF;
2986         priv->tstamp.rx_filter = HWTSTAMP_FILTER_NONE;
2987 }
2988
2989 int mlx5e_open_locked(struct net_device *netdev)
2990 {
2991         struct mlx5e_priv *priv = netdev_priv(netdev);
2992         bool is_xdp = priv->channels.params.xdp_prog;
2993         int err;
2994
2995         set_bit(MLX5E_STATE_OPENED, &priv->state);
2996         if (is_xdp)
2997                 mlx5e_xdp_set_open(priv);
2998
2999         err = mlx5e_open_channels(priv, &priv->channels);
3000         if (err)
3001                 goto err_clear_state_opened_flag;
3002
3003         priv->profile->update_rx(priv);
3004         mlx5e_activate_priv_channels(priv);
3005         if (priv->profile->update_carrier)
3006                 priv->profile->update_carrier(priv);
3007
3008         mlx5e_queue_update_stats(priv);
3009         return 0;
3010
3011 err_clear_state_opened_flag:
3012         if (is_xdp)
3013                 mlx5e_xdp_set_closed(priv);
3014         clear_bit(MLX5E_STATE_OPENED, &priv->state);
3015         return err;
3016 }
3017
3018 int mlx5e_open(struct net_device *netdev)
3019 {
3020         struct mlx5e_priv *priv = netdev_priv(netdev);
3021         int err;
3022
3023         mutex_lock(&priv->state_lock);
3024         err = mlx5e_open_locked(netdev);
3025         if (!err)
3026                 mlx5_set_port_admin_status(priv->mdev, MLX5_PORT_UP);
3027         mutex_unlock(&priv->state_lock);
3028
3029         if (mlx5_vxlan_allowed(priv->mdev->vxlan))
3030                 udp_tunnel_get_rx_info(netdev);
3031
3032         return err;
3033 }
3034
3035 int mlx5e_close_locked(struct net_device *netdev)
3036 {
3037         struct mlx5e_priv *priv = netdev_priv(netdev);
3038
3039         /* May already be CLOSED in case a previous configuration operation
3040          * (e.g RX/TX queue size change) that involves close&open failed.
3041          */
3042         if (!test_bit(MLX5E_STATE_OPENED, &priv->state))
3043                 return 0;
3044
3045         if (priv->channels.params.xdp_prog)
3046                 mlx5e_xdp_set_closed(priv);
3047         clear_bit(MLX5E_STATE_OPENED, &priv->state);
3048
3049         netif_carrier_off(priv->netdev);
3050         mlx5e_deactivate_priv_channels(priv);
3051         mlx5e_close_channels(&priv->channels);
3052
3053         return 0;
3054 }
3055
3056 int mlx5e_close(struct net_device *netdev)
3057 {
3058         struct mlx5e_priv *priv = netdev_priv(netdev);
3059         int err;
3060
3061         if (!netif_device_present(netdev))
3062                 return -ENODEV;
3063
3064         mutex_lock(&priv->state_lock);
3065         mlx5_set_port_admin_status(priv->mdev, MLX5_PORT_DOWN);
3066         err = mlx5e_close_locked(netdev);
3067         mutex_unlock(&priv->state_lock);
3068
3069         return err;
3070 }
3071
3072 static int mlx5e_alloc_drop_rq(struct mlx5_core_dev *mdev,
3073                                struct mlx5e_rq *rq,
3074                                struct mlx5e_rq_param *param)
3075 {
3076         void *rqc = param->rqc;
3077         void *rqc_wq = MLX5_ADDR_OF(rqc, rqc, wq);
3078         int err;
3079
3080         param->wq.db_numa_node = param->wq.buf_numa_node;
3081
3082         err = mlx5_wq_cyc_create(mdev, &param->wq, rqc_wq, &rq->wqe.wq,
3083                                  &rq->wq_ctrl);
3084         if (err)
3085                 return err;
3086
3087         /* Mark as unused given "Drop-RQ" packets never reach XDP */
3088         xdp_rxq_info_unused(&rq->xdp_rxq);
3089
3090         rq->mdev = mdev;
3091
3092         return 0;
3093 }
3094
3095 static int mlx5e_alloc_drop_cq(struct mlx5_core_dev *mdev,
3096                                struct mlx5e_cq *cq,
3097                                struct mlx5e_cq_param *param)
3098 {
3099         param->wq.buf_numa_node = dev_to_node(mdev->device);
3100         param->wq.db_numa_node  = dev_to_node(mdev->device);
3101
3102         return mlx5e_alloc_cq_common(mdev, param, cq);
3103 }
3104
3105 int mlx5e_open_drop_rq(struct mlx5e_priv *priv,
3106                        struct mlx5e_rq *drop_rq)
3107 {
3108         struct mlx5_core_dev *mdev = priv->mdev;
3109         struct mlx5e_cq_param cq_param = {};
3110         struct mlx5e_rq_param rq_param = {};
3111         struct mlx5e_cq *cq = &drop_rq->cq;
3112         int err;
3113
3114         mlx5e_build_drop_rq_param(priv, &rq_param);
3115
3116         err = mlx5e_alloc_drop_cq(mdev, cq, &cq_param);
3117         if (err)
3118                 return err;
3119
3120         err = mlx5e_create_cq(cq, &cq_param);
3121         if (err)
3122                 goto err_free_cq;
3123
3124         err = mlx5e_alloc_drop_rq(mdev, drop_rq, &rq_param);
3125         if (err)
3126                 goto err_destroy_cq;
3127
3128         err = mlx5e_create_rq(drop_rq, &rq_param);
3129         if (err)
3130                 goto err_free_rq;
3131
3132         err = mlx5e_modify_rq_state(drop_rq, MLX5_RQC_STATE_RST, MLX5_RQC_STATE_RDY);
3133         if (err)
3134                 mlx5_core_warn(priv->mdev, "modify_rq_state failed, rx_if_down_packets won't be counted %d\n", err);
3135
3136         return 0;
3137
3138 err_free_rq:
3139         mlx5e_free_rq(drop_rq);
3140
3141 err_destroy_cq:
3142         mlx5e_destroy_cq(cq);
3143
3144 err_free_cq:
3145         mlx5e_free_cq(cq);
3146
3147         return err;
3148 }
3149
3150 void mlx5e_close_drop_rq(struct mlx5e_rq *drop_rq)
3151 {
3152         mlx5e_destroy_rq(drop_rq);
3153         mlx5e_free_rq(drop_rq);
3154         mlx5e_destroy_cq(&drop_rq->cq);
3155         mlx5e_free_cq(&drop_rq->cq);
3156 }
3157
3158 int mlx5e_create_tis(struct mlx5_core_dev *mdev, void *in, u32 *tisn)
3159 {
3160         void *tisc = MLX5_ADDR_OF(create_tis_in, in, ctx);
3161
3162         MLX5_SET(tisc, tisc, transport_domain, mdev->mlx5e_res.td.tdn);
3163
3164         if (MLX5_GET(tisc, tisc, tls_en))
3165                 MLX5_SET(tisc, tisc, pd, mdev->mlx5e_res.pdn);
3166
3167         if (mlx5_lag_is_lacp_owner(mdev))
3168                 MLX5_SET(tisc, tisc, strict_lag_tx_port_affinity, 1);
3169
3170         return mlx5_core_create_tis(mdev, in, MLX5_ST_SZ_BYTES(create_tis_in), tisn);
3171 }
3172
3173 void mlx5e_destroy_tis(struct mlx5_core_dev *mdev, u32 tisn)
3174 {
3175         mlx5_core_destroy_tis(mdev, tisn);
3176 }
3177
3178 int mlx5e_create_tises(struct mlx5e_priv *priv)
3179 {
3180         int err;
3181         int tc;
3182
3183         for (tc = 0; tc < priv->profile->max_tc; tc++) {
3184                 u32 in[MLX5_ST_SZ_DW(create_tis_in)] = {};
3185                 void *tisc;
3186
3187                 tisc = MLX5_ADDR_OF(create_tis_in, in, ctx);
3188
3189                 MLX5_SET(tisc, tisc, prio, tc << 1);
3190
3191                 err = mlx5e_create_tis(priv->mdev, in, &priv->tisn[tc]);
3192                 if (err)
3193                         goto err_close_tises;
3194         }
3195
3196         return 0;
3197
3198 err_close_tises:
3199         for (tc--; tc >= 0; tc--)
3200                 mlx5e_destroy_tis(priv->mdev, priv->tisn[tc]);
3201
3202         return err;
3203 }
3204
3205 static void mlx5e_cleanup_nic_tx(struct mlx5e_priv *priv)
3206 {
3207         int tc;
3208
3209         mlx5e_tx_reporter_destroy(priv);
3210         for (tc = 0; tc < priv->profile->max_tc; tc++)
3211                 mlx5e_destroy_tis(priv->mdev, priv->tisn[tc]);
3212 }
3213
3214 static void mlx5e_build_indir_tir_ctx_common(struct mlx5e_priv *priv,
3215                                              u32 rqtn, u32 *tirc)
3216 {
3217         MLX5_SET(tirc, tirc, transport_domain, priv->mdev->mlx5e_res.td.tdn);
3218         MLX5_SET(tirc, tirc, disp_type, MLX5_TIRC_DISP_TYPE_INDIRECT);
3219         MLX5_SET(tirc, tirc, indirect_table, rqtn);
3220         MLX5_SET(tirc, tirc, tunneled_offload_en,
3221                  priv->channels.params.tunneled_offload_en);
3222
3223         mlx5e_build_tir_ctx_lro(&priv->channels.params, tirc);
3224 }
3225
3226 static void mlx5e_build_indir_tir_ctx(struct mlx5e_priv *priv,
3227                                       enum mlx5e_traffic_types tt,
3228                                       u32 *tirc)
3229 {
3230         mlx5e_build_indir_tir_ctx_common(priv, priv->indir_rqt.rqtn, tirc);
3231         mlx5e_build_indir_tir_ctx_hash(&priv->rss_params,
3232                                        &tirc_default_config[tt], tirc, false);
3233 }
3234
3235 static void mlx5e_build_direct_tir_ctx(struct mlx5e_priv *priv, u32 rqtn, u32 *tirc)
3236 {
3237         mlx5e_build_indir_tir_ctx_common(priv, rqtn, tirc);
3238         MLX5_SET(tirc, tirc, rx_hash_fn, MLX5_RX_HASH_FN_INVERTED_XOR8);
3239 }
3240
3241 static void mlx5e_build_inner_indir_tir_ctx(struct mlx5e_priv *priv,
3242                                             enum mlx5e_traffic_types tt,
3243                                             u32 *tirc)
3244 {
3245         mlx5e_build_indir_tir_ctx_common(priv, priv->indir_rqt.rqtn, tirc);
3246         mlx5e_build_indir_tir_ctx_hash(&priv->rss_params,
3247                                        &tirc_default_config[tt], tirc, true);
3248 }
3249
3250 int mlx5e_create_indirect_tirs(struct mlx5e_priv *priv, bool inner_ttc)
3251 {
3252         struct mlx5e_tir *tir;
3253         void *tirc;
3254         int inlen;
3255         int i = 0;
3256         int err;
3257         u32 *in;
3258         int tt;
3259
3260         inlen = MLX5_ST_SZ_BYTES(create_tir_in);
3261         in = kvzalloc(inlen, GFP_KERNEL);
3262         if (!in)
3263                 return -ENOMEM;
3264
3265         for (tt = 0; tt < MLX5E_NUM_INDIR_TIRS; tt++) {
3266                 memset(in, 0, inlen);
3267                 tir = &priv->indir_tir[tt];
3268                 tirc = MLX5_ADDR_OF(create_tir_in, in, ctx);
3269                 mlx5e_build_indir_tir_ctx(priv, tt, tirc);
3270                 err = mlx5e_create_tir(priv->mdev, tir, in, inlen);
3271                 if (err) {
3272                         mlx5_core_warn(priv->mdev, "create indirect tirs failed, %d\n", err);
3273                         goto err_destroy_inner_tirs;
3274                 }
3275         }
3276
3277         if (!inner_ttc || !mlx5e_tunnel_inner_ft_supported(priv->mdev))
3278                 goto out;
3279
3280         for (i = 0; i < MLX5E_NUM_INDIR_TIRS; i++) {
3281                 memset(in, 0, inlen);
3282                 tir = &priv->inner_indir_tir[i];
3283                 tirc = MLX5_ADDR_OF(create_tir_in, in, ctx);
3284                 mlx5e_build_inner_indir_tir_ctx(priv, i, tirc);
3285                 err = mlx5e_create_tir(priv->mdev, tir, in, inlen);
3286                 if (err) {
3287                         mlx5_core_warn(priv->mdev, "create inner indirect tirs failed, %d\n", err);
3288                         goto err_destroy_inner_tirs;
3289                 }
3290         }
3291
3292 out:
3293         kvfree(in);
3294
3295         return 0;
3296
3297 err_destroy_inner_tirs:
3298         for (i--; i >= 0; i--)
3299                 mlx5e_destroy_tir(priv->mdev, &priv->inner_indir_tir[i]);
3300
3301         for (tt--; tt >= 0; tt--)
3302                 mlx5e_destroy_tir(priv->mdev, &priv->indir_tir[tt]);
3303
3304         kvfree(in);
3305
3306         return err;
3307 }
3308
3309 int mlx5e_create_direct_tirs(struct mlx5e_priv *priv, struct mlx5e_tir *tirs)
3310 {
3311         const int max_nch = mlx5e_get_netdev_max_channels(priv->netdev);
3312         struct mlx5e_tir *tir;
3313         void *tirc;
3314         int inlen;
3315         int err = 0;
3316         u32 *in;
3317         int ix;
3318
3319         inlen = MLX5_ST_SZ_BYTES(create_tir_in);
3320         in = kvzalloc(inlen, GFP_KERNEL);
3321         if (!in)
3322                 return -ENOMEM;
3323
3324         for (ix = 0; ix < max_nch; ix++) {
3325                 memset(in, 0, inlen);
3326                 tir = &tirs[ix];
3327                 tirc = MLX5_ADDR_OF(create_tir_in, in, ctx);
3328                 mlx5e_build_direct_tir_ctx(priv, tir->rqt.rqtn, tirc);
3329                 err = mlx5e_create_tir(priv->mdev, tir, in, inlen);
3330                 if (unlikely(err))
3331                         goto err_destroy_ch_tirs;
3332         }
3333
3334         goto out;
3335
3336 err_destroy_ch_tirs:
3337         mlx5_core_warn(priv->mdev, "create tirs failed, %d\n", err);
3338         for (ix--; ix >= 0; ix--)
3339                 mlx5e_destroy_tir(priv->mdev, &tirs[ix]);
3340
3341 out:
3342         kvfree(in);
3343
3344         return err;
3345 }
3346
3347 void mlx5e_destroy_indirect_tirs(struct mlx5e_priv *priv, bool inner_ttc)
3348 {
3349         int i;
3350
3351         for (i = 0; i < MLX5E_NUM_INDIR_TIRS; i++)
3352                 mlx5e_destroy_tir(priv->mdev, &priv->indir_tir[i]);
3353
3354         if (!inner_ttc || !mlx5e_tunnel_inner_ft_supported(priv->mdev))
3355                 return;
3356
3357         for (i = 0; i < MLX5E_NUM_INDIR_TIRS; i++)
3358                 mlx5e_destroy_tir(priv->mdev, &priv->inner_indir_tir[i]);
3359 }
3360
3361 void mlx5e_destroy_direct_tirs(struct mlx5e_priv *priv, struct mlx5e_tir *tirs)
3362 {
3363         const int max_nch = mlx5e_get_netdev_max_channels(priv->netdev);
3364         int i;
3365
3366         for (i = 0; i < max_nch; i++)
3367                 mlx5e_destroy_tir(priv->mdev, &tirs[i]);
3368 }
3369
3370 static int mlx5e_modify_channels_scatter_fcs(struct mlx5e_channels *chs, bool enable)
3371 {
3372         int err = 0;
3373         int i;
3374
3375         for (i = 0; i < chs->num; i++) {
3376                 err = mlx5e_modify_rq_scatter_fcs(&chs->c[i]->rq, enable);
3377                 if (err)
3378                         return err;
3379         }
3380
3381         return 0;
3382 }
3383
3384 static int mlx5e_modify_channels_vsd(struct mlx5e_channels *chs, bool vsd)
3385 {
3386         int err = 0;
3387         int i;
3388
3389         for (i = 0; i < chs->num; i++) {
3390                 err = mlx5e_modify_rq_vsd(&chs->c[i]->rq, vsd);
3391                 if (err)
3392                         return err;
3393         }
3394
3395         return 0;
3396 }
3397
3398 static int mlx5e_setup_tc_mqprio(struct mlx5e_priv *priv,
3399                                  struct tc_mqprio_qopt *mqprio)
3400 {
3401         struct mlx5e_channels new_channels = {};
3402         u8 tc = mqprio->num_tc;
3403         int err = 0;
3404
3405         mqprio->hw = TC_MQPRIO_HW_OFFLOAD_TCS;
3406
3407         if (tc && tc != MLX5E_MAX_NUM_TC)
3408                 return -EINVAL;
3409
3410         mutex_lock(&priv->state_lock);
3411
3412         new_channels.params = priv->channels.params;
3413         new_channels.params.num_tc = tc ? tc : 1;
3414
3415         if (!test_bit(MLX5E_STATE_OPENED, &priv->state)) {
3416                 priv->channels.params = new_channels.params;
3417                 goto out;
3418         }
3419
3420         err = mlx5e_safe_switch_channels(priv, &new_channels, NULL);
3421         if (err)
3422                 goto out;
3423
3424         priv->max_opened_tc = max_t(u8, priv->max_opened_tc,
3425                                     new_channels.params.num_tc);
3426 out:
3427         mutex_unlock(&priv->state_lock);
3428         return err;
3429 }
3430
3431 #ifdef CONFIG_MLX5_ESWITCH
3432 static int mlx5e_setup_tc_cls_flower(struct mlx5e_priv *priv,
3433                                      struct flow_cls_offload *cls_flower,
3434                                      unsigned long flags)
3435 {
3436         switch (cls_flower->command) {
3437         case FLOW_CLS_REPLACE:
3438                 return mlx5e_configure_flower(priv->netdev, priv, cls_flower,
3439                                               flags);
3440         case FLOW_CLS_DESTROY:
3441                 return mlx5e_delete_flower(priv->netdev, priv, cls_flower,
3442                                            flags);
3443         case FLOW_CLS_STATS:
3444                 return mlx5e_stats_flower(priv->netdev, priv, cls_flower,
3445                                           flags);
3446         default:
3447                 return -EOPNOTSUPP;
3448         }
3449 }
3450
3451 static int mlx5e_setup_tc_block_cb(enum tc_setup_type type, void *type_data,
3452                                    void *cb_priv)
3453 {
3454         unsigned long flags = MLX5_TC_FLAG(INGRESS) | MLX5_TC_FLAG(NIC_OFFLOAD);
3455         struct mlx5e_priv *priv = cb_priv;
3456
3457         switch (type) {
3458         case TC_SETUP_CLSFLOWER:
3459                 return mlx5e_setup_tc_cls_flower(priv, type_data, flags);
3460         default:
3461                 return -EOPNOTSUPP;
3462         }
3463 }
3464 #endif
3465
3466 static LIST_HEAD(mlx5e_block_cb_list);
3467
3468 static int mlx5e_setup_tc(struct net_device *dev, enum tc_setup_type type,
3469                           void *type_data)
3470 {
3471         struct mlx5e_priv *priv = netdev_priv(dev);
3472
3473         switch (type) {
3474 #ifdef CONFIG_MLX5_ESWITCH
3475         case TC_SETUP_BLOCK:
3476                 return flow_block_cb_setup_simple(type_data,
3477                                                   &mlx5e_block_cb_list,
3478                                                   mlx5e_setup_tc_block_cb,
3479                                                   priv, priv, true);
3480 #endif
3481         case TC_SETUP_QDISC_MQPRIO:
3482                 return mlx5e_setup_tc_mqprio(priv, type_data);
3483         default:
3484                 return -EOPNOTSUPP;
3485         }
3486 }
3487
3488 void mlx5e_fold_sw_stats64(struct mlx5e_priv *priv, struct rtnl_link_stats64 *s)
3489 {
3490         int i;
3491
3492         for (i = 0; i < mlx5e_get_netdev_max_channels(priv->netdev); i++) {
3493                 struct mlx5e_channel_stats *channel_stats = &priv->channel_stats[i];
3494                 struct mlx5e_rq_stats *xskrq_stats = &channel_stats->xskrq;
3495                 struct mlx5e_rq_stats *rq_stats = &channel_stats->rq;
3496                 int j;
3497
3498                 s->rx_packets   += rq_stats->packets + xskrq_stats->packets;
3499                 s->rx_bytes     += rq_stats->bytes + xskrq_stats->bytes;
3500
3501                 for (j = 0; j < priv->max_opened_tc; j++) {
3502                         struct mlx5e_sq_stats *sq_stats = &channel_stats->sq[j];
3503
3504                         s->tx_packets    += sq_stats->packets;
3505                         s->tx_bytes      += sq_stats->bytes;
3506                         s->tx_dropped    += sq_stats->dropped;
3507                 }
3508         }
3509 }
3510
3511 void
3512 mlx5e_get_stats(struct net_device *dev, struct rtnl_link_stats64 *stats)
3513 {
3514         struct mlx5e_priv *priv = netdev_priv(dev);
3515         struct mlx5e_vport_stats *vstats = &priv->stats.vport;
3516         struct mlx5e_pport_stats *pstats = &priv->stats.pport;
3517
3518         if (!mlx5e_monitor_counter_supported(priv)) {
3519                 /* update HW stats in background for next time */
3520                 mlx5e_queue_update_stats(priv);
3521         }
3522
3523         if (mlx5e_is_uplink_rep(priv)) {
3524                 stats->rx_packets = PPORT_802_3_GET(pstats, a_frames_received_ok);
3525                 stats->rx_bytes   = PPORT_802_3_GET(pstats, a_octets_received_ok);
3526                 stats->tx_packets = PPORT_802_3_GET(pstats, a_frames_transmitted_ok);
3527                 stats->tx_bytes   = PPORT_802_3_GET(pstats, a_octets_transmitted_ok);
3528         } else {
3529                 mlx5e_fold_sw_stats64(priv, stats);
3530         }
3531
3532         stats->rx_dropped = priv->stats.qcnt.rx_out_of_buffer;
3533
3534         stats->rx_length_errors =
3535                 PPORT_802_3_GET(pstats, a_in_range_length_errors) +
3536                 PPORT_802_3_GET(pstats, a_out_of_range_length_field) +
3537                 PPORT_802_3_GET(pstats, a_frame_too_long_errors);
3538         stats->rx_crc_errors =
3539                 PPORT_802_3_GET(pstats, a_frame_check_sequence_errors);
3540         stats->rx_frame_errors = PPORT_802_3_GET(pstats, a_alignment_errors);
3541         stats->tx_aborted_errors = PPORT_2863_GET(pstats, if_out_discards);
3542         stats->rx_errors = stats->rx_length_errors + stats->rx_crc_errors +
3543                            stats->rx_frame_errors;
3544         stats->tx_errors = stats->tx_aborted_errors + stats->tx_carrier_errors;
3545
3546         /* vport multicast also counts packets that are dropped due to steering
3547          * or rx out of buffer
3548          */
3549         stats->multicast =
3550                 VPORT_COUNTER_GET(vstats, received_eth_multicast.packets);
3551 }
3552
3553 static void mlx5e_set_rx_mode(struct net_device *dev)
3554 {
3555         struct mlx5e_priv *priv = netdev_priv(dev);
3556
3557         queue_work(priv->wq, &priv->set_rx_mode_work);
3558 }
3559
3560 static int mlx5e_set_mac(struct net_device *netdev, void *addr)
3561 {
3562         struct mlx5e_priv *priv = netdev_priv(netdev);
3563         struct sockaddr *saddr = addr;
3564
3565         if (!is_valid_ether_addr(saddr->sa_data))
3566                 return -EADDRNOTAVAIL;
3567
3568         netif_addr_lock_bh(netdev);
3569         ether_addr_copy(netdev->dev_addr, saddr->sa_data);
3570         netif_addr_unlock_bh(netdev);
3571
3572         queue_work(priv->wq, &priv->set_rx_mode_work);
3573
3574         return 0;
3575 }
3576
3577 #define MLX5E_SET_FEATURE(features, feature, enable)    \
3578         do {                                            \
3579                 if (enable)                             \
3580                         *features |= feature;           \
3581                 else                                    \
3582                         *features &= ~feature;          \
3583         } while (0)
3584
3585 typedef int (*mlx5e_feature_handler)(struct net_device *netdev, bool enable);
3586
3587 static int set_feature_lro(struct net_device *netdev, bool enable)
3588 {
3589         struct mlx5e_priv *priv = netdev_priv(netdev);
3590         struct mlx5_core_dev *mdev = priv->mdev;
3591         struct mlx5e_channels new_channels = {};
3592         struct mlx5e_params *old_params;
3593         int err = 0;
3594         bool reset;
3595
3596         mutex_lock(&priv->state_lock);
3597
3598         if (enable && priv->xsk.refcnt) {
3599                 netdev_warn(netdev, "LRO is incompatible with AF_XDP (%hu XSKs are active)\n",
3600                             priv->xsk.refcnt);
3601                 err = -EINVAL;
3602                 goto out;
3603         }
3604
3605         old_params = &priv->channels.params;
3606         if (enable && !MLX5E_GET_PFLAG(old_params, MLX5E_PFLAG_RX_STRIDING_RQ)) {
3607                 netdev_warn(netdev, "can't set LRO with legacy RQ\n");
3608                 err = -EINVAL;
3609                 goto out;
3610         }
3611
3612         reset = test_bit(MLX5E_STATE_OPENED, &priv->state);
3613
3614         new_channels.params = *old_params;
3615         new_channels.params.lro_en = enable;
3616
3617         if (old_params->rq_wq_type != MLX5_WQ_TYPE_CYCLIC) {
3618                 if (mlx5e_rx_mpwqe_is_linear_skb(mdev, old_params, NULL) ==
3619                     mlx5e_rx_mpwqe_is_linear_skb(mdev, &new_channels.params, NULL))
3620                         reset = false;
3621         }
3622
3623         if (!reset) {
3624                 *old_params = new_channels.params;
3625                 err = mlx5e_modify_tirs_lro(priv);
3626                 goto out;
3627         }
3628
3629         err = mlx5e_safe_switch_channels(priv, &new_channels, mlx5e_modify_tirs_lro);
3630 out:
3631         mutex_unlock(&priv->state_lock);
3632         return err;
3633 }
3634
3635 static int set_feature_cvlan_filter(struct net_device *netdev, bool enable)
3636 {
3637         struct mlx5e_priv *priv = netdev_priv(netdev);
3638
3639         if (enable)
3640                 mlx5e_enable_cvlan_filter(priv);
3641         else
3642                 mlx5e_disable_cvlan_filter(priv);
3643
3644         return 0;
3645 }
3646
3647 #ifdef CONFIG_MLX5_ESWITCH
3648 static int set_feature_tc_num_filters(struct net_device *netdev, bool enable)
3649 {
3650         struct mlx5e_priv *priv = netdev_priv(netdev);
3651
3652         if (!enable && mlx5e_tc_num_filters(priv, MLX5_TC_FLAG(NIC_OFFLOAD))) {
3653                 netdev_err(netdev,
3654                            "Active offloaded tc filters, can't turn hw_tc_offload off\n");
3655                 return -EINVAL;
3656         }
3657
3658         return 0;
3659 }
3660 #endif
3661
3662 static int set_feature_rx_all(struct net_device *netdev, bool enable)
3663 {
3664         struct mlx5e_priv *priv = netdev_priv(netdev);
3665         struct mlx5_core_dev *mdev = priv->mdev;
3666
3667         return mlx5_set_port_fcs(mdev, !enable);
3668 }
3669
3670 static int set_feature_rx_fcs(struct net_device *netdev, bool enable)
3671 {
3672         struct mlx5e_priv *priv = netdev_priv(netdev);
3673         int err;
3674
3675         mutex_lock(&priv->state_lock);
3676
3677         priv->channels.params.scatter_fcs_en = enable;
3678         err = mlx5e_modify_channels_scatter_fcs(&priv->channels, enable);
3679         if (err)
3680                 priv->channels.params.scatter_fcs_en = !enable;
3681
3682         mutex_unlock(&priv->state_lock);
3683
3684         return err;
3685 }
3686
3687 static int set_feature_rx_vlan(struct net_device *netdev, bool enable)
3688 {
3689         struct mlx5e_priv *priv = netdev_priv(netdev);
3690         int err = 0;
3691
3692         mutex_lock(&priv->state_lock);
3693
3694         priv->channels.params.vlan_strip_disable = !enable;
3695         if (!test_bit(MLX5E_STATE_OPENED, &priv->state))
3696                 goto unlock;
3697
3698         err = mlx5e_modify_channels_vsd(&priv->channels, !enable);
3699         if (err)
3700                 priv->channels.params.vlan_strip_disable = enable;
3701
3702 unlock:
3703         mutex_unlock(&priv->state_lock);
3704
3705         return err;
3706 }
3707
3708 #ifdef CONFIG_MLX5_EN_ARFS
3709 static int set_feature_arfs(struct net_device *netdev, bool enable)
3710 {
3711         struct mlx5e_priv *priv = netdev_priv(netdev);
3712         int err;
3713
3714         if (enable)
3715                 err = mlx5e_arfs_enable(priv);
3716         else
3717                 err = mlx5e_arfs_disable(priv);
3718
3719         return err;
3720 }
3721 #endif
3722
3723 static int mlx5e_handle_feature(struct net_device *netdev,
3724                                 netdev_features_t *features,
3725                                 netdev_features_t wanted_features,
3726                                 netdev_features_t feature,
3727                                 mlx5e_feature_handler feature_handler)
3728 {
3729         netdev_features_t changes = wanted_features ^ netdev->features;
3730         bool enable = !!(wanted_features & feature);
3731         int err;
3732
3733         if (!(changes & feature))
3734                 return 0;
3735
3736         err = feature_handler(netdev, enable);
3737         if (err) {
3738                 netdev_err(netdev, "%s feature %pNF failed, err %d\n",
3739                            enable ? "Enable" : "Disable", &feature, err);
3740                 return err;
3741         }
3742
3743         MLX5E_SET_FEATURE(features, feature, enable);
3744         return 0;
3745 }
3746
3747 int mlx5e_set_features(struct net_device *netdev, netdev_features_t features)
3748 {
3749         netdev_features_t oper_features = netdev->features;
3750         int err = 0;
3751
3752 #define MLX5E_HANDLE_FEATURE(feature, handler) \
3753         mlx5e_handle_feature(netdev, &oper_features, features, feature, handler)
3754
3755         err |= MLX5E_HANDLE_FEATURE(NETIF_F_LRO, set_feature_lro);
3756         err |= MLX5E_HANDLE_FEATURE(NETIF_F_HW_VLAN_CTAG_FILTER,
3757                                     set_feature_cvlan_filter);
3758 #ifdef CONFIG_MLX5_ESWITCH
3759         err |= MLX5E_HANDLE_FEATURE(NETIF_F_HW_TC, set_feature_tc_num_filters);
3760 #endif
3761         err |= MLX5E_HANDLE_FEATURE(NETIF_F_RXALL, set_feature_rx_all);
3762         err |= MLX5E_HANDLE_FEATURE(NETIF_F_RXFCS, set_feature_rx_fcs);
3763         err |= MLX5E_HANDLE_FEATURE(NETIF_F_HW_VLAN_CTAG_RX, set_feature_rx_vlan);
3764 #ifdef CONFIG_MLX5_EN_ARFS
3765         err |= MLX5E_HANDLE_FEATURE(NETIF_F_NTUPLE, set_feature_arfs);
3766 #endif
3767
3768         if (err) {
3769                 netdev->features = oper_features;
3770                 return -EINVAL;
3771         }
3772
3773         return 0;
3774 }
3775
3776 static netdev_features_t mlx5e_fix_features(struct net_device *netdev,
3777                                             netdev_features_t features)
3778 {
3779         struct mlx5e_priv *priv = netdev_priv(netdev);
3780         struct mlx5e_params *params;
3781
3782         mutex_lock(&priv->state_lock);
3783         params = &priv->channels.params;
3784         if (!bitmap_empty(priv->fs.vlan.active_svlans, VLAN_N_VID)) {
3785                 /* HW strips the outer C-tag header, this is a problem
3786                  * for S-tag traffic.
3787                  */
3788                 features &= ~NETIF_F_HW_VLAN_CTAG_RX;
3789                 if (!params->vlan_strip_disable)
3790                         netdev_warn(netdev, "Dropping C-tag vlan stripping offload due to S-tag vlan\n");
3791         }
3792         if (!MLX5E_GET_PFLAG(params, MLX5E_PFLAG_RX_STRIDING_RQ)) {
3793                 if (features & NETIF_F_LRO) {
3794                         netdev_warn(netdev, "Disabling LRO, not supported in legacy RQ\n");
3795                         features &= ~NETIF_F_LRO;
3796                 }
3797         }
3798
3799         if (MLX5E_GET_PFLAG(params, MLX5E_PFLAG_RX_CQE_COMPRESS)) {
3800                 features &= ~NETIF_F_RXHASH;
3801                 if (netdev->features & NETIF_F_RXHASH)
3802                         netdev_warn(netdev, "Disabling rxhash, not supported when CQE compress is active\n");
3803         }
3804
3805         mutex_unlock(&priv->state_lock);
3806
3807         return features;
3808 }
3809
3810 static bool mlx5e_xsk_validate_mtu(struct net_device *netdev,
3811                                    struct mlx5e_channels *chs,
3812                                    struct mlx5e_params *new_params,
3813                                    struct mlx5_core_dev *mdev)
3814 {
3815         u16 ix;
3816
3817         for (ix = 0; ix < chs->params.num_channels; ix++) {
3818                 struct xdp_umem *umem = mlx5e_xsk_get_umem(&chs->params, chs->params.xsk, ix);
3819                 struct mlx5e_xsk_param xsk;
3820
3821                 if (!umem)
3822                         continue;
3823
3824                 mlx5e_build_xsk_param(umem, &xsk);
3825
3826                 if (!mlx5e_validate_xsk_param(new_params, &xsk, mdev)) {
3827                         u32 hr = mlx5e_get_linear_rq_headroom(new_params, &xsk);
3828                         int max_mtu_frame, max_mtu_page, max_mtu;
3829
3830                         /* Two criteria must be met:
3831                          * 1. HW MTU + all headrooms <= XSK frame size.
3832                          * 2. Size of SKBs allocated on XDP_PASS <= PAGE_SIZE.
3833                          */
3834                         max_mtu_frame = MLX5E_HW2SW_MTU(new_params, xsk.chunk_size - hr);
3835                         max_mtu_page = mlx5e_xdp_max_mtu(new_params, &xsk);
3836                         max_mtu = min(max_mtu_frame, max_mtu_page);
3837
3838                         netdev_err(netdev, "MTU %d is too big for an XSK running on channel %hu. Try MTU <= %d\n",
3839                                    new_params->sw_mtu, ix, max_mtu);
3840                         return false;
3841                 }
3842         }
3843
3844         return true;
3845 }
3846
3847 int mlx5e_change_mtu(struct net_device *netdev, int new_mtu,
3848                      change_hw_mtu_cb set_mtu_cb)
3849 {
3850         struct mlx5e_priv *priv = netdev_priv(netdev);
3851         struct mlx5e_channels new_channels = {};
3852         struct mlx5e_params *params;
3853         int err = 0;
3854         bool reset;
3855
3856         mutex_lock(&priv->state_lock);
3857
3858         params = &priv->channels.params;
3859
3860         reset = !params->lro_en;
3861         reset = reset && test_bit(MLX5E_STATE_OPENED, &priv->state);
3862
3863         new_channels.params = *params;
3864         new_channels.params.sw_mtu = new_mtu;
3865
3866         if (params->xdp_prog &&
3867             !mlx5e_rx_is_linear_skb(&new_channels.params, NULL)) {
3868                 netdev_err(netdev, "MTU(%d) > %d is not allowed while XDP enabled\n",
3869                            new_mtu, mlx5e_xdp_max_mtu(params, NULL));
3870                 err = -EINVAL;
3871                 goto out;
3872         }
3873
3874         if (priv->xsk.refcnt &&
3875             !mlx5e_xsk_validate_mtu(netdev, &priv->channels,
3876                                     &new_channels.params, priv->mdev)) {
3877                 err = -EINVAL;
3878                 goto out;
3879         }
3880
3881         if (params->rq_wq_type == MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ) {
3882                 bool is_linear = mlx5e_rx_mpwqe_is_linear_skb(priv->mdev,
3883                                                               &new_channels.params,
3884                                                               NULL);
3885                 u8 ppw_old = mlx5e_mpwqe_log_pkts_per_wqe(params, NULL);
3886                 u8 ppw_new = mlx5e_mpwqe_log_pkts_per_wqe(&new_channels.params, NULL);
3887
3888                 /* If XSK is active, XSK RQs are linear. */
3889                 is_linear |= priv->xsk.refcnt;
3890
3891                 /* Always reset in linear mode - hw_mtu is used in data path. */
3892                 reset = reset && (is_linear || (ppw_old != ppw_new));
3893         }
3894
3895         if (!reset) {
3896                 params->sw_mtu = new_mtu;
3897                 if (set_mtu_cb)
3898                         set_mtu_cb(priv);
3899                 netdev->mtu = params->sw_mtu;
3900                 goto out;
3901         }
3902
3903         err = mlx5e_safe_switch_channels(priv, &new_channels, set_mtu_cb);
3904         if (err)
3905                 goto out;
3906
3907         netdev->mtu = new_channels.params.sw_mtu;
3908
3909 out:
3910         mutex_unlock(&priv->state_lock);
3911         return err;
3912 }
3913
3914 static int mlx5e_change_nic_mtu(struct net_device *netdev, int new_mtu)
3915 {
3916         return mlx5e_change_mtu(netdev, new_mtu, mlx5e_set_dev_port_mtu);
3917 }
3918
3919 int mlx5e_hwstamp_set(struct mlx5e_priv *priv, struct ifreq *ifr)
3920 {
3921         struct hwtstamp_config config;
3922         int err;
3923
3924         if (!MLX5_CAP_GEN(priv->mdev, device_frequency_khz) ||
3925             (mlx5_clock_get_ptp_index(priv->mdev) == -1))
3926                 return -EOPNOTSUPP;
3927
3928         if (copy_from_user(&config, ifr->ifr_data, sizeof(config)))
3929                 return -EFAULT;
3930
3931         /* TX HW timestamp */
3932         switch (config.tx_type) {
3933         case HWTSTAMP_TX_OFF:
3934         case HWTSTAMP_TX_ON:
3935                 break;
3936         default:
3937                 return -ERANGE;
3938         }
3939
3940         mutex_lock(&priv->state_lock);
3941         /* RX HW timestamp */
3942         switch (config.rx_filter) {
3943         case HWTSTAMP_FILTER_NONE:
3944                 /* Reset CQE compression to Admin default */
3945                 mlx5e_modify_rx_cqe_compression_locked(priv, priv->channels.params.rx_cqe_compress_def);
3946                 break;
3947         case HWTSTAMP_FILTER_ALL:
3948         case HWTSTAMP_FILTER_SOME:
3949         case HWTSTAMP_FILTER_PTP_V1_L4_EVENT:
3950         case HWTSTAMP_FILTER_PTP_V1_L4_SYNC:
3951         case HWTSTAMP_FILTER_PTP_V1_L4_DELAY_REQ:
3952         case HWTSTAMP_FILTER_PTP_V2_L4_EVENT:
3953         case HWTSTAMP_FILTER_PTP_V2_L4_SYNC:
3954         case HWTSTAMP_FILTER_PTP_V2_L4_DELAY_REQ:
3955         case HWTSTAMP_FILTER_PTP_V2_L2_EVENT:
3956         case HWTSTAMP_FILTER_PTP_V2_L2_SYNC:
3957         case HWTSTAMP_FILTER_PTP_V2_L2_DELAY_REQ:
3958         case HWTSTAMP_FILTER_PTP_V2_EVENT:
3959         case HWTSTAMP_FILTER_PTP_V2_SYNC:
3960         case HWTSTAMP_FILTER_PTP_V2_DELAY_REQ:
3961         case HWTSTAMP_FILTER_NTP_ALL:
3962                 /* Disable CQE compression */
3963                 if (MLX5E_GET_PFLAG(&priv->channels.params, MLX5E_PFLAG_RX_CQE_COMPRESS))
3964                         netdev_warn(priv->netdev, "Disabling RX cqe compression\n");
3965                 err = mlx5e_modify_rx_cqe_compression_locked(priv, false);
3966                 if (err) {
3967                         netdev_err(priv->netdev, "Failed disabling cqe compression err=%d\n", err);
3968                         mutex_unlock(&priv->state_lock);
3969                         return err;
3970                 }
3971                 config.rx_filter = HWTSTAMP_FILTER_ALL;
3972                 break;
3973         default:
3974                 mutex_unlock(&priv->state_lock);
3975                 return -ERANGE;
3976         }
3977
3978         memcpy(&priv->tstamp, &config, sizeof(config));
3979         mutex_unlock(&priv->state_lock);
3980
3981         /* might need to fix some features */
3982         netdev_update_features(priv->netdev);
3983
3984         return copy_to_user(ifr->ifr_data, &config,
3985                             sizeof(config)) ? -EFAULT : 0;
3986 }
3987
3988 int mlx5e_hwstamp_get(struct mlx5e_priv *priv, struct ifreq *ifr)
3989 {
3990         struct hwtstamp_config *cfg = &priv->tstamp;
3991
3992         if (!MLX5_CAP_GEN(priv->mdev, device_frequency_khz))
3993                 return -EOPNOTSUPP;
3994
3995         return copy_to_user(ifr->ifr_data, cfg, sizeof(*cfg)) ? -EFAULT : 0;
3996 }
3997
3998 static int mlx5e_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
3999 {
4000         struct mlx5e_priv *priv = netdev_priv(dev);
4001
4002         switch (cmd) {
4003         case SIOCSHWTSTAMP:
4004                 return mlx5e_hwstamp_set(priv, ifr);
4005         case SIOCGHWTSTAMP:
4006                 return mlx5e_hwstamp_get(priv, ifr);
4007         default:
4008                 return -EOPNOTSUPP;
4009         }
4010 }
4011
4012 #ifdef CONFIG_MLX5_ESWITCH
4013 int mlx5e_set_vf_mac(struct net_device *dev, int vf, u8 *mac)
4014 {
4015         struct mlx5e_priv *priv = netdev_priv(dev);
4016         struct mlx5_core_dev *mdev = priv->mdev;
4017
4018         return mlx5_eswitch_set_vport_mac(mdev->priv.eswitch, vf + 1, mac);
4019 }
4020
4021 static int mlx5e_set_vf_vlan(struct net_device *dev, int vf, u16 vlan, u8 qos,
4022                              __be16 vlan_proto)
4023 {
4024         struct mlx5e_priv *priv = netdev_priv(dev);
4025         struct mlx5_core_dev *mdev = priv->mdev;
4026
4027         if (vlan_proto != htons(ETH_P_8021Q))
4028                 return -EPROTONOSUPPORT;
4029
4030         return mlx5_eswitch_set_vport_vlan(mdev->priv.eswitch, vf + 1,
4031                                            vlan, qos);
4032 }
4033
4034 static int mlx5e_set_vf_spoofchk(struct net_device *dev, int vf, bool setting)
4035 {
4036         struct mlx5e_priv *priv = netdev_priv(dev);
4037         struct mlx5_core_dev *mdev = priv->mdev;
4038
4039         return mlx5_eswitch_set_vport_spoofchk(mdev->priv.eswitch, vf + 1, setting);
4040 }
4041
4042 static int mlx5e_set_vf_trust(struct net_device *dev, int vf, bool setting)
4043 {
4044         struct mlx5e_priv *priv = netdev_priv(dev);
4045         struct mlx5_core_dev *mdev = priv->mdev;
4046
4047         return mlx5_eswitch_set_vport_trust(mdev->priv.eswitch, vf + 1, setting);
4048 }
4049
4050 int mlx5e_set_vf_rate(struct net_device *dev, int vf, int min_tx_rate,
4051                       int max_tx_rate)
4052 {
4053         struct mlx5e_priv *priv = netdev_priv(dev);
4054         struct mlx5_core_dev *mdev = priv->mdev;
4055
4056         return mlx5_eswitch_set_vport_rate(mdev->priv.eswitch, vf + 1,
4057                                            max_tx_rate, min_tx_rate);
4058 }
4059
4060 static int mlx5_vport_link2ifla(u8 esw_link)
4061 {
4062         switch (esw_link) {
4063         case MLX5_VPORT_ADMIN_STATE_DOWN:
4064                 return IFLA_VF_LINK_STATE_DISABLE;
4065         case MLX5_VPORT_ADMIN_STATE_UP:
4066                 return IFLA_VF_LINK_STATE_ENABLE;
4067         }
4068         return IFLA_VF_LINK_STATE_AUTO;
4069 }
4070
4071 static int mlx5_ifla_link2vport(u8 ifla_link)
4072 {
4073         switch (ifla_link) {
4074         case IFLA_VF_LINK_STATE_DISABLE:
4075                 return MLX5_VPORT_ADMIN_STATE_DOWN;
4076         case IFLA_VF_LINK_STATE_ENABLE:
4077                 return MLX5_VPORT_ADMIN_STATE_UP;
4078         }
4079         return MLX5_VPORT_ADMIN_STATE_AUTO;
4080 }
4081
4082 static int mlx5e_set_vf_link_state(struct net_device *dev, int vf,
4083                                    int link_state)
4084 {
4085         struct mlx5e_priv *priv = netdev_priv(dev);
4086         struct mlx5_core_dev *mdev = priv->mdev;
4087
4088         return mlx5_eswitch_set_vport_state(mdev->priv.eswitch, vf + 1,
4089                                             mlx5_ifla_link2vport(link_state));
4090 }
4091
4092 int mlx5e_get_vf_config(struct net_device *dev,
4093                         int vf, struct ifla_vf_info *ivi)
4094 {
4095         struct mlx5e_priv *priv = netdev_priv(dev);
4096         struct mlx5_core_dev *mdev = priv->mdev;
4097         int err;
4098
4099         err = mlx5_eswitch_get_vport_config(mdev->priv.eswitch, vf + 1, ivi);
4100         if (err)
4101                 return err;
4102         ivi->linkstate = mlx5_vport_link2ifla(ivi->linkstate);
4103         return 0;
4104 }
4105
4106 int mlx5e_get_vf_stats(struct net_device *dev,
4107                        int vf, struct ifla_vf_stats *vf_stats)
4108 {
4109         struct mlx5e_priv *priv = netdev_priv(dev);
4110         struct mlx5_core_dev *mdev = priv->mdev;
4111
4112         return mlx5_eswitch_get_vport_stats(mdev->priv.eswitch, vf + 1,
4113                                             vf_stats);
4114 }
4115 #endif
4116
4117 struct mlx5e_vxlan_work {
4118         struct work_struct      work;
4119         struct mlx5e_priv       *priv;
4120         u16                     port;
4121 };
4122
4123 static void mlx5e_vxlan_add_work(struct work_struct *work)
4124 {
4125         struct mlx5e_vxlan_work *vxlan_work =
4126                 container_of(work, struct mlx5e_vxlan_work, work);
4127         struct mlx5e_priv *priv = vxlan_work->priv;
4128         u16 port = vxlan_work->port;
4129
4130         mutex_lock(&priv->state_lock);
4131         mlx5_vxlan_add_port(priv->mdev->vxlan, port);
4132         mutex_unlock(&priv->state_lock);
4133
4134         kfree(vxlan_work);
4135 }
4136
4137 static void mlx5e_vxlan_del_work(struct work_struct *work)
4138 {
4139         struct mlx5e_vxlan_work *vxlan_work =
4140                 container_of(work, struct mlx5e_vxlan_work, work);
4141         struct mlx5e_priv *priv         = vxlan_work->priv;
4142         u16 port = vxlan_work->port;
4143
4144         mutex_lock(&priv->state_lock);
4145         mlx5_vxlan_del_port(priv->mdev->vxlan, port);
4146         mutex_unlock(&priv->state_lock);
4147         kfree(vxlan_work);
4148 }
4149
4150 static void mlx5e_vxlan_queue_work(struct mlx5e_priv *priv, u16 port, int add)
4151 {
4152         struct mlx5e_vxlan_work *vxlan_work;
4153
4154         vxlan_work = kmalloc(sizeof(*vxlan_work), GFP_ATOMIC);
4155         if (!vxlan_work)
4156                 return;
4157
4158         if (add)
4159                 INIT_WORK(&vxlan_work->work, mlx5e_vxlan_add_work);
4160         else
4161                 INIT_WORK(&vxlan_work->work, mlx5e_vxlan_del_work);
4162
4163         vxlan_work->priv = priv;
4164         vxlan_work->port = port;
4165         queue_work(priv->wq, &vxlan_work->work);
4166 }
4167
4168 void mlx5e_add_vxlan_port(struct net_device *netdev, struct udp_tunnel_info *ti)
4169 {
4170         struct mlx5e_priv *priv = netdev_priv(netdev);
4171
4172         if (ti->type != UDP_TUNNEL_TYPE_VXLAN)
4173                 return;
4174
4175         if (!mlx5_vxlan_allowed(priv->mdev->vxlan))
4176                 return;
4177
4178         mlx5e_vxlan_queue_work(priv, be16_to_cpu(ti->port), 1);
4179 }
4180
4181 void mlx5e_del_vxlan_port(struct net_device *netdev, struct udp_tunnel_info *ti)
4182 {
4183         struct mlx5e_priv *priv = netdev_priv(netdev);
4184
4185         if (ti->type != UDP_TUNNEL_TYPE_VXLAN)
4186                 return;
4187
4188         if (!mlx5_vxlan_allowed(priv->mdev->vxlan))
4189                 return;
4190
4191         mlx5e_vxlan_queue_work(priv, be16_to_cpu(ti->port), 0);
4192 }
4193
4194 static netdev_features_t mlx5e_tunnel_features_check(struct mlx5e_priv *priv,
4195                                                      struct sk_buff *skb,
4196                                                      netdev_features_t features)
4197 {
4198         unsigned int offset = 0;
4199         struct udphdr *udph;
4200         u8 proto;
4201         u16 port;
4202
4203         switch (vlan_get_protocol(skb)) {
4204         case htons(ETH_P_IP):
4205                 proto = ip_hdr(skb)->protocol;
4206                 break;
4207         case htons(ETH_P_IPV6):
4208                 proto = ipv6_find_hdr(skb, &offset, -1, NULL, NULL);
4209                 break;
4210         default:
4211                 goto out;
4212         }
4213
4214         switch (proto) {
4215         case IPPROTO_GRE:
4216                 return features;
4217         case IPPROTO_UDP:
4218                 udph = udp_hdr(skb);
4219                 port = be16_to_cpu(udph->dest);
4220
4221                 /* Verify if UDP port is being offloaded by HW */
4222                 if (mlx5_vxlan_lookup_port(priv->mdev->vxlan, port))
4223                         return features;
4224
4225 #if IS_ENABLED(CONFIG_GENEVE)
4226                 /* Support Geneve offload for default UDP port */
4227                 if (port == GENEVE_UDP_PORT && mlx5_geneve_tx_allowed(priv->mdev))
4228                         return features;
4229 #endif
4230         }
4231
4232 out:
4233         /* Disable CSUM and GSO if the udp dport is not offloaded by HW */
4234         return features & ~(NETIF_F_CSUM_MASK | NETIF_F_GSO_MASK);
4235 }
4236
4237 netdev_features_t mlx5e_features_check(struct sk_buff *skb,
4238                                        struct net_device *netdev,
4239                                        netdev_features_t features)
4240 {
4241         struct mlx5e_priv *priv = netdev_priv(netdev);
4242
4243         features = vlan_features_check(skb, features);
4244         features = vxlan_features_check(skb, features);
4245
4246 #ifdef CONFIG_MLX5_EN_IPSEC
4247         if (mlx5e_ipsec_feature_check(skb, netdev, features))
4248                 return features;
4249 #endif
4250
4251         /* Validate if the tunneled packet is being offloaded by HW */
4252         if (skb->encapsulation &&
4253             (features & NETIF_F_CSUM_MASK || features & NETIF_F_GSO_MASK))
4254                 return mlx5e_tunnel_features_check(priv, skb, features);
4255
4256         return features;
4257 }
4258
4259 static void mlx5e_tx_timeout_work(struct work_struct *work)
4260 {
4261         struct mlx5e_priv *priv = container_of(work, struct mlx5e_priv,
4262                                                tx_timeout_work);
4263         bool report_failed = false;
4264         int err;
4265         int i;
4266
4267         rtnl_lock();
4268         mutex_lock(&priv->state_lock);
4269
4270         if (!test_bit(MLX5E_STATE_OPENED, &priv->state))
4271                 goto unlock;
4272
4273         for (i = 0; i < priv->channels.num * priv->channels.params.num_tc; i++) {
4274                 struct netdev_queue *dev_queue =
4275                         netdev_get_tx_queue(priv->netdev, i);
4276                 struct mlx5e_txqsq *sq = priv->txq2sq[i];
4277
4278                 if (!netif_xmit_stopped(dev_queue))
4279                         continue;
4280
4281                 if (mlx5e_tx_reporter_timeout(sq))
4282                         report_failed = true;
4283         }
4284
4285         if (!report_failed)
4286                 goto unlock;
4287
4288         err = mlx5e_safe_reopen_channels(priv);
4289         if (err)
4290                 netdev_err(priv->netdev,
4291                            "mlx5e_safe_reopen_channels failed recovering from a tx_timeout, err(%d).\n",
4292                            err);
4293
4294 unlock:
4295         mutex_unlock(&priv->state_lock);
4296         rtnl_unlock();
4297 }
4298
4299 static void mlx5e_tx_timeout(struct net_device *dev)
4300 {
4301         struct mlx5e_priv *priv = netdev_priv(dev);
4302
4303         netdev_err(dev, "TX timeout detected\n");
4304         queue_work(priv->wq, &priv->tx_timeout_work);
4305 }
4306
4307 static int mlx5e_xdp_allowed(struct mlx5e_priv *priv, struct bpf_prog *prog)
4308 {
4309         struct net_device *netdev = priv->netdev;
4310         struct mlx5e_channels new_channels = {};
4311
4312         if (priv->channels.params.lro_en) {
4313                 netdev_warn(netdev, "can't set XDP while LRO is on, disable LRO first\n");
4314                 return -EINVAL;
4315         }
4316
4317         if (MLX5_IPSEC_DEV(priv->mdev)) {
4318                 netdev_warn(netdev, "can't set XDP with IPSec offload\n");
4319                 return -EINVAL;
4320         }
4321
4322         new_channels.params = priv->channels.params;
4323         new_channels.params.xdp_prog = prog;
4324
4325         /* No XSK params: AF_XDP can't be enabled yet at the point of setting
4326          * the XDP program.
4327          */
4328         if (!mlx5e_rx_is_linear_skb(&new_channels.params, NULL)) {
4329                 netdev_warn(netdev, "XDP is not allowed with MTU(%d) > %d\n",
4330                             new_channels.params.sw_mtu,
4331                             mlx5e_xdp_max_mtu(&new_channels.params, NULL));
4332                 return -EINVAL;
4333         }
4334
4335         return 0;
4336 }
4337
4338 static int mlx5e_xdp_update_state(struct mlx5e_priv *priv)
4339 {
4340         if (priv->channels.params.xdp_prog)
4341                 mlx5e_xdp_set_open(priv);
4342         else
4343                 mlx5e_xdp_set_closed(priv);
4344
4345         return 0;
4346 }
4347
4348 static int mlx5e_xdp_set(struct net_device *netdev, struct bpf_prog *prog)
4349 {
4350         struct mlx5e_priv *priv = netdev_priv(netdev);
4351         struct bpf_prog *old_prog;
4352         bool reset, was_opened;
4353         int err = 0;
4354         int i;
4355
4356         mutex_lock(&priv->state_lock);
4357
4358         if (prog) {
4359                 err = mlx5e_xdp_allowed(priv, prog);
4360                 if (err)
4361                         goto unlock;
4362         }
4363
4364         was_opened = test_bit(MLX5E_STATE_OPENED, &priv->state);
4365         /* no need for full reset when exchanging programs */
4366         reset = (!priv->channels.params.xdp_prog || !prog);
4367
4368         if (was_opened && !reset) {
4369                 /* num_channels is invariant here, so we can take the
4370                  * batched reference right upfront.
4371                  */
4372                 prog = bpf_prog_add(prog, priv->channels.num);
4373                 if (IS_ERR(prog)) {
4374                         err = PTR_ERR(prog);
4375                         goto unlock;
4376                 }
4377         }
4378
4379         if (was_opened && reset) {
4380                 struct mlx5e_channels new_channels = {};
4381
4382                 new_channels.params = priv->channels.params;
4383                 new_channels.params.xdp_prog = prog;
4384                 mlx5e_set_rq_type(priv->mdev, &new_channels.params);
4385                 old_prog = priv->channels.params.xdp_prog;
4386
4387                 err = mlx5e_safe_switch_channels(priv, &new_channels, mlx5e_xdp_update_state);
4388                 if (err)
4389                         goto unlock;
4390         } else {
4391                 /* exchange programs, extra prog reference we got from caller
4392                  * as long as we don't fail from this point onwards.
4393                  */
4394                 old_prog = xchg(&priv->channels.params.xdp_prog, prog);
4395         }
4396
4397         if (old_prog)
4398                 bpf_prog_put(old_prog);
4399
4400         if (!was_opened && reset) /* change RQ type according to priv->xdp_prog */
4401                 mlx5e_set_rq_type(priv->mdev, &priv->channels.params);
4402
4403         if (!was_opened || reset)
4404                 goto unlock;
4405
4406         /* exchanging programs w/o reset, we update ref counts on behalf
4407          * of the channels RQs here.
4408          */
4409         for (i = 0; i < priv->channels.num; i++) {
4410                 struct mlx5e_channel *c = priv->channels.c[i];
4411                 bool xsk_open = test_bit(MLX5E_CHANNEL_STATE_XSK, c->state);
4412
4413                 clear_bit(MLX5E_RQ_STATE_ENABLED, &c->rq.state);
4414                 if (xsk_open)
4415                         clear_bit(MLX5E_RQ_STATE_ENABLED, &c->xskrq.state);
4416                 napi_synchronize(&c->napi);
4417                 /* prevent mlx5e_poll_rx_cq from accessing rq->xdp_prog */
4418
4419                 old_prog = xchg(&c->rq.xdp_prog, prog);
4420                 if (old_prog)
4421                         bpf_prog_put(old_prog);
4422
4423                 if (xsk_open) {
4424                         old_prog = xchg(&c->xskrq.xdp_prog, prog);
4425                         if (old_prog)
4426                                 bpf_prog_put(old_prog);
4427                 }
4428
4429                 set_bit(MLX5E_RQ_STATE_ENABLED, &c->rq.state);
4430                 if (xsk_open)
4431                         set_bit(MLX5E_RQ_STATE_ENABLED, &c->xskrq.state);
4432                 /* napi_schedule in case we have missed anything */
4433                 napi_schedule(&c->napi);
4434         }
4435
4436 unlock:
4437         mutex_unlock(&priv->state_lock);
4438         return err;
4439 }
4440
4441 static u32 mlx5e_xdp_query(struct net_device *dev)
4442 {
4443         struct mlx5e_priv *priv = netdev_priv(dev);
4444         const struct bpf_prog *xdp_prog;
4445         u32 prog_id = 0;
4446
4447         mutex_lock(&priv->state_lock);
4448         xdp_prog = priv->channels.params.xdp_prog;
4449         if (xdp_prog)
4450                 prog_id = xdp_prog->aux->id;
4451         mutex_unlock(&priv->state_lock);
4452
4453         return prog_id;
4454 }
4455
4456 static int mlx5e_xdp(struct net_device *dev, struct netdev_bpf *xdp)
4457 {
4458         switch (xdp->command) {
4459         case XDP_SETUP_PROG:
4460                 return mlx5e_xdp_set(dev, xdp->prog);
4461         case XDP_QUERY_PROG:
4462                 xdp->prog_id = mlx5e_xdp_query(dev);
4463                 return 0;
4464         case XDP_SETUP_XSK_UMEM:
4465                 return mlx5e_xsk_setup_umem(dev, xdp->xsk.umem,
4466                                             xdp->xsk.queue_id);
4467         default:
4468                 return -EINVAL;
4469         }
4470 }
4471
4472 #ifdef CONFIG_MLX5_ESWITCH
4473 static int mlx5e_bridge_getlink(struct sk_buff *skb, u32 pid, u32 seq,
4474                                 struct net_device *dev, u32 filter_mask,
4475                                 int nlflags)
4476 {
4477         struct mlx5e_priv *priv = netdev_priv(dev);
4478         struct mlx5_core_dev *mdev = priv->mdev;
4479         u8 mode, setting;
4480         int err;
4481
4482         err = mlx5_eswitch_get_vepa(mdev->priv.eswitch, &setting);
4483         if (err)
4484                 return err;
4485         mode = setting ? BRIDGE_MODE_VEPA : BRIDGE_MODE_VEB;
4486         return ndo_dflt_bridge_getlink(skb, pid, seq, dev,
4487                                        mode,
4488                                        0, 0, nlflags, filter_mask, NULL);
4489 }
4490
4491 static int mlx5e_bridge_setlink(struct net_device *dev, struct nlmsghdr *nlh,
4492                                 u16 flags, struct netlink_ext_ack *extack)
4493 {
4494         struct mlx5e_priv *priv = netdev_priv(dev);
4495         struct mlx5_core_dev *mdev = priv->mdev;
4496         struct nlattr *attr, *br_spec;
4497         u16 mode = BRIDGE_MODE_UNDEF;
4498         u8 setting;
4499         int rem;
4500
4501         br_spec = nlmsg_find_attr(nlh, sizeof(struct ifinfomsg), IFLA_AF_SPEC);
4502         if (!br_spec)
4503                 return -EINVAL;
4504
4505         nla_for_each_nested(attr, br_spec, rem) {
4506                 if (nla_type(attr) != IFLA_BRIDGE_MODE)
4507                         continue;
4508
4509                 if (nla_len(attr) < sizeof(mode))
4510                         return -EINVAL;
4511
4512                 mode = nla_get_u16(attr);
4513                 if (mode > BRIDGE_MODE_VEPA)
4514                         return -EINVAL;
4515
4516                 break;
4517         }
4518
4519         if (mode == BRIDGE_MODE_UNDEF)
4520                 return -EINVAL;
4521
4522         setting = (mode == BRIDGE_MODE_VEPA) ?  1 : 0;
4523         return mlx5_eswitch_set_vepa(mdev->priv.eswitch, setting);
4524 }
4525 #endif
4526
4527 const struct net_device_ops mlx5e_netdev_ops = {
4528         .ndo_open                = mlx5e_open,
4529         .ndo_stop                = mlx5e_close,
4530         .ndo_start_xmit          = mlx5e_xmit,
4531         .ndo_setup_tc            = mlx5e_setup_tc,
4532         .ndo_select_queue        = mlx5e_select_queue,
4533         .ndo_get_stats64         = mlx5e_get_stats,
4534         .ndo_set_rx_mode         = mlx5e_set_rx_mode,
4535         .ndo_set_mac_address     = mlx5e_set_mac,
4536         .ndo_vlan_rx_add_vid     = mlx5e_vlan_rx_add_vid,
4537         .ndo_vlan_rx_kill_vid    = mlx5e_vlan_rx_kill_vid,
4538         .ndo_set_features        = mlx5e_set_features,
4539         .ndo_fix_features        = mlx5e_fix_features,
4540         .ndo_change_mtu          = mlx5e_change_nic_mtu,
4541         .ndo_do_ioctl            = mlx5e_ioctl,
4542         .ndo_set_tx_maxrate      = mlx5e_set_tx_maxrate,
4543         .ndo_udp_tunnel_add      = mlx5e_add_vxlan_port,
4544         .ndo_udp_tunnel_del      = mlx5e_del_vxlan_port,
4545         .ndo_features_check      = mlx5e_features_check,
4546         .ndo_tx_timeout          = mlx5e_tx_timeout,
4547         .ndo_bpf                 = mlx5e_xdp,
4548         .ndo_xdp_xmit            = mlx5e_xdp_xmit,
4549         .ndo_xsk_async_xmit      = mlx5e_xsk_async_xmit,
4550 #ifdef CONFIG_MLX5_EN_ARFS
4551         .ndo_rx_flow_steer       = mlx5e_rx_flow_steer,
4552 #endif
4553 #ifdef CONFIG_MLX5_ESWITCH
4554         .ndo_bridge_setlink      = mlx5e_bridge_setlink,
4555         .ndo_bridge_getlink      = mlx5e_bridge_getlink,
4556
4557         /* SRIOV E-Switch NDOs */
4558         .ndo_set_vf_mac          = mlx5e_set_vf_mac,
4559         .ndo_set_vf_vlan         = mlx5e_set_vf_vlan,
4560         .ndo_set_vf_spoofchk     = mlx5e_set_vf_spoofchk,
4561         .ndo_set_vf_trust        = mlx5e_set_vf_trust,
4562         .ndo_set_vf_rate         = mlx5e_set_vf_rate,
4563         .ndo_get_vf_config       = mlx5e_get_vf_config,
4564         .ndo_set_vf_link_state   = mlx5e_set_vf_link_state,
4565         .ndo_get_vf_stats        = mlx5e_get_vf_stats,
4566 #endif
4567 };
4568
4569 static int mlx5e_check_required_hca_cap(struct mlx5_core_dev *mdev)
4570 {
4571         if (MLX5_CAP_GEN(mdev, port_type) != MLX5_CAP_PORT_TYPE_ETH)
4572                 return -EOPNOTSUPP;
4573         if (!MLX5_CAP_GEN(mdev, eth_net_offloads) ||
4574             !MLX5_CAP_GEN(mdev, nic_flow_table) ||
4575             !MLX5_CAP_ETH(mdev, csum_cap) ||
4576             !MLX5_CAP_ETH(mdev, max_lso_cap) ||
4577             !MLX5_CAP_ETH(mdev, vlan_cap) ||
4578             !MLX5_CAP_ETH(mdev, rss_ind_tbl_cap) ||
4579             MLX5_CAP_FLOWTABLE(mdev,
4580                                flow_table_properties_nic_receive.max_ft_level)
4581                                < 3) {
4582                 mlx5_core_warn(mdev,
4583                                "Not creating net device, some required device capabilities are missing\n");
4584                 return -EOPNOTSUPP;
4585         }
4586         if (!MLX5_CAP_ETH(mdev, self_lb_en_modifiable))
4587                 mlx5_core_warn(mdev, "Self loop back prevention is not supported\n");
4588         if (!MLX5_CAP_GEN(mdev, cq_moderation))
4589                 mlx5_core_warn(mdev, "CQ moderation is not supported\n");
4590
4591         return 0;
4592 }
4593
4594 void mlx5e_build_default_indir_rqt(u32 *indirection_rqt, int len,
4595                                    int num_channels)
4596 {
4597         int i;
4598
4599         for (i = 0; i < len; i++)
4600                 indirection_rqt[i] = i % num_channels;
4601 }
4602
4603 static bool slow_pci_heuristic(struct mlx5_core_dev *mdev)
4604 {
4605         u32 link_speed = 0;
4606         u32 pci_bw = 0;
4607
4608         mlx5e_port_max_linkspeed(mdev, &link_speed);
4609         pci_bw = pcie_bandwidth_available(mdev->pdev, NULL, NULL, NULL);
4610         mlx5_core_dbg_once(mdev, "Max link speed = %d, PCI BW = %d\n",
4611                            link_speed, pci_bw);
4612
4613 #define MLX5E_SLOW_PCI_RATIO (2)
4614
4615         return link_speed && pci_bw &&
4616                 link_speed > MLX5E_SLOW_PCI_RATIO * pci_bw;
4617 }
4618
4619 static struct dim_cq_moder mlx5e_get_def_tx_moderation(u8 cq_period_mode)
4620 {
4621         struct dim_cq_moder moder;
4622
4623         moder.cq_period_mode = cq_period_mode;
4624         moder.pkts = MLX5E_PARAMS_DEFAULT_TX_CQ_MODERATION_PKTS;
4625         moder.usec = MLX5E_PARAMS_DEFAULT_TX_CQ_MODERATION_USEC;
4626         if (cq_period_mode == MLX5_CQ_PERIOD_MODE_START_FROM_CQE)
4627                 moder.usec = MLX5E_PARAMS_DEFAULT_TX_CQ_MODERATION_USEC_FROM_CQE;
4628
4629         return moder;
4630 }
4631
4632 static struct dim_cq_moder mlx5e_get_def_rx_moderation(u8 cq_period_mode)
4633 {
4634         struct dim_cq_moder moder;
4635
4636         moder.cq_period_mode = cq_period_mode;
4637         moder.pkts = MLX5E_PARAMS_DEFAULT_RX_CQ_MODERATION_PKTS;
4638         moder.usec = MLX5E_PARAMS_DEFAULT_RX_CQ_MODERATION_USEC;
4639         if (cq_period_mode == MLX5_CQ_PERIOD_MODE_START_FROM_CQE)
4640                 moder.usec = MLX5E_PARAMS_DEFAULT_RX_CQ_MODERATION_USEC_FROM_CQE;
4641
4642         return moder;
4643 }
4644
4645 static u8 mlx5_to_net_dim_cq_period_mode(u8 cq_period_mode)
4646 {
4647         return cq_period_mode == MLX5_CQ_PERIOD_MODE_START_FROM_CQE ?
4648                 DIM_CQ_PERIOD_MODE_START_FROM_CQE :
4649                 DIM_CQ_PERIOD_MODE_START_FROM_EQE;
4650 }
4651
4652 void mlx5e_set_tx_cq_mode_params(struct mlx5e_params *params, u8 cq_period_mode)
4653 {
4654         if (params->tx_dim_enabled) {
4655                 u8 dim_period_mode = mlx5_to_net_dim_cq_period_mode(cq_period_mode);
4656
4657                 params->tx_cq_moderation = net_dim_get_def_tx_moderation(dim_period_mode);
4658         } else {
4659                 params->tx_cq_moderation = mlx5e_get_def_tx_moderation(cq_period_mode);
4660         }
4661
4662         MLX5E_SET_PFLAG(params, MLX5E_PFLAG_TX_CQE_BASED_MODER,
4663                         params->tx_cq_moderation.cq_period_mode ==
4664                                 MLX5_CQ_PERIOD_MODE_START_FROM_CQE);
4665 }
4666
4667 void mlx5e_set_rx_cq_mode_params(struct mlx5e_params *params, u8 cq_period_mode)
4668 {
4669         if (params->rx_dim_enabled) {
4670                 u8 dim_period_mode = mlx5_to_net_dim_cq_period_mode(cq_period_mode);
4671
4672                 params->rx_cq_moderation = net_dim_get_def_rx_moderation(dim_period_mode);
4673         } else {
4674                 params->rx_cq_moderation = mlx5e_get_def_rx_moderation(cq_period_mode);
4675         }
4676
4677         MLX5E_SET_PFLAG(params, MLX5E_PFLAG_RX_CQE_BASED_MODER,
4678                         params->rx_cq_moderation.cq_period_mode ==
4679                                 MLX5_CQ_PERIOD_MODE_START_FROM_CQE);
4680 }
4681
4682 static u32 mlx5e_choose_lro_timeout(struct mlx5_core_dev *mdev, u32 wanted_timeout)
4683 {
4684         int i;
4685
4686         /* The supported periods are organized in ascending order */
4687         for (i = 0; i < MLX5E_LRO_TIMEOUT_ARR_SIZE - 1; i++)
4688                 if (MLX5_CAP_ETH(mdev, lro_timer_supported_periods[i]) >= wanted_timeout)
4689                         break;
4690
4691         return MLX5_CAP_ETH(mdev, lro_timer_supported_periods[i]);
4692 }
4693
4694 void mlx5e_build_rq_params(struct mlx5_core_dev *mdev,
4695                            struct mlx5e_params *params)
4696 {
4697         /* Prefer Striding RQ, unless any of the following holds:
4698          * - Striding RQ configuration is not possible/supported.
4699          * - Slow PCI heuristic.
4700          * - Legacy RQ would use linear SKB while Striding RQ would use non-linear.
4701          *
4702          * No XSK params: checking the availability of striding RQ in general.
4703          */
4704         if (!slow_pci_heuristic(mdev) &&
4705             mlx5e_striding_rq_possible(mdev, params) &&
4706             (mlx5e_rx_mpwqe_is_linear_skb(mdev, params, NULL) ||
4707              !mlx5e_rx_is_linear_skb(params, NULL)))
4708                 MLX5E_SET_PFLAG(params, MLX5E_PFLAG_RX_STRIDING_RQ, true);
4709         mlx5e_set_rq_type(mdev, params);
4710         mlx5e_init_rq_type_params(mdev, params);
4711 }
4712
4713 void mlx5e_build_rss_params(struct mlx5e_rss_params *rss_params,
4714                             u16 num_channels)
4715 {
4716         enum mlx5e_traffic_types tt;
4717
4718         rss_params->hfunc = ETH_RSS_HASH_TOP;
4719         netdev_rss_key_fill(rss_params->toeplitz_hash_key,
4720                             sizeof(rss_params->toeplitz_hash_key));
4721         mlx5e_build_default_indir_rqt(rss_params->indirection_rqt,
4722                                       MLX5E_INDIR_RQT_SIZE, num_channels);
4723         for (tt = 0; tt < MLX5E_NUM_INDIR_TIRS; tt++)
4724                 rss_params->rx_hash_fields[tt] =
4725                         tirc_default_config[tt].rx_hash_fields;
4726 }
4727
4728 void mlx5e_build_nic_params(struct mlx5_core_dev *mdev,
4729                             struct mlx5e_xsk *xsk,
4730                             struct mlx5e_rss_params *rss_params,
4731                             struct mlx5e_params *params,
4732                             u16 max_channels, u16 mtu)
4733 {
4734         u8 rx_cq_period_mode;
4735
4736         params->sw_mtu = mtu;
4737         params->hard_mtu = MLX5E_ETH_HARD_MTU;
4738         params->num_channels = max_channels;
4739         params->num_tc       = 1;
4740
4741         /* SQ */
4742         params->log_sq_size = is_kdump_kernel() ?
4743                 MLX5E_PARAMS_MINIMUM_LOG_SQ_SIZE :
4744                 MLX5E_PARAMS_DEFAULT_LOG_SQ_SIZE;
4745
4746         /* XDP SQ */
4747         MLX5E_SET_PFLAG(params, MLX5E_PFLAG_XDP_TX_MPWQE,
4748                         MLX5_CAP_ETH(mdev, enhanced_multi_pkt_send_wqe));
4749
4750         /* set CQE compression */
4751         params->rx_cqe_compress_def = false;
4752         if (MLX5_CAP_GEN(mdev, cqe_compression) &&
4753             MLX5_CAP_GEN(mdev, vport_group_manager))
4754                 params->rx_cqe_compress_def = slow_pci_heuristic(mdev);
4755
4756         MLX5E_SET_PFLAG(params, MLX5E_PFLAG_RX_CQE_COMPRESS, params->rx_cqe_compress_def);
4757         MLX5E_SET_PFLAG(params, MLX5E_PFLAG_RX_NO_CSUM_COMPLETE, false);
4758
4759         /* RQ */
4760         mlx5e_build_rq_params(mdev, params);
4761
4762         /* HW LRO */
4763
4764         /* TODO: && MLX5_CAP_ETH(mdev, lro_cap) */
4765         if (params->rq_wq_type == MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ) {
4766                 /* No XSK params: checking the availability of striding RQ in general. */
4767                 if (!mlx5e_rx_mpwqe_is_linear_skb(mdev, params, NULL))
4768                         params->lro_en = !slow_pci_heuristic(mdev);
4769         }
4770         params->lro_timeout = mlx5e_choose_lro_timeout(mdev, MLX5E_DEFAULT_LRO_TIMEOUT);
4771
4772         /* CQ moderation params */
4773         rx_cq_period_mode = MLX5_CAP_GEN(mdev, cq_period_start_from_cqe) ?
4774                         MLX5_CQ_PERIOD_MODE_START_FROM_CQE :
4775                         MLX5_CQ_PERIOD_MODE_START_FROM_EQE;
4776         params->rx_dim_enabled = MLX5_CAP_GEN(mdev, cq_moderation);
4777         params->tx_dim_enabled = MLX5_CAP_GEN(mdev, cq_moderation);
4778         mlx5e_set_rx_cq_mode_params(params, rx_cq_period_mode);
4779         mlx5e_set_tx_cq_mode_params(params, MLX5_CQ_PERIOD_MODE_START_FROM_EQE);
4780
4781         /* TX inline */
4782         mlx5_query_min_inline(mdev, &params->tx_min_inline_mode);
4783
4784         /* RSS */
4785         mlx5e_build_rss_params(rss_params, params->num_channels);
4786         params->tunneled_offload_en =
4787                 mlx5e_tunnel_inner_ft_supported(mdev);
4788
4789         /* AF_XDP */
4790         params->xsk = xsk;
4791 }
4792
4793 static void mlx5e_set_netdev_dev_addr(struct net_device *netdev)
4794 {
4795         struct mlx5e_priv *priv = netdev_priv(netdev);
4796
4797         mlx5_query_mac_address(priv->mdev, netdev->dev_addr);
4798         if (is_zero_ether_addr(netdev->dev_addr) &&
4799             !MLX5_CAP_GEN(priv->mdev, vport_group_manager)) {
4800                 eth_hw_addr_random(netdev);
4801                 mlx5_core_info(priv->mdev, "Assigned random MAC address %pM\n", netdev->dev_addr);
4802         }
4803 }
4804
4805 static void mlx5e_build_nic_netdev(struct net_device *netdev)
4806 {
4807         struct mlx5e_priv *priv = netdev_priv(netdev);
4808         struct mlx5_core_dev *mdev = priv->mdev;
4809         bool fcs_supported;
4810         bool fcs_enabled;
4811
4812         SET_NETDEV_DEV(netdev, mdev->device);
4813
4814         netdev->netdev_ops = &mlx5e_netdev_ops;
4815
4816 #ifdef CONFIG_MLX5_CORE_EN_DCB
4817         if (MLX5_CAP_GEN(mdev, vport_group_manager) && MLX5_CAP_GEN(mdev, qos))
4818                 netdev->dcbnl_ops = &mlx5e_dcbnl_ops;
4819 #endif
4820
4821         netdev->watchdog_timeo    = 15 * HZ;
4822
4823         netdev->ethtool_ops       = &mlx5e_ethtool_ops;
4824
4825         netdev->vlan_features    |= NETIF_F_SG;
4826         netdev->vlan_features    |= NETIF_F_HW_CSUM;
4827         netdev->vlan_features    |= NETIF_F_GRO;
4828         netdev->vlan_features    |= NETIF_F_TSO;
4829         netdev->vlan_features    |= NETIF_F_TSO6;
4830         netdev->vlan_features    |= NETIF_F_RXCSUM;
4831         netdev->vlan_features    |= NETIF_F_RXHASH;
4832
4833         netdev->mpls_features    |= NETIF_F_SG;
4834         netdev->mpls_features    |= NETIF_F_HW_CSUM;
4835         netdev->mpls_features    |= NETIF_F_TSO;
4836         netdev->mpls_features    |= NETIF_F_TSO6;
4837
4838         netdev->hw_enc_features  |= NETIF_F_HW_VLAN_CTAG_TX;
4839         netdev->hw_enc_features  |= NETIF_F_HW_VLAN_CTAG_RX;
4840
4841         if (!!MLX5_CAP_ETH(mdev, lro_cap) &&
4842             mlx5e_check_fragmented_striding_rq_cap(mdev))
4843                 netdev->vlan_features    |= NETIF_F_LRO;
4844
4845         netdev->hw_features       = netdev->vlan_features;
4846         netdev->hw_features      |= NETIF_F_HW_VLAN_CTAG_TX;
4847         netdev->hw_features      |= NETIF_F_HW_VLAN_CTAG_RX;
4848         netdev->hw_features      |= NETIF_F_HW_VLAN_CTAG_FILTER;
4849         netdev->hw_features      |= NETIF_F_HW_VLAN_STAG_TX;
4850
4851         if (mlx5_vxlan_allowed(mdev->vxlan) || mlx5_geneve_tx_allowed(mdev) ||
4852             MLX5_CAP_ETH(mdev, tunnel_stateless_gre)) {
4853                 netdev->hw_enc_features |= NETIF_F_HW_CSUM;
4854                 netdev->hw_enc_features |= NETIF_F_TSO;
4855                 netdev->hw_enc_features |= NETIF_F_TSO6;
4856                 netdev->hw_enc_features |= NETIF_F_GSO_PARTIAL;
4857         }
4858
4859         if (mlx5_vxlan_allowed(mdev->vxlan) || mlx5_geneve_tx_allowed(mdev)) {
4860                 netdev->hw_features     |= NETIF_F_GSO_UDP_TUNNEL |
4861                                            NETIF_F_GSO_UDP_TUNNEL_CSUM;
4862                 netdev->hw_enc_features |= NETIF_F_GSO_UDP_TUNNEL |
4863                                            NETIF_F_GSO_UDP_TUNNEL_CSUM;
4864                 netdev->gso_partial_features = NETIF_F_GSO_UDP_TUNNEL_CSUM;
4865         }
4866
4867         if (MLX5_CAP_ETH(mdev, tunnel_stateless_gre)) {
4868                 netdev->hw_features     |= NETIF_F_GSO_GRE |
4869                                            NETIF_F_GSO_GRE_CSUM;
4870                 netdev->hw_enc_features |= NETIF_F_GSO_GRE |
4871                                            NETIF_F_GSO_GRE_CSUM;
4872                 netdev->gso_partial_features |= NETIF_F_GSO_GRE |
4873                                                 NETIF_F_GSO_GRE_CSUM;
4874         }
4875
4876         netdev->hw_features                      |= NETIF_F_GSO_PARTIAL;
4877         netdev->gso_partial_features             |= NETIF_F_GSO_UDP_L4;
4878         netdev->hw_features                      |= NETIF_F_GSO_UDP_L4;
4879         netdev->features                         |= NETIF_F_GSO_UDP_L4;
4880
4881         mlx5_query_port_fcs(mdev, &fcs_supported, &fcs_enabled);
4882
4883         if (fcs_supported)
4884                 netdev->hw_features |= NETIF_F_RXALL;
4885
4886         if (MLX5_CAP_ETH(mdev, scatter_fcs))
4887                 netdev->hw_features |= NETIF_F_RXFCS;
4888
4889         netdev->features          = netdev->hw_features;
4890         if (!priv->channels.params.lro_en)
4891                 netdev->features  &= ~NETIF_F_LRO;
4892
4893         if (fcs_enabled)
4894                 netdev->features  &= ~NETIF_F_RXALL;
4895
4896         if (!priv->channels.params.scatter_fcs_en)
4897                 netdev->features  &= ~NETIF_F_RXFCS;
4898
4899         /* prefere CQE compression over rxhash */
4900         if (MLX5E_GET_PFLAG(&priv->channels.params, MLX5E_PFLAG_RX_CQE_COMPRESS))
4901                 netdev->features &= ~NETIF_F_RXHASH;
4902
4903 #define FT_CAP(f) MLX5_CAP_FLOWTABLE(mdev, flow_table_properties_nic_receive.f)
4904         if (FT_CAP(flow_modify_en) &&
4905             FT_CAP(modify_root) &&
4906             FT_CAP(identified_miss_table_mode) &&
4907             FT_CAP(flow_table_modify)) {
4908 #ifdef CONFIG_MLX5_ESWITCH
4909                 netdev->hw_features      |= NETIF_F_HW_TC;
4910 #endif
4911 #ifdef CONFIG_MLX5_EN_ARFS
4912                 netdev->hw_features      |= NETIF_F_NTUPLE;
4913 #endif
4914         }
4915
4916         netdev->features         |= NETIF_F_HIGHDMA;
4917         netdev->features         |= NETIF_F_HW_VLAN_STAG_FILTER;
4918
4919         netdev->priv_flags       |= IFF_UNICAST_FLT;
4920
4921         mlx5e_set_netdev_dev_addr(netdev);
4922         mlx5e_ipsec_build_netdev(priv);
4923         mlx5e_tls_build_netdev(priv);
4924 }
4925
4926 void mlx5e_create_q_counters(struct mlx5e_priv *priv)
4927 {
4928         struct mlx5_core_dev *mdev = priv->mdev;
4929         int err;
4930
4931         err = mlx5_core_alloc_q_counter(mdev, &priv->q_counter);
4932         if (err) {
4933                 mlx5_core_warn(mdev, "alloc queue counter failed, %d\n", err);
4934                 priv->q_counter = 0;
4935         }
4936
4937         err = mlx5_core_alloc_q_counter(mdev, &priv->drop_rq_q_counter);
4938         if (err) {
4939                 mlx5_core_warn(mdev, "alloc drop RQ counter failed, %d\n", err);
4940                 priv->drop_rq_q_counter = 0;
4941         }
4942 }
4943
4944 void mlx5e_destroy_q_counters(struct mlx5e_priv *priv)
4945 {
4946         if (priv->q_counter)
4947                 mlx5_core_dealloc_q_counter(priv->mdev, priv->q_counter);
4948
4949         if (priv->drop_rq_q_counter)
4950                 mlx5_core_dealloc_q_counter(priv->mdev, priv->drop_rq_q_counter);
4951 }
4952
4953 static int mlx5e_nic_init(struct mlx5_core_dev *mdev,
4954                           struct net_device *netdev,
4955                           const struct mlx5e_profile *profile,
4956                           void *ppriv)
4957 {
4958         struct mlx5e_priv *priv = netdev_priv(netdev);
4959         struct mlx5e_rss_params *rss = &priv->rss_params;
4960         int err;
4961
4962         err = mlx5e_netdev_init(netdev, priv, mdev, profile, ppriv);
4963         if (err)
4964                 return err;
4965
4966         mlx5e_build_nic_params(mdev, &priv->xsk, rss, &priv->channels.params,
4967                                mlx5e_get_netdev_max_channels(netdev),
4968                                netdev->mtu);
4969
4970         mlx5e_timestamp_init(priv);
4971
4972         err = mlx5e_ipsec_init(priv);
4973         if (err)
4974                 mlx5_core_err(mdev, "IPSec initialization failed, %d\n", err);
4975         err = mlx5e_tls_init(priv);
4976         if (err)
4977                 mlx5_core_err(mdev, "TLS initialization failed, %d\n", err);
4978         mlx5e_build_nic_netdev(netdev);
4979         mlx5e_build_tc2txq_maps(priv);
4980
4981         return 0;
4982 }
4983
4984 static void mlx5e_nic_cleanup(struct mlx5e_priv *priv)
4985 {
4986         mlx5e_tls_cleanup(priv);
4987         mlx5e_ipsec_cleanup(priv);
4988         mlx5e_netdev_cleanup(priv->netdev, priv);
4989 }
4990
4991 static int mlx5e_init_nic_rx(struct mlx5e_priv *priv)
4992 {
4993         struct mlx5_core_dev *mdev = priv->mdev;
4994         int err;
4995
4996         mlx5e_create_q_counters(priv);
4997
4998         err = mlx5e_open_drop_rq(priv, &priv->drop_rq);
4999         if (err) {
5000                 mlx5_core_err(mdev, "open drop rq failed, %d\n", err);
5001                 goto err_destroy_q_counters;
5002         }
5003
5004         err = mlx5e_create_indirect_rqt(priv);
5005         if (err)
5006                 goto err_close_drop_rq;
5007
5008         err = mlx5e_create_direct_rqts(priv, priv->direct_tir);
5009         if (err)
5010                 goto err_destroy_indirect_rqts;
5011
5012         err = mlx5e_create_indirect_tirs(priv, true);
5013         if (err)
5014                 goto err_destroy_direct_rqts;
5015
5016         err = mlx5e_create_direct_tirs(priv, priv->direct_tir);
5017         if (err)
5018                 goto err_destroy_indirect_tirs;
5019
5020         err = mlx5e_create_direct_rqts(priv, priv->xsk_tir);
5021         if (unlikely(err))
5022                 goto err_destroy_direct_tirs;
5023
5024         err = mlx5e_create_direct_tirs(priv, priv->xsk_tir);
5025         if (unlikely(err))
5026                 goto err_destroy_xsk_rqts;
5027
5028         err = mlx5e_create_flow_steering(priv);
5029         if (err) {
5030                 mlx5_core_warn(mdev, "create flow steering failed, %d\n", err);
5031                 goto err_destroy_xsk_tirs;
5032         }
5033
5034         err = mlx5e_tc_nic_init(priv);
5035         if (err)
5036                 goto err_destroy_flow_steering;
5037
5038         return 0;
5039
5040 err_destroy_flow_steering:
5041         mlx5e_destroy_flow_steering(priv);
5042 err_destroy_xsk_tirs:
5043         mlx5e_destroy_direct_tirs(priv, priv->xsk_tir);
5044 err_destroy_xsk_rqts:
5045         mlx5e_destroy_direct_rqts(priv, priv->xsk_tir);
5046 err_destroy_direct_tirs:
5047         mlx5e_destroy_direct_tirs(priv, priv->direct_tir);
5048 err_destroy_indirect_tirs:
5049         mlx5e_destroy_indirect_tirs(priv, true);
5050 err_destroy_direct_rqts:
5051         mlx5e_destroy_direct_rqts(priv, priv->direct_tir);
5052 err_destroy_indirect_rqts:
5053         mlx5e_destroy_rqt(priv, &priv->indir_rqt);
5054 err_close_drop_rq:
5055         mlx5e_close_drop_rq(&priv->drop_rq);
5056 err_destroy_q_counters:
5057         mlx5e_destroy_q_counters(priv);
5058         return err;
5059 }
5060
5061 static void mlx5e_cleanup_nic_rx(struct mlx5e_priv *priv)
5062 {
5063         mlx5e_tc_nic_cleanup(priv);
5064         mlx5e_destroy_flow_steering(priv);
5065         mlx5e_destroy_direct_tirs(priv, priv->xsk_tir);
5066         mlx5e_destroy_direct_rqts(priv, priv->xsk_tir);
5067         mlx5e_destroy_direct_tirs(priv, priv->direct_tir);
5068         mlx5e_destroy_indirect_tirs(priv, true);
5069         mlx5e_destroy_direct_rqts(priv, priv->direct_tir);
5070         mlx5e_destroy_rqt(priv, &priv->indir_rqt);
5071         mlx5e_close_drop_rq(&priv->drop_rq);
5072         mlx5e_destroy_q_counters(priv);
5073 }
5074
5075 static int mlx5e_init_nic_tx(struct mlx5e_priv *priv)
5076 {
5077         int err;
5078
5079         err = mlx5e_create_tises(priv);
5080         if (err) {
5081                 mlx5_core_warn(priv->mdev, "create tises failed, %d\n", err);
5082                 return err;
5083         }
5084
5085 #ifdef CONFIG_MLX5_CORE_EN_DCB
5086         mlx5e_dcbnl_initialize(priv);
5087 #endif
5088         mlx5e_tx_reporter_create(priv);
5089         return 0;
5090 }
5091
5092 static void mlx5e_nic_enable(struct mlx5e_priv *priv)
5093 {
5094         struct net_device *netdev = priv->netdev;
5095         struct mlx5_core_dev *mdev = priv->mdev;
5096
5097         mlx5e_init_l2_addr(priv);
5098
5099         /* Marking the link as currently not needed by the Driver */
5100         if (!netif_running(netdev))
5101                 mlx5_set_port_admin_status(mdev, MLX5_PORT_DOWN);
5102
5103         mlx5e_set_netdev_mtu_boundaries(priv);
5104         mlx5e_set_dev_port_mtu(priv);
5105
5106         mlx5_lag_add(mdev, netdev);
5107
5108         mlx5e_enable_async_events(priv);
5109         if (mlx5e_monitor_counter_supported(priv))
5110                 mlx5e_monitor_counter_init(priv);
5111
5112         if (netdev->reg_state != NETREG_REGISTERED)
5113                 return;
5114 #ifdef CONFIG_MLX5_CORE_EN_DCB
5115         mlx5e_dcbnl_init_app(priv);
5116 #endif
5117
5118         queue_work(priv->wq, &priv->set_rx_mode_work);
5119
5120         rtnl_lock();
5121         if (netif_running(netdev))
5122                 mlx5e_open(netdev);
5123         netif_device_attach(netdev);
5124         rtnl_unlock();
5125 }
5126
5127 static void mlx5e_nic_disable(struct mlx5e_priv *priv)
5128 {
5129         struct mlx5_core_dev *mdev = priv->mdev;
5130
5131 #ifdef CONFIG_MLX5_CORE_EN_DCB
5132         if (priv->netdev->reg_state == NETREG_REGISTERED)
5133                 mlx5e_dcbnl_delete_app(priv);
5134 #endif
5135
5136         rtnl_lock();
5137         if (netif_running(priv->netdev))
5138                 mlx5e_close(priv->netdev);
5139         netif_device_detach(priv->netdev);
5140         rtnl_unlock();
5141
5142         queue_work(priv->wq, &priv->set_rx_mode_work);
5143
5144         if (mlx5e_monitor_counter_supported(priv))
5145                 mlx5e_monitor_counter_cleanup(priv);
5146
5147         mlx5e_disable_async_events(priv);
5148         mlx5_lag_remove(mdev);
5149 }
5150
5151 int mlx5e_update_nic_rx(struct mlx5e_priv *priv)
5152 {
5153         return mlx5e_refresh_tirs(priv, false);
5154 }
5155
5156 static const struct mlx5e_profile mlx5e_nic_profile = {
5157         .init              = mlx5e_nic_init,
5158         .cleanup           = mlx5e_nic_cleanup,
5159         .init_rx           = mlx5e_init_nic_rx,
5160         .cleanup_rx        = mlx5e_cleanup_nic_rx,
5161         .init_tx           = mlx5e_init_nic_tx,
5162         .cleanup_tx        = mlx5e_cleanup_nic_tx,
5163         .enable            = mlx5e_nic_enable,
5164         .disable           = mlx5e_nic_disable,
5165         .update_rx         = mlx5e_update_nic_rx,
5166         .update_stats      = mlx5e_update_ndo_stats,
5167         .update_carrier    = mlx5e_update_carrier,
5168         .rx_handlers.handle_rx_cqe       = mlx5e_handle_rx_cqe,
5169         .rx_handlers.handle_rx_cqe_mpwqe = mlx5e_handle_rx_cqe_mpwrq,
5170         .max_tc            = MLX5E_MAX_NUM_TC,
5171 };
5172
5173 /* mlx5e generic netdev management API (move to en_common.c) */
5174
5175 /* mlx5e_netdev_init/cleanup must be called from profile->init/cleanup callbacks */
5176 int mlx5e_netdev_init(struct net_device *netdev,
5177                       struct mlx5e_priv *priv,
5178                       struct mlx5_core_dev *mdev,
5179                       const struct mlx5e_profile *profile,
5180                       void *ppriv)
5181 {
5182         /* priv init */
5183         priv->mdev        = mdev;
5184         priv->netdev      = netdev;
5185         priv->profile     = profile;
5186         priv->ppriv       = ppriv;
5187         priv->msglevel    = MLX5E_MSG_LEVEL;
5188         priv->max_opened_tc = 1;
5189
5190         mutex_init(&priv->state_lock);
5191         INIT_WORK(&priv->update_carrier_work, mlx5e_update_carrier_work);
5192         INIT_WORK(&priv->set_rx_mode_work, mlx5e_set_rx_mode_work);
5193         INIT_WORK(&priv->tx_timeout_work, mlx5e_tx_timeout_work);
5194         INIT_WORK(&priv->update_stats_work, mlx5e_update_stats_work);
5195
5196         priv->wq = create_singlethread_workqueue("mlx5e");
5197         if (!priv->wq)
5198                 return -ENOMEM;
5199
5200         /* netdev init */
5201         netif_carrier_off(netdev);
5202
5203 #ifdef CONFIG_MLX5_EN_ARFS
5204         netdev->rx_cpu_rmap =  mlx5_eq_table_get_rmap(mdev);
5205 #endif
5206
5207         return 0;
5208 }
5209
5210 void mlx5e_netdev_cleanup(struct net_device *netdev, struct mlx5e_priv *priv)
5211 {
5212         destroy_workqueue(priv->wq);
5213 }
5214
5215 struct net_device *mlx5e_create_netdev(struct mlx5_core_dev *mdev,
5216                                        const struct mlx5e_profile *profile,
5217                                        int nch,
5218                                        void *ppriv)
5219 {
5220         struct net_device *netdev;
5221         int err;
5222
5223         netdev = alloc_etherdev_mqs(sizeof(struct mlx5e_priv),
5224                                     nch * profile->max_tc,
5225                                     nch * MLX5E_NUM_RQ_GROUPS);
5226         if (!netdev) {
5227                 mlx5_core_err(mdev, "alloc_etherdev_mqs() failed\n");
5228                 return NULL;
5229         }
5230
5231         err = profile->init(mdev, netdev, profile, ppriv);
5232         if (err) {
5233                 mlx5_core_err(mdev, "failed to init mlx5e profile %d\n", err);
5234                 goto err_free_netdev;
5235         }
5236
5237         return netdev;
5238
5239 err_free_netdev:
5240         free_netdev(netdev);
5241
5242         return NULL;
5243 }
5244
5245 int mlx5e_attach_netdev(struct mlx5e_priv *priv)
5246 {
5247         const struct mlx5e_profile *profile;
5248         int max_nch;
5249         int err;
5250
5251         profile = priv->profile;
5252         clear_bit(MLX5E_STATE_DESTROYING, &priv->state);
5253
5254         /* max number of channels may have changed */
5255         max_nch = mlx5e_get_max_num_channels(priv->mdev);
5256         if (priv->channels.params.num_channels > max_nch) {
5257                 mlx5_core_warn(priv->mdev, "MLX5E: Reducing number of channels to %d\n", max_nch);
5258                 priv->channels.params.num_channels = max_nch;
5259                 mlx5e_build_default_indir_rqt(priv->rss_params.indirection_rqt,
5260                                               MLX5E_INDIR_RQT_SIZE, max_nch);
5261         }
5262
5263         err = profile->init_tx(priv);
5264         if (err)
5265                 goto out;
5266
5267         err = profile->init_rx(priv);
5268         if (err)
5269                 goto err_cleanup_tx;
5270
5271         if (profile->enable)
5272                 profile->enable(priv);
5273
5274         return 0;
5275
5276 err_cleanup_tx:
5277         profile->cleanup_tx(priv);
5278
5279 out:
5280         return err;
5281 }
5282
5283 void mlx5e_detach_netdev(struct mlx5e_priv *priv)
5284 {
5285         const struct mlx5e_profile *profile = priv->profile;
5286
5287         set_bit(MLX5E_STATE_DESTROYING, &priv->state);
5288
5289         if (profile->disable)
5290                 profile->disable(priv);
5291         flush_workqueue(priv->wq);
5292
5293         profile->cleanup_rx(priv);
5294         profile->cleanup_tx(priv);
5295         cancel_work_sync(&priv->update_stats_work);
5296 }
5297
5298 void mlx5e_destroy_netdev(struct mlx5e_priv *priv)
5299 {
5300         const struct mlx5e_profile *profile = priv->profile;
5301         struct net_device *netdev = priv->netdev;
5302
5303         if (profile->cleanup)
5304                 profile->cleanup(priv);
5305         free_netdev(netdev);
5306 }
5307
5308 /* mlx5e_attach and mlx5e_detach scope should be only creating/destroying
5309  * hardware contexts and to connect it to the current netdev.
5310  */
5311 static int mlx5e_attach(struct mlx5_core_dev *mdev, void *vpriv)
5312 {
5313         struct mlx5e_priv *priv = vpriv;
5314         struct net_device *netdev = priv->netdev;
5315         int err;
5316
5317         if (netif_device_present(netdev))
5318                 return 0;
5319
5320         err = mlx5e_create_mdev_resources(mdev);
5321         if (err)
5322                 return err;
5323
5324         err = mlx5e_attach_netdev(priv);
5325         if (err) {
5326                 mlx5e_destroy_mdev_resources(mdev);
5327                 return err;
5328         }
5329
5330         return 0;
5331 }
5332
5333 static void mlx5e_detach(struct mlx5_core_dev *mdev, void *vpriv)
5334 {
5335         struct mlx5e_priv *priv = vpriv;
5336         struct net_device *netdev = priv->netdev;
5337
5338 #ifdef CONFIG_MLX5_ESWITCH
5339         if (MLX5_ESWITCH_MANAGER(mdev) && vpriv == mdev)
5340                 return;
5341 #endif
5342
5343         if (!netif_device_present(netdev))
5344                 return;
5345
5346         mlx5e_detach_netdev(priv);
5347         mlx5e_destroy_mdev_resources(mdev);
5348 }
5349
5350 static void *mlx5e_add(struct mlx5_core_dev *mdev)
5351 {
5352         struct net_device *netdev;
5353         void *priv;
5354         int err;
5355         int nch;
5356
5357         err = mlx5e_check_required_hca_cap(mdev);
5358         if (err)
5359                 return NULL;
5360
5361 #ifdef CONFIG_MLX5_ESWITCH
5362         if (MLX5_ESWITCH_MANAGER(mdev) &&
5363             mlx5_eswitch_mode(mdev->priv.eswitch) == MLX5_ESWITCH_OFFLOADS) {
5364                 mlx5e_rep_register_vport_reps(mdev);
5365                 return mdev;
5366         }
5367 #endif
5368
5369         nch = mlx5e_get_max_num_channels(mdev);
5370         netdev = mlx5e_create_netdev(mdev, &mlx5e_nic_profile, nch, NULL);
5371         if (!netdev) {
5372                 mlx5_core_err(mdev, "mlx5e_create_netdev failed\n");
5373                 return NULL;
5374         }
5375
5376         priv = netdev_priv(netdev);
5377
5378         err = mlx5e_attach(mdev, priv);
5379         if (err) {
5380                 mlx5_core_err(mdev, "mlx5e_attach failed, %d\n", err);
5381                 goto err_destroy_netdev;
5382         }
5383
5384         err = register_netdev(netdev);
5385         if (err) {
5386                 mlx5_core_err(mdev, "register_netdev failed, %d\n", err);
5387                 goto err_detach;
5388         }
5389
5390 #ifdef CONFIG_MLX5_CORE_EN_DCB
5391         mlx5e_dcbnl_init_app(priv);
5392 #endif
5393         return priv;
5394
5395 err_detach:
5396         mlx5e_detach(mdev, priv);
5397 err_destroy_netdev:
5398         mlx5e_destroy_netdev(priv);
5399         return NULL;
5400 }
5401
5402 static void mlx5e_remove(struct mlx5_core_dev *mdev, void *vpriv)
5403 {
5404         struct mlx5e_priv *priv;
5405
5406 #ifdef CONFIG_MLX5_ESWITCH
5407         if (MLX5_ESWITCH_MANAGER(mdev) && vpriv == mdev) {
5408                 mlx5e_rep_unregister_vport_reps(mdev);
5409                 return;
5410         }
5411 #endif
5412         priv = vpriv;
5413 #ifdef CONFIG_MLX5_CORE_EN_DCB
5414         mlx5e_dcbnl_delete_app(priv);
5415 #endif
5416         unregister_netdev(priv->netdev);
5417         mlx5e_detach(mdev, vpriv);
5418         mlx5e_destroy_netdev(priv);
5419 }
5420
5421 static struct mlx5_interface mlx5e_interface = {
5422         .add       = mlx5e_add,
5423         .remove    = mlx5e_remove,
5424         .attach    = mlx5e_attach,
5425         .detach    = mlx5e_detach,
5426         .protocol  = MLX5_INTERFACE_PROTOCOL_ETH,
5427 };
5428
5429 void mlx5e_init(void)
5430 {
5431         mlx5e_ipsec_build_inverse_table();
5432         mlx5e_build_ptys2ethtool_map();
5433         mlx5_register_interface(&mlx5e_interface);
5434 }
5435
5436 void mlx5e_cleanup(void)
5437 {
5438         mlx5_unregister_interface(&mlx5e_interface);
5439 }