drivers/net/ethernet/mellanox/mlx5/core/en_main.c

   1 /*
   2  * Copyright (c) 2015-2016, Mellanox Technologies. All rights reserved.
   3  *
   4  * This software is available to you under a choice of one of two
   5  * licenses.  You may choose to be licensed under the terms of the GNU
   6  * General Public License (GPL) Version 2, available from the file
   7  * COPYING in the main directory of this source tree, or the
   8  * OpenIB.org BSD license below:
   9  *
  10  *     Redistribution and use in source and binary forms, with or
  11  *     without modification, are permitted provided that the following
  12  *     conditions are met:
  13  *
  14  *      - Redistributions of source code must retain the above
  15  *        copyright notice, this list of conditions and the following
  16  *        disclaimer.
  17  *
  18  *      - Redistributions in binary form must reproduce the above
  19  *        copyright notice, this list of conditions and the following
  20  *        disclaimer in the documentation and/or other materials
  21  *        provided with the distribution.
  22  *
  23  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  24  * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  25  * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
  26  * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
  27  * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
  28  * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
  29  * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
  30  * SOFTWARE.
  31  */
  32
  33 #include <net/tc_act/tc_gact.h>
  34 #include <net/pkt_cls.h>
  35 #include <linux/mlx5/fs.h>
  36 #include <net/vxlan.h>
  37 #include <linux/bpf.h>
  38 #include <linux/if_bridge.h>
  39 #include <net/page_pool.h>
  40 #include "eswitch.h"
  41 #include "en.h"
  42 #include "en_tc.h"
  43 #include "en_rep.h"
  44 #include "en_accel/ipsec.h"
  45 #include "en_accel/ipsec_rxtx.h"
  46 #include "en_accel/tls.h"
  47 #include "accel/ipsec.h"
  48 #include "accel/tls.h"
  49 #include "lib/vxlan.h"
  50 #include "lib/clock.h"
  51 #include "en/port.h"
  52 #include "en/xdp.h"
  53 #include "lib/eq.h"
  54 #include "en/monitor_stats.h"
  55 #include "en/reporter.h"
  56
  57 struct mlx5e_rq_param {
  58         u32                     rqc[MLX5_ST_SZ_DW(rqc)];
  59         struct mlx5_wq_param    wq;
  60         struct mlx5e_rq_frags_info frags_info;
  61 };
  62
  63 struct mlx5e_sq_param {
  64         u32                        sqc[MLX5_ST_SZ_DW(sqc)];
  65         struct mlx5_wq_param       wq;
  66         bool                       is_mpw;
  67 };
  68
  69 struct mlx5e_cq_param {
  70         u32                        cqc[MLX5_ST_SZ_DW(cqc)];
  71         struct mlx5_wq_param       wq;
  72         u16                        eq_ix;
  73         u8                         cq_period_mode;
  74 };
  75
  76 struct mlx5e_channel_param {
  77         struct mlx5e_rq_param      rq;
  78         struct mlx5e_sq_param      sq;
  79         struct mlx5e_sq_param      xdp_sq;
  80         struct mlx5e_sq_param      icosq;
  81         struct mlx5e_cq_param      rx_cq;
  82         struct mlx5e_cq_param      tx_cq;
  83         struct mlx5e_cq_param      icosq_cq;
  84 };
  85
  86 bool mlx5e_check_fragmented_striding_rq_cap(struct mlx5_core_dev *mdev)
  87 {
  88         bool striding_rq_umr = MLX5_CAP_GEN(mdev, striding_rq) &&
  89                 MLX5_CAP_GEN(mdev, umr_ptr_rlky) &&
  90                 MLX5_CAP_ETH(mdev, reg_umr_sq);
  91         u16 max_wqe_sz_cap = MLX5_CAP_GEN(mdev, max_wqe_sz_sq);
  92         bool inline_umr = MLX5E_UMR_WQE_INLINE_SZ <= max_wqe_sz_cap;
  93
  94         if (!striding_rq_umr)
  95                 return false;
  96         if (!inline_umr) {
  97                 mlx5_core_warn(mdev, "Cannot support Striding RQ: UMR WQE size (%d) exceeds maximum supported (%d).\n",
  98                                (int)MLX5E_UMR_WQE_INLINE_SZ, max_wqe_sz_cap);
  99                 return false;
 100         }
 101         return true;
 102 }
 103
 104 static u32 mlx5e_rx_get_linear_frag_sz(struct mlx5e_params *params)
 105 {
 106         u16 hw_mtu = MLX5E_SW2HW_MTU(params, params->sw_mtu);
 107         u16 linear_rq_headroom = params->xdp_prog ?
 108                 XDP_PACKET_HEADROOM : MLX5_RX_HEADROOM;
 109         u32 frag_sz;
 110
 111         linear_rq_headroom += NET_IP_ALIGN;
 112
 113         frag_sz = MLX5_SKB_FRAG_SZ(linear_rq_headroom + hw_mtu);
 114
 115         if (params->xdp_prog && frag_sz < PAGE_SIZE)
 116                 frag_sz = PAGE_SIZE;
 117
 118         return frag_sz;
 119 }
 120
 121 static u8 mlx5e_mpwqe_log_pkts_per_wqe(struct mlx5e_params *params)
 122 {
 123         u32 linear_frag_sz = mlx5e_rx_get_linear_frag_sz(params);
 124
 125         return MLX5_MPWRQ_LOG_WQE_SZ - order_base_2(linear_frag_sz);
 126 }
 127
 128 static bool mlx5e_rx_is_linear_skb(struct mlx5_core_dev *mdev,
 129                                    struct mlx5e_params *params)
 130 {
 131         u32 frag_sz = mlx5e_rx_get_linear_frag_sz(params);
 132
 133         return !params->lro_en && frag_sz <= PAGE_SIZE;
 134 }
 135
 136 #define MLX5_MAX_MPWQE_LOG_WQE_STRIDE_SZ ((BIT(__mlx5_bit_sz(wq, log_wqe_stride_size)) - 1) + \
 137                                           MLX5_MPWQE_LOG_STRIDE_SZ_BASE)
 138 static bool mlx5e_rx_mpwqe_is_linear_skb(struct mlx5_core_dev *mdev,
 139                                          struct mlx5e_params *params)
 140 {
 141         u32 frag_sz = mlx5e_rx_get_linear_frag_sz(params);
 142         s8 signed_log_num_strides_param;
 143         u8 log_num_strides;
 144
 145         if (!mlx5e_rx_is_linear_skb(mdev, params))
 146                 return false;
 147
 148         if (order_base_2(frag_sz) > MLX5_MAX_MPWQE_LOG_WQE_STRIDE_SZ)
 149                 return false;
 150
 151         if (MLX5_CAP_GEN(mdev, ext_stride_num_range))
 152                 return true;
 153
 154         log_num_strides = MLX5_MPWRQ_LOG_WQE_SZ - order_base_2(frag_sz);
 155         signed_log_num_strides_param =
 156                 (s8)log_num_strides - MLX5_MPWQE_LOG_NUM_STRIDES_BASE;
 157
 158         return signed_log_num_strides_param >= 0;
 159 }
 160
 161 static u8 mlx5e_mpwqe_get_log_rq_size(struct mlx5e_params *params)
 162 {
 163         if (params->log_rq_mtu_frames <
 164             mlx5e_mpwqe_log_pkts_per_wqe(params) + MLX5E_PARAMS_MINIMUM_LOG_RQ_SIZE_MPW)
 165                 return MLX5E_PARAMS_MINIMUM_LOG_RQ_SIZE_MPW;
 166
 167         return params->log_rq_mtu_frames - mlx5e_mpwqe_log_pkts_per_wqe(params);
 168 }
 169
 170 static u8 mlx5e_mpwqe_get_log_stride_size(struct mlx5_core_dev *mdev,
 171                                           struct mlx5e_params *params)
 172 {
 173         if (mlx5e_rx_mpwqe_is_linear_skb(mdev, params))
 174                 return order_base_2(mlx5e_rx_get_linear_frag_sz(params));
 175
 176         return MLX5_MPWRQ_DEF_LOG_STRIDE_SZ(mdev);
 177 }
 178
 179 static u8 mlx5e_mpwqe_get_log_num_strides(struct mlx5_core_dev *mdev,
 180                                           struct mlx5e_params *params)
 181 {
 182         return MLX5_MPWRQ_LOG_WQE_SZ -
 183                 mlx5e_mpwqe_get_log_stride_size(mdev, params);
 184 }
 185
 186 static u16 mlx5e_get_rq_headroom(struct mlx5_core_dev *mdev,
 187                                  struct mlx5e_params *params)
 188 {
 189         u16 linear_rq_headroom = params->xdp_prog ?
 190                 XDP_PACKET_HEADROOM : MLX5_RX_HEADROOM;
 191         bool is_linear_skb;
 192
 193         linear_rq_headroom += NET_IP_ALIGN;
 194
 195         is_linear_skb = (params->rq_wq_type == MLX5_WQ_TYPE_CYCLIC) ?
 196                 mlx5e_rx_is_linear_skb(mdev, params) :
 197                 mlx5e_rx_mpwqe_is_linear_skb(mdev, params);
 198
 199         return is_linear_skb ? linear_rq_headroom : 0;
 200 }
 201
 202 void mlx5e_init_rq_type_params(struct mlx5_core_dev *mdev,
 203                                struct mlx5e_params *params)
 204 {
 205         params->lro_wqe_sz = MLX5E_PARAMS_DEFAULT_LRO_WQE_SZ;
 206         params->log_rq_mtu_frames = is_kdump_kernel() ?
 207                 MLX5E_PARAMS_MINIMUM_LOG_RQ_SIZE :
 208                 MLX5E_PARAMS_DEFAULT_LOG_RQ_SIZE;
 209
 210         mlx5_core_info(mdev, "MLX5E: StrdRq(%d) RqSz(%ld) StrdSz(%ld) RxCqeCmprss(%d)\n",
 211                        params->rq_wq_type == MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ,
 212                        params->rq_wq_type == MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ ?
 213                        BIT(mlx5e_mpwqe_get_log_rq_size(params)) :
 214                        BIT(params->log_rq_mtu_frames),
 215                        BIT(mlx5e_mpwqe_get_log_stride_size(mdev, params)),
 216                        MLX5E_GET_PFLAG(params, MLX5E_PFLAG_RX_CQE_COMPRESS));
 217 }
 218
 219 bool mlx5e_striding_rq_possible(struct mlx5_core_dev *mdev,
 220                                 struct mlx5e_params *params)
 221 {
 222         return mlx5e_check_fragmented_striding_rq_cap(mdev) &&
 223                 !MLX5_IPSEC_DEV(mdev) &&
 224                 !(params->xdp_prog && !mlx5e_rx_mpwqe_is_linear_skb(mdev, params));
 225 }
 226
 227 void mlx5e_set_rq_type(struct mlx5_core_dev *mdev, struct mlx5e_params *params)
 228 {
 229         params->rq_wq_type = mlx5e_striding_rq_possible(mdev, params) &&
 230                 MLX5E_GET_PFLAG(params, MLX5E_PFLAG_RX_STRIDING_RQ) ?
 231                 MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ :
 232                 MLX5_WQ_TYPE_CYCLIC;
 233 }
 234
 235 void mlx5e_update_carrier(struct mlx5e_priv *priv)
 236 {
 237         struct mlx5_core_dev *mdev = priv->mdev;
 238         u8 port_state;
 239
 240         port_state = mlx5_query_vport_state(mdev,
 241                                             MLX5_VPORT_STATE_OP_MOD_VNIC_VPORT,
 242                                             0);
 243
 244         if (port_state == VPORT_STATE_UP) {
 245                 netdev_info(priv->netdev, "Link up\n");
 246                 netif_carrier_on(priv->netdev);
 247         } else {
 248                 netdev_info(priv->netdev, "Link down\n");
 249                 netif_carrier_off(priv->netdev);
 250         }
 251 }
 252
 253 static void mlx5e_update_carrier_work(struct work_struct *work)
 254 {
 255         struct mlx5e_priv *priv = container_of(work, struct mlx5e_priv,
 256                                                update_carrier_work);
 257
 258         mutex_lock(&priv->state_lock);
 259         if (test_bit(MLX5E_STATE_OPENED, &priv->state))
 260                 if (priv->profile->update_carrier)
 261                         priv->profile->update_carrier(priv);
 262         mutex_unlock(&priv->state_lock);
 263 }
 264
 265 void mlx5e_update_stats(struct mlx5e_priv *priv)
 266 {
 267         int i;
 268
 269         for (i = mlx5e_num_stats_grps - 1; i >= 0; i--)
 270                 if (mlx5e_stats_grps[i].update_stats)
 271                         mlx5e_stats_grps[i].update_stats(priv);
 272 }
 273
 274 void mlx5e_update_ndo_stats(struct mlx5e_priv *priv)
 275 {
 276         int i;
 277
 278         for (i = mlx5e_num_stats_grps - 1; i >= 0; i--)
 279                 if (mlx5e_stats_grps[i].update_stats_mask &
 280                     MLX5E_NDO_UPDATE_STATS)
 281                         mlx5e_stats_grps[i].update_stats(priv);
 282 }
 283
 284 static void mlx5e_update_stats_work(struct work_struct *work)
 285 {
 286         struct mlx5e_priv *priv = container_of(work, struct mlx5e_priv,
 287                                                update_stats_work);
 288
 289         mutex_lock(&priv->state_lock);
 290         priv->profile->update_stats(priv);
 291         mutex_unlock(&priv->state_lock);
 292 }
 293
 294 void mlx5e_queue_update_stats(struct mlx5e_priv *priv)
 295 {
 296         if (!priv->profile->update_stats)
 297                 return;
 298
 299         if (unlikely(test_bit(MLX5E_STATE_DESTROYING, &priv->state)))
 300                 return;
 301
 302         queue_work(priv->wq, &priv->update_stats_work);
 303 }
 304
 305 static int async_event(struct notifier_block *nb, unsigned long event, void *data)
 306 {
 307         struct mlx5e_priv *priv = container_of(nb, struct mlx5e_priv, events_nb);
 308         struct mlx5_eqe   *eqe = data;
 309
 310         if (event != MLX5_EVENT_TYPE_PORT_CHANGE)
 311                 return NOTIFY_DONE;
 312
 313         switch (eqe->sub_type) {
 314         case MLX5_PORT_CHANGE_SUBTYPE_DOWN:
 315         case MLX5_PORT_CHANGE_SUBTYPE_ACTIVE:
 316                 queue_work(priv->wq, &priv->update_carrier_work);
 317                 break;
 318         default:
 319                 return NOTIFY_DONE;
 320         }
 321
 322         return NOTIFY_OK;
 323 }
 324
 325 static void mlx5e_enable_async_events(struct mlx5e_priv *priv)
 326 {
 327         priv->events_nb.notifier_call = async_event;
 328         mlx5_notifier_register(priv->mdev, &priv->events_nb);
 329 }
 330
 331 static void mlx5e_disable_async_events(struct mlx5e_priv *priv)
 332 {
 333         mlx5_notifier_unregister(priv->mdev, &priv->events_nb);
 334 }
 335
 336 static inline void mlx5e_build_umr_wqe(struct mlx5e_rq *rq,
 337                                        struct mlx5e_icosq *sq,
 338                                        struct mlx5e_umr_wqe *wqe)
 339 {
 340         struct mlx5_wqe_ctrl_seg      *cseg = &wqe->ctrl;
 341         struct mlx5_wqe_umr_ctrl_seg *ucseg = &wqe->uctrl;
 342         u8 ds_cnt = DIV_ROUND_UP(MLX5E_UMR_WQE_INLINE_SZ, MLX5_SEND_WQE_DS);
 343
 344         cseg->qpn_ds    = cpu_to_be32((sq->sqn << MLX5_WQE_CTRL_QPN_SHIFT) |
 345                                       ds_cnt);
 346         cseg->fm_ce_se  = MLX5_WQE_CTRL_CQ_UPDATE;
 347         cseg->imm       = rq->mkey_be;
 348
 349         ucseg->flags = MLX5_UMR_TRANSLATION_OFFSET_EN | MLX5_UMR_INLINE;
 350         ucseg->xlt_octowords =
 351                 cpu_to_be16(MLX5_MTT_OCTW(MLX5_MPWRQ_PAGES_PER_WQE));
 352         ucseg->mkey_mask     = cpu_to_be64(MLX5_MKEY_MASK_FREE);
 353 }
 354
 355 static u32 mlx5e_rqwq_get_size(struct mlx5e_rq *rq)
 356 {
 357         switch (rq->wq_type) {
 358         case MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ:
 359                 return mlx5_wq_ll_get_size(&rq->mpwqe.wq);
 360         default:
 361                 return mlx5_wq_cyc_get_size(&rq->wqe.wq);
 362         }
 363 }
 364
 365 static u32 mlx5e_rqwq_get_cur_sz(struct mlx5e_rq *rq)
 366 {
 367         switch (rq->wq_type) {
 368         case MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ:
 369                 return rq->mpwqe.wq.cur_sz;
 370         default:
 371                 return rq->wqe.wq.cur_sz;
 372         }
 373 }
 374
 375 static int mlx5e_rq_alloc_mpwqe_info(struct mlx5e_rq *rq,
 376                                      struct mlx5e_channel *c)
 377 {
 378         int wq_sz = mlx5_wq_ll_get_size(&rq->mpwqe.wq);
 379
 380         rq->mpwqe.info = kvzalloc_node(array_size(wq_sz,
 381                                                   sizeof(*rq->mpwqe.info)),
 382                                        GFP_KERNEL, cpu_to_node(c->cpu));
 383         if (!rq->mpwqe.info)
 384                 return -ENOMEM;
 385
 386         mlx5e_build_umr_wqe(rq, &c->icosq, &rq->mpwqe.umr_wqe);
 387
 388         return 0;
 389 }
 390
 391 static int mlx5e_create_umr_mkey(struct mlx5_core_dev *mdev,
 392                                  u64 npages, u8 page_shift,
 393                                  struct mlx5_core_mkey *umr_mkey)
 394 {
 395         int inlen = MLX5_ST_SZ_BYTES(create_mkey_in);
 396         void *mkc;
 397         u32 *in;
 398         int err;
 399
 400         in = kvzalloc(inlen, GFP_KERNEL);
 401         if (!in)
 402                 return -ENOMEM;
 403
 404         mkc = MLX5_ADDR_OF(create_mkey_in, in, memory_key_mkey_entry);
 405
 406         MLX5_SET(mkc, mkc, free, 1);
 407         MLX5_SET(mkc, mkc, umr_en, 1);
 408         MLX5_SET(mkc, mkc, lw, 1);
 409         MLX5_SET(mkc, mkc, lr, 1);
 410         MLX5_SET(mkc, mkc, access_mode_1_0, MLX5_MKC_ACCESS_MODE_MTT);
 411
 412         MLX5_SET(mkc, mkc, qpn, 0xffffff);
 413         MLX5_SET(mkc, mkc, pd, mdev->mlx5e_res.pdn);
 414         MLX5_SET64(mkc, mkc, len, npages << page_shift);
 415         MLX5_SET(mkc, mkc, translations_octword_size,
 416                  MLX5_MTT_OCTW(npages));
 417         MLX5_SET(mkc, mkc, log_page_size, page_shift);
 418
 419         err = mlx5_core_create_mkey(mdev, umr_mkey, in, inlen);
 420
 421         kvfree(in);
 422         return err;
 423 }
 424
 425 static int mlx5e_create_rq_umr_mkey(struct mlx5_core_dev *mdev, struct mlx5e_rq *rq)
 426 {
 427         u64 num_mtts = MLX5E_REQUIRED_MTTS(mlx5_wq_ll_get_size(&rq->mpwqe.wq));
 428
 429         return mlx5e_create_umr_mkey(mdev, num_mtts, PAGE_SHIFT, &rq->umr_mkey);
 430 }
 431
 432 static inline u64 mlx5e_get_mpwqe_offset(struct mlx5e_rq *rq, u16 wqe_ix)
 433 {
 434         return (wqe_ix << MLX5E_LOG_ALIGNED_MPWQE_PPW) << PAGE_SHIFT;
 435 }
 436
 437 static void mlx5e_init_frags_partition(struct mlx5e_rq *rq)
 438 {
 439         struct mlx5e_wqe_frag_info next_frag, *prev;
 440         int i;
 441
 442         next_frag.di = &rq->wqe.di[0];
 443         next_frag.offset = 0;
 444         prev = NULL;
 445
 446         for (i = 0; i < mlx5_wq_cyc_get_size(&rq->wqe.wq); i++) {
 447                 struct mlx5e_rq_frag_info *frag_info = &rq->wqe.info.arr[0];
 448                 struct mlx5e_wqe_frag_info *frag =
 449                         &rq->wqe.frags[i << rq->wqe.info.log_num_frags];
 450                 int f;
 451
 452                 for (f = 0; f < rq->wqe.info.num_frags; f++, frag++) {
 453                         if (next_frag.offset + frag_info[f].frag_stride > PAGE_SIZE) {
 454                                 next_frag.di++;
 455                                 next_frag.offset = 0;
 456                                 if (prev)
 457                                         prev->last_in_page = true;
 458                         }
 459                         *frag = next_frag;
 460
 461                         /* prepare next */
 462                         next_frag.offset += frag_info[f].frag_stride;
 463                         prev = frag;
 464                 }
 465         }
 466
 467         if (prev)
 468                 prev->last_in_page = true;
 469 }
 470
 471 static int mlx5e_init_di_list(struct mlx5e_rq *rq,
 472                               struct mlx5e_params *params,
 473                               int wq_sz, int cpu)
 474 {
 475         int len = wq_sz << rq->wqe.info.log_num_frags;
 476
 477         rq->wqe.di = kvzalloc_node(array_size(len, sizeof(*rq->wqe.di)),
 478                                    GFP_KERNEL, cpu_to_node(cpu));
 479         if (!rq->wqe.di)
 480                 return -ENOMEM;
 481
 482         mlx5e_init_frags_partition(rq);
 483
 484         return 0;
 485 }
 486
 487 static void mlx5e_free_di_list(struct mlx5e_rq *rq)
 488 {
 489         kvfree(rq->wqe.di);
 490 }
 491
 492 static int mlx5e_alloc_rq(struct mlx5e_channel *c,
 493                           struct mlx5e_params *params,
 494                           struct mlx5e_rq_param *rqp,
 495                           struct mlx5e_rq *rq)
 496 {
 497         struct page_pool_params pp_params = { 0 };
 498         struct mlx5_core_dev *mdev = c->mdev;
 499         void *rqc = rqp->rqc;
 500         void *rqc_wq = MLX5_ADDR_OF(rqc, rqc, wq);
 501         u32 pool_size;
 502         int wq_sz;
 503         int err;
 504         int i;
 505
 506         rqp->wq.db_numa_node = cpu_to_node(c->cpu);
 507
 508         rq->wq_type = params->rq_wq_type;
 509         rq->pdev    = c->pdev;
 510         rq->netdev  = c->netdev;
 511         rq->tstamp  = c->tstamp;
 512         rq->clock   = &mdev->clock;
 513         rq->channel = c;
 514         rq->ix      = c->ix;
 515         rq->mdev    = mdev;
 516         rq->hw_mtu  = MLX5E_SW2HW_MTU(params, params->sw_mtu);
 517         rq->stats   = &c->priv->channel_stats[c->ix].rq;
 518
 519         rq->xdp_prog = params->xdp_prog ? bpf_prog_inc(params->xdp_prog) : NULL;
 520         if (IS_ERR(rq->xdp_prog)) {
 521                 err = PTR_ERR(rq->xdp_prog);
 522                 rq->xdp_prog = NULL;
 523                 goto err_rq_wq_destroy;
 524         }
 525
 526         err = xdp_rxq_info_reg(&rq->xdp_rxq, rq->netdev, rq->ix);
 527         if (err < 0)
 528                 goto err_rq_wq_destroy;
 529
 530         rq->buff.map_dir = rq->xdp_prog ? DMA_BIDIRECTIONAL : DMA_FROM_DEVICE;
 531         rq->buff.headroom = mlx5e_get_rq_headroom(mdev, params);
 532         pool_size = 1 << params->log_rq_mtu_frames;
 533
 534         switch (rq->wq_type) {
 535         case MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ:
 536                 err = mlx5_wq_ll_create(mdev, &rqp->wq, rqc_wq, &rq->mpwqe.wq,
 537                                         &rq->wq_ctrl);
 538                 if (err)
 539                         return err;
 540
 541                 rq->mpwqe.wq.db = &rq->mpwqe.wq.db[MLX5_RCV_DBR];
 542
 543                 wq_sz = mlx5_wq_ll_get_size(&rq->mpwqe.wq);
 544
 545                 pool_size = MLX5_MPWRQ_PAGES_PER_WQE << mlx5e_mpwqe_get_log_rq_size(params);
 546
 547                 rq->post_wqes = mlx5e_post_rx_mpwqes;
 548                 rq->dealloc_wqe = mlx5e_dealloc_rx_mpwqe;
 549
 550                 rq->handle_rx_cqe = c->priv->profile->rx_handlers.handle_rx_cqe_mpwqe;
 551 #ifdef CONFIG_MLX5_EN_IPSEC
 552                 if (MLX5_IPSEC_DEV(mdev)) {
 553                         err = -EINVAL;
 554                         netdev_err(c->netdev, "MPWQE RQ with IPSec offload not supported\n");
 555                         goto err_rq_wq_destroy;
 556                 }
 557 #endif
 558                 if (!rq->handle_rx_cqe) {
 559                         err = -EINVAL;
 560                         netdev_err(c->netdev, "RX handler of MPWQE RQ is not set, err %d\n", err);
 561                         goto err_rq_wq_destroy;
 562                 }
 563
 564                 rq->mpwqe.skb_from_cqe_mpwrq =
 565                         mlx5e_rx_mpwqe_is_linear_skb(mdev, params) ?
 566                         mlx5e_skb_from_cqe_mpwrq_linear :
 567                         mlx5e_skb_from_cqe_mpwrq_nonlinear;
 568                 rq->mpwqe.log_stride_sz = mlx5e_mpwqe_get_log_stride_size(mdev, params);
 569                 rq->mpwqe.num_strides = BIT(mlx5e_mpwqe_get_log_num_strides(mdev, params));
 570
 571                 err = mlx5e_create_rq_umr_mkey(mdev, rq);
 572                 if (err)
 573                         goto err_rq_wq_destroy;
 574                 rq->mkey_be = cpu_to_be32(rq->umr_mkey.key);
 575
 576                 err = mlx5e_rq_alloc_mpwqe_info(rq, c);
 577                 if (err)
 578                         goto err_free;
 579                 break;
 580         default: /* MLX5_WQ_TYPE_CYCLIC */
 581                 err = mlx5_wq_cyc_create(mdev, &rqp->wq, rqc_wq, &rq->wqe.wq,
 582                                          &rq->wq_ctrl);
 583                 if (err)
 584                         return err;
 585
 586                 rq->wqe.wq.db = &rq->wqe.wq.db[MLX5_RCV_DBR];
 587
 588                 wq_sz = mlx5_wq_cyc_get_size(&rq->wqe.wq);
 589
 590                 rq->wqe.info = rqp->frags_info;
 591                 rq->wqe.frags =
 592                         kvzalloc_node(array_size(sizeof(*rq->wqe.frags),
 593                                         (wq_sz << rq->wqe.info.log_num_frags)),
 594                                       GFP_KERNEL, cpu_to_node(c->cpu));
 595                 if (!rq->wqe.frags) {
 596                         err = -ENOMEM;
 597                         goto err_free;
 598                 }
 599
 600                 err = mlx5e_init_di_list(rq, params, wq_sz, c->cpu);
 601                 if (err)
 602                         goto err_free;
 603                 rq->post_wqes = mlx5e_post_rx_wqes;
 604                 rq->dealloc_wqe = mlx5e_dealloc_rx_wqe;
 605
 606 #ifdef CONFIG_MLX5_EN_IPSEC
 607                 if (c->priv->ipsec)
 608                         rq->handle_rx_cqe = mlx5e_ipsec_handle_rx_cqe;
 609                 else
 610 #endif
 611                         rq->handle_rx_cqe = c->priv->profile->rx_handlers.handle_rx_cqe;
 612                 if (!rq->handle_rx_cqe) {
 613                         err = -EINVAL;
 614                         netdev_err(c->netdev, "RX handler of RQ is not set, err %d\n", err);
 615                         goto err_free;
 616                 }
 617
 618                 rq->wqe.skb_from_cqe = mlx5e_rx_is_linear_skb(mdev, params) ?
 619                         mlx5e_skb_from_cqe_linear :
 620                         mlx5e_skb_from_cqe_nonlinear;
 621                 rq->mkey_be = c->mkey_be;
 622         }
 623
 624         /* Create a page_pool and register it with rxq */
 625         pp_params.order     = 0;
 626         pp_params.flags     = 0; /* No-internal DMA mapping in page_pool */
 627         pp_params.pool_size = pool_size;
 628         pp_params.nid       = cpu_to_node(c->cpu);
 629         pp_params.dev       = c->pdev;
 630         pp_params.dma_dir   = rq->buff.map_dir;
 631
 632         /* page_pool can be used even when there is no rq->xdp_prog,
 633          * given page_pool does not handle DMA mapping there is no
 634          * required state to clear. And page_pool gracefully handle
 635          * elevated refcnt.
 636          */
 637         rq->page_pool = page_pool_create(&pp_params);
 638         if (IS_ERR(rq->page_pool)) {
 639                 err = PTR_ERR(rq->page_pool);
 640                 rq->page_pool = NULL;
 641                 goto err_free;
 642         }
 643         err = xdp_rxq_info_reg_mem_model(&rq->xdp_rxq,
 644                                          MEM_TYPE_PAGE_POOL, rq->page_pool);
 645         if (err)
 646                 goto err_free;
 647
 648         for (i = 0; i < wq_sz; i++) {
 649                 if (rq->wq_type == MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ) {
 650                         struct mlx5e_rx_wqe_ll *wqe =
 651                                 mlx5_wq_ll_get_wqe(&rq->mpwqe.wq, i);
 652                         u32 byte_count =
 653                                 rq->mpwqe.num_strides << rq->mpwqe.log_stride_sz;
 654                         u64 dma_offset = mlx5e_get_mpwqe_offset(rq, i);
 655
 656                         wqe->data[0].addr = cpu_to_be64(dma_offset + rq->buff.headroom);
 657                         wqe->data[0].byte_count = cpu_to_be32(byte_count);
 658                         wqe->data[0].lkey = rq->mkey_be;
 659                 } else {
 660                         struct mlx5e_rx_wqe_cyc *wqe =
 661                                 mlx5_wq_cyc_get_wqe(&rq->wqe.wq, i);
 662                         int f;
 663
 664                         for (f = 0; f < rq->wqe.info.num_frags; f++) {
 665                                 u32 frag_size = rq->wqe.info.arr[f].frag_size |
 666                                         MLX5_HW_START_PADDING;
 667
 668                                 wqe->data[f].byte_count = cpu_to_be32(frag_size);
 669                                 wqe->data[f].lkey = rq->mkey_be;
 670                         }
 671                         /* check if num_frags is not a pow of two */
 672                         if (rq->wqe.info.num_frags < (1 << rq->wqe.info.log_num_frags)) {
 673                                 wqe->data[f].byte_count = 0;
 674                                 wqe->data[f].lkey = cpu_to_be32(MLX5_INVALID_LKEY);
 675                                 wqe->data[f].addr = 0;
 676                         }
 677                 }
 678         }
 679
 680         INIT_WORK(&rq->dim.work, mlx5e_rx_dim_work);
 681
 682         switch (params->rx_cq_moderation.cq_period_mode) {
 683         case MLX5_CQ_PERIOD_MODE_START_FROM_CQE:
 684                 rq->dim.mode = NET_DIM_CQ_PERIOD_MODE_START_FROM_CQE;
 685                 break;
 686         case MLX5_CQ_PERIOD_MODE_START_FROM_EQE:
 687         default:
 688                 rq->dim.mode = NET_DIM_CQ_PERIOD_MODE_START_FROM_EQE;
 689         }
 690
 691         rq->page_cache.head = 0;
 692         rq->page_cache.tail = 0;
 693
 694         return 0;
 695
 696 err_free:
 697         switch (rq->wq_type) {
 698         case MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ:
 699                 kvfree(rq->mpwqe.info);
 700                 mlx5_core_destroy_mkey(mdev, &rq->umr_mkey);
 701                 break;
 702         default: /* MLX5_WQ_TYPE_CYCLIC */
 703                 kvfree(rq->wqe.frags);
 704                 mlx5e_free_di_list(rq);
 705         }
 706
 707 err_rq_wq_destroy:
 708         if (rq->xdp_prog)
 709                 bpf_prog_put(rq->xdp_prog);
 710         xdp_rxq_info_unreg(&rq->xdp_rxq);
 711         if (rq->page_pool)
 712                 page_pool_destroy(rq->page_pool);
 713         mlx5_wq_destroy(&rq->wq_ctrl);
 714
 715         return err;
 716 }
 717
 718 static void mlx5e_free_rq(struct mlx5e_rq *rq)
 719 {
 720         int i;
 721
 722         if (rq->xdp_prog)
 723                 bpf_prog_put(rq->xdp_prog);
 724
 725         xdp_rxq_info_unreg(&rq->xdp_rxq);
 726         if (rq->page_pool)
 727                 page_pool_destroy(rq->page_pool);
 728
 729         switch (rq->wq_type) {
 730         case MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ:
 731                 kvfree(rq->mpwqe.info);
 732                 mlx5_core_destroy_mkey(rq->mdev, &rq->umr_mkey);
 733                 break;
 734         default: /* MLX5_WQ_TYPE_CYCLIC */
 735                 kvfree(rq->wqe.frags);
 736                 mlx5e_free_di_list(rq);
 737         }
 738
 739         for (i = rq->page_cache.head; i != rq->page_cache.tail;
 740              i = (i + 1) & (MLX5E_CACHE_SIZE - 1)) {
 741                 struct mlx5e_dma_info *dma_info = &rq->page_cache.page_cache[i];
 742
 743                 mlx5e_page_release(rq, dma_info, false);
 744         }
 745         mlx5_wq_destroy(&rq->wq_ctrl);
 746 }
 747
 748 static int mlx5e_create_rq(struct mlx5e_rq *rq,
 749                            struct mlx5e_rq_param *param)
 750 {
 751         struct mlx5_core_dev *mdev = rq->mdev;
 752
 753         void *in;
 754         void *rqc;
 755         void *wq;
 756         int inlen;
 757         int err;
 758
 759         inlen = MLX5_ST_SZ_BYTES(create_rq_in) +
 760                 sizeof(u64) * rq->wq_ctrl.buf.npages;
 761         in = kvzalloc(inlen, GFP_KERNEL);
 762         if (!in)
 763                 return -ENOMEM;
 764
 765         rqc = MLX5_ADDR_OF(create_rq_in, in, ctx);
 766         wq  = MLX5_ADDR_OF(rqc, rqc, wq);
 767
 768         memcpy(rqc, param->rqc, sizeof(param->rqc));
 769
 770         MLX5_SET(rqc,  rqc, cqn,                rq->cq.mcq.cqn);
 771         MLX5_SET(rqc,  rqc, state,              MLX5_RQC_STATE_RST);
 772         MLX5_SET(wq,   wq,  log_wq_pg_sz,       rq->wq_ctrl.buf.page_shift -
 773                                                 MLX5_ADAPTER_PAGE_SHIFT);
 774         MLX5_SET64(wq, wq,  dbr_addr,           rq->wq_ctrl.db.dma);
 775
 776         mlx5_fill_page_frag_array(&rq->wq_ctrl.buf,
 777                                   (__be64 *)MLX5_ADDR_OF(wq, wq, pas));
 778
 779         err = mlx5_core_create_rq(mdev, in, inlen, &rq->rqn);
 780
 781         kvfree(in);
 782
 783         return err;
 784 }
 785
 786 static int mlx5e_modify_rq_state(struct mlx5e_rq *rq, int curr_state,
 787                                  int next_state)
 788 {
 789         struct mlx5_core_dev *mdev = rq->mdev;
 790
 791         void *in;
 792         void *rqc;
 793         int inlen;
 794         int err;
 795
 796         inlen = MLX5_ST_SZ_BYTES(modify_rq_in);
 797         in = kvzalloc(inlen, GFP_KERNEL);
 798         if (!in)
 799                 return -ENOMEM;
 800
 801         rqc = MLX5_ADDR_OF(modify_rq_in, in, ctx);
 802
 803         MLX5_SET(modify_rq_in, in, rq_state, curr_state);
 804         MLX5_SET(rqc, rqc, state, next_state);
 805
 806         err = mlx5_core_modify_rq(mdev, rq->rqn, in, inlen);
 807
 808         kvfree(in);
 809
 810         return err;
 811 }
 812
 813 static int mlx5e_modify_rq_scatter_fcs(struct mlx5e_rq *rq, bool enable)
 814 {
 815         struct mlx5e_channel *c = rq->channel;
 816         struct mlx5e_priv *priv = c->priv;
 817         struct mlx5_core_dev *mdev = priv->mdev;
 818
 819         void *in;
 820         void *rqc;
 821         int inlen;
 822         int err;
 823
 824         inlen = MLX5_ST_SZ_BYTES(modify_rq_in);
 825         in = kvzalloc(inlen, GFP_KERNEL);
 826         if (!in)
 827                 return -ENOMEM;
 828
 829         rqc = MLX5_ADDR_OF(modify_rq_in, in, ctx);
 830
 831         MLX5_SET(modify_rq_in, in, rq_state, MLX5_RQC_STATE_RDY);
 832         MLX5_SET64(modify_rq_in, in, modify_bitmask,
 833                    MLX5_MODIFY_RQ_IN_MODIFY_BITMASK_SCATTER_FCS);
 834         MLX5_SET(rqc, rqc, scatter_fcs, enable);
 835         MLX5_SET(rqc, rqc, state, MLX5_RQC_STATE_RDY);
 836
 837         err = mlx5_core_modify_rq(mdev, rq->rqn, in, inlen);
 838
 839         kvfree(in);
 840
 841         return err;
 842 }
 843
 844 static int mlx5e_modify_rq_vsd(struct mlx5e_rq *rq, bool vsd)
 845 {
 846         struct mlx5e_channel *c = rq->channel;
 847         struct mlx5_core_dev *mdev = c->mdev;
 848         void *in;
 849         void *rqc;
 850         int inlen;
 851         int err;
 852
 853         inlen = MLX5_ST_SZ_BYTES(modify_rq_in);
 854         in = kvzalloc(inlen, GFP_KERNEL);
 855         if (!in)
 856                 return -ENOMEM;
 857
 858         rqc = MLX5_ADDR_OF(modify_rq_in, in, ctx);
 859
 860         MLX5_SET(modify_rq_in, in, rq_state, MLX5_RQC_STATE_RDY);
 861         MLX5_SET64(modify_rq_in, in, modify_bitmask,
 862                    MLX5_MODIFY_RQ_IN_MODIFY_BITMASK_VSD);
 863         MLX5_SET(rqc, rqc, vsd, vsd);
 864         MLX5_SET(rqc, rqc, state, MLX5_RQC_STATE_RDY);
 865
 866         err = mlx5_core_modify_rq(mdev, rq->rqn, in, inlen);
 867
 868         kvfree(in);
 869
 870         return err;
 871 }
 872
 873 static void mlx5e_destroy_rq(struct mlx5e_rq *rq)
 874 {
 875         mlx5_core_destroy_rq(rq->mdev, rq->rqn);
 876 }
 877
 878 static int mlx5e_wait_for_min_rx_wqes(struct mlx5e_rq *rq, int wait_time)
 879 {
 880         unsigned long exp_time = jiffies + msecs_to_jiffies(wait_time);
 881         struct mlx5e_channel *c = rq->channel;
 882
 883         u16 min_wqes = mlx5_min_rx_wqes(rq->wq_type, mlx5e_rqwq_get_size(rq));
 884
 885         do {
 886                 if (mlx5e_rqwq_get_cur_sz(rq) >= min_wqes)
 887                         return 0;
 888
 889                 msleep(20);
 890         } while (time_before(jiffies, exp_time));
 891
 892         netdev_warn(c->netdev, "Failed to get min RX wqes on Channel[%d] RQN[0x%x] wq cur_sz(%d) min_rx_wqes(%d)\n",
 893                     c->ix, rq->rqn, mlx5e_rqwq_get_cur_sz(rq), min_wqes);
 894
 895         return -ETIMEDOUT;
 896 }
 897
 898 static void mlx5e_free_rx_descs(struct mlx5e_rq *rq)
 899 {
 900         __be16 wqe_ix_be;
 901         u16 wqe_ix;
 902
 903         if (rq->wq_type == MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ) {
 904                 struct mlx5_wq_ll *wq = &rq->mpwqe.wq;
 905
 906                 /* UMR WQE (if in progress) is always at wq->head */
 907                 if (rq->mpwqe.umr_in_progress)
 908                         rq->dealloc_wqe(rq, wq->head);
 909
 910                 while (!mlx5_wq_ll_is_empty(wq)) {
 911                         struct mlx5e_rx_wqe_ll *wqe;
 912
 913                         wqe_ix_be = *wq->tail_next;
 914                         wqe_ix    = be16_to_cpu(wqe_ix_be);
 915                         wqe       = mlx5_wq_ll_get_wqe(wq, wqe_ix);
 916                         rq->dealloc_wqe(rq, wqe_ix);
 917                         mlx5_wq_ll_pop(wq, wqe_ix_be,
 918                                        &wqe->next.next_wqe_index);
 919                 }
 920         } else {
 921                 struct mlx5_wq_cyc *wq = &rq->wqe.wq;
 922
 923                 while (!mlx5_wq_cyc_is_empty(wq)) {
 924                         wqe_ix = mlx5_wq_cyc_get_tail(wq);
 925                         rq->dealloc_wqe(rq, wqe_ix);
 926                         mlx5_wq_cyc_pop(wq);
 927                 }
 928         }
 929
 930 }
 931
 932 static int mlx5e_open_rq(struct mlx5e_channel *c,
 933                          struct mlx5e_params *params,
 934                          struct mlx5e_rq_param *param,
 935                          struct mlx5e_rq *rq)
 936 {
 937         int err;
 938
 939         err = mlx5e_alloc_rq(c, params, param, rq);
 940         if (err)
 941                 return err;
 942
 943         err = mlx5e_create_rq(rq, param);
 944         if (err)
 945                 goto err_free_rq;
 946
 947         err = mlx5e_modify_rq_state(rq, MLX5_RQC_STATE_RST, MLX5_RQC_STATE_RDY);
 948         if (err)
 949                 goto err_destroy_rq;
 950
 951         if (params->rx_dim_enabled)
 952                 __set_bit(MLX5E_RQ_STATE_AM, &c->rq.state);
 953
 954         if (MLX5E_GET_PFLAG(params, MLX5E_PFLAG_RX_NO_CSUM_COMPLETE))
 955                 __set_bit(MLX5E_RQ_STATE_NO_CSUM_COMPLETE, &c->rq.state);
 956
 957         return 0;
 958
 959 err_destroy_rq:
 960         mlx5e_destroy_rq(rq);
 961 err_free_rq:
 962         mlx5e_free_rq(rq);
 963
 964         return err;
 965 }
 966
 967 static void mlx5e_activate_rq(struct mlx5e_rq *rq)
 968 {
 969         struct mlx5e_icosq *sq = &rq->channel->icosq;
 970         struct mlx5_wq_cyc *wq = &sq->wq;
 971         struct mlx5e_tx_wqe *nopwqe;
 972
 973         u16 pi = mlx5_wq_cyc_ctr2ix(wq, sq->pc);
 974
 975         set_bit(MLX5E_RQ_STATE_ENABLED, &rq->state);
 976         sq->db.ico_wqe[pi].opcode     = MLX5_OPCODE_NOP;
 977         nopwqe = mlx5e_post_nop(wq, sq->sqn, &sq->pc);
 978         mlx5e_notify_hw(wq, sq->pc, sq->uar_map, &nopwqe->ctrl);
 979 }
 980
 981 static void mlx5e_deactivate_rq(struct mlx5e_rq *rq)
 982 {
 983         clear_bit(MLX5E_RQ_STATE_ENABLED, &rq->state);
 984         napi_synchronize(&rq->channel->napi); /* prevent mlx5e_post_rx_wqes */
 985 }
 986
 987 static void mlx5e_close_rq(struct mlx5e_rq *rq)
 988 {
 989         cancel_work_sync(&rq->dim.work);
 990         mlx5e_destroy_rq(rq);
 991         mlx5e_free_rx_descs(rq);
 992         mlx5e_free_rq(rq);
 993 }
 994
 995 static void mlx5e_free_xdpsq_db(struct mlx5e_xdpsq *sq)
 996 {
 997         kvfree(sq->db.xdpi_fifo.xi);
 998         kvfree(sq->db.wqe_info);
 999 }
1000
1001 static int mlx5e_alloc_xdpsq_fifo(struct mlx5e_xdpsq *sq, int numa)
1002 {
1003         struct mlx5e_xdp_info_fifo *xdpi_fifo = &sq->db.xdpi_fifo;
1004         int wq_sz        = mlx5_wq_cyc_get_size(&sq->wq);
1005         int dsegs_per_wq = wq_sz * MLX5_SEND_WQEBB_NUM_DS;
1006
1007         xdpi_fifo->xi = kvzalloc_node(sizeof(*xdpi_fifo->xi) * dsegs_per_wq,
1008                                       GFP_KERNEL, numa);
1009         if (!xdpi_fifo->xi)
1010                 return -ENOMEM;
1011
1012         xdpi_fifo->pc   = &sq->xdpi_fifo_pc;
1013         xdpi_fifo->cc   = &sq->xdpi_fifo_cc;
1014         xdpi_fifo->mask = dsegs_per_wq - 1;
1015
1016         return 0;
1017 }
1018
1019 static int mlx5e_alloc_xdpsq_db(struct mlx5e_xdpsq *sq, int numa)
1020 {
1021         int wq_sz = mlx5_wq_cyc_get_size(&sq->wq);
1022         int err;
1023
1024         sq->db.wqe_info = kvzalloc_node(sizeof(*sq->db.wqe_info) * wq_sz,
1025                                         GFP_KERNEL, numa);
1026         if (!sq->db.wqe_info)
1027                 return -ENOMEM;
1028
1029         err = mlx5e_alloc_xdpsq_fifo(sq, numa);
1030         if (err) {
1031                 mlx5e_free_xdpsq_db(sq);
1032                 return err;
1033         }
1034
1035         return 0;
1036 }
1037
1038 static int mlx5e_alloc_xdpsq(struct mlx5e_channel *c,
1039                              struct mlx5e_params *params,
1040                              struct mlx5e_sq_param *param,
1041                              struct mlx5e_xdpsq *sq,
1042                              bool is_redirect)
1043 {
1044         void *sqc_wq               = MLX5_ADDR_OF(sqc, param->sqc, wq);
1045         struct mlx5_core_dev *mdev = c->mdev;
1046         struct mlx5_wq_cyc *wq = &sq->wq;
1047         int err;
1048
1049         sq->pdev      = c->pdev;
1050         sq->mkey_be   = c->mkey_be;
1051         sq->channel   = c;
1052         sq->uar_map   = mdev->mlx5e_res.bfreg.map;
1053         sq->min_inline_mode = params->tx_min_inline_mode;
1054         sq->hw_mtu    = MLX5E_SW2HW_MTU(params, params->sw_mtu);
1055         sq->stats     = is_redirect ?
1056                 &c->priv->channel_stats[c->ix].xdpsq :
1057                 &c->priv->channel_stats[c->ix].rq_xdpsq;
1058
1059         param->wq.db_numa_node = cpu_to_node(c->cpu);
1060         err = mlx5_wq_cyc_create(mdev, &param->wq, sqc_wq, wq, &sq->wq_ctrl);
1061         if (err)
1062                 return err;
1063         wq->db = &wq->db[MLX5_SND_DBR];
1064
1065         err = mlx5e_alloc_xdpsq_db(sq, cpu_to_node(c->cpu));
1066         if (err)
1067                 goto err_sq_wq_destroy;
1068
1069         return 0;
1070
1071 err_sq_wq_destroy:
1072         mlx5_wq_destroy(&sq->wq_ctrl);
1073
1074         return err;
1075 }
1076
1077 static void mlx5e_free_xdpsq(struct mlx5e_xdpsq *sq)
1078 {
1079         mlx5e_free_xdpsq_db(sq);
1080         mlx5_wq_destroy(&sq->wq_ctrl);
1081 }
1082
1083 static void mlx5e_free_icosq_db(struct mlx5e_icosq *sq)
1084 {
1085         kvfree(sq->db.ico_wqe);
1086 }
1087
1088 static int mlx5e_alloc_icosq_db(struct mlx5e_icosq *sq, int numa)
1089 {
1090         u8 wq_sz = mlx5_wq_cyc_get_size(&sq->wq);
1091
1092         sq->db.ico_wqe = kvzalloc_node(array_size(wq_sz,
1093                                                   sizeof(*sq->db.ico_wqe)),
1094                                        GFP_KERNEL, numa);
1095         if (!sq->db.ico_wqe)
1096                 return -ENOMEM;
1097
1098         return 0;
1099 }
1100
1101 static int mlx5e_alloc_icosq(struct mlx5e_channel *c,
1102                              struct mlx5e_sq_param *param,
1103                              struct mlx5e_icosq *sq)
1104 {
1105         void *sqc_wq               = MLX5_ADDR_OF(sqc, param->sqc, wq);
1106         struct mlx5_core_dev *mdev = c->mdev;
1107         struct mlx5_wq_cyc *wq = &sq->wq;
1108         int err;
1109
1110         sq->channel   = c;
1111         sq->uar_map   = mdev->mlx5e_res.bfreg.map;
1112
1113         param->wq.db_numa_node = cpu_to_node(c->cpu);
1114         err = mlx5_wq_cyc_create(mdev, &param->wq, sqc_wq, wq, &sq->wq_ctrl);
1115         if (err)
1116                 return err;
1117         wq->db = &wq->db[MLX5_SND_DBR];
1118
1119         err = mlx5e_alloc_icosq_db(sq, cpu_to_node(c->cpu));
1120         if (err)
1121                 goto err_sq_wq_destroy;
1122
1123         return 0;
1124
1125 err_sq_wq_destroy:
1126         mlx5_wq_destroy(&sq->wq_ctrl);
1127
1128         return err;
1129 }
1130
1131 static void mlx5e_free_icosq(struct mlx5e_icosq *sq)
1132 {
1133         mlx5e_free_icosq_db(sq);
1134         mlx5_wq_destroy(&sq->wq_ctrl);
1135 }
1136
1137 static void mlx5e_free_txqsq_db(struct mlx5e_txqsq *sq)
1138 {
1139         kvfree(sq->db.wqe_info);
1140         kvfree(sq->db.dma_fifo);
1141 }
1142
1143 static int mlx5e_alloc_txqsq_db(struct mlx5e_txqsq *sq, int numa)
1144 {
1145         int wq_sz = mlx5_wq_cyc_get_size(&sq->wq);
1146         int df_sz = wq_sz * MLX5_SEND_WQEBB_NUM_DS;
1147
1148         sq->db.dma_fifo = kvzalloc_node(array_size(df_sz,
1149                                                    sizeof(*sq->db.dma_fifo)),
1150                                         GFP_KERNEL, numa);
1151         sq->db.wqe_info = kvzalloc_node(array_size(wq_sz,
1152                                                    sizeof(*sq->db.wqe_info)),
1153                                         GFP_KERNEL, numa);
1154         if (!sq->db.dma_fifo || !sq->db.wqe_info) {
1155                 mlx5e_free_txqsq_db(sq);
1156                 return -ENOMEM;
1157         }
1158
1159         sq->dma_fifo_mask = df_sz - 1;
1160
1161         return 0;
1162 }
1163
1164 static void mlx5e_tx_err_cqe_work(struct work_struct *recover_work);
1165 static int mlx5e_alloc_txqsq(struct mlx5e_channel *c,
1166                              int txq_ix,
1167                              struct mlx5e_params *params,
1168                              struct mlx5e_sq_param *param,
1169                              struct mlx5e_txqsq *sq,
1170                              int tc)
1171 {
1172         void *sqc_wq               = MLX5_ADDR_OF(sqc, param->sqc, wq);
1173         struct mlx5_core_dev *mdev = c->mdev;
1174         struct mlx5_wq_cyc *wq = &sq->wq;
1175         int err;
1176
1177         sq->pdev      = c->pdev;
1178         sq->tstamp    = c->tstamp;
1179         sq->clock     = &mdev->clock;
1180         sq->mkey_be   = c->mkey_be;
1181         sq->channel   = c;
1182         sq->txq_ix    = txq_ix;
1183         sq->uar_map   = mdev->mlx5e_res.bfreg.map;
1184         sq->min_inline_mode = params->tx_min_inline_mode;
1185         sq->stats     = &c->priv->channel_stats[c->ix].sq[tc];
1186         INIT_WORK(&sq->recover_work, mlx5e_tx_err_cqe_work);
1187         if (MLX5_IPSEC_DEV(c->priv->mdev))
1188                 set_bit(MLX5E_SQ_STATE_IPSEC, &sq->state);
1189         if (mlx5_accel_is_tls_device(c->priv->mdev))
1190                 set_bit(MLX5E_SQ_STATE_TLS, &sq->state);
1191
1192         param->wq.db_numa_node = cpu_to_node(c->cpu);
1193         err = mlx5_wq_cyc_create(mdev, &param->wq, sqc_wq, wq, &sq->wq_ctrl);
1194         if (err)
1195                 return err;
1196         wq->db    = &wq->db[MLX5_SND_DBR];
1197
1198         err = mlx5e_alloc_txqsq_db(sq, cpu_to_node(c->cpu));
1199         if (err)
1200                 goto err_sq_wq_destroy;
1201
1202         INIT_WORK(&sq->dim.work, mlx5e_tx_dim_work);
1203         sq->dim.mode = params->tx_cq_moderation.cq_period_mode;
1204
1205         return 0;
1206
1207 err_sq_wq_destroy:
1208         mlx5_wq_destroy(&sq->wq_ctrl);
1209
1210         return err;
1211 }
1212
1213 static void mlx5e_free_txqsq(struct mlx5e_txqsq *sq)
1214 {
1215         mlx5e_free_txqsq_db(sq);
1216         mlx5_wq_destroy(&sq->wq_ctrl);
1217 }
1218
1219 struct mlx5e_create_sq_param {
1220         struct mlx5_wq_ctrl        *wq_ctrl;
1221         u32                         cqn;
1222         u32                         tisn;
1223         u8                          tis_lst_sz;
1224         u8                          min_inline_mode;
1225 };
1226
1227 static int mlx5e_create_sq(struct mlx5_core_dev *mdev,
1228                            struct mlx5e_sq_param *param,
1229                            struct mlx5e_create_sq_param *csp,
1230                            u32 *sqn)
1231 {
1232         void *in;
1233         void *sqc;
1234         void *wq;
1235         int inlen;
1236         int err;
1237
1238         inlen = MLX5_ST_SZ_BYTES(create_sq_in) +
1239                 sizeof(u64) * csp->wq_ctrl->buf.npages;
1240         in = kvzalloc(inlen, GFP_KERNEL);
1241         if (!in)
1242                 return -ENOMEM;
1243
1244         sqc = MLX5_ADDR_OF(create_sq_in, in, ctx);
1245         wq = MLX5_ADDR_OF(sqc, sqc, wq);
1246
1247         memcpy(sqc, param->sqc, sizeof(param->sqc));
1248         MLX5_SET(sqc,  sqc, tis_lst_sz, csp->tis_lst_sz);
1249         MLX5_SET(sqc,  sqc, tis_num_0, csp->tisn);
1250         MLX5_SET(sqc,  sqc, cqn, csp->cqn);
1251
1252         if (MLX5_CAP_ETH(mdev, wqe_inline_mode) == MLX5_CAP_INLINE_MODE_VPORT_CONTEXT)
1253                 MLX5_SET(sqc,  sqc, min_wqe_inline_mode, csp->min_inline_mode);
1254
1255         MLX5_SET(sqc,  sqc, state, MLX5_SQC_STATE_RST);
1256         MLX5_SET(sqc,  sqc, flush_in_error_en, 1);
1257
1258         MLX5_SET(wq,   wq, wq_type,       MLX5_WQ_TYPE_CYCLIC);
1259         MLX5_SET(wq,   wq, uar_page,      mdev->mlx5e_res.bfreg.index);
1260         MLX5_SET(wq,   wq, log_wq_pg_sz,  csp->wq_ctrl->buf.page_shift -
1261                                           MLX5_ADAPTER_PAGE_SHIFT);
1262         MLX5_SET64(wq, wq, dbr_addr,      csp->wq_ctrl->db.dma);
1263
1264         mlx5_fill_page_frag_array(&csp->wq_ctrl->buf,
1265                                   (__be64 *)MLX5_ADDR_OF(wq, wq, pas));
1266
1267         err = mlx5_core_create_sq(mdev, in, inlen, sqn);
1268
1269         kvfree(in);
1270
1271         return err;
1272 }
1273
1274 int mlx5e_modify_sq(struct mlx5_core_dev *mdev, u32 sqn,
1275                     struct mlx5e_modify_sq_param *p)
1276 {
1277         void *in;
1278         void *sqc;
1279         int inlen;
1280         int err;
1281
1282         inlen = MLX5_ST_SZ_BYTES(modify_sq_in);
1283         in = kvzalloc(inlen, GFP_KERNEL);
1284         if (!in)
1285                 return -ENOMEM;
1286
1287         sqc = MLX5_ADDR_OF(modify_sq_in, in, ctx);
1288
1289         MLX5_SET(modify_sq_in, in, sq_state, p->curr_state);
1290         MLX5_SET(sqc, sqc, state, p->next_state);
1291         if (p->rl_update && p->next_state == MLX5_SQC_STATE_RDY) {
1292                 MLX5_SET64(modify_sq_in, in, modify_bitmask, 1);
1293                 MLX5_SET(sqc,  sqc, packet_pacing_rate_limit_index, p->rl_index);
1294         }
1295
1296         err = mlx5_core_modify_sq(mdev, sqn, in, inlen);
1297
1298         kvfree(in);
1299
1300         return err;
1301 }
1302
1303 static void mlx5e_destroy_sq(struct mlx5_core_dev *mdev, u32 sqn)
1304 {
1305         mlx5_core_destroy_sq(mdev, sqn);
1306 }
1307
1308 static int mlx5e_create_sq_rdy(struct mlx5_core_dev *mdev,
1309                                struct mlx5e_sq_param *param,
1310                                struct mlx5e_create_sq_param *csp,
1311                                u32 *sqn)
1312 {
1313         struct mlx5e_modify_sq_param msp = {0};
1314         int err;
1315
1316         err = mlx5e_create_sq(mdev, param, csp, sqn);
1317         if (err)
1318                 return err;
1319
1320         msp.curr_state = MLX5_SQC_STATE_RST;
1321         msp.next_state = MLX5_SQC_STATE_RDY;
1322         err = mlx5e_modify_sq(mdev, *sqn, &msp);
1323         if (err)
1324                 mlx5e_destroy_sq(mdev, *sqn);
1325
1326         return err;
1327 }
1328
1329 static int mlx5e_set_sq_maxrate(struct net_device *dev,
1330                                 struct mlx5e_txqsq *sq, u32 rate);
1331
1332 static int mlx5e_open_txqsq(struct mlx5e_channel *c,
1333                             u32 tisn,
1334                             int txq_ix,
1335                             struct mlx5e_params *params,
1336                             struct mlx5e_sq_param *param,
1337                             struct mlx5e_txqsq *sq,
1338                             int tc)
1339 {
1340         struct mlx5e_create_sq_param csp = {};
1341         u32 tx_rate;
1342         int err;
1343
1344         err = mlx5e_alloc_txqsq(c, txq_ix, params, param, sq, tc);
1345         if (err)
1346                 return err;
1347
1348         csp.tisn            = tisn;
1349         csp.tis_lst_sz      = 1;
1350         csp.cqn             = sq->cq.mcq.cqn;
1351         csp.wq_ctrl         = &sq->wq_ctrl;
1352         csp.min_inline_mode = sq->min_inline_mode;
1353         err = mlx5e_create_sq_rdy(c->mdev, param, &csp, &sq->sqn);
1354         if (err)
1355                 goto err_free_txqsq;
1356
1357         tx_rate = c->priv->tx_rates[sq->txq_ix];
1358         if (tx_rate)
1359                 mlx5e_set_sq_maxrate(c->netdev, sq, tx_rate);
1360
1361         if (params->tx_dim_enabled)
1362                 sq->state |= BIT(MLX5E_SQ_STATE_AM);
1363
1364         return 0;
1365
1366 err_free_txqsq:
1367         clear_bit(MLX5E_SQ_STATE_ENABLED, &sq->state);
1368         mlx5e_free_txqsq(sq);
1369
1370         return err;
1371 }
1372
1373 void mlx5e_activate_txqsq(struct mlx5e_txqsq *sq)
1374 {
1375         sq->txq = netdev_get_tx_queue(sq->channel->netdev, sq->txq_ix);
1376         clear_bit(MLX5E_SQ_STATE_RECOVERING, &sq->state);
1377         set_bit(MLX5E_SQ_STATE_ENABLED, &sq->state);
1378         netdev_tx_reset_queue(sq->txq);
1379         netif_tx_start_queue(sq->txq);
1380 }
1381
1382 void mlx5e_tx_disable_queue(struct netdev_queue *txq)
1383 {
1384         __netif_tx_lock_bh(txq);
1385         netif_tx_stop_queue(txq);
1386         __netif_tx_unlock_bh(txq);
1387 }
1388
1389 static void mlx5e_deactivate_txqsq(struct mlx5e_txqsq *sq)
1390 {
1391         struct mlx5e_channel *c = sq->channel;
1392         struct mlx5_wq_cyc *wq = &sq->wq;
1393
1394         clear_bit(MLX5E_SQ_STATE_ENABLED, &sq->state);
1395         /* prevent netif_tx_wake_queue */
1396         napi_synchronize(&c->napi);
1397
1398         mlx5e_tx_disable_queue(sq->txq);
1399
1400         /* last doorbell out, godspeed .. */
1401         if (mlx5e_wqc_has_room_for(wq, sq->cc, sq->pc, 1)) {
1402                 u16 pi = mlx5_wq_cyc_ctr2ix(wq, sq->pc);
1403                 struct mlx5e_tx_wqe *nop;
1404
1405                 sq->db.wqe_info[pi].skb = NULL;
1406                 nop = mlx5e_post_nop(wq, sq->sqn, &sq->pc);
1407                 mlx5e_notify_hw(wq, sq->pc, sq->uar_map, &nop->ctrl);
1408         }
1409 }
1410
1411 static void mlx5e_close_txqsq(struct mlx5e_txqsq *sq)
1412 {
1413         struct mlx5e_channel *c = sq->channel;
1414         struct mlx5_core_dev *mdev = c->mdev;
1415         struct mlx5_rate_limit rl = {0};
1416
1417         cancel_work_sync(&sq->dim.work);
1418         cancel_work_sync(&sq->recover_work);
1419         mlx5e_destroy_sq(mdev, sq->sqn);
1420         if (sq->rate_limit) {
1421                 rl.rate = sq->rate_limit;
1422                 mlx5_rl_remove_rate(mdev, &rl);
1423         }
1424         mlx5e_free_txqsq_descs(sq);
1425         mlx5e_free_txqsq(sq);
1426 }
1427
1428 static void mlx5e_tx_err_cqe_work(struct work_struct *recover_work)
1429 {
1430         struct mlx5e_txqsq *sq = container_of(recover_work, struct mlx5e_txqsq,
1431                                               recover_work);
1432
1433         mlx5e_tx_reporter_err_cqe(sq);
1434 }
1435
1436 static int mlx5e_open_icosq(struct mlx5e_channel *c,
1437                             struct mlx5e_params *params,
1438                             struct mlx5e_sq_param *param,
1439                             struct mlx5e_icosq *sq)
1440 {
1441         struct mlx5e_create_sq_param csp = {};
1442         int err;
1443
1444         err = mlx5e_alloc_icosq(c, param, sq);
1445         if (err)
1446                 return err;
1447
1448         csp.cqn             = sq->cq.mcq.cqn;
1449         csp.wq_ctrl         = &sq->wq_ctrl;
1450         csp.min_inline_mode = params->tx_min_inline_mode;
1451         set_bit(MLX5E_SQ_STATE_ENABLED, &sq->state);
1452         err = mlx5e_create_sq_rdy(c->mdev, param, &csp, &sq->sqn);
1453         if (err)
1454                 goto err_free_icosq;
1455
1456         return 0;
1457
1458 err_free_icosq:
1459         clear_bit(MLX5E_SQ_STATE_ENABLED, &sq->state);
1460         mlx5e_free_icosq(sq);
1461
1462         return err;
1463 }
1464
1465 static void mlx5e_close_icosq(struct mlx5e_icosq *sq)
1466 {
1467         struct mlx5e_channel *c = sq->channel;
1468
1469         clear_bit(MLX5E_SQ_STATE_ENABLED, &sq->state);
1470         napi_synchronize(&c->napi);
1471
1472         mlx5e_destroy_sq(c->mdev, sq->sqn);
1473         mlx5e_free_icosq(sq);
1474 }
1475
1476 static int mlx5e_open_xdpsq(struct mlx5e_channel *c,
1477                             struct mlx5e_params *params,
1478                             struct mlx5e_sq_param *param,
1479                             struct mlx5e_xdpsq *sq,
1480                             bool is_redirect)
1481 {
1482         struct mlx5e_create_sq_param csp = {};
1483         int err;
1484
1485         err = mlx5e_alloc_xdpsq(c, params, param, sq, is_redirect);
1486         if (err)
1487                 return err;
1488
1489         csp.tis_lst_sz      = 1;
1490         csp.tisn            = c->priv->tisn[0]; /* tc = 0 */
1491         csp.cqn             = sq->cq.mcq.cqn;
1492         csp.wq_ctrl         = &sq->wq_ctrl;
1493         csp.min_inline_mode = sq->min_inline_mode;
1494         set_bit(MLX5E_SQ_STATE_ENABLED, &sq->state);
1495         err = mlx5e_create_sq_rdy(c->mdev, param, &csp, &sq->sqn);
1496         if (err)
1497                 goto err_free_xdpsq;
1498
1499         mlx5e_set_xmit_fp(sq, param->is_mpw);
1500
1501         if (!param->is_mpw) {
1502                 unsigned int ds_cnt = MLX5E_XDP_TX_DS_COUNT;
1503                 unsigned int inline_hdr_sz = 0;
1504                 int i;
1505
1506                 if (sq->min_inline_mode != MLX5_INLINE_MODE_NONE) {
1507                         inline_hdr_sz = MLX5E_XDP_MIN_INLINE;
1508                         ds_cnt++;
1509                 }
1510
1511                 /* Pre initialize fixed WQE fields */
1512                 for (i = 0; i < mlx5_wq_cyc_get_size(&sq->wq); i++) {
1513                         struct mlx5e_xdp_wqe_info *wi  = &sq->db.wqe_info[i];
1514                         struct mlx5e_tx_wqe      *wqe  = mlx5_wq_cyc_get_wqe(&sq->wq, i);
1515                         struct mlx5_wqe_ctrl_seg *cseg = &wqe->ctrl;
1516                         struct mlx5_wqe_eth_seg  *eseg = &wqe->eth;
1517                         struct mlx5_wqe_data_seg *dseg;
1518
1519                         cseg->qpn_ds = cpu_to_be32((sq->sqn << 8) | ds_cnt);
1520                         eseg->inline_hdr.sz = cpu_to_be16(inline_hdr_sz);
1521
1522                         dseg = (struct mlx5_wqe_data_seg *)cseg + (ds_cnt - 1);
1523                         dseg->lkey = sq->mkey_be;
1524
1525                         wi->num_wqebbs = 1;
1526                         wi->num_ds     = 1;
1527                 }
1528         }
1529
1530         return 0;
1531
1532 err_free_xdpsq:
1533         clear_bit(MLX5E_SQ_STATE_ENABLED, &sq->state);
1534         mlx5e_free_xdpsq(sq);
1535
1536         return err;
1537 }
1538
1539 static void mlx5e_close_xdpsq(struct mlx5e_xdpsq *sq, struct mlx5e_rq *rq)
1540 {
1541         struct mlx5e_channel *c = sq->channel;
1542
1543         clear_bit(MLX5E_SQ_STATE_ENABLED, &sq->state);
1544         napi_synchronize(&c->napi);
1545
1546         mlx5e_destroy_sq(c->mdev, sq->sqn);
1547         mlx5e_free_xdpsq_descs(sq, rq);
1548         mlx5e_free_xdpsq(sq);
1549 }
1550
1551 static int mlx5e_alloc_cq_common(struct mlx5_core_dev *mdev,
1552                                  struct mlx5e_cq_param *param,
1553                                  struct mlx5e_cq *cq)
1554 {
1555         struct mlx5_core_cq *mcq = &cq->mcq;
1556         int eqn_not_used;
1557         unsigned int irqn;
1558         int err;
1559         u32 i;
1560
1561         err = mlx5_vector2eqn(mdev, param->eq_ix, &eqn_not_used, &irqn);
1562         if (err)
1563                 return err;
1564
1565         err = mlx5_cqwq_create(mdev, &param->wq, param->cqc, &cq->wq,
1566                                &cq->wq_ctrl);
1567         if (err)
1568                 return err;
1569
1570         mcq->cqe_sz     = 64;
1571         mcq->set_ci_db  = cq->wq_ctrl.db.db;
1572         mcq->arm_db     = cq->wq_ctrl.db.db + 1;
1573         *mcq->set_ci_db = 0;
1574         *mcq->arm_db    = 0;
1575         mcq->vector     = param->eq_ix;
1576         mcq->comp       = mlx5e_completion_event;
1577         mcq->event      = mlx5e_cq_error_event;
1578         mcq->irqn       = irqn;
1579
1580         for (i = 0; i < mlx5_cqwq_get_size(&cq->wq); i++) {
1581                 struct mlx5_cqe64 *cqe = mlx5_cqwq_get_wqe(&cq->wq, i);
1582
1583                 cqe->op_own = 0xf1;
1584         }
1585
1586         cq->mdev = mdev;
1587
1588         return 0;
1589 }
1590
1591 static int mlx5e_alloc_cq(struct mlx5e_channel *c,
1592                           struct mlx5e_cq_param *param,
1593                           struct mlx5e_cq *cq)
1594 {
1595         struct mlx5_core_dev *mdev = c->priv->mdev;
1596         int err;
1597
1598         param->wq.buf_numa_node = cpu_to_node(c->cpu);
1599         param->wq.db_numa_node  = cpu_to_node(c->cpu);
1600         param->eq_ix   = c->ix;
1601
1602         err = mlx5e_alloc_cq_common(mdev, param, cq);
1603
1604         cq->napi    = &c->napi;
1605         cq->channel = c;
1606
1607         return err;
1608 }
1609
1610 static void mlx5e_free_cq(struct mlx5e_cq *cq)
1611 {
1612         mlx5_wq_destroy(&cq->wq_ctrl);
1613 }
1614
1615 static int mlx5e_create_cq(struct mlx5e_cq *cq, struct mlx5e_cq_param *param)
1616 {
1617         struct mlx5_core_dev *mdev = cq->mdev;
1618         struct mlx5_core_cq *mcq = &cq->mcq;
1619
1620         void *in;
1621         void *cqc;
1622         int inlen;
1623         unsigned int irqn_not_used;
1624         int eqn;
1625         int err;
1626
1627         err = mlx5_vector2eqn(mdev, param->eq_ix, &eqn, &irqn_not_used);
1628         if (err)
1629                 return err;
1630
1631         inlen = MLX5_ST_SZ_BYTES(create_cq_in) +
1632                 sizeof(u64) * cq->wq_ctrl.buf.npages;
1633         in = kvzalloc(inlen, GFP_KERNEL);
1634         if (!in)
1635                 return -ENOMEM;
1636
1637         cqc = MLX5_ADDR_OF(create_cq_in, in, cq_context);
1638
1639         memcpy(cqc, param->cqc, sizeof(param->cqc));
1640
1641         mlx5_fill_page_frag_array(&cq->wq_ctrl.buf,
1642                                   (__be64 *)MLX5_ADDR_OF(create_cq_in, in, pas));
1643
1644         MLX5_SET(cqc,   cqc, cq_period_mode, param->cq_period_mode);
1645         MLX5_SET(cqc,   cqc, c_eqn,         eqn);
1646         MLX5_SET(cqc,   cqc, uar_page,      mdev->priv.uar->index);
1647         MLX5_SET(cqc,   cqc, log_page_size, cq->wq_ctrl.buf.page_shift -
1648                                             MLX5_ADAPTER_PAGE_SHIFT);
1649         MLX5_SET64(cqc, cqc, dbr_addr,      cq->wq_ctrl.db.dma);
1650
1651         err = mlx5_core_create_cq(mdev, mcq, in, inlen);
1652
1653         kvfree(in);
1654
1655         if (err)
1656                 return err;
1657
1658         mlx5e_cq_arm(cq);
1659
1660         return 0;
1661 }
1662
1663 static void mlx5e_destroy_cq(struct mlx5e_cq *cq)
1664 {
1665         mlx5_core_destroy_cq(cq->mdev, &cq->mcq);
1666 }
1667
1668 static int mlx5e_open_cq(struct mlx5e_channel *c,
1669                          struct net_dim_cq_moder moder,
1670                          struct mlx5e_cq_param *param,
1671                          struct mlx5e_cq *cq)
1672 {
1673         struct mlx5_core_dev *mdev = c->mdev;
1674         int err;
1675
1676         err = mlx5e_alloc_cq(c, param, cq);
1677         if (err)
1678                 return err;
1679
1680         err = mlx5e_create_cq(cq, param);
1681         if (err)
1682                 goto err_free_cq;
1683
1684         if (MLX5_CAP_GEN(mdev, cq_moderation))
1685                 mlx5_core_modify_cq_moderation(mdev, &cq->mcq, moder.usec, moder.pkts);
1686         return 0;
1687
1688 err_free_cq:
1689         mlx5e_free_cq(cq);
1690
1691         return err;
1692 }
1693
1694 static void mlx5e_close_cq(struct mlx5e_cq *cq)
1695 {
1696         mlx5e_destroy_cq(cq);
1697         mlx5e_free_cq(cq);
1698 }
1699
1700 static int mlx5e_open_tx_cqs(struct mlx5e_channel *c,
1701                              struct mlx5e_params *params,
1702                              struct mlx5e_channel_param *cparam)
1703 {
1704         int err;
1705         int tc;
1706
1707         for (tc = 0; tc < c->num_tc; tc++) {
1708                 err = mlx5e_open_cq(c, params->tx_cq_moderation,
1709                                     &cparam->tx_cq, &c->sq[tc].cq);
1710                 if (err)
1711                         goto err_close_tx_cqs;
1712         }
1713
1714         return 0;
1715
1716 err_close_tx_cqs:
1717         for (tc--; tc >= 0; tc--)
1718                 mlx5e_close_cq(&c->sq[tc].cq);
1719
1720         return err;
1721 }
1722
1723 static void mlx5e_close_tx_cqs(struct mlx5e_channel *c)
1724 {
1725         int tc;
1726
1727         for (tc = 0; tc < c->num_tc; tc++)
1728                 mlx5e_close_cq(&c->sq[tc].cq);
1729 }
1730
1731 static int mlx5e_open_sqs(struct mlx5e_channel *c,
1732                           struct mlx5e_params *params,
1733                           struct mlx5e_channel_param *cparam)
1734 {
1735         struct mlx5e_priv *priv = c->priv;
1736         int err, tc, max_nch = mlx5e_get_netdev_max_channels(priv->netdev);
1737
1738         for (tc = 0; tc < params->num_tc; tc++) {
1739                 int txq_ix = c->ix + tc * max_nch;
1740
1741                 err = mlx5e_open_txqsq(c, c->priv->tisn[tc], txq_ix,
1742                                        params, &cparam->sq, &c->sq[tc], tc);
1743                 if (err)
1744                         goto err_close_sqs;
1745         }
1746
1747         return 0;
1748
1749 err_close_sqs:
1750         for (tc--; tc >= 0; tc--)
1751                 mlx5e_close_txqsq(&c->sq[tc]);
1752
1753         return err;
1754 }
1755
1756 static void mlx5e_close_sqs(struct mlx5e_channel *c)
1757 {
1758         int tc;
1759
1760         for (tc = 0; tc < c->num_tc; tc++)
1761                 mlx5e_close_txqsq(&c->sq[tc]);
1762 }
1763
1764 static int mlx5e_set_sq_maxrate(struct net_device *dev,
1765                                 struct mlx5e_txqsq *sq, u32 rate)
1766 {
1767         struct mlx5e_priv *priv = netdev_priv(dev);
1768         struct mlx5_core_dev *mdev = priv->mdev;
1769         struct mlx5e_modify_sq_param msp = {0};
1770         struct mlx5_rate_limit rl = {0};
1771         u16 rl_index = 0;
1772         int err;
1773
1774         if (rate == sq->rate_limit)
1775                 /* nothing to do */
1776                 return 0;
1777
1778         if (sq->rate_limit) {
1779                 rl.rate = sq->rate_limit;
1780                 /* remove current rl index to free space to next ones */
1781                 mlx5_rl_remove_rate(mdev, &rl);
1782         }
1783
1784         sq->rate_limit = 0;
1785
1786         if (rate) {
1787                 rl.rate = rate;
1788                 err = mlx5_rl_add_rate(mdev, &rl_index, &rl);
1789                 if (err) {
1790                         netdev_err(dev, "Failed configuring rate %u: %d\n",
1791                                    rate, err);
1792                         return err;
1793                 }
1794         }
1795
1796         msp.curr_state = MLX5_SQC_STATE_RDY;
1797         msp.next_state = MLX5_SQC_STATE_RDY;
1798         msp.rl_index   = rl_index;
1799         msp.rl_update  = true;
1800         err = mlx5e_modify_sq(mdev, sq->sqn, &msp);
1801         if (err) {
1802                 netdev_err(dev, "Failed configuring rate %u: %d\n",
1803                            rate, err);
1804                 /* remove the rate from the table */
1805                 if (rate)
1806                         mlx5_rl_remove_rate(mdev, &rl);
1807                 return err;
1808         }
1809
1810         sq->rate_limit = rate;
1811         return 0;
1812 }
1813
1814 static int mlx5e_set_tx_maxrate(struct net_device *dev, int index, u32 rate)
1815 {
1816         struct mlx5e_priv *priv = netdev_priv(dev);
1817         struct mlx5_core_dev *mdev = priv->mdev;
1818         struct mlx5e_txqsq *sq = priv->txq2sq[index];
1819         int err = 0;
1820
1821         if (!mlx5_rl_is_supported(mdev)) {
1822                 netdev_err(dev, "Rate limiting is not supported on this device\n");
1823                 return -EINVAL;
1824         }
1825
1826         /* rate is given in Mb/sec, HW config is in Kb/sec */
1827         rate = rate << 10;
1828
1829         /* Check whether rate in valid range, 0 is always valid */
1830         if (rate && !mlx5_rl_is_in_range(mdev, rate)) {
1831                 netdev_err(dev, "TX rate %u, is not in range\n", rate);
1832                 return -ERANGE;
1833         }
1834
1835         mutex_lock(&priv->state_lock);
1836         if (test_bit(MLX5E_STATE_OPENED, &priv->state))
1837                 err = mlx5e_set_sq_maxrate(dev, sq, rate);
1838         if (!err)
1839                 priv->tx_rates[index] = rate;
1840         mutex_unlock(&priv->state_lock);
1841
1842         return err;
1843 }
1844
1845 static int mlx5e_alloc_xps_cpumask(struct mlx5e_channel *c,
1846                                    struct mlx5e_params *params)
1847 {
1848         int num_comp_vectors = mlx5_comp_vectors_count(c->mdev);
1849         int irq;
1850
1851         if (!zalloc_cpumask_var(&c->xps_cpumask, GFP_KERNEL))
1852                 return -ENOMEM;
1853
1854         for (irq = c->ix; irq < num_comp_vectors; irq += params->num_channels) {
1855                 int cpu = cpumask_first(mlx5_comp_irq_get_affinity_mask(c->mdev, irq));
1856
1857                 cpumask_set_cpu(cpu, c->xps_cpumask);
1858         }
1859
1860         return 0;
1861 }
1862
1863 static void mlx5e_free_xps_cpumask(struct mlx5e_channel *c)
1864 {
1865         free_cpumask_var(c->xps_cpumask);
1866 }
1867
1868 static int mlx5e_open_channel(struct mlx5e_priv *priv, int ix,
1869                               struct mlx5e_params *params,
1870                               struct mlx5e_channel_param *cparam,
1871                               struct mlx5e_channel **cp)
1872 {
1873         int cpu = cpumask_first(mlx5_comp_irq_get_affinity_mask(priv->mdev, ix));
1874         struct net_dim_cq_moder icocq_moder = {0, 0};
1875         struct net_device *netdev = priv->netdev;
1876         struct mlx5e_channel *c;
1877         unsigned int irq;
1878         int err;
1879         int eqn;
1880
1881         err = mlx5_vector2eqn(priv->mdev, ix, &eqn, &irq);
1882         if (err)
1883                 return err;
1884
1885         c = kvzalloc_node(sizeof(*c), GFP_KERNEL, cpu_to_node(cpu));
1886         if (!c)
1887                 return -ENOMEM;
1888
1889         c->priv     = priv;
1890         c->mdev     = priv->mdev;
1891         c->tstamp   = &priv->tstamp;
1892         c->ix       = ix;
1893         c->cpu      = cpu;
1894         c->pdev     = &priv->mdev->pdev->dev;
1895         c->netdev   = priv->netdev;
1896         c->mkey_be  = cpu_to_be32(priv->mdev->mlx5e_res.mkey.key);
1897         c->num_tc   = params->num_tc;
1898         c->xdp      = !!params->xdp_prog;
1899         c->stats    = &priv->channel_stats[ix].ch;
1900         c->irq_desc = irq_to_desc(irq);
1901
1902         err = mlx5e_alloc_xps_cpumask(c, params);
1903         if (err)
1904                 goto err_free_channel;
1905
1906         netif_napi_add(netdev, &c->napi, mlx5e_napi_poll, 64);
1907
1908         err = mlx5e_open_cq(c, icocq_moder, &cparam->icosq_cq, &c->icosq.cq);
1909         if (err)
1910                 goto err_napi_del;
1911
1912         err = mlx5e_open_tx_cqs(c, params, cparam);
1913         if (err)
1914                 goto err_close_icosq_cq;
1915
1916         err = mlx5e_open_cq(c, params->tx_cq_moderation, &cparam->tx_cq, &c->xdpsq.cq);
1917         if (err)
1918                 goto err_close_tx_cqs;
1919
1920         err = mlx5e_open_cq(c, params->rx_cq_moderation, &cparam->rx_cq, &c->rq.cq);
1921         if (err)
1922                 goto err_close_xdp_tx_cqs;
1923
1924         /* XDP SQ CQ params are same as normal TXQ sq CQ params */
1925         err = c->xdp ? mlx5e_open_cq(c, params->tx_cq_moderation,
1926                                      &cparam->tx_cq, &c->rq.xdpsq.cq) : 0;
1927         if (err)
1928                 goto err_close_rx_cq;
1929
1930         napi_enable(&c->napi);
1931
1932         err = mlx5e_open_icosq(c, params, &cparam->icosq, &c->icosq);
1933         if (err)
1934                 goto err_disable_napi;
1935
1936         err = mlx5e_open_sqs(c, params, cparam);
1937         if (err)
1938                 goto err_close_icosq;
1939
1940         err = c->xdp ? mlx5e_open_xdpsq(c, params, &cparam->xdp_sq, &c->rq.xdpsq, false) : 0;
1941         if (err)
1942                 goto err_close_sqs;
1943
1944         err = mlx5e_open_rq(c, params, &cparam->rq, &c->rq);
1945         if (err)
1946                 goto err_close_xdp_sq;
1947
1948         err = mlx5e_open_xdpsq(c, params, &cparam->xdp_sq, &c->xdpsq, true);
1949         if (err)
1950                 goto err_close_rq;
1951
1952         *cp = c;
1953
1954         return 0;
1955
1956 err_close_rq:
1957         mlx5e_close_rq(&c->rq);
1958
1959 err_close_xdp_sq:
1960         if (c->xdp)
1961                 mlx5e_close_xdpsq(&c->rq.xdpsq, &c->rq);
1962
1963 err_close_sqs:
1964         mlx5e_close_sqs(c);
1965
1966 err_close_icosq:
1967         mlx5e_close_icosq(&c->icosq);
1968
1969 err_disable_napi:
1970         napi_disable(&c->napi);
1971         if (c->xdp)
1972                 mlx5e_close_cq(&c->rq.xdpsq.cq);
1973
1974 err_close_rx_cq:
1975         mlx5e_close_cq(&c->rq.cq);
1976
1977 err_close_xdp_tx_cqs:
1978         mlx5e_close_cq(&c->xdpsq.cq);
1979
1980 err_close_tx_cqs:
1981         mlx5e_close_tx_cqs(c);
1982
1983 err_close_icosq_cq:
1984         mlx5e_close_cq(&c->icosq.cq);
1985
1986 err_napi_del:
1987         netif_napi_del(&c->napi);
1988         mlx5e_free_xps_cpumask(c);
1989
1990 err_free_channel:
1991         kvfree(c);
1992
1993         return err;
1994 }
1995
1996 static void mlx5e_activate_channel(struct mlx5e_channel *c)
1997 {
1998         int tc;
1999
2000         for (tc = 0; tc < c->num_tc; tc++)
2001                 mlx5e_activate_txqsq(&c->sq[tc]);
2002         mlx5e_activate_rq(&c->rq);
2003         netif_set_xps_queue(c->netdev, c->xps_cpumask, c->ix);
2004 }
2005
2006 static void mlx5e_deactivate_channel(struct mlx5e_channel *c)
2007 {
2008         int tc;
2009
2010         mlx5e_deactivate_rq(&c->rq);
2011         for (tc = 0; tc < c->num_tc; tc++)
2012                 mlx5e_deactivate_txqsq(&c->sq[tc]);
2013 }
2014
2015 static void mlx5e_close_channel(struct mlx5e_channel *c)
2016 {
2017         mlx5e_close_xdpsq(&c->xdpsq, NULL);
2018         mlx5e_close_rq(&c->rq);
2019         if (c->xdp)
2020                 mlx5e_close_xdpsq(&c->rq.xdpsq, &c->rq);
2021         mlx5e_close_sqs(c);
2022         mlx5e_close_icosq(&c->icosq);
2023         napi_disable(&c->napi);
2024         if (c->xdp)
2025                 mlx5e_close_cq(&c->rq.xdpsq.cq);
2026         mlx5e_close_cq(&c->rq.cq);
2027         mlx5e_close_cq(&c->xdpsq.cq);
2028         mlx5e_close_tx_cqs(c);
2029         mlx5e_close_cq(&c->icosq.cq);
2030         netif_napi_del(&c->napi);
2031         mlx5e_free_xps_cpumask(c);
2032
2033         kvfree(c);
2034 }
2035
2036 #define DEFAULT_FRAG_SIZE (2048)
2037
2038 static void mlx5e_build_rq_frags_info(struct mlx5_core_dev *mdev,
2039                                       struct mlx5e_params *params,
2040                                       struct mlx5e_rq_frags_info *info)
2041 {
2042         u32 byte_count = MLX5E_SW2HW_MTU(params, params->sw_mtu);
2043         int frag_size_max = DEFAULT_FRAG_SIZE;
2044         u32 buf_size = 0;
2045         int i;
2046
2047 #ifdef CONFIG_MLX5_EN_IPSEC
2048         if (MLX5_IPSEC_DEV(mdev))
2049                 byte_count += MLX5E_METADATA_ETHER_LEN;
2050 #endif
2051
2052         if (mlx5e_rx_is_linear_skb(mdev, params)) {
2053                 int frag_stride;
2054
2055                 frag_stride = mlx5e_rx_get_linear_frag_sz(params);
2056                 frag_stride = roundup_pow_of_two(frag_stride);
2057
2058                 info->arr[0].frag_size = byte_count;
2059                 info->arr[0].frag_stride = frag_stride;
2060                 info->num_frags = 1;
2061                 info->wqe_bulk = PAGE_SIZE / frag_stride;
2062                 goto out;
2063         }
2064
2065         if (byte_count > PAGE_SIZE +
2066             (MLX5E_MAX_RX_FRAGS - 1) * frag_size_max)
2067                 frag_size_max = PAGE_SIZE;
2068
2069         i = 0;
2070         while (buf_size < byte_count) {
2071                 int frag_size = byte_count - buf_size;
2072
2073                 if (i < MLX5E_MAX_RX_FRAGS - 1)
2074                         frag_size = min(frag_size, frag_size_max);
2075
2076                 info->arr[i].frag_size = frag_size;
2077                 info->arr[i].frag_stride = roundup_pow_of_two(frag_size);
2078
2079                 buf_size += frag_size;
2080                 i++;
2081         }
2082         info->num_frags = i;
2083         /* number of different wqes sharing a page */
2084         info->wqe_bulk = 1 + (info->num_frags % 2);
2085
2086 out:
2087         info->wqe_bulk = max_t(u8, info->wqe_bulk, 8);
2088         info->log_num_frags = order_base_2(info->num_frags);
2089 }
2090
2091 static inline u8 mlx5e_get_rqwq_log_stride(u8 wq_type, int ndsegs)
2092 {
2093         int sz = sizeof(struct mlx5_wqe_data_seg) * ndsegs;
2094
2095         switch (wq_type) {
2096         case MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ:
2097                 sz += sizeof(struct mlx5e_rx_wqe_ll);
2098                 break;
2099         default: /* MLX5_WQ_TYPE_CYCLIC */
2100                 sz += sizeof(struct mlx5e_rx_wqe_cyc);
2101         }
2102
2103         return order_base_2(sz);
2104 }
2105
2106 static void mlx5e_build_rq_param(struct mlx5e_priv *priv,
2107                                  struct mlx5e_params *params,
2108                                  struct mlx5e_rq_param *param)
2109 {
2110         struct mlx5_core_dev *mdev = priv->mdev;
2111         void *rqc = param->rqc;
2112         void *wq = MLX5_ADDR_OF(rqc, rqc, wq);
2113         int ndsegs = 1;
2114
2115         switch (params->rq_wq_type) {
2116         case MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ:
2117                 MLX5_SET(wq, wq, log_wqe_num_of_strides,
2118                          mlx5e_mpwqe_get_log_num_strides(mdev, params) -
2119                          MLX5_MPWQE_LOG_NUM_STRIDES_BASE);
2120                 MLX5_SET(wq, wq, log_wqe_stride_size,
2121                          mlx5e_mpwqe_get_log_stride_size(mdev, params) -
2122                          MLX5_MPWQE_LOG_STRIDE_SZ_BASE);
2123                 MLX5_SET(wq, wq, log_wq_sz, mlx5e_mpwqe_get_log_rq_size(params));
2124                 break;
2125         default: /* MLX5_WQ_TYPE_CYCLIC */
2126                 MLX5_SET(wq, wq, log_wq_sz, params->log_rq_mtu_frames);
2127                 mlx5e_build_rq_frags_info(mdev, params, &param->frags_info);
2128                 ndsegs = param->frags_info.num_frags;
2129         }
2130
2131         MLX5_SET(wq, wq, wq_type,          params->rq_wq_type);
2132         MLX5_SET(wq, wq, end_padding_mode, MLX5_WQ_END_PAD_MODE_ALIGN);
2133         MLX5_SET(wq, wq, log_wq_stride,
2134                  mlx5e_get_rqwq_log_stride(params->rq_wq_type, ndsegs));
2135         MLX5_SET(wq, wq, pd,               mdev->mlx5e_res.pdn);
2136         MLX5_SET(rqc, rqc, counter_set_id, priv->q_counter);
2137         MLX5_SET(rqc, rqc, vsd,            params->vlan_strip_disable);
2138         MLX5_SET(rqc, rqc, scatter_fcs,    params->scatter_fcs_en);
2139
2140         param->wq.buf_numa_node = dev_to_node(&mdev->pdev->dev);
2141 }
2142
2143 static void mlx5e_build_drop_rq_param(struct mlx5e_priv *priv,
2144                                       struct mlx5e_rq_param *param)
2145 {
2146         struct mlx5_core_dev *mdev = priv->mdev;
2147         void *rqc = param->rqc;
2148         void *wq = MLX5_ADDR_OF(rqc, rqc, wq);
2149
2150         MLX5_SET(wq, wq, wq_type, MLX5_WQ_TYPE_CYCLIC);
2151         MLX5_SET(wq, wq, log_wq_stride,
2152                  mlx5e_get_rqwq_log_stride(MLX5_WQ_TYPE_CYCLIC, 1));
2153         MLX5_SET(rqc, rqc, counter_set_id, priv->drop_rq_q_counter);
2154
2155         param->wq.buf_numa_node = dev_to_node(&mdev->pdev->dev);
2156 }
2157
2158 static void mlx5e_build_sq_param_common(struct mlx5e_priv *priv,
2159                                         struct mlx5e_sq_param *param)
2160 {
2161         void *sqc = param->sqc;
2162         void *wq = MLX5_ADDR_OF(sqc, sqc, wq);
2163
2164         MLX5_SET(wq, wq, log_wq_stride, ilog2(MLX5_SEND_WQE_BB));
2165         MLX5_SET(wq, wq, pd,            priv->mdev->mlx5e_res.pdn);
2166
2167         param->wq.buf_numa_node = dev_to_node(&priv->mdev->pdev->dev);
2168 }
2169
2170 static void mlx5e_build_sq_param(struct mlx5e_priv *priv,
2171                                  struct mlx5e_params *params,
2172                                  struct mlx5e_sq_param *param)
2173 {
2174         void *sqc = param->sqc;
2175         void *wq = MLX5_ADDR_OF(sqc, sqc, wq);
2176
2177         mlx5e_build_sq_param_common(priv, param);
2178         MLX5_SET(wq, wq, log_wq_sz, params->log_sq_size);
2179         MLX5_SET(sqc, sqc, allow_swp, !!MLX5_IPSEC_DEV(priv->mdev));
2180 }
2181
2182 static void mlx5e_build_common_cq_param(struct mlx5e_priv *priv,
2183                                         struct mlx5e_cq_param *param)
2184 {
2185         void *cqc = param->cqc;
2186
2187         MLX5_SET(cqc, cqc, uar_page, priv->mdev->priv.uar->index);
2188         if (MLX5_CAP_GEN(priv->mdev, cqe_128_always) && cache_line_size() >= 128)
2189                 MLX5_SET(cqc, cqc, cqe_sz, CQE_STRIDE_128_PAD);
2190 }
2191
2192 static void mlx5e_build_rx_cq_param(struct mlx5e_priv *priv,
2193                                     struct mlx5e_params *params,
2194                                     struct mlx5e_cq_param *param)
2195 {
2196         struct mlx5_core_dev *mdev = priv->mdev;
2197         void *cqc = param->cqc;
2198         u8 log_cq_size;
2199
2200         switch (params->rq_wq_type) {
2201         case MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ:
2202                 log_cq_size = mlx5e_mpwqe_get_log_rq_size(params) +
2203                         mlx5e_mpwqe_get_log_num_strides(mdev, params);
2204                 break;
2205         default: /* MLX5_WQ_TYPE_CYCLIC */
2206                 log_cq_size = params->log_rq_mtu_frames;
2207         }
2208
2209         MLX5_SET(cqc, cqc, log_cq_size, log_cq_size);
2210         if (MLX5E_GET_PFLAG(params, MLX5E_PFLAG_RX_CQE_COMPRESS)) {
2211                 MLX5_SET(cqc, cqc, mini_cqe_res_format, MLX5_CQE_FORMAT_CSUM);
2212                 MLX5_SET(cqc, cqc, cqe_comp_en, 1);
2213         }
2214
2215         mlx5e_build_common_cq_param(priv, param);
2216         param->cq_period_mode = params->rx_cq_moderation.cq_period_mode;
2217 }
2218
2219 static void mlx5e_build_tx_cq_param(struct mlx5e_priv *priv,
2220                                     struct mlx5e_params *params,
2221                                     struct mlx5e_cq_param *param)
2222 {
2223         void *cqc = param->cqc;
2224
2225         MLX5_SET(cqc, cqc, log_cq_size, params->log_sq_size);
2226
2227         mlx5e_build_common_cq_param(priv, param);
2228         param->cq_period_mode = params->tx_cq_moderation.cq_period_mode;
2229 }
2230
2231 static void mlx5e_build_ico_cq_param(struct mlx5e_priv *priv,
2232                                      u8 log_wq_size,
2233                                      struct mlx5e_cq_param *param)
2234 {
2235         void *cqc = param->cqc;
2236
2237         MLX5_SET(cqc, cqc, log_cq_size, log_wq_size);
2238
2239         mlx5e_build_common_cq_param(priv, param);
2240
2241         param->cq_period_mode = NET_DIM_CQ_PERIOD_MODE_START_FROM_EQE;
2242 }
2243
2244 static void mlx5e_build_icosq_param(struct mlx5e_priv *priv,
2245                                     u8 log_wq_size,
2246                                     struct mlx5e_sq_param *param)
2247 {
2248         void *sqc = param->sqc;
2249         void *wq = MLX5_ADDR_OF(sqc, sqc, wq);
2250
2251         mlx5e_build_sq_param_common(priv, param);
2252
2253         MLX5_SET(wq, wq, log_wq_sz, log_wq_size);
2254         MLX5_SET(sqc, sqc, reg_umr, MLX5_CAP_ETH(priv->mdev, reg_umr_sq));
2255 }
2256
2257 static void mlx5e_build_xdpsq_param(struct mlx5e_priv *priv,
2258                                     struct mlx5e_params *params,
2259                                     struct mlx5e_sq_param *param)
2260 {
2261         void *sqc = param->sqc;
2262         void *wq = MLX5_ADDR_OF(sqc, sqc, wq);
2263
2264         mlx5e_build_sq_param_common(priv, param);
2265         MLX5_SET(wq, wq, log_wq_sz, params->log_sq_size);
2266         param->is_mpw = MLX5E_GET_PFLAG(params, MLX5E_PFLAG_XDP_TX_MPWQE);
2267 }
2268
2269 static void mlx5e_build_channel_param(struct mlx5e_priv *priv,
2270                                       struct mlx5e_params *params,
2271                                       struct mlx5e_channel_param *cparam)
2272 {
2273         u8 icosq_log_wq_sz = MLX5E_PARAMS_MINIMUM_LOG_SQ_SIZE;
2274
2275         mlx5e_build_rq_param(priv, params, &cparam->rq);
2276         mlx5e_build_sq_param(priv, params, &cparam->sq);
2277         mlx5e_build_xdpsq_param(priv, params, &cparam->xdp_sq);
2278         mlx5e_build_icosq_param(priv, icosq_log_wq_sz, &cparam->icosq);
2279         mlx5e_build_rx_cq_param(priv, params, &cparam->rx_cq);
2280         mlx5e_build_tx_cq_param(priv, params, &cparam->tx_cq);
2281         mlx5e_build_ico_cq_param(priv, icosq_log_wq_sz, &cparam->icosq_cq);
2282 }
2283
2284 int mlx5e_open_channels(struct mlx5e_priv *priv,
2285                         struct mlx5e_channels *chs)
2286 {
2287         struct mlx5e_channel_param *cparam;
2288         int err = -ENOMEM;
2289         int i;
2290
2291         chs->num = chs->params.num_channels;
2292
2293         chs->c = kcalloc(chs->num, sizeof(struct mlx5e_channel *), GFP_KERNEL);
2294         cparam = kvzalloc(sizeof(struct mlx5e_channel_param), GFP_KERNEL);
2295         if (!chs->c || !cparam)
2296                 goto err_free;
2297
2298         mlx5e_build_channel_param(priv, &chs->params, cparam);
2299         for (i = 0; i < chs->num; i++) {
2300                 err = mlx5e_open_channel(priv, i, &chs->params, cparam, &chs->c[i]);
2301                 if (err)
2302                         goto err_close_channels;
2303         }
2304
2305         if (!IS_ERR_OR_NULL(priv->tx_reporter))
2306                 devlink_health_reporter_state_update(priv->tx_reporter,
2307                                                      DEVLINK_HEALTH_REPORTER_STATE_HEALTHY);
2308
2309         kvfree(cparam);
2310         return 0;
2311
2312 err_close_channels:
2313         for (i--; i >= 0; i--)
2314                 mlx5e_close_channel(chs->c[i]);
2315
2316 err_free:
2317         kfree(chs->c);
2318         kvfree(cparam);
2319         chs->num = 0;
2320         return err;
2321 }
2322
2323 static void mlx5e_activate_channels(struct mlx5e_channels *chs)
2324 {
2325         int i;
2326
2327         for (i = 0; i < chs->num; i++)
2328                 mlx5e_activate_channel(chs->c[i]);
2329 }
2330
2331 static int mlx5e_wait_channels_min_rx_wqes(struct mlx5e_channels *chs)
2332 {
2333         int err = 0;
2334         int i;
2335
2336         for (i = 0; i < chs->num; i++)
2337                 err |= mlx5e_wait_for_min_rx_wqes(&chs->c[i]->rq,
2338                                                   err ? 0 : 20000);
2339
2340         return err ? -ETIMEDOUT : 0;
2341 }
2342
2343 static void mlx5e_deactivate_channels(struct mlx5e_channels *chs)
2344 {
2345         int i;
2346
2347         for (i = 0; i < chs->num; i++)
2348                 mlx5e_deactivate_channel(chs->c[i]);
2349 }
2350
2351 void mlx5e_close_channels(struct mlx5e_channels *chs)
2352 {
2353         int i;
2354
2355         for (i = 0; i < chs->num; i++)
2356                 mlx5e_close_channel(chs->c[i]);
2357
2358         kfree(chs->c);
2359         chs->num = 0;
2360 }
2361
2362 static int
2363 mlx5e_create_rqt(struct mlx5e_priv *priv, int sz, struct mlx5e_rqt *rqt)
2364 {
2365         struct mlx5_core_dev *mdev = priv->mdev;
2366         void *rqtc;
2367         int inlen;
2368         int err;
2369         u32 *in;
2370         int i;
2371
2372         inlen = MLX5_ST_SZ_BYTES(create_rqt_in) + sizeof(u32) * sz;
2373         in = kvzalloc(inlen, GFP_KERNEL);
2374         if (!in)
2375                 return -ENOMEM;
2376
2377         rqtc = MLX5_ADDR_OF(create_rqt_in, in, rqt_context);
2378
2379         MLX5_SET(rqtc, rqtc, rqt_actual_size, sz);
2380         MLX5_SET(rqtc, rqtc, rqt_max_size, sz);
2381
2382         for (i = 0; i < sz; i++)
2383                 MLX5_SET(rqtc, rqtc, rq_num[i], priv->drop_rq.rqn);
2384
2385         err = mlx5_core_create_rqt(mdev, in, inlen, &rqt->rqtn);
2386         if (!err)
2387                 rqt->enabled = true;
2388
2389         kvfree(in);
2390         return err;
2391 }
2392
2393 void mlx5e_destroy_rqt(struct mlx5e_priv *priv, struct mlx5e_rqt *rqt)
2394 {
2395         rqt->enabled = false;
2396         mlx5_core_destroy_rqt(priv->mdev, rqt->rqtn);
2397 }
2398
2399 int mlx5e_create_indirect_rqt(struct mlx5e_priv *priv)
2400 {
2401         struct mlx5e_rqt *rqt = &priv->indir_rqt;
2402         int err;
2403
2404         err = mlx5e_create_rqt(priv, MLX5E_INDIR_RQT_SIZE, rqt);
2405         if (err)
2406                 mlx5_core_warn(priv->mdev, "create indirect rqts failed, %d\n", err);
2407         return err;
2408 }
2409
2410 int mlx5e_create_direct_rqts(struct mlx5e_priv *priv)
2411 {
2412         struct mlx5e_rqt *rqt;
2413         int err;
2414         int ix;
2415
2416         for (ix = 0; ix < mlx5e_get_netdev_max_channels(priv->netdev); ix++) {
2417                 rqt = &priv->direct_tir[ix].rqt;
2418                 err = mlx5e_create_rqt(priv, 1 /*size */, rqt);
2419                 if (err)
2420                         goto err_destroy_rqts;
2421         }
2422
2423         return 0;
2424
2425 err_destroy_rqts:
2426         mlx5_core_warn(priv->mdev, "create direct rqts failed, %d\n", err);
2427         for (ix--; ix >= 0; ix--)
2428                 mlx5e_destroy_rqt(priv, &priv->direct_tir[ix].rqt);
2429
2430         return err;
2431 }
2432
2433 void mlx5e_destroy_direct_rqts(struct mlx5e_priv *priv)
2434 {
2435         int i;
2436
2437         for (i = 0; i < mlx5e_get_netdev_max_channels(priv->netdev); i++)
2438                 mlx5e_destroy_rqt(priv, &priv->direct_tir[i].rqt);
2439 }
2440
2441 static int mlx5e_rx_hash_fn(int hfunc)
2442 {
2443         return (hfunc == ETH_RSS_HASH_TOP) ?
2444                MLX5_RX_HASH_FN_TOEPLITZ :
2445                MLX5_RX_HASH_FN_INVERTED_XOR8;
2446 }
2447
2448 int mlx5e_bits_invert(unsigned long a, int size)
2449 {
2450         int inv = 0;
2451         int i;
2452
2453         for (i = 0; i < size; i++)
2454                 inv |= (test_bit(size - i - 1, &a) ? 1 : 0) << i;
2455
2456         return inv;
2457 }
2458
2459 static void mlx5e_fill_rqt_rqns(struct mlx5e_priv *priv, int sz,
2460                                 struct mlx5e_redirect_rqt_param rrp, void *rqtc)
2461 {
2462         int i;
2463
2464         for (i = 0; i < sz; i++) {
2465                 u32 rqn;
2466
2467                 if (rrp.is_rss) {
2468                         int ix = i;
2469
2470                         if (rrp.rss.hfunc == ETH_RSS_HASH_XOR)
2471                                 ix = mlx5e_bits_invert(i, ilog2(sz));
2472
2473                         ix = priv->rss_params.indirection_rqt[ix];
2474                         rqn = rrp.rss.channels->c[ix]->rq.rqn;
2475                 } else {
2476                         rqn = rrp.rqn;
2477                 }
2478                 MLX5_SET(rqtc, rqtc, rq_num[i], rqn);
2479         }
2480 }
2481
2482 int mlx5e_redirect_rqt(struct mlx5e_priv *priv, u32 rqtn, int sz,
2483                        struct mlx5e_redirect_rqt_param rrp)
2484 {
2485         struct mlx5_core_dev *mdev = priv->mdev;
2486         void *rqtc;
2487         int inlen;
2488         u32 *in;
2489         int err;
2490
2491         inlen = MLX5_ST_SZ_BYTES(modify_rqt_in) + sizeof(u32) * sz;
2492         in = kvzalloc(inlen, GFP_KERNEL);
2493         if (!in)
2494                 return -ENOMEM;
2495
2496         rqtc = MLX5_ADDR_OF(modify_rqt_in, in, ctx);
2497
2498         MLX5_SET(rqtc, rqtc, rqt_actual_size, sz);
2499         MLX5_SET(modify_rqt_in, in, bitmask.rqn_list, 1);
2500         mlx5e_fill_rqt_rqns(priv, sz, rrp, rqtc);
2501         err = mlx5_core_modify_rqt(mdev, rqtn, in, inlen);
2502
2503         kvfree(in);
2504         return err;
2505 }
2506
2507 static u32 mlx5e_get_direct_rqn(struct mlx5e_priv *priv, int ix,
2508                                 struct mlx5e_redirect_rqt_param rrp)
2509 {
2510         if (!rrp.is_rss)
2511                 return rrp.rqn;
2512
2513         if (ix >= rrp.rss.channels->num)
2514                 return priv->drop_rq.rqn;
2515
2516         return rrp.rss.channels->c[ix]->rq.rqn;
2517 }
2518
2519 static void mlx5e_redirect_rqts(struct mlx5e_priv *priv,
2520                                 struct mlx5e_redirect_rqt_param rrp)
2521 {
2522         u32 rqtn;
2523         int ix;
2524
2525         if (priv->indir_rqt.enabled) {
2526                 /* RSS RQ table */
2527                 rqtn = priv->indir_rqt.rqtn;
2528                 mlx5e_redirect_rqt(priv, rqtn, MLX5E_INDIR_RQT_SIZE, rrp);
2529         }
2530
2531         for (ix = 0; ix < mlx5e_get_netdev_max_channels(priv->netdev); ix++) {
2532                 struct mlx5e_redirect_rqt_param direct_rrp = {
2533                         .is_rss = false,
2534                         {
2535                                 .rqn    = mlx5e_get_direct_rqn(priv, ix, rrp)
2536                         },
2537                 };
2538
2539                 /* Direct RQ Tables */
2540                 if (!priv->direct_tir[ix].rqt.enabled)
2541                         continue;
2542
2543                 rqtn = priv->direct_tir[ix].rqt.rqtn;
2544                 mlx5e_redirect_rqt(priv, rqtn, 1, direct_rrp);
2545         }
2546 }
2547
2548 static void mlx5e_redirect_rqts_to_channels(struct mlx5e_priv *priv,
2549                                             struct mlx5e_channels *chs)
2550 {
2551         struct mlx5e_redirect_rqt_param rrp = {
2552                 .is_rss        = true,
2553                 {
2554                         .rss = {
2555                                 .channels  = chs,
2556                                 .hfunc     = priv->rss_params.hfunc,
2557                         }
2558                 },
2559         };
2560
2561         mlx5e_redirect_rqts(priv, rrp);
2562 }
2563
2564 static void mlx5e_redirect_rqts_to_drop(struct mlx5e_priv *priv)
2565 {
2566         struct mlx5e_redirect_rqt_param drop_rrp = {
2567                 .is_rss = false,
2568                 {
2569                         .rqn = priv->drop_rq.rqn,
2570                 },
2571         };
2572
2573         mlx5e_redirect_rqts(priv, drop_rrp);
2574 }
2575
2576 static const struct mlx5e_tirc_config tirc_default_config[MLX5E_NUM_INDIR_TIRS] = {
2577         [MLX5E_TT_IPV4_TCP] = { .l3_prot_type = MLX5_L3_PROT_TYPE_IPV4,
2578                                 .l4_prot_type = MLX5_L4_PROT_TYPE_TCP,
2579                                 .rx_hash_fields = MLX5_HASH_IP_L4PORTS,
2580         },
2581         [MLX5E_TT_IPV6_TCP] = { .l3_prot_type = MLX5_L3_PROT_TYPE_IPV6,
2582                                 .l4_prot_type = MLX5_L4_PROT_TYPE_TCP,
2583                                 .rx_hash_fields = MLX5_HASH_IP_L4PORTS,
2584         },
2585         [MLX5E_TT_IPV4_UDP] = { .l3_prot_type = MLX5_L3_PROT_TYPE_IPV4,
2586                                 .l4_prot_type = MLX5_L4_PROT_TYPE_UDP,
2587                                 .rx_hash_fields = MLX5_HASH_IP_L4PORTS,
2588         },
2589         [MLX5E_TT_IPV6_UDP] = { .l3_prot_type = MLX5_L3_PROT_TYPE_IPV6,
2590                                 .l4_prot_type = MLX5_L4_PROT_TYPE_UDP,
2591                                 .rx_hash_fields = MLX5_HASH_IP_L4PORTS,
2592         },
2593         [MLX5E_TT_IPV4_IPSEC_AH] = { .l3_prot_type = MLX5_L3_PROT_TYPE_IPV4,
2594                                      .l4_prot_type = 0,
2595                                      .rx_hash_fields = MLX5_HASH_IP_IPSEC_SPI,
2596         },
2597         [MLX5E_TT_IPV6_IPSEC_AH] = { .l3_prot_type = MLX5_L3_PROT_TYPE_IPV6,
2598                                      .l4_prot_type = 0,
2599                                      .rx_hash_fields = MLX5_HASH_IP_IPSEC_SPI,
2600         },
2601         [MLX5E_TT_IPV4_IPSEC_ESP] = { .l3_prot_type = MLX5_L3_PROT_TYPE_IPV4,
2602                                       .l4_prot_type = 0,
2603                                       .rx_hash_fields = MLX5_HASH_IP_IPSEC_SPI,
2604         },
2605         [MLX5E_TT_IPV6_IPSEC_ESP] = { .l3_prot_type = MLX5_L3_PROT_TYPE_IPV6,
2606                                       .l4_prot_type = 0,
2607                                       .rx_hash_fields = MLX5_HASH_IP_IPSEC_SPI,
2608         },
2609         [MLX5E_TT_IPV4] = { .l3_prot_type = MLX5_L3_PROT_TYPE_IPV4,
2610                             .l4_prot_type = 0,
2611                             .rx_hash_fields = MLX5_HASH_IP,
2612         },
2613         [MLX5E_TT_IPV6] = { .l3_prot_type = MLX5_L3_PROT_TYPE_IPV6,
2614                             .l4_prot_type = 0,
2615                             .rx_hash_fields = MLX5_HASH_IP,
2616         },
2617 };
2618
2619 struct mlx5e_tirc_config mlx5e_tirc_get_default_config(enum mlx5e_traffic_types tt)
2620 {
2621         return tirc_default_config[tt];
2622 }
2623
2624 static void mlx5e_build_tir_ctx_lro(struct mlx5e_params *params, void *tirc)
2625 {
2626         if (!params->lro_en)
2627                 return;
2628
2629 #define ROUGH_MAX_L2_L3_HDR_SZ 256
2630
2631         MLX5_SET(tirc, tirc, lro_enable_mask,
2632                  MLX5_TIRC_LRO_ENABLE_MASK_IPV4_LRO |
2633                  MLX5_TIRC_LRO_ENABLE_MASK_IPV6_LRO);
2634         MLX5_SET(tirc, tirc, lro_max_ip_payload_size,
2635                  (params->lro_wqe_sz - ROUGH_MAX_L2_L3_HDR_SZ) >> 8);
2636         MLX5_SET(tirc, tirc, lro_timeout_period_usecs, params->lro_timeout);
2637 }
2638
2639 void mlx5e_build_indir_tir_ctx_hash(struct mlx5e_rss_params *rss_params,
2640                                     const struct mlx5e_tirc_config *ttconfig,
2641                                     void *tirc, bool inner)
2642 {
2643         void *hfso = inner ? MLX5_ADDR_OF(tirc, tirc, rx_hash_field_selector_inner) :
2644                              MLX5_ADDR_OF(tirc, tirc, rx_hash_field_selector_outer);
2645
2646         MLX5_SET(tirc, tirc, rx_hash_fn, mlx5e_rx_hash_fn(rss_params->hfunc));
2647         if (rss_params->hfunc == ETH_RSS_HASH_TOP) {
2648                 void *rss_key = MLX5_ADDR_OF(tirc, tirc,
2649                                              rx_hash_toeplitz_key);
2650                 size_t len = MLX5_FLD_SZ_BYTES(tirc,
2651                                                rx_hash_toeplitz_key);
2652
2653                 MLX5_SET(tirc, tirc, rx_hash_symmetric, 1);
2654                 memcpy(rss_key, rss_params->toeplitz_hash_key, len);
2655         }
2656         MLX5_SET(rx_hash_field_select, hfso, l3_prot_type,
2657                  ttconfig->l3_prot_type);
2658         MLX5_SET(rx_hash_field_select, hfso, l4_prot_type,
2659                  ttconfig->l4_prot_type);
2660         MLX5_SET(rx_hash_field_select, hfso, selected_fields,
2661                  ttconfig->rx_hash_fields);
2662 }
2663
2664 static void mlx5e_update_rx_hash_fields(struct mlx5e_tirc_config *ttconfig,
2665                                         enum mlx5e_traffic_types tt,
2666                                         u32 rx_hash_fields)
2667 {
2668         *ttconfig                = tirc_default_config[tt];
2669         ttconfig->rx_hash_fields = rx_hash_fields;
2670 }
2671
2672 void mlx5e_modify_tirs_hash(struct mlx5e_priv *priv, void *in, int inlen)
2673 {
2674         void *tirc = MLX5_ADDR_OF(modify_tir_in, in, ctx);
2675         struct mlx5e_rss_params *rss = &priv->rss_params;
2676         struct mlx5_core_dev *mdev = priv->mdev;
2677         int ctxlen = MLX5_ST_SZ_BYTES(tirc);
2678         struct mlx5e_tirc_config ttconfig;
2679         int tt;
2680
2681         MLX5_SET(modify_tir_in, in, bitmask.hash, 1);
2682
2683         for (tt = 0; tt < MLX5E_NUM_INDIR_TIRS; tt++) {
2684                 memset(tirc, 0, ctxlen);
2685                 mlx5e_update_rx_hash_fields(&ttconfig, tt,
2686                                             rss->rx_hash_fields[tt]);
2687                 mlx5e_build_indir_tir_ctx_hash(rss, &ttconfig, tirc, false);
2688                 mlx5_core_modify_tir(mdev, priv->indir_tir[tt].tirn, in, inlen);
2689         }
2690
2691         if (!mlx5e_tunnel_inner_ft_supported(priv->mdev))
2692                 return;
2693
2694         for (tt = 0; tt < MLX5E_NUM_INDIR_TIRS; tt++) {
2695                 memset(tirc, 0, ctxlen);
2696                 mlx5e_update_rx_hash_fields(&ttconfig, tt,
2697                                             rss->rx_hash_fields[tt]);
2698                 mlx5e_build_indir_tir_ctx_hash(rss, &ttconfig, tirc, true);
2699                 mlx5_core_modify_tir(mdev, priv->inner_indir_tir[tt].tirn, in,
2700                                      inlen);
2701         }
2702 }
2703
2704 static int mlx5e_modify_tirs_lro(struct mlx5e_priv *priv)
2705 {
2706         struct mlx5_core_dev *mdev = priv->mdev;
2707
2708         void *in;
2709         void *tirc;
2710         int inlen;
2711         int err;
2712         int tt;
2713         int ix;
2714
2715         inlen = MLX5_ST_SZ_BYTES(modify_tir_in);
2716         in = kvzalloc(inlen, GFP_KERNEL);
2717         if (!in)
2718                 return -ENOMEM;
2719
2720         MLX5_SET(modify_tir_in, in, bitmask.lro, 1);
2721         tirc = MLX5_ADDR_OF(modify_tir_in, in, ctx);
2722
2723         mlx5e_build_tir_ctx_lro(&priv->channels.params, tirc);
2724
2725         for (tt = 0; tt < MLX5E_NUM_INDIR_TIRS; tt++) {
2726                 err = mlx5_core_modify_tir(mdev, priv->indir_tir[tt].tirn, in,
2727                                            inlen);
2728                 if (err)
2729                         goto free_in;
2730         }
2731
2732         for (ix = 0; ix < mlx5e_get_netdev_max_channels(priv->netdev); ix++) {
2733                 err = mlx5_core_modify_tir(mdev, priv->direct_tir[ix].tirn,
2734                                            in, inlen);
2735                 if (err)
2736                         goto free_in;
2737         }
2738
2739 free_in:
2740         kvfree(in);
2741
2742         return err;
2743 }
2744
2745 static void mlx5e_build_inner_indir_tir_ctx(struct mlx5e_priv *priv,
2746                                             enum mlx5e_traffic_types tt,
2747                                             u32 *tirc)
2748 {
2749         MLX5_SET(tirc, tirc, transport_domain, priv->mdev->mlx5e_res.td.tdn);
2750
2751         mlx5e_build_tir_ctx_lro(&priv->channels.params, tirc);
2752
2753         MLX5_SET(tirc, tirc, disp_type, MLX5_TIRC_DISP_TYPE_INDIRECT);
2754         MLX5_SET(tirc, tirc, indirect_table, priv->indir_rqt.rqtn);
2755         MLX5_SET(tirc, tirc, tunneled_offload_en, 0x1);
2756
2757         mlx5e_build_indir_tir_ctx_hash(&priv->rss_params,
2758                                        &tirc_default_config[tt], tirc, true);
2759 }
2760
2761 static int mlx5e_set_mtu(struct mlx5_core_dev *mdev,
2762                          struct mlx5e_params *params, u16 mtu)
2763 {
2764         u16 hw_mtu = MLX5E_SW2HW_MTU(params, mtu);
2765         int err;
2766
2767         err = mlx5_set_port_mtu(mdev, hw_mtu, 1);
2768         if (err)
2769                 return err;
2770
2771         /* Update vport context MTU */
2772         mlx5_modify_nic_vport_mtu(mdev, hw_mtu);
2773         return 0;
2774 }
2775
2776 static void mlx5e_query_mtu(struct mlx5_core_dev *mdev,
2777                             struct mlx5e_params *params, u16 *mtu)
2778 {
2779         u16 hw_mtu = 0;
2780         int err;
2781
2782         err = mlx5_query_nic_vport_mtu(mdev, &hw_mtu);
2783         if (err || !hw_mtu) /* fallback to port oper mtu */
2784                 mlx5_query_port_oper_mtu(mdev, &hw_mtu, 1);
2785
2786         *mtu = MLX5E_HW2SW_MTU(params, hw_mtu);
2787 }
2788
2789 int mlx5e_set_dev_port_mtu(struct mlx5e_priv *priv)
2790 {
2791         struct mlx5e_params *params = &priv->channels.params;
2792         struct net_device *netdev = priv->netdev;
2793         struct mlx5_core_dev *mdev = priv->mdev;
2794         u16 mtu;
2795         int err;
2796
2797         err = mlx5e_set_mtu(mdev, params, params->sw_mtu);
2798         if (err)
2799                 return err;
2800
2801         mlx5e_query_mtu(mdev, params, &mtu);
2802         if (mtu != params->sw_mtu)
2803                 netdev_warn(netdev, "%s: VPort MTU %d is different than netdev mtu %d\n",
2804                             __func__, mtu, params->sw_mtu);
2805
2806         params->sw_mtu = mtu;
2807         return 0;
2808 }
2809
2810 static void mlx5e_netdev_set_tcs(struct net_device *netdev)
2811 {
2812         struct mlx5e_priv *priv = netdev_priv(netdev);
2813         int nch = priv->channels.params.num_channels;
2814         int ntc = priv->channels.params.num_tc;
2815         int tc;
2816
2817         netdev_reset_tc(netdev);
2818
2819         if (ntc == 1)
2820                 return;
2821
2822         netdev_set_num_tc(netdev, ntc);
2823
2824         /* Map netdev TCs to offset 0
2825          * We have our own UP to TXQ mapping for QoS
2826          */
2827         for (tc = 0; tc < ntc; tc++)
2828                 netdev_set_tc_queue(netdev, tc, nch, 0);
2829 }
2830
2831 static void mlx5e_build_tc2txq_maps(struct mlx5e_priv *priv)
2832 {
2833         int max_nch = mlx5e_get_netdev_max_channels(priv->netdev);
2834         int i, tc;
2835
2836         for (i = 0; i < max_nch; i++)
2837                 for (tc = 0; tc < priv->profile->max_tc; tc++)
2838                         priv->channel_tc2txq[i][tc] = i + tc * max_nch;
2839 }
2840
2841 static void mlx5e_build_tx2sq_maps(struct mlx5e_priv *priv)
2842 {
2843         struct mlx5e_channel *c;
2844         struct mlx5e_txqsq *sq;
2845         int i, tc;
2846
2847         for (i = 0; i < priv->channels.num; i++) {
2848                 c = priv->channels.c[i];
2849                 for (tc = 0; tc < c->num_tc; tc++) {
2850                         sq = &c->sq[tc];
2851                         priv->txq2sq[sq->txq_ix] = sq;
2852                 }
2853         }
2854 }
2855
2856 void mlx5e_activate_priv_channels(struct mlx5e_priv *priv)
2857 {
2858         int num_txqs = priv->channels.num * priv->channels.params.num_tc;
2859         struct net_device *netdev = priv->netdev;
2860
2861         mlx5e_netdev_set_tcs(netdev);
2862         netif_set_real_num_tx_queues(netdev, num_txqs);
2863         netif_set_real_num_rx_queues(netdev, priv->channels.num);
2864
2865         mlx5e_build_tx2sq_maps(priv);
2866         mlx5e_activate_channels(&priv->channels);
2867         mlx5e_xdp_tx_enable(priv);
2868         netif_tx_start_all_queues(priv->netdev);
2869
2870         if (mlx5e_is_vport_rep(priv))
2871                 mlx5e_add_sqs_fwd_rules(priv);
2872
2873         mlx5e_wait_channels_min_rx_wqes(&priv->channels);
2874         mlx5e_redirect_rqts_to_channels(priv, &priv->channels);
2875 }
2876
2877 void mlx5e_deactivate_priv_channels(struct mlx5e_priv *priv)
2878 {
2879         mlx5e_redirect_rqts_to_drop(priv);
2880
2881         if (mlx5e_is_vport_rep(priv))
2882                 mlx5e_remove_sqs_fwd_rules(priv);
2883
2884         /* FIXME: This is a W/A only for tx timeout watch dog false alarm when
2885          * polling for inactive tx queues.
2886          */
2887         netif_tx_stop_all_queues(priv->netdev);
2888         netif_tx_disable(priv->netdev);
2889         mlx5e_xdp_tx_disable(priv);
2890         mlx5e_deactivate_channels(&priv->channels);
2891 }
2892
2893 static void mlx5e_switch_priv_channels(struct mlx5e_priv *priv,
2894                                        struct mlx5e_channels *new_chs,
2895                                        mlx5e_fp_hw_modify hw_modify)
2896 {
2897         struct net_device *netdev = priv->netdev;
2898         int new_num_txqs;
2899         int carrier_ok;
2900
2901         new_num_txqs = new_chs->num * new_chs->params.num_tc;
2902
2903         carrier_ok = netif_carrier_ok(netdev);
2904         netif_carrier_off(netdev);
2905
2906         if (new_num_txqs < netdev->real_num_tx_queues)
2907                 netif_set_real_num_tx_queues(netdev, new_num_txqs);
2908
2909         mlx5e_deactivate_priv_channels(priv);
2910         mlx5e_close_channels(&priv->channels);
2911
2912         priv->channels = *new_chs;
2913
2914         /* New channels are ready to roll, modify HW settings if needed */
2915         if (hw_modify)
2916                 hw_modify(priv);
2917
2918         mlx5e_refresh_tirs(priv, false);
2919         mlx5e_activate_priv_channels(priv);
2920
2921         /* return carrier back if needed */
2922         if (carrier_ok)
2923                 netif_carrier_on(netdev);
2924 }
2925
2926 int mlx5e_safe_switch_channels(struct mlx5e_priv *priv,
2927                                struct mlx5e_channels *new_chs,
2928                                mlx5e_fp_hw_modify hw_modify)
2929 {
2930         int err;
2931
2932         err = mlx5e_open_channels(priv, new_chs);
2933         if (err)
2934                 return err;
2935
2936         mlx5e_switch_priv_channels(priv, new_chs, hw_modify);
2937         return 0;
2938 }
2939
2940 void mlx5e_timestamp_init(struct mlx5e_priv *priv)
2941 {
2942         priv->tstamp.tx_type   = HWTSTAMP_TX_OFF;
2943         priv->tstamp.rx_filter = HWTSTAMP_FILTER_NONE;
2944 }
2945
2946 int mlx5e_open_locked(struct net_device *netdev)
2947 {
2948         struct mlx5e_priv *priv = netdev_priv(netdev);
2949         int err;
2950
2951         set_bit(MLX5E_STATE_OPENED, &priv->state);
2952
2953         err = mlx5e_open_channels(priv, &priv->channels);
2954         if (err)
2955                 goto err_clear_state_opened_flag;
2956
2957         mlx5e_refresh_tirs(priv, false);
2958         mlx5e_activate_priv_channels(priv);
2959         if (priv->profile->update_carrier)
2960                 priv->profile->update_carrier(priv);
2961
2962         mlx5e_queue_update_stats(priv);
2963         return 0;
2964
2965 err_clear_state_opened_flag:
2966         clear_bit(MLX5E_STATE_OPENED, &priv->state);
2967         return err;
2968 }
2969
2970 int mlx5e_open(struct net_device *netdev)
2971 {
2972         struct mlx5e_priv *priv = netdev_priv(netdev);
2973         int err;
2974
2975         mutex_lock(&priv->state_lock);
2976         err = mlx5e_open_locked(netdev);
2977         if (!err)
2978                 mlx5_set_port_admin_status(priv->mdev, MLX5_PORT_UP);
2979         mutex_unlock(&priv->state_lock);
2980
2981         if (mlx5_vxlan_allowed(priv->mdev->vxlan))
2982                 udp_tunnel_get_rx_info(netdev);
2983
2984         return err;
2985 }
2986
2987 int mlx5e_close_locked(struct net_device *netdev)
2988 {
2989         struct mlx5e_priv *priv = netdev_priv(netdev);
2990
2991         /* May already be CLOSED in case a previous configuration operation
2992          * (e.g RX/TX queue size change) that involves close&open failed.
2993          */
2994         if (!test_bit(MLX5E_STATE_OPENED, &priv->state))
2995                 return 0;
2996
2997         clear_bit(MLX5E_STATE_OPENED, &priv->state);
2998
2999         netif_carrier_off(priv->netdev);
3000         mlx5e_deactivate_priv_channels(priv);
3001         mlx5e_close_channels(&priv->channels);
3002
3003         return 0;
3004 }
3005
3006 int mlx5e_close(struct net_device *netdev)
3007 {
3008         struct mlx5e_priv *priv = netdev_priv(netdev);
3009         int err;
3010
3011         if (!netif_device_present(netdev))
3012                 return -ENODEV;
3013
3014         mutex_lock(&priv->state_lock);
3015         mlx5_set_port_admin_status(priv->mdev, MLX5_PORT_DOWN);
3016         err = mlx5e_close_locked(netdev);
3017         mutex_unlock(&priv->state_lock);
3018
3019         return err;
3020 }
3021
3022 static int mlx5e_alloc_drop_rq(struct mlx5_core_dev *mdev,
3023                                struct mlx5e_rq *rq,
3024                                struct mlx5e_rq_param *param)
3025 {
3026         void *rqc = param->rqc;
3027         void *rqc_wq = MLX5_ADDR_OF(rqc, rqc, wq);
3028         int err;
3029
3030         param->wq.db_numa_node = param->wq.buf_numa_node;
3031
3032         err = mlx5_wq_cyc_create(mdev, &param->wq, rqc_wq, &rq->wqe.wq,
3033                                  &rq->wq_ctrl);
3034         if (err)
3035                 return err;
3036
3037         /* Mark as unused given "Drop-RQ" packets never reach XDP */
3038         xdp_rxq_info_unused(&rq->xdp_rxq);
3039
3040         rq->mdev = mdev;
3041
3042         return 0;
3043 }
3044
3045 static int mlx5e_alloc_drop_cq(struct mlx5_core_dev *mdev,
3046                                struct mlx5e_cq *cq,
3047                                struct mlx5e_cq_param *param)
3048 {
3049         param->wq.buf_numa_node = dev_to_node(&mdev->pdev->dev);
3050         param->wq.db_numa_node  = dev_to_node(&mdev->pdev->dev);
3051
3052         return mlx5e_alloc_cq_common(mdev, param, cq);
3053 }
3054
3055 int mlx5e_open_drop_rq(struct mlx5e_priv *priv,
3056                        struct mlx5e_rq *drop_rq)
3057 {
3058         struct mlx5_core_dev *mdev = priv->mdev;
3059         struct mlx5e_cq_param cq_param = {};
3060         struct mlx5e_rq_param rq_param = {};
3061         struct mlx5e_cq *cq = &drop_rq->cq;
3062         int err;
3063
3064         mlx5e_build_drop_rq_param(priv, &rq_param);
3065
3066         err = mlx5e_alloc_drop_cq(mdev, cq, &cq_param);
3067         if (err)
3068                 return err;
3069
3070         err = mlx5e_create_cq(cq, &cq_param);
3071         if (err)
3072                 goto err_free_cq;
3073
3074         err = mlx5e_alloc_drop_rq(mdev, drop_rq, &rq_param);
3075         if (err)
3076                 goto err_destroy_cq;
3077
3078         err = mlx5e_create_rq(drop_rq, &rq_param);
3079         if (err)
3080                 goto err_free_rq;
3081
3082         err = mlx5e_modify_rq_state(drop_rq, MLX5_RQC_STATE_RST, MLX5_RQC_STATE_RDY);
3083         if (err)
3084                 mlx5_core_warn(priv->mdev, "modify_rq_state failed, rx_if_down_packets won't be counted %d\n", err);
3085
3086         return 0;
3087
3088 err_free_rq:
3089         mlx5e_free_rq(drop_rq);
3090
3091 err_destroy_cq:
3092         mlx5e_destroy_cq(cq);
3093
3094 err_free_cq:
3095         mlx5e_free_cq(cq);
3096
3097         return err;
3098 }
3099
3100 void mlx5e_close_drop_rq(struct mlx5e_rq *drop_rq)
3101 {
3102         mlx5e_destroy_rq(drop_rq);
3103         mlx5e_free_rq(drop_rq);
3104         mlx5e_destroy_cq(&drop_rq->cq);
3105         mlx5e_free_cq(&drop_rq->cq);
3106 }
3107
3108 int mlx5e_create_tis(struct mlx5_core_dev *mdev, int tc,
3109                      u32 underlay_qpn, u32 *tisn)
3110 {
3111         u32 in[MLX5_ST_SZ_DW(create_tis_in)] = {0};
3112         void *tisc = MLX5_ADDR_OF(create_tis_in, in, ctx);
3113
3114         MLX5_SET(tisc, tisc, prio, tc << 1);
3115         MLX5_SET(tisc, tisc, underlay_qpn, underlay_qpn);
3116         MLX5_SET(tisc, tisc, transport_domain, mdev->mlx5e_res.td.tdn);
3117
3118         if (mlx5_lag_is_lacp_owner(mdev))
3119                 MLX5_SET(tisc, tisc, strict_lag_tx_port_affinity, 1);
3120
3121         return mlx5_core_create_tis(mdev, in, sizeof(in), tisn);
3122 }
3123
3124 void mlx5e_destroy_tis(struct mlx5_core_dev *mdev, u32 tisn)
3125 {
3126         mlx5_core_destroy_tis(mdev, tisn);
3127 }
3128
3129 int mlx5e_create_tises(struct mlx5e_priv *priv)
3130 {
3131         int err;
3132         int tc;
3133
3134         for (tc = 0; tc < priv->profile->max_tc; tc++) {
3135                 err = mlx5e_create_tis(priv->mdev, tc, 0, &priv->tisn[tc]);
3136                 if (err)
3137                         goto err_close_tises;
3138         }
3139
3140         return 0;
3141
3142 err_close_tises:
3143         for (tc--; tc >= 0; tc--)
3144                 mlx5e_destroy_tis(priv->mdev, priv->tisn[tc]);
3145
3146         return err;
3147 }
3148
3149 static void mlx5e_cleanup_nic_tx(struct mlx5e_priv *priv)
3150 {
3151         int tc;
3152
3153         mlx5e_tx_reporter_destroy(priv);
3154         for (tc = 0; tc < priv->profile->max_tc; tc++)
3155                 mlx5e_destroy_tis(priv->mdev, priv->tisn[tc]);
3156 }
3157
3158 static void mlx5e_build_indir_tir_ctx(struct mlx5e_priv *priv,
3159                                       enum mlx5e_traffic_types tt,
3160                                       u32 *tirc)
3161 {
3162         MLX5_SET(tirc, tirc, transport_domain, priv->mdev->mlx5e_res.td.tdn);
3163
3164         mlx5e_build_tir_ctx_lro(&priv->channels.params, tirc);
3165
3166         MLX5_SET(tirc, tirc, disp_type, MLX5_TIRC_DISP_TYPE_INDIRECT);
3167         MLX5_SET(tirc, tirc, indirect_table, priv->indir_rqt.rqtn);
3168
3169         mlx5e_build_indir_tir_ctx_hash(&priv->rss_params,
3170                                        &tirc_default_config[tt], tirc, false);
3171 }
3172
3173 static void mlx5e_build_direct_tir_ctx(struct mlx5e_priv *priv, u32 rqtn, u32 *tirc)
3174 {
3175         MLX5_SET(tirc, tirc, transport_domain, priv->mdev->mlx5e_res.td.tdn);
3176
3177         mlx5e_build_tir_ctx_lro(&priv->channels.params, tirc);
3178
3179         MLX5_SET(tirc, tirc, disp_type, MLX5_TIRC_DISP_TYPE_INDIRECT);
3180         MLX5_SET(tirc, tirc, indirect_table, rqtn);
3181         MLX5_SET(tirc, tirc, rx_hash_fn, MLX5_RX_HASH_FN_INVERTED_XOR8);
3182 }
3183
3184 int mlx5e_create_indirect_tirs(struct mlx5e_priv *priv, bool inner_ttc)
3185 {
3186         struct mlx5e_tir *tir;
3187         void *tirc;
3188         int inlen;
3189         int i = 0;
3190         int err;
3191         u32 *in;
3192         int tt;
3193
3194         inlen = MLX5_ST_SZ_BYTES(create_tir_in);
3195         in = kvzalloc(inlen, GFP_KERNEL);
3196         if (!in)
3197                 return -ENOMEM;
3198
3199         for (tt = 0; tt < MLX5E_NUM_INDIR_TIRS; tt++) {
3200                 memset(in, 0, inlen);
3201                 tir = &priv->indir_tir[tt];
3202                 tirc = MLX5_ADDR_OF(create_tir_in, in, ctx);
3203                 mlx5e_build_indir_tir_ctx(priv, tt, tirc);
3204                 err = mlx5e_create_tir(priv->mdev, tir, in, inlen);
3205                 if (err) {
3206                         mlx5_core_warn(priv->mdev, "create indirect tirs failed, %d\n", err);
3207                         goto err_destroy_inner_tirs;
3208                 }
3209         }
3210
3211         if (!inner_ttc || !mlx5e_tunnel_inner_ft_supported(priv->mdev))
3212                 goto out;
3213
3214         for (i = 0; i < MLX5E_NUM_INDIR_TIRS; i++) {
3215                 memset(in, 0, inlen);
3216                 tir = &priv->inner_indir_tir[i];
3217                 tirc = MLX5_ADDR_OF(create_tir_in, in, ctx);
3218                 mlx5e_build_inner_indir_tir_ctx(priv, i, tirc);
3219                 err = mlx5e_create_tir(priv->mdev, tir, in, inlen);
3220                 if (err) {
3221                         mlx5_core_warn(priv->mdev, "create inner indirect tirs failed, %d\n", err);
3222                         goto err_destroy_inner_tirs;
3223                 }
3224         }
3225
3226 out:
3227         kvfree(in);
3228
3229         return 0;
3230
3231 err_destroy_inner_tirs:
3232         for (i--; i >= 0; i--)
3233                 mlx5e_destroy_tir(priv->mdev, &priv->inner_indir_tir[i]);
3234
3235         for (tt--; tt >= 0; tt--)
3236                 mlx5e_destroy_tir(priv->mdev, &priv->indir_tir[tt]);
3237
3238         kvfree(in);
3239
3240         return err;
3241 }
3242
3243 int mlx5e_create_direct_tirs(struct mlx5e_priv *priv)
3244 {
3245         int nch = mlx5e_get_netdev_max_channels(priv->netdev);
3246         struct mlx5e_tir *tir;
3247         void *tirc;
3248         int inlen;
3249         int err;
3250         u32 *in;
3251         int ix;
3252
3253         inlen = MLX5_ST_SZ_BYTES(create_tir_in);
3254         in = kvzalloc(inlen, GFP_KERNEL);
3255         if (!in)
3256                 return -ENOMEM;
3257
3258         for (ix = 0; ix < nch; ix++) {
3259                 memset(in, 0, inlen);
3260                 tir = &priv->direct_tir[ix];
3261                 tirc = MLX5_ADDR_OF(create_tir_in, in, ctx);
3262                 mlx5e_build_direct_tir_ctx(priv, priv->direct_tir[ix].rqt.rqtn, tirc);
3263                 err = mlx5e_create_tir(priv->mdev, tir, in, inlen);
3264                 if (err)
3265                         goto err_destroy_ch_tirs;
3266         }
3267
3268         kvfree(in);
3269
3270         return 0;
3271
3272 err_destroy_ch_tirs:
3273         mlx5_core_warn(priv->mdev, "create direct tirs failed, %d\n", err);
3274         for (ix--; ix >= 0; ix--)
3275                 mlx5e_destroy_tir(priv->mdev, &priv->direct_tir[ix]);
3276
3277         kvfree(in);
3278
3279         return err;
3280 }
3281
3282 void mlx5e_destroy_indirect_tirs(struct mlx5e_priv *priv, bool inner_ttc)
3283 {
3284         int i;
3285
3286         for (i = 0; i < MLX5E_NUM_INDIR_TIRS; i++)
3287                 mlx5e_destroy_tir(priv->mdev, &priv->indir_tir[i]);
3288
3289         if (!inner_ttc || !mlx5e_tunnel_inner_ft_supported(priv->mdev))
3290                 return;
3291
3292         for (i = 0; i < MLX5E_NUM_INDIR_TIRS; i++)
3293                 mlx5e_destroy_tir(priv->mdev, &priv->inner_indir_tir[i]);
3294 }
3295
3296 void mlx5e_destroy_direct_tirs(struct mlx5e_priv *priv)
3297 {
3298         int nch = mlx5e_get_netdev_max_channels(priv->netdev);
3299         int i;
3300
3301         for (i = 0; i < nch; i++)
3302                 mlx5e_destroy_tir(priv->mdev, &priv->direct_tir[i]);
3303 }
3304
3305 static int mlx5e_modify_channels_scatter_fcs(struct mlx5e_channels *chs, bool enable)
3306 {
3307         int err = 0;
3308         int i;
3309
3310         for (i = 0; i < chs->num; i++) {
3311                 err = mlx5e_modify_rq_scatter_fcs(&chs->c[i]->rq, enable);
3312                 if (err)
3313                         return err;
3314         }
3315
3316         return 0;
3317 }
3318
3319 static int mlx5e_modify_channels_vsd(struct mlx5e_channels *chs, bool vsd)
3320 {
3321         int err = 0;
3322         int i;
3323
3324         for (i = 0; i < chs->num; i++) {
3325                 err = mlx5e_modify_rq_vsd(&chs->c[i]->rq, vsd);
3326                 if (err)
3327                         return err;
3328         }
3329
3330         return 0;
3331 }
3332
3333 static int mlx5e_setup_tc_mqprio(struct net_device *netdev,
3334                                  struct tc_mqprio_qopt *mqprio)
3335 {
3336         struct mlx5e_priv *priv = netdev_priv(netdev);
3337         struct mlx5e_channels new_channels = {};
3338         u8 tc = mqprio->num_tc;
3339         int err = 0;
3340
3341         mqprio->hw = TC_MQPRIO_HW_OFFLOAD_TCS;
3342
3343         if (tc && tc != MLX5E_MAX_NUM_TC)
3344                 return -EINVAL;
3345
3346         mutex_lock(&priv->state_lock);
3347
3348         new_channels.params = priv->channels.params;
3349         new_channels.params.num_tc = tc ? tc : 1;
3350
3351         if (!test_bit(MLX5E_STATE_OPENED, &priv->state)) {
3352                 priv->channels.params = new_channels.params;
3353                 goto out;
3354         }
3355
3356         err = mlx5e_safe_switch_channels(priv, &new_channels, NULL);
3357         if (err)
3358                 goto out;
3359
3360         priv->max_opened_tc = max_t(u8, priv->max_opened_tc,
3361                                     new_channels.params.num_tc);
3362 out:
3363         mutex_unlock(&priv->state_lock);
3364         return err;
3365 }
3366
3367 #ifdef CONFIG_MLX5_ESWITCH
3368 static int mlx5e_setup_tc_cls_flower(struct mlx5e_priv *priv,
3369                                      struct tc_cls_flower_offload *cls_flower,
3370                                      int flags)
3371 {
3372         switch (cls_flower->command) {
3373         case TC_CLSFLOWER_REPLACE:
3374                 return mlx5e_configure_flower(priv->netdev, priv, cls_flower,
3375                                               flags);
3376         case TC_CLSFLOWER_DESTROY:
3377                 return mlx5e_delete_flower(priv->netdev, priv, cls_flower,
3378                                            flags);
3379         case TC_CLSFLOWER_STATS:
3380                 return mlx5e_stats_flower(priv->netdev, priv, cls_flower,
3381                                           flags);
3382         default:
3383                 return -EOPNOTSUPP;
3384         }
3385 }
3386
3387 static int mlx5e_setup_tc_block_cb(enum tc_setup_type type, void *type_data,
3388                                    void *cb_priv)
3389 {
3390         struct mlx5e_priv *priv = cb_priv;
3391
3392         switch (type) {
3393         case TC_SETUP_CLSFLOWER:
3394                 return mlx5e_setup_tc_cls_flower(priv, type_data, MLX5E_TC_INGRESS |
3395                                                  MLX5E_TC_NIC_OFFLOAD);
3396         default:
3397                 return -EOPNOTSUPP;
3398         }
3399 }
3400
3401 static int mlx5e_setup_tc_block(struct net_device *dev,
3402                                 struct tc_block_offload *f)
3403 {
3404         struct mlx5e_priv *priv = netdev_priv(dev);
3405
3406         if (f->binder_type != TCF_BLOCK_BINDER_TYPE_CLSACT_INGRESS)
3407                 return -EOPNOTSUPP;
3408
3409         switch (f->command) {
3410         case TC_BLOCK_BIND:
3411                 return tcf_block_cb_register(f->block, mlx5e_setup_tc_block_cb,
3412                                              priv, priv, f->extack);
3413         case TC_BLOCK_UNBIND:
3414                 tcf_block_cb_unregister(f->block, mlx5e_setup_tc_block_cb,
3415                                         priv);
3416                 return 0;
3417         default:
3418                 return -EOPNOTSUPP;
3419         }
3420 }
3421 #endif
3422
3423 static int mlx5e_setup_tc(struct net_device *dev, enum tc_setup_type type,
3424                           void *type_data)
3425 {
3426         switch (type) {
3427 #ifdef CONFIG_MLX5_ESWITCH
3428         case TC_SETUP_BLOCK:
3429                 return mlx5e_setup_tc_block(dev, type_data);
3430 #endif
3431         case TC_SETUP_QDISC_MQPRIO:
3432                 return mlx5e_setup_tc_mqprio(dev, type_data);
3433         default:
3434                 return -EOPNOTSUPP;
3435         }
3436 }
3437
3438 void mlx5e_fold_sw_stats64(struct mlx5e_priv *priv, struct rtnl_link_stats64 *s)
3439 {
3440         int i;
3441
3442         for (i = 0; i < mlx5e_get_netdev_max_channels(priv->netdev); i++) {
3443                 struct mlx5e_channel_stats *channel_stats = &priv->channel_stats[i];
3444                 struct mlx5e_rq_stats *rq_stats = &channel_stats->rq;
3445                 int j;
3446
3447                 s->rx_packets   += rq_stats->packets;
3448                 s->rx_bytes     += rq_stats->bytes;
3449
3450                 for (j = 0; j < priv->max_opened_tc; j++) {
3451                         struct mlx5e_sq_stats *sq_stats = &channel_stats->sq[j];
3452
3453                         s->tx_packets    += sq_stats->packets;
3454                         s->tx_bytes      += sq_stats->bytes;
3455                         s->tx_dropped    += sq_stats->dropped;
3456                 }
3457         }
3458 }
3459
3460 void
3461 mlx5e_get_stats(struct net_device *dev, struct rtnl_link_stats64 *stats)
3462 {
3463         struct mlx5e_priv *priv = netdev_priv(dev);
3464         struct mlx5e_vport_stats *vstats = &priv->stats.vport;
3465         struct mlx5e_pport_stats *pstats = &priv->stats.pport;
3466
3467         if (!mlx5e_monitor_counter_supported(priv)) {
3468                 /* update HW stats in background for next time */
3469                 mlx5e_queue_update_stats(priv);
3470         }
3471
3472         if (mlx5e_is_uplink_rep(priv)) {
3473                 stats->rx_packets = PPORT_802_3_GET(pstats, a_frames_received_ok);
3474                 stats->rx_bytes   = PPORT_802_3_GET(pstats, a_octets_received_ok);
3475                 stats->tx_packets = PPORT_802_3_GET(pstats, a_frames_transmitted_ok);
3476                 stats->tx_bytes   = PPORT_802_3_GET(pstats, a_octets_transmitted_ok);
3477         } else {
3478                 mlx5e_fold_sw_stats64(priv, stats);
3479         }
3480
3481         stats->rx_dropped = priv->stats.qcnt.rx_out_of_buffer;
3482
3483         stats->rx_length_errors =
3484                 PPORT_802_3_GET(pstats, a_in_range_length_errors) +
3485                 PPORT_802_3_GET(pstats, a_out_of_range_length_field) +
3486                 PPORT_802_3_GET(pstats, a_frame_too_long_errors);
3487         stats->rx_crc_errors =
3488                 PPORT_802_3_GET(pstats, a_frame_check_sequence_errors);
3489         stats->rx_frame_errors = PPORT_802_3_GET(pstats, a_alignment_errors);
3490         stats->tx_aborted_errors = PPORT_2863_GET(pstats, if_out_discards);
3491         stats->rx_errors = stats->rx_length_errors + stats->rx_crc_errors +
3492                            stats->rx_frame_errors;
3493         stats->tx_errors = stats->tx_aborted_errors + stats->tx_carrier_errors;
3494
3495         /* vport multicast also counts packets that are dropped due to steering
3496          * or rx out of buffer
3497          */
3498         stats->multicast =
3499                 VPORT_COUNTER_GET(vstats, received_eth_multicast.packets);
3500 }
3501
3502 static void mlx5e_set_rx_mode(struct net_device *dev)
3503 {
3504         struct mlx5e_priv *priv = netdev_priv(dev);
3505
3506         queue_work(priv->wq, &priv->set_rx_mode_work);
3507 }
3508
3509 static int mlx5e_set_mac(struct net_device *netdev, void *addr)
3510 {
3511         struct mlx5e_priv *priv = netdev_priv(netdev);
3512         struct sockaddr *saddr = addr;
3513
3514         if (!is_valid_ether_addr(saddr->sa_data))
3515                 return -EADDRNOTAVAIL;
3516
3517         netif_addr_lock_bh(netdev);
3518         ether_addr_copy(netdev->dev_addr, saddr->sa_data);
3519         netif_addr_unlock_bh(netdev);
3520
3521         queue_work(priv->wq, &priv->set_rx_mode_work);
3522
3523         return 0;
3524 }
3525
3526 #define MLX5E_SET_FEATURE(features, feature, enable)    \
3527         do {                                            \
3528                 if (enable)                             \
3529                         *features |= feature;           \
3530                 else                                    \
3531                         *features &= ~feature;          \
3532         } while (0)
3533
3534 typedef int (*mlx5e_feature_handler)(struct net_device *netdev, bool enable);
3535
3536 static int set_feature_lro(struct net_device *netdev, bool enable)
3537 {
3538         struct mlx5e_priv *priv = netdev_priv(netdev);
3539         struct mlx5_core_dev *mdev = priv->mdev;
3540         struct mlx5e_channels new_channels = {};
3541         struct mlx5e_params *old_params;
3542         int err = 0;
3543         bool reset;
3544
3545         mutex_lock(&priv->state_lock);
3546
3547         old_params = &priv->channels.params;
3548         if (enable && !MLX5E_GET_PFLAG(old_params, MLX5E_PFLAG_RX_STRIDING_RQ)) {
3549                 netdev_warn(netdev, "can't set LRO with legacy RQ\n");
3550                 err = -EINVAL;
3551                 goto out;
3552         }
3553
3554         reset = test_bit(MLX5E_STATE_OPENED, &priv->state);
3555
3556         new_channels.params = *old_params;
3557         new_channels.params.lro_en = enable;
3558
3559         if (old_params->rq_wq_type != MLX5_WQ_TYPE_CYCLIC) {
3560                 if (mlx5e_rx_mpwqe_is_linear_skb(mdev, old_params) ==
3561                     mlx5e_rx_mpwqe_is_linear_skb(mdev, &new_channels.params))
3562                         reset = false;
3563         }
3564
3565         if (!reset) {
3566                 *old_params = new_channels.params;
3567                 err = mlx5e_modify_tirs_lro(priv);
3568                 goto out;
3569         }
3570
3571         err = mlx5e_safe_switch_channels(priv, &new_channels, mlx5e_modify_tirs_lro);
3572 out:
3573         mutex_unlock(&priv->state_lock);
3574         return err;
3575 }
3576
3577 static int set_feature_cvlan_filter(struct net_device *netdev, bool enable)
3578 {
3579         struct mlx5e_priv *priv = netdev_priv(netdev);
3580
3581         if (enable)
3582                 mlx5e_enable_cvlan_filter(priv);
3583         else
3584                 mlx5e_disable_cvlan_filter(priv);
3585
3586         return 0;
3587 }
3588
3589 #ifdef CONFIG_MLX5_ESWITCH
3590 static int set_feature_tc_num_filters(struct net_device *netdev, bool enable)
3591 {
3592         struct mlx5e_priv *priv = netdev_priv(netdev);
3593
3594         if (!enable && mlx5e_tc_num_filters(priv, MLX5E_TC_NIC_OFFLOAD)) {
3595                 netdev_err(netdev,
3596                            "Active offloaded tc filters, can't turn hw_tc_offload off\n");
3597                 return -EINVAL;
3598         }
3599
3600         return 0;
3601 }
3602 #endif
3603
3604 static int set_feature_rx_all(struct net_device *netdev, bool enable)
3605 {
3606         struct mlx5e_priv *priv = netdev_priv(netdev);
3607         struct mlx5_core_dev *mdev = priv->mdev;
3608
3609         return mlx5_set_port_fcs(mdev, !enable);
3610 }
3611
3612 static int set_feature_rx_fcs(struct net_device *netdev, bool enable)
3613 {
3614         struct mlx5e_priv *priv = netdev_priv(netdev);
3615         int err;
3616
3617         mutex_lock(&priv->state_lock);
3618
3619         priv->channels.params.scatter_fcs_en = enable;
3620         err = mlx5e_modify_channels_scatter_fcs(&priv->channels, enable);
3621         if (err)
3622                 priv->channels.params.scatter_fcs_en = !enable;
3623
3624         mutex_unlock(&priv->state_lock);
3625
3626         return err;
3627 }
3628
3629 static int set_feature_rx_vlan(struct net_device *netdev, bool enable)
3630 {
3631         struct mlx5e_priv *priv = netdev_priv(netdev);
3632         int err = 0;
3633
3634         mutex_lock(&priv->state_lock);
3635
3636         priv->channels.params.vlan_strip_disable = !enable;
3637         if (!test_bit(MLX5E_STATE_OPENED, &priv->state))
3638                 goto unlock;
3639
3640         err = mlx5e_modify_channels_vsd(&priv->channels, !enable);
3641         if (err)
3642                 priv->channels.params.vlan_strip_disable = enable;
3643
3644 unlock:
3645         mutex_unlock(&priv->state_lock);
3646
3647         return err;
3648 }
3649
3650 #ifdef CONFIG_MLX5_EN_ARFS
3651 static int set_feature_arfs(struct net_device *netdev, bool enable)
3652 {
3653         struct mlx5e_priv *priv = netdev_priv(netdev);
3654         int err;
3655
3656         if (enable)
3657                 err = mlx5e_arfs_enable(priv);
3658         else
3659                 err = mlx5e_arfs_disable(priv);
3660
3661         return err;
3662 }
3663 #endif
3664
3665 static int mlx5e_handle_feature(struct net_device *netdev,
3666                                 netdev_features_t *features,
3667                                 netdev_features_t wanted_features,
3668                                 netdev_features_t feature,
3669                                 mlx5e_feature_handler feature_handler)
3670 {
3671         netdev_features_t changes = wanted_features ^ netdev->features;
3672         bool enable = !!(wanted_features & feature);
3673         int err;
3674
3675         if (!(changes & feature))
3676                 return 0;
3677
3678         err = feature_handler(netdev, enable);
3679         if (err) {
3680                 netdev_err(netdev, "%s feature %pNF failed, err %d\n",
3681                            enable ? "Enable" : "Disable", &feature, err);
3682                 return err;
3683         }
3684
3685         MLX5E_SET_FEATURE(features, feature, enable);
3686         return 0;
3687 }
3688
3689 static int mlx5e_set_features(struct net_device *netdev,
3690                               netdev_features_t features)
3691 {
3692         netdev_features_t oper_features = netdev->features;
3693         int err = 0;
3694
3695 #define MLX5E_HANDLE_FEATURE(feature, handler) \
3696         mlx5e_handle_feature(netdev, &oper_features, features, feature, handler)
3697
3698         err |= MLX5E_HANDLE_FEATURE(NETIF_F_LRO, set_feature_lro);
3699         err |= MLX5E_HANDLE_FEATURE(NETIF_F_HW_VLAN_CTAG_FILTER,
3700                                     set_feature_cvlan_filter);
3701 #ifdef CONFIG_MLX5_ESWITCH
3702         err |= MLX5E_HANDLE_FEATURE(NETIF_F_HW_TC, set_feature_tc_num_filters);
3703 #endif
3704         err |= MLX5E_HANDLE_FEATURE(NETIF_F_RXALL, set_feature_rx_all);
3705         err |= MLX5E_HANDLE_FEATURE(NETIF_F_RXFCS, set_feature_rx_fcs);
3706         err |= MLX5E_HANDLE_FEATURE(NETIF_F_HW_VLAN_CTAG_RX, set_feature_rx_vlan);
3707 #ifdef CONFIG_MLX5_EN_ARFS
3708         err |= MLX5E_HANDLE_FEATURE(NETIF_F_NTUPLE, set_feature_arfs);
3709 #endif
3710
3711         if (err) {
3712                 netdev->features = oper_features;
3713                 return -EINVAL;
3714         }
3715
3716         return 0;
3717 }
3718
3719 static netdev_features_t mlx5e_fix_features(struct net_device *netdev,
3720                                             netdev_features_t features)
3721 {
3722         struct mlx5e_priv *priv = netdev_priv(netdev);
3723         struct mlx5e_params *params;
3724
3725         mutex_lock(&priv->state_lock);
3726         params = &priv->channels.params;
3727         if (!bitmap_empty(priv->fs.vlan.active_svlans, VLAN_N_VID)) {
3728                 /* HW strips the outer C-tag header, this is a problem
3729                  * for S-tag traffic.
3730                  */
3731                 features &= ~NETIF_F_HW_VLAN_CTAG_RX;
3732                 if (!params->vlan_strip_disable)
3733                         netdev_warn(netdev, "Dropping C-tag vlan stripping offload due to S-tag vlan\n");
3734         }
3735         if (!MLX5E_GET_PFLAG(params, MLX5E_PFLAG_RX_STRIDING_RQ)) {
3736                 features &= ~NETIF_F_LRO;
3737                 if (params->lro_en)
3738                         netdev_warn(netdev, "Disabling LRO, not supported in legacy RQ\n");
3739         }
3740
3741         mutex_unlock(&priv->state_lock);
3742
3743         return features;
3744 }
3745
3746 int mlx5e_change_mtu(struct net_device *netdev, int new_mtu,
3747                      change_hw_mtu_cb set_mtu_cb)
3748 {
3749         struct mlx5e_priv *priv = netdev_priv(netdev);
3750         struct mlx5e_channels new_channels = {};
3751         struct mlx5e_params *params;
3752         int err = 0;
3753         bool reset;
3754
3755         mutex_lock(&priv->state_lock);
3756
3757         params = &priv->channels.params;
3758
3759         reset = !params->lro_en;
3760         reset = reset && test_bit(MLX5E_STATE_OPENED, &priv->state);
3761
3762         new_channels.params = *params;
3763         new_channels.params.sw_mtu = new_mtu;
3764
3765         if (params->xdp_prog &&
3766             !mlx5e_rx_is_linear_skb(priv->mdev, &new_channels.params)) {
3767                 netdev_err(netdev, "MTU(%d) > %d is not allowed while XDP enabled\n",
3768                            new_mtu, MLX5E_XDP_MAX_MTU);
3769                 err = -EINVAL;
3770                 goto out;
3771         }
3772
3773         if (params->rq_wq_type == MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ) {
3774                 bool is_linear = mlx5e_rx_mpwqe_is_linear_skb(priv->mdev, &new_channels.params);
3775                 u8 ppw_old = mlx5e_mpwqe_log_pkts_per_wqe(params);
3776                 u8 ppw_new = mlx5e_mpwqe_log_pkts_per_wqe(&new_channels.params);
3777
3778                 reset = reset && (is_linear || (ppw_old != ppw_new));
3779         }
3780
3781         if (!reset) {
3782                 params->sw_mtu = new_mtu;
3783                 if (set_mtu_cb)
3784                         set_mtu_cb(priv);
3785                 netdev->mtu = params->sw_mtu;
3786                 goto out;
3787         }
3788
3789         err = mlx5e_safe_switch_channels(priv, &new_channels, set_mtu_cb);
3790         if (err)
3791                 goto out;
3792
3793         netdev->mtu = new_channels.params.sw_mtu;
3794
3795 out:
3796         mutex_unlock(&priv->state_lock);
3797         return err;
3798 }
3799
3800 static int mlx5e_change_nic_mtu(struct net_device *netdev, int new_mtu)
3801 {
3802         return mlx5e_change_mtu(netdev, new_mtu, mlx5e_set_dev_port_mtu);
3803 }
3804
3805 int mlx5e_hwstamp_set(struct mlx5e_priv *priv, struct ifreq *ifr)
3806 {
3807         struct hwtstamp_config config;
3808         int err;
3809
3810         if (!MLX5_CAP_GEN(priv->mdev, device_frequency_khz) ||
3811             (mlx5_clock_get_ptp_index(priv->mdev) == -1))
3812                 return -EOPNOTSUPP;
3813
3814         if (copy_from_user(&config, ifr->ifr_data, sizeof(config)))
3815                 return -EFAULT;
3816
3817         /* TX HW timestamp */
3818         switch (config.tx_type) {
3819         case HWTSTAMP_TX_OFF:
3820         case HWTSTAMP_TX_ON:
3821                 break;
3822         default:
3823                 return -ERANGE;
3824         }
3825
3826         mutex_lock(&priv->state_lock);
3827         /* RX HW timestamp */
3828         switch (config.rx_filter) {
3829         case HWTSTAMP_FILTER_NONE:
3830                 /* Reset CQE compression to Admin default */
3831                 mlx5e_modify_rx_cqe_compression_locked(priv, priv->channels.params.rx_cqe_compress_def);
3832                 break;
3833         case HWTSTAMP_FILTER_ALL:
3834         case HWTSTAMP_FILTER_SOME:
3835         case HWTSTAMP_FILTER_PTP_V1_L4_EVENT:
3836         case HWTSTAMP_FILTER_PTP_V1_L4_SYNC:
3837         case HWTSTAMP_FILTER_PTP_V1_L4_DELAY_REQ:
3838         case HWTSTAMP_FILTER_PTP_V2_L4_EVENT:
3839         case HWTSTAMP_FILTER_PTP_V2_L4_SYNC:
3840         case HWTSTAMP_FILTER_PTP_V2_L4_DELAY_REQ:
3841         case HWTSTAMP_FILTER_PTP_V2_L2_EVENT:
3842         case HWTSTAMP_FILTER_PTP_V2_L2_SYNC:
3843         case HWTSTAMP_FILTER_PTP_V2_L2_DELAY_REQ:
3844         case HWTSTAMP_FILTER_PTP_V2_EVENT:
3845         case HWTSTAMP_FILTER_PTP_V2_SYNC:
3846         case HWTSTAMP_FILTER_PTP_V2_DELAY_REQ:
3847         case HWTSTAMP_FILTER_NTP_ALL:
3848                 /* Disable CQE compression */
3849                 netdev_warn(priv->netdev, "Disabling cqe compression");
3850                 err = mlx5e_modify_rx_cqe_compression_locked(priv, false);
3851                 if (err) {
3852                         netdev_err(priv->netdev, "Failed disabling cqe compression err=%d\n", err);
3853                         mutex_unlock(&priv->state_lock);
3854                         return err;
3855                 }
3856                 config.rx_filter = HWTSTAMP_FILTER_ALL;
3857                 break;
3858         default:
3859                 mutex_unlock(&priv->state_lock);
3860                 return -ERANGE;
3861         }
3862
3863         memcpy(&priv->tstamp, &config, sizeof(config));
3864         mutex_unlock(&priv->state_lock);
3865
3866         return copy_to_user(ifr->ifr_data, &config,
3867                             sizeof(config)) ? -EFAULT : 0;
3868 }
3869
3870 int mlx5e_hwstamp_get(struct mlx5e_priv *priv, struct ifreq *ifr)
3871 {
3872         struct hwtstamp_config *cfg = &priv->tstamp;
3873
3874         if (!MLX5_CAP_GEN(priv->mdev, device_frequency_khz))
3875                 return -EOPNOTSUPP;
3876
3877         return copy_to_user(ifr->ifr_data, cfg, sizeof(*cfg)) ? -EFAULT : 0;
3878 }
3879
3880 static int mlx5e_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
3881 {
3882         struct mlx5e_priv *priv = netdev_priv(dev);
3883
3884         switch (cmd) {
3885         case SIOCSHWTSTAMP:
3886                 return mlx5e_hwstamp_set(priv, ifr);
3887         case SIOCGHWTSTAMP:
3888                 return mlx5e_hwstamp_get(priv, ifr);
3889         default:
3890                 return -EOPNOTSUPP;
3891         }
3892 }
3893
3894 #ifdef CONFIG_MLX5_ESWITCH
3895 int mlx5e_set_vf_mac(struct net_device *dev, int vf, u8 *mac)
3896 {
3897         struct mlx5e_priv *priv = netdev_priv(dev);
3898         struct mlx5_core_dev *mdev = priv->mdev;
3899
3900         return mlx5_eswitch_set_vport_mac(mdev->priv.eswitch, vf + 1, mac);
3901 }
3902
3903 static int mlx5e_set_vf_vlan(struct net_device *dev, int vf, u16 vlan, u8 qos,
3904                              __be16 vlan_proto)
3905 {
3906         struct mlx5e_priv *priv = netdev_priv(dev);
3907         struct mlx5_core_dev *mdev = priv->mdev;
3908
3909         if (vlan_proto != htons(ETH_P_8021Q))
3910                 return -EPROTONOSUPPORT;
3911
3912         return mlx5_eswitch_set_vport_vlan(mdev->priv.eswitch, vf + 1,
3913                                            vlan, qos);
3914 }
3915
3916 static int mlx5e_set_vf_spoofchk(struct net_device *dev, int vf, bool setting)
3917 {
3918         struct mlx5e_priv *priv = netdev_priv(dev);
3919         struct mlx5_core_dev *mdev = priv->mdev;
3920
3921         return mlx5_eswitch_set_vport_spoofchk(mdev->priv.eswitch, vf + 1, setting);
3922 }
3923
3924 static int mlx5e_set_vf_trust(struct net_device *dev, int vf, bool setting)
3925 {
3926         struct mlx5e_priv *priv = netdev_priv(dev);
3927         struct mlx5_core_dev *mdev = priv->mdev;
3928
3929         return mlx5_eswitch_set_vport_trust(mdev->priv.eswitch, vf + 1, setting);
3930 }
3931
3932 int mlx5e_set_vf_rate(struct net_device *dev, int vf, int min_tx_rate,
3933                       int max_tx_rate)
3934 {
3935         struct mlx5e_priv *priv = netdev_priv(dev);
3936         struct mlx5_core_dev *mdev = priv->mdev;
3937
3938         return mlx5_eswitch_set_vport_rate(mdev->priv.eswitch, vf + 1,
3939                                            max_tx_rate, min_tx_rate);
3940 }
3941
3942 static int mlx5_vport_link2ifla(u8 esw_link)
3943 {
3944         switch (esw_link) {
3945         case MLX5_VPORT_ADMIN_STATE_DOWN:
3946                 return IFLA_VF_LINK_STATE_DISABLE;
3947         case MLX5_VPORT_ADMIN_STATE_UP:
3948                 return IFLA_VF_LINK_STATE_ENABLE;
3949         }
3950         return IFLA_VF_LINK_STATE_AUTO;
3951 }
3952
3953 static int mlx5_ifla_link2vport(u8 ifla_link)
3954 {
3955         switch (ifla_link) {
3956         case IFLA_VF_LINK_STATE_DISABLE:
3957                 return MLX5_VPORT_ADMIN_STATE_DOWN;
3958         case IFLA_VF_LINK_STATE_ENABLE:
3959                 return MLX5_VPORT_ADMIN_STATE_UP;
3960         }
3961         return MLX5_VPORT_ADMIN_STATE_AUTO;
3962 }
3963
3964 static int mlx5e_set_vf_link_state(struct net_device *dev, int vf,
3965                                    int link_state)
3966 {
3967         struct mlx5e_priv *priv = netdev_priv(dev);
3968         struct mlx5_core_dev *mdev = priv->mdev;
3969
3970         return mlx5_eswitch_set_vport_state(mdev->priv.eswitch, vf + 1,
3971                                             mlx5_ifla_link2vport(link_state));
3972 }
3973
3974 int mlx5e_get_vf_config(struct net_device *dev,
3975                         int vf, struct ifla_vf_info *ivi)
3976 {
3977         struct mlx5e_priv *priv = netdev_priv(dev);
3978         struct mlx5_core_dev *mdev = priv->mdev;
3979         int err;
3980
3981         err = mlx5_eswitch_get_vport_config(mdev->priv.eswitch, vf + 1, ivi);
3982         if (err)
3983                 return err;
3984         ivi->linkstate = mlx5_vport_link2ifla(ivi->linkstate);
3985         return 0;
3986 }
3987
3988 int mlx5e_get_vf_stats(struct net_device *dev,
3989                        int vf, struct ifla_vf_stats *vf_stats)
3990 {
3991         struct mlx5e_priv *priv = netdev_priv(dev);
3992         struct mlx5_core_dev *mdev = priv->mdev;
3993
3994         return mlx5_eswitch_get_vport_stats(mdev->priv.eswitch, vf + 1,
3995                                             vf_stats);
3996 }
3997 #endif
3998
3999 struct mlx5e_vxlan_work {
4000         struct work_struct      work;
4001         struct mlx5e_priv       *priv;
4002         u16                     port;
4003 };
4004
4005 static void mlx5e_vxlan_add_work(struct work_struct *work)
4006 {
4007         struct mlx5e_vxlan_work *vxlan_work =
4008                 container_of(work, struct mlx5e_vxlan_work, work);
4009         struct mlx5e_priv *priv = vxlan_work->priv;
4010         u16 port = vxlan_work->port;
4011
4012         mutex_lock(&priv->state_lock);
4013         mlx5_vxlan_add_port(priv->mdev->vxlan, port);
4014         mutex_unlock(&priv->state_lock);
4015
4016         kfree(vxlan_work);
4017 }
4018
4019 static void mlx5e_vxlan_del_work(struct work_struct *work)
4020 {
4021         struct mlx5e_vxlan_work *vxlan_work =
4022                 container_of(work, struct mlx5e_vxlan_work, work);
4023         struct mlx5e_priv *priv         = vxlan_work->priv;
4024         u16 port = vxlan_work->port;
4025
4026         mutex_lock(&priv->state_lock);
4027         mlx5_vxlan_del_port(priv->mdev->vxlan, port);
4028         mutex_unlock(&priv->state_lock);
4029         kfree(vxlan_work);
4030 }
4031
4032 static void mlx5e_vxlan_queue_work(struct mlx5e_priv *priv, u16 port, int add)
4033 {
4034         struct mlx5e_vxlan_work *vxlan_work;
4035
4036         vxlan_work = kmalloc(sizeof(*vxlan_work), GFP_ATOMIC);
4037         if (!vxlan_work)
4038                 return;
4039
4040         if (add)
4041                 INIT_WORK(&vxlan_work->work, mlx5e_vxlan_add_work);
4042         else
4043                 INIT_WORK(&vxlan_work->work, mlx5e_vxlan_del_work);
4044
4045         vxlan_work->priv = priv;
4046         vxlan_work->port = port;
4047         queue_work(priv->wq, &vxlan_work->work);
4048 }
4049
4050 void mlx5e_add_vxlan_port(struct net_device *netdev, struct udp_tunnel_info *ti)
4051 {
4052         struct mlx5e_priv *priv = netdev_priv(netdev);
4053
4054         if (ti->type != UDP_TUNNEL_TYPE_VXLAN)
4055                 return;
4056
4057         if (!mlx5_vxlan_allowed(priv->mdev->vxlan))
4058                 return;
4059
4060         mlx5e_vxlan_queue_work(priv, be16_to_cpu(ti->port), 1);
4061 }
4062
4063 void mlx5e_del_vxlan_port(struct net_device *netdev, struct udp_tunnel_info *ti)
4064 {
4065         struct mlx5e_priv *priv = netdev_priv(netdev);
4066
4067         if (ti->type != UDP_TUNNEL_TYPE_VXLAN)
4068                 return;
4069
4070         if (!mlx5_vxlan_allowed(priv->mdev->vxlan))
4071                 return;
4072
4073         mlx5e_vxlan_queue_work(priv, be16_to_cpu(ti->port), 0);
4074 }
4075
4076 static netdev_features_t mlx5e_tunnel_features_check(struct mlx5e_priv *priv,
4077                                                      struct sk_buff *skb,
4078                                                      netdev_features_t features)
4079 {
4080         unsigned int offset = 0;
4081         struct udphdr *udph;
4082         u8 proto;
4083         u16 port;
4084
4085         switch (vlan_get_protocol(skb)) {
4086         case htons(ETH_P_IP):
4087                 proto = ip_hdr(skb)->protocol;
4088                 break;
4089         case htons(ETH_P_IPV6):
4090                 proto = ipv6_find_hdr(skb, &offset, -1, NULL, NULL);
4091                 break;
4092         default:
4093                 goto out;
4094         }
4095
4096         switch (proto) {
4097         case IPPROTO_GRE:
4098                 return features;
4099         case IPPROTO_UDP:
4100                 udph = udp_hdr(skb);
4101                 port = be16_to_cpu(udph->dest);
4102
4103                 /* Verify if UDP port is being offloaded by HW */
4104                 if (mlx5_vxlan_lookup_port(priv->mdev->vxlan, port))
4105                         return features;
4106         }
4107
4108 out:
4109         /* Disable CSUM and GSO if the udp dport is not offloaded by HW */
4110         return features & ~(NETIF_F_CSUM_MASK | NETIF_F_GSO_MASK);
4111 }
4112
4113 netdev_features_t mlx5e_features_check(struct sk_buff *skb,
4114                                        struct net_device *netdev,
4115                                        netdev_features_t features)
4116 {
4117         struct mlx5e_priv *priv = netdev_priv(netdev);
4118
4119         features = vlan_features_check(skb, features);
4120         features = vxlan_features_check(skb, features);
4121
4122 #ifdef CONFIG_MLX5_EN_IPSEC
4123         if (mlx5e_ipsec_feature_check(skb, netdev, features))
4124                 return features;
4125 #endif
4126
4127         /* Validate if the tunneled packet is being offloaded by HW */
4128         if (skb->encapsulation &&
4129             (features & NETIF_F_CSUM_MASK || features & NETIF_F_GSO_MASK))
4130                 return mlx5e_tunnel_features_check(priv, skb, features);
4131
4132         return features;
4133 }
4134
4135 static void mlx5e_tx_timeout_work(struct work_struct *work)
4136 {
4137         struct mlx5e_priv *priv = container_of(work, struct mlx5e_priv,
4138                                                tx_timeout_work);
4139         bool report_failed = false;
4140         int err;
4141         int i;
4142
4143         rtnl_lock();
4144         mutex_lock(&priv->state_lock);
4145
4146         if (!test_bit(MLX5E_STATE_OPENED, &priv->state))
4147                 goto unlock;
4148
4149         for (i = 0; i < priv->channels.num * priv->channels.params.num_tc; i++) {
4150                 struct netdev_queue *dev_queue =
4151                         netdev_get_tx_queue(priv->netdev, i);
4152                 struct mlx5e_txqsq *sq = priv->txq2sq[i];
4153
4154                 if (!netif_xmit_stopped(dev_queue))
4155                         continue;
4156
4157                 if (mlx5e_tx_reporter_timeout(sq))
4158                         report_failed = true;
4159         }
4160
4161         if (!report_failed)
4162                 goto unlock;
4163
4164         mlx5e_close_locked(priv->netdev);
4165         err = mlx5e_open_locked(priv->netdev);
4166         if (err)
4167                 netdev_err(priv->netdev,
4168                            "mlx5e_open_locked failed recovering from a tx_timeout, err(%d).\n",
4169                            err);
4170
4171 unlock:
4172         mutex_unlock(&priv->state_lock);
4173         rtnl_unlock();
4174 }
4175
4176 static void mlx5e_tx_timeout(struct net_device *dev)
4177 {
4178         struct mlx5e_priv *priv = netdev_priv(dev);
4179
4180         netdev_err(dev, "TX timeout detected\n");
4181         queue_work(priv->wq, &priv->tx_timeout_work);
4182 }
4183
4184 static int mlx5e_xdp_allowed(struct mlx5e_priv *priv, struct bpf_prog *prog)
4185 {
4186         struct net_device *netdev = priv->netdev;
4187         struct mlx5e_channels new_channels = {};
4188
4189         if (priv->channels.params.lro_en) {
4190                 netdev_warn(netdev, "can't set XDP while LRO is on, disable LRO first\n");
4191                 return -EINVAL;
4192         }
4193
4194         if (MLX5_IPSEC_DEV(priv->mdev)) {
4195                 netdev_warn(netdev, "can't set XDP with IPSec offload\n");
4196                 return -EINVAL;
4197         }
4198
4199         new_channels.params = priv->channels.params;
4200         new_channels.params.xdp_prog = prog;
4201
4202         if (!mlx5e_rx_is_linear_skb(priv->mdev, &new_channels.params)) {
4203                 netdev_warn(netdev, "XDP is not allowed with MTU(%d) > %d\n",
4204                             new_channels.params.sw_mtu, MLX5E_XDP_MAX_MTU);
4205                 return -EINVAL;
4206         }
4207
4208         return 0;
4209 }
4210
4211 static int mlx5e_xdp_set(struct net_device *netdev, struct bpf_prog *prog)
4212 {
4213         struct mlx5e_priv *priv = netdev_priv(netdev);
4214         struct bpf_prog *old_prog;
4215         bool reset, was_opened;
4216         int err = 0;
4217         int i;
4218
4219         mutex_lock(&priv->state_lock);
4220
4221         if (prog) {
4222                 err = mlx5e_xdp_allowed(priv, prog);
4223                 if (err)
4224                         goto unlock;
4225         }
4226
4227         was_opened = test_bit(MLX5E_STATE_OPENED, &priv->state);
4228         /* no need for full reset when exchanging programs */
4229         reset = (!priv->channels.params.xdp_prog || !prog);
4230
4231         if (was_opened && reset)
4232                 mlx5e_close_locked(netdev);
4233         if (was_opened && !reset) {
4234                 /* num_channels is invariant here, so we can take the
4235                  * batched reference right upfront.
4236                  */
4237                 prog = bpf_prog_add(prog, priv->channels.num);
4238                 if (IS_ERR(prog)) {
4239                         err = PTR_ERR(prog);
4240                         goto unlock;
4241                 }
4242         }
4243
4244         /* exchange programs, extra prog reference we got from caller
4245          * as long as we don't fail from this point onwards.
4246          */
4247         old_prog = xchg(&priv->channels.params.xdp_prog, prog);
4248         if (old_prog)
4249                 bpf_prog_put(old_prog);
4250
4251         if (reset) /* change RQ type according to priv->xdp_prog */
4252                 mlx5e_set_rq_type(priv->mdev, &priv->channels.params);
4253
4254         if (was_opened && reset)
4255                 mlx5e_open_locked(netdev);
4256
4257         if (!test_bit(MLX5E_STATE_OPENED, &priv->state) || reset)
4258                 goto unlock;
4259
4260         /* exchanging programs w/o reset, we update ref counts on behalf
4261          * of the channels RQs here.
4262          */
4263         for (i = 0; i < priv->channels.num; i++) {
4264                 struct mlx5e_channel *c = priv->channels.c[i];
4265
4266                 clear_bit(MLX5E_RQ_STATE_ENABLED, &c->rq.state);
4267                 napi_synchronize(&c->napi);
4268                 /* prevent mlx5e_poll_rx_cq from accessing rq->xdp_prog */
4269
4270                 old_prog = xchg(&c->rq.xdp_prog, prog);
4271
4272                 set_bit(MLX5E_RQ_STATE_ENABLED, &c->rq.state);
4273                 /* napi_schedule in case we have missed anything */
4274                 napi_schedule(&c->napi);
4275
4276                 if (old_prog)
4277                         bpf_prog_put(old_prog);
4278         }
4279
4280 unlock:
4281         mutex_unlock(&priv->state_lock);
4282         return err;
4283 }
4284
4285 static u32 mlx5e_xdp_query(struct net_device *dev)
4286 {
4287         struct mlx5e_priv *priv = netdev_priv(dev);
4288         const struct bpf_prog *xdp_prog;
4289         u32 prog_id = 0;
4290
4291         mutex_lock(&priv->state_lock);
4292         xdp_prog = priv->channels.params.xdp_prog;
4293         if (xdp_prog)
4294                 prog_id = xdp_prog->aux->id;
4295         mutex_unlock(&priv->state_lock);
4296
4297         return prog_id;
4298 }
4299
4300 static int mlx5e_xdp(struct net_device *dev, struct netdev_bpf *xdp)
4301 {
4302         switch (xdp->command) {
4303         case XDP_SETUP_PROG:
4304                 return mlx5e_xdp_set(dev, xdp->prog);
4305         case XDP_QUERY_PROG:
4306                 xdp->prog_id = mlx5e_xdp_query(dev);
4307                 return 0;
4308         default:
4309                 return -EINVAL;
4310         }
4311 }
4312
4313 #ifdef CONFIG_MLX5_ESWITCH
4314 static int mlx5e_bridge_getlink(struct sk_buff *skb, u32 pid, u32 seq,
4315                                 struct net_device *dev, u32 filter_mask,
4316                                 int nlflags)
4317 {
4318         struct mlx5e_priv *priv = netdev_priv(dev);
4319         struct mlx5_core_dev *mdev = priv->mdev;
4320         u8 mode, setting;
4321         int err;
4322
4323         err = mlx5_eswitch_get_vepa(mdev->priv.eswitch, &setting);
4324         if (err)
4325                 return err;
4326         mode = setting ? BRIDGE_MODE_VEPA : BRIDGE_MODE_VEB;
4327         return ndo_dflt_bridge_getlink(skb, pid, seq, dev,
4328                                        mode,
4329                                        0, 0, nlflags, filter_mask, NULL);
4330 }
4331
4332 static int mlx5e_bridge_setlink(struct net_device *dev, struct nlmsghdr *nlh,
4333                                 u16 flags, struct netlink_ext_ack *extack)
4334 {
4335         struct mlx5e_priv *priv = netdev_priv(dev);
4336         struct mlx5_core_dev *mdev = priv->mdev;
4337         struct nlattr *attr, *br_spec;
4338         u16 mode = BRIDGE_MODE_UNDEF;
4339         u8 setting;
4340         int rem;
4341
4342         br_spec = nlmsg_find_attr(nlh, sizeof(struct ifinfomsg), IFLA_AF_SPEC);
4343         if (!br_spec)
4344                 return -EINVAL;
4345
4346         nla_for_each_nested(attr, br_spec, rem) {
4347                 if (nla_type(attr) != IFLA_BRIDGE_MODE)
4348                         continue;
4349
4350                 if (nla_len(attr) < sizeof(mode))
4351                         return -EINVAL;
4352
4353                 mode = nla_get_u16(attr);
4354                 if (mode > BRIDGE_MODE_VEPA)
4355                         return -EINVAL;
4356
4357                 break;
4358         }
4359
4360         if (mode == BRIDGE_MODE_UNDEF)
4361                 return -EINVAL;
4362
4363         setting = (mode == BRIDGE_MODE_VEPA) ?  1 : 0;
4364         return mlx5_eswitch_set_vepa(mdev->priv.eswitch, setting);
4365 }
4366 #endif
4367
4368 const struct net_device_ops mlx5e_netdev_ops = {
4369         .ndo_open                = mlx5e_open,
4370         .ndo_stop                = mlx5e_close,
4371         .ndo_start_xmit          = mlx5e_xmit,
4372         .ndo_setup_tc            = mlx5e_setup_tc,
4373         .ndo_select_queue        = mlx5e_select_queue,
4374         .ndo_get_stats64         = mlx5e_get_stats,
4375         .ndo_set_rx_mode         = mlx5e_set_rx_mode,
4376         .ndo_set_mac_address     = mlx5e_set_mac,
4377         .ndo_vlan_rx_add_vid     = mlx5e_vlan_rx_add_vid,
4378         .ndo_vlan_rx_kill_vid    = mlx5e_vlan_rx_kill_vid,
4379         .ndo_set_features        = mlx5e_set_features,
4380         .ndo_fix_features        = mlx5e_fix_features,
4381         .ndo_change_mtu          = mlx5e_change_nic_mtu,
4382         .ndo_do_ioctl            = mlx5e_ioctl,
4383         .ndo_set_tx_maxrate      = mlx5e_set_tx_maxrate,
4384         .ndo_udp_tunnel_add      = mlx5e_add_vxlan_port,
4385         .ndo_udp_tunnel_del      = mlx5e_del_vxlan_port,
4386         .ndo_features_check      = mlx5e_features_check,
4387         .ndo_tx_timeout          = mlx5e_tx_timeout,
4388         .ndo_bpf                 = mlx5e_xdp,
4389         .ndo_xdp_xmit            = mlx5e_xdp_xmit,
4390 #ifdef CONFIG_MLX5_EN_ARFS
4391         .ndo_rx_flow_steer       = mlx5e_rx_flow_steer,
4392 #endif
4393 #ifdef CONFIG_MLX5_ESWITCH
4394         .ndo_bridge_setlink      = mlx5e_bridge_setlink,
4395         .ndo_bridge_getlink      = mlx5e_bridge_getlink,
4396
4397         /* SRIOV E-Switch NDOs */
4398         .ndo_set_vf_mac          = mlx5e_set_vf_mac,
4399         .ndo_set_vf_vlan         = mlx5e_set_vf_vlan,
4400         .ndo_set_vf_spoofchk     = mlx5e_set_vf_spoofchk,
4401         .ndo_set_vf_trust        = mlx5e_set_vf_trust,
4402         .ndo_set_vf_rate         = mlx5e_set_vf_rate,
4403         .ndo_get_vf_config       = mlx5e_get_vf_config,
4404         .ndo_set_vf_link_state   = mlx5e_set_vf_link_state,
4405         .ndo_get_vf_stats        = mlx5e_get_vf_stats,
4406 #endif
4407 };
4408
4409 static int mlx5e_check_required_hca_cap(struct mlx5_core_dev *mdev)
4410 {
4411         if (MLX5_CAP_GEN(mdev, port_type) != MLX5_CAP_PORT_TYPE_ETH)
4412                 return -EOPNOTSUPP;
4413         if (!MLX5_CAP_GEN(mdev, eth_net_offloads) ||
4414             !MLX5_CAP_GEN(mdev, nic_flow_table) ||
4415             !MLX5_CAP_ETH(mdev, csum_cap) ||
4416             !MLX5_CAP_ETH(mdev, max_lso_cap) ||
4417             !MLX5_CAP_ETH(mdev, vlan_cap) ||
4418             !MLX5_CAP_ETH(mdev, rss_ind_tbl_cap) ||
4419             MLX5_CAP_FLOWTABLE(mdev,
4420                                flow_table_properties_nic_receive.max_ft_level)
4421                                < 3) {
4422                 mlx5_core_warn(mdev,
4423                                "Not creating net device, some required device capabilities are missing\n");
4424                 return -EOPNOTSUPP;
4425         }
4426         if (!MLX5_CAP_ETH(mdev, self_lb_en_modifiable))
4427                 mlx5_core_warn(mdev, "Self loop back prevention is not supported\n");
4428         if (!MLX5_CAP_GEN(mdev, cq_moderation))
4429                 mlx5_core_warn(mdev, "CQ moderation is not supported\n");
4430
4431         return 0;
4432 }
4433
4434 void mlx5e_build_default_indir_rqt(u32 *indirection_rqt, int len,
4435                                    int num_channels)
4436 {
4437         int i;
4438
4439         for (i = 0; i < len; i++)
4440                 indirection_rqt[i] = i % num_channels;
4441 }
4442
4443 static bool slow_pci_heuristic(struct mlx5_core_dev *mdev)
4444 {
4445         u32 link_speed = 0;
4446         u32 pci_bw = 0;
4447
4448         mlx5e_port_max_linkspeed(mdev, &link_speed);
4449         pci_bw = pcie_bandwidth_available(mdev->pdev, NULL, NULL, NULL);
4450         mlx5_core_dbg_once(mdev, "Max link speed = %d, PCI BW = %d\n",
4451                            link_speed, pci_bw);
4452
4453 #define MLX5E_SLOW_PCI_RATIO (2)
4454
4455         return link_speed && pci_bw &&
4456                 link_speed > MLX5E_SLOW_PCI_RATIO * pci_bw;
4457 }
4458
4459 static struct net_dim_cq_moder mlx5e_get_def_tx_moderation(u8 cq_period_mode)
4460 {
4461         struct net_dim_cq_moder moder;
4462
4463         moder.cq_period_mode = cq_period_mode;
4464         moder.pkts = MLX5E_PARAMS_DEFAULT_TX_CQ_MODERATION_PKTS;
4465         moder.usec = MLX5E_PARAMS_DEFAULT_TX_CQ_MODERATION_USEC;
4466         if (cq_period_mode == MLX5_CQ_PERIOD_MODE_START_FROM_CQE)
4467                 moder.usec = MLX5E_PARAMS_DEFAULT_TX_CQ_MODERATION_USEC_FROM_CQE;
4468
4469         return moder;
4470 }
4471
4472 static struct net_dim_cq_moder mlx5e_get_def_rx_moderation(u8 cq_period_mode)
4473 {
4474         struct net_dim_cq_moder moder;
4475
4476         moder.cq_period_mode = cq_period_mode;
4477         moder.pkts = MLX5E_PARAMS_DEFAULT_RX_CQ_MODERATION_PKTS;
4478         moder.usec = MLX5E_PARAMS_DEFAULT_RX_CQ_MODERATION_USEC;
4479         if (cq_period_mode == MLX5_CQ_PERIOD_MODE_START_FROM_CQE)
4480                 moder.usec = MLX5E_PARAMS_DEFAULT_RX_CQ_MODERATION_USEC_FROM_CQE;
4481
4482         return moder;
4483 }
4484
4485 static u8 mlx5_to_net_dim_cq_period_mode(u8 cq_period_mode)
4486 {
4487         return cq_period_mode == MLX5_CQ_PERIOD_MODE_START_FROM_CQE ?
4488                 NET_DIM_CQ_PERIOD_MODE_START_FROM_CQE :
4489                 NET_DIM_CQ_PERIOD_MODE_START_FROM_EQE;
4490 }
4491
4492 void mlx5e_set_tx_cq_mode_params(struct mlx5e_params *params, u8 cq_period_mode)
4493 {
4494         if (params->tx_dim_enabled) {
4495                 u8 dim_period_mode = mlx5_to_net_dim_cq_period_mode(cq_period_mode);
4496
4497                 params->tx_cq_moderation = net_dim_get_def_tx_moderation(dim_period_mode);
4498         } else {
4499                 params->tx_cq_moderation = mlx5e_get_def_tx_moderation(cq_period_mode);
4500         }
4501
4502         MLX5E_SET_PFLAG(params, MLX5E_PFLAG_TX_CQE_BASED_MODER,
4503                         params->tx_cq_moderation.cq_period_mode ==
4504                                 MLX5_CQ_PERIOD_MODE_START_FROM_CQE);
4505 }
4506
4507 void mlx5e_set_rx_cq_mode_params(struct mlx5e_params *params, u8 cq_period_mode)
4508 {
4509         if (params->rx_dim_enabled) {
4510                 u8 dim_period_mode = mlx5_to_net_dim_cq_period_mode(cq_period_mode);
4511
4512                 params->rx_cq_moderation = net_dim_get_def_rx_moderation(dim_period_mode);
4513         } else {
4514                 params->rx_cq_moderation = mlx5e_get_def_rx_moderation(cq_period_mode);
4515         }
4516
4517         MLX5E_SET_PFLAG(params, MLX5E_PFLAG_RX_CQE_BASED_MODER,
4518                         params->rx_cq_moderation.cq_period_mode ==
4519                                 MLX5_CQ_PERIOD_MODE_START_FROM_CQE);
4520 }
4521
4522 static u32 mlx5e_choose_lro_timeout(struct mlx5_core_dev *mdev, u32 wanted_timeout)
4523 {
4524         int i;
4525
4526         /* The supported periods are organized in ascending order */
4527         for (i = 0; i < MLX5E_LRO_TIMEOUT_ARR_SIZE - 1; i++)
4528                 if (MLX5_CAP_ETH(mdev, lro_timer_supported_periods[i]) >= wanted_timeout)
4529                         break;
4530
4531         return MLX5_CAP_ETH(mdev, lro_timer_supported_periods[i]);
4532 }
4533
4534 void mlx5e_build_rq_params(struct mlx5_core_dev *mdev,
4535                            struct mlx5e_params *params)
4536 {
4537         /* Prefer Striding RQ, unless any of the following holds:
4538          * - Striding RQ configuration is not possible/supported.
4539          * - Slow PCI heuristic.
4540          * - Legacy RQ would use linear SKB while Striding RQ would use non-linear.
4541          */
4542         if (!slow_pci_heuristic(mdev) &&
4543             mlx5e_striding_rq_possible(mdev, params) &&
4544             (mlx5e_rx_mpwqe_is_linear_skb(mdev, params) ||
4545              !mlx5e_rx_is_linear_skb(mdev, params)))
4546                 MLX5E_SET_PFLAG(params, MLX5E_PFLAG_RX_STRIDING_RQ, true);
4547         mlx5e_set_rq_type(mdev, params);
4548         mlx5e_init_rq_type_params(mdev, params);
4549 }
4550
4551 void mlx5e_build_rss_params(struct mlx5e_rss_params *rss_params,
4552                             u16 num_channels)
4553 {
4554         enum mlx5e_traffic_types tt;
4555
4556         rss_params->hfunc = ETH_RSS_HASH_XOR;
4557         netdev_rss_key_fill(rss_params->toeplitz_hash_key,
4558                             sizeof(rss_params->toeplitz_hash_key));
4559         mlx5e_build_default_indir_rqt(rss_params->indirection_rqt,
4560                                       MLX5E_INDIR_RQT_SIZE, num_channels);
4561         for (tt = 0; tt < MLX5E_NUM_INDIR_TIRS; tt++)
4562                 rss_params->rx_hash_fields[tt] =
4563                         tirc_default_config[tt].rx_hash_fields;
4564 }
4565
4566 void mlx5e_build_nic_params(struct mlx5_core_dev *mdev,
4567                             struct mlx5e_rss_params *rss_params,
4568                             struct mlx5e_params *params,
4569                             u16 max_channels, u16 mtu)
4570 {
4571         u8 rx_cq_period_mode;
4572
4573         params->sw_mtu = mtu;
4574         params->hard_mtu = MLX5E_ETH_HARD_MTU;
4575         params->num_channels = max_channels;
4576         params->num_tc       = 1;
4577
4578         /* SQ */
4579         params->log_sq_size = is_kdump_kernel() ?
4580                 MLX5E_PARAMS_MINIMUM_LOG_SQ_SIZE :
4581                 MLX5E_PARAMS_DEFAULT_LOG_SQ_SIZE;
4582
4583         /* XDP SQ */
4584         MLX5E_SET_PFLAG(params, MLX5E_PFLAG_XDP_TX_MPWQE,
4585                         MLX5_CAP_ETH(mdev, enhanced_multi_pkt_send_wqe));
4586
4587         /* set CQE compression */
4588         params->rx_cqe_compress_def = false;
4589         if (MLX5_CAP_GEN(mdev, cqe_compression) &&
4590             MLX5_CAP_GEN(mdev, vport_group_manager))
4591                 params->rx_cqe_compress_def = slow_pci_heuristic(mdev);
4592
4593         MLX5E_SET_PFLAG(params, MLX5E_PFLAG_RX_CQE_COMPRESS, params->rx_cqe_compress_def);
4594         MLX5E_SET_PFLAG(params, MLX5E_PFLAG_RX_NO_CSUM_COMPLETE, false);
4595
4596         /* RQ */
4597         mlx5e_build_rq_params(mdev, params);
4598
4599         /* HW LRO */
4600
4601         /* TODO: && MLX5_CAP_ETH(mdev, lro_cap) */
4602         if (params->rq_wq_type == MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ)
4603                 if (!mlx5e_rx_mpwqe_is_linear_skb(mdev, params))
4604                         params->lro_en = !slow_pci_heuristic(mdev);
4605         params->lro_timeout = mlx5e_choose_lro_timeout(mdev, MLX5E_DEFAULT_LRO_TIMEOUT);
4606
4607         /* CQ moderation params */
4608         rx_cq_period_mode = MLX5_CAP_GEN(mdev, cq_period_start_from_cqe) ?
4609                         MLX5_CQ_PERIOD_MODE_START_FROM_CQE :
4610                         MLX5_CQ_PERIOD_MODE_START_FROM_EQE;
4611         params->rx_dim_enabled = MLX5_CAP_GEN(mdev, cq_moderation);
4612         params->tx_dim_enabled = MLX5_CAP_GEN(mdev, cq_moderation);
4613         mlx5e_set_rx_cq_mode_params(params, rx_cq_period_mode);
4614         mlx5e_set_tx_cq_mode_params(params, MLX5_CQ_PERIOD_MODE_START_FROM_EQE);
4615
4616         /* TX inline */
4617         params->tx_min_inline_mode = mlx5e_params_calculate_tx_min_inline(mdev);
4618
4619         /* RSS */
4620         mlx5e_build_rss_params(rss_params, params->num_channels);
4621 }
4622
4623 static void mlx5e_set_netdev_dev_addr(struct net_device *netdev)
4624 {
4625         struct mlx5e_priv *priv = netdev_priv(netdev);
4626
4627         mlx5_query_nic_vport_mac_address(priv->mdev, 0, netdev->dev_addr);
4628         if (is_zero_ether_addr(netdev->dev_addr) &&
4629             !MLX5_CAP_GEN(priv->mdev, vport_group_manager)) {
4630                 eth_hw_addr_random(netdev);
4631                 mlx5_core_info(priv->mdev, "Assigned random MAC address %pM\n", netdev->dev_addr);
4632         }
4633 }
4634
4635 static void mlx5e_build_nic_netdev(struct net_device *netdev)
4636 {
4637         struct mlx5e_priv *priv = netdev_priv(netdev);
4638         struct mlx5_core_dev *mdev = priv->mdev;
4639         bool fcs_supported;
4640         bool fcs_enabled;
4641
4642         SET_NETDEV_DEV(netdev, &mdev->pdev->dev);
4643
4644         netdev->netdev_ops = &mlx5e_netdev_ops;
4645
4646 #ifdef CONFIG_MLX5_CORE_EN_DCB
4647         if (MLX5_CAP_GEN(mdev, vport_group_manager) && MLX5_CAP_GEN(mdev, qos))
4648                 netdev->dcbnl_ops = &mlx5e_dcbnl_ops;
4649 #endif
4650
4651         netdev->watchdog_timeo    = 15 * HZ;
4652
4653         netdev->ethtool_ops       = &mlx5e_ethtool_ops;
4654
4655         netdev->vlan_features    |= NETIF_F_SG;
4656         netdev->vlan_features    |= NETIF_F_IP_CSUM;
4657         netdev->vlan_features    |= NETIF_F_IPV6_CSUM;
4658         netdev->vlan_features    |= NETIF_F_GRO;
4659         netdev->vlan_features    |= NETIF_F_TSO;
4660         netdev->vlan_features    |= NETIF_F_TSO6;
4661         netdev->vlan_features    |= NETIF_F_RXCSUM;
4662         netdev->vlan_features    |= NETIF_F_RXHASH;
4663
4664         netdev->hw_enc_features  |= NETIF_F_HW_VLAN_CTAG_TX;
4665         netdev->hw_enc_features  |= NETIF_F_HW_VLAN_CTAG_RX;
4666
4667         if (!!MLX5_CAP_ETH(mdev, lro_cap) &&
4668             mlx5e_check_fragmented_striding_rq_cap(mdev))
4669                 netdev->vlan_features    |= NETIF_F_LRO;
4670
4671         netdev->hw_features       = netdev->vlan_features;
4672         netdev->hw_features      |= NETIF_F_HW_VLAN_CTAG_TX;
4673         netdev->hw_features      |= NETIF_F_HW_VLAN_CTAG_RX;
4674         netdev->hw_features      |= NETIF_F_HW_VLAN_CTAG_FILTER;
4675         netdev->hw_features      |= NETIF_F_HW_VLAN_STAG_TX;
4676
4677         if (mlx5_vxlan_allowed(mdev->vxlan) || MLX5_CAP_ETH(mdev, tunnel_stateless_gre)) {
4678                 netdev->hw_enc_features |= NETIF_F_IP_CSUM;
4679                 netdev->hw_enc_features |= NETIF_F_IPV6_CSUM;
4680                 netdev->hw_enc_features |= NETIF_F_TSO;
4681                 netdev->hw_enc_features |= NETIF_F_TSO6;
4682                 netdev->hw_enc_features |= NETIF_F_GSO_PARTIAL;
4683         }
4684
4685         if (mlx5_vxlan_allowed(mdev->vxlan)) {
4686                 netdev->hw_features     |= NETIF_F_GSO_UDP_TUNNEL |
4687                                            NETIF_F_GSO_UDP_TUNNEL_CSUM;
4688                 netdev->hw_enc_features |= NETIF_F_GSO_UDP_TUNNEL |
4689                                            NETIF_F_GSO_UDP_TUNNEL_CSUM;
4690                 netdev->gso_partial_features = NETIF_F_GSO_UDP_TUNNEL_CSUM;
4691         }
4692
4693         if (MLX5_CAP_ETH(mdev, tunnel_stateless_gre)) {
4694                 netdev->hw_features     |= NETIF_F_GSO_GRE |
4695                                            NETIF_F_GSO_GRE_CSUM;
4696                 netdev->hw_enc_features |= NETIF_F_GSO_GRE |
4697                                            NETIF_F_GSO_GRE_CSUM;
4698                 netdev->gso_partial_features |= NETIF_F_GSO_GRE |
4699                                                 NETIF_F_GSO_GRE_CSUM;
4700         }
4701
4702         netdev->hw_features                      |= NETIF_F_GSO_PARTIAL;
4703         netdev->gso_partial_features             |= NETIF_F_GSO_UDP_L4;
4704         netdev->hw_features                      |= NETIF_F_GSO_UDP_L4;
4705         netdev->features                         |= NETIF_F_GSO_UDP_L4;
4706
4707         mlx5_query_port_fcs(mdev, &fcs_supported, &fcs_enabled);
4708
4709         if (fcs_supported)
4710                 netdev->hw_features |= NETIF_F_RXALL;
4711
4712         if (MLX5_CAP_ETH(mdev, scatter_fcs))
4713                 netdev->hw_features |= NETIF_F_RXFCS;
4714
4715         netdev->features          = netdev->hw_features;
4716         if (!priv->channels.params.lro_en)
4717                 netdev->features  &= ~NETIF_F_LRO;
4718
4719         if (fcs_enabled)
4720                 netdev->features  &= ~NETIF_F_RXALL;
4721
4722         if (!priv->channels.params.scatter_fcs_en)
4723                 netdev->features  &= ~NETIF_F_RXFCS;
4724
4725 #define FT_CAP(f) MLX5_CAP_FLOWTABLE(mdev, flow_table_properties_nic_receive.f)
4726         if (FT_CAP(flow_modify_en) &&
4727             FT_CAP(modify_root) &&
4728             FT_CAP(identified_miss_table_mode) &&
4729             FT_CAP(flow_table_modify)) {
4730 #ifdef CONFIG_MLX5_ESWITCH
4731                 netdev->hw_features      |= NETIF_F_HW_TC;
4732 #endif
4733 #ifdef CONFIG_MLX5_EN_ARFS
4734                 netdev->hw_features      |= NETIF_F_NTUPLE;
4735 #endif
4736         }
4737
4738         netdev->features         |= NETIF_F_HIGHDMA;
4739         netdev->features         |= NETIF_F_HW_VLAN_STAG_FILTER;
4740
4741         netdev->priv_flags       |= IFF_UNICAST_FLT;
4742
4743         mlx5e_set_netdev_dev_addr(netdev);
4744         mlx5e_ipsec_build_netdev(priv);
4745         mlx5e_tls_build_netdev(priv);
4746 }
4747
4748 void mlx5e_create_q_counters(struct mlx5e_priv *priv)
4749 {
4750         struct mlx5_core_dev *mdev = priv->mdev;
4751         int err;
4752
4753         err = mlx5_core_alloc_q_counter(mdev, &priv->q_counter);
4754         if (err) {
4755                 mlx5_core_warn(mdev, "alloc queue counter failed, %d\n", err);
4756                 priv->q_counter = 0;
4757         }
4758
4759         err = mlx5_core_alloc_q_counter(mdev, &priv->drop_rq_q_counter);
4760         if (err) {
4761                 mlx5_core_warn(mdev, "alloc drop RQ counter failed, %d\n", err);
4762                 priv->drop_rq_q_counter = 0;
4763         }
4764 }
4765
4766 void mlx5e_destroy_q_counters(struct mlx5e_priv *priv)
4767 {
4768         if (priv->q_counter)
4769                 mlx5_core_dealloc_q_counter(priv->mdev, priv->q_counter);
4770
4771         if (priv->drop_rq_q_counter)
4772                 mlx5_core_dealloc_q_counter(priv->mdev, priv->drop_rq_q_counter);
4773 }
4774
4775 static int mlx5e_nic_init(struct mlx5_core_dev *mdev,
4776                           struct net_device *netdev,
4777                           const struct mlx5e_profile *profile,
4778                           void *ppriv)
4779 {
4780         struct mlx5e_priv *priv = netdev_priv(netdev);
4781         struct mlx5e_rss_params *rss = &priv->rss_params;
4782         int err;
4783
4784         err = mlx5e_netdev_init(netdev, priv, mdev, profile, ppriv);
4785         if (err)
4786                 return err;
4787
4788         mlx5e_build_nic_params(mdev, rss, &priv->channels.params,
4789                                mlx5e_get_netdev_max_channels(netdev),
4790                                netdev->mtu);
4791
4792         mlx5e_timestamp_init(priv);
4793
4794         err = mlx5e_ipsec_init(priv);
4795         if (err)
4796                 mlx5_core_err(mdev, "IPSec initialization failed, %d\n", err);
4797         err = mlx5e_tls_init(priv);
4798         if (err)
4799                 mlx5_core_err(mdev, "TLS initialization failed, %d\n", err);
4800         mlx5e_build_nic_netdev(netdev);
4801         mlx5e_build_tc2txq_maps(priv);
4802
4803         return 0;
4804 }
4805
4806 static void mlx5e_nic_cleanup(struct mlx5e_priv *priv)
4807 {
4808         mlx5e_tls_cleanup(priv);
4809         mlx5e_ipsec_cleanup(priv);
4810         mlx5e_netdev_cleanup(priv->netdev, priv);
4811 }
4812
4813 static int mlx5e_init_nic_rx(struct mlx5e_priv *priv)
4814 {
4815         struct mlx5_core_dev *mdev = priv->mdev;
4816         int err;
4817
4818         mlx5e_create_q_counters(priv);
4819
4820         err = mlx5e_open_drop_rq(priv, &priv->drop_rq);
4821         if (err) {
4822                 mlx5_core_err(mdev, "open drop rq failed, %d\n", err);
4823                 goto err_destroy_q_counters;
4824         }
4825
4826         err = mlx5e_create_indirect_rqt(priv);
4827         if (err)
4828                 goto err_close_drop_rq;
4829
4830         err = mlx5e_create_direct_rqts(priv);
4831         if (err)
4832                 goto err_destroy_indirect_rqts;
4833
4834         err = mlx5e_create_indirect_tirs(priv, true);
4835         if (err)
4836                 goto err_destroy_direct_rqts;
4837
4838         err = mlx5e_create_direct_tirs(priv);
4839         if (err)
4840                 goto err_destroy_indirect_tirs;
4841
4842         err = mlx5e_create_flow_steering(priv);
4843         if (err) {
4844                 mlx5_core_warn(mdev, "create flow steering failed, %d\n", err);
4845                 goto err_destroy_direct_tirs;
4846         }
4847
4848         err = mlx5e_tc_nic_init(priv);
4849         if (err)
4850                 goto err_destroy_flow_steering;
4851
4852         return 0;
4853
4854 err_destroy_flow_steering:
4855         mlx5e_destroy_flow_steering(priv);
4856 err_destroy_direct_tirs:
4857         mlx5e_destroy_direct_tirs(priv);
4858 err_destroy_indirect_tirs:
4859         mlx5e_destroy_indirect_tirs(priv, true);
4860 err_destroy_direct_rqts:
4861         mlx5e_destroy_direct_rqts(priv);
4862 err_destroy_indirect_rqts:
4863         mlx5e_destroy_rqt(priv, &priv->indir_rqt);
4864 err_close_drop_rq:
4865         mlx5e_close_drop_rq(&priv->drop_rq);
4866 err_destroy_q_counters:
4867         mlx5e_destroy_q_counters(priv);
4868         return err;
4869 }
4870
4871 static void mlx5e_cleanup_nic_rx(struct mlx5e_priv *priv)
4872 {
4873         mlx5e_tc_nic_cleanup(priv);
4874         mlx5e_destroy_flow_steering(priv);
4875         mlx5e_destroy_direct_tirs(priv);
4876         mlx5e_destroy_indirect_tirs(priv, true);
4877         mlx5e_destroy_direct_rqts(priv);
4878         mlx5e_destroy_rqt(priv, &priv->indir_rqt);
4879         mlx5e_close_drop_rq(&priv->drop_rq);
4880         mlx5e_destroy_q_counters(priv);
4881 }
4882
4883 static int mlx5e_init_nic_tx(struct mlx5e_priv *priv)
4884 {
4885         int err;
4886
4887         err = mlx5e_create_tises(priv);
4888         if (err) {
4889                 mlx5_core_warn(priv->mdev, "create tises failed, %d\n", err);
4890                 return err;
4891         }
4892
4893 #ifdef CONFIG_MLX5_CORE_EN_DCB
4894         mlx5e_dcbnl_initialize(priv);
4895 #endif
4896         mlx5e_tx_reporter_create(priv);
4897         return 0;
4898 }
4899
4900 static void mlx5e_nic_enable(struct mlx5e_priv *priv)
4901 {
4902         struct net_device *netdev = priv->netdev;
4903         struct mlx5_core_dev *mdev = priv->mdev;
4904         u16 max_mtu;
4905
4906         mlx5e_init_l2_addr(priv);
4907
4908         /* Marking the link as currently not needed by the Driver */
4909         if (!netif_running(netdev))
4910                 mlx5_set_port_admin_status(mdev, MLX5_PORT_DOWN);
4911
4912         /* MTU range: 68 - hw-specific max */
4913         netdev->min_mtu = ETH_MIN_MTU;
4914         mlx5_query_port_max_mtu(priv->mdev, &max_mtu, 1);
4915         netdev->max_mtu = MLX5E_HW2SW_MTU(&priv->channels.params, max_mtu);
4916         mlx5e_set_dev_port_mtu(priv);
4917
4918         mlx5_lag_add(mdev, netdev);
4919
4920         mlx5e_enable_async_events(priv);
4921         if (mlx5e_monitor_counter_supported(priv))
4922                 mlx5e_monitor_counter_init(priv);
4923
4924         if (netdev->reg_state != NETREG_REGISTERED)
4925                 return;
4926 #ifdef CONFIG_MLX5_CORE_EN_DCB
4927         mlx5e_dcbnl_init_app(priv);
4928 #endif
4929
4930         queue_work(priv->wq, &priv->set_rx_mode_work);
4931
4932         rtnl_lock();
4933         if (netif_running(netdev))
4934                 mlx5e_open(netdev);
4935         netif_device_attach(netdev);
4936         rtnl_unlock();
4937 }
4938
4939 static void mlx5e_nic_disable(struct mlx5e_priv *priv)
4940 {
4941         struct mlx5_core_dev *mdev = priv->mdev;
4942
4943 #ifdef CONFIG_MLX5_CORE_EN_DCB
4944         if (priv->netdev->reg_state == NETREG_REGISTERED)
4945                 mlx5e_dcbnl_delete_app(priv);
4946 #endif
4947
4948         rtnl_lock();
4949         if (netif_running(priv->netdev))
4950                 mlx5e_close(priv->netdev);
4951         netif_device_detach(priv->netdev);
4952         rtnl_unlock();
4953
4954         queue_work(priv->wq, &priv->set_rx_mode_work);
4955
4956         if (mlx5e_monitor_counter_supported(priv))
4957                 mlx5e_monitor_counter_cleanup(priv);
4958
4959         mlx5e_disable_async_events(priv);
4960         mlx5_lag_remove(mdev);
4961 }
4962
4963 static const struct mlx5e_profile mlx5e_nic_profile = {
4964         .init              = mlx5e_nic_init,
4965         .cleanup           = mlx5e_nic_cleanup,
4966         .init_rx           = mlx5e_init_nic_rx,
4967         .cleanup_rx        = mlx5e_cleanup_nic_rx,
4968         .init_tx           = mlx5e_init_nic_tx,
4969         .cleanup_tx        = mlx5e_cleanup_nic_tx,
4970         .enable            = mlx5e_nic_enable,
4971         .disable           = mlx5e_nic_disable,
4972         .update_stats      = mlx5e_update_ndo_stats,
4973         .update_carrier    = mlx5e_update_carrier,
4974         .rx_handlers.handle_rx_cqe       = mlx5e_handle_rx_cqe,
4975         .rx_handlers.handle_rx_cqe_mpwqe = mlx5e_handle_rx_cqe_mpwrq,
4976         .max_tc            = MLX5E_MAX_NUM_TC,
4977 };
4978
4979 /* mlx5e generic netdev management API (move to en_common.c) */
4980
4981 /* mlx5e_netdev_init/cleanup must be called from profile->init/cleanup callbacks */
4982 int mlx5e_netdev_init(struct net_device *netdev,
4983                       struct mlx5e_priv *priv,
4984                       struct mlx5_core_dev *mdev,
4985                       const struct mlx5e_profile *profile,
4986                       void *ppriv)
4987 {
4988         /* priv init */
4989         priv->mdev        = mdev;
4990         priv->netdev      = netdev;
4991         priv->profile     = profile;
4992         priv->ppriv       = ppriv;
4993         priv->msglevel    = MLX5E_MSG_LEVEL;
4994         priv->max_opened_tc = 1;
4995
4996         mutex_init(&priv->state_lock);
4997         INIT_WORK(&priv->update_carrier_work, mlx5e_update_carrier_work);
4998         INIT_WORK(&priv->set_rx_mode_work, mlx5e_set_rx_mode_work);
4999         INIT_WORK(&priv->tx_timeout_work, mlx5e_tx_timeout_work);
5000         INIT_WORK(&priv->update_stats_work, mlx5e_update_stats_work);
5001
5002         priv->wq = create_singlethread_workqueue("mlx5e");
5003         if (!priv->wq)
5004                 return -ENOMEM;
5005
5006         /* netdev init */
5007         netif_carrier_off(netdev);
5008
5009 #ifdef CONFIG_MLX5_EN_ARFS
5010         netdev->rx_cpu_rmap =  mlx5_eq_table_get_rmap(mdev);
5011 #endif
5012
5013         return 0;
5014 }
5015
5016 void mlx5e_netdev_cleanup(struct net_device *netdev, struct mlx5e_priv *priv)
5017 {
5018         destroy_workqueue(priv->wq);
5019 }
5020
5021 struct net_device *mlx5e_create_netdev(struct mlx5_core_dev *mdev,
5022                                        const struct mlx5e_profile *profile,
5023                                        int nch,
5024                                        void *ppriv)
5025 {
5026         struct net_device *netdev;
5027         int err;
5028
5029         netdev = alloc_etherdev_mqs(sizeof(struct mlx5e_priv),
5030                                     nch * profile->max_tc,
5031                                     nch);
5032         if (!netdev) {
5033                 mlx5_core_err(mdev, "alloc_etherdev_mqs() failed\n");
5034                 return NULL;
5035         }
5036
5037         err = profile->init(mdev, netdev, profile, ppriv);
5038         if (err) {
5039                 mlx5_core_err(mdev, "failed to init mlx5e profile %d\n", err);
5040                 goto err_free_netdev;
5041         }
5042
5043         return netdev;
5044
5045 err_free_netdev:
5046         free_netdev(netdev);
5047
5048         return NULL;
5049 }
5050
5051 int mlx5e_attach_netdev(struct mlx5e_priv *priv)
5052 {
5053         const struct mlx5e_profile *profile;
5054         int max_nch;
5055         int err;
5056
5057         profile = priv->profile;
5058         clear_bit(MLX5E_STATE_DESTROYING, &priv->state);
5059
5060         /* max number of channels may have changed */
5061         max_nch = mlx5e_get_max_num_channels(priv->mdev);
5062         if (priv->channels.params.num_channels > max_nch) {
5063                 mlx5_core_warn(priv->mdev, "MLX5E: Reducing number of channels to %d\n", max_nch);
5064                 priv->channels.params.num_channels = max_nch;
5065                 mlx5e_build_default_indir_rqt(priv->rss_params.indirection_rqt,
5066                                               MLX5E_INDIR_RQT_SIZE, max_nch);
5067         }
5068
5069         err = profile->init_tx(priv);
5070         if (err)
5071                 goto out;
5072
5073         err = profile->init_rx(priv);
5074         if (err)
5075                 goto err_cleanup_tx;
5076
5077         if (profile->enable)
5078                 profile->enable(priv);
5079
5080         return 0;
5081
5082 err_cleanup_tx:
5083         profile->cleanup_tx(priv);
5084
5085 out:
5086         return err;
5087 }
5088
5089 void mlx5e_detach_netdev(struct mlx5e_priv *priv)
5090 {
5091         const struct mlx5e_profile *profile = priv->profile;
5092
5093         set_bit(MLX5E_STATE_DESTROYING, &priv->state);
5094
5095         if (profile->disable)
5096                 profile->disable(priv);
5097         flush_workqueue(priv->wq);
5098
5099         profile->cleanup_rx(priv);
5100         profile->cleanup_tx(priv);
5101         cancel_work_sync(&priv->update_stats_work);
5102 }
5103
5104 void mlx5e_destroy_netdev(struct mlx5e_priv *priv)
5105 {
5106         const struct mlx5e_profile *profile = priv->profile;
5107         struct net_device *netdev = priv->netdev;
5108
5109         if (profile->cleanup)
5110                 profile->cleanup(priv);
5111         free_netdev(netdev);
5112 }
5113
5114 /* mlx5e_attach and mlx5e_detach scope should be only creating/destroying
5115  * hardware contexts and to connect it to the current netdev.
5116  */
5117 static int mlx5e_attach(struct mlx5_core_dev *mdev, void *vpriv)
5118 {
5119         struct mlx5e_priv *priv = vpriv;
5120         struct net_device *netdev = priv->netdev;
5121         int err;
5122
5123         if (netif_device_present(netdev))
5124                 return 0;
5125
5126         err = mlx5e_create_mdev_resources(mdev);
5127         if (err)
5128                 return err;
5129
5130         err = mlx5e_attach_netdev(priv);
5131         if (err) {
5132                 mlx5e_destroy_mdev_resources(mdev);
5133                 return err;
5134         }
5135
5136         return 0;
5137 }
5138
5139 static void mlx5e_detach(struct mlx5_core_dev *mdev, void *vpriv)
5140 {
5141         struct mlx5e_priv *priv = vpriv;
5142         struct net_device *netdev = priv->netdev;
5143
5144         if (!netif_device_present(netdev))
5145                 return;
5146
5147         mlx5e_detach_netdev(priv);
5148         mlx5e_destroy_mdev_resources(mdev);
5149 }
5150
5151 static void *mlx5e_add(struct mlx5_core_dev *mdev)
5152 {
5153         struct net_device *netdev;
5154         void *priv;
5155         int err;
5156         int nch;
5157
5158         err = mlx5e_check_required_hca_cap(mdev);
5159         if (err)
5160                 return NULL;
5161
5162 #ifdef CONFIG_MLX5_ESWITCH
5163         if (MLX5_ESWITCH_MANAGER(mdev) &&
5164             mlx5_eswitch_mode(mdev->priv.eswitch) == SRIOV_OFFLOADS) {
5165                 mlx5e_rep_register_vport_reps(mdev);
5166                 return mdev;
5167         }
5168 #endif
5169
5170         nch = mlx5e_get_max_num_channels(mdev);
5171         netdev = mlx5e_create_netdev(mdev, &mlx5e_nic_profile, nch, NULL);
5172         if (!netdev) {
5173                 mlx5_core_err(mdev, "mlx5e_create_netdev failed\n");
5174                 return NULL;
5175         }
5176
5177         priv = netdev_priv(netdev);
5178
5179         err = mlx5e_attach(mdev, priv);
5180         if (err) {
5181                 mlx5_core_err(mdev, "mlx5e_attach failed, %d\n", err);
5182                 goto err_destroy_netdev;
5183         }
5184
5185         err = register_netdev(netdev);
5186         if (err) {
5187                 mlx5_core_err(mdev, "register_netdev failed, %d\n", err);
5188                 goto err_detach;
5189         }
5190
5191 #ifdef CONFIG_MLX5_CORE_EN_DCB
5192         mlx5e_dcbnl_init_app(priv);
5193 #endif
5194         return priv;
5195
5196 err_detach:
5197         mlx5e_detach(mdev, priv);
5198 err_destroy_netdev:
5199         mlx5e_destroy_netdev(priv);
5200         return NULL;
5201 }
5202
5203 static void mlx5e_remove(struct mlx5_core_dev *mdev, void *vpriv)
5204 {
5205         struct mlx5e_priv *priv;
5206
5207 #ifdef CONFIG_MLX5_ESWITCH
5208         if (MLX5_ESWITCH_MANAGER(mdev) && vpriv == mdev) {
5209                 mlx5e_rep_unregister_vport_reps(mdev);
5210                 return;
5211         }
5212 #endif
5213         priv = vpriv;
5214 #ifdef CONFIG_MLX5_CORE_EN_DCB
5215         mlx5e_dcbnl_delete_app(priv);
5216 #endif
5217         unregister_netdev(priv->netdev);
5218         mlx5e_detach(mdev, vpriv);
5219         mlx5e_destroy_netdev(priv);
5220 }
5221
5222 static struct mlx5_interface mlx5e_interface = {
5223         .add       = mlx5e_add,
5224         .remove    = mlx5e_remove,
5225         .attach    = mlx5e_attach,
5226         .detach    = mlx5e_detach,
5227         .protocol  = MLX5_INTERFACE_PROTOCOL_ETH,
5228 };
5229
5230 void mlx5e_init(void)
5231 {
5232         mlx5e_ipsec_build_inverse_table();
5233         mlx5e_build_ptys2ethtool_map();
5234         mlx5_register_interface(&mlx5e_interface);
5235 }
5236
5237 void mlx5e_cleanup(void)
5238 {
5239         mlx5_unregister_interface(&mlx5e_interface);
5240 }