2 * Copyright (c) 2015-2016, Mellanox Technologies. All rights reserved.
4 * This software is available to you under a choice of one of two
5 * licenses. You may choose to be licensed under the terms of the GNU
6 * General Public License (GPL) Version 2, available from the file
7 * COPYING in the main directory of this source tree, or the
8 * OpenIB.org BSD license below:
10 * Redistribution and use in source and binary forms, with or
11 * without modification, are permitted provided that the following
14 * - Redistributions of source code must retain the above
15 * copyright notice, this list of conditions and the following
18 * - Redistributions in binary form must reproduce the above
19 * copyright notice, this list of conditions and the following
20 * disclaimer in the documentation and/or other materials
21 * provided with the distribution.
23 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
24 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
25 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
26 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
27 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
28 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
29 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
33 #include <net/tc_act/tc_gact.h>
34 #include <linux/mlx5/fs.h>
35 #include <net/vxlan.h>
36 #include <net/geneve.h>
37 #include <linux/bpf.h>
38 #include <linux/debugfs.h>
39 #include <linux/if_bridge.h>
40 #include <linux/filter.h>
41 #include <net/page_pool/types.h>
42 #include <net/pkt_sched.h>
43 #include <net/xdp_sock_drv.h>
49 #include "en_accel/ipsec.h"
50 #include "en_accel/macsec.h"
51 #include "en_accel/en_accel.h"
52 #include "en_accel/ktls.h"
53 #include "lib/vxlan.h"
54 #include "lib/clock.h"
58 #include "en/monitor_stats.h"
59 #include "en/health.h"
60 #include "en/params.h"
61 #include "en/xsk/pool.h"
62 #include "en/xsk/setup.h"
63 #include "en/xsk/rx.h"
64 #include "en/xsk/tx.h"
65 #include "en/hv_vhca_stats.h"
66 #include "en/devlink.h"
72 #include "lib/devcom.h"
74 bool mlx5e_check_fragmented_striding_rq_cap(struct mlx5_core_dev *mdev, u8 page_shift,
75 enum mlx5e_mpwrq_umr_mode umr_mode)
77 u16 umr_wqebbs, max_wqebbs;
80 striding_rq_umr = MLX5_CAP_GEN(mdev, striding_rq) && MLX5_CAP_GEN(mdev, umr_ptr_rlky) &&
81 MLX5_CAP_ETH(mdev, reg_umr_sq);
85 umr_wqebbs = mlx5e_mpwrq_umr_wqebbs(mdev, page_shift, umr_mode);
86 max_wqebbs = mlx5e_get_max_sq_aligned_wqebbs(mdev);
87 /* Sanity check; should never happen, because mlx5e_mpwrq_umr_wqebbs is
88 * calculated from mlx5e_get_max_sq_aligned_wqebbs.
90 if (WARN_ON(umr_wqebbs > max_wqebbs))
96 void mlx5e_update_carrier(struct mlx5e_priv *priv)
98 struct mlx5_core_dev *mdev = priv->mdev;
102 port_state = mlx5_query_vport_state(mdev,
103 MLX5_VPORT_STATE_OP_MOD_VNIC_VPORT,
106 up = port_state == VPORT_STATE_UP;
107 if (up == netif_carrier_ok(priv->netdev))
108 netif_carrier_event(priv->netdev);
110 netdev_info(priv->netdev, "Link up\n");
111 netif_carrier_on(priv->netdev);
113 netdev_info(priv->netdev, "Link down\n");
114 netif_carrier_off(priv->netdev);
118 static void mlx5e_update_carrier_work(struct work_struct *work)
120 struct mlx5e_priv *priv = container_of(work, struct mlx5e_priv,
121 update_carrier_work);
123 mutex_lock(&priv->state_lock);
124 if (test_bit(MLX5E_STATE_OPENED, &priv->state))
125 if (priv->profile->update_carrier)
126 priv->profile->update_carrier(priv);
127 mutex_unlock(&priv->state_lock);
130 static void mlx5e_update_stats_work(struct work_struct *work)
132 struct mlx5e_priv *priv = container_of(work, struct mlx5e_priv,
135 mutex_lock(&priv->state_lock);
136 priv->profile->update_stats(priv);
137 mutex_unlock(&priv->state_lock);
140 void mlx5e_queue_update_stats(struct mlx5e_priv *priv)
142 if (!priv->profile->update_stats)
145 if (unlikely(test_bit(MLX5E_STATE_DESTROYING, &priv->state)))
148 queue_work(priv->wq, &priv->update_stats_work);
151 static int async_event(struct notifier_block *nb, unsigned long event, void *data)
153 struct mlx5e_priv *priv = container_of(nb, struct mlx5e_priv, events_nb);
154 struct mlx5_eqe *eqe = data;
156 if (event != MLX5_EVENT_TYPE_PORT_CHANGE)
159 switch (eqe->sub_type) {
160 case MLX5_PORT_CHANGE_SUBTYPE_DOWN:
161 case MLX5_PORT_CHANGE_SUBTYPE_ACTIVE:
162 queue_work(priv->wq, &priv->update_carrier_work);
171 static void mlx5e_enable_async_events(struct mlx5e_priv *priv)
173 priv->events_nb.notifier_call = async_event;
174 mlx5_notifier_register(priv->mdev, &priv->events_nb);
177 static void mlx5e_disable_async_events(struct mlx5e_priv *priv)
179 mlx5_notifier_unregister(priv->mdev, &priv->events_nb);
182 static int mlx5e_devcom_event_mpv(int event, void *my_data, void *event_data)
184 struct mlx5e_priv *slave_priv = my_data;
187 case MPV_DEVCOM_MASTER_UP:
188 mlx5_devcom_comp_set_ready(slave_priv->devcom, true);
190 case MPV_DEVCOM_MASTER_DOWN:
191 /* no need for comp set ready false since we unregister after
192 * and it hurts cleanup flow.
195 case MPV_DEVCOM_IPSEC_MASTER_UP:
196 case MPV_DEVCOM_IPSEC_MASTER_DOWN:
197 mlx5e_ipsec_handle_mpv_event(event, my_data, event_data);
204 static int mlx5e_devcom_init_mpv(struct mlx5e_priv *priv, u64 *data)
206 priv->devcom = mlx5_devcom_register_component(priv->mdev->priv.devc,
209 mlx5e_devcom_event_mpv,
211 if (IS_ERR_OR_NULL(priv->devcom))
214 if (mlx5_core_is_mp_master(priv->mdev)) {
215 mlx5_devcom_send_event(priv->devcom, MPV_DEVCOM_MASTER_UP,
216 MPV_DEVCOM_MASTER_UP, priv);
217 mlx5e_ipsec_send_event(priv, MPV_DEVCOM_IPSEC_MASTER_UP);
223 static void mlx5e_devcom_cleanup_mpv(struct mlx5e_priv *priv)
225 if (IS_ERR_OR_NULL(priv->devcom))
228 if (mlx5_core_is_mp_master(priv->mdev)) {
229 mlx5_devcom_send_event(priv->devcom, MPV_DEVCOM_MASTER_DOWN,
230 MPV_DEVCOM_MASTER_DOWN, priv);
231 mlx5e_ipsec_send_event(priv, MPV_DEVCOM_IPSEC_MASTER_DOWN);
234 mlx5_devcom_unregister_component(priv->devcom);
237 static int blocking_event(struct notifier_block *nb, unsigned long event, void *data)
239 struct mlx5e_priv *priv = container_of(nb, struct mlx5e_priv, blocking_events_nb);
240 struct mlx5_devlink_trap_event_ctx *trap_event_ctx = data;
244 case MLX5_DRIVER_EVENT_TYPE_TRAP:
245 err = mlx5e_handle_trap_event(priv, trap_event_ctx->trap);
247 trap_event_ctx->err = err;
251 case MLX5_DRIVER_EVENT_AFFILIATION_DONE:
252 if (mlx5e_devcom_init_mpv(priv, data))
255 case MLX5_DRIVER_EVENT_AFFILIATION_REMOVED:
256 mlx5e_devcom_cleanup_mpv(priv);
264 static void mlx5e_enable_blocking_events(struct mlx5e_priv *priv)
266 priv->blocking_events_nb.notifier_call = blocking_event;
267 mlx5_blocking_notifier_register(priv->mdev, &priv->blocking_events_nb);
270 static void mlx5e_disable_blocking_events(struct mlx5e_priv *priv)
272 mlx5_blocking_notifier_unregister(priv->mdev, &priv->blocking_events_nb);
275 static u16 mlx5e_mpwrq_umr_octowords(u32 entries, enum mlx5e_mpwrq_umr_mode umr_mode)
277 u8 umr_entry_size = mlx5e_mpwrq_umr_entry_size(umr_mode);
280 sz = ALIGN(entries * umr_entry_size, MLX5_UMR_FLEX_ALIGNMENT);
282 return sz / MLX5_OCTWORD;
285 static inline void mlx5e_build_umr_wqe(struct mlx5e_rq *rq,
286 struct mlx5e_icosq *sq,
287 struct mlx5e_umr_wqe *wqe)
289 struct mlx5_wqe_ctrl_seg *cseg = &wqe->ctrl;
290 struct mlx5_wqe_umr_ctrl_seg *ucseg = &wqe->uctrl;
294 ds_cnt = DIV_ROUND_UP(mlx5e_mpwrq_umr_wqe_sz(rq->mdev, rq->mpwqe.page_shift,
298 cseg->qpn_ds = cpu_to_be32((sq->sqn << MLX5_WQE_CTRL_QPN_SHIFT) |
300 cseg->umr_mkey = rq->mpwqe.umr_mkey_be;
302 ucseg->flags = MLX5_UMR_TRANSLATION_OFFSET_EN | MLX5_UMR_INLINE;
303 octowords = mlx5e_mpwrq_umr_octowords(rq->mpwqe.pages_per_wqe, rq->mpwqe.umr_mode);
304 ucseg->xlt_octowords = cpu_to_be16(octowords);
305 ucseg->mkey_mask = cpu_to_be64(MLX5_MKEY_MASK_FREE);
308 static int mlx5e_rq_shampo_hd_alloc(struct mlx5e_rq *rq, int node)
310 rq->mpwqe.shampo = kvzalloc_node(sizeof(*rq->mpwqe.shampo),
312 if (!rq->mpwqe.shampo)
317 static void mlx5e_rq_shampo_hd_free(struct mlx5e_rq *rq)
319 kvfree(rq->mpwqe.shampo);
322 static int mlx5e_rq_shampo_hd_info_alloc(struct mlx5e_rq *rq, int node)
324 struct mlx5e_shampo_hd *shampo = rq->mpwqe.shampo;
326 shampo->bitmap = bitmap_zalloc_node(shampo->hd_per_wq, GFP_KERNEL,
328 shampo->info = kvzalloc_node(array_size(shampo->hd_per_wq,
329 sizeof(*shampo->info)),
331 shampo->pages = kvzalloc_node(array_size(shampo->hd_per_wq,
332 sizeof(*shampo->pages)),
334 if (!shampo->bitmap || !shampo->info || !shampo->pages)
340 kvfree(shampo->info);
341 kvfree(shampo->bitmap);
342 kvfree(shampo->pages);
347 static void mlx5e_rq_shampo_hd_info_free(struct mlx5e_rq *rq)
349 kvfree(rq->mpwqe.shampo->bitmap);
350 kvfree(rq->mpwqe.shampo->info);
351 kvfree(rq->mpwqe.shampo->pages);
354 static int mlx5e_rq_alloc_mpwqe_info(struct mlx5e_rq *rq, int node)
356 int wq_sz = mlx5_wq_ll_get_size(&rq->mpwqe.wq);
359 alloc_size = array_size(wq_sz, struct_size(rq->mpwqe.info,
360 alloc_units.frag_pages,
361 rq->mpwqe.pages_per_wqe));
363 rq->mpwqe.info = kvzalloc_node(alloc_size, GFP_KERNEL, node);
367 /* For deferred page release (release right before alloc), make sure
368 * that on first round release is not called.
370 for (int i = 0; i < wq_sz; i++) {
371 struct mlx5e_mpw_info *wi = mlx5e_get_mpw_info(rq, i);
373 bitmap_fill(wi->skip_release_bitmap, rq->mpwqe.pages_per_wqe);
376 mlx5e_build_umr_wqe(rq, rq->icosq, &rq->mpwqe.umr_wqe);
382 static u8 mlx5e_mpwrq_access_mode(enum mlx5e_mpwrq_umr_mode umr_mode)
385 case MLX5E_MPWRQ_UMR_MODE_ALIGNED:
386 return MLX5_MKC_ACCESS_MODE_MTT;
387 case MLX5E_MPWRQ_UMR_MODE_UNALIGNED:
388 return MLX5_MKC_ACCESS_MODE_KSM;
389 case MLX5E_MPWRQ_UMR_MODE_OVERSIZED:
390 return MLX5_MKC_ACCESS_MODE_KLMS;
391 case MLX5E_MPWRQ_UMR_MODE_TRIPLE:
392 return MLX5_MKC_ACCESS_MODE_KSM;
394 WARN_ONCE(1, "MPWRQ UMR mode %d is not known\n", umr_mode);
398 static int mlx5e_create_umr_mkey(struct mlx5_core_dev *mdev,
399 u32 npages, u8 page_shift, u32 *umr_mkey,
400 dma_addr_t filler_addr,
401 enum mlx5e_mpwrq_umr_mode umr_mode,
404 struct mlx5_mtt *mtt;
405 struct mlx5_ksm *ksm;
406 struct mlx5_klm *klm;
414 if ((umr_mode == MLX5E_MPWRQ_UMR_MODE_UNALIGNED ||
415 umr_mode == MLX5E_MPWRQ_UMR_MODE_TRIPLE) &&
416 !MLX5_CAP_GEN(mdev, fixed_buffer_size)) {
417 mlx5_core_warn(mdev, "Unaligned AF_XDP requires fixed_buffer_size capability\n");
421 octwords = mlx5e_mpwrq_umr_octowords(npages, umr_mode);
423 inlen = MLX5_FLEXIBLE_INLEN(mdev, MLX5_ST_SZ_BYTES(create_mkey_in),
424 MLX5_OCTWORD, octwords);
428 in = kvzalloc(inlen, GFP_KERNEL);
432 mkc = MLX5_ADDR_OF(create_mkey_in, in, memory_key_mkey_entry);
434 MLX5_SET(mkc, mkc, free, 1);
435 MLX5_SET(mkc, mkc, umr_en, 1);
436 MLX5_SET(mkc, mkc, lw, 1);
437 MLX5_SET(mkc, mkc, lr, 1);
438 MLX5_SET(mkc, mkc, access_mode_1_0, mlx5e_mpwrq_access_mode(umr_mode));
439 mlx5e_mkey_set_relaxed_ordering(mdev, mkc);
440 MLX5_SET(mkc, mkc, qpn, 0xffffff);
441 MLX5_SET(mkc, mkc, pd, mdev->mlx5e_res.hw_objs.pdn);
442 MLX5_SET64(mkc, mkc, len, npages << page_shift);
443 MLX5_SET(mkc, mkc, translations_octword_size, octwords);
444 if (umr_mode == MLX5E_MPWRQ_UMR_MODE_TRIPLE)
445 MLX5_SET(mkc, mkc, log_page_size, page_shift - 2);
446 else if (umr_mode != MLX5E_MPWRQ_UMR_MODE_OVERSIZED)
447 MLX5_SET(mkc, mkc, log_page_size, page_shift);
448 MLX5_SET(create_mkey_in, in, translations_octword_actual_size, octwords);
450 /* Initialize the mkey with all MTTs pointing to a default
451 * page (filler_addr). When the channels are activated, UMR
452 * WQEs will redirect the RX WQEs to the actual memory from
453 * the RQ's pool, while the gaps (wqe_overflow) remain mapped
454 * to the default page.
457 case MLX5E_MPWRQ_UMR_MODE_OVERSIZED:
458 klm = MLX5_ADDR_OF(create_mkey_in, in, klm_pas_mtt);
459 for (i = 0; i < npages; i++) {
460 klm[i << 1] = (struct mlx5_klm) {
461 .va = cpu_to_be64(filler_addr),
462 .bcount = cpu_to_be32(xsk_chunk_size),
463 .key = cpu_to_be32(mdev->mlx5e_res.hw_objs.mkey),
465 klm[(i << 1) + 1] = (struct mlx5_klm) {
466 .va = cpu_to_be64(filler_addr),
467 .bcount = cpu_to_be32((1 << page_shift) - xsk_chunk_size),
468 .key = cpu_to_be32(mdev->mlx5e_res.hw_objs.mkey),
472 case MLX5E_MPWRQ_UMR_MODE_UNALIGNED:
473 ksm = MLX5_ADDR_OF(create_mkey_in, in, klm_pas_mtt);
474 for (i = 0; i < npages; i++)
475 ksm[i] = (struct mlx5_ksm) {
476 .key = cpu_to_be32(mdev->mlx5e_res.hw_objs.mkey),
477 .va = cpu_to_be64(filler_addr),
480 case MLX5E_MPWRQ_UMR_MODE_ALIGNED:
481 mtt = MLX5_ADDR_OF(create_mkey_in, in, klm_pas_mtt);
482 for (i = 0; i < npages; i++)
483 mtt[i] = (struct mlx5_mtt) {
484 .ptag = cpu_to_be64(filler_addr),
487 case MLX5E_MPWRQ_UMR_MODE_TRIPLE:
488 ksm = MLX5_ADDR_OF(create_mkey_in, in, klm_pas_mtt);
489 for (i = 0; i < npages * 4; i++) {
490 ksm[i] = (struct mlx5_ksm) {
491 .key = cpu_to_be32(mdev->mlx5e_res.hw_objs.mkey),
492 .va = cpu_to_be64(filler_addr),
498 err = mlx5_core_create_mkey(mdev, umr_mkey, in, inlen);
504 static int mlx5e_create_umr_klm_mkey(struct mlx5_core_dev *mdev,
513 inlen = MLX5_ST_SZ_BYTES(create_mkey_in);
515 in = kvzalloc(inlen, GFP_KERNEL);
519 mkc = MLX5_ADDR_OF(create_mkey_in, in, memory_key_mkey_entry);
521 MLX5_SET(mkc, mkc, free, 1);
522 MLX5_SET(mkc, mkc, umr_en, 1);
523 MLX5_SET(mkc, mkc, lw, 1);
524 MLX5_SET(mkc, mkc, lr, 1);
525 MLX5_SET(mkc, mkc, access_mode_1_0, MLX5_MKC_ACCESS_MODE_KLMS);
526 mlx5e_mkey_set_relaxed_ordering(mdev, mkc);
527 MLX5_SET(mkc, mkc, qpn, 0xffffff);
528 MLX5_SET(mkc, mkc, pd, mdev->mlx5e_res.hw_objs.pdn);
529 MLX5_SET(mkc, mkc, translations_octword_size, nentries);
530 MLX5_SET(mkc, mkc, length64, 1);
531 err = mlx5_core_create_mkey(mdev, umr_mkey, in, inlen);
537 static int mlx5e_create_rq_umr_mkey(struct mlx5_core_dev *mdev, struct mlx5e_rq *rq)
539 u32 xsk_chunk_size = rq->xsk_pool ? rq->xsk_pool->chunk_size : 0;
540 u32 wq_size = mlx5_wq_ll_get_size(&rq->mpwqe.wq);
541 u32 num_entries, max_num_entries;
545 max_num_entries = mlx5e_mpwrq_max_num_entries(mdev, rq->mpwqe.umr_mode);
547 /* Shouldn't overflow, the result is at most MLX5E_MAX_RQ_NUM_MTTS. */
548 if (WARN_ON_ONCE(check_mul_overflow(wq_size, (u32)rq->mpwqe.mtts_per_wqe,
550 num_entries > max_num_entries))
551 mlx5_core_err(mdev, "%s: multiplication overflow: %u * %u > %u\n",
552 __func__, wq_size, rq->mpwqe.mtts_per_wqe,
555 err = mlx5e_create_umr_mkey(mdev, num_entries, rq->mpwqe.page_shift,
556 &umr_mkey, rq->wqe_overflow.addr,
557 rq->mpwqe.umr_mode, xsk_chunk_size);
558 rq->mpwqe.umr_mkey_be = cpu_to_be32(umr_mkey);
562 static int mlx5e_create_rq_hd_umr_mkey(struct mlx5_core_dev *mdev,
565 u32 max_klm_size = BIT(MLX5_CAP_GEN(mdev, log_max_klm_list_size));
567 if (max_klm_size < rq->mpwqe.shampo->hd_per_wq) {
568 mlx5_core_err(mdev, "max klm list size 0x%x is smaller than shampo header buffer list size 0x%x\n",
569 max_klm_size, rq->mpwqe.shampo->hd_per_wq);
572 return mlx5e_create_umr_klm_mkey(mdev, rq->mpwqe.shampo->hd_per_wq,
573 &rq->mpwqe.shampo->mkey);
576 static void mlx5e_init_frags_partition(struct mlx5e_rq *rq)
578 struct mlx5e_wqe_frag_info next_frag = {};
579 struct mlx5e_wqe_frag_info *prev = NULL;
582 WARN_ON(rq->xsk_pool);
584 next_frag.frag_page = &rq->wqe.alloc_units->frag_pages[0];
586 /* Skip first release due to deferred release. */
587 next_frag.flags = BIT(MLX5E_WQE_FRAG_SKIP_RELEASE);
589 for (i = 0; i < mlx5_wq_cyc_get_size(&rq->wqe.wq); i++) {
590 struct mlx5e_rq_frag_info *frag_info = &rq->wqe.info.arr[0];
591 struct mlx5e_wqe_frag_info *frag =
592 &rq->wqe.frags[i << rq->wqe.info.log_num_frags];
595 for (f = 0; f < rq->wqe.info.num_frags; f++, frag++) {
596 if (next_frag.offset + frag_info[f].frag_stride > PAGE_SIZE) {
597 /* Pages are assigned at runtime. */
598 next_frag.frag_page++;
599 next_frag.offset = 0;
601 prev->flags |= BIT(MLX5E_WQE_FRAG_LAST_IN_PAGE);
606 next_frag.offset += frag_info[f].frag_stride;
612 prev->flags |= BIT(MLX5E_WQE_FRAG_LAST_IN_PAGE);
615 static void mlx5e_init_xsk_buffs(struct mlx5e_rq *rq)
619 /* Assumptions used by XSK batched allocator. */
620 WARN_ON(rq->wqe.info.num_frags != 1);
621 WARN_ON(rq->wqe.info.log_num_frags != 0);
622 WARN_ON(rq->wqe.info.arr[0].frag_stride != PAGE_SIZE);
624 /* Considering the above assumptions a fragment maps to a single
627 for (i = 0; i < mlx5_wq_cyc_get_size(&rq->wqe.wq); i++) {
628 rq->wqe.frags[i].xskp = &rq->wqe.alloc_units->xsk_buffs[i];
630 /* Skip first release due to deferred release as WQES are
633 rq->wqe.frags[i].flags |= BIT(MLX5E_WQE_FRAG_SKIP_RELEASE);
637 static int mlx5e_init_wqe_alloc_info(struct mlx5e_rq *rq, int node)
639 int wq_sz = mlx5_wq_cyc_get_size(&rq->wqe.wq);
640 int len = wq_sz << rq->wqe.info.log_num_frags;
641 struct mlx5e_wqe_frag_info *frags;
642 union mlx5e_alloc_units *aus;
646 aus_sz = sizeof(*aus->xsk_buffs);
648 aus_sz = sizeof(*aus->frag_pages);
650 aus = kvzalloc_node(array_size(len, aus_sz), GFP_KERNEL, node);
654 frags = kvzalloc_node(array_size(len, sizeof(*frags)), GFP_KERNEL, node);
660 rq->wqe.alloc_units = aus;
661 rq->wqe.frags = frags;
664 mlx5e_init_xsk_buffs(rq);
666 mlx5e_init_frags_partition(rq);
671 static void mlx5e_free_wqe_alloc_info(struct mlx5e_rq *rq)
673 kvfree(rq->wqe.frags);
674 kvfree(rq->wqe.alloc_units);
677 static void mlx5e_rq_err_cqe_work(struct work_struct *recover_work)
679 struct mlx5e_rq *rq = container_of(recover_work, struct mlx5e_rq, recover_work);
681 mlx5e_reporter_rq_cqe_err(rq);
684 static int mlx5e_alloc_mpwqe_rq_drop_page(struct mlx5e_rq *rq)
686 rq->wqe_overflow.page = alloc_page(GFP_KERNEL);
687 if (!rq->wqe_overflow.page)
690 rq->wqe_overflow.addr = dma_map_page(rq->pdev, rq->wqe_overflow.page, 0,
691 PAGE_SIZE, rq->buff.map_dir);
692 if (dma_mapping_error(rq->pdev, rq->wqe_overflow.addr)) {
693 __free_page(rq->wqe_overflow.page);
699 static void mlx5e_free_mpwqe_rq_drop_page(struct mlx5e_rq *rq)
701 dma_unmap_page(rq->pdev, rq->wqe_overflow.addr, PAGE_SIZE,
703 __free_page(rq->wqe_overflow.page);
706 static int mlx5e_init_rxq_rq(struct mlx5e_channel *c, struct mlx5e_params *params,
707 u32 xdp_frag_size, struct mlx5e_rq *rq)
709 struct mlx5_core_dev *mdev = c->mdev;
712 rq->wq_type = params->rq_wq_type;
714 rq->netdev = c->netdev;
716 rq->tstamp = c->tstamp;
717 rq->clock = &mdev->clock;
718 rq->icosq = &c->icosq;
723 MLX5E_SW2HW_MTU(params, params->sw_mtu) - ETH_FCS_LEN * !params->scatter_fcs_en;
724 rq->xdpsq = &c->rq_xdpsq;
725 rq->stats = &c->priv->channel_stats[c->ix]->rq;
726 rq->ptp_cyc2time = mlx5_rq_ts_translator(mdev);
727 err = mlx5e_rq_set_handlers(rq, params, NULL);
731 return __xdp_rxq_info_reg(&rq->xdp_rxq, rq->netdev, rq->ix, c->napi.napi_id,
735 static int mlx5_rq_shampo_alloc(struct mlx5_core_dev *mdev,
736 struct mlx5e_params *params,
737 struct mlx5e_rq_param *rqp,
742 void *wqc = MLX5_ADDR_OF(rqc, rqp->rqc, wq);
746 if (!test_bit(MLX5E_RQ_STATE_SHAMPO, &rq->state))
748 err = mlx5e_rq_shampo_hd_alloc(rq, node);
751 rq->mpwqe.shampo->hd_per_wq =
752 mlx5e_shampo_hd_per_wq(mdev, params, rqp);
753 err = mlx5e_create_rq_hd_umr_mkey(mdev, rq);
756 err = mlx5e_rq_shampo_hd_info_alloc(rq, node);
758 goto err_shampo_info;
759 rq->hw_gro_data = kvzalloc_node(sizeof(*rq->hw_gro_data), GFP_KERNEL, node);
760 if (!rq->hw_gro_data) {
762 goto err_hw_gro_data;
764 rq->mpwqe.shampo->key =
765 cpu_to_be32(rq->mpwqe.shampo->mkey);
766 rq->mpwqe.shampo->hd_per_wqe =
767 mlx5e_shampo_hd_per_wqe(mdev, params, rqp);
768 wq_size = BIT(MLX5_GET(wq, wqc, log_wq_sz));
769 *pool_size += (rq->mpwqe.shampo->hd_per_wqe * wq_size) /
770 MLX5E_SHAMPO_WQ_HEADER_PER_PAGE;
774 mlx5e_rq_shampo_hd_info_free(rq);
776 mlx5_core_destroy_mkey(mdev, rq->mpwqe.shampo->mkey);
778 mlx5e_rq_shampo_hd_free(rq);
783 static void mlx5e_rq_free_shampo(struct mlx5e_rq *rq)
785 if (!test_bit(MLX5E_RQ_STATE_SHAMPO, &rq->state))
788 kvfree(rq->hw_gro_data);
789 mlx5e_rq_shampo_hd_info_free(rq);
790 mlx5_core_destroy_mkey(rq->mdev, rq->mpwqe.shampo->mkey);
791 mlx5e_rq_shampo_hd_free(rq);
794 static int mlx5e_alloc_rq(struct mlx5e_params *params,
795 struct mlx5e_xsk_param *xsk,
796 struct mlx5e_rq_param *rqp,
797 int node, struct mlx5e_rq *rq)
799 struct mlx5_core_dev *mdev = rq->mdev;
800 void *rqc = rqp->rqc;
801 void *rqc_wq = MLX5_ADDR_OF(rqc, rqc, wq);
807 rqp->wq.db_numa_node = node;
808 INIT_WORK(&rq->recover_work, mlx5e_rq_err_cqe_work);
810 if (params->xdp_prog)
811 bpf_prog_inc(params->xdp_prog);
812 RCU_INIT_POINTER(rq->xdp_prog, params->xdp_prog);
814 rq->buff.map_dir = params->xdp_prog ? DMA_BIDIRECTIONAL : DMA_FROM_DEVICE;
815 rq->buff.headroom = mlx5e_get_rq_headroom(mdev, params, xsk);
816 pool_size = 1 << params->log_rq_mtu_frames;
818 rq->mkey_be = cpu_to_be32(mdev->mlx5e_res.hw_objs.mkey);
820 switch (rq->wq_type) {
821 case MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ:
822 err = mlx5_wq_ll_create(mdev, &rqp->wq, rqc_wq, &rq->mpwqe.wq,
825 goto err_rq_xdp_prog;
827 err = mlx5e_alloc_mpwqe_rq_drop_page(rq);
829 goto err_rq_wq_destroy;
831 rq->mpwqe.wq.db = &rq->mpwqe.wq.db[MLX5_RCV_DBR];
833 wq_sz = mlx5_wq_ll_get_size(&rq->mpwqe.wq);
835 rq->mpwqe.page_shift = mlx5e_mpwrq_page_shift(mdev, xsk);
836 rq->mpwqe.umr_mode = mlx5e_mpwrq_umr_mode(mdev, xsk);
837 rq->mpwqe.pages_per_wqe =
838 mlx5e_mpwrq_pages_per_wqe(mdev, rq->mpwqe.page_shift,
840 rq->mpwqe.umr_wqebbs =
841 mlx5e_mpwrq_umr_wqebbs(mdev, rq->mpwqe.page_shift,
843 rq->mpwqe.mtts_per_wqe =
844 mlx5e_mpwrq_mtts_per_wqe(mdev, rq->mpwqe.page_shift,
847 pool_size = rq->mpwqe.pages_per_wqe <<
848 mlx5e_mpwqe_get_log_rq_size(mdev, params, xsk);
850 if (!mlx5e_rx_mpwqe_is_linear_skb(mdev, params, xsk) && params->xdp_prog)
851 pool_size *= 2; /* additional page per packet for the linear part */
853 rq->mpwqe.log_stride_sz = mlx5e_mpwqe_get_log_stride_size(mdev, params, xsk);
854 rq->mpwqe.num_strides =
855 BIT(mlx5e_mpwqe_get_log_num_strides(mdev, params, xsk));
856 rq->mpwqe.min_wqe_bulk = mlx5e_mpwqe_get_min_wqe_bulk(wq_sz);
858 rq->buff.frame0_sz = (1 << rq->mpwqe.log_stride_sz);
860 err = mlx5e_create_rq_umr_mkey(mdev, rq);
862 goto err_rq_drop_page;
864 err = mlx5e_rq_alloc_mpwqe_info(rq, node);
868 err = mlx5_rq_shampo_alloc(mdev, params, rqp, rq, &pool_size, node);
870 goto err_free_mpwqe_info;
873 default: /* MLX5_WQ_TYPE_CYCLIC */
874 err = mlx5_wq_cyc_create(mdev, &rqp->wq, rqc_wq, &rq->wqe.wq,
877 goto err_rq_xdp_prog;
879 rq->wqe.wq.db = &rq->wqe.wq.db[MLX5_RCV_DBR];
881 wq_sz = mlx5_wq_cyc_get_size(&rq->wqe.wq);
883 rq->wqe.info = rqp->frags_info;
884 rq->buff.frame0_sz = rq->wqe.info.arr[0].frag_stride;
886 err = mlx5e_init_wqe_alloc_info(rq, node);
888 goto err_rq_wq_destroy;
892 err = xdp_rxq_info_reg_mem_model(&rq->xdp_rxq,
893 MEM_TYPE_XSK_BUFF_POOL, NULL);
894 xsk_pool_set_rxq_info(rq->xsk_pool, &rq->xdp_rxq);
896 /* Create a page_pool and register it with rxq */
897 struct page_pool_params pp_params = { 0 };
900 pp_params.flags = PP_FLAG_DMA_MAP | PP_FLAG_DMA_SYNC_DEV;
901 pp_params.pool_size = pool_size;
902 pp_params.nid = node;
903 pp_params.dev = rq->pdev;
904 pp_params.napi = rq->cq.napi;
905 pp_params.netdev = rq->netdev;
906 pp_params.dma_dir = rq->buff.map_dir;
907 pp_params.max_len = PAGE_SIZE;
909 /* page_pool can be used even when there is no rq->xdp_prog,
910 * given page_pool does not handle DMA mapping there is no
911 * required state to clear. And page_pool gracefully handle
914 rq->page_pool = page_pool_create(&pp_params);
915 if (IS_ERR(rq->page_pool)) {
916 err = PTR_ERR(rq->page_pool);
917 rq->page_pool = NULL;
918 goto err_free_by_rq_type;
920 if (xdp_rxq_info_is_reg(&rq->xdp_rxq))
921 err = xdp_rxq_info_reg_mem_model(&rq->xdp_rxq,
922 MEM_TYPE_PAGE_POOL, rq->page_pool);
925 goto err_destroy_page_pool;
927 for (i = 0; i < wq_sz; i++) {
928 if (rq->wq_type == MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ) {
929 struct mlx5e_rx_wqe_ll *wqe =
930 mlx5_wq_ll_get_wqe(&rq->mpwqe.wq, i);
932 rq->mpwqe.num_strides << rq->mpwqe.log_stride_sz;
933 u64 dma_offset = mul_u32_u32(i, rq->mpwqe.mtts_per_wqe) <<
934 rq->mpwqe.page_shift;
935 u16 headroom = test_bit(MLX5E_RQ_STATE_SHAMPO, &rq->state) ?
936 0 : rq->buff.headroom;
938 wqe->data[0].addr = cpu_to_be64(dma_offset + headroom);
939 wqe->data[0].byte_count = cpu_to_be32(byte_count);
940 wqe->data[0].lkey = rq->mpwqe.umr_mkey_be;
942 struct mlx5e_rx_wqe_cyc *wqe =
943 mlx5_wq_cyc_get_wqe(&rq->wqe.wq, i);
946 for (f = 0; f < rq->wqe.info.num_frags; f++) {
947 u32 frag_size = rq->wqe.info.arr[f].frag_size |
948 MLX5_HW_START_PADDING;
950 wqe->data[f].byte_count = cpu_to_be32(frag_size);
951 wqe->data[f].lkey = rq->mkey_be;
953 /* check if num_frags is not a pow of two */
954 if (rq->wqe.info.num_frags < (1 << rq->wqe.info.log_num_frags)) {
955 wqe->data[f].byte_count = 0;
956 wqe->data[f].lkey = params->terminate_lkey_be;
957 wqe->data[f].addr = 0;
962 INIT_WORK(&rq->dim.work, mlx5e_rx_dim_work);
964 switch (params->rx_cq_moderation.cq_period_mode) {
965 case MLX5_CQ_PERIOD_MODE_START_FROM_CQE:
966 rq->dim.mode = DIM_CQ_PERIOD_MODE_START_FROM_CQE;
968 case MLX5_CQ_PERIOD_MODE_START_FROM_EQE:
970 rq->dim.mode = DIM_CQ_PERIOD_MODE_START_FROM_EQE;
975 err_destroy_page_pool:
976 page_pool_destroy(rq->page_pool);
978 switch (rq->wq_type) {
979 case MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ:
980 mlx5e_rq_free_shampo(rq);
982 kvfree(rq->mpwqe.info);
984 mlx5_core_destroy_mkey(mdev, be32_to_cpu(rq->mpwqe.umr_mkey_be));
986 mlx5e_free_mpwqe_rq_drop_page(rq);
988 default: /* MLX5_WQ_TYPE_CYCLIC */
989 mlx5e_free_wqe_alloc_info(rq);
992 mlx5_wq_destroy(&rq->wq_ctrl);
994 if (params->xdp_prog)
995 bpf_prog_put(params->xdp_prog);
1000 static void mlx5e_free_rq(struct mlx5e_rq *rq)
1002 struct bpf_prog *old_prog;
1004 if (xdp_rxq_info_is_reg(&rq->xdp_rxq)) {
1005 old_prog = rcu_dereference_protected(rq->xdp_prog,
1006 lockdep_is_held(&rq->priv->state_lock));
1008 bpf_prog_put(old_prog);
1011 switch (rq->wq_type) {
1012 case MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ:
1013 kvfree(rq->mpwqe.info);
1014 mlx5_core_destroy_mkey(rq->mdev, be32_to_cpu(rq->mpwqe.umr_mkey_be));
1015 mlx5e_free_mpwqe_rq_drop_page(rq);
1016 mlx5e_rq_free_shampo(rq);
1018 default: /* MLX5_WQ_TYPE_CYCLIC */
1019 mlx5e_free_wqe_alloc_info(rq);
1022 xdp_rxq_info_unreg(&rq->xdp_rxq);
1023 page_pool_destroy(rq->page_pool);
1024 mlx5_wq_destroy(&rq->wq_ctrl);
1027 int mlx5e_create_rq(struct mlx5e_rq *rq, struct mlx5e_rq_param *param)
1029 struct mlx5_core_dev *mdev = rq->mdev;
1037 inlen = MLX5_ST_SZ_BYTES(create_rq_in) +
1038 sizeof(u64) * rq->wq_ctrl.buf.npages;
1039 in = kvzalloc(inlen, GFP_KERNEL);
1043 ts_format = mlx5_is_real_time_rq(mdev) ?
1044 MLX5_TIMESTAMP_FORMAT_REAL_TIME :
1045 MLX5_TIMESTAMP_FORMAT_FREE_RUNNING;
1046 rqc = MLX5_ADDR_OF(create_rq_in, in, ctx);
1047 wq = MLX5_ADDR_OF(rqc, rqc, wq);
1049 memcpy(rqc, param->rqc, sizeof(param->rqc));
1051 MLX5_SET(rqc, rqc, cqn, rq->cq.mcq.cqn);
1052 MLX5_SET(rqc, rqc, state, MLX5_RQC_STATE_RST);
1053 MLX5_SET(rqc, rqc, ts_format, ts_format);
1054 MLX5_SET(wq, wq, log_wq_pg_sz, rq->wq_ctrl.buf.page_shift -
1055 MLX5_ADAPTER_PAGE_SHIFT);
1056 MLX5_SET64(wq, wq, dbr_addr, rq->wq_ctrl.db.dma);
1058 if (test_bit(MLX5E_RQ_STATE_SHAMPO, &rq->state)) {
1059 MLX5_SET(wq, wq, log_headers_buffer_entry_num,
1060 order_base_2(rq->mpwqe.shampo->hd_per_wq));
1061 MLX5_SET(wq, wq, headers_mkey, rq->mpwqe.shampo->mkey);
1064 mlx5_fill_page_frag_array(&rq->wq_ctrl.buf,
1065 (__be64 *)MLX5_ADDR_OF(wq, wq, pas));
1067 err = mlx5_core_create_rq(mdev, in, inlen, &rq->rqn);
1074 static int mlx5e_modify_rq_state(struct mlx5e_rq *rq, int curr_state, int next_state)
1076 struct mlx5_core_dev *mdev = rq->mdev;
1083 inlen = MLX5_ST_SZ_BYTES(modify_rq_in);
1084 in = kvzalloc(inlen, GFP_KERNEL);
1088 if (curr_state == MLX5_RQC_STATE_RST && next_state == MLX5_RQC_STATE_RDY)
1089 mlx5e_rqwq_reset(rq);
1091 rqc = MLX5_ADDR_OF(modify_rq_in, in, ctx);
1093 MLX5_SET(modify_rq_in, in, rq_state, curr_state);
1094 MLX5_SET(rqc, rqc, state, next_state);
1096 err = mlx5_core_modify_rq(mdev, rq->rqn, in);
1103 static void mlx5e_flush_rq_cq(struct mlx5e_rq *rq)
1105 struct mlx5_cqwq *cqwq = &rq->cq.wq;
1106 struct mlx5_cqe64 *cqe;
1108 if (test_bit(MLX5E_RQ_STATE_MINI_CQE_ENHANCED, &rq->state)) {
1109 while ((cqe = mlx5_cqwq_get_cqe_enahnced_comp(cqwq)))
1110 mlx5_cqwq_pop(cqwq);
1112 while ((cqe = mlx5_cqwq_get_cqe(cqwq)))
1113 mlx5_cqwq_pop(cqwq);
1116 mlx5_cqwq_update_db_record(cqwq);
1119 int mlx5e_flush_rq(struct mlx5e_rq *rq, int curr_state)
1121 struct net_device *dev = rq->netdev;
1124 err = mlx5e_modify_rq_state(rq, curr_state, MLX5_RQC_STATE_RST);
1126 netdev_err(dev, "Failed to move rq 0x%x to reset\n", rq->rqn);
1130 mlx5e_free_rx_descs(rq);
1131 mlx5e_flush_rq_cq(rq);
1133 err = mlx5e_modify_rq_state(rq, MLX5_RQC_STATE_RST, MLX5_RQC_STATE_RDY);
1135 netdev_err(dev, "Failed to move rq 0x%x to ready\n", rq->rqn);
1142 static int mlx5e_modify_rq_vsd(struct mlx5e_rq *rq, bool vsd)
1144 struct mlx5_core_dev *mdev = rq->mdev;
1150 inlen = MLX5_ST_SZ_BYTES(modify_rq_in);
1151 in = kvzalloc(inlen, GFP_KERNEL);
1155 rqc = MLX5_ADDR_OF(modify_rq_in, in, ctx);
1157 MLX5_SET(modify_rq_in, in, rq_state, MLX5_RQC_STATE_RDY);
1158 MLX5_SET64(modify_rq_in, in, modify_bitmask,
1159 MLX5_MODIFY_RQ_IN_MODIFY_BITMASK_VSD);
1160 MLX5_SET(rqc, rqc, vsd, vsd);
1161 MLX5_SET(rqc, rqc, state, MLX5_RQC_STATE_RDY);
1163 err = mlx5_core_modify_rq(mdev, rq->rqn, in);
1170 void mlx5e_destroy_rq(struct mlx5e_rq *rq)
1172 mlx5_core_destroy_rq(rq->mdev, rq->rqn);
1175 int mlx5e_wait_for_min_rx_wqes(struct mlx5e_rq *rq, int wait_time)
1177 unsigned long exp_time = jiffies + msecs_to_jiffies(wait_time);
1179 u16 min_wqes = mlx5_min_rx_wqes(rq->wq_type, mlx5e_rqwq_get_size(rq));
1182 if (mlx5e_rqwq_get_cur_sz(rq) >= min_wqes)
1186 } while (time_before(jiffies, exp_time));
1188 netdev_warn(rq->netdev, "Failed to get min RX wqes on Channel[%d] RQN[0x%x] wq cur_sz(%d) min_rx_wqes(%d)\n",
1189 rq->ix, rq->rqn, mlx5e_rqwq_get_cur_sz(rq), min_wqes);
1191 mlx5e_reporter_rx_timeout(rq);
1195 void mlx5e_free_rx_missing_descs(struct mlx5e_rq *rq)
1197 struct mlx5_wq_ll *wq;
1201 if (rq->wq_type != MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ)
1207 /* Release WQEs that are in missing state: they have been
1208 * popped from the list after completion but were not freed
1209 * due to deferred release.
1210 * Also free the linked-list reserved entry, hence the "+ 1".
1212 for (i = 0; i < mlx5_wq_ll_missing(wq) + 1; i++) {
1213 rq->dealloc_wqe(rq, head);
1214 head = mlx5_wq_ll_get_wqe_next_ix(wq, head);
1217 if (test_bit(MLX5E_RQ_STATE_SHAMPO, &rq->state)) {
1220 len = (rq->mpwqe.shampo->pi - rq->mpwqe.shampo->ci) &
1221 (rq->mpwqe.shampo->hd_per_wq - 1);
1222 mlx5e_shampo_dealloc_hd(rq, len, rq->mpwqe.shampo->ci, false);
1223 rq->mpwqe.shampo->pi = rq->mpwqe.shampo->ci;
1226 rq->mpwqe.actual_wq_head = wq->head;
1227 rq->mpwqe.umr_in_progress = 0;
1228 rq->mpwqe.umr_completed = 0;
1231 void mlx5e_free_rx_descs(struct mlx5e_rq *rq)
1236 if (rq->wq_type == MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ) {
1237 struct mlx5_wq_ll *wq = &rq->mpwqe.wq;
1239 mlx5e_free_rx_missing_descs(rq);
1241 while (!mlx5_wq_ll_is_empty(wq)) {
1242 struct mlx5e_rx_wqe_ll *wqe;
1244 wqe_ix_be = *wq->tail_next;
1245 wqe_ix = be16_to_cpu(wqe_ix_be);
1246 wqe = mlx5_wq_ll_get_wqe(wq, wqe_ix);
1247 rq->dealloc_wqe(rq, wqe_ix);
1248 mlx5_wq_ll_pop(wq, wqe_ix_be,
1249 &wqe->next.next_wqe_index);
1252 if (test_bit(MLX5E_RQ_STATE_SHAMPO, &rq->state))
1253 mlx5e_shampo_dealloc_hd(rq, rq->mpwqe.shampo->hd_per_wq,
1256 struct mlx5_wq_cyc *wq = &rq->wqe.wq;
1257 u16 missing = mlx5_wq_cyc_missing(wq);
1258 u16 head = mlx5_wq_cyc_get_head(wq);
1260 while (!mlx5_wq_cyc_is_empty(wq)) {
1261 wqe_ix = mlx5_wq_cyc_get_tail(wq);
1262 rq->dealloc_wqe(rq, wqe_ix);
1263 mlx5_wq_cyc_pop(wq);
1265 /* Missing slots might also contain unreleased pages due to
1269 wqe_ix = mlx5_wq_cyc_ctr2ix(wq, head++);
1270 rq->dealloc_wqe(rq, wqe_ix);
1276 int mlx5e_open_rq(struct mlx5e_params *params, struct mlx5e_rq_param *param,
1277 struct mlx5e_xsk_param *xsk, int node,
1278 struct mlx5e_rq *rq)
1280 struct mlx5_core_dev *mdev = rq->mdev;
1283 if (params->packet_merge.type == MLX5E_PACKET_MERGE_SHAMPO)
1284 __set_bit(MLX5E_RQ_STATE_SHAMPO, &rq->state);
1286 err = mlx5e_alloc_rq(params, xsk, param, node, rq);
1290 err = mlx5e_create_rq(rq, param);
1294 err = mlx5e_modify_rq_state(rq, MLX5_RQC_STATE_RST, MLX5_RQC_STATE_RDY);
1296 goto err_destroy_rq;
1298 if (MLX5_CAP_ETH(mdev, cqe_checksum_full))
1299 __set_bit(MLX5E_RQ_STATE_CSUM_FULL, &rq->state);
1301 if (params->rx_dim_enabled)
1302 __set_bit(MLX5E_RQ_STATE_DIM, &rq->state);
1304 /* We disable csum_complete when XDP is enabled since
1305 * XDP programs might manipulate packets which will render
1306 * skb->checksum incorrect.
1308 if (MLX5E_GET_PFLAG(params, MLX5E_PFLAG_RX_NO_CSUM_COMPLETE) || params->xdp_prog)
1309 __set_bit(MLX5E_RQ_STATE_NO_CSUM_COMPLETE, &rq->state);
1311 /* For CQE compression on striding RQ, use stride index provided by
1312 * HW if capability is supported.
1314 if (MLX5E_GET_PFLAG(params, MLX5E_PFLAG_RX_STRIDING_RQ) &&
1315 MLX5_CAP_GEN(mdev, mini_cqe_resp_stride_index))
1316 __set_bit(MLX5E_RQ_STATE_MINI_CQE_HW_STRIDX, &rq->state);
1318 /* For enhanced CQE compression packet processing. decompress
1319 * session according to the enhanced layout.
1321 if (MLX5E_GET_PFLAG(params, MLX5E_PFLAG_RX_CQE_COMPRESS) &&
1322 MLX5_CAP_GEN(mdev, enhanced_cqe_compression))
1323 __set_bit(MLX5E_RQ_STATE_MINI_CQE_ENHANCED, &rq->state);
1328 mlx5e_destroy_rq(rq);
1335 void mlx5e_activate_rq(struct mlx5e_rq *rq)
1337 set_bit(MLX5E_RQ_STATE_ENABLED, &rq->state);
1340 void mlx5e_deactivate_rq(struct mlx5e_rq *rq)
1342 clear_bit(MLX5E_RQ_STATE_ENABLED, &rq->state);
1343 synchronize_net(); /* Sync with NAPI to prevent mlx5e_post_rx_wqes. */
1346 void mlx5e_close_rq(struct mlx5e_rq *rq)
1348 cancel_work_sync(&rq->dim.work);
1349 cancel_work_sync(&rq->recover_work);
1350 mlx5e_destroy_rq(rq);
1351 mlx5e_free_rx_descs(rq);
1355 u32 mlx5e_profile_get_tisn(struct mlx5_core_dev *mdev,
1356 struct mlx5e_priv *priv,
1357 const struct mlx5e_profile *profile,
1360 if (profile->get_tisn)
1361 return profile->get_tisn(mdev, priv, lag_port, tc);
1363 return mdev->mlx5e_res.hw_objs.tisn[lag_port][tc];
1366 static void mlx5e_free_xdpsq_db(struct mlx5e_xdpsq *sq)
1368 kvfree(sq->db.xdpi_fifo.xi);
1369 kvfree(sq->db.wqe_info);
1372 static int mlx5e_alloc_xdpsq_fifo(struct mlx5e_xdpsq *sq, int numa)
1374 struct mlx5e_xdp_info_fifo *xdpi_fifo = &sq->db.xdpi_fifo;
1375 int wq_sz = mlx5_wq_cyc_get_size(&sq->wq);
1379 /* upper bound for maximum num of entries of all xmit_modes. */
1380 entries = roundup_pow_of_two(wq_sz * MLX5_SEND_WQEBB_NUM_DS *
1381 MLX5E_XDP_FIFO_ENTRIES2DS_MAX_RATIO);
1383 size = array_size(sizeof(*xdpi_fifo->xi), entries);
1384 xdpi_fifo->xi = kvzalloc_node(size, GFP_KERNEL, numa);
1388 xdpi_fifo->pc = &sq->xdpi_fifo_pc;
1389 xdpi_fifo->cc = &sq->xdpi_fifo_cc;
1390 xdpi_fifo->mask = entries - 1;
1395 static int mlx5e_alloc_xdpsq_db(struct mlx5e_xdpsq *sq, int numa)
1397 int wq_sz = mlx5_wq_cyc_get_size(&sq->wq);
1401 size = array_size(sizeof(*sq->db.wqe_info), wq_sz);
1402 sq->db.wqe_info = kvzalloc_node(size, GFP_KERNEL, numa);
1403 if (!sq->db.wqe_info)
1406 err = mlx5e_alloc_xdpsq_fifo(sq, numa);
1408 mlx5e_free_xdpsq_db(sq);
1415 static int mlx5e_alloc_xdpsq(struct mlx5e_channel *c,
1416 struct mlx5e_params *params,
1417 struct xsk_buff_pool *xsk_pool,
1418 struct mlx5e_sq_param *param,
1419 struct mlx5e_xdpsq *sq,
1422 void *sqc_wq = MLX5_ADDR_OF(sqc, param->sqc, wq);
1423 struct mlx5_core_dev *mdev = c->mdev;
1424 struct mlx5_wq_cyc *wq = &sq->wq;
1428 sq->mkey_be = c->mkey_be;
1430 sq->uar_map = mdev->mlx5e_res.hw_objs.bfreg.map;
1431 sq->min_inline_mode = params->tx_min_inline_mode;
1432 sq->hw_mtu = MLX5E_SW2HW_MTU(params, params->sw_mtu) - ETH_FCS_LEN;
1433 sq->xsk_pool = xsk_pool;
1435 sq->stats = sq->xsk_pool ?
1436 &c->priv->channel_stats[c->ix]->xsksq :
1438 &c->priv->channel_stats[c->ix]->xdpsq :
1439 &c->priv->channel_stats[c->ix]->rq_xdpsq;
1440 sq->stop_room = param->is_mpw ? mlx5e_stop_room_for_mpwqe(mdev) :
1441 mlx5e_stop_room_for_max_wqe(mdev);
1442 sq->max_sq_mpw_wqebbs = mlx5e_get_max_sq_aligned_wqebbs(mdev);
1444 param->wq.db_numa_node = cpu_to_node(c->cpu);
1445 err = mlx5_wq_cyc_create(mdev, ¶m->wq, sqc_wq, wq, &sq->wq_ctrl);
1448 wq->db = &wq->db[MLX5_SND_DBR];
1450 err = mlx5e_alloc_xdpsq_db(sq, cpu_to_node(c->cpu));
1452 goto err_sq_wq_destroy;
1457 mlx5_wq_destroy(&sq->wq_ctrl);
1462 static void mlx5e_free_xdpsq(struct mlx5e_xdpsq *sq)
1464 mlx5e_free_xdpsq_db(sq);
1465 mlx5_wq_destroy(&sq->wq_ctrl);
1468 static void mlx5e_free_icosq_db(struct mlx5e_icosq *sq)
1470 kvfree(sq->db.wqe_info);
1473 static int mlx5e_alloc_icosq_db(struct mlx5e_icosq *sq, int numa)
1475 int wq_sz = mlx5_wq_cyc_get_size(&sq->wq);
1478 size = array_size(wq_sz, sizeof(*sq->db.wqe_info));
1479 sq->db.wqe_info = kvzalloc_node(size, GFP_KERNEL, numa);
1480 if (!sq->db.wqe_info)
1486 static void mlx5e_icosq_err_cqe_work(struct work_struct *recover_work)
1488 struct mlx5e_icosq *sq = container_of(recover_work, struct mlx5e_icosq,
1491 mlx5e_reporter_icosq_cqe_err(sq);
1494 static void mlx5e_async_icosq_err_cqe_work(struct work_struct *recover_work)
1496 struct mlx5e_icosq *sq = container_of(recover_work, struct mlx5e_icosq,
1499 /* Not implemented yet. */
1501 netdev_warn(sq->channel->netdev, "async_icosq recovery is not implemented\n");
1504 static int mlx5e_alloc_icosq(struct mlx5e_channel *c,
1505 struct mlx5e_sq_param *param,
1506 struct mlx5e_icosq *sq,
1507 work_func_t recover_work_func)
1509 void *sqc_wq = MLX5_ADDR_OF(sqc, param->sqc, wq);
1510 struct mlx5_core_dev *mdev = c->mdev;
1511 struct mlx5_wq_cyc *wq = &sq->wq;
1515 sq->uar_map = mdev->mlx5e_res.hw_objs.bfreg.map;
1516 sq->reserved_room = param->stop_room;
1518 param->wq.db_numa_node = cpu_to_node(c->cpu);
1519 err = mlx5_wq_cyc_create(mdev, ¶m->wq, sqc_wq, wq, &sq->wq_ctrl);
1522 wq->db = &wq->db[MLX5_SND_DBR];
1524 err = mlx5e_alloc_icosq_db(sq, cpu_to_node(c->cpu));
1526 goto err_sq_wq_destroy;
1528 INIT_WORK(&sq->recover_work, recover_work_func);
1533 mlx5_wq_destroy(&sq->wq_ctrl);
1538 static void mlx5e_free_icosq(struct mlx5e_icosq *sq)
1540 mlx5e_free_icosq_db(sq);
1541 mlx5_wq_destroy(&sq->wq_ctrl);
1544 void mlx5e_free_txqsq_db(struct mlx5e_txqsq *sq)
1546 kvfree(sq->db.wqe_info);
1547 kvfree(sq->db.skb_fifo.fifo);
1548 kvfree(sq->db.dma_fifo);
1551 int mlx5e_alloc_txqsq_db(struct mlx5e_txqsq *sq, int numa)
1553 int wq_sz = mlx5_wq_cyc_get_size(&sq->wq);
1554 int df_sz = wq_sz * MLX5_SEND_WQEBB_NUM_DS;
1556 sq->db.dma_fifo = kvzalloc_node(array_size(df_sz,
1557 sizeof(*sq->db.dma_fifo)),
1559 sq->db.skb_fifo.fifo = kvzalloc_node(array_size(df_sz,
1560 sizeof(*sq->db.skb_fifo.fifo)),
1562 sq->db.wqe_info = kvzalloc_node(array_size(wq_sz,
1563 sizeof(*sq->db.wqe_info)),
1565 if (!sq->db.dma_fifo || !sq->db.skb_fifo.fifo || !sq->db.wqe_info) {
1566 mlx5e_free_txqsq_db(sq);
1570 sq->dma_fifo_mask = df_sz - 1;
1572 sq->db.skb_fifo.pc = &sq->skb_fifo_pc;
1573 sq->db.skb_fifo.cc = &sq->skb_fifo_cc;
1574 sq->db.skb_fifo.mask = df_sz - 1;
1579 static int mlx5e_alloc_txqsq(struct mlx5e_channel *c,
1581 struct mlx5e_params *params,
1582 struct mlx5e_sq_param *param,
1583 struct mlx5e_txqsq *sq,
1586 void *sqc_wq = MLX5_ADDR_OF(sqc, param->sqc, wq);
1587 struct mlx5_core_dev *mdev = c->mdev;
1588 struct mlx5_wq_cyc *wq = &sq->wq;
1592 sq->clock = &mdev->clock;
1593 sq->mkey_be = c->mkey_be;
1594 sq->netdev = c->netdev;
1599 sq->txq_ix = txq_ix;
1600 sq->uar_map = mdev->mlx5e_res.hw_objs.bfreg.map;
1601 sq->min_inline_mode = params->tx_min_inline_mode;
1602 sq->hw_mtu = MLX5E_SW2HW_MTU(params, params->sw_mtu);
1603 sq->max_sq_mpw_wqebbs = mlx5e_get_max_sq_aligned_wqebbs(mdev);
1604 INIT_WORK(&sq->recover_work, mlx5e_tx_err_cqe_work);
1605 if (!MLX5_CAP_ETH(mdev, wqe_vlan_insert))
1606 set_bit(MLX5E_SQ_STATE_VLAN_NEED_L2_INLINE, &sq->state);
1607 if (mlx5_ipsec_device_caps(c->priv->mdev))
1608 set_bit(MLX5E_SQ_STATE_IPSEC, &sq->state);
1610 set_bit(MLX5E_SQ_STATE_MPWQE, &sq->state);
1611 sq->stop_room = param->stop_room;
1612 sq->ptp_cyc2time = mlx5_sq_ts_translator(mdev);
1614 param->wq.db_numa_node = cpu_to_node(c->cpu);
1615 err = mlx5_wq_cyc_create(mdev, ¶m->wq, sqc_wq, wq, &sq->wq_ctrl);
1618 wq->db = &wq->db[MLX5_SND_DBR];
1620 err = mlx5e_alloc_txqsq_db(sq, cpu_to_node(c->cpu));
1622 goto err_sq_wq_destroy;
1624 INIT_WORK(&sq->dim.work, mlx5e_tx_dim_work);
1625 sq->dim.mode = params->tx_cq_moderation.cq_period_mode;
1630 mlx5_wq_destroy(&sq->wq_ctrl);
1635 void mlx5e_free_txqsq(struct mlx5e_txqsq *sq)
1637 mlx5e_free_txqsq_db(sq);
1638 mlx5_wq_destroy(&sq->wq_ctrl);
1641 static int mlx5e_create_sq(struct mlx5_core_dev *mdev,
1642 struct mlx5e_sq_param *param,
1643 struct mlx5e_create_sq_param *csp,
1653 inlen = MLX5_ST_SZ_BYTES(create_sq_in) +
1654 sizeof(u64) * csp->wq_ctrl->buf.npages;
1655 in = kvzalloc(inlen, GFP_KERNEL);
1659 ts_format = mlx5_is_real_time_sq(mdev) ?
1660 MLX5_TIMESTAMP_FORMAT_REAL_TIME :
1661 MLX5_TIMESTAMP_FORMAT_FREE_RUNNING;
1662 sqc = MLX5_ADDR_OF(create_sq_in, in, ctx);
1663 wq = MLX5_ADDR_OF(sqc, sqc, wq);
1665 memcpy(sqc, param->sqc, sizeof(param->sqc));
1666 MLX5_SET(sqc, sqc, tis_lst_sz, csp->tis_lst_sz);
1667 MLX5_SET(sqc, sqc, tis_num_0, csp->tisn);
1668 MLX5_SET(sqc, sqc, cqn, csp->cqn);
1669 MLX5_SET(sqc, sqc, ts_cqe_to_dest_cqn, csp->ts_cqe_to_dest_cqn);
1670 MLX5_SET(sqc, sqc, ts_format, ts_format);
1673 if (MLX5_CAP_ETH(mdev, wqe_inline_mode) == MLX5_CAP_INLINE_MODE_VPORT_CONTEXT)
1674 MLX5_SET(sqc, sqc, min_wqe_inline_mode, csp->min_inline_mode);
1676 MLX5_SET(sqc, sqc, state, MLX5_SQC_STATE_RST);
1677 MLX5_SET(sqc, sqc, flush_in_error_en, 1);
1679 MLX5_SET(wq, wq, wq_type, MLX5_WQ_TYPE_CYCLIC);
1680 MLX5_SET(wq, wq, uar_page, mdev->mlx5e_res.hw_objs.bfreg.index);
1681 MLX5_SET(wq, wq, log_wq_pg_sz, csp->wq_ctrl->buf.page_shift -
1682 MLX5_ADAPTER_PAGE_SHIFT);
1683 MLX5_SET64(wq, wq, dbr_addr, csp->wq_ctrl->db.dma);
1685 mlx5_fill_page_frag_array(&csp->wq_ctrl->buf,
1686 (__be64 *)MLX5_ADDR_OF(wq, wq, pas));
1688 err = mlx5_core_create_sq(mdev, in, inlen, sqn);
1695 int mlx5e_modify_sq(struct mlx5_core_dev *mdev, u32 sqn,
1696 struct mlx5e_modify_sq_param *p)
1704 inlen = MLX5_ST_SZ_BYTES(modify_sq_in);
1705 in = kvzalloc(inlen, GFP_KERNEL);
1709 sqc = MLX5_ADDR_OF(modify_sq_in, in, ctx);
1711 MLX5_SET(modify_sq_in, in, sq_state, p->curr_state);
1712 MLX5_SET(sqc, sqc, state, p->next_state);
1713 if (p->rl_update && p->next_state == MLX5_SQC_STATE_RDY) {
1715 MLX5_SET(sqc, sqc, packet_pacing_rate_limit_index, p->rl_index);
1717 if (p->qos_update && p->next_state == MLX5_SQC_STATE_RDY) {
1719 MLX5_SET(sqc, sqc, qos_queue_group_id, p->qos_queue_group_id);
1721 MLX5_SET64(modify_sq_in, in, modify_bitmask, bitmask);
1723 err = mlx5_core_modify_sq(mdev, sqn, in);
1730 static void mlx5e_destroy_sq(struct mlx5_core_dev *mdev, u32 sqn)
1732 mlx5_core_destroy_sq(mdev, sqn);
1735 int mlx5e_create_sq_rdy(struct mlx5_core_dev *mdev,
1736 struct mlx5e_sq_param *param,
1737 struct mlx5e_create_sq_param *csp,
1738 u16 qos_queue_group_id,
1741 struct mlx5e_modify_sq_param msp = {0};
1744 err = mlx5e_create_sq(mdev, param, csp, sqn);
1748 msp.curr_state = MLX5_SQC_STATE_RST;
1749 msp.next_state = MLX5_SQC_STATE_RDY;
1750 if (qos_queue_group_id) {
1751 msp.qos_update = true;
1752 msp.qos_queue_group_id = qos_queue_group_id;
1754 err = mlx5e_modify_sq(mdev, *sqn, &msp);
1756 mlx5e_destroy_sq(mdev, *sqn);
1761 static int mlx5e_set_sq_maxrate(struct net_device *dev,
1762 struct mlx5e_txqsq *sq, u32 rate);
1764 int mlx5e_open_txqsq(struct mlx5e_channel *c, u32 tisn, int txq_ix,
1765 struct mlx5e_params *params, struct mlx5e_sq_param *param,
1766 struct mlx5e_txqsq *sq, int tc, u16 qos_queue_group_id,
1767 struct mlx5e_sq_stats *sq_stats)
1769 struct mlx5e_create_sq_param csp = {};
1773 err = mlx5e_alloc_txqsq(c, txq_ix, params, param, sq, tc);
1777 sq->stats = sq_stats;
1781 csp.cqn = sq->cq.mcq.cqn;
1782 csp.wq_ctrl = &sq->wq_ctrl;
1783 csp.min_inline_mode = sq->min_inline_mode;
1784 err = mlx5e_create_sq_rdy(c->mdev, param, &csp, qos_queue_group_id, &sq->sqn);
1786 goto err_free_txqsq;
1788 tx_rate = c->priv->tx_rates[sq->txq_ix];
1790 mlx5e_set_sq_maxrate(c->netdev, sq, tx_rate);
1792 if (params->tx_dim_enabled)
1793 sq->state |= BIT(MLX5E_SQ_STATE_DIM);
1798 mlx5e_free_txqsq(sq);
1803 void mlx5e_activate_txqsq(struct mlx5e_txqsq *sq)
1805 sq->txq = netdev_get_tx_queue(sq->netdev, sq->txq_ix);
1806 set_bit(MLX5E_SQ_STATE_ENABLED, &sq->state);
1807 netdev_tx_reset_queue(sq->txq);
1808 netif_tx_start_queue(sq->txq);
1811 void mlx5e_tx_disable_queue(struct netdev_queue *txq)
1813 __netif_tx_lock_bh(txq);
1814 netif_tx_stop_queue(txq);
1815 __netif_tx_unlock_bh(txq);
1818 void mlx5e_deactivate_txqsq(struct mlx5e_txqsq *sq)
1820 struct mlx5_wq_cyc *wq = &sq->wq;
1822 clear_bit(MLX5E_SQ_STATE_ENABLED, &sq->state);
1823 synchronize_net(); /* Sync with NAPI to prevent netif_tx_wake_queue. */
1825 mlx5e_tx_disable_queue(sq->txq);
1827 /* last doorbell out, godspeed .. */
1828 if (mlx5e_wqc_has_room_for(wq, sq->cc, sq->pc, 1)) {
1829 u16 pi = mlx5_wq_cyc_ctr2ix(wq, sq->pc);
1830 struct mlx5e_tx_wqe *nop;
1832 sq->db.wqe_info[pi] = (struct mlx5e_tx_wqe_info) {
1836 nop = mlx5e_post_nop(wq, sq->sqn, &sq->pc);
1837 mlx5e_notify_hw(wq, sq->pc, sq->uar_map, &nop->ctrl);
1841 void mlx5e_close_txqsq(struct mlx5e_txqsq *sq)
1843 struct mlx5_core_dev *mdev = sq->mdev;
1844 struct mlx5_rate_limit rl = {0};
1846 cancel_work_sync(&sq->dim.work);
1847 cancel_work_sync(&sq->recover_work);
1848 mlx5e_destroy_sq(mdev, sq->sqn);
1849 if (sq->rate_limit) {
1850 rl.rate = sq->rate_limit;
1851 mlx5_rl_remove_rate(mdev, &rl);
1853 mlx5e_free_txqsq_descs(sq);
1854 mlx5e_free_txqsq(sq);
1857 void mlx5e_tx_err_cqe_work(struct work_struct *recover_work)
1859 struct mlx5e_txqsq *sq = container_of(recover_work, struct mlx5e_txqsq,
1862 mlx5e_reporter_tx_err_cqe(sq);
1865 static int mlx5e_open_icosq(struct mlx5e_channel *c, struct mlx5e_params *params,
1866 struct mlx5e_sq_param *param, struct mlx5e_icosq *sq,
1867 work_func_t recover_work_func)
1869 struct mlx5e_create_sq_param csp = {};
1872 err = mlx5e_alloc_icosq(c, param, sq, recover_work_func);
1876 csp.cqn = sq->cq.mcq.cqn;
1877 csp.wq_ctrl = &sq->wq_ctrl;
1878 csp.min_inline_mode = params->tx_min_inline_mode;
1879 err = mlx5e_create_sq_rdy(c->mdev, param, &csp, 0, &sq->sqn);
1881 goto err_free_icosq;
1883 if (param->is_tls) {
1884 sq->ktls_resync = mlx5e_ktls_rx_resync_create_resp_list();
1885 if (IS_ERR(sq->ktls_resync)) {
1886 err = PTR_ERR(sq->ktls_resync);
1887 goto err_destroy_icosq;
1893 mlx5e_destroy_sq(c->mdev, sq->sqn);
1895 mlx5e_free_icosq(sq);
1900 void mlx5e_activate_icosq(struct mlx5e_icosq *icosq)
1902 set_bit(MLX5E_SQ_STATE_ENABLED, &icosq->state);
1905 void mlx5e_deactivate_icosq(struct mlx5e_icosq *icosq)
1907 clear_bit(MLX5E_SQ_STATE_ENABLED, &icosq->state);
1908 synchronize_net(); /* Sync with NAPI. */
1911 static void mlx5e_close_icosq(struct mlx5e_icosq *sq)
1913 struct mlx5e_channel *c = sq->channel;
1915 if (sq->ktls_resync)
1916 mlx5e_ktls_rx_resync_destroy_resp_list(sq->ktls_resync);
1917 mlx5e_destroy_sq(c->mdev, sq->sqn);
1918 mlx5e_free_icosq_descs(sq);
1919 mlx5e_free_icosq(sq);
1922 int mlx5e_open_xdpsq(struct mlx5e_channel *c, struct mlx5e_params *params,
1923 struct mlx5e_sq_param *param, struct xsk_buff_pool *xsk_pool,
1924 struct mlx5e_xdpsq *sq, bool is_redirect)
1926 struct mlx5e_create_sq_param csp = {};
1929 err = mlx5e_alloc_xdpsq(c, params, xsk_pool, param, sq, is_redirect);
1934 csp.tisn = mlx5e_profile_get_tisn(c->mdev, c->priv, c->priv->profile,
1935 c->lag_port, 0); /* tc = 0 */
1936 csp.cqn = sq->cq.mcq.cqn;
1937 csp.wq_ctrl = &sq->wq_ctrl;
1938 csp.min_inline_mode = sq->min_inline_mode;
1939 set_bit(MLX5E_SQ_STATE_ENABLED, &sq->state);
1941 if (param->is_xdp_mb)
1942 set_bit(MLX5E_SQ_STATE_XDP_MULTIBUF, &sq->state);
1944 err = mlx5e_create_sq_rdy(c->mdev, param, &csp, 0, &sq->sqn);
1946 goto err_free_xdpsq;
1948 mlx5e_set_xmit_fp(sq, param->is_mpw);
1950 if (!param->is_mpw && !test_bit(MLX5E_SQ_STATE_XDP_MULTIBUF, &sq->state)) {
1951 unsigned int ds_cnt = MLX5E_TX_WQE_EMPTY_DS_COUNT + 1;
1952 unsigned int inline_hdr_sz = 0;
1955 if (sq->min_inline_mode != MLX5_INLINE_MODE_NONE) {
1956 inline_hdr_sz = MLX5E_XDP_MIN_INLINE;
1960 /* Pre initialize fixed WQE fields */
1961 for (i = 0; i < mlx5_wq_cyc_get_size(&sq->wq); i++) {
1962 struct mlx5e_tx_wqe *wqe = mlx5_wq_cyc_get_wqe(&sq->wq, i);
1963 struct mlx5_wqe_ctrl_seg *cseg = &wqe->ctrl;
1964 struct mlx5_wqe_eth_seg *eseg = &wqe->eth;
1966 sq->db.wqe_info[i] = (struct mlx5e_xdp_wqe_info) {
1971 cseg->qpn_ds = cpu_to_be32((sq->sqn << 8) | ds_cnt);
1972 eseg->inline_hdr.sz = cpu_to_be16(inline_hdr_sz);
1979 clear_bit(MLX5E_SQ_STATE_ENABLED, &sq->state);
1980 mlx5e_free_xdpsq(sq);
1985 void mlx5e_close_xdpsq(struct mlx5e_xdpsq *sq)
1987 struct mlx5e_channel *c = sq->channel;
1989 clear_bit(MLX5E_SQ_STATE_ENABLED, &sq->state);
1990 synchronize_net(); /* Sync with NAPI. */
1992 mlx5e_destroy_sq(c->mdev, sq->sqn);
1993 mlx5e_free_xdpsq_descs(sq);
1994 mlx5e_free_xdpsq(sq);
1997 static int mlx5e_alloc_cq_common(struct mlx5_core_dev *mdev,
1998 struct net_device *netdev,
1999 struct workqueue_struct *workqueue,
2000 struct mlx5e_cq_param *param,
2001 struct mlx5e_cq *cq)
2003 struct mlx5_core_cq *mcq = &cq->mcq;
2007 err = mlx5_cqwq_create(mdev, ¶m->wq, param->cqc, &cq->wq,
2013 mcq->set_ci_db = cq->wq_ctrl.db.db;
2014 mcq->arm_db = cq->wq_ctrl.db.db + 1;
2015 *mcq->set_ci_db = 0;
2017 mcq->vector = param->eq_ix;
2018 mcq->comp = mlx5e_completion_event;
2019 mcq->event = mlx5e_cq_error_event;
2021 for (i = 0; i < mlx5_cqwq_get_size(&cq->wq); i++) {
2022 struct mlx5_cqe64 *cqe = mlx5_cqwq_get_wqe(&cq->wq, i);
2025 cqe->validity_iteration_count = 0xff;
2029 cq->netdev = netdev;
2030 cq->workqueue = workqueue;
2035 static int mlx5e_alloc_cq(struct mlx5_core_dev *mdev,
2036 struct mlx5e_cq_param *param,
2037 struct mlx5e_create_cq_param *ccp,
2038 struct mlx5e_cq *cq)
2042 param->wq.buf_numa_node = ccp->node;
2043 param->wq.db_numa_node = ccp->node;
2044 param->eq_ix = ccp->ix;
2046 err = mlx5e_alloc_cq_common(mdev, ccp->netdev, ccp->wq, param, cq);
2048 cq->napi = ccp->napi;
2049 cq->ch_stats = ccp->ch_stats;
2054 static void mlx5e_free_cq(struct mlx5e_cq *cq)
2056 mlx5_wq_destroy(&cq->wq_ctrl);
2059 static int mlx5e_create_cq(struct mlx5e_cq *cq, struct mlx5e_cq_param *param)
2061 u32 out[MLX5_ST_SZ_DW(create_cq_out)];
2062 struct mlx5_core_dev *mdev = cq->mdev;
2063 struct mlx5_core_cq *mcq = &cq->mcq;
2071 err = mlx5_comp_eqn_get(mdev, param->eq_ix, &eqn);
2075 inlen = MLX5_ST_SZ_BYTES(create_cq_in) +
2076 sizeof(u64) * cq->wq_ctrl.buf.npages;
2077 in = kvzalloc(inlen, GFP_KERNEL);
2081 cqc = MLX5_ADDR_OF(create_cq_in, in, cq_context);
2083 memcpy(cqc, param->cqc, sizeof(param->cqc));
2085 mlx5_fill_page_frag_array(&cq->wq_ctrl.buf,
2086 (__be64 *)MLX5_ADDR_OF(create_cq_in, in, pas));
2088 MLX5_SET(cqc, cqc, cq_period_mode, param->cq_period_mode);
2089 MLX5_SET(cqc, cqc, c_eqn_or_apu_element, eqn);
2090 MLX5_SET(cqc, cqc, uar_page, mdev->priv.uar->index);
2091 MLX5_SET(cqc, cqc, log_page_size, cq->wq_ctrl.buf.page_shift -
2092 MLX5_ADAPTER_PAGE_SHIFT);
2093 MLX5_SET64(cqc, cqc, dbr_addr, cq->wq_ctrl.db.dma);
2095 err = mlx5_core_create_cq(mdev, mcq, in, inlen, out, sizeof(out));
2107 static void mlx5e_destroy_cq(struct mlx5e_cq *cq)
2109 mlx5_core_destroy_cq(cq->mdev, &cq->mcq);
2112 int mlx5e_open_cq(struct mlx5_core_dev *mdev, struct dim_cq_moder moder,
2113 struct mlx5e_cq_param *param, struct mlx5e_create_cq_param *ccp,
2114 struct mlx5e_cq *cq)
2118 err = mlx5e_alloc_cq(mdev, param, ccp, cq);
2122 err = mlx5e_create_cq(cq, param);
2126 if (MLX5_CAP_GEN(mdev, cq_moderation))
2127 mlx5_core_modify_cq_moderation(mdev, &cq->mcq, moder.usec, moder.pkts);
2136 void mlx5e_close_cq(struct mlx5e_cq *cq)
2138 mlx5e_destroy_cq(cq);
2142 static int mlx5e_open_tx_cqs(struct mlx5e_channel *c,
2143 struct mlx5e_params *params,
2144 struct mlx5e_create_cq_param *ccp,
2145 struct mlx5e_channel_param *cparam)
2150 for (tc = 0; tc < c->num_tc; tc++) {
2151 err = mlx5e_open_cq(c->mdev, params->tx_cq_moderation, &cparam->txq_sq.cqp,
2152 ccp, &c->sq[tc].cq);
2154 goto err_close_tx_cqs;
2160 for (tc--; tc >= 0; tc--)
2161 mlx5e_close_cq(&c->sq[tc].cq);
2166 static void mlx5e_close_tx_cqs(struct mlx5e_channel *c)
2170 for (tc = 0; tc < c->num_tc; tc++)
2171 mlx5e_close_cq(&c->sq[tc].cq);
2174 static int mlx5e_mqprio_txq_to_tc(struct netdev_tc_txq *tc_to_txq, unsigned int txq)
2178 for (tc = 0; tc < TC_MAX_QUEUE; tc++)
2179 if (txq - tc_to_txq[tc].offset < tc_to_txq[tc].count)
2182 WARN(1, "Unexpected TCs configuration. No match found for txq %u", txq);
2186 static int mlx5e_txq_get_qos_node_hw_id(struct mlx5e_params *params, int txq_ix,
2191 if (params->mqprio.mode != TC_MQPRIO_MODE_CHANNEL) {
2196 tc = mlx5e_mqprio_txq_to_tc(params->mqprio.tc_to_txq, txq_ix);
2200 if (tc >= params->mqprio.num_tc) {
2201 WARN(1, "Unexpected TCs configuration. tc %d is out of range of %u",
2202 tc, params->mqprio.num_tc);
2206 *hw_id = params->mqprio.channel.hw_id[tc];
2210 static int mlx5e_open_sqs(struct mlx5e_channel *c,
2211 struct mlx5e_params *params,
2212 struct mlx5e_channel_param *cparam)
2216 for (tc = 0; tc < mlx5e_get_dcb_num_tc(params); tc++) {
2217 int txq_ix = c->ix + tc * params->num_channels;
2218 u32 qos_queue_group_id;
2221 tisn = mlx5e_profile_get_tisn(c->mdev, c->priv, c->priv->profile,
2223 err = mlx5e_txq_get_qos_node_hw_id(params, txq_ix, &qos_queue_group_id);
2227 err = mlx5e_open_txqsq(c, tisn, txq_ix,
2228 params, &cparam->txq_sq, &c->sq[tc], tc,
2230 &c->priv->channel_stats[c->ix]->sq[tc]);
2238 for (tc--; tc >= 0; tc--)
2239 mlx5e_close_txqsq(&c->sq[tc]);
2244 static void mlx5e_close_sqs(struct mlx5e_channel *c)
2248 for (tc = 0; tc < c->num_tc; tc++)
2249 mlx5e_close_txqsq(&c->sq[tc]);
2252 static int mlx5e_set_sq_maxrate(struct net_device *dev,
2253 struct mlx5e_txqsq *sq, u32 rate)
2255 struct mlx5e_priv *priv = netdev_priv(dev);
2256 struct mlx5_core_dev *mdev = priv->mdev;
2257 struct mlx5e_modify_sq_param msp = {0};
2258 struct mlx5_rate_limit rl = {0};
2262 if (rate == sq->rate_limit)
2266 if (sq->rate_limit) {
2267 rl.rate = sq->rate_limit;
2268 /* remove current rl index to free space to next ones */
2269 mlx5_rl_remove_rate(mdev, &rl);
2276 err = mlx5_rl_add_rate(mdev, &rl_index, &rl);
2278 netdev_err(dev, "Failed configuring rate %u: %d\n",
2284 msp.curr_state = MLX5_SQC_STATE_RDY;
2285 msp.next_state = MLX5_SQC_STATE_RDY;
2286 msp.rl_index = rl_index;
2287 msp.rl_update = true;
2288 err = mlx5e_modify_sq(mdev, sq->sqn, &msp);
2290 netdev_err(dev, "Failed configuring rate %u: %d\n",
2292 /* remove the rate from the table */
2294 mlx5_rl_remove_rate(mdev, &rl);
2298 sq->rate_limit = rate;
2302 static int mlx5e_set_tx_maxrate(struct net_device *dev, int index, u32 rate)
2304 struct mlx5e_priv *priv = netdev_priv(dev);
2305 struct mlx5_core_dev *mdev = priv->mdev;
2306 struct mlx5e_txqsq *sq = priv->txq2sq[index];
2309 if (!mlx5_rl_is_supported(mdev)) {
2310 netdev_err(dev, "Rate limiting is not supported on this device\n");
2314 /* rate is given in Mb/sec, HW config is in Kb/sec */
2317 /* Check whether rate in valid range, 0 is always valid */
2318 if (rate && !mlx5_rl_is_in_range(mdev, rate)) {
2319 netdev_err(dev, "TX rate %u, is not in range\n", rate);
2323 mutex_lock(&priv->state_lock);
2324 if (test_bit(MLX5E_STATE_OPENED, &priv->state))
2325 err = mlx5e_set_sq_maxrate(dev, sq, rate);
2327 priv->tx_rates[index] = rate;
2328 mutex_unlock(&priv->state_lock);
2333 static int mlx5e_open_rxq_rq(struct mlx5e_channel *c, struct mlx5e_params *params,
2334 struct mlx5e_rq_param *rq_params)
2338 err = mlx5e_init_rxq_rq(c, params, rq_params->xdp_frag_size, &c->rq);
2342 return mlx5e_open_rq(params, rq_params, NULL, cpu_to_node(c->cpu), &c->rq);
2345 static int mlx5e_open_queues(struct mlx5e_channel *c,
2346 struct mlx5e_params *params,
2347 struct mlx5e_channel_param *cparam)
2349 struct dim_cq_moder icocq_moder = {0, 0};
2350 struct mlx5e_create_cq_param ccp;
2353 mlx5e_build_create_cq_param(&ccp, c);
2355 err = mlx5e_open_cq(c->mdev, icocq_moder, &cparam->async_icosq.cqp, &ccp,
2356 &c->async_icosq.cq);
2360 err = mlx5e_open_cq(c->mdev, icocq_moder, &cparam->icosq.cqp, &ccp,
2363 goto err_close_async_icosq_cq;
2365 err = mlx5e_open_tx_cqs(c, params, &ccp, cparam);
2367 goto err_close_icosq_cq;
2369 err = mlx5e_open_cq(c->mdev, params->tx_cq_moderation, &cparam->xdp_sq.cqp, &ccp,
2372 goto err_close_tx_cqs;
2374 err = mlx5e_open_cq(c->mdev, params->rx_cq_moderation, &cparam->rq.cqp, &ccp,
2377 goto err_close_xdp_tx_cqs;
2379 err = c->xdp ? mlx5e_open_cq(c->mdev, params->tx_cq_moderation, &cparam->xdp_sq.cqp,
2380 &ccp, &c->rq_xdpsq.cq) : 0;
2382 goto err_close_rx_cq;
2384 spin_lock_init(&c->async_icosq_lock);
2386 err = mlx5e_open_icosq(c, params, &cparam->async_icosq, &c->async_icosq,
2387 mlx5e_async_icosq_err_cqe_work);
2389 goto err_close_xdpsq_cq;
2391 mutex_init(&c->icosq_recovery_lock);
2393 err = mlx5e_open_icosq(c, params, &cparam->icosq, &c->icosq,
2394 mlx5e_icosq_err_cqe_work);
2396 goto err_close_async_icosq;
2398 err = mlx5e_open_sqs(c, params, cparam);
2400 goto err_close_icosq;
2402 err = mlx5e_open_rxq_rq(c, params, &cparam->rq);
2407 err = mlx5e_open_xdpsq(c, params, &cparam->xdp_sq, NULL,
2408 &c->rq_xdpsq, false);
2413 err = mlx5e_open_xdpsq(c, params, &cparam->xdp_sq, NULL, &c->xdpsq, true);
2415 goto err_close_xdp_sq;
2421 mlx5e_close_xdpsq(&c->rq_xdpsq);
2424 mlx5e_close_rq(&c->rq);
2430 mlx5e_close_icosq(&c->icosq);
2432 err_close_async_icosq:
2433 mlx5e_close_icosq(&c->async_icosq);
2437 mlx5e_close_cq(&c->rq_xdpsq.cq);
2440 mlx5e_close_cq(&c->rq.cq);
2442 err_close_xdp_tx_cqs:
2443 mlx5e_close_cq(&c->xdpsq.cq);
2446 mlx5e_close_tx_cqs(c);
2449 mlx5e_close_cq(&c->icosq.cq);
2451 err_close_async_icosq_cq:
2452 mlx5e_close_cq(&c->async_icosq.cq);
2457 static void mlx5e_close_queues(struct mlx5e_channel *c)
2459 mlx5e_close_xdpsq(&c->xdpsq);
2461 mlx5e_close_xdpsq(&c->rq_xdpsq);
2462 /* The same ICOSQ is used for UMRs for both RQ and XSKRQ. */
2463 cancel_work_sync(&c->icosq.recover_work);
2464 mlx5e_close_rq(&c->rq);
2466 mlx5e_close_icosq(&c->icosq);
2467 mutex_destroy(&c->icosq_recovery_lock);
2468 mlx5e_close_icosq(&c->async_icosq);
2470 mlx5e_close_cq(&c->rq_xdpsq.cq);
2471 mlx5e_close_cq(&c->rq.cq);
2472 mlx5e_close_cq(&c->xdpsq.cq);
2473 mlx5e_close_tx_cqs(c);
2474 mlx5e_close_cq(&c->icosq.cq);
2475 mlx5e_close_cq(&c->async_icosq.cq);
2478 static u8 mlx5e_enumerate_lag_port(struct mlx5_core_dev *mdev, int ix)
2480 u16 port_aff_bias = mlx5_core_is_pf(mdev) ? 0 : MLX5_CAP_GEN(mdev, vhca_id);
2482 return (ix + port_aff_bias) % mlx5e_get_num_lag_ports(mdev);
2485 static int mlx5e_channel_stats_alloc(struct mlx5e_priv *priv, int ix, int cpu)
2487 if (ix > priv->stats_nch) {
2488 netdev_warn(priv->netdev, "Unexpected channel stats index %d > %d\n", ix,
2493 if (priv->channel_stats[ix])
2496 /* Asymmetric dynamic memory allocation.
2497 * Freed in mlx5e_priv_arrays_free, not on channel closure.
2499 netdev_dbg(priv->netdev, "Creating channel stats %d\n", ix);
2500 priv->channel_stats[ix] = kvzalloc_node(sizeof(**priv->channel_stats),
2501 GFP_KERNEL, cpu_to_node(cpu));
2502 if (!priv->channel_stats[ix])
2509 void mlx5e_trigger_napi_icosq(struct mlx5e_channel *c)
2511 spin_lock_bh(&c->async_icosq_lock);
2512 mlx5e_trigger_irq(&c->async_icosq);
2513 spin_unlock_bh(&c->async_icosq_lock);
2516 void mlx5e_trigger_napi_sched(struct napi_struct *napi)
2519 napi_schedule(napi);
2523 static int mlx5e_open_channel(struct mlx5e_priv *priv, int ix,
2524 struct mlx5e_params *params,
2525 struct mlx5e_channel_param *cparam,
2526 struct xsk_buff_pool *xsk_pool,
2527 struct mlx5e_channel **cp)
2529 int cpu = mlx5_comp_vector_get_cpu(priv->mdev, ix);
2530 struct net_device *netdev = priv->netdev;
2531 struct mlx5e_xsk_param xsk;
2532 struct mlx5e_channel *c;
2536 err = mlx5_comp_irqn_get(priv->mdev, ix, &irq);
2540 err = mlx5e_channel_stats_alloc(priv, ix, cpu);
2544 c = kvzalloc_node(sizeof(*c), GFP_KERNEL, cpu_to_node(cpu));
2549 c->mdev = priv->mdev;
2550 c->tstamp = &priv->tstamp;
2553 c->pdev = mlx5_core_dma_dev(priv->mdev);
2554 c->netdev = priv->netdev;
2555 c->mkey_be = cpu_to_be32(priv->mdev->mlx5e_res.hw_objs.mkey);
2556 c->num_tc = mlx5e_get_dcb_num_tc(params);
2557 c->xdp = !!params->xdp_prog;
2558 c->stats = &priv->channel_stats[ix]->ch;
2559 c->aff_mask = irq_get_effective_affinity_mask(irq);
2560 c->lag_port = mlx5e_enumerate_lag_port(priv->mdev, ix);
2562 netif_napi_add(netdev, &c->napi, mlx5e_napi_poll);
2564 err = mlx5e_open_queues(c, params, cparam);
2569 mlx5e_build_xsk_param(xsk_pool, &xsk);
2570 err = mlx5e_open_xsk(priv, params, &xsk, xsk_pool, c);
2572 goto err_close_queues;
2580 mlx5e_close_queues(c);
2583 netif_napi_del(&c->napi);
2590 static void mlx5e_activate_channel(struct mlx5e_channel *c)
2594 napi_enable(&c->napi);
2596 for (tc = 0; tc < c->num_tc; tc++)
2597 mlx5e_activate_txqsq(&c->sq[tc]);
2598 mlx5e_activate_icosq(&c->icosq);
2599 mlx5e_activate_icosq(&c->async_icosq);
2601 if (test_bit(MLX5E_CHANNEL_STATE_XSK, c->state))
2602 mlx5e_activate_xsk(c);
2604 mlx5e_activate_rq(&c->rq);
2607 static void mlx5e_deactivate_channel(struct mlx5e_channel *c)
2611 if (test_bit(MLX5E_CHANNEL_STATE_XSK, c->state))
2612 mlx5e_deactivate_xsk(c);
2614 mlx5e_deactivate_rq(&c->rq);
2616 mlx5e_deactivate_icosq(&c->async_icosq);
2617 mlx5e_deactivate_icosq(&c->icosq);
2618 for (tc = 0; tc < c->num_tc; tc++)
2619 mlx5e_deactivate_txqsq(&c->sq[tc]);
2620 mlx5e_qos_deactivate_queues(c);
2622 napi_disable(&c->napi);
2625 static void mlx5e_close_channel(struct mlx5e_channel *c)
2627 if (test_bit(MLX5E_CHANNEL_STATE_XSK, c->state))
2629 mlx5e_close_queues(c);
2630 mlx5e_qos_close_queues(c);
2631 netif_napi_del(&c->napi);
2636 int mlx5e_open_channels(struct mlx5e_priv *priv,
2637 struct mlx5e_channels *chs)
2639 struct mlx5e_channel_param *cparam;
2643 chs->num = chs->params.num_channels;
2645 chs->c = kcalloc(chs->num, sizeof(struct mlx5e_channel *), GFP_KERNEL);
2646 cparam = kvzalloc(sizeof(struct mlx5e_channel_param), GFP_KERNEL);
2647 if (!chs->c || !cparam)
2650 err = mlx5e_build_channel_param(priv->mdev, &chs->params, priv->q_counter, cparam);
2654 for (i = 0; i < chs->num; i++) {
2655 struct xsk_buff_pool *xsk_pool = NULL;
2657 if (chs->params.xdp_prog)
2658 xsk_pool = mlx5e_xsk_get_pool(&chs->params, chs->params.xsk, i);
2660 err = mlx5e_open_channel(priv, i, &chs->params, cparam, xsk_pool, &chs->c[i]);
2662 goto err_close_channels;
2665 if (MLX5E_GET_PFLAG(&chs->params, MLX5E_PFLAG_TX_PORT_TS) || chs->params.ptp_rx) {
2666 err = mlx5e_ptp_open(priv, &chs->params, chs->c[0]->lag_port, &chs->ptp);
2668 goto err_close_channels;
2672 err = mlx5e_qos_open_queues(priv, chs);
2677 mlx5e_health_channels_update(priv);
2683 mlx5e_ptp_close(chs->ptp);
2686 for (i--; i >= 0; i--)
2687 mlx5e_close_channel(chs->c[i]);
2696 static void mlx5e_activate_channels(struct mlx5e_priv *priv, struct mlx5e_channels *chs)
2700 for (i = 0; i < chs->num; i++)
2701 mlx5e_activate_channel(chs->c[i]);
2704 mlx5e_qos_activate_queues(priv);
2706 for (i = 0; i < chs->num; i++)
2707 mlx5e_trigger_napi_icosq(chs->c[i]);
2710 mlx5e_ptp_activate_channel(chs->ptp);
2713 static int mlx5e_wait_channels_min_rx_wqes(struct mlx5e_channels *chs)
2718 for (i = 0; i < chs->num; i++) {
2719 int timeout = err ? 0 : MLX5E_RQ_WQES_TIMEOUT;
2720 struct mlx5e_channel *c = chs->c[i];
2722 if (test_bit(MLX5E_CHANNEL_STATE_XSK, c->state))
2725 err |= mlx5e_wait_for_min_rx_wqes(&c->rq, timeout);
2727 /* Don't wait on the XSK RQ, because the newer xdpsock sample
2728 * doesn't provide any Fill Ring entries at the setup stage.
2732 return err ? -ETIMEDOUT : 0;
2735 static void mlx5e_deactivate_channels(struct mlx5e_channels *chs)
2740 mlx5e_ptp_deactivate_channel(chs->ptp);
2742 for (i = 0; i < chs->num; i++)
2743 mlx5e_deactivate_channel(chs->c[i]);
2746 void mlx5e_close_channels(struct mlx5e_channels *chs)
2752 mlx5e_ptp_close(chs->ptp);
2755 for (i = 0; i < chs->num; i++)
2756 mlx5e_close_channel(chs->c[i]);
2762 static int mlx5e_modify_tirs_packet_merge(struct mlx5e_priv *priv)
2764 struct mlx5e_rx_res *res = priv->rx_res;
2766 return mlx5e_rx_res_packet_merge_set_param(res, &priv->channels.params.packet_merge);
2769 static MLX5E_DEFINE_PREACTIVATE_WRAPPER_CTX(mlx5e_modify_tirs_packet_merge);
2771 static int mlx5e_set_mtu(struct mlx5_core_dev *mdev,
2772 struct mlx5e_params *params, u16 mtu)
2774 u16 hw_mtu = MLX5E_SW2HW_MTU(params, mtu);
2777 err = mlx5_set_port_mtu(mdev, hw_mtu, 1);
2781 /* Update vport context MTU */
2782 mlx5_modify_nic_vport_mtu(mdev, hw_mtu);
2786 static void mlx5e_query_mtu(struct mlx5_core_dev *mdev,
2787 struct mlx5e_params *params, u16 *mtu)
2792 err = mlx5_query_nic_vport_mtu(mdev, &hw_mtu);
2793 if (err || !hw_mtu) /* fallback to port oper mtu */
2794 mlx5_query_port_oper_mtu(mdev, &hw_mtu, 1);
2796 *mtu = MLX5E_HW2SW_MTU(params, hw_mtu);
2799 int mlx5e_set_dev_port_mtu(struct mlx5e_priv *priv)
2801 struct mlx5e_params *params = &priv->channels.params;
2802 struct net_device *netdev = priv->netdev;
2803 struct mlx5_core_dev *mdev = priv->mdev;
2807 err = mlx5e_set_mtu(mdev, params, params->sw_mtu);
2811 mlx5e_query_mtu(mdev, params, &mtu);
2812 if (mtu != params->sw_mtu)
2813 netdev_warn(netdev, "%s: VPort MTU %d is different than netdev mtu %d\n",
2814 __func__, mtu, params->sw_mtu);
2816 params->sw_mtu = mtu;
2820 MLX5E_DEFINE_PREACTIVATE_WRAPPER_CTX(mlx5e_set_dev_port_mtu);
2822 void mlx5e_set_netdev_mtu_boundaries(struct mlx5e_priv *priv)
2824 struct mlx5e_params *params = &priv->channels.params;
2825 struct net_device *netdev = priv->netdev;
2826 struct mlx5_core_dev *mdev = priv->mdev;
2829 /* MTU range: 68 - hw-specific max */
2830 netdev->min_mtu = ETH_MIN_MTU;
2832 mlx5_query_port_max_mtu(mdev, &max_mtu, 1);
2833 netdev->max_mtu = min_t(unsigned int, MLX5E_HW2SW_MTU(params, max_mtu),
2837 static int mlx5e_netdev_set_tcs(struct net_device *netdev, u16 nch, u8 ntc,
2838 struct netdev_tc_txq *tc_to_txq)
2842 netdev_reset_tc(netdev);
2847 err = netdev_set_num_tc(netdev, ntc);
2849 netdev_WARN(netdev, "netdev_set_num_tc failed (%d), ntc = %d\n", err, ntc);
2853 for (tc = 0; tc < ntc; tc++) {
2856 count = tc_to_txq[tc].count;
2857 offset = tc_to_txq[tc].offset;
2858 netdev_set_tc_queue(netdev, tc, count, offset);
2864 int mlx5e_update_tx_netdev_queues(struct mlx5e_priv *priv)
2866 int nch, ntc, num_txqs, err;
2870 qos_queues = mlx5e_htb_cur_leaf_nodes(priv->htb);
2872 nch = priv->channels.params.num_channels;
2873 ntc = mlx5e_get_dcb_num_tc(&priv->channels.params);
2874 num_txqs = nch * ntc + qos_queues;
2875 if (MLX5E_GET_PFLAG(&priv->channels.params, MLX5E_PFLAG_TX_PORT_TS))
2878 netdev_dbg(priv->netdev, "Setting num_txqs %d\n", num_txqs);
2879 err = netif_set_real_num_tx_queues(priv->netdev, num_txqs);
2881 netdev_warn(priv->netdev, "netif_set_real_num_tx_queues failed, %d\n", err);
2886 static int mlx5e_update_netdev_queues(struct mlx5e_priv *priv)
2888 struct netdev_tc_txq old_tc_to_txq[TC_MAX_QUEUE], *tc_to_txq;
2889 struct net_device *netdev = priv->netdev;
2890 int old_num_txqs, old_ntc;
2895 old_num_txqs = netdev->real_num_tx_queues;
2896 old_ntc = netdev->num_tc ? : 1;
2897 for (i = 0; i < ARRAY_SIZE(old_tc_to_txq); i++)
2898 old_tc_to_txq[i] = netdev->tc_to_txq[i];
2900 nch = priv->channels.params.num_channels;
2901 ntc = priv->channels.params.mqprio.num_tc;
2902 tc_to_txq = priv->channels.params.mqprio.tc_to_txq;
2904 err = mlx5e_netdev_set_tcs(netdev, nch, ntc, tc_to_txq);
2907 err = mlx5e_update_tx_netdev_queues(priv);
2910 err = netif_set_real_num_rx_queues(netdev, nch);
2912 netdev_warn(netdev, "netif_set_real_num_rx_queues failed, %d\n", err);
2919 /* netif_set_real_num_rx_queues could fail only when nch increased. Only
2920 * one of nch and ntc is changed in this function. That means, the call
2921 * to netif_set_real_num_tx_queues below should not fail, because it
2922 * decreases the number of TX queues.
2924 WARN_ON_ONCE(netif_set_real_num_tx_queues(netdev, old_num_txqs));
2927 WARN_ON_ONCE(mlx5e_netdev_set_tcs(netdev, old_num_txqs / old_ntc, old_ntc,
2933 static MLX5E_DEFINE_PREACTIVATE_WRAPPER_CTX(mlx5e_update_netdev_queues);
2935 static void mlx5e_set_default_xps_cpumasks(struct mlx5e_priv *priv,
2936 struct mlx5e_params *params)
2938 struct mlx5_core_dev *mdev = priv->mdev;
2939 int num_comp_vectors, ix, irq;
2941 num_comp_vectors = mlx5_comp_vectors_max(mdev);
2943 for (ix = 0; ix < params->num_channels; ix++) {
2944 cpumask_clear(priv->scratchpad.cpumask);
2946 for (irq = ix; irq < num_comp_vectors; irq += params->num_channels) {
2947 int cpu = mlx5_comp_vector_get_cpu(mdev, irq);
2949 cpumask_set_cpu(cpu, priv->scratchpad.cpumask);
2952 netif_set_xps_queue(priv->netdev, priv->scratchpad.cpumask, ix);
2956 static int mlx5e_num_channels_changed(struct mlx5e_priv *priv)
2958 u16 count = priv->channels.params.num_channels;
2961 err = mlx5e_update_netdev_queues(priv);
2965 mlx5e_set_default_xps_cpumasks(priv, &priv->channels.params);
2967 /* This function may be called on attach, before priv->rx_res is created. */
2969 mlx5e_rx_res_rss_update_num_channels(priv->rx_res, count);
2971 if (!netif_is_rxfh_configured(priv->netdev))
2972 mlx5e_rx_res_rss_set_indir_uniform(priv->rx_res, count);
2978 MLX5E_DEFINE_PREACTIVATE_WRAPPER_CTX(mlx5e_num_channels_changed);
2980 static void mlx5e_build_txq_maps(struct mlx5e_priv *priv)
2982 int i, ch, tc, num_tc;
2984 ch = priv->channels.num;
2985 num_tc = mlx5e_get_dcb_num_tc(&priv->channels.params);
2987 for (i = 0; i < ch; i++) {
2988 for (tc = 0; tc < num_tc; tc++) {
2989 struct mlx5e_channel *c = priv->channels.c[i];
2990 struct mlx5e_txqsq *sq = &c->sq[tc];
2992 priv->txq2sq[sq->txq_ix] = sq;
2996 if (!priv->channels.ptp)
2999 if (!test_bit(MLX5E_PTP_STATE_TX, priv->channels.ptp->state))
3002 for (tc = 0; tc < num_tc; tc++) {
3003 struct mlx5e_ptp *c = priv->channels.ptp;
3004 struct mlx5e_txqsq *sq = &c->ptpsq[tc].txqsq;
3006 priv->txq2sq[sq->txq_ix] = sq;
3010 /* Make the change to txq2sq visible before the queue is started.
3011 * As mlx5e_xmit runs under a spinlock, there is an implicit ACQUIRE,
3012 * which pairs with this barrier.
3017 void mlx5e_activate_priv_channels(struct mlx5e_priv *priv)
3019 mlx5e_build_txq_maps(priv);
3020 mlx5e_activate_channels(priv, &priv->channels);
3021 mlx5e_xdp_tx_enable(priv);
3023 /* dev_watchdog() wants all TX queues to be started when the carrier is
3024 * OK, including the ones in range real_num_tx_queues..num_tx_queues-1.
3025 * Make it happy to avoid TX timeout false alarms.
3027 netif_tx_start_all_queues(priv->netdev);
3029 if (mlx5e_is_vport_rep(priv))
3030 mlx5e_rep_activate_channels(priv);
3032 set_bit(MLX5E_STATE_CHANNELS_ACTIVE, &priv->state);
3034 mlx5e_wait_channels_min_rx_wqes(&priv->channels);
3037 mlx5e_rx_res_channels_activate(priv->rx_res, &priv->channels);
3040 static void mlx5e_cancel_tx_timeout_work(struct mlx5e_priv *priv)
3042 WARN_ON_ONCE(test_bit(MLX5E_STATE_CHANNELS_ACTIVE, &priv->state));
3043 if (current_work() != &priv->tx_timeout_work)
3044 cancel_work_sync(&priv->tx_timeout_work);
3047 void mlx5e_deactivate_priv_channels(struct mlx5e_priv *priv)
3050 mlx5e_rx_res_channels_deactivate(priv->rx_res);
3052 clear_bit(MLX5E_STATE_CHANNELS_ACTIVE, &priv->state);
3053 mlx5e_cancel_tx_timeout_work(priv);
3055 if (mlx5e_is_vport_rep(priv))
3056 mlx5e_rep_deactivate_channels(priv);
3058 /* The results of ndo_select_queue are unreliable, while netdev config
3059 * is being changed (real_num_tx_queues, num_tc). Stop all queues to
3060 * prevent ndo_start_xmit from being called, so that it can assume that
3061 * the selected queue is always valid.
3063 netif_tx_disable(priv->netdev);
3065 mlx5e_xdp_tx_disable(priv);
3066 mlx5e_deactivate_channels(&priv->channels);
3069 static int mlx5e_switch_priv_params(struct mlx5e_priv *priv,
3070 struct mlx5e_params *new_params,
3071 mlx5e_fp_preactivate preactivate,
3074 struct mlx5e_params old_params;
3076 old_params = priv->channels.params;
3077 priv->channels.params = *new_params;
3082 err = preactivate(priv, context);
3084 priv->channels.params = old_params;
3092 static int mlx5e_switch_priv_channels(struct mlx5e_priv *priv,
3093 struct mlx5e_channels *new_chs,
3094 mlx5e_fp_preactivate preactivate,
3097 struct net_device *netdev = priv->netdev;
3098 struct mlx5e_channels old_chs;
3102 carrier_ok = netif_carrier_ok(netdev);
3103 netif_carrier_off(netdev);
3105 mlx5e_deactivate_priv_channels(priv);
3107 old_chs = priv->channels;
3108 priv->channels = *new_chs;
3110 /* New channels are ready to roll, call the preactivate hook if needed
3111 * to modify HW settings or update kernel parameters.
3114 err = preactivate(priv, context);
3116 priv->channels = old_chs;
3121 mlx5e_close_channels(&old_chs);
3122 priv->profile->update_rx(priv);
3124 mlx5e_selq_apply(&priv->selq);
3126 mlx5e_activate_priv_channels(priv);
3128 /* return carrier back if needed */
3130 netif_carrier_on(netdev);
3135 int mlx5e_safe_switch_params(struct mlx5e_priv *priv,
3136 struct mlx5e_params *params,
3137 mlx5e_fp_preactivate preactivate,
3138 void *context, bool reset)
3140 struct mlx5e_channels *new_chs;
3143 reset &= test_bit(MLX5E_STATE_OPENED, &priv->state);
3145 return mlx5e_switch_priv_params(priv, params, preactivate, context);
3147 new_chs = kzalloc(sizeof(*new_chs), GFP_KERNEL);
3150 new_chs->params = *params;
3152 mlx5e_selq_prepare_params(&priv->selq, &new_chs->params);
3154 err = mlx5e_open_channels(priv, new_chs);
3156 goto err_cancel_selq;
3158 err = mlx5e_switch_priv_channels(priv, new_chs, preactivate, context);
3166 mlx5e_close_channels(new_chs);
3169 mlx5e_selq_cancel(&priv->selq);
3174 int mlx5e_safe_reopen_channels(struct mlx5e_priv *priv)
3176 return mlx5e_safe_switch_params(priv, &priv->channels.params, NULL, NULL, true);
3179 void mlx5e_timestamp_init(struct mlx5e_priv *priv)
3181 priv->tstamp.tx_type = HWTSTAMP_TX_OFF;
3182 priv->tstamp.rx_filter = HWTSTAMP_FILTER_NONE;
3185 static void mlx5e_modify_admin_state(struct mlx5_core_dev *mdev,
3186 enum mlx5_port_status state)
3188 struct mlx5_eswitch *esw = mdev->priv.eswitch;
3189 int vport_admin_state;
3191 mlx5_set_port_admin_status(mdev, state);
3193 if (mlx5_eswitch_mode(mdev) == MLX5_ESWITCH_OFFLOADS ||
3194 !MLX5_CAP_GEN(mdev, uplink_follow))
3197 if (state == MLX5_PORT_UP)
3198 vport_admin_state = MLX5_VPORT_ADMIN_STATE_AUTO;
3200 vport_admin_state = MLX5_VPORT_ADMIN_STATE_DOWN;
3202 mlx5_eswitch_set_vport_state(esw, MLX5_VPORT_UPLINK, vport_admin_state);
3205 int mlx5e_open_locked(struct net_device *netdev)
3207 struct mlx5e_priv *priv = netdev_priv(netdev);
3210 mlx5e_selq_prepare_params(&priv->selq, &priv->channels.params);
3212 set_bit(MLX5E_STATE_OPENED, &priv->state);
3214 err = mlx5e_open_channels(priv, &priv->channels);
3216 goto err_clear_state_opened_flag;
3218 err = priv->profile->update_rx(priv);
3220 goto err_close_channels;
3222 mlx5e_selq_apply(&priv->selq);
3223 mlx5e_activate_priv_channels(priv);
3224 mlx5e_apply_traps(priv, true);
3225 if (priv->profile->update_carrier)
3226 priv->profile->update_carrier(priv);
3228 mlx5e_queue_update_stats(priv);
3232 mlx5e_close_channels(&priv->channels);
3233 err_clear_state_opened_flag:
3234 clear_bit(MLX5E_STATE_OPENED, &priv->state);
3235 mlx5e_selq_cancel(&priv->selq);
3239 int mlx5e_open(struct net_device *netdev)
3241 struct mlx5e_priv *priv = netdev_priv(netdev);
3244 mutex_lock(&priv->state_lock);
3245 err = mlx5e_open_locked(netdev);
3247 mlx5e_modify_admin_state(priv->mdev, MLX5_PORT_UP);
3248 mutex_unlock(&priv->state_lock);
3253 int mlx5e_close_locked(struct net_device *netdev)
3255 struct mlx5e_priv *priv = netdev_priv(netdev);
3257 /* May already be CLOSED in case a previous configuration operation
3258 * (e.g RX/TX queue size change) that involves close&open failed.
3260 if (!test_bit(MLX5E_STATE_OPENED, &priv->state))
3263 mlx5e_apply_traps(priv, false);
3264 clear_bit(MLX5E_STATE_OPENED, &priv->state);
3266 netif_carrier_off(priv->netdev);
3267 mlx5e_deactivate_priv_channels(priv);
3268 mlx5e_close_channels(&priv->channels);
3273 int mlx5e_close(struct net_device *netdev)
3275 struct mlx5e_priv *priv = netdev_priv(netdev);
3278 if (!netif_device_present(netdev))
3281 mutex_lock(&priv->state_lock);
3282 mlx5e_modify_admin_state(priv->mdev, MLX5_PORT_DOWN);
3283 err = mlx5e_close_locked(netdev);
3284 mutex_unlock(&priv->state_lock);
3289 static void mlx5e_free_drop_rq(struct mlx5e_rq *rq)
3291 mlx5_wq_destroy(&rq->wq_ctrl);
3294 static int mlx5e_alloc_drop_rq(struct mlx5_core_dev *mdev,
3295 struct mlx5e_rq *rq,
3296 struct mlx5e_rq_param *param)
3298 void *rqc = param->rqc;
3299 void *rqc_wq = MLX5_ADDR_OF(rqc, rqc, wq);
3302 param->wq.db_numa_node = param->wq.buf_numa_node;
3304 err = mlx5_wq_cyc_create(mdev, ¶m->wq, rqc_wq, &rq->wqe.wq,
3309 /* Mark as unused given "Drop-RQ" packets never reach XDP */
3310 xdp_rxq_info_unused(&rq->xdp_rxq);
3317 static int mlx5e_alloc_drop_cq(struct mlx5e_priv *priv,
3318 struct mlx5e_cq *cq,
3319 struct mlx5e_cq_param *param)
3321 struct mlx5_core_dev *mdev = priv->mdev;
3323 param->wq.buf_numa_node = dev_to_node(mlx5_core_dma_dev(mdev));
3324 param->wq.db_numa_node = dev_to_node(mlx5_core_dma_dev(mdev));
3326 return mlx5e_alloc_cq_common(priv->mdev, priv->netdev, priv->wq, param, cq);
3329 int mlx5e_open_drop_rq(struct mlx5e_priv *priv,
3330 struct mlx5e_rq *drop_rq)
3332 struct mlx5_core_dev *mdev = priv->mdev;
3333 struct mlx5e_cq_param cq_param = {};
3334 struct mlx5e_rq_param rq_param = {};
3335 struct mlx5e_cq *cq = &drop_rq->cq;
3338 mlx5e_build_drop_rq_param(mdev, priv->drop_rq_q_counter, &rq_param);
3340 err = mlx5e_alloc_drop_cq(priv, cq, &cq_param);
3344 err = mlx5e_create_cq(cq, &cq_param);
3348 err = mlx5e_alloc_drop_rq(mdev, drop_rq, &rq_param);
3350 goto err_destroy_cq;
3352 err = mlx5e_create_rq(drop_rq, &rq_param);
3356 err = mlx5e_modify_rq_state(drop_rq, MLX5_RQC_STATE_RST, MLX5_RQC_STATE_RDY);
3358 mlx5_core_warn(priv->mdev, "modify_rq_state failed, rx_if_down_packets won't be counted %d\n", err);
3363 mlx5e_free_drop_rq(drop_rq);
3366 mlx5e_destroy_cq(cq);
3374 void mlx5e_close_drop_rq(struct mlx5e_rq *drop_rq)
3376 mlx5e_destroy_rq(drop_rq);
3377 mlx5e_free_drop_rq(drop_rq);
3378 mlx5e_destroy_cq(&drop_rq->cq);
3379 mlx5e_free_cq(&drop_rq->cq);
3382 static void mlx5e_cleanup_nic_tx(struct mlx5e_priv *priv)
3384 if (priv->mqprio_rl) {
3385 mlx5e_mqprio_rl_cleanup(priv->mqprio_rl);
3386 mlx5e_mqprio_rl_free(priv->mqprio_rl);
3387 priv->mqprio_rl = NULL;
3389 mlx5e_accel_cleanup_tx(priv);
3392 static int mlx5e_modify_channels_vsd(struct mlx5e_channels *chs, bool vsd)
3397 for (i = 0; i < chs->num; i++) {
3398 err = mlx5e_modify_rq_vsd(&chs->c[i]->rq, vsd);
3402 if (chs->ptp && test_bit(MLX5E_PTP_STATE_RX, chs->ptp->state))
3403 return mlx5e_modify_rq_vsd(&chs->ptp->rq, vsd);
3408 static void mlx5e_mqprio_build_default_tc_to_txq(struct netdev_tc_txq *tc_to_txq,
3413 memset(tc_to_txq, 0, sizeof(*tc_to_txq) * TC_MAX_QUEUE);
3415 /* Map netdev TCs to offset 0.
3416 * We have our own UP to TXQ mapping for DCB mode of QoS
3418 for (tc = 0; tc < ntc; tc++) {
3419 tc_to_txq[tc] = (struct netdev_tc_txq) {
3426 static void mlx5e_mqprio_build_tc_to_txq(struct netdev_tc_txq *tc_to_txq,
3427 struct tc_mqprio_qopt *qopt)
3431 for (tc = 0; tc < TC_MAX_QUEUE; tc++) {
3432 tc_to_txq[tc] = (struct netdev_tc_txq) {
3433 .count = qopt->count[tc],
3434 .offset = qopt->offset[tc],
3439 static void mlx5e_params_mqprio_dcb_set(struct mlx5e_params *params, u8 num_tc)
3441 params->mqprio.mode = TC_MQPRIO_MODE_DCB;
3442 params->mqprio.num_tc = num_tc;
3443 mlx5e_mqprio_build_default_tc_to_txq(params->mqprio.tc_to_txq, num_tc,
3444 params->num_channels);
3447 static void mlx5e_mqprio_rl_update_params(struct mlx5e_params *params,
3448 struct mlx5e_mqprio_rl *rl)
3452 for (tc = 0; tc < TC_MAX_QUEUE; tc++) {
3456 mlx5e_mqprio_rl_get_node_hw_id(rl, tc, &hw_id);
3457 params->mqprio.channel.hw_id[tc] = hw_id;
3461 static void mlx5e_params_mqprio_channel_set(struct mlx5e_params *params,
3462 struct tc_mqprio_qopt_offload *mqprio,
3463 struct mlx5e_mqprio_rl *rl)
3467 params->mqprio.mode = TC_MQPRIO_MODE_CHANNEL;
3468 params->mqprio.num_tc = mqprio->qopt.num_tc;
3470 for (tc = 0; tc < TC_MAX_QUEUE; tc++)
3471 params->mqprio.channel.max_rate[tc] = mqprio->max_rate[tc];
3473 mlx5e_mqprio_rl_update_params(params, rl);
3474 mlx5e_mqprio_build_tc_to_txq(params->mqprio.tc_to_txq, &mqprio->qopt);
3477 static void mlx5e_params_mqprio_reset(struct mlx5e_params *params)
3479 mlx5e_params_mqprio_dcb_set(params, 1);
3482 static int mlx5e_setup_tc_mqprio_dcb(struct mlx5e_priv *priv,
3483 struct tc_mqprio_qopt *mqprio)
3485 struct mlx5e_params new_params;
3486 u8 tc = mqprio->num_tc;
3489 mqprio->hw = TC_MQPRIO_HW_OFFLOAD_TCS;
3491 if (tc && tc != MLX5_MAX_NUM_TC)
3494 new_params = priv->channels.params;
3495 mlx5e_params_mqprio_dcb_set(&new_params, tc ? tc : 1);
3497 err = mlx5e_safe_switch_params(priv, &new_params,
3498 mlx5e_num_channels_changed_ctx, NULL, true);
3500 if (!err && priv->mqprio_rl) {
3501 mlx5e_mqprio_rl_cleanup(priv->mqprio_rl);
3502 mlx5e_mqprio_rl_free(priv->mqprio_rl);
3503 priv->mqprio_rl = NULL;
3506 priv->max_opened_tc = max_t(u8, priv->max_opened_tc,
3507 mlx5e_get_dcb_num_tc(&priv->channels.params));
3511 static int mlx5e_mqprio_channel_validate(struct mlx5e_priv *priv,
3512 struct tc_mqprio_qopt_offload *mqprio)
3514 struct net_device *netdev = priv->netdev;
3515 struct mlx5e_ptp *ptp_channel;
3519 ptp_channel = priv->channels.ptp;
3520 if (ptp_channel && test_bit(MLX5E_PTP_STATE_TX, ptp_channel->state)) {
3522 "Cannot activate MQPRIO mode channel since it conflicts with TX port TS\n");
3526 if (mqprio->qopt.offset[0] != 0 || mqprio->qopt.num_tc < 1 ||
3527 mqprio->qopt.num_tc > MLX5E_MAX_NUM_MQPRIO_CH_TC)
3530 for (i = 0; i < mqprio->qopt.num_tc; i++) {
3531 if (!mqprio->qopt.count[i]) {
3532 netdev_err(netdev, "Zero size for queue-group (%d) is not supported\n", i);
3535 if (mqprio->min_rate[i]) {
3536 netdev_err(netdev, "Min tx rate is not supported\n");
3540 if (mqprio->max_rate[i]) {
3543 err = mlx5e_qos_bytes_rate_check(priv->mdev, mqprio->max_rate[i]);
3548 if (mqprio->qopt.offset[i] != agg_count) {
3549 netdev_err(netdev, "Discontinuous queues config is not supported\n");
3552 agg_count += mqprio->qopt.count[i];
3555 if (priv->channels.params.num_channels != agg_count) {
3556 netdev_err(netdev, "Num of queues (%d) does not match available (%d)\n",
3557 agg_count, priv->channels.params.num_channels);
3564 static bool mlx5e_mqprio_rate_limit(u8 num_tc, u64 max_rate[])
3568 for (tc = 0; tc < num_tc; tc++)
3574 static struct mlx5e_mqprio_rl *mlx5e_mqprio_rl_create(struct mlx5_core_dev *mdev,
3575 u8 num_tc, u64 max_rate[])
3577 struct mlx5e_mqprio_rl *rl;
3580 if (!mlx5e_mqprio_rate_limit(num_tc, max_rate))
3583 rl = mlx5e_mqprio_rl_alloc();
3585 return ERR_PTR(-ENOMEM);
3587 err = mlx5e_mqprio_rl_init(rl, mdev, num_tc, max_rate);
3589 mlx5e_mqprio_rl_free(rl);
3590 return ERR_PTR(err);
3596 static int mlx5e_setup_tc_mqprio_channel(struct mlx5e_priv *priv,
3597 struct tc_mqprio_qopt_offload *mqprio)
3599 mlx5e_fp_preactivate preactivate;
3600 struct mlx5e_params new_params;
3601 struct mlx5e_mqprio_rl *rl;
3605 err = mlx5e_mqprio_channel_validate(priv, mqprio);
3609 rl = mlx5e_mqprio_rl_create(priv->mdev, mqprio->qopt.num_tc, mqprio->max_rate);
3613 new_params = priv->channels.params;
3614 mlx5e_params_mqprio_channel_set(&new_params, mqprio, rl);
3616 nch_changed = mlx5e_get_dcb_num_tc(&priv->channels.params) > 1;
3617 preactivate = nch_changed ? mlx5e_num_channels_changed_ctx :
3618 mlx5e_update_netdev_queues_ctx;
3619 err = mlx5e_safe_switch_params(priv, &new_params, preactivate, NULL, true);
3622 mlx5e_mqprio_rl_cleanup(rl);
3623 mlx5e_mqprio_rl_free(rl);
3628 if (priv->mqprio_rl) {
3629 mlx5e_mqprio_rl_cleanup(priv->mqprio_rl);
3630 mlx5e_mqprio_rl_free(priv->mqprio_rl);
3632 priv->mqprio_rl = rl;
3637 static int mlx5e_setup_tc_mqprio(struct mlx5e_priv *priv,
3638 struct tc_mqprio_qopt_offload *mqprio)
3640 /* MQPRIO is another toplevel qdisc that can't be attached
3641 * simultaneously with the offloaded HTB.
3643 if (WARN_ON(mlx5e_selq_is_htb_enabled(&priv->selq)))
3646 switch (mqprio->mode) {
3647 case TC_MQPRIO_MODE_DCB:
3648 return mlx5e_setup_tc_mqprio_dcb(priv, &mqprio->qopt);
3649 case TC_MQPRIO_MODE_CHANNEL:
3650 return mlx5e_setup_tc_mqprio_channel(priv, mqprio);
3656 static LIST_HEAD(mlx5e_block_cb_list);
3658 static int mlx5e_setup_tc(struct net_device *dev, enum tc_setup_type type,
3661 struct mlx5e_priv *priv = netdev_priv(dev);
3662 bool tc_unbind = false;
3665 if (type == TC_SETUP_BLOCK &&
3666 ((struct flow_block_offload *)type_data)->command == FLOW_BLOCK_UNBIND)
3669 if (!netif_device_present(dev) && !tc_unbind)
3673 case TC_SETUP_BLOCK: {
3674 struct flow_block_offload *f = type_data;
3676 f->unlocked_driver_cb = true;
3677 return flow_block_cb_setup_simple(type_data,
3678 &mlx5e_block_cb_list,
3679 mlx5e_setup_tc_block_cb,
3682 case TC_SETUP_QDISC_MQPRIO:
3683 mutex_lock(&priv->state_lock);
3684 err = mlx5e_setup_tc_mqprio(priv, type_data);
3685 mutex_unlock(&priv->state_lock);
3687 case TC_SETUP_QDISC_HTB:
3688 mutex_lock(&priv->state_lock);
3689 err = mlx5e_htb_setup_tc(priv, type_data);
3690 mutex_unlock(&priv->state_lock);
3697 void mlx5e_fold_sw_stats64(struct mlx5e_priv *priv, struct rtnl_link_stats64 *s)
3701 for (i = 0; i < priv->stats_nch; i++) {
3702 struct mlx5e_channel_stats *channel_stats = priv->channel_stats[i];
3703 struct mlx5e_rq_stats *xskrq_stats = &channel_stats->xskrq;
3704 struct mlx5e_rq_stats *rq_stats = &channel_stats->rq;
3707 s->rx_packets += rq_stats->packets + xskrq_stats->packets;
3708 s->rx_bytes += rq_stats->bytes + xskrq_stats->bytes;
3709 s->multicast += rq_stats->mcast_packets + xskrq_stats->mcast_packets;
3711 for (j = 0; j < priv->max_opened_tc; j++) {
3712 struct mlx5e_sq_stats *sq_stats = &channel_stats->sq[j];
3714 s->tx_packets += sq_stats->packets;
3715 s->tx_bytes += sq_stats->bytes;
3716 s->tx_dropped += sq_stats->dropped;
3719 if (priv->tx_ptp_opened) {
3720 for (i = 0; i < priv->max_opened_tc; i++) {
3721 struct mlx5e_sq_stats *sq_stats = &priv->ptp_stats.sq[i];
3723 s->tx_packets += sq_stats->packets;
3724 s->tx_bytes += sq_stats->bytes;
3725 s->tx_dropped += sq_stats->dropped;
3728 if (priv->rx_ptp_opened) {
3729 struct mlx5e_rq_stats *rq_stats = &priv->ptp_stats.rq;
3731 s->rx_packets += rq_stats->packets;
3732 s->rx_bytes += rq_stats->bytes;
3733 s->multicast += rq_stats->mcast_packets;
3738 mlx5e_get_stats(struct net_device *dev, struct rtnl_link_stats64 *stats)
3740 struct mlx5e_priv *priv = netdev_priv(dev);
3741 struct mlx5e_pport_stats *pstats = &priv->stats.pport;
3743 if (!netif_device_present(dev))
3746 /* In switchdev mode, monitor counters doesn't monitor
3747 * rx/tx stats of 802_3. The update stats mechanism
3748 * should keep the 802_3 layout counters updated
3750 if (!mlx5e_monitor_counter_supported(priv) ||
3751 mlx5e_is_uplink_rep(priv)) {
3752 /* update HW stats in background for next time */
3753 mlx5e_queue_update_stats(priv);
3756 if (mlx5e_is_uplink_rep(priv)) {
3757 struct mlx5e_vport_stats *vstats = &priv->stats.vport;
3759 stats->rx_packets = PPORT_802_3_GET(pstats, a_frames_received_ok);
3760 stats->rx_bytes = PPORT_802_3_GET(pstats, a_octets_received_ok);
3761 stats->tx_packets = PPORT_802_3_GET(pstats, a_frames_transmitted_ok);
3762 stats->tx_bytes = PPORT_802_3_GET(pstats, a_octets_transmitted_ok);
3764 /* vport multicast also counts packets that are dropped due to steering
3765 * or rx out of buffer
3767 stats->multicast = VPORT_COUNTER_GET(vstats, received_eth_multicast.packets);
3769 mlx5e_fold_sw_stats64(priv, stats);
3772 stats->rx_dropped = priv->stats.qcnt.rx_out_of_buffer;
3774 stats->rx_length_errors =
3775 PPORT_802_3_GET(pstats, a_in_range_length_errors) +
3776 PPORT_802_3_GET(pstats, a_out_of_range_length_field) +
3777 PPORT_802_3_GET(pstats, a_frame_too_long_errors) +
3778 VNIC_ENV_GET(&priv->stats.vnic, eth_wqe_too_small);
3779 stats->rx_crc_errors =
3780 PPORT_802_3_GET(pstats, a_frame_check_sequence_errors);
3781 stats->rx_frame_errors = PPORT_802_3_GET(pstats, a_alignment_errors);
3782 stats->tx_aborted_errors = PPORT_2863_GET(pstats, if_out_discards);
3783 stats->rx_errors = stats->rx_length_errors + stats->rx_crc_errors +
3784 stats->rx_frame_errors;
3785 stats->tx_errors = stats->tx_aborted_errors + stats->tx_carrier_errors;
3788 static void mlx5e_nic_set_rx_mode(struct mlx5e_priv *priv)
3790 if (mlx5e_is_uplink_rep(priv))
3791 return; /* no rx mode for uplink rep */
3793 queue_work(priv->wq, &priv->set_rx_mode_work);
3796 static void mlx5e_set_rx_mode(struct net_device *dev)
3798 struct mlx5e_priv *priv = netdev_priv(dev);
3800 mlx5e_nic_set_rx_mode(priv);
3803 static int mlx5e_set_mac(struct net_device *netdev, void *addr)
3805 struct mlx5e_priv *priv = netdev_priv(netdev);
3806 struct sockaddr *saddr = addr;
3808 if (!is_valid_ether_addr(saddr->sa_data))
3809 return -EADDRNOTAVAIL;
3811 netif_addr_lock_bh(netdev);
3812 eth_hw_addr_set(netdev, saddr->sa_data);
3813 netif_addr_unlock_bh(netdev);
3815 mlx5e_nic_set_rx_mode(priv);
3820 #define MLX5E_SET_FEATURE(features, feature, enable) \
3823 *features |= feature; \
3825 *features &= ~feature; \
3828 typedef int (*mlx5e_feature_handler)(struct net_device *netdev, bool enable);
3830 static int set_feature_lro(struct net_device *netdev, bool enable)
3832 struct mlx5e_priv *priv = netdev_priv(netdev);
3833 struct mlx5_core_dev *mdev = priv->mdev;
3834 struct mlx5e_params *cur_params;
3835 struct mlx5e_params new_params;
3839 mutex_lock(&priv->state_lock);
3841 cur_params = &priv->channels.params;
3842 new_params = *cur_params;
3845 new_params.packet_merge.type = MLX5E_PACKET_MERGE_LRO;
3846 else if (new_params.packet_merge.type == MLX5E_PACKET_MERGE_LRO)
3847 new_params.packet_merge.type = MLX5E_PACKET_MERGE_NONE;
3851 if (!(cur_params->packet_merge.type == MLX5E_PACKET_MERGE_SHAMPO &&
3852 new_params.packet_merge.type == MLX5E_PACKET_MERGE_LRO)) {
3853 if (cur_params->rq_wq_type == MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ) {
3854 if (mlx5e_rx_mpwqe_is_linear_skb(mdev, cur_params, NULL) ==
3855 mlx5e_rx_mpwqe_is_linear_skb(mdev, &new_params, NULL))
3860 err = mlx5e_safe_switch_params(priv, &new_params,
3861 mlx5e_modify_tirs_packet_merge_ctx, NULL, reset);
3863 mutex_unlock(&priv->state_lock);
3867 static int set_feature_hw_gro(struct net_device *netdev, bool enable)
3869 struct mlx5e_priv *priv = netdev_priv(netdev);
3870 struct mlx5e_params new_params;
3874 mutex_lock(&priv->state_lock);
3875 new_params = priv->channels.params;
3878 new_params.packet_merge.type = MLX5E_PACKET_MERGE_SHAMPO;
3879 new_params.packet_merge.shampo.match_criteria_type =
3880 MLX5_RQC_SHAMPO_MATCH_CRITERIA_TYPE_EXTENDED;
3881 new_params.packet_merge.shampo.alignment_granularity =
3882 MLX5_RQC_SHAMPO_NO_MATCH_ALIGNMENT_GRANULARITY_STRIDE;
3883 } else if (new_params.packet_merge.type == MLX5E_PACKET_MERGE_SHAMPO) {
3884 new_params.packet_merge.type = MLX5E_PACKET_MERGE_NONE;
3889 err = mlx5e_safe_switch_params(priv, &new_params, NULL, NULL, reset);
3891 mutex_unlock(&priv->state_lock);
3895 static int set_feature_cvlan_filter(struct net_device *netdev, bool enable)
3897 struct mlx5e_priv *priv = netdev_priv(netdev);
3900 mlx5e_enable_cvlan_filter(priv->fs,
3901 !!(priv->netdev->flags & IFF_PROMISC));
3903 mlx5e_disable_cvlan_filter(priv->fs,
3904 !!(priv->netdev->flags & IFF_PROMISC));
3909 static int set_feature_hw_tc(struct net_device *netdev, bool enable)
3911 struct mlx5e_priv *priv = netdev_priv(netdev);
3914 #if IS_ENABLED(CONFIG_MLX5_CLS_ACT)
3915 int tc_flag = mlx5e_is_uplink_rep(priv) ? MLX5_TC_FLAG(ESW_OFFLOAD) :
3916 MLX5_TC_FLAG(NIC_OFFLOAD);
3917 if (!enable && mlx5e_tc_num_filters(priv, tc_flag)) {
3919 "Active offloaded tc filters, can't turn hw_tc_offload off\n");
3924 mutex_lock(&priv->state_lock);
3925 if (!enable && mlx5e_selq_is_htb_enabled(&priv->selq)) {
3926 netdev_err(netdev, "Active HTB offload, can't turn hw_tc_offload off\n");
3929 mutex_unlock(&priv->state_lock);
3934 static int set_feature_rx_all(struct net_device *netdev, bool enable)
3936 struct mlx5e_priv *priv = netdev_priv(netdev);
3937 struct mlx5_core_dev *mdev = priv->mdev;
3939 return mlx5_set_port_fcs(mdev, !enable);
3942 static int mlx5e_set_rx_port_ts(struct mlx5_core_dev *mdev, bool enable)
3944 u32 in[MLX5_ST_SZ_DW(pcmr_reg)] = {};
3945 bool supported, curr_state;
3948 if (!MLX5_CAP_GEN(mdev, ports_check))
3951 err = mlx5_query_ports_check(mdev, in, sizeof(in));
3955 supported = MLX5_GET(pcmr_reg, in, rx_ts_over_crc_cap);
3956 curr_state = MLX5_GET(pcmr_reg, in, rx_ts_over_crc);
3958 if (!supported || enable == curr_state)
3961 MLX5_SET(pcmr_reg, in, local_port, 1);
3962 MLX5_SET(pcmr_reg, in, rx_ts_over_crc, enable);
3964 return mlx5_set_ports_check(mdev, in, sizeof(in));
3967 static int mlx5e_set_rx_port_ts_wrap(struct mlx5e_priv *priv, void *ctx)
3969 struct mlx5_core_dev *mdev = priv->mdev;
3970 bool enable = *(bool *)ctx;
3972 return mlx5e_set_rx_port_ts(mdev, enable);
3975 static int set_feature_rx_fcs(struct net_device *netdev, bool enable)
3977 struct mlx5e_priv *priv = netdev_priv(netdev);
3978 struct mlx5e_channels *chs = &priv->channels;
3979 struct mlx5e_params new_params;
3981 bool rx_ts_over_crc = !enable;
3983 mutex_lock(&priv->state_lock);
3985 new_params = chs->params;
3986 new_params.scatter_fcs_en = enable;
3987 err = mlx5e_safe_switch_params(priv, &new_params, mlx5e_set_rx_port_ts_wrap,
3988 &rx_ts_over_crc, true);
3989 mutex_unlock(&priv->state_lock);
3993 static int set_feature_rx_vlan(struct net_device *netdev, bool enable)
3995 struct mlx5e_priv *priv = netdev_priv(netdev);
3998 mutex_lock(&priv->state_lock);
4000 mlx5e_fs_set_vlan_strip_disable(priv->fs, !enable);
4001 priv->channels.params.vlan_strip_disable = !enable;
4003 if (!test_bit(MLX5E_STATE_OPENED, &priv->state))
4006 err = mlx5e_modify_channels_vsd(&priv->channels, !enable);
4008 mlx5e_fs_set_vlan_strip_disable(priv->fs, enable);
4009 priv->channels.params.vlan_strip_disable = enable;
4012 mutex_unlock(&priv->state_lock);
4017 int mlx5e_vlan_rx_add_vid(struct net_device *dev, __be16 proto, u16 vid)
4019 struct mlx5e_priv *priv = netdev_priv(dev);
4020 struct mlx5e_flow_steering *fs = priv->fs;
4022 if (mlx5e_is_uplink_rep(priv))
4023 return 0; /* no vlan table for uplink rep */
4025 return mlx5e_fs_vlan_rx_add_vid(fs, dev, proto, vid);
4028 int mlx5e_vlan_rx_kill_vid(struct net_device *dev, __be16 proto, u16 vid)
4030 struct mlx5e_priv *priv = netdev_priv(dev);
4031 struct mlx5e_flow_steering *fs = priv->fs;
4033 if (mlx5e_is_uplink_rep(priv))
4034 return 0; /* no vlan table for uplink rep */
4036 return mlx5e_fs_vlan_rx_kill_vid(fs, dev, proto, vid);
4039 #ifdef CONFIG_MLX5_EN_ARFS
4040 static int set_feature_arfs(struct net_device *netdev, bool enable)
4042 struct mlx5e_priv *priv = netdev_priv(netdev);
4046 err = mlx5e_arfs_enable(priv->fs);
4048 err = mlx5e_arfs_disable(priv->fs);
4054 static int mlx5e_handle_feature(struct net_device *netdev,
4055 netdev_features_t *features,
4056 netdev_features_t feature,
4057 mlx5e_feature_handler feature_handler)
4059 netdev_features_t changes = *features ^ netdev->features;
4060 bool enable = !!(*features & feature);
4063 if (!(changes & feature))
4066 err = feature_handler(netdev, enable);
4068 MLX5E_SET_FEATURE(features, feature, !enable);
4069 netdev_err(netdev, "%s feature %pNF failed, err %d\n",
4070 enable ? "Enable" : "Disable", &feature, err);
4077 void mlx5e_set_xdp_feature(struct net_device *netdev)
4079 struct mlx5e_priv *priv = netdev_priv(netdev);
4080 struct mlx5e_params *params = &priv->channels.params;
4083 if (params->packet_merge.type != MLX5E_PACKET_MERGE_NONE) {
4084 xdp_clear_features_flag(netdev);
4088 val = NETDEV_XDP_ACT_BASIC | NETDEV_XDP_ACT_REDIRECT |
4089 NETDEV_XDP_ACT_XSK_ZEROCOPY |
4090 NETDEV_XDP_ACT_RX_SG |
4091 NETDEV_XDP_ACT_NDO_XMIT |
4092 NETDEV_XDP_ACT_NDO_XMIT_SG;
4093 xdp_set_features_flag(netdev, val);
4096 int mlx5e_set_features(struct net_device *netdev, netdev_features_t features)
4098 netdev_features_t oper_features = features;
4101 #define MLX5E_HANDLE_FEATURE(feature, handler) \
4102 mlx5e_handle_feature(netdev, &oper_features, feature, handler)
4104 err |= MLX5E_HANDLE_FEATURE(NETIF_F_LRO, set_feature_lro);
4105 err |= MLX5E_HANDLE_FEATURE(NETIF_F_GRO_HW, set_feature_hw_gro);
4106 err |= MLX5E_HANDLE_FEATURE(NETIF_F_HW_VLAN_CTAG_FILTER,
4107 set_feature_cvlan_filter);
4108 err |= MLX5E_HANDLE_FEATURE(NETIF_F_HW_TC, set_feature_hw_tc);
4109 err |= MLX5E_HANDLE_FEATURE(NETIF_F_RXALL, set_feature_rx_all);
4110 err |= MLX5E_HANDLE_FEATURE(NETIF_F_RXFCS, set_feature_rx_fcs);
4111 err |= MLX5E_HANDLE_FEATURE(NETIF_F_HW_VLAN_CTAG_RX, set_feature_rx_vlan);
4112 #ifdef CONFIG_MLX5_EN_ARFS
4113 err |= MLX5E_HANDLE_FEATURE(NETIF_F_NTUPLE, set_feature_arfs);
4115 err |= MLX5E_HANDLE_FEATURE(NETIF_F_HW_TLS_RX, mlx5e_ktls_set_feature_rx);
4118 netdev->features = oper_features;
4122 /* update XDP supported features */
4123 mlx5e_set_xdp_feature(netdev);
4128 static netdev_features_t mlx5e_fix_uplink_rep_features(struct net_device *netdev,
4129 netdev_features_t features)
4131 features &= ~NETIF_F_HW_TLS_RX;
4132 if (netdev->features & NETIF_F_HW_TLS_RX)
4133 netdev_warn(netdev, "Disabling hw_tls_rx, not supported in switchdev mode\n");
4135 features &= ~NETIF_F_HW_TLS_TX;
4136 if (netdev->features & NETIF_F_HW_TLS_TX)
4137 netdev_warn(netdev, "Disabling hw_tls_tx, not supported in switchdev mode\n");
4139 features &= ~NETIF_F_NTUPLE;
4140 if (netdev->features & NETIF_F_NTUPLE)
4141 netdev_warn(netdev, "Disabling ntuple, not supported in switchdev mode\n");
4143 features &= ~NETIF_F_GRO_HW;
4144 if (netdev->features & NETIF_F_GRO_HW)
4145 netdev_warn(netdev, "Disabling HW_GRO, not supported in switchdev mode\n");
4147 features &= ~NETIF_F_HW_VLAN_CTAG_FILTER;
4148 if (netdev->features & NETIF_F_HW_VLAN_CTAG_FILTER)
4149 netdev_warn(netdev, "Disabling HW_VLAN CTAG FILTERING, not supported in switchdev mode\n");
4154 static netdev_features_t mlx5e_fix_features(struct net_device *netdev,
4155 netdev_features_t features)
4157 struct mlx5e_priv *priv = netdev_priv(netdev);
4158 struct mlx5e_vlan_table *vlan;
4159 struct mlx5e_params *params;
4161 if (!netif_device_present(netdev))
4164 vlan = mlx5e_fs_get_vlan(priv->fs);
4165 mutex_lock(&priv->state_lock);
4166 params = &priv->channels.params;
4168 !bitmap_empty(mlx5e_vlan_get_active_svlans(vlan), VLAN_N_VID)) {
4169 /* HW strips the outer C-tag header, this is a problem
4170 * for S-tag traffic.
4172 features &= ~NETIF_F_HW_VLAN_CTAG_RX;
4173 if (!params->vlan_strip_disable)
4174 netdev_warn(netdev, "Dropping C-tag vlan stripping offload due to S-tag vlan\n");
4177 if (!MLX5E_GET_PFLAG(params, MLX5E_PFLAG_RX_STRIDING_RQ)) {
4178 if (features & NETIF_F_LRO) {
4179 netdev_warn(netdev, "Disabling LRO, not supported in legacy RQ\n");
4180 features &= ~NETIF_F_LRO;
4182 if (features & NETIF_F_GRO_HW) {
4183 netdev_warn(netdev, "Disabling HW-GRO, not supported in legacy RQ\n");
4184 features &= ~NETIF_F_GRO_HW;
4188 if (params->xdp_prog) {
4189 if (features & NETIF_F_LRO) {
4190 netdev_warn(netdev, "LRO is incompatible with XDP\n");
4191 features &= ~NETIF_F_LRO;
4193 if (features & NETIF_F_GRO_HW) {
4194 netdev_warn(netdev, "HW GRO is incompatible with XDP\n");
4195 features &= ~NETIF_F_GRO_HW;
4199 if (priv->xsk.refcnt) {
4200 if (features & NETIF_F_LRO) {
4201 netdev_warn(netdev, "LRO is incompatible with AF_XDP (%u XSKs are active)\n",
4203 features &= ~NETIF_F_LRO;
4205 if (features & NETIF_F_GRO_HW) {
4206 netdev_warn(netdev, "HW GRO is incompatible with AF_XDP (%u XSKs are active)\n",
4208 features &= ~NETIF_F_GRO_HW;
4212 if (MLX5E_GET_PFLAG(params, MLX5E_PFLAG_RX_CQE_COMPRESS)) {
4213 features &= ~NETIF_F_RXHASH;
4214 if (netdev->features & NETIF_F_RXHASH)
4215 netdev_warn(netdev, "Disabling rxhash, not supported when CQE compress is active\n");
4217 if (features & NETIF_F_GRO_HW) {
4218 netdev_warn(netdev, "Disabling HW-GRO, not supported when CQE compress is active\n");
4219 features &= ~NETIF_F_GRO_HW;
4223 if (mlx5e_is_uplink_rep(priv)) {
4224 features = mlx5e_fix_uplink_rep_features(netdev, features);
4225 features |= NETIF_F_NETNS_LOCAL;
4227 features &= ~NETIF_F_NETNS_LOCAL;
4230 mutex_unlock(&priv->state_lock);
4235 static bool mlx5e_xsk_validate_mtu(struct net_device *netdev,
4236 struct mlx5e_channels *chs,
4237 struct mlx5e_params *new_params,
4238 struct mlx5_core_dev *mdev)
4242 for (ix = 0; ix < chs->params.num_channels; ix++) {
4243 struct xsk_buff_pool *xsk_pool =
4244 mlx5e_xsk_get_pool(&chs->params, chs->params.xsk, ix);
4245 struct mlx5e_xsk_param xsk;
4251 mlx5e_build_xsk_param(xsk_pool, &xsk);
4252 max_xdp_mtu = mlx5e_xdp_max_mtu(new_params, &xsk);
4254 /* Validate XSK params and XDP MTU in advance */
4255 if (!mlx5e_validate_xsk_param(new_params, &xsk, mdev) ||
4256 new_params->sw_mtu > max_xdp_mtu) {
4257 u32 hr = mlx5e_get_linear_rq_headroom(new_params, &xsk);
4258 int max_mtu_frame, max_mtu_page, max_mtu;
4260 /* Two criteria must be met:
4261 * 1. HW MTU + all headrooms <= XSK frame size.
4262 * 2. Size of SKBs allocated on XDP_PASS <= PAGE_SIZE.
4264 max_mtu_frame = MLX5E_HW2SW_MTU(new_params, xsk.chunk_size - hr);
4265 max_mtu_page = MLX5E_HW2SW_MTU(new_params, SKB_MAX_HEAD(0));
4266 max_mtu = min3(max_mtu_frame, max_mtu_page, max_xdp_mtu);
4268 netdev_err(netdev, "MTU %d is too big for an XSK running on channel %u or its redirection XDP program. Try MTU <= %d\n",
4269 new_params->sw_mtu, ix, max_mtu);
4277 static bool mlx5e_params_validate_xdp(struct net_device *netdev,
4278 struct mlx5_core_dev *mdev,
4279 struct mlx5e_params *params)
4283 /* No XSK params: AF_XDP can't be enabled yet at the point of setting
4286 is_linear = params->rq_wq_type == MLX5_WQ_TYPE_CYCLIC ?
4287 mlx5e_rx_is_linear_skb(mdev, params, NULL) :
4288 mlx5e_rx_mpwqe_is_linear_skb(mdev, params, NULL);
4291 if (!params->xdp_prog->aux->xdp_has_frags) {
4292 netdev_warn(netdev, "MTU(%d) > %d, too big for an XDP program not aware of multi buffer\n",
4294 mlx5e_xdp_max_mtu(params, NULL));
4297 if (params->rq_wq_type == MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ &&
4298 !mlx5e_verify_params_rx_mpwqe_strides(mdev, params, NULL)) {
4299 netdev_warn(netdev, "XDP is not allowed with striding RQ and MTU(%d) > %d\n",
4301 mlx5e_xdp_max_mtu(params, NULL));
4309 int mlx5e_change_mtu(struct net_device *netdev, int new_mtu,
4310 mlx5e_fp_preactivate preactivate)
4312 struct mlx5e_priv *priv = netdev_priv(netdev);
4313 struct mlx5e_params new_params;
4314 struct mlx5e_params *params;
4318 mutex_lock(&priv->state_lock);
4320 params = &priv->channels.params;
4322 new_params = *params;
4323 new_params.sw_mtu = new_mtu;
4324 err = mlx5e_validate_params(priv->mdev, &new_params);
4328 if (new_params.xdp_prog && !mlx5e_params_validate_xdp(netdev, priv->mdev,
4334 if (priv->xsk.refcnt &&
4335 !mlx5e_xsk_validate_mtu(netdev, &priv->channels,
4336 &new_params, priv->mdev)) {
4341 if (params->packet_merge.type == MLX5E_PACKET_MERGE_LRO)
4344 if (params->rq_wq_type == MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ &&
4345 params->packet_merge.type != MLX5E_PACKET_MERGE_SHAMPO) {
4346 bool is_linear_old = mlx5e_rx_mpwqe_is_linear_skb(priv->mdev, params, NULL);
4347 bool is_linear_new = mlx5e_rx_mpwqe_is_linear_skb(priv->mdev,
4349 u8 sz_old = mlx5e_mpwqe_get_log_rq_size(priv->mdev, params, NULL);
4350 u8 sz_new = mlx5e_mpwqe_get_log_rq_size(priv->mdev, &new_params, NULL);
4352 /* Always reset in linear mode - hw_mtu is used in data path.
4353 * Check that the mode was non-linear and didn't change.
4354 * If XSK is active, XSK RQs are linear.
4355 * Reset if the RQ size changed, even if it's non-linear.
4357 if (!is_linear_old && !is_linear_new && !priv->xsk.refcnt &&
4362 err = mlx5e_safe_switch_params(priv, &new_params, preactivate, NULL, reset);
4365 netdev->mtu = params->sw_mtu;
4366 mutex_unlock(&priv->state_lock);
4370 static int mlx5e_change_nic_mtu(struct net_device *netdev, int new_mtu)
4372 return mlx5e_change_mtu(netdev, new_mtu, mlx5e_set_dev_port_mtu_ctx);
4375 int mlx5e_ptp_rx_manage_fs_ctx(struct mlx5e_priv *priv, void *ctx)
4377 bool set = *(bool *)ctx;
4379 return mlx5e_ptp_rx_manage_fs(priv, set);
4382 static int mlx5e_hwstamp_config_no_ptp_rx(struct mlx5e_priv *priv, bool rx_filter)
4384 bool rx_cqe_compress_def = priv->channels.params.rx_cqe_compress_def;
4388 /* Reset CQE compression to Admin default */
4389 return mlx5e_modify_rx_cqe_compression_locked(priv, rx_cqe_compress_def, false);
4391 if (!MLX5E_GET_PFLAG(&priv->channels.params, MLX5E_PFLAG_RX_CQE_COMPRESS))
4394 /* Disable CQE compression */
4395 netdev_warn(priv->netdev, "Disabling RX cqe compression\n");
4396 err = mlx5e_modify_rx_cqe_compression_locked(priv, false, true);
4398 netdev_err(priv->netdev, "Failed disabling cqe compression err=%d\n", err);
4403 static int mlx5e_hwstamp_config_ptp_rx(struct mlx5e_priv *priv, bool ptp_rx)
4405 struct mlx5e_params new_params;
4407 if (ptp_rx == priv->channels.params.ptp_rx)
4410 new_params = priv->channels.params;
4411 new_params.ptp_rx = ptp_rx;
4412 return mlx5e_safe_switch_params(priv, &new_params, mlx5e_ptp_rx_manage_fs_ctx,
4413 &new_params.ptp_rx, true);
4416 int mlx5e_hwstamp_set(struct mlx5e_priv *priv, struct ifreq *ifr)
4418 struct hwtstamp_config config;
4419 bool rx_cqe_compress_def;
4423 if (!MLX5_CAP_GEN(priv->mdev, device_frequency_khz) ||
4424 (mlx5_clock_get_ptp_index(priv->mdev) == -1))
4427 if (copy_from_user(&config, ifr->ifr_data, sizeof(config)))
4430 /* TX HW timestamp */
4431 switch (config.tx_type) {
4432 case HWTSTAMP_TX_OFF:
4433 case HWTSTAMP_TX_ON:
4439 mutex_lock(&priv->state_lock);
4440 rx_cqe_compress_def = priv->channels.params.rx_cqe_compress_def;
4442 /* RX HW timestamp */
4443 switch (config.rx_filter) {
4444 case HWTSTAMP_FILTER_NONE:
4447 case HWTSTAMP_FILTER_ALL:
4448 case HWTSTAMP_FILTER_SOME:
4449 case HWTSTAMP_FILTER_PTP_V1_L4_EVENT:
4450 case HWTSTAMP_FILTER_PTP_V1_L4_SYNC:
4451 case HWTSTAMP_FILTER_PTP_V1_L4_DELAY_REQ:
4452 case HWTSTAMP_FILTER_PTP_V2_L4_EVENT:
4453 case HWTSTAMP_FILTER_PTP_V2_L4_SYNC:
4454 case HWTSTAMP_FILTER_PTP_V2_L4_DELAY_REQ:
4455 case HWTSTAMP_FILTER_PTP_V2_L2_EVENT:
4456 case HWTSTAMP_FILTER_PTP_V2_L2_SYNC:
4457 case HWTSTAMP_FILTER_PTP_V2_L2_DELAY_REQ:
4458 case HWTSTAMP_FILTER_PTP_V2_EVENT:
4459 case HWTSTAMP_FILTER_PTP_V2_SYNC:
4460 case HWTSTAMP_FILTER_PTP_V2_DELAY_REQ:
4461 case HWTSTAMP_FILTER_NTP_ALL:
4462 config.rx_filter = HWTSTAMP_FILTER_ALL;
4463 /* ptp_rx is set if both HW TS is set and CQE
4464 * compression is set
4466 ptp_rx = rx_cqe_compress_def;
4473 if (!mlx5e_profile_feature_cap(priv->profile, PTP_RX))
4474 err = mlx5e_hwstamp_config_no_ptp_rx(priv,
4475 config.rx_filter != HWTSTAMP_FILTER_NONE);
4477 err = mlx5e_hwstamp_config_ptp_rx(priv, ptp_rx);
4481 memcpy(&priv->tstamp, &config, sizeof(config));
4482 mutex_unlock(&priv->state_lock);
4484 /* might need to fix some features */
4485 netdev_update_features(priv->netdev);
4487 return copy_to_user(ifr->ifr_data, &config,
4488 sizeof(config)) ? -EFAULT : 0;
4490 mutex_unlock(&priv->state_lock);
4494 int mlx5e_hwstamp_get(struct mlx5e_priv *priv, struct ifreq *ifr)
4496 struct hwtstamp_config *cfg = &priv->tstamp;
4498 if (!MLX5_CAP_GEN(priv->mdev, device_frequency_khz))
4501 return copy_to_user(ifr->ifr_data, cfg, sizeof(*cfg)) ? -EFAULT : 0;
4504 static int mlx5e_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
4506 struct mlx5e_priv *priv = netdev_priv(dev);
4510 return mlx5e_hwstamp_set(priv, ifr);
4512 return mlx5e_hwstamp_get(priv, ifr);
4518 #ifdef CONFIG_MLX5_ESWITCH
4519 int mlx5e_set_vf_mac(struct net_device *dev, int vf, u8 *mac)
4521 struct mlx5e_priv *priv = netdev_priv(dev);
4522 struct mlx5_core_dev *mdev = priv->mdev;
4524 return mlx5_eswitch_set_vport_mac(mdev->priv.eswitch, vf + 1, mac);
4527 static int mlx5e_set_vf_vlan(struct net_device *dev, int vf, u16 vlan, u8 qos,
4530 struct mlx5e_priv *priv = netdev_priv(dev);
4531 struct mlx5_core_dev *mdev = priv->mdev;
4533 if (vlan_proto != htons(ETH_P_8021Q))
4534 return -EPROTONOSUPPORT;
4536 return mlx5_eswitch_set_vport_vlan(mdev->priv.eswitch, vf + 1,
4540 static int mlx5e_set_vf_spoofchk(struct net_device *dev, int vf, bool setting)
4542 struct mlx5e_priv *priv = netdev_priv(dev);
4543 struct mlx5_core_dev *mdev = priv->mdev;
4545 return mlx5_eswitch_set_vport_spoofchk(mdev->priv.eswitch, vf + 1, setting);
4548 static int mlx5e_set_vf_trust(struct net_device *dev, int vf, bool setting)
4550 struct mlx5e_priv *priv = netdev_priv(dev);
4551 struct mlx5_core_dev *mdev = priv->mdev;
4553 return mlx5_eswitch_set_vport_trust(mdev->priv.eswitch, vf + 1, setting);
4556 int mlx5e_set_vf_rate(struct net_device *dev, int vf, int min_tx_rate,
4559 struct mlx5e_priv *priv = netdev_priv(dev);
4560 struct mlx5_core_dev *mdev = priv->mdev;
4562 return mlx5_eswitch_set_vport_rate(mdev->priv.eswitch, vf + 1,
4563 max_tx_rate, min_tx_rate);
4566 static int mlx5_vport_link2ifla(u8 esw_link)
4569 case MLX5_VPORT_ADMIN_STATE_DOWN:
4570 return IFLA_VF_LINK_STATE_DISABLE;
4571 case MLX5_VPORT_ADMIN_STATE_UP:
4572 return IFLA_VF_LINK_STATE_ENABLE;
4574 return IFLA_VF_LINK_STATE_AUTO;
4577 static int mlx5_ifla_link2vport(u8 ifla_link)
4579 switch (ifla_link) {
4580 case IFLA_VF_LINK_STATE_DISABLE:
4581 return MLX5_VPORT_ADMIN_STATE_DOWN;
4582 case IFLA_VF_LINK_STATE_ENABLE:
4583 return MLX5_VPORT_ADMIN_STATE_UP;
4585 return MLX5_VPORT_ADMIN_STATE_AUTO;
4588 static int mlx5e_set_vf_link_state(struct net_device *dev, int vf,
4591 struct mlx5e_priv *priv = netdev_priv(dev);
4592 struct mlx5_core_dev *mdev = priv->mdev;
4594 if (mlx5e_is_uplink_rep(priv))
4597 return mlx5_eswitch_set_vport_state(mdev->priv.eswitch, vf + 1,
4598 mlx5_ifla_link2vport(link_state));
4601 int mlx5e_get_vf_config(struct net_device *dev,
4602 int vf, struct ifla_vf_info *ivi)
4604 struct mlx5e_priv *priv = netdev_priv(dev);
4605 struct mlx5_core_dev *mdev = priv->mdev;
4608 if (!netif_device_present(dev))
4611 err = mlx5_eswitch_get_vport_config(mdev->priv.eswitch, vf + 1, ivi);
4614 ivi->linkstate = mlx5_vport_link2ifla(ivi->linkstate);
4618 int mlx5e_get_vf_stats(struct net_device *dev,
4619 int vf, struct ifla_vf_stats *vf_stats)
4621 struct mlx5e_priv *priv = netdev_priv(dev);
4622 struct mlx5_core_dev *mdev = priv->mdev;
4624 return mlx5_eswitch_get_vport_stats(mdev->priv.eswitch, vf + 1,
4629 mlx5e_has_offload_stats(const struct net_device *dev, int attr_id)
4631 struct mlx5e_priv *priv = netdev_priv(dev);
4633 if (!netif_device_present(dev))
4636 if (!mlx5e_is_uplink_rep(priv))
4639 return mlx5e_rep_has_offload_stats(dev, attr_id);
4643 mlx5e_get_offload_stats(int attr_id, const struct net_device *dev,
4646 struct mlx5e_priv *priv = netdev_priv(dev);
4648 if (!mlx5e_is_uplink_rep(priv))
4651 return mlx5e_rep_get_offload_stats(attr_id, dev, sp);
4655 static bool mlx5e_tunnel_proto_supported_tx(struct mlx5_core_dev *mdev, u8 proto_type)
4657 switch (proto_type) {
4659 return MLX5_CAP_ETH(mdev, tunnel_stateless_gre);
4662 return (MLX5_CAP_ETH(mdev, tunnel_stateless_ip_over_ip) ||
4663 MLX5_CAP_ETH(mdev, tunnel_stateless_ip_over_ip_tx));
4669 static bool mlx5e_gre_tunnel_inner_proto_offload_supported(struct mlx5_core_dev *mdev,
4670 struct sk_buff *skb)
4672 switch (skb->inner_protocol) {
4673 case htons(ETH_P_IP):
4674 case htons(ETH_P_IPV6):
4675 case htons(ETH_P_TEB):
4677 case htons(ETH_P_MPLS_UC):
4678 case htons(ETH_P_MPLS_MC):
4679 return MLX5_CAP_ETH(mdev, tunnel_stateless_mpls_over_gre);
4684 static netdev_features_t mlx5e_tunnel_features_check(struct mlx5e_priv *priv,
4685 struct sk_buff *skb,
4686 netdev_features_t features)
4688 unsigned int offset = 0;
4689 struct udphdr *udph;
4693 switch (vlan_get_protocol(skb)) {
4694 case htons(ETH_P_IP):
4695 proto = ip_hdr(skb)->protocol;
4697 case htons(ETH_P_IPV6):
4698 proto = ipv6_find_hdr(skb, &offset, -1, NULL, NULL);
4706 if (mlx5e_gre_tunnel_inner_proto_offload_supported(priv->mdev, skb))
4711 if (mlx5e_tunnel_proto_supported_tx(priv->mdev, IPPROTO_IPIP))
4715 udph = udp_hdr(skb);
4716 port = be16_to_cpu(udph->dest);
4718 /* Verify if UDP port is being offloaded by HW */
4719 if (mlx5_vxlan_lookup_port(priv->mdev->vxlan, port))
4722 #if IS_ENABLED(CONFIG_GENEVE)
4723 /* Support Geneve offload for default UDP port */
4724 if (port == GENEVE_UDP_PORT && mlx5_geneve_tx_allowed(priv->mdev))
4728 #ifdef CONFIG_MLX5_EN_IPSEC
4730 return mlx5e_ipsec_feature_check(skb, features);
4735 /* Disable CSUM and GSO if the udp dport is not offloaded by HW */
4736 return features & ~(NETIF_F_CSUM_MASK | NETIF_F_GSO_MASK);
4739 netdev_features_t mlx5e_features_check(struct sk_buff *skb,
4740 struct net_device *netdev,
4741 netdev_features_t features)
4743 struct mlx5e_priv *priv = netdev_priv(netdev);
4745 features = vlan_features_check(skb, features);
4746 features = vxlan_features_check(skb, features);
4748 /* Validate if the tunneled packet is being offloaded by HW */
4749 if (skb->encapsulation &&
4750 (features & NETIF_F_CSUM_MASK || features & NETIF_F_GSO_MASK))
4751 return mlx5e_tunnel_features_check(priv, skb, features);
4756 static void mlx5e_tx_timeout_work(struct work_struct *work)
4758 struct mlx5e_priv *priv = container_of(work, struct mlx5e_priv,
4760 struct net_device *netdev = priv->netdev;
4763 /* Take rtnl_lock to ensure no change in netdev->real_num_tx_queues
4764 * through this flow. However, channel closing flows have to wait for
4765 * this work to finish while holding rtnl lock too. So either get the
4766 * lock or find that channels are being closed for other reason and
4767 * this work is not relevant anymore.
4769 while (!rtnl_trylock()) {
4770 if (!test_bit(MLX5E_STATE_CHANNELS_ACTIVE, &priv->state))
4775 if (!test_bit(MLX5E_STATE_OPENED, &priv->state))
4778 for (i = 0; i < netdev->real_num_tx_queues; i++) {
4779 struct netdev_queue *dev_queue =
4780 netdev_get_tx_queue(netdev, i);
4781 struct mlx5e_txqsq *sq = priv->txq2sq[i];
4783 if (!netif_xmit_stopped(dev_queue))
4786 if (mlx5e_reporter_tx_timeout(sq))
4787 /* break if tried to reopened channels */
4795 static void mlx5e_tx_timeout(struct net_device *dev, unsigned int txqueue)
4797 struct mlx5e_priv *priv = netdev_priv(dev);
4799 netdev_err(dev, "TX timeout detected\n");
4800 queue_work(priv->wq, &priv->tx_timeout_work);
4803 static int mlx5e_xdp_allowed(struct net_device *netdev, struct mlx5_core_dev *mdev,
4804 struct mlx5e_params *params)
4806 if (params->packet_merge.type != MLX5E_PACKET_MERGE_NONE) {
4807 netdev_warn(netdev, "can't set XDP while HW-GRO/LRO is on, disable them first\n");
4811 if (!mlx5e_params_validate_xdp(netdev, mdev, params))
4817 static void mlx5e_rq_replace_xdp_prog(struct mlx5e_rq *rq, struct bpf_prog *prog)
4819 struct bpf_prog *old_prog;
4821 old_prog = rcu_replace_pointer(rq->xdp_prog, prog,
4822 lockdep_is_held(&rq->priv->state_lock));
4824 bpf_prog_put(old_prog);
4827 static int mlx5e_xdp_set(struct net_device *netdev, struct bpf_prog *prog)
4829 struct mlx5e_priv *priv = netdev_priv(netdev);
4830 struct mlx5e_params new_params;
4831 struct bpf_prog *old_prog;
4836 mutex_lock(&priv->state_lock);
4838 new_params = priv->channels.params;
4839 new_params.xdp_prog = prog;
4842 err = mlx5e_xdp_allowed(netdev, priv->mdev, &new_params);
4847 /* no need for full reset when exchanging programs */
4848 reset = (!priv->channels.params.xdp_prog || !prog);
4850 old_prog = priv->channels.params.xdp_prog;
4852 err = mlx5e_safe_switch_params(priv, &new_params, NULL, NULL, reset);
4857 bpf_prog_put(old_prog);
4859 if (!test_bit(MLX5E_STATE_OPENED, &priv->state) || reset)
4862 /* exchanging programs w/o reset, we update ref counts on behalf
4863 * of the channels RQs here.
4865 bpf_prog_add(prog, priv->channels.num);
4866 for (i = 0; i < priv->channels.num; i++) {
4867 struct mlx5e_channel *c = priv->channels.c[i];
4869 mlx5e_rq_replace_xdp_prog(&c->rq, prog);
4870 if (test_bit(MLX5E_CHANNEL_STATE_XSK, c->state)) {
4872 mlx5e_rq_replace_xdp_prog(&c->xskrq, prog);
4877 mutex_unlock(&priv->state_lock);
4879 /* Need to fix some features. */
4881 netdev_update_features(netdev);
4886 static int mlx5e_xdp(struct net_device *dev, struct netdev_bpf *xdp)
4888 switch (xdp->command) {
4889 case XDP_SETUP_PROG:
4890 return mlx5e_xdp_set(dev, xdp->prog);
4891 case XDP_SETUP_XSK_POOL:
4892 return mlx5e_xsk_setup_pool(dev, xdp->xsk.pool,
4899 #ifdef CONFIG_MLX5_ESWITCH
4900 static int mlx5e_bridge_getlink(struct sk_buff *skb, u32 pid, u32 seq,
4901 struct net_device *dev, u32 filter_mask,
4904 struct mlx5e_priv *priv = netdev_priv(dev);
4905 struct mlx5_core_dev *mdev = priv->mdev;
4909 err = mlx5_eswitch_get_vepa(mdev->priv.eswitch, &setting);
4912 mode = setting ? BRIDGE_MODE_VEPA : BRIDGE_MODE_VEB;
4913 return ndo_dflt_bridge_getlink(skb, pid, seq, dev,
4915 0, 0, nlflags, filter_mask, NULL);
4918 static int mlx5e_bridge_setlink(struct net_device *dev, struct nlmsghdr *nlh,
4919 u16 flags, struct netlink_ext_ack *extack)
4921 struct mlx5e_priv *priv = netdev_priv(dev);
4922 struct mlx5_core_dev *mdev = priv->mdev;
4923 struct nlattr *attr, *br_spec;
4924 u16 mode = BRIDGE_MODE_UNDEF;
4928 br_spec = nlmsg_find_attr(nlh, sizeof(struct ifinfomsg), IFLA_AF_SPEC);
4932 nla_for_each_nested(attr, br_spec, rem) {
4933 if (nla_type(attr) != IFLA_BRIDGE_MODE)
4936 mode = nla_get_u16(attr);
4937 if (mode > BRIDGE_MODE_VEPA)
4943 if (mode == BRIDGE_MODE_UNDEF)
4946 setting = (mode == BRIDGE_MODE_VEPA) ? 1 : 0;
4947 return mlx5_eswitch_set_vepa(mdev->priv.eswitch, setting);
4951 const struct net_device_ops mlx5e_netdev_ops = {
4952 .ndo_open = mlx5e_open,
4953 .ndo_stop = mlx5e_close,
4954 .ndo_start_xmit = mlx5e_xmit,
4955 .ndo_setup_tc = mlx5e_setup_tc,
4956 .ndo_select_queue = mlx5e_select_queue,
4957 .ndo_get_stats64 = mlx5e_get_stats,
4958 .ndo_set_rx_mode = mlx5e_set_rx_mode,
4959 .ndo_set_mac_address = mlx5e_set_mac,
4960 .ndo_vlan_rx_add_vid = mlx5e_vlan_rx_add_vid,
4961 .ndo_vlan_rx_kill_vid = mlx5e_vlan_rx_kill_vid,
4962 .ndo_set_features = mlx5e_set_features,
4963 .ndo_fix_features = mlx5e_fix_features,
4964 .ndo_change_mtu = mlx5e_change_nic_mtu,
4965 .ndo_eth_ioctl = mlx5e_ioctl,
4966 .ndo_set_tx_maxrate = mlx5e_set_tx_maxrate,
4967 .ndo_features_check = mlx5e_features_check,
4968 .ndo_tx_timeout = mlx5e_tx_timeout,
4969 .ndo_bpf = mlx5e_xdp,
4970 .ndo_xdp_xmit = mlx5e_xdp_xmit,
4971 .ndo_xsk_wakeup = mlx5e_xsk_wakeup,
4972 #ifdef CONFIG_MLX5_EN_ARFS
4973 .ndo_rx_flow_steer = mlx5e_rx_flow_steer,
4975 #ifdef CONFIG_MLX5_ESWITCH
4976 .ndo_bridge_setlink = mlx5e_bridge_setlink,
4977 .ndo_bridge_getlink = mlx5e_bridge_getlink,
4979 /* SRIOV E-Switch NDOs */
4980 .ndo_set_vf_mac = mlx5e_set_vf_mac,
4981 .ndo_set_vf_vlan = mlx5e_set_vf_vlan,
4982 .ndo_set_vf_spoofchk = mlx5e_set_vf_spoofchk,
4983 .ndo_set_vf_trust = mlx5e_set_vf_trust,
4984 .ndo_set_vf_rate = mlx5e_set_vf_rate,
4985 .ndo_get_vf_config = mlx5e_get_vf_config,
4986 .ndo_set_vf_link_state = mlx5e_set_vf_link_state,
4987 .ndo_get_vf_stats = mlx5e_get_vf_stats,
4988 .ndo_has_offload_stats = mlx5e_has_offload_stats,
4989 .ndo_get_offload_stats = mlx5e_get_offload_stats,
4993 static u32 mlx5e_choose_lro_timeout(struct mlx5_core_dev *mdev, u32 wanted_timeout)
4997 /* The supported periods are organized in ascending order */
4998 for (i = 0; i < MLX5E_LRO_TIMEOUT_ARR_SIZE - 1; i++)
4999 if (MLX5_CAP_ETH(mdev, lro_timer_supported_periods[i]) >= wanted_timeout)
5002 return MLX5_CAP_ETH(mdev, lro_timer_supported_periods[i]);
5005 void mlx5e_build_nic_params(struct mlx5e_priv *priv, struct mlx5e_xsk *xsk, u16 mtu)
5007 struct mlx5e_params *params = &priv->channels.params;
5008 struct mlx5_core_dev *mdev = priv->mdev;
5009 u8 rx_cq_period_mode;
5011 params->sw_mtu = mtu;
5012 params->hard_mtu = MLX5E_ETH_HARD_MTU;
5013 params->num_channels = min_t(unsigned int, MLX5E_MAX_NUM_CHANNELS / 2,
5015 mlx5e_params_mqprio_reset(params);
5018 params->log_sq_size = is_kdump_kernel() ?
5019 MLX5E_PARAMS_MINIMUM_LOG_SQ_SIZE :
5020 MLX5E_PARAMS_DEFAULT_LOG_SQ_SIZE;
5021 MLX5E_SET_PFLAG(params, MLX5E_PFLAG_SKB_TX_MPWQE, mlx5e_tx_mpwqe_supported(mdev));
5024 MLX5E_SET_PFLAG(params, MLX5E_PFLAG_XDP_TX_MPWQE, mlx5e_tx_mpwqe_supported(mdev));
5026 /* set CQE compression */
5027 params->rx_cqe_compress_def = false;
5028 if (MLX5_CAP_GEN(mdev, cqe_compression) &&
5029 MLX5_CAP_GEN(mdev, vport_group_manager))
5030 params->rx_cqe_compress_def = slow_pci_heuristic(mdev);
5032 MLX5E_SET_PFLAG(params, MLX5E_PFLAG_RX_CQE_COMPRESS, params->rx_cqe_compress_def);
5033 MLX5E_SET_PFLAG(params, MLX5E_PFLAG_RX_NO_CSUM_COMPLETE, false);
5036 mlx5e_build_rq_params(mdev, params);
5038 params->terminate_lkey_be = mlx5_core_get_terminate_scatter_list_mkey(mdev);
5040 params->packet_merge.timeout = mlx5e_choose_lro_timeout(mdev, MLX5E_DEFAULT_LRO_TIMEOUT);
5042 /* CQ moderation params */
5043 rx_cq_period_mode = MLX5_CAP_GEN(mdev, cq_period_start_from_cqe) ?
5044 MLX5_CQ_PERIOD_MODE_START_FROM_CQE :
5045 MLX5_CQ_PERIOD_MODE_START_FROM_EQE;
5046 params->rx_dim_enabled = MLX5_CAP_GEN(mdev, cq_moderation);
5047 params->tx_dim_enabled = MLX5_CAP_GEN(mdev, cq_moderation);
5048 mlx5e_set_rx_cq_mode_params(params, rx_cq_period_mode);
5049 mlx5e_set_tx_cq_mode_params(params, MLX5_CQ_PERIOD_MODE_START_FROM_EQE);
5052 mlx5_query_min_inline(mdev, ¶ms->tx_min_inline_mode);
5057 /* Do not update netdev->features directly in here
5058 * on mlx5e_attach_netdev() we will call mlx5e_update_features()
5059 * To update netdev->features please modify mlx5e_fix_features()
5063 static void mlx5e_set_netdev_dev_addr(struct net_device *netdev)
5065 struct mlx5e_priv *priv = netdev_priv(netdev);
5068 mlx5_query_mac_address(priv->mdev, addr);
5069 if (is_zero_ether_addr(addr) &&
5070 !MLX5_CAP_GEN(priv->mdev, vport_group_manager)) {
5071 eth_hw_addr_random(netdev);
5072 mlx5_core_info(priv->mdev, "Assigned random MAC address %pM\n", netdev->dev_addr);
5076 eth_hw_addr_set(netdev, addr);
5079 static int mlx5e_vxlan_set_port(struct net_device *netdev, unsigned int table,
5080 unsigned int entry, struct udp_tunnel_info *ti)
5082 struct mlx5e_priv *priv = netdev_priv(netdev);
5084 return mlx5_vxlan_add_port(priv->mdev->vxlan, ntohs(ti->port));
5087 static int mlx5e_vxlan_unset_port(struct net_device *netdev, unsigned int table,
5088 unsigned int entry, struct udp_tunnel_info *ti)
5090 struct mlx5e_priv *priv = netdev_priv(netdev);
5092 return mlx5_vxlan_del_port(priv->mdev->vxlan, ntohs(ti->port));
5095 void mlx5e_vxlan_set_netdev_info(struct mlx5e_priv *priv)
5097 if (!mlx5_vxlan_allowed(priv->mdev->vxlan))
5100 priv->nic_info.set_port = mlx5e_vxlan_set_port;
5101 priv->nic_info.unset_port = mlx5e_vxlan_unset_port;
5102 priv->nic_info.flags = UDP_TUNNEL_NIC_INFO_MAY_SLEEP |
5103 UDP_TUNNEL_NIC_INFO_STATIC_IANA_VXLAN;
5104 priv->nic_info.tables[0].tunnel_types = UDP_TUNNEL_TYPE_VXLAN;
5105 /* Don't count the space hard-coded to the IANA port */
5106 priv->nic_info.tables[0].n_entries =
5107 mlx5_vxlan_max_udp_ports(priv->mdev) - 1;
5109 priv->netdev->udp_tunnel_nic_info = &priv->nic_info;
5112 static bool mlx5e_tunnel_any_tx_proto_supported(struct mlx5_core_dev *mdev)
5116 for (tt = 0; tt < MLX5_NUM_TUNNEL_TT; tt++) {
5117 if (mlx5e_tunnel_proto_supported_tx(mdev, mlx5_get_proto_by_tunnel_type(tt)))
5120 return (mlx5_vxlan_allowed(mdev->vxlan) || mlx5_geneve_tx_allowed(mdev));
5123 static void mlx5e_build_nic_netdev(struct net_device *netdev)
5125 struct mlx5e_priv *priv = netdev_priv(netdev);
5126 struct mlx5_core_dev *mdev = priv->mdev;
5130 SET_NETDEV_DEV(netdev, mdev->device);
5132 netdev->netdev_ops = &mlx5e_netdev_ops;
5133 netdev->xdp_metadata_ops = &mlx5e_xdp_metadata_ops;
5134 netdev->xsk_tx_metadata_ops = &mlx5e_xsk_tx_metadata_ops;
5136 mlx5e_dcbnl_build_netdev(netdev);
5138 netdev->watchdog_timeo = 15 * HZ;
5140 netdev->ethtool_ops = &mlx5e_ethtool_ops;
5142 netdev->vlan_features |= NETIF_F_SG;
5143 netdev->vlan_features |= NETIF_F_HW_CSUM;
5144 netdev->vlan_features |= NETIF_F_HW_MACSEC;
5145 netdev->vlan_features |= NETIF_F_GRO;
5146 netdev->vlan_features |= NETIF_F_TSO;
5147 netdev->vlan_features |= NETIF_F_TSO6;
5148 netdev->vlan_features |= NETIF_F_RXCSUM;
5149 netdev->vlan_features |= NETIF_F_RXHASH;
5150 netdev->vlan_features |= NETIF_F_GSO_PARTIAL;
5152 netdev->mpls_features |= NETIF_F_SG;
5153 netdev->mpls_features |= NETIF_F_HW_CSUM;
5154 netdev->mpls_features |= NETIF_F_TSO;
5155 netdev->mpls_features |= NETIF_F_TSO6;
5157 netdev->hw_enc_features |= NETIF_F_HW_VLAN_CTAG_TX;
5158 netdev->hw_enc_features |= NETIF_F_HW_VLAN_CTAG_RX;
5160 /* Tunneled LRO is not supported in the driver, and the same RQs are
5161 * shared between inner and outer TIRs, so the driver can't disable LRO
5162 * for inner TIRs while having it enabled for outer TIRs. Due to this,
5163 * block LRO altogether if the firmware declares tunneled LRO support.
5165 if (!!MLX5_CAP_ETH(mdev, lro_cap) &&
5166 !MLX5_CAP_ETH(mdev, tunnel_lro_vxlan) &&
5167 !MLX5_CAP_ETH(mdev, tunnel_lro_gre) &&
5168 mlx5e_check_fragmented_striding_rq_cap(mdev, PAGE_SHIFT,
5169 MLX5E_MPWRQ_UMR_MODE_ALIGNED))
5170 netdev->vlan_features |= NETIF_F_LRO;
5172 netdev->hw_features = netdev->vlan_features;
5173 netdev->hw_features |= NETIF_F_HW_VLAN_CTAG_TX;
5174 netdev->hw_features |= NETIF_F_HW_VLAN_CTAG_RX;
5175 netdev->hw_features |= NETIF_F_HW_VLAN_CTAG_FILTER;
5176 netdev->hw_features |= NETIF_F_HW_VLAN_STAG_TX;
5178 if (mlx5e_tunnel_any_tx_proto_supported(mdev)) {
5179 netdev->hw_enc_features |= NETIF_F_HW_CSUM;
5180 netdev->hw_enc_features |= NETIF_F_TSO;
5181 netdev->hw_enc_features |= NETIF_F_TSO6;
5182 netdev->hw_enc_features |= NETIF_F_GSO_PARTIAL;
5185 if (mlx5_vxlan_allowed(mdev->vxlan) || mlx5_geneve_tx_allowed(mdev)) {
5186 netdev->hw_features |= NETIF_F_GSO_UDP_TUNNEL |
5187 NETIF_F_GSO_UDP_TUNNEL_CSUM;
5188 netdev->hw_enc_features |= NETIF_F_GSO_UDP_TUNNEL |
5189 NETIF_F_GSO_UDP_TUNNEL_CSUM;
5190 netdev->gso_partial_features = NETIF_F_GSO_UDP_TUNNEL_CSUM;
5191 netdev->vlan_features |= NETIF_F_GSO_UDP_TUNNEL |
5192 NETIF_F_GSO_UDP_TUNNEL_CSUM;
5195 if (mlx5e_tunnel_proto_supported_tx(mdev, IPPROTO_GRE)) {
5196 netdev->hw_features |= NETIF_F_GSO_GRE |
5197 NETIF_F_GSO_GRE_CSUM;
5198 netdev->hw_enc_features |= NETIF_F_GSO_GRE |
5199 NETIF_F_GSO_GRE_CSUM;
5200 netdev->gso_partial_features |= NETIF_F_GSO_GRE |
5201 NETIF_F_GSO_GRE_CSUM;
5204 if (mlx5e_tunnel_proto_supported_tx(mdev, IPPROTO_IPIP)) {
5205 netdev->hw_features |= NETIF_F_GSO_IPXIP4 |
5207 netdev->hw_enc_features |= NETIF_F_GSO_IPXIP4 |
5209 netdev->gso_partial_features |= NETIF_F_GSO_IPXIP4 |
5213 netdev->gso_partial_features |= NETIF_F_GSO_UDP_L4;
5214 netdev->hw_features |= NETIF_F_GSO_UDP_L4;
5216 mlx5_query_port_fcs(mdev, &fcs_supported, &fcs_enabled);
5219 netdev->hw_features |= NETIF_F_RXALL;
5221 if (MLX5_CAP_ETH(mdev, scatter_fcs))
5222 netdev->hw_features |= NETIF_F_RXFCS;
5224 if (mlx5_qos_is_supported(mdev))
5225 netdev->hw_features |= NETIF_F_HW_TC;
5227 netdev->features = netdev->hw_features;
5231 netdev->features &= ~NETIF_F_RXALL;
5232 netdev->features &= ~NETIF_F_LRO;
5233 netdev->features &= ~NETIF_F_GRO_HW;
5234 netdev->features &= ~NETIF_F_RXFCS;
5236 #define FT_CAP(f) MLX5_CAP_FLOWTABLE(mdev, flow_table_properties_nic_receive.f)
5237 if (FT_CAP(flow_modify_en) &&
5238 FT_CAP(modify_root) &&
5239 FT_CAP(identified_miss_table_mode) &&
5240 FT_CAP(flow_table_modify)) {
5241 #if IS_ENABLED(CONFIG_MLX5_CLS_ACT)
5242 netdev->hw_features |= NETIF_F_HW_TC;
5244 #ifdef CONFIG_MLX5_EN_ARFS
5245 netdev->hw_features |= NETIF_F_NTUPLE;
5249 netdev->features |= NETIF_F_HIGHDMA;
5250 netdev->features |= NETIF_F_HW_VLAN_STAG_FILTER;
5252 netdev->priv_flags |= IFF_UNICAST_FLT;
5254 netif_set_tso_max_size(netdev, GSO_MAX_SIZE);
5255 mlx5e_set_xdp_feature(netdev);
5256 mlx5e_set_netdev_dev_addr(netdev);
5257 mlx5e_macsec_build_netdev(priv);
5258 mlx5e_ipsec_build_netdev(priv);
5259 mlx5e_ktls_build_netdev(priv);
5262 void mlx5e_create_q_counters(struct mlx5e_priv *priv)
5264 u32 out[MLX5_ST_SZ_DW(alloc_q_counter_out)] = {};
5265 u32 in[MLX5_ST_SZ_DW(alloc_q_counter_in)] = {};
5266 struct mlx5_core_dev *mdev = priv->mdev;
5269 MLX5_SET(alloc_q_counter_in, in, opcode, MLX5_CMD_OP_ALLOC_Q_COUNTER);
5270 err = mlx5_cmd_exec_inout(mdev, alloc_q_counter, in, out);
5273 MLX5_GET(alloc_q_counter_out, out, counter_set_id);
5275 err = mlx5_cmd_exec_inout(mdev, alloc_q_counter, in, out);
5277 priv->drop_rq_q_counter =
5278 MLX5_GET(alloc_q_counter_out, out, counter_set_id);
5281 void mlx5e_destroy_q_counters(struct mlx5e_priv *priv)
5283 u32 in[MLX5_ST_SZ_DW(dealloc_q_counter_in)] = {};
5285 MLX5_SET(dealloc_q_counter_in, in, opcode,
5286 MLX5_CMD_OP_DEALLOC_Q_COUNTER);
5287 if (priv->q_counter) {
5288 MLX5_SET(dealloc_q_counter_in, in, counter_set_id,
5290 mlx5_cmd_exec_in(priv->mdev, dealloc_q_counter, in);
5293 if (priv->drop_rq_q_counter) {
5294 MLX5_SET(dealloc_q_counter_in, in, counter_set_id,
5295 priv->drop_rq_q_counter);
5296 mlx5_cmd_exec_in(priv->mdev, dealloc_q_counter, in);
5300 static int mlx5e_nic_init(struct mlx5_core_dev *mdev,
5301 struct net_device *netdev)
5303 const bool take_rtnl = netdev->reg_state == NETREG_REGISTERED;
5304 struct mlx5e_priv *priv = netdev_priv(netdev);
5305 struct mlx5e_flow_steering *fs;
5308 mlx5e_build_nic_params(priv, &priv->xsk, netdev->mtu);
5309 mlx5e_vxlan_set_netdev_info(priv);
5311 mlx5e_timestamp_init(priv);
5313 priv->dfs_root = debugfs_create_dir("nic",
5314 mlx5_debugfs_get_dev_root(mdev));
5316 fs = mlx5e_fs_init(priv->profile, mdev,
5317 !test_bit(MLX5E_STATE_DESTROYING, &priv->state),
5321 mlx5_core_err(mdev, "FS initialization failed, %d\n", err);
5322 debugfs_remove_recursive(priv->dfs_root);
5327 err = mlx5e_ktls_init(priv);
5329 mlx5_core_err(mdev, "TLS initialization failed, %d\n", err);
5331 mlx5e_health_create_reporters(priv);
5333 /* If netdev is already registered (e.g. move from uplink to nic profile),
5334 * RTNL lock must be held before triggering netdev notifiers.
5339 /* update XDP supported features */
5340 mlx5e_set_xdp_feature(netdev);
5348 static void mlx5e_nic_cleanup(struct mlx5e_priv *priv)
5350 mlx5e_health_destroy_reporters(priv);
5351 mlx5e_ktls_cleanup(priv);
5352 mlx5e_fs_cleanup(priv->fs);
5353 debugfs_remove_recursive(priv->dfs_root);
5357 static int mlx5e_init_nic_rx(struct mlx5e_priv *priv)
5359 struct mlx5_core_dev *mdev = priv->mdev;
5360 enum mlx5e_rx_res_features features;
5363 mlx5e_create_q_counters(priv);
5365 err = mlx5e_open_drop_rq(priv, &priv->drop_rq);
5367 mlx5_core_err(mdev, "open drop rq failed, %d\n", err);
5368 goto err_destroy_q_counters;
5371 features = MLX5E_RX_RES_FEATURE_PTP;
5372 if (mlx5_tunnel_inner_ft_supported(mdev))
5373 features |= MLX5E_RX_RES_FEATURE_INNER_FT;
5375 priv->rx_res = mlx5e_rx_res_create(priv->mdev, features, priv->max_nch, priv->drop_rq.rqn,
5376 &priv->channels.params.packet_merge,
5377 priv->channels.params.num_channels);
5378 if (IS_ERR(priv->rx_res)) {
5379 err = PTR_ERR(priv->rx_res);
5380 priv->rx_res = NULL;
5381 mlx5_core_err(mdev, "create rx resources failed, %d\n", err);
5382 goto err_close_drop_rq;
5385 err = mlx5e_create_flow_steering(priv->fs, priv->rx_res, priv->profile,
5388 mlx5_core_warn(mdev, "create flow steering failed, %d\n", err);
5389 goto err_destroy_rx_res;
5392 err = mlx5e_tc_nic_init(priv);
5394 goto err_destroy_flow_steering;
5396 err = mlx5e_accel_init_rx(priv);
5398 goto err_tc_nic_cleanup;
5400 #ifdef CONFIG_MLX5_EN_ARFS
5401 priv->netdev->rx_cpu_rmap = mlx5_eq_table_get_rmap(priv->mdev);
5407 mlx5e_tc_nic_cleanup(priv);
5408 err_destroy_flow_steering:
5409 mlx5e_destroy_flow_steering(priv->fs, !!(priv->netdev->hw_features & NETIF_F_NTUPLE),
5412 mlx5e_rx_res_destroy(priv->rx_res);
5413 priv->rx_res = NULL;
5415 mlx5e_close_drop_rq(&priv->drop_rq);
5416 err_destroy_q_counters:
5417 mlx5e_destroy_q_counters(priv);
5421 static void mlx5e_cleanup_nic_rx(struct mlx5e_priv *priv)
5423 mlx5e_accel_cleanup_rx(priv);
5424 mlx5e_tc_nic_cleanup(priv);
5425 mlx5e_destroy_flow_steering(priv->fs, !!(priv->netdev->hw_features & NETIF_F_NTUPLE),
5427 mlx5e_rx_res_destroy(priv->rx_res);
5428 priv->rx_res = NULL;
5429 mlx5e_close_drop_rq(&priv->drop_rq);
5430 mlx5e_destroy_q_counters(priv);
5433 static void mlx5e_set_mqprio_rl(struct mlx5e_priv *priv)
5435 struct mlx5e_params *params;
5436 struct mlx5e_mqprio_rl *rl;
5438 params = &priv->channels.params;
5439 if (params->mqprio.mode != TC_MQPRIO_MODE_CHANNEL)
5442 rl = mlx5e_mqprio_rl_create(priv->mdev, params->mqprio.num_tc,
5443 params->mqprio.channel.max_rate);
5446 priv->mqprio_rl = rl;
5447 mlx5e_mqprio_rl_update_params(params, rl);
5450 static int mlx5e_init_nic_tx(struct mlx5e_priv *priv)
5454 err = mlx5e_accel_init_tx(priv);
5458 mlx5e_set_mqprio_rl(priv);
5459 mlx5e_dcbnl_initialize(priv);
5463 static void mlx5e_nic_enable(struct mlx5e_priv *priv)
5465 struct net_device *netdev = priv->netdev;
5466 struct mlx5_core_dev *mdev = priv->mdev;
5469 mlx5e_fs_init_l2_addr(priv->fs, netdev);
5470 mlx5e_ipsec_init(priv);
5472 err = mlx5e_macsec_init(priv);
5474 mlx5_core_err(mdev, "MACsec initialization failed, %d\n", err);
5476 /* Marking the link as currently not needed by the Driver */
5477 if (!netif_running(netdev))
5478 mlx5e_modify_admin_state(mdev, MLX5_PORT_DOWN);
5480 mlx5e_set_netdev_mtu_boundaries(priv);
5481 mlx5e_set_dev_port_mtu(priv);
5483 mlx5_lag_add_netdev(mdev, netdev);
5485 mlx5e_enable_async_events(priv);
5486 mlx5e_enable_blocking_events(priv);
5487 if (mlx5e_monitor_counter_supported(priv))
5488 mlx5e_monitor_counter_init(priv);
5490 mlx5e_hv_vhca_stats_create(priv);
5491 if (netdev->reg_state != NETREG_REGISTERED)
5493 mlx5e_dcbnl_init_app(priv);
5495 mlx5e_nic_set_rx_mode(priv);
5498 if (netif_running(netdev))
5500 udp_tunnel_nic_reset_ntf(priv->netdev);
5501 netif_device_attach(netdev);
5505 static void mlx5e_nic_disable(struct mlx5e_priv *priv)
5507 struct mlx5_core_dev *mdev = priv->mdev;
5509 if (priv->netdev->reg_state == NETREG_REGISTERED)
5510 mlx5e_dcbnl_delete_app(priv);
5513 if (netif_running(priv->netdev))
5514 mlx5e_close(priv->netdev);
5515 netif_device_detach(priv->netdev);
5518 mlx5e_nic_set_rx_mode(priv);
5520 mlx5e_hv_vhca_stats_destroy(priv);
5521 if (mlx5e_monitor_counter_supported(priv))
5522 mlx5e_monitor_counter_cleanup(priv);
5524 mlx5e_disable_blocking_events(priv);
5525 if (priv->en_trap) {
5526 mlx5e_deactivate_trap(priv);
5527 mlx5e_close_trap(priv->en_trap);
5528 priv->en_trap = NULL;
5530 mlx5e_disable_async_events(priv);
5531 mlx5_lag_remove_netdev(mdev, priv->netdev);
5532 mlx5_vxlan_reset_to_default(mdev->vxlan);
5533 mlx5e_macsec_cleanup(priv);
5534 mlx5e_ipsec_cleanup(priv);
5537 int mlx5e_update_nic_rx(struct mlx5e_priv *priv)
5539 return mlx5e_refresh_tirs(priv, false, false);
5542 static const struct mlx5e_profile mlx5e_nic_profile = {
5543 .init = mlx5e_nic_init,
5544 .cleanup = mlx5e_nic_cleanup,
5545 .init_rx = mlx5e_init_nic_rx,
5546 .cleanup_rx = mlx5e_cleanup_nic_rx,
5547 .init_tx = mlx5e_init_nic_tx,
5548 .cleanup_tx = mlx5e_cleanup_nic_tx,
5549 .enable = mlx5e_nic_enable,
5550 .disable = mlx5e_nic_disable,
5551 .update_rx = mlx5e_update_nic_rx,
5552 .update_stats = mlx5e_stats_update_ndo_stats,
5553 .update_carrier = mlx5e_update_carrier,
5554 .rx_handlers = &mlx5e_rx_handlers_nic,
5555 .max_tc = MLX5_MAX_NUM_TC,
5556 .stats_grps = mlx5e_nic_stats_grps,
5557 .stats_grps_num = mlx5e_nic_stats_grps_num,
5558 .features = BIT(MLX5E_PROFILE_FEATURE_PTP_RX) |
5559 BIT(MLX5E_PROFILE_FEATURE_PTP_TX) |
5560 BIT(MLX5E_PROFILE_FEATURE_QOS_HTB) |
5561 BIT(MLX5E_PROFILE_FEATURE_FS_VLAN) |
5562 BIT(MLX5E_PROFILE_FEATURE_FS_TC),
5565 static int mlx5e_profile_max_num_channels(struct mlx5_core_dev *mdev,
5566 const struct mlx5e_profile *profile)
5570 nch = mlx5e_get_max_num_channels(mdev);
5572 if (profile->max_nch_limit)
5573 nch = min_t(int, nch, profile->max_nch_limit(mdev));
5578 mlx5e_calc_max_nch(struct mlx5_core_dev *mdev, struct net_device *netdev,
5579 const struct mlx5e_profile *profile)
5582 unsigned int max_nch, tmp;
5584 /* core resources */
5585 max_nch = mlx5e_profile_max_num_channels(mdev, profile);
5587 /* netdev rx queues */
5588 max_nch = min_t(unsigned int, max_nch, netdev->num_rx_queues);
5590 /* netdev tx queues */
5591 tmp = netdev->num_tx_queues;
5592 if (mlx5_qos_is_supported(mdev))
5593 tmp -= mlx5e_qos_max_leaf_nodes(mdev);
5594 if (MLX5_CAP_GEN(mdev, ts_cqe_to_dest_cqn))
5595 tmp -= profile->max_tc;
5596 tmp = tmp / profile->max_tc;
5597 max_nch = min_t(unsigned int, max_nch, tmp);
5602 int mlx5e_get_pf_num_tirs(struct mlx5_core_dev *mdev)
5604 /* Indirect TIRS: 2 sets of TTCs (inner + outer steering)
5605 * and 1 set of direct TIRS
5607 return 2 * MLX5E_NUM_INDIR_TIRS
5608 + mlx5e_profile_max_num_channels(mdev, &mlx5e_nic_profile);
5611 void mlx5e_set_rx_mode_work(struct work_struct *work)
5613 struct mlx5e_priv *priv = container_of(work, struct mlx5e_priv,
5616 return mlx5e_fs_set_rx_mode_work(priv->fs, priv->netdev);
5619 /* mlx5e generic netdev management API (move to en_common.c) */
5620 int mlx5e_priv_init(struct mlx5e_priv *priv,
5621 const struct mlx5e_profile *profile,
5622 struct net_device *netdev,
5623 struct mlx5_core_dev *mdev)
5625 int nch, num_txqs, node;
5628 num_txqs = netdev->num_tx_queues;
5629 nch = mlx5e_calc_max_nch(mdev, netdev, profile);
5630 node = dev_to_node(mlx5_core_dma_dev(mdev));
5634 priv->netdev = netdev;
5635 priv->max_nch = nch;
5636 priv->max_opened_tc = 1;
5638 if (!alloc_cpumask_var(&priv->scratchpad.cpumask, GFP_KERNEL))
5641 mutex_init(&priv->state_lock);
5643 err = mlx5e_selq_init(&priv->selq, &priv->state_lock);
5645 goto err_free_cpumask;
5647 INIT_WORK(&priv->update_carrier_work, mlx5e_update_carrier_work);
5648 INIT_WORK(&priv->set_rx_mode_work, mlx5e_set_rx_mode_work);
5649 INIT_WORK(&priv->tx_timeout_work, mlx5e_tx_timeout_work);
5650 INIT_WORK(&priv->update_stats_work, mlx5e_update_stats_work);
5652 priv->wq = create_singlethread_workqueue("mlx5e");
5656 priv->txq2sq = kcalloc_node(num_txqs, sizeof(*priv->txq2sq), GFP_KERNEL, node);
5658 goto err_destroy_workqueue;
5660 priv->tx_rates = kcalloc_node(num_txqs, sizeof(*priv->tx_rates), GFP_KERNEL, node);
5661 if (!priv->tx_rates)
5662 goto err_free_txq2sq;
5664 priv->channel_stats =
5665 kcalloc_node(nch, sizeof(*priv->channel_stats), GFP_KERNEL, node);
5666 if (!priv->channel_stats)
5667 goto err_free_tx_rates;
5672 kfree(priv->tx_rates);
5674 kfree(priv->txq2sq);
5675 err_destroy_workqueue:
5676 destroy_workqueue(priv->wq);
5678 mlx5e_selq_cleanup(&priv->selq);
5680 free_cpumask_var(priv->scratchpad.cpumask);
5684 void mlx5e_priv_cleanup(struct mlx5e_priv *priv)
5688 /* bail if change profile failed and also rollback failed */
5692 for (i = 0; i < priv->stats_nch; i++)
5693 kvfree(priv->channel_stats[i]);
5694 kfree(priv->channel_stats);
5695 kfree(priv->tx_rates);
5696 kfree(priv->txq2sq);
5697 destroy_workqueue(priv->wq);
5698 mutex_lock(&priv->state_lock);
5699 mlx5e_selq_cleanup(&priv->selq);
5700 mutex_unlock(&priv->state_lock);
5701 free_cpumask_var(priv->scratchpad.cpumask);
5703 for (i = 0; i < priv->htb_max_qos_sqs; i++)
5704 kfree(priv->htb_qos_sq_stats[i]);
5705 kvfree(priv->htb_qos_sq_stats);
5707 memset(priv, 0, sizeof(*priv));
5710 static unsigned int mlx5e_get_max_num_txqs(struct mlx5_core_dev *mdev,
5711 const struct mlx5e_profile *profile)
5713 unsigned int nch, ptp_txqs, qos_txqs;
5715 nch = mlx5e_profile_max_num_channels(mdev, profile);
5717 ptp_txqs = MLX5_CAP_GEN(mdev, ts_cqe_to_dest_cqn) &&
5718 mlx5e_profile_feature_cap(profile, PTP_TX) ?
5719 profile->max_tc : 0;
5721 qos_txqs = mlx5_qos_is_supported(mdev) &&
5722 mlx5e_profile_feature_cap(profile, QOS_HTB) ?
5723 mlx5e_qos_max_leaf_nodes(mdev) : 0;
5725 return nch * profile->max_tc + ptp_txqs + qos_txqs;
5728 static unsigned int mlx5e_get_max_num_rxqs(struct mlx5_core_dev *mdev,
5729 const struct mlx5e_profile *profile)
5731 return mlx5e_profile_max_num_channels(mdev, profile);
5735 mlx5e_create_netdev(struct mlx5_core_dev *mdev, const struct mlx5e_profile *profile)
5737 struct net_device *netdev;
5738 unsigned int txqs, rxqs;
5741 txqs = mlx5e_get_max_num_txqs(mdev, profile);
5742 rxqs = mlx5e_get_max_num_rxqs(mdev, profile);
5744 netdev = alloc_etherdev_mqs(sizeof(struct mlx5e_priv), txqs, rxqs);
5746 mlx5_core_err(mdev, "alloc_etherdev_mqs() failed\n");
5750 err = mlx5e_priv_init(netdev_priv(netdev), profile, netdev, mdev);
5752 mlx5_core_err(mdev, "mlx5e_priv_init failed, err=%d\n", err);
5753 goto err_free_netdev;
5756 netif_carrier_off(netdev);
5757 netif_tx_disable(netdev);
5758 dev_net_set(netdev, mlx5_core_net(mdev));
5763 free_netdev(netdev);
5768 static void mlx5e_update_features(struct net_device *netdev)
5770 if (netdev->reg_state != NETREG_REGISTERED)
5771 return; /* features will be updated on netdev registration */
5774 netdev_update_features(netdev);
5778 static void mlx5e_reset_channels(struct net_device *netdev)
5780 netdev_reset_tc(netdev);
5783 int mlx5e_attach_netdev(struct mlx5e_priv *priv)
5785 const bool take_rtnl = priv->netdev->reg_state == NETREG_REGISTERED;
5786 const struct mlx5e_profile *profile = priv->profile;
5790 clear_bit(MLX5E_STATE_DESTROYING, &priv->state);
5792 mlx5e_fs_set_state_destroy(priv->fs,
5793 !test_bit(MLX5E_STATE_DESTROYING, &priv->state));
5795 /* Validate the max_wqe_size_sq capability. */
5796 if (WARN_ON_ONCE(mlx5e_get_max_sq_wqebbs(priv->mdev) < MLX5E_MAX_TX_WQEBBS)) {
5797 mlx5_core_warn(priv->mdev, "MLX5E: Max SQ WQEBBs firmware capability: %u, needed %u\n",
5798 mlx5e_get_max_sq_wqebbs(priv->mdev), (unsigned int)MLX5E_MAX_TX_WQEBBS);
5802 /* max number of channels may have changed */
5803 max_nch = mlx5e_calc_max_nch(priv->mdev, priv->netdev, profile);
5804 if (priv->channels.params.num_channels > max_nch) {
5805 mlx5_core_warn(priv->mdev, "MLX5E: Reducing number of channels to %d\n", max_nch);
5806 /* Reducing the number of channels - RXFH has to be reset, and
5807 * mlx5e_num_channels_changed below will build the RQT.
5809 priv->netdev->priv_flags &= ~IFF_RXFH_CONFIGURED;
5810 priv->channels.params.num_channels = max_nch;
5811 if (priv->channels.params.mqprio.mode == TC_MQPRIO_MODE_CHANNEL) {
5812 mlx5_core_warn(priv->mdev, "MLX5E: Disabling MQPRIO channel mode\n");
5813 mlx5e_params_mqprio_reset(&priv->channels.params);
5816 if (max_nch != priv->max_nch) {
5817 mlx5_core_warn(priv->mdev,
5818 "MLX5E: Updating max number of channels from %u to %u\n",
5819 priv->max_nch, max_nch);
5820 priv->max_nch = max_nch;
5823 /* 1. Set the real number of queues in the kernel the first time.
5824 * 2. Set our default XPS cpumask.
5827 * rtnl_lock is required by netif_set_real_num_*_queues in case the
5828 * netdev has been registered by this point (if this function was called
5829 * in the reload or resume flow).
5833 err = mlx5e_num_channels_changed(priv);
5839 err = profile->init_tx(priv);
5843 err = profile->init_rx(priv);
5845 goto err_cleanup_tx;
5847 if (profile->enable)
5848 profile->enable(priv);
5850 mlx5e_update_features(priv->netdev);
5855 profile->cleanup_tx(priv);
5858 mlx5e_reset_channels(priv->netdev);
5859 set_bit(MLX5E_STATE_DESTROYING, &priv->state);
5861 mlx5e_fs_set_state_destroy(priv->fs,
5862 !test_bit(MLX5E_STATE_DESTROYING, &priv->state));
5863 cancel_work_sync(&priv->update_stats_work);
5867 void mlx5e_detach_netdev(struct mlx5e_priv *priv)
5869 const struct mlx5e_profile *profile = priv->profile;
5871 set_bit(MLX5E_STATE_DESTROYING, &priv->state);
5873 mlx5e_fs_set_state_destroy(priv->fs,
5874 !test_bit(MLX5E_STATE_DESTROYING, &priv->state));
5876 if (profile->disable)
5877 profile->disable(priv);
5878 flush_workqueue(priv->wq);
5880 profile->cleanup_rx(priv);
5881 profile->cleanup_tx(priv);
5882 mlx5e_reset_channels(priv->netdev);
5883 cancel_work_sync(&priv->update_stats_work);
5887 mlx5e_netdev_init_profile(struct net_device *netdev, struct mlx5_core_dev *mdev,
5888 const struct mlx5e_profile *new_profile, void *new_ppriv)
5890 struct mlx5e_priv *priv = netdev_priv(netdev);
5893 err = mlx5e_priv_init(priv, new_profile, netdev, mdev);
5895 mlx5_core_err(mdev, "mlx5e_priv_init failed, err=%d\n", err);
5898 netif_carrier_off(netdev);
5899 priv->profile = new_profile;
5900 priv->ppriv = new_ppriv;
5901 err = new_profile->init(priv->mdev, priv->netdev);
5908 mlx5e_priv_cleanup(priv);
5913 mlx5e_netdev_attach_profile(struct net_device *netdev, struct mlx5_core_dev *mdev,
5914 const struct mlx5e_profile *new_profile, void *new_ppriv)
5916 struct mlx5e_priv *priv = netdev_priv(netdev);
5919 err = mlx5e_netdev_init_profile(netdev, mdev, new_profile, new_ppriv);
5923 err = mlx5e_attach_netdev(priv);
5925 goto profile_cleanup;
5929 new_profile->cleanup(priv);
5930 mlx5e_priv_cleanup(priv);
5934 int mlx5e_netdev_change_profile(struct mlx5e_priv *priv,
5935 const struct mlx5e_profile *new_profile, void *new_ppriv)
5937 const struct mlx5e_profile *orig_profile = priv->profile;
5938 struct net_device *netdev = priv->netdev;
5939 struct mlx5_core_dev *mdev = priv->mdev;
5940 void *orig_ppriv = priv->ppriv;
5941 int err, rollback_err;
5943 /* cleanup old profile */
5944 mlx5e_detach_netdev(priv);
5945 priv->profile->cleanup(priv);
5946 mlx5e_priv_cleanup(priv);
5948 if (mdev->state == MLX5_DEVICE_STATE_INTERNAL_ERROR) {
5949 mlx5e_netdev_init_profile(netdev, mdev, new_profile, new_ppriv);
5950 set_bit(MLX5E_STATE_DESTROYING, &priv->state);
5954 err = mlx5e_netdev_attach_profile(netdev, mdev, new_profile, new_ppriv);
5955 if (err) { /* roll back to original profile */
5956 netdev_warn(netdev, "%s: new profile init failed, %d\n", __func__, err);
5963 rollback_err = mlx5e_netdev_attach_profile(netdev, mdev, orig_profile, orig_ppriv);
5965 netdev_err(netdev, "%s: failed to rollback to orig profile, %d\n",
5966 __func__, rollback_err);
5970 void mlx5e_netdev_attach_nic_profile(struct mlx5e_priv *priv)
5972 mlx5e_netdev_change_profile(priv, &mlx5e_nic_profile, NULL);
5975 void mlx5e_destroy_netdev(struct mlx5e_priv *priv)
5977 struct net_device *netdev = priv->netdev;
5979 mlx5e_priv_cleanup(priv);
5980 free_netdev(netdev);
5983 static int mlx5e_resume(struct auxiliary_device *adev)
5985 struct mlx5_adev *edev = container_of(adev, struct mlx5_adev, adev);
5986 struct mlx5e_dev *mlx5e_dev = auxiliary_get_drvdata(adev);
5987 struct mlx5e_priv *priv = mlx5e_dev->priv;
5988 struct net_device *netdev = priv->netdev;
5989 struct mlx5_core_dev *mdev = edev->mdev;
5992 if (netif_device_present(netdev))
5995 err = mlx5e_create_mdev_resources(mdev);
5999 err = mlx5e_attach_netdev(priv);
6001 mlx5e_destroy_mdev_resources(mdev);
6008 static int _mlx5e_suspend(struct auxiliary_device *adev)
6010 struct mlx5e_dev *mlx5e_dev = auxiliary_get_drvdata(adev);
6011 struct mlx5e_priv *priv = mlx5e_dev->priv;
6012 struct net_device *netdev = priv->netdev;
6013 struct mlx5_core_dev *mdev = priv->mdev;
6015 if (!netif_device_present(netdev)) {
6016 if (test_bit(MLX5E_STATE_DESTROYING, &priv->state))
6017 mlx5e_destroy_mdev_resources(mdev);
6021 mlx5e_detach_netdev(priv);
6022 mlx5e_destroy_mdev_resources(mdev);
6026 static int mlx5e_suspend(struct auxiliary_device *adev, pm_message_t state)
6028 return _mlx5e_suspend(adev);
6031 static int _mlx5e_probe(struct auxiliary_device *adev)
6033 struct mlx5_adev *edev = container_of(adev, struct mlx5_adev, adev);
6034 const struct mlx5e_profile *profile = &mlx5e_nic_profile;
6035 struct mlx5_core_dev *mdev = edev->mdev;
6036 struct mlx5e_dev *mlx5e_dev;
6037 struct net_device *netdev;
6038 struct mlx5e_priv *priv;
6041 mlx5e_dev = mlx5e_create_devlink(&adev->dev, mdev);
6042 if (IS_ERR(mlx5e_dev))
6043 return PTR_ERR(mlx5e_dev);
6044 auxiliary_set_drvdata(adev, mlx5e_dev);
6046 err = mlx5e_devlink_port_register(mlx5e_dev, mdev);
6048 mlx5_core_err(mdev, "mlx5e_devlink_port_register failed, %d\n", err);
6049 goto err_devlink_unregister;
6052 netdev = mlx5e_create_netdev(mdev, profile);
6054 mlx5_core_err(mdev, "mlx5e_create_netdev failed\n");
6056 goto err_devlink_port_unregister;
6058 SET_NETDEV_DEVLINK_PORT(netdev, &mlx5e_dev->dl_port);
6060 mlx5e_build_nic_netdev(netdev);
6062 priv = netdev_priv(netdev);
6063 mlx5e_dev->priv = priv;
6065 priv->profile = profile;
6068 err = profile->init(mdev, netdev);
6070 mlx5_core_err(mdev, "mlx5e_nic_profile init failed, %d\n", err);
6071 goto err_destroy_netdev;
6074 err = mlx5e_resume(adev);
6076 mlx5_core_err(mdev, "mlx5e_resume failed, %d\n", err);
6077 goto err_profile_cleanup;
6080 err = register_netdev(netdev);
6082 mlx5_core_err(mdev, "register_netdev failed, %d\n", err);
6086 mlx5e_dcbnl_init_app(priv);
6087 mlx5_core_uplink_netdev_set(mdev, netdev);
6088 mlx5e_params_print_info(mdev, &priv->channels.params);
6092 _mlx5e_suspend(adev);
6093 err_profile_cleanup:
6094 profile->cleanup(priv);
6096 mlx5e_destroy_netdev(priv);
6097 err_devlink_port_unregister:
6098 mlx5e_devlink_port_unregister(mlx5e_dev);
6099 err_devlink_unregister:
6100 mlx5e_destroy_devlink(mlx5e_dev);
6104 static int mlx5e_probe(struct auxiliary_device *adev,
6105 const struct auxiliary_device_id *id)
6107 return _mlx5e_probe(adev);
6110 static void mlx5e_remove(struct auxiliary_device *adev)
6112 struct mlx5e_dev *mlx5e_dev = auxiliary_get_drvdata(adev);
6113 struct mlx5e_priv *priv = mlx5e_dev->priv;
6115 mlx5_core_uplink_netdev_set(priv->mdev, NULL);
6116 mlx5e_dcbnl_delete_app(priv);
6117 unregister_netdev(priv->netdev);
6118 _mlx5e_suspend(adev);
6119 priv->profile->cleanup(priv);
6120 mlx5e_destroy_netdev(priv);
6121 mlx5e_devlink_port_unregister(mlx5e_dev);
6122 mlx5e_destroy_devlink(mlx5e_dev);
6125 static const struct auxiliary_device_id mlx5e_id_table[] = {
6126 { .name = MLX5_ADEV_NAME ".eth", },
6130 MODULE_DEVICE_TABLE(auxiliary, mlx5e_id_table);
6132 static struct auxiliary_driver mlx5e_driver = {
6134 .probe = mlx5e_probe,
6135 .remove = mlx5e_remove,
6136 .suspend = mlx5e_suspend,
6137 .resume = mlx5e_resume,
6138 .id_table = mlx5e_id_table,
6141 int mlx5e_init(void)
6145 mlx5e_build_ptys2ethtool_map();
6146 ret = auxiliary_driver_register(&mlx5e_driver);
6150 ret = mlx5e_rep_init();
6152 auxiliary_driver_unregister(&mlx5e_driver);
6156 void mlx5e_cleanup(void)
6158 mlx5e_rep_cleanup();
6159 auxiliary_driver_unregister(&mlx5e_driver);