drivers/net/ethernet/mellanox/mlx5/core/en_main.c

   1 /*
   2  * Copyright (c) 2015-2016, Mellanox Technologies. All rights reserved.
   3  *
   4  * This software is available to you under a choice of one of two
   5  * licenses.  You may choose to be licensed under the terms of the GNU
   6  * General Public License (GPL) Version 2, available from the file
   7  * COPYING in the main directory of this source tree, or the
   8  * OpenIB.org BSD license below:
   9  *
  10  *     Redistribution and use in source and binary forms, with or
  11  *     without modification, are permitted provided that the following
  12  *     conditions are met:
  13  *
  14  *      - Redistributions of source code must retain the above
  15  *        copyright notice, this list of conditions and the following
  16  *        disclaimer.
  17  *
  18  *      - Redistributions in binary form must reproduce the above
  19  *        copyright notice, this list of conditions and the following
  20  *        disclaimer in the documentation and/or other materials
  21  *        provided with the distribution.
  22  *
  23  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  24  * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  25  * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
  26  * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
  27  * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
  28  * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
  29  * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
  30  * SOFTWARE.
  31  */
  32
  33 #include <net/tc_act/tc_gact.h>
  34 #include <net/pkt_cls.h>
  35 #include <linux/mlx5/fs.h>
  36 #include <net/vxlan.h>
  37 #include <net/geneve.h>
  38 #include <linux/bpf.h>
  39 #include <linux/if_bridge.h>
  40 #include <net/page_pool.h>
  41 #include <net/xdp_sock.h>
  42 #include "eswitch.h"
  43 #include "en.h"
  44 #include "en/txrx.h"
  45 #include "en_tc.h"
  46 #include "en_rep.h"
  47 #include "en_accel/ipsec.h"
  48 #include "en_accel/ipsec_rxtx.h"
  49 #include "en_accel/en_accel.h"
  50 #include "en_accel/tls.h"
  51 #include "accel/ipsec.h"
  52 #include "accel/tls.h"
  53 #include "lib/vxlan.h"
  54 #include "lib/clock.h"
  55 #include "en/port.h"
  56 #include "en/xdp.h"
  57 #include "lib/eq.h"
  58 #include "en/monitor_stats.h"
  59 #include "en/reporter.h"
  60 #include "en/params.h"
  61 #include "en/xsk/umem.h"
  62 #include "en/xsk/setup.h"
  63 #include "en/xsk/rx.h"
  64 #include "en/xsk/tx.h"
  65
  66
  67 bool mlx5e_check_fragmented_striding_rq_cap(struct mlx5_core_dev *mdev)
  68 {
  69         bool striding_rq_umr = MLX5_CAP_GEN(mdev, striding_rq) &&
  70                 MLX5_CAP_GEN(mdev, umr_ptr_rlky) &&
  71                 MLX5_CAP_ETH(mdev, reg_umr_sq);
  72         u16 max_wqe_sz_cap = MLX5_CAP_GEN(mdev, max_wqe_sz_sq);
  73         bool inline_umr = MLX5E_UMR_WQE_INLINE_SZ <= max_wqe_sz_cap;
  74
  75         if (!striding_rq_umr)
  76                 return false;
  77         if (!inline_umr) {
  78                 mlx5_core_warn(mdev, "Cannot support Striding RQ: UMR WQE size (%d) exceeds maximum supported (%d).\n",
  79                                (int)MLX5E_UMR_WQE_INLINE_SZ, max_wqe_sz_cap);
  80                 return false;
  81         }
  82         return true;
  83 }
  84
  85 void mlx5e_init_rq_type_params(struct mlx5_core_dev *mdev,
  86                                struct mlx5e_params *params)
  87 {
  88         params->log_rq_mtu_frames = is_kdump_kernel() ?
  89                 MLX5E_PARAMS_MINIMUM_LOG_RQ_SIZE :
  90                 MLX5E_PARAMS_DEFAULT_LOG_RQ_SIZE;
  91
  92         mlx5_core_info(mdev, "MLX5E: StrdRq(%d) RqSz(%ld) StrdSz(%ld) RxCqeCmprss(%d)\n",
  93                        params->rq_wq_type == MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ,
  94                        params->rq_wq_type == MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ ?
  95                        BIT(mlx5e_mpwqe_get_log_rq_size(params, NULL)) :
  96                        BIT(params->log_rq_mtu_frames),
  97                        BIT(mlx5e_mpwqe_get_log_stride_size(mdev, params, NULL)),
  98                        MLX5E_GET_PFLAG(params, MLX5E_PFLAG_RX_CQE_COMPRESS));
  99 }
 100
 101 bool mlx5e_striding_rq_possible(struct mlx5_core_dev *mdev,
 102                                 struct mlx5e_params *params)
 103 {
 104         if (!mlx5e_check_fragmented_striding_rq_cap(mdev))
 105                 return false;
 106
 107         if (MLX5_IPSEC_DEV(mdev))
 108                 return false;
 109
 110         if (params->xdp_prog) {
 111                 /* XSK params are not considered here. If striding RQ is in use,
 112                  * and an XSK is being opened, mlx5e_rx_mpwqe_is_linear_skb will
 113                  * be called with the known XSK params.
 114                  */
 115                 if (!mlx5e_rx_mpwqe_is_linear_skb(mdev, params, NULL))
 116                         return false;
 117         }
 118
 119         return true;
 120 }
 121
 122 void mlx5e_set_rq_type(struct mlx5_core_dev *mdev, struct mlx5e_params *params)
 123 {
 124         params->rq_wq_type = mlx5e_striding_rq_possible(mdev, params) &&
 125                 MLX5E_GET_PFLAG(params, MLX5E_PFLAG_RX_STRIDING_RQ) ?
 126                 MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ :
 127                 MLX5_WQ_TYPE_CYCLIC;
 128 }
 129
 130 void mlx5e_update_carrier(struct mlx5e_priv *priv)
 131 {
 132         struct mlx5_core_dev *mdev = priv->mdev;
 133         u8 port_state;
 134
 135         port_state = mlx5_query_vport_state(mdev,
 136                                             MLX5_VPORT_STATE_OP_MOD_VNIC_VPORT,
 137                                             0);
 138
 139         if (port_state == VPORT_STATE_UP) {
 140                 netdev_info(priv->netdev, "Link up\n");
 141                 netif_carrier_on(priv->netdev);
 142         } else {
 143                 netdev_info(priv->netdev, "Link down\n");
 144                 netif_carrier_off(priv->netdev);
 145         }
 146 }
 147
 148 static void mlx5e_update_carrier_work(struct work_struct *work)
 149 {
 150         struct mlx5e_priv *priv = container_of(work, struct mlx5e_priv,
 151                                                update_carrier_work);
 152
 153         mutex_lock(&priv->state_lock);
 154         if (test_bit(MLX5E_STATE_OPENED, &priv->state))
 155                 if (priv->profile->update_carrier)
 156                         priv->profile->update_carrier(priv);
 157         mutex_unlock(&priv->state_lock);
 158 }
 159
 160 void mlx5e_update_stats(struct mlx5e_priv *priv)
 161 {
 162         int i;
 163
 164         for (i = mlx5e_num_stats_grps - 1; i >= 0; i--)
 165                 if (mlx5e_stats_grps[i].update_stats)
 166                         mlx5e_stats_grps[i].update_stats(priv);
 167 }
 168
 169 void mlx5e_update_ndo_stats(struct mlx5e_priv *priv)
 170 {
 171         int i;
 172
 173         for (i = mlx5e_num_stats_grps - 1; i >= 0; i--)
 174                 if (mlx5e_stats_grps[i].update_stats_mask &
 175                     MLX5E_NDO_UPDATE_STATS)
 176                         mlx5e_stats_grps[i].update_stats(priv);
 177 }
 178
 179 static void mlx5e_update_stats_work(struct work_struct *work)
 180 {
 181         struct mlx5e_priv *priv = container_of(work, struct mlx5e_priv,
 182                                                update_stats_work);
 183
 184         mutex_lock(&priv->state_lock);
 185         priv->profile->update_stats(priv);
 186         mutex_unlock(&priv->state_lock);
 187 }
 188
 189 void mlx5e_queue_update_stats(struct mlx5e_priv *priv)
 190 {
 191         if (!priv->profile->update_stats)
 192                 return;
 193
 194         if (unlikely(test_bit(MLX5E_STATE_DESTROYING, &priv->state)))
 195                 return;
 196
 197         queue_work(priv->wq, &priv->update_stats_work);
 198 }
 199
 200 static int async_event(struct notifier_block *nb, unsigned long event, void *data)
 201 {
 202         struct mlx5e_priv *priv = container_of(nb, struct mlx5e_priv, events_nb);
 203         struct mlx5_eqe   *eqe = data;
 204
 205         if (event != MLX5_EVENT_TYPE_PORT_CHANGE)
 206                 return NOTIFY_DONE;
 207
 208         switch (eqe->sub_type) {
 209         case MLX5_PORT_CHANGE_SUBTYPE_DOWN:
 210         case MLX5_PORT_CHANGE_SUBTYPE_ACTIVE:
 211                 queue_work(priv->wq, &priv->update_carrier_work);
 212                 break;
 213         default:
 214                 return NOTIFY_DONE;
 215         }
 216
 217         return NOTIFY_OK;
 218 }
 219
 220 static void mlx5e_enable_async_events(struct mlx5e_priv *priv)
 221 {
 222         priv->events_nb.notifier_call = async_event;
 223         mlx5_notifier_register(priv->mdev, &priv->events_nb);
 224 }
 225
 226 static void mlx5e_disable_async_events(struct mlx5e_priv *priv)
 227 {
 228         mlx5_notifier_unregister(priv->mdev, &priv->events_nb);
 229 }
 230
 231 static inline void mlx5e_build_umr_wqe(struct mlx5e_rq *rq,
 232                                        struct mlx5e_icosq *sq,
 233                                        struct mlx5e_umr_wqe *wqe)
 234 {
 235         struct mlx5_wqe_ctrl_seg      *cseg = &wqe->ctrl;
 236         struct mlx5_wqe_umr_ctrl_seg *ucseg = &wqe->uctrl;
 237         u8 ds_cnt = DIV_ROUND_UP(MLX5E_UMR_WQE_INLINE_SZ, MLX5_SEND_WQE_DS);
 238
 239         cseg->qpn_ds    = cpu_to_be32((sq->sqn << MLX5_WQE_CTRL_QPN_SHIFT) |
 240                                       ds_cnt);
 241         cseg->fm_ce_se  = MLX5_WQE_CTRL_CQ_UPDATE;
 242         cseg->imm       = rq->mkey_be;
 243
 244         ucseg->flags = MLX5_UMR_TRANSLATION_OFFSET_EN | MLX5_UMR_INLINE;
 245         ucseg->xlt_octowords =
 246                 cpu_to_be16(MLX5_MTT_OCTW(MLX5_MPWRQ_PAGES_PER_WQE));
 247         ucseg->mkey_mask     = cpu_to_be64(MLX5_MKEY_MASK_FREE);
 248 }
 249
 250 static u32 mlx5e_rqwq_get_size(struct mlx5e_rq *rq)
 251 {
 252         switch (rq->wq_type) {
 253         case MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ:
 254                 return mlx5_wq_ll_get_size(&rq->mpwqe.wq);
 255         default:
 256                 return mlx5_wq_cyc_get_size(&rq->wqe.wq);
 257         }
 258 }
 259
 260 static u32 mlx5e_rqwq_get_cur_sz(struct mlx5e_rq *rq)
 261 {
 262         switch (rq->wq_type) {
 263         case MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ:
 264                 return rq->mpwqe.wq.cur_sz;
 265         default:
 266                 return rq->wqe.wq.cur_sz;
 267         }
 268 }
 269
 270 static int mlx5e_rq_alloc_mpwqe_info(struct mlx5e_rq *rq,
 271                                      struct mlx5e_channel *c)
 272 {
 273         int wq_sz = mlx5_wq_ll_get_size(&rq->mpwqe.wq);
 274
 275         rq->mpwqe.info = kvzalloc_node(array_size(wq_sz,
 276                                                   sizeof(*rq->mpwqe.info)),
 277                                        GFP_KERNEL, cpu_to_node(c->cpu));
 278         if (!rq->mpwqe.info)
 279                 return -ENOMEM;
 280
 281         mlx5e_build_umr_wqe(rq, &c->icosq, &rq->mpwqe.umr_wqe);
 282
 283         return 0;
 284 }
 285
 286 static int mlx5e_create_umr_mkey(struct mlx5_core_dev *mdev,
 287                                  u64 npages, u8 page_shift,
 288                                  struct mlx5_core_mkey *umr_mkey)
 289 {
 290         int inlen = MLX5_ST_SZ_BYTES(create_mkey_in);
 291         void *mkc;
 292         u32 *in;
 293         int err;
 294
 295         in = kvzalloc(inlen, GFP_KERNEL);
 296         if (!in)
 297                 return -ENOMEM;
 298
 299         mkc = MLX5_ADDR_OF(create_mkey_in, in, memory_key_mkey_entry);
 300
 301         MLX5_SET(mkc, mkc, free, 1);
 302         MLX5_SET(mkc, mkc, umr_en, 1);
 303         MLX5_SET(mkc, mkc, lw, 1);
 304         MLX5_SET(mkc, mkc, lr, 1);
 305         MLX5_SET(mkc, mkc, access_mode_1_0, MLX5_MKC_ACCESS_MODE_MTT);
 306
 307         MLX5_SET(mkc, mkc, qpn, 0xffffff);
 308         MLX5_SET(mkc, mkc, pd, mdev->mlx5e_res.pdn);
 309         MLX5_SET64(mkc, mkc, len, npages << page_shift);
 310         MLX5_SET(mkc, mkc, translations_octword_size,
 311                  MLX5_MTT_OCTW(npages));
 312         MLX5_SET(mkc, mkc, log_page_size, page_shift);
 313
 314         err = mlx5_core_create_mkey(mdev, umr_mkey, in, inlen);
 315
 316         kvfree(in);
 317         return err;
 318 }
 319
 320 static int mlx5e_create_rq_umr_mkey(struct mlx5_core_dev *mdev, struct mlx5e_rq *rq)
 321 {
 322         u64 num_mtts = MLX5E_REQUIRED_MTTS(mlx5_wq_ll_get_size(&rq->mpwqe.wq));
 323
 324         return mlx5e_create_umr_mkey(mdev, num_mtts, PAGE_SHIFT, &rq->umr_mkey);
 325 }
 326
 327 static inline u64 mlx5e_get_mpwqe_offset(struct mlx5e_rq *rq, u16 wqe_ix)
 328 {
 329         return (wqe_ix << MLX5E_LOG_ALIGNED_MPWQE_PPW) << PAGE_SHIFT;
 330 }
 331
 332 static void mlx5e_init_frags_partition(struct mlx5e_rq *rq)
 333 {
 334         struct mlx5e_wqe_frag_info next_frag = {};
 335         struct mlx5e_wqe_frag_info *prev = NULL;
 336         int i;
 337
 338         next_frag.di = &rq->wqe.di[0];
 339
 340         for (i = 0; i < mlx5_wq_cyc_get_size(&rq->wqe.wq); i++) {
 341                 struct mlx5e_rq_frag_info *frag_info = &rq->wqe.info.arr[0];
 342                 struct mlx5e_wqe_frag_info *frag =
 343                         &rq->wqe.frags[i << rq->wqe.info.log_num_frags];
 344                 int f;
 345
 346                 for (f = 0; f < rq->wqe.info.num_frags; f++, frag++) {
 347                         if (next_frag.offset + frag_info[f].frag_stride > PAGE_SIZE) {
 348                                 next_frag.di++;
 349                                 next_frag.offset = 0;
 350                                 if (prev)
 351                                         prev->last_in_page = true;
 352                         }
 353                         *frag = next_frag;
 354
 355                         /* prepare next */
 356                         next_frag.offset += frag_info[f].frag_stride;
 357                         prev = frag;
 358                 }
 359         }
 360
 361         if (prev)
 362                 prev->last_in_page = true;
 363 }
 364
 365 static int mlx5e_init_di_list(struct mlx5e_rq *rq,
 366                               int wq_sz, int cpu)
 367 {
 368         int len = wq_sz << rq->wqe.info.log_num_frags;
 369
 370         rq->wqe.di = kvzalloc_node(array_size(len, sizeof(*rq->wqe.di)),
 371                                    GFP_KERNEL, cpu_to_node(cpu));
 372         if (!rq->wqe.di)
 373                 return -ENOMEM;
 374
 375         mlx5e_init_frags_partition(rq);
 376
 377         return 0;
 378 }
 379
 380 static void mlx5e_free_di_list(struct mlx5e_rq *rq)
 381 {
 382         kvfree(rq->wqe.di);
 383 }
 384
 385 static int mlx5e_alloc_rq(struct mlx5e_channel *c,
 386                           struct mlx5e_params *params,
 387                           struct mlx5e_xsk_param *xsk,
 388                           struct xdp_umem *umem,
 389                           struct mlx5e_rq_param *rqp,
 390                           struct mlx5e_rq *rq)
 391 {
 392         struct page_pool_params pp_params = { 0 };
 393         struct mlx5_core_dev *mdev = c->mdev;
 394         void *rqc = rqp->rqc;
 395         void *rqc_wq = MLX5_ADDR_OF(rqc, rqc, wq);
 396         u32 num_xsk_frames = 0;
 397         u32 rq_xdp_ix;
 398         u32 pool_size;
 399         int wq_sz;
 400         int err;
 401         int i;
 402
 403         rqp->wq.db_numa_node = cpu_to_node(c->cpu);
 404
 405         rq->wq_type = params->rq_wq_type;
 406         rq->pdev    = c->pdev;
 407         rq->netdev  = c->netdev;
 408         rq->tstamp  = c->tstamp;
 409         rq->clock   = &mdev->clock;
 410         rq->channel = c;
 411         rq->ix      = c->ix;
 412         rq->mdev    = mdev;
 413         rq->hw_mtu  = MLX5E_SW2HW_MTU(params, params->sw_mtu);
 414         rq->xdpsq   = &c->rq_xdpsq;
 415         rq->umem    = umem;
 416
 417         if (rq->umem)
 418                 rq->stats = &c->priv->channel_stats[c->ix].xskrq;
 419         else
 420                 rq->stats = &c->priv->channel_stats[c->ix].rq;
 421
 422         rq->xdp_prog = params->xdp_prog ? bpf_prog_inc(params->xdp_prog) : NULL;
 423         if (IS_ERR(rq->xdp_prog)) {
 424                 err = PTR_ERR(rq->xdp_prog);
 425                 rq->xdp_prog = NULL;
 426                 goto err_rq_wq_destroy;
 427         }
 428
 429         rq_xdp_ix = rq->ix;
 430         if (xsk)
 431                 rq_xdp_ix += params->num_channels * MLX5E_RQ_GROUP_XSK;
 432         err = xdp_rxq_info_reg(&rq->xdp_rxq, rq->netdev, rq_xdp_ix);
 433         if (err < 0)
 434                 goto err_rq_wq_destroy;
 435
 436         rq->buff.map_dir = rq->xdp_prog ? DMA_BIDIRECTIONAL : DMA_FROM_DEVICE;
 437         rq->buff.headroom = mlx5e_get_rq_headroom(mdev, params, xsk);
 438         rq->buff.umem_headroom = xsk ? xsk->headroom : 0;
 439         pool_size = 1 << params->log_rq_mtu_frames;
 440
 441         switch (rq->wq_type) {
 442         case MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ:
 443                 err = mlx5_wq_ll_create(mdev, &rqp->wq, rqc_wq, &rq->mpwqe.wq,
 444                                         &rq->wq_ctrl);
 445                 if (err)
 446                         return err;
 447
 448                 rq->mpwqe.wq.db = &rq->mpwqe.wq.db[MLX5_RCV_DBR];
 449
 450                 wq_sz = mlx5_wq_ll_get_size(&rq->mpwqe.wq);
 451
 452                 if (xsk)
 453                         num_xsk_frames = wq_sz <<
 454                                 mlx5e_mpwqe_get_log_num_strides(mdev, params, xsk);
 455
 456                 pool_size = MLX5_MPWRQ_PAGES_PER_WQE <<
 457                         mlx5e_mpwqe_get_log_rq_size(params, xsk);
 458
 459                 rq->post_wqes = mlx5e_post_rx_mpwqes;
 460                 rq->dealloc_wqe = mlx5e_dealloc_rx_mpwqe;
 461
 462                 rq->handle_rx_cqe = c->priv->profile->rx_handlers.handle_rx_cqe_mpwqe;
 463 #ifdef CONFIG_MLX5_EN_IPSEC
 464                 if (MLX5_IPSEC_DEV(mdev)) {
 465                         err = -EINVAL;
 466                         netdev_err(c->netdev, "MPWQE RQ with IPSec offload not supported\n");
 467                         goto err_rq_wq_destroy;
 468                 }
 469 #endif
 470                 if (!rq->handle_rx_cqe) {
 471                         err = -EINVAL;
 472                         netdev_err(c->netdev, "RX handler of MPWQE RQ is not set, err %d\n", err);
 473                         goto err_rq_wq_destroy;
 474                 }
 475
 476                 rq->mpwqe.skb_from_cqe_mpwrq = xsk ?
 477                         mlx5e_xsk_skb_from_cqe_mpwrq_linear :
 478                         mlx5e_rx_mpwqe_is_linear_skb(mdev, params, NULL) ?
 479                                 mlx5e_skb_from_cqe_mpwrq_linear :
 480                                 mlx5e_skb_from_cqe_mpwrq_nonlinear;
 481
 482                 rq->mpwqe.log_stride_sz = mlx5e_mpwqe_get_log_stride_size(mdev, params, xsk);
 483                 rq->mpwqe.num_strides =
 484                         BIT(mlx5e_mpwqe_get_log_num_strides(mdev, params, xsk));
 485
 486                 err = mlx5e_create_rq_umr_mkey(mdev, rq);
 487                 if (err)
 488                         goto err_rq_wq_destroy;
 489                 rq->mkey_be = cpu_to_be32(rq->umr_mkey.key);
 490
 491                 err = mlx5e_rq_alloc_mpwqe_info(rq, c);
 492                 if (err)
 493                         goto err_free;
 494                 break;
 495         default: /* MLX5_WQ_TYPE_CYCLIC */
 496                 err = mlx5_wq_cyc_create(mdev, &rqp->wq, rqc_wq, &rq->wqe.wq,
 497                                          &rq->wq_ctrl);
 498                 if (err)
 499                         return err;
 500
 501                 rq->wqe.wq.db = &rq->wqe.wq.db[MLX5_RCV_DBR];
 502
 503                 wq_sz = mlx5_wq_cyc_get_size(&rq->wqe.wq);
 504
 505                 if (xsk)
 506                         num_xsk_frames = wq_sz << rq->wqe.info.log_num_frags;
 507
 508                 rq->wqe.info = rqp->frags_info;
 509                 rq->wqe.frags =
 510                         kvzalloc_node(array_size(sizeof(*rq->wqe.frags),
 511                                         (wq_sz << rq->wqe.info.log_num_frags)),
 512                                       GFP_KERNEL, cpu_to_node(c->cpu));
 513                 if (!rq->wqe.frags) {
 514                         err = -ENOMEM;
 515                         goto err_free;
 516                 }
 517
 518                 err = mlx5e_init_di_list(rq, wq_sz, c->cpu);
 519                 if (err)
 520                         goto err_free;
 521
 522                 rq->post_wqes = mlx5e_post_rx_wqes;
 523                 rq->dealloc_wqe = mlx5e_dealloc_rx_wqe;
 524
 525 #ifdef CONFIG_MLX5_EN_IPSEC
 526                 if (c->priv->ipsec)
 527                         rq->handle_rx_cqe = mlx5e_ipsec_handle_rx_cqe;
 528                 else
 529 #endif
 530                         rq->handle_rx_cqe = c->priv->profile->rx_handlers.handle_rx_cqe;
 531                 if (!rq->handle_rx_cqe) {
 532                         err = -EINVAL;
 533                         netdev_err(c->netdev, "RX handler of RQ is not set, err %d\n", err);
 534                         goto err_free;
 535                 }
 536
 537                 rq->wqe.skb_from_cqe = xsk ?
 538                         mlx5e_xsk_skb_from_cqe_linear :
 539                         mlx5e_rx_is_linear_skb(params, NULL) ?
 540                                 mlx5e_skb_from_cqe_linear :
 541                                 mlx5e_skb_from_cqe_nonlinear;
 542                 rq->mkey_be = c->mkey_be;
 543         }
 544
 545         if (xsk) {
 546                 err = mlx5e_xsk_resize_reuseq(umem, num_xsk_frames);
 547                 if (unlikely(err)) {
 548                         mlx5_core_err(mdev, "Unable to allocate the Reuse Ring for %u frames\n",
 549                                       num_xsk_frames);
 550                         goto err_free;
 551                 }
 552
 553                 rq->zca.free = mlx5e_xsk_zca_free;
 554                 err = xdp_rxq_info_reg_mem_model(&rq->xdp_rxq,
 555                                                  MEM_TYPE_ZERO_COPY,
 556                                                  &rq->zca);
 557         } else {
 558                 /* Create a page_pool and register it with rxq */
 559                 pp_params.order     = 0;
 560                 pp_params.flags     = 0; /* No-internal DMA mapping in page_pool */
 561                 pp_params.pool_size = pool_size;
 562                 pp_params.nid       = cpu_to_node(c->cpu);
 563                 pp_params.dev       = c->pdev;
 564                 pp_params.dma_dir   = rq->buff.map_dir;
 565
 566                 /* page_pool can be used even when there is no rq->xdp_prog,
 567                  * given page_pool does not handle DMA mapping there is no
 568                  * required state to clear. And page_pool gracefully handle
 569                  * elevated refcnt.
 570                  */
 571                 rq->page_pool = page_pool_create(&pp_params);
 572                 if (IS_ERR(rq->page_pool)) {
 573                         err = PTR_ERR(rq->page_pool);
 574                         rq->page_pool = NULL;
 575                         goto err_free;
 576                 }
 577                 err = xdp_rxq_info_reg_mem_model(&rq->xdp_rxq,
 578                                                  MEM_TYPE_PAGE_POOL, rq->page_pool);
 579         }
 580         if (err)
 581                 goto err_free;
 582
 583         for (i = 0; i < wq_sz; i++) {
 584                 if (rq->wq_type == MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ) {
 585                         struct mlx5e_rx_wqe_ll *wqe =
 586                                 mlx5_wq_ll_get_wqe(&rq->mpwqe.wq, i);
 587                         u32 byte_count =
 588                                 rq->mpwqe.num_strides << rq->mpwqe.log_stride_sz;
 589                         u64 dma_offset = mlx5e_get_mpwqe_offset(rq, i);
 590
 591                         wqe->data[0].addr = cpu_to_be64(dma_offset + rq->buff.headroom);
 592                         wqe->data[0].byte_count = cpu_to_be32(byte_count);
 593                         wqe->data[0].lkey = rq->mkey_be;
 594                 } else {
 595                         struct mlx5e_rx_wqe_cyc *wqe =
 596                                 mlx5_wq_cyc_get_wqe(&rq->wqe.wq, i);
 597                         int f;
 598
 599                         for (f = 0; f < rq->wqe.info.num_frags; f++) {
 600                                 u32 frag_size = rq->wqe.info.arr[f].frag_size |
 601                                         MLX5_HW_START_PADDING;
 602
 603                                 wqe->data[f].byte_count = cpu_to_be32(frag_size);
 604                                 wqe->data[f].lkey = rq->mkey_be;
 605                         }
 606                         /* check if num_frags is not a pow of two */
 607                         if (rq->wqe.info.num_frags < (1 << rq->wqe.info.log_num_frags)) {
 608                                 wqe->data[f].byte_count = 0;
 609                                 wqe->data[f].lkey = cpu_to_be32(MLX5_INVALID_LKEY);
 610                                 wqe->data[f].addr = 0;
 611                         }
 612                 }
 613         }
 614
 615         INIT_WORK(&rq->dim.work, mlx5e_rx_dim_work);
 616
 617         switch (params->rx_cq_moderation.cq_period_mode) {
 618         case MLX5_CQ_PERIOD_MODE_START_FROM_CQE:
 619                 rq->dim.mode = DIM_CQ_PERIOD_MODE_START_FROM_CQE;
 620                 break;
 621         case MLX5_CQ_PERIOD_MODE_START_FROM_EQE:
 622         default:
 623                 rq->dim.mode = DIM_CQ_PERIOD_MODE_START_FROM_EQE;
 624         }
 625
 626         rq->page_cache.head = 0;
 627         rq->page_cache.tail = 0;
 628
 629         return 0;
 630
 631 err_free:
 632         switch (rq->wq_type) {
 633         case MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ:
 634                 kvfree(rq->mpwqe.info);
 635                 mlx5_core_destroy_mkey(mdev, &rq->umr_mkey);
 636                 break;
 637         default: /* MLX5_WQ_TYPE_CYCLIC */
 638                 kvfree(rq->wqe.frags);
 639                 mlx5e_free_di_list(rq);
 640         }
 641
 642 err_rq_wq_destroy:
 643         if (rq->xdp_prog)
 644                 bpf_prog_put(rq->xdp_prog);
 645         xdp_rxq_info_unreg(&rq->xdp_rxq);
 646         page_pool_destroy(rq->page_pool);
 647         mlx5_wq_destroy(&rq->wq_ctrl);
 648
 649         return err;
 650 }
 651
 652 static void mlx5e_free_rq(struct mlx5e_rq *rq)
 653 {
 654         int i;
 655
 656         if (rq->xdp_prog)
 657                 bpf_prog_put(rq->xdp_prog);
 658
 659         switch (rq->wq_type) {
 660         case MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ:
 661                 kvfree(rq->mpwqe.info);
 662                 mlx5_core_destroy_mkey(rq->mdev, &rq->umr_mkey);
 663                 break;
 664         default: /* MLX5_WQ_TYPE_CYCLIC */
 665                 kvfree(rq->wqe.frags);
 666                 mlx5e_free_di_list(rq);
 667         }
 668
 669         for (i = rq->page_cache.head; i != rq->page_cache.tail;
 670              i = (i + 1) & (MLX5E_CACHE_SIZE - 1)) {
 671                 struct mlx5e_dma_info *dma_info = &rq->page_cache.page_cache[i];
 672
 673                 /* With AF_XDP, page_cache is not used, so this loop is not
 674                  * entered, and it's safe to call mlx5e_page_release_dynamic
 675                  * directly.
 676                  */
 677                 mlx5e_page_release_dynamic(rq, dma_info, false);
 678         }
 679
 680         xdp_rxq_info_unreg(&rq->xdp_rxq);
 681         page_pool_destroy(rq->page_pool);
 682         mlx5_wq_destroy(&rq->wq_ctrl);
 683 }
 684
 685 static int mlx5e_create_rq(struct mlx5e_rq *rq,
 686                            struct mlx5e_rq_param *param)
 687 {
 688         struct mlx5_core_dev *mdev = rq->mdev;
 689
 690         void *in;
 691         void *rqc;
 692         void *wq;
 693         int inlen;
 694         int err;
 695
 696         inlen = MLX5_ST_SZ_BYTES(create_rq_in) +
 697                 sizeof(u64) * rq->wq_ctrl.buf.npages;
 698         in = kvzalloc(inlen, GFP_KERNEL);
 699         if (!in)
 700                 return -ENOMEM;
 701
 702         rqc = MLX5_ADDR_OF(create_rq_in, in, ctx);
 703         wq  = MLX5_ADDR_OF(rqc, rqc, wq);
 704
 705         memcpy(rqc, param->rqc, sizeof(param->rqc));
 706
 707         MLX5_SET(rqc,  rqc, cqn,                rq->cq.mcq.cqn);
 708         MLX5_SET(rqc,  rqc, state,              MLX5_RQC_STATE_RST);
 709         MLX5_SET(wq,   wq,  log_wq_pg_sz,       rq->wq_ctrl.buf.page_shift -
 710                                                 MLX5_ADAPTER_PAGE_SHIFT);
 711         MLX5_SET64(wq, wq,  dbr_addr,           rq->wq_ctrl.db.dma);
 712
 713         mlx5_fill_page_frag_array(&rq->wq_ctrl.buf,
 714                                   (__be64 *)MLX5_ADDR_OF(wq, wq, pas));
 715
 716         err = mlx5_core_create_rq(mdev, in, inlen, &rq->rqn);
 717
 718         kvfree(in);
 719
 720         return err;
 721 }
 722
 723 static int mlx5e_modify_rq_state(struct mlx5e_rq *rq, int curr_state,
 724                                  int next_state)
 725 {
 726         struct mlx5_core_dev *mdev = rq->mdev;
 727
 728         void *in;
 729         void *rqc;
 730         int inlen;
 731         int err;
 732
 733         inlen = MLX5_ST_SZ_BYTES(modify_rq_in);
 734         in = kvzalloc(inlen, GFP_KERNEL);
 735         if (!in)
 736                 return -ENOMEM;
 737
 738         rqc = MLX5_ADDR_OF(modify_rq_in, in, ctx);
 739
 740         MLX5_SET(modify_rq_in, in, rq_state, curr_state);
 741         MLX5_SET(rqc, rqc, state, next_state);
 742
 743         err = mlx5_core_modify_rq(mdev, rq->rqn, in, inlen);
 744
 745         kvfree(in);
 746
 747         return err;
 748 }
 749
 750 static int mlx5e_modify_rq_scatter_fcs(struct mlx5e_rq *rq, bool enable)
 751 {
 752         struct mlx5e_channel *c = rq->channel;
 753         struct mlx5e_priv *priv = c->priv;
 754         struct mlx5_core_dev *mdev = priv->mdev;
 755
 756         void *in;
 757         void *rqc;
 758         int inlen;
 759         int err;
 760
 761         inlen = MLX5_ST_SZ_BYTES(modify_rq_in);
 762         in = kvzalloc(inlen, GFP_KERNEL);
 763         if (!in)
 764                 return -ENOMEM;
 765
 766         rqc = MLX5_ADDR_OF(modify_rq_in, in, ctx);
 767
 768         MLX5_SET(modify_rq_in, in, rq_state, MLX5_RQC_STATE_RDY);
 769         MLX5_SET64(modify_rq_in, in, modify_bitmask,
 770                    MLX5_MODIFY_RQ_IN_MODIFY_BITMASK_SCATTER_FCS);
 771         MLX5_SET(rqc, rqc, scatter_fcs, enable);
 772         MLX5_SET(rqc, rqc, state, MLX5_RQC_STATE_RDY);
 773
 774         err = mlx5_core_modify_rq(mdev, rq->rqn, in, inlen);
 775
 776         kvfree(in);
 777
 778         return err;
 779 }
 780
 781 static int mlx5e_modify_rq_vsd(struct mlx5e_rq *rq, bool vsd)
 782 {
 783         struct mlx5e_channel *c = rq->channel;
 784         struct mlx5_core_dev *mdev = c->mdev;
 785         void *in;
 786         void *rqc;
 787         int inlen;
 788         int err;
 789
 790         inlen = MLX5_ST_SZ_BYTES(modify_rq_in);
 791         in = kvzalloc(inlen, GFP_KERNEL);
 792         if (!in)
 793                 return -ENOMEM;
 794
 795         rqc = MLX5_ADDR_OF(modify_rq_in, in, ctx);
 796
 797         MLX5_SET(modify_rq_in, in, rq_state, MLX5_RQC_STATE_RDY);
 798         MLX5_SET64(modify_rq_in, in, modify_bitmask,
 799                    MLX5_MODIFY_RQ_IN_MODIFY_BITMASK_VSD);
 800         MLX5_SET(rqc, rqc, vsd, vsd);
 801         MLX5_SET(rqc, rqc, state, MLX5_RQC_STATE_RDY);
 802
 803         err = mlx5_core_modify_rq(mdev, rq->rqn, in, inlen);
 804
 805         kvfree(in);
 806
 807         return err;
 808 }
 809
 810 static void mlx5e_destroy_rq(struct mlx5e_rq *rq)
 811 {
 812         mlx5_core_destroy_rq(rq->mdev, rq->rqn);
 813 }
 814
 815 int mlx5e_wait_for_min_rx_wqes(struct mlx5e_rq *rq, int wait_time)
 816 {
 817         unsigned long exp_time = jiffies + msecs_to_jiffies(wait_time);
 818         struct mlx5e_channel *c = rq->channel;
 819
 820         u16 min_wqes = mlx5_min_rx_wqes(rq->wq_type, mlx5e_rqwq_get_size(rq));
 821
 822         do {
 823                 if (mlx5e_rqwq_get_cur_sz(rq) >= min_wqes)
 824                         return 0;
 825
 826                 msleep(20);
 827         } while (time_before(jiffies, exp_time));
 828
 829         netdev_warn(c->netdev, "Failed to get min RX wqes on Channel[%d] RQN[0x%x] wq cur_sz(%d) min_rx_wqes(%d)\n",
 830                     c->ix, rq->rqn, mlx5e_rqwq_get_cur_sz(rq), min_wqes);
 831
 832         return -ETIMEDOUT;
 833 }
 834
 835 static void mlx5e_free_rx_descs(struct mlx5e_rq *rq)
 836 {
 837         __be16 wqe_ix_be;
 838         u16 wqe_ix;
 839
 840         if (rq->wq_type == MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ) {
 841                 struct mlx5_wq_ll *wq = &rq->mpwqe.wq;
 842                 u16 head = wq->head;
 843                 int i;
 844
 845                 /* Outstanding UMR WQEs (in progress) start at wq->head */
 846                 for (i = 0; i < rq->mpwqe.umr_in_progress; i++) {
 847                         rq->dealloc_wqe(rq, head);
 848                         head = mlx5_wq_ll_get_wqe_next_ix(wq, head);
 849                 }
 850
 851                 while (!mlx5_wq_ll_is_empty(wq)) {
 852                         struct mlx5e_rx_wqe_ll *wqe;
 853
 854                         wqe_ix_be = *wq->tail_next;
 855                         wqe_ix    = be16_to_cpu(wqe_ix_be);
 856                         wqe       = mlx5_wq_ll_get_wqe(wq, wqe_ix);
 857                         rq->dealloc_wqe(rq, wqe_ix);
 858                         mlx5_wq_ll_pop(wq, wqe_ix_be,
 859                                        &wqe->next.next_wqe_index);
 860                 }
 861         } else {
 862                 struct mlx5_wq_cyc *wq = &rq->wqe.wq;
 863
 864                 while (!mlx5_wq_cyc_is_empty(wq)) {
 865                         wqe_ix = mlx5_wq_cyc_get_tail(wq);
 866                         rq->dealloc_wqe(rq, wqe_ix);
 867                         mlx5_wq_cyc_pop(wq);
 868                 }
 869         }
 870
 871 }
 872
 873 int mlx5e_open_rq(struct mlx5e_channel *c, struct mlx5e_params *params,
 874                   struct mlx5e_rq_param *param, struct mlx5e_xsk_param *xsk,
 875                   struct xdp_umem *umem, struct mlx5e_rq *rq)
 876 {
 877         int err;
 878
 879         err = mlx5e_alloc_rq(c, params, xsk, umem, param, rq);
 880         if (err)
 881                 return err;
 882
 883         err = mlx5e_create_rq(rq, param);
 884         if (err)
 885                 goto err_free_rq;
 886
 887         err = mlx5e_modify_rq_state(rq, MLX5_RQC_STATE_RST, MLX5_RQC_STATE_RDY);
 888         if (err)
 889                 goto err_destroy_rq;
 890
 891         if (MLX5_CAP_ETH(c->mdev, cqe_checksum_full))
 892                 __set_bit(MLX5E_RQ_STATE_CSUM_FULL, &c->rq.state);
 893
 894         if (params->rx_dim_enabled)
 895                 __set_bit(MLX5E_RQ_STATE_AM, &c->rq.state);
 896
 897         /* We disable csum_complete when XDP is enabled since
 898          * XDP programs might manipulate packets which will render
 899          * skb->checksum incorrect.
 900          */
 901         if (MLX5E_GET_PFLAG(params, MLX5E_PFLAG_RX_NO_CSUM_COMPLETE) || c->xdp)
 902                 __set_bit(MLX5E_RQ_STATE_NO_CSUM_COMPLETE, &c->rq.state);
 903
 904         return 0;
 905
 906 err_destroy_rq:
 907         mlx5e_destroy_rq(rq);
 908 err_free_rq:
 909         mlx5e_free_rq(rq);
 910
 911         return err;
 912 }
 913
 914 static void mlx5e_activate_rq(struct mlx5e_rq *rq)
 915 {
 916         set_bit(MLX5E_RQ_STATE_ENABLED, &rq->state);
 917         mlx5e_trigger_irq(&rq->channel->icosq);
 918 }
 919
 920 void mlx5e_deactivate_rq(struct mlx5e_rq *rq)
 921 {
 922         clear_bit(MLX5E_RQ_STATE_ENABLED, &rq->state);
 923         napi_synchronize(&rq->channel->napi); /* prevent mlx5e_post_rx_wqes */
 924 }
 925
 926 void mlx5e_close_rq(struct mlx5e_rq *rq)
 927 {
 928         cancel_work_sync(&rq->dim.work);
 929         mlx5e_destroy_rq(rq);
 930         mlx5e_free_rx_descs(rq);
 931         mlx5e_free_rq(rq);
 932 }
 933
 934 static void mlx5e_free_xdpsq_db(struct mlx5e_xdpsq *sq)
 935 {
 936         kvfree(sq->db.xdpi_fifo.xi);
 937         kvfree(sq->db.wqe_info);
 938 }
 939
 940 static int mlx5e_alloc_xdpsq_fifo(struct mlx5e_xdpsq *sq, int numa)
 941 {
 942         struct mlx5e_xdp_info_fifo *xdpi_fifo = &sq->db.xdpi_fifo;
 943         int wq_sz        = mlx5_wq_cyc_get_size(&sq->wq);
 944         int dsegs_per_wq = wq_sz * MLX5_SEND_WQEBB_NUM_DS;
 945
 946         xdpi_fifo->xi = kvzalloc_node(sizeof(*xdpi_fifo->xi) * dsegs_per_wq,
 947                                       GFP_KERNEL, numa);
 948         if (!xdpi_fifo->xi)
 949                 return -ENOMEM;
 950
 951         xdpi_fifo->pc   = &sq->xdpi_fifo_pc;
 952         xdpi_fifo->cc   = &sq->xdpi_fifo_cc;
 953         xdpi_fifo->mask = dsegs_per_wq - 1;
 954
 955         return 0;
 956 }
 957
 958 static int mlx5e_alloc_xdpsq_db(struct mlx5e_xdpsq *sq, int numa)
 959 {
 960         int wq_sz = mlx5_wq_cyc_get_size(&sq->wq);
 961         int err;
 962
 963         sq->db.wqe_info = kvzalloc_node(sizeof(*sq->db.wqe_info) * wq_sz,
 964                                         GFP_KERNEL, numa);
 965         if (!sq->db.wqe_info)
 966                 return -ENOMEM;
 967
 968         err = mlx5e_alloc_xdpsq_fifo(sq, numa);
 969         if (err) {
 970                 mlx5e_free_xdpsq_db(sq);
 971                 return err;
 972         }
 973
 974         return 0;
 975 }
 976
 977 static int mlx5e_alloc_xdpsq(struct mlx5e_channel *c,
 978                              struct mlx5e_params *params,
 979                              struct xdp_umem *umem,
 980                              struct mlx5e_sq_param *param,
 981                              struct mlx5e_xdpsq *sq,
 982                              bool is_redirect)
 983 {
 984         void *sqc_wq               = MLX5_ADDR_OF(sqc, param->sqc, wq);
 985         struct mlx5_core_dev *mdev = c->mdev;
 986         struct mlx5_wq_cyc *wq = &sq->wq;
 987         int err;
 988
 989         sq->pdev      = c->pdev;
 990         sq->mkey_be   = c->mkey_be;
 991         sq->channel   = c;
 992         sq->uar_map   = mdev->mlx5e_res.bfreg.map;
 993         sq->min_inline_mode = params->tx_min_inline_mode;
 994         sq->hw_mtu    = MLX5E_SW2HW_MTU(params, params->sw_mtu);
 995         sq->umem      = umem;
 996
 997         sq->stats = sq->umem ?
 998                 &c->priv->channel_stats[c->ix].xsksq :
 999                 is_redirect ?
1000                         &c->priv->channel_stats[c->ix].xdpsq :
1001                         &c->priv->channel_stats[c->ix].rq_xdpsq;
1002
1003         param->wq.db_numa_node = cpu_to_node(c->cpu);
1004         err = mlx5_wq_cyc_create(mdev, &param->wq, sqc_wq, wq, &sq->wq_ctrl);
1005         if (err)
1006                 return err;
1007         wq->db = &wq->db[MLX5_SND_DBR];
1008
1009         err = mlx5e_alloc_xdpsq_db(sq, cpu_to_node(c->cpu));
1010         if (err)
1011                 goto err_sq_wq_destroy;
1012
1013         return 0;
1014
1015 err_sq_wq_destroy:
1016         mlx5_wq_destroy(&sq->wq_ctrl);
1017
1018         return err;
1019 }
1020
1021 static void mlx5e_free_xdpsq(struct mlx5e_xdpsq *sq)
1022 {
1023         mlx5e_free_xdpsq_db(sq);
1024         mlx5_wq_destroy(&sq->wq_ctrl);
1025 }
1026
1027 static void mlx5e_free_icosq_db(struct mlx5e_icosq *sq)
1028 {
1029         kvfree(sq->db.ico_wqe);
1030 }
1031
1032 static int mlx5e_alloc_icosq_db(struct mlx5e_icosq *sq, int numa)
1033 {
1034         int wq_sz = mlx5_wq_cyc_get_size(&sq->wq);
1035
1036         sq->db.ico_wqe = kvzalloc_node(array_size(wq_sz,
1037                                                   sizeof(*sq->db.ico_wqe)),
1038                                        GFP_KERNEL, numa);
1039         if (!sq->db.ico_wqe)
1040                 return -ENOMEM;
1041
1042         return 0;
1043 }
1044
1045 static int mlx5e_alloc_icosq(struct mlx5e_channel *c,
1046                              struct mlx5e_sq_param *param,
1047                              struct mlx5e_icosq *sq)
1048 {
1049         void *sqc_wq               = MLX5_ADDR_OF(sqc, param->sqc, wq);
1050         struct mlx5_core_dev *mdev = c->mdev;
1051         struct mlx5_wq_cyc *wq = &sq->wq;
1052         int err;
1053
1054         sq->channel   = c;
1055         sq->uar_map   = mdev->mlx5e_res.bfreg.map;
1056
1057         param->wq.db_numa_node = cpu_to_node(c->cpu);
1058         err = mlx5_wq_cyc_create(mdev, &param->wq, sqc_wq, wq, &sq->wq_ctrl);
1059         if (err)
1060                 return err;
1061         wq->db = &wq->db[MLX5_SND_DBR];
1062
1063         err = mlx5e_alloc_icosq_db(sq, cpu_to_node(c->cpu));
1064         if (err)
1065                 goto err_sq_wq_destroy;
1066
1067         return 0;
1068
1069 err_sq_wq_destroy:
1070         mlx5_wq_destroy(&sq->wq_ctrl);
1071
1072         return err;
1073 }
1074
1075 static void mlx5e_free_icosq(struct mlx5e_icosq *sq)
1076 {
1077         mlx5e_free_icosq_db(sq);
1078         mlx5_wq_destroy(&sq->wq_ctrl);
1079 }
1080
1081 static void mlx5e_free_txqsq_db(struct mlx5e_txqsq *sq)
1082 {
1083         kvfree(sq->db.wqe_info);
1084         kvfree(sq->db.dma_fifo);
1085 }
1086
1087 static int mlx5e_alloc_txqsq_db(struct mlx5e_txqsq *sq, int numa)
1088 {
1089         int wq_sz = mlx5_wq_cyc_get_size(&sq->wq);
1090         int df_sz = wq_sz * MLX5_SEND_WQEBB_NUM_DS;
1091
1092         sq->db.dma_fifo = kvzalloc_node(array_size(df_sz,
1093                                                    sizeof(*sq->db.dma_fifo)),
1094                                         GFP_KERNEL, numa);
1095         sq->db.wqe_info = kvzalloc_node(array_size(wq_sz,
1096                                                    sizeof(*sq->db.wqe_info)),
1097                                         GFP_KERNEL, numa);
1098         if (!sq->db.dma_fifo || !sq->db.wqe_info) {
1099                 mlx5e_free_txqsq_db(sq);
1100                 return -ENOMEM;
1101         }
1102
1103         sq->dma_fifo_mask = df_sz - 1;
1104
1105         return 0;
1106 }
1107
1108 static void mlx5e_tx_err_cqe_work(struct work_struct *recover_work);
1109 static int mlx5e_alloc_txqsq(struct mlx5e_channel *c,
1110                              int txq_ix,
1111                              struct mlx5e_params *params,
1112                              struct mlx5e_sq_param *param,
1113                              struct mlx5e_txqsq *sq,
1114                              int tc)
1115 {
1116         void *sqc_wq               = MLX5_ADDR_OF(sqc, param->sqc, wq);
1117         struct mlx5_core_dev *mdev = c->mdev;
1118         struct mlx5_wq_cyc *wq = &sq->wq;
1119         int err;
1120
1121         sq->pdev      = c->pdev;
1122         sq->tstamp    = c->tstamp;
1123         sq->clock     = &mdev->clock;
1124         sq->mkey_be   = c->mkey_be;
1125         sq->channel   = c;
1126         sq->ch_ix     = c->ix;
1127         sq->txq_ix    = txq_ix;
1128         sq->uar_map   = mdev->mlx5e_res.bfreg.map;
1129         sq->min_inline_mode = params->tx_min_inline_mode;
1130         sq->stats     = &c->priv->channel_stats[c->ix].sq[tc];
1131         sq->stop_room = MLX5E_SQ_STOP_ROOM;
1132         INIT_WORK(&sq->recover_work, mlx5e_tx_err_cqe_work);
1133         if (MLX5_IPSEC_DEV(c->priv->mdev))
1134                 set_bit(MLX5E_SQ_STATE_IPSEC, &sq->state);
1135         if (mlx5_accel_is_tls_device(c->priv->mdev)) {
1136                 set_bit(MLX5E_SQ_STATE_TLS, &sq->state);
1137                 sq->stop_room += MLX5E_SQ_TLS_ROOM;
1138         }
1139
1140         param->wq.db_numa_node = cpu_to_node(c->cpu);
1141         err = mlx5_wq_cyc_create(mdev, &param->wq, sqc_wq, wq, &sq->wq_ctrl);
1142         if (err)
1143                 return err;
1144         wq->db    = &wq->db[MLX5_SND_DBR];
1145
1146         err = mlx5e_alloc_txqsq_db(sq, cpu_to_node(c->cpu));
1147         if (err)
1148                 goto err_sq_wq_destroy;
1149
1150         INIT_WORK(&sq->dim.work, mlx5e_tx_dim_work);
1151         sq->dim.mode = params->tx_cq_moderation.cq_period_mode;
1152
1153         return 0;
1154
1155 err_sq_wq_destroy:
1156         mlx5_wq_destroy(&sq->wq_ctrl);
1157
1158         return err;
1159 }
1160
1161 static void mlx5e_free_txqsq(struct mlx5e_txqsq *sq)
1162 {
1163         mlx5e_free_txqsq_db(sq);
1164         mlx5_wq_destroy(&sq->wq_ctrl);
1165 }
1166
1167 struct mlx5e_create_sq_param {
1168         struct mlx5_wq_ctrl        *wq_ctrl;
1169         u32                         cqn;
1170         u32                         tisn;
1171         u8                          tis_lst_sz;
1172         u8                          min_inline_mode;
1173 };
1174
1175 static int mlx5e_create_sq(struct mlx5_core_dev *mdev,
1176                            struct mlx5e_sq_param *param,
1177                            struct mlx5e_create_sq_param *csp,
1178                            u32 *sqn)
1179 {
1180         void *in;
1181         void *sqc;
1182         void *wq;
1183         int inlen;
1184         int err;
1185
1186         inlen = MLX5_ST_SZ_BYTES(create_sq_in) +
1187                 sizeof(u64) * csp->wq_ctrl->buf.npages;
1188         in = kvzalloc(inlen, GFP_KERNEL);
1189         if (!in)
1190                 return -ENOMEM;
1191
1192         sqc = MLX5_ADDR_OF(create_sq_in, in, ctx);
1193         wq = MLX5_ADDR_OF(sqc, sqc, wq);
1194
1195         memcpy(sqc, param->sqc, sizeof(param->sqc));
1196         MLX5_SET(sqc,  sqc, tis_lst_sz, csp->tis_lst_sz);
1197         MLX5_SET(sqc,  sqc, tis_num_0, csp->tisn);
1198         MLX5_SET(sqc,  sqc, cqn, csp->cqn);
1199
1200         if (MLX5_CAP_ETH(mdev, wqe_inline_mode) == MLX5_CAP_INLINE_MODE_VPORT_CONTEXT)
1201                 MLX5_SET(sqc,  sqc, min_wqe_inline_mode, csp->min_inline_mode);
1202
1203         MLX5_SET(sqc,  sqc, state, MLX5_SQC_STATE_RST);
1204         MLX5_SET(sqc,  sqc, flush_in_error_en, 1);
1205
1206         MLX5_SET(wq,   wq, wq_type,       MLX5_WQ_TYPE_CYCLIC);
1207         MLX5_SET(wq,   wq, uar_page,      mdev->mlx5e_res.bfreg.index);
1208         MLX5_SET(wq,   wq, log_wq_pg_sz,  csp->wq_ctrl->buf.page_shift -
1209                                           MLX5_ADAPTER_PAGE_SHIFT);
1210         MLX5_SET64(wq, wq, dbr_addr,      csp->wq_ctrl->db.dma);
1211
1212         mlx5_fill_page_frag_array(&csp->wq_ctrl->buf,
1213                                   (__be64 *)MLX5_ADDR_OF(wq, wq, pas));
1214
1215         err = mlx5_core_create_sq(mdev, in, inlen, sqn);
1216
1217         kvfree(in);
1218
1219         return err;
1220 }
1221
1222 int mlx5e_modify_sq(struct mlx5_core_dev *mdev, u32 sqn,
1223                     struct mlx5e_modify_sq_param *p)
1224 {
1225         void *in;
1226         void *sqc;
1227         int inlen;
1228         int err;
1229
1230         inlen = MLX5_ST_SZ_BYTES(modify_sq_in);
1231         in = kvzalloc(inlen, GFP_KERNEL);
1232         if (!in)
1233                 return -ENOMEM;
1234
1235         sqc = MLX5_ADDR_OF(modify_sq_in, in, ctx);
1236
1237         MLX5_SET(modify_sq_in, in, sq_state, p->curr_state);
1238         MLX5_SET(sqc, sqc, state, p->next_state);
1239         if (p->rl_update && p->next_state == MLX5_SQC_STATE_RDY) {
1240                 MLX5_SET64(modify_sq_in, in, modify_bitmask, 1);
1241                 MLX5_SET(sqc,  sqc, packet_pacing_rate_limit_index, p->rl_index);
1242         }
1243
1244         err = mlx5_core_modify_sq(mdev, sqn, in, inlen);
1245
1246         kvfree(in);
1247
1248         return err;
1249 }
1250
1251 static void mlx5e_destroy_sq(struct mlx5_core_dev *mdev, u32 sqn)
1252 {
1253         mlx5_core_destroy_sq(mdev, sqn);
1254 }
1255
1256 static int mlx5e_create_sq_rdy(struct mlx5_core_dev *mdev,
1257                                struct mlx5e_sq_param *param,
1258                                struct mlx5e_create_sq_param *csp,
1259                                u32 *sqn)
1260 {
1261         struct mlx5e_modify_sq_param msp = {0};
1262         int err;
1263
1264         err = mlx5e_create_sq(mdev, param, csp, sqn);
1265         if (err)
1266                 return err;
1267
1268         msp.curr_state = MLX5_SQC_STATE_RST;
1269         msp.next_state = MLX5_SQC_STATE_RDY;
1270         err = mlx5e_modify_sq(mdev, *sqn, &msp);
1271         if (err)
1272                 mlx5e_destroy_sq(mdev, *sqn);
1273
1274         return err;
1275 }
1276
1277 static int mlx5e_set_sq_maxrate(struct net_device *dev,
1278                                 struct mlx5e_txqsq *sq, u32 rate);
1279
1280 static int mlx5e_open_txqsq(struct mlx5e_channel *c,
1281                             u32 tisn,
1282                             int txq_ix,
1283                             struct mlx5e_params *params,
1284                             struct mlx5e_sq_param *param,
1285                             struct mlx5e_txqsq *sq,
1286                             int tc)
1287 {
1288         struct mlx5e_create_sq_param csp = {};
1289         u32 tx_rate;
1290         int err;
1291
1292         err = mlx5e_alloc_txqsq(c, txq_ix, params, param, sq, tc);
1293         if (err)
1294                 return err;
1295
1296         csp.tisn            = tisn;
1297         csp.tis_lst_sz      = 1;
1298         csp.cqn             = sq->cq.mcq.cqn;
1299         csp.wq_ctrl         = &sq->wq_ctrl;
1300         csp.min_inline_mode = sq->min_inline_mode;
1301         err = mlx5e_create_sq_rdy(c->mdev, param, &csp, &sq->sqn);
1302         if (err)
1303                 goto err_free_txqsq;
1304
1305         tx_rate = c->priv->tx_rates[sq->txq_ix];
1306         if (tx_rate)
1307                 mlx5e_set_sq_maxrate(c->netdev, sq, tx_rate);
1308
1309         if (params->tx_dim_enabled)
1310                 sq->state |= BIT(MLX5E_SQ_STATE_AM);
1311
1312         return 0;
1313
1314 err_free_txqsq:
1315         clear_bit(MLX5E_SQ_STATE_ENABLED, &sq->state);
1316         mlx5e_free_txqsq(sq);
1317
1318         return err;
1319 }
1320
1321 void mlx5e_activate_txqsq(struct mlx5e_txqsq *sq)
1322 {
1323         sq->txq = netdev_get_tx_queue(sq->channel->netdev, sq->txq_ix);
1324         set_bit(MLX5E_SQ_STATE_ENABLED, &sq->state);
1325         netdev_tx_reset_queue(sq->txq);
1326         netif_tx_start_queue(sq->txq);
1327 }
1328
1329 void mlx5e_tx_disable_queue(struct netdev_queue *txq)
1330 {
1331         __netif_tx_lock_bh(txq);
1332         netif_tx_stop_queue(txq);
1333         __netif_tx_unlock_bh(txq);
1334 }
1335
1336 static void mlx5e_deactivate_txqsq(struct mlx5e_txqsq *sq)
1337 {
1338         struct mlx5e_channel *c = sq->channel;
1339         struct mlx5_wq_cyc *wq = &sq->wq;
1340
1341         clear_bit(MLX5E_SQ_STATE_ENABLED, &sq->state);
1342         /* prevent netif_tx_wake_queue */
1343         napi_synchronize(&c->napi);
1344
1345         mlx5e_tx_disable_queue(sq->txq);
1346
1347         /* last doorbell out, godspeed .. */
1348         if (mlx5e_wqc_has_room_for(wq, sq->cc, sq->pc, 1)) {
1349                 u16 pi = mlx5_wq_cyc_ctr2ix(wq, sq->pc);
1350                 struct mlx5e_tx_wqe *nop;
1351
1352                 sq->db.wqe_info[pi].skb = NULL;
1353                 nop = mlx5e_post_nop(wq, sq->sqn, &sq->pc);
1354                 mlx5e_notify_hw(wq, sq->pc, sq->uar_map, &nop->ctrl);
1355         }
1356 }
1357
1358 static void mlx5e_close_txqsq(struct mlx5e_txqsq *sq)
1359 {
1360         struct mlx5e_channel *c = sq->channel;
1361         struct mlx5_core_dev *mdev = c->mdev;
1362         struct mlx5_rate_limit rl = {0};
1363
1364         cancel_work_sync(&sq->dim.work);
1365         cancel_work_sync(&sq->recover_work);
1366         mlx5e_destroy_sq(mdev, sq->sqn);
1367         if (sq->rate_limit) {
1368                 rl.rate = sq->rate_limit;
1369                 mlx5_rl_remove_rate(mdev, &rl);
1370         }
1371         mlx5e_free_txqsq_descs(sq);
1372         mlx5e_free_txqsq(sq);
1373 }
1374
1375 static void mlx5e_tx_err_cqe_work(struct work_struct *recover_work)
1376 {
1377         struct mlx5e_txqsq *sq = container_of(recover_work, struct mlx5e_txqsq,
1378                                               recover_work);
1379
1380         mlx5e_tx_reporter_err_cqe(sq);
1381 }
1382
1383 int mlx5e_open_icosq(struct mlx5e_channel *c, struct mlx5e_params *params,
1384                      struct mlx5e_sq_param *param, struct mlx5e_icosq *sq)
1385 {
1386         struct mlx5e_create_sq_param csp = {};
1387         int err;
1388
1389         err = mlx5e_alloc_icosq(c, param, sq);
1390         if (err)
1391                 return err;
1392
1393         csp.cqn             = sq->cq.mcq.cqn;
1394         csp.wq_ctrl         = &sq->wq_ctrl;
1395         csp.min_inline_mode = params->tx_min_inline_mode;
1396         set_bit(MLX5E_SQ_STATE_ENABLED, &sq->state);
1397         err = mlx5e_create_sq_rdy(c->mdev, param, &csp, &sq->sqn);
1398         if (err)
1399                 goto err_free_icosq;
1400
1401         return 0;
1402
1403 err_free_icosq:
1404         clear_bit(MLX5E_SQ_STATE_ENABLED, &sq->state);
1405         mlx5e_free_icosq(sq);
1406
1407         return err;
1408 }
1409
1410 void mlx5e_close_icosq(struct mlx5e_icosq *sq)
1411 {
1412         struct mlx5e_channel *c = sq->channel;
1413
1414         clear_bit(MLX5E_SQ_STATE_ENABLED, &sq->state);
1415         napi_synchronize(&c->napi);
1416
1417         mlx5e_destroy_sq(c->mdev, sq->sqn);
1418         mlx5e_free_icosq(sq);
1419 }
1420
1421 int mlx5e_open_xdpsq(struct mlx5e_channel *c, struct mlx5e_params *params,
1422                      struct mlx5e_sq_param *param, struct xdp_umem *umem,
1423                      struct mlx5e_xdpsq *sq, bool is_redirect)
1424 {
1425         struct mlx5e_create_sq_param csp = {};
1426         int err;
1427
1428         err = mlx5e_alloc_xdpsq(c, params, umem, param, sq, is_redirect);
1429         if (err)
1430                 return err;
1431
1432         csp.tis_lst_sz      = 1;
1433         csp.tisn            = c->priv->tisn[0]; /* tc = 0 */
1434         csp.cqn             = sq->cq.mcq.cqn;
1435         csp.wq_ctrl         = &sq->wq_ctrl;
1436         csp.min_inline_mode = sq->min_inline_mode;
1437         set_bit(MLX5E_SQ_STATE_ENABLED, &sq->state);
1438         err = mlx5e_create_sq_rdy(c->mdev, param, &csp, &sq->sqn);
1439         if (err)
1440                 goto err_free_xdpsq;
1441
1442         mlx5e_set_xmit_fp(sq, param->is_mpw);
1443
1444         if (!param->is_mpw) {
1445                 unsigned int ds_cnt = MLX5E_XDP_TX_DS_COUNT;
1446                 unsigned int inline_hdr_sz = 0;
1447                 int i;
1448
1449                 if (sq->min_inline_mode != MLX5_INLINE_MODE_NONE) {
1450                         inline_hdr_sz = MLX5E_XDP_MIN_INLINE;
1451                         ds_cnt++;
1452                 }
1453
1454                 /* Pre initialize fixed WQE fields */
1455                 for (i = 0; i < mlx5_wq_cyc_get_size(&sq->wq); i++) {
1456                         struct mlx5e_xdp_wqe_info *wi  = &sq->db.wqe_info[i];
1457                         struct mlx5e_tx_wqe      *wqe  = mlx5_wq_cyc_get_wqe(&sq->wq, i);
1458                         struct mlx5_wqe_ctrl_seg *cseg = &wqe->ctrl;
1459                         struct mlx5_wqe_eth_seg  *eseg = &wqe->eth;
1460                         struct mlx5_wqe_data_seg *dseg;
1461
1462                         cseg->qpn_ds = cpu_to_be32((sq->sqn << 8) | ds_cnt);
1463                         eseg->inline_hdr.sz = cpu_to_be16(inline_hdr_sz);
1464
1465                         dseg = (struct mlx5_wqe_data_seg *)cseg + (ds_cnt - 1);
1466                         dseg->lkey = sq->mkey_be;
1467
1468                         wi->num_wqebbs = 1;
1469                         wi->num_pkts   = 1;
1470                 }
1471         }
1472
1473         return 0;
1474
1475 err_free_xdpsq:
1476         clear_bit(MLX5E_SQ_STATE_ENABLED, &sq->state);
1477         mlx5e_free_xdpsq(sq);
1478
1479         return err;
1480 }
1481
1482 void mlx5e_close_xdpsq(struct mlx5e_xdpsq *sq)
1483 {
1484         struct mlx5e_channel *c = sq->channel;
1485
1486         clear_bit(MLX5E_SQ_STATE_ENABLED, &sq->state);
1487         napi_synchronize(&c->napi);
1488
1489         mlx5e_destroy_sq(c->mdev, sq->sqn);
1490         mlx5e_free_xdpsq_descs(sq);
1491         mlx5e_free_xdpsq(sq);
1492 }
1493
1494 static int mlx5e_alloc_cq_common(struct mlx5_core_dev *mdev,
1495                                  struct mlx5e_cq_param *param,
1496                                  struct mlx5e_cq *cq)
1497 {
1498         struct mlx5_core_cq *mcq = &cq->mcq;
1499         int eqn_not_used;
1500         unsigned int irqn;
1501         int err;
1502         u32 i;
1503
1504         err = mlx5_vector2eqn(mdev, param->eq_ix, &eqn_not_used, &irqn);
1505         if (err)
1506                 return err;
1507
1508         err = mlx5_cqwq_create(mdev, &param->wq, param->cqc, &cq->wq,
1509                                &cq->wq_ctrl);
1510         if (err)
1511                 return err;
1512
1513         mcq->cqe_sz     = 64;
1514         mcq->set_ci_db  = cq->wq_ctrl.db.db;
1515         mcq->arm_db     = cq->wq_ctrl.db.db + 1;
1516         *mcq->set_ci_db = 0;
1517         *mcq->arm_db    = 0;
1518         mcq->vector     = param->eq_ix;
1519         mcq->comp       = mlx5e_completion_event;
1520         mcq->event      = mlx5e_cq_error_event;
1521         mcq->irqn       = irqn;
1522
1523         for (i = 0; i < mlx5_cqwq_get_size(&cq->wq); i++) {
1524                 struct mlx5_cqe64 *cqe = mlx5_cqwq_get_wqe(&cq->wq, i);
1525
1526                 cqe->op_own = 0xf1;
1527         }
1528
1529         cq->mdev = mdev;
1530
1531         return 0;
1532 }
1533
1534 static int mlx5e_alloc_cq(struct mlx5e_channel *c,
1535                           struct mlx5e_cq_param *param,
1536                           struct mlx5e_cq *cq)
1537 {
1538         struct mlx5_core_dev *mdev = c->priv->mdev;
1539         int err;
1540
1541         param->wq.buf_numa_node = cpu_to_node(c->cpu);
1542         param->wq.db_numa_node  = cpu_to_node(c->cpu);
1543         param->eq_ix   = c->ix;
1544
1545         err = mlx5e_alloc_cq_common(mdev, param, cq);
1546
1547         cq->napi    = &c->napi;
1548         cq->channel = c;
1549
1550         return err;
1551 }
1552
1553 static void mlx5e_free_cq(struct mlx5e_cq *cq)
1554 {
1555         mlx5_wq_destroy(&cq->wq_ctrl);
1556 }
1557
1558 static int mlx5e_create_cq(struct mlx5e_cq *cq, struct mlx5e_cq_param *param)
1559 {
1560         u32 out[MLX5_ST_SZ_DW(create_cq_out)];
1561         struct mlx5_core_dev *mdev = cq->mdev;
1562         struct mlx5_core_cq *mcq = &cq->mcq;
1563
1564         void *in;
1565         void *cqc;
1566         int inlen;
1567         unsigned int irqn_not_used;
1568         int eqn;
1569         int err;
1570
1571         err = mlx5_vector2eqn(mdev, param->eq_ix, &eqn, &irqn_not_used);
1572         if (err)
1573                 return err;
1574
1575         inlen = MLX5_ST_SZ_BYTES(create_cq_in) +
1576                 sizeof(u64) * cq->wq_ctrl.buf.npages;
1577         in = kvzalloc(inlen, GFP_KERNEL);
1578         if (!in)
1579                 return -ENOMEM;
1580
1581         cqc = MLX5_ADDR_OF(create_cq_in, in, cq_context);
1582
1583         memcpy(cqc, param->cqc, sizeof(param->cqc));
1584
1585         mlx5_fill_page_frag_array(&cq->wq_ctrl.buf,
1586                                   (__be64 *)MLX5_ADDR_OF(create_cq_in, in, pas));
1587
1588         MLX5_SET(cqc,   cqc, cq_period_mode, param->cq_period_mode);
1589         MLX5_SET(cqc,   cqc, c_eqn,         eqn);
1590         MLX5_SET(cqc,   cqc, uar_page,      mdev->priv.uar->index);
1591         MLX5_SET(cqc,   cqc, log_page_size, cq->wq_ctrl.buf.page_shift -
1592                                             MLX5_ADAPTER_PAGE_SHIFT);
1593         MLX5_SET64(cqc, cqc, dbr_addr,      cq->wq_ctrl.db.dma);
1594
1595         err = mlx5_core_create_cq(mdev, mcq, in, inlen, out, sizeof(out));
1596
1597         kvfree(in);
1598
1599         if (err)
1600                 return err;
1601
1602         mlx5e_cq_arm(cq);
1603
1604         return 0;
1605 }
1606
1607 static void mlx5e_destroy_cq(struct mlx5e_cq *cq)
1608 {
1609         mlx5_core_destroy_cq(cq->mdev, &cq->mcq);
1610 }
1611
1612 int mlx5e_open_cq(struct mlx5e_channel *c, struct dim_cq_moder moder,
1613                   struct mlx5e_cq_param *param, struct mlx5e_cq *cq)
1614 {
1615         struct mlx5_core_dev *mdev = c->mdev;
1616         int err;
1617
1618         err = mlx5e_alloc_cq(c, param, cq);
1619         if (err)
1620                 return err;
1621
1622         err = mlx5e_create_cq(cq, param);
1623         if (err)
1624                 goto err_free_cq;
1625
1626         if (MLX5_CAP_GEN(mdev, cq_moderation))
1627                 mlx5_core_modify_cq_moderation(mdev, &cq->mcq, moder.usec, moder.pkts);
1628         return 0;
1629
1630 err_free_cq:
1631         mlx5e_free_cq(cq);
1632
1633         return err;
1634 }
1635
1636 void mlx5e_close_cq(struct mlx5e_cq *cq)
1637 {
1638         mlx5e_destroy_cq(cq);
1639         mlx5e_free_cq(cq);
1640 }
1641
1642 static int mlx5e_open_tx_cqs(struct mlx5e_channel *c,
1643                              struct mlx5e_params *params,
1644                              struct mlx5e_channel_param *cparam)
1645 {
1646         int err;
1647         int tc;
1648
1649         for (tc = 0; tc < c->num_tc; tc++) {
1650                 err = mlx5e_open_cq(c, params->tx_cq_moderation,
1651                                     &cparam->tx_cq, &c->sq[tc].cq);
1652                 if (err)
1653                         goto err_close_tx_cqs;
1654         }
1655
1656         return 0;
1657
1658 err_close_tx_cqs:
1659         for (tc--; tc >= 0; tc--)
1660                 mlx5e_close_cq(&c->sq[tc].cq);
1661
1662         return err;
1663 }
1664
1665 static void mlx5e_close_tx_cqs(struct mlx5e_channel *c)
1666 {
1667         int tc;
1668
1669         for (tc = 0; tc < c->num_tc; tc++)
1670                 mlx5e_close_cq(&c->sq[tc].cq);
1671 }
1672
1673 static int mlx5e_open_sqs(struct mlx5e_channel *c,
1674                           struct mlx5e_params *params,
1675                           struct mlx5e_channel_param *cparam)
1676 {
1677         struct mlx5e_priv *priv = c->priv;
1678         int err, tc;
1679
1680         for (tc = 0; tc < params->num_tc; tc++) {
1681                 int txq_ix = c->ix + tc * priv->max_nch;
1682
1683                 err = mlx5e_open_txqsq(c, c->priv->tisn[tc], txq_ix,
1684                                        params, &cparam->sq, &c->sq[tc], tc);
1685                 if (err)
1686                         goto err_close_sqs;
1687         }
1688
1689         return 0;
1690
1691 err_close_sqs:
1692         for (tc--; tc >= 0; tc--)
1693                 mlx5e_close_txqsq(&c->sq[tc]);
1694
1695         return err;
1696 }
1697
1698 static void mlx5e_close_sqs(struct mlx5e_channel *c)
1699 {
1700         int tc;
1701
1702         for (tc = 0; tc < c->num_tc; tc++)
1703                 mlx5e_close_txqsq(&c->sq[tc]);
1704 }
1705
1706 static int mlx5e_set_sq_maxrate(struct net_device *dev,
1707                                 struct mlx5e_txqsq *sq, u32 rate)
1708 {
1709         struct mlx5e_priv *priv = netdev_priv(dev);
1710         struct mlx5_core_dev *mdev = priv->mdev;
1711         struct mlx5e_modify_sq_param msp = {0};
1712         struct mlx5_rate_limit rl = {0};
1713         u16 rl_index = 0;
1714         int err;
1715
1716         if (rate == sq->rate_limit)
1717                 /* nothing to do */
1718                 return 0;
1719
1720         if (sq->rate_limit) {
1721                 rl.rate = sq->rate_limit;
1722                 /* remove current rl index to free space to next ones */
1723                 mlx5_rl_remove_rate(mdev, &rl);
1724         }
1725
1726         sq->rate_limit = 0;
1727
1728         if (rate) {
1729                 rl.rate = rate;
1730                 err = mlx5_rl_add_rate(mdev, &rl_index, &rl);
1731                 if (err) {
1732                         netdev_err(dev, "Failed configuring rate %u: %d\n",
1733                                    rate, err);
1734                         return err;
1735                 }
1736         }
1737
1738         msp.curr_state = MLX5_SQC_STATE_RDY;
1739         msp.next_state = MLX5_SQC_STATE_RDY;
1740         msp.rl_index   = rl_index;
1741         msp.rl_update  = true;
1742         err = mlx5e_modify_sq(mdev, sq->sqn, &msp);
1743         if (err) {
1744                 netdev_err(dev, "Failed configuring rate %u: %d\n",
1745                            rate, err);
1746                 /* remove the rate from the table */
1747                 if (rate)
1748                         mlx5_rl_remove_rate(mdev, &rl);
1749                 return err;
1750         }
1751
1752         sq->rate_limit = rate;
1753         return 0;
1754 }
1755
1756 static int mlx5e_set_tx_maxrate(struct net_device *dev, int index, u32 rate)
1757 {
1758         struct mlx5e_priv *priv = netdev_priv(dev);
1759         struct mlx5_core_dev *mdev = priv->mdev;
1760         struct mlx5e_txqsq *sq = priv->txq2sq[index];
1761         int err = 0;
1762
1763         if (!mlx5_rl_is_supported(mdev)) {
1764                 netdev_err(dev, "Rate limiting is not supported on this device\n");
1765                 return -EINVAL;
1766         }
1767
1768         /* rate is given in Mb/sec, HW config is in Kb/sec */
1769         rate = rate << 10;
1770
1771         /* Check whether rate in valid range, 0 is always valid */
1772         if (rate && !mlx5_rl_is_in_range(mdev, rate)) {
1773                 netdev_err(dev, "TX rate %u, is not in range\n", rate);
1774                 return -ERANGE;
1775         }
1776
1777         mutex_lock(&priv->state_lock);
1778         if (test_bit(MLX5E_STATE_OPENED, &priv->state))
1779                 err = mlx5e_set_sq_maxrate(dev, sq, rate);
1780         if (!err)
1781                 priv->tx_rates[index] = rate;
1782         mutex_unlock(&priv->state_lock);
1783
1784         return err;
1785 }
1786
1787 static int mlx5e_alloc_xps_cpumask(struct mlx5e_channel *c,
1788                                    struct mlx5e_params *params)
1789 {
1790         int num_comp_vectors = mlx5_comp_vectors_count(c->mdev);
1791         int irq;
1792
1793         if (!zalloc_cpumask_var(&c->xps_cpumask, GFP_KERNEL))
1794                 return -ENOMEM;
1795
1796         for (irq = c->ix; irq < num_comp_vectors; irq += params->num_channels) {
1797                 int cpu = cpumask_first(mlx5_comp_irq_get_affinity_mask(c->mdev, irq));
1798
1799                 cpumask_set_cpu(cpu, c->xps_cpumask);
1800         }
1801
1802         return 0;
1803 }
1804
1805 static void mlx5e_free_xps_cpumask(struct mlx5e_channel *c)
1806 {
1807         free_cpumask_var(c->xps_cpumask);
1808 }
1809
1810 static int mlx5e_open_queues(struct mlx5e_channel *c,
1811                              struct mlx5e_params *params,
1812                              struct mlx5e_channel_param *cparam)
1813 {
1814         struct dim_cq_moder icocq_moder = {0, 0};
1815         int err;
1816
1817         err = mlx5e_open_cq(c, icocq_moder, &cparam->icosq_cq, &c->icosq.cq);
1818         if (err)
1819                 return err;
1820
1821         err = mlx5e_open_tx_cqs(c, params, cparam);
1822         if (err)
1823                 goto err_close_icosq_cq;
1824
1825         err = mlx5e_open_cq(c, params->tx_cq_moderation, &cparam->tx_cq, &c->xdpsq.cq);
1826         if (err)
1827                 goto err_close_tx_cqs;
1828
1829         err = mlx5e_open_cq(c, params->rx_cq_moderation, &cparam->rx_cq, &c->rq.cq);
1830         if (err)
1831                 goto err_close_xdp_tx_cqs;
1832
1833         /* XDP SQ CQ params are same as normal TXQ sq CQ params */
1834         err = c->xdp ? mlx5e_open_cq(c, params->tx_cq_moderation,
1835                                      &cparam->tx_cq, &c->rq_xdpsq.cq) : 0;
1836         if (err)
1837                 goto err_close_rx_cq;
1838
1839         napi_enable(&c->napi);
1840
1841         err = mlx5e_open_icosq(c, params, &cparam->icosq, &c->icosq);
1842         if (err)
1843                 goto err_disable_napi;
1844
1845         err = mlx5e_open_sqs(c, params, cparam);
1846         if (err)
1847                 goto err_close_icosq;
1848
1849         if (c->xdp) {
1850                 err = mlx5e_open_xdpsq(c, params, &cparam->xdp_sq, NULL,
1851                                        &c->rq_xdpsq, false);
1852                 if (err)
1853                         goto err_close_sqs;
1854         }
1855
1856         err = mlx5e_open_rq(c, params, &cparam->rq, NULL, NULL, &c->rq);
1857         if (err)
1858                 goto err_close_xdp_sq;
1859
1860         err = mlx5e_open_xdpsq(c, params, &cparam->xdp_sq, NULL, &c->xdpsq, true);
1861         if (err)
1862                 goto err_close_rq;
1863
1864         return 0;
1865
1866 err_close_rq:
1867         mlx5e_close_rq(&c->rq);
1868
1869 err_close_xdp_sq:
1870         if (c->xdp)
1871                 mlx5e_close_xdpsq(&c->rq_xdpsq);
1872
1873 err_close_sqs:
1874         mlx5e_close_sqs(c);
1875
1876 err_close_icosq:
1877         mlx5e_close_icosq(&c->icosq);
1878
1879 err_disable_napi:
1880         napi_disable(&c->napi);
1881
1882         if (c->xdp)
1883                 mlx5e_close_cq(&c->rq_xdpsq.cq);
1884
1885 err_close_rx_cq:
1886         mlx5e_close_cq(&c->rq.cq);
1887
1888 err_close_xdp_tx_cqs:
1889         mlx5e_close_cq(&c->xdpsq.cq);
1890
1891 err_close_tx_cqs:
1892         mlx5e_close_tx_cqs(c);
1893
1894 err_close_icosq_cq:
1895         mlx5e_close_cq(&c->icosq.cq);
1896
1897         return err;
1898 }
1899
1900 static void mlx5e_close_queues(struct mlx5e_channel *c)
1901 {
1902         mlx5e_close_xdpsq(&c->xdpsq);
1903         mlx5e_close_rq(&c->rq);
1904         if (c->xdp)
1905                 mlx5e_close_xdpsq(&c->rq_xdpsq);
1906         mlx5e_close_sqs(c);
1907         mlx5e_close_icosq(&c->icosq);
1908         napi_disable(&c->napi);
1909         if (c->xdp)
1910                 mlx5e_close_cq(&c->rq_xdpsq.cq);
1911         mlx5e_close_cq(&c->rq.cq);
1912         mlx5e_close_cq(&c->xdpsq.cq);
1913         mlx5e_close_tx_cqs(c);
1914         mlx5e_close_cq(&c->icosq.cq);
1915 }
1916
1917 static int mlx5e_open_channel(struct mlx5e_priv *priv, int ix,
1918                               struct mlx5e_params *params,
1919                               struct mlx5e_channel_param *cparam,
1920                               struct xdp_umem *umem,
1921                               struct mlx5e_channel **cp)
1922 {
1923         int cpu = cpumask_first(mlx5_comp_irq_get_affinity_mask(priv->mdev, ix));
1924         struct net_device *netdev = priv->netdev;
1925         struct mlx5e_xsk_param xsk;
1926         struct mlx5e_channel *c;
1927         unsigned int irq;
1928         int err;
1929         int eqn;
1930
1931         err = mlx5_vector2eqn(priv->mdev, ix, &eqn, &irq);
1932         if (err)
1933                 return err;
1934
1935         c = kvzalloc_node(sizeof(*c), GFP_KERNEL, cpu_to_node(cpu));
1936         if (!c)
1937                 return -ENOMEM;
1938
1939         c->priv     = priv;
1940         c->mdev     = priv->mdev;
1941         c->tstamp   = &priv->tstamp;
1942         c->ix       = ix;
1943         c->cpu      = cpu;
1944         c->pdev     = priv->mdev->device;
1945         c->netdev   = priv->netdev;
1946         c->mkey_be  = cpu_to_be32(priv->mdev->mlx5e_res.mkey.key);
1947         c->num_tc   = params->num_tc;
1948         c->xdp      = !!params->xdp_prog;
1949         c->stats    = &priv->channel_stats[ix].ch;
1950         c->irq_desc = irq_to_desc(irq);
1951
1952         err = mlx5e_alloc_xps_cpumask(c, params);
1953         if (err)
1954                 goto err_free_channel;
1955
1956         netif_napi_add(netdev, &c->napi, mlx5e_napi_poll, 64);
1957
1958         err = mlx5e_open_queues(c, params, cparam);
1959         if (unlikely(err))
1960                 goto err_napi_del;
1961
1962         if (umem) {
1963                 mlx5e_build_xsk_param(umem, &xsk);
1964                 err = mlx5e_open_xsk(priv, params, &xsk, umem, c);
1965                 if (unlikely(err))
1966                         goto err_close_queues;
1967         }
1968
1969         *cp = c;
1970
1971         return 0;
1972
1973 err_close_queues:
1974         mlx5e_close_queues(c);
1975
1976 err_napi_del:
1977         netif_napi_del(&c->napi);
1978         mlx5e_free_xps_cpumask(c);
1979
1980 err_free_channel:
1981         kvfree(c);
1982
1983         return err;
1984 }
1985
1986 static void mlx5e_activate_channel(struct mlx5e_channel *c)
1987 {
1988         int tc;
1989
1990         for (tc = 0; tc < c->num_tc; tc++)
1991                 mlx5e_activate_txqsq(&c->sq[tc]);
1992         mlx5e_activate_rq(&c->rq);
1993         netif_set_xps_queue(c->netdev, c->xps_cpumask, c->ix);
1994
1995         if (test_bit(MLX5E_CHANNEL_STATE_XSK, c->state))
1996                 mlx5e_activate_xsk(c);
1997 }
1998
1999 static void mlx5e_deactivate_channel(struct mlx5e_channel *c)
2000 {
2001         int tc;
2002
2003         if (test_bit(MLX5E_CHANNEL_STATE_XSK, c->state))
2004                 mlx5e_deactivate_xsk(c);
2005
2006         mlx5e_deactivate_rq(&c->rq);
2007         for (tc = 0; tc < c->num_tc; tc++)
2008                 mlx5e_deactivate_txqsq(&c->sq[tc]);
2009 }
2010
2011 static void mlx5e_close_channel(struct mlx5e_channel *c)
2012 {
2013         if (test_bit(MLX5E_CHANNEL_STATE_XSK, c->state))
2014                 mlx5e_close_xsk(c);
2015         mlx5e_close_queues(c);
2016         netif_napi_del(&c->napi);
2017         mlx5e_free_xps_cpumask(c);
2018
2019         kvfree(c);
2020 }
2021
2022 #define DEFAULT_FRAG_SIZE (2048)
2023
2024 static void mlx5e_build_rq_frags_info(struct mlx5_core_dev *mdev,
2025                                       struct mlx5e_params *params,
2026                                       struct mlx5e_xsk_param *xsk,
2027                                       struct mlx5e_rq_frags_info *info)
2028 {
2029         u32 byte_count = MLX5E_SW2HW_MTU(params, params->sw_mtu);
2030         int frag_size_max = DEFAULT_FRAG_SIZE;
2031         u32 buf_size = 0;
2032         int i;
2033
2034 #ifdef CONFIG_MLX5_EN_IPSEC
2035         if (MLX5_IPSEC_DEV(mdev))
2036                 byte_count += MLX5E_METADATA_ETHER_LEN;
2037 #endif
2038
2039         if (mlx5e_rx_is_linear_skb(params, xsk)) {
2040                 int frag_stride;
2041
2042                 frag_stride = mlx5e_rx_get_linear_frag_sz(params, xsk);
2043                 frag_stride = roundup_pow_of_two(frag_stride);
2044
2045                 info->arr[0].frag_size = byte_count;
2046                 info->arr[0].frag_stride = frag_stride;
2047                 info->num_frags = 1;
2048                 info->wqe_bulk = PAGE_SIZE / frag_stride;
2049                 goto out;
2050         }
2051
2052         if (byte_count > PAGE_SIZE +
2053             (MLX5E_MAX_RX_FRAGS - 1) * frag_size_max)
2054                 frag_size_max = PAGE_SIZE;
2055
2056         i = 0;
2057         while (buf_size < byte_count) {
2058                 int frag_size = byte_count - buf_size;
2059
2060                 if (i < MLX5E_MAX_RX_FRAGS - 1)
2061                         frag_size = min(frag_size, frag_size_max);
2062
2063                 info->arr[i].frag_size = frag_size;
2064                 info->arr[i].frag_stride = roundup_pow_of_two(frag_size);
2065
2066                 buf_size += frag_size;
2067                 i++;
2068         }
2069         info->num_frags = i;
2070         /* number of different wqes sharing a page */
2071         info->wqe_bulk = 1 + (info->num_frags % 2);
2072
2073 out:
2074         info->wqe_bulk = max_t(u8, info->wqe_bulk, 8);
2075         info->log_num_frags = order_base_2(info->num_frags);
2076 }
2077
2078 static inline u8 mlx5e_get_rqwq_log_stride(u8 wq_type, int ndsegs)
2079 {
2080         int sz = sizeof(struct mlx5_wqe_data_seg) * ndsegs;
2081
2082         switch (wq_type) {
2083         case MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ:
2084                 sz += sizeof(struct mlx5e_rx_wqe_ll);
2085                 break;
2086         default: /* MLX5_WQ_TYPE_CYCLIC */
2087                 sz += sizeof(struct mlx5e_rx_wqe_cyc);
2088         }
2089
2090         return order_base_2(sz);
2091 }
2092
2093 static u8 mlx5e_get_rq_log_wq_sz(void *rqc)
2094 {
2095         void *wq = MLX5_ADDR_OF(rqc, rqc, wq);
2096
2097         return MLX5_GET(wq, wq, log_wq_sz);
2098 }
2099
2100 void mlx5e_build_rq_param(struct mlx5e_priv *priv,
2101                           struct mlx5e_params *params,
2102                           struct mlx5e_xsk_param *xsk,
2103                           struct mlx5e_rq_param *param)
2104 {
2105         struct mlx5_core_dev *mdev = priv->mdev;
2106         void *rqc = param->rqc;
2107         void *wq = MLX5_ADDR_OF(rqc, rqc, wq);
2108         int ndsegs = 1;
2109
2110         switch (params->rq_wq_type) {
2111         case MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ:
2112                 MLX5_SET(wq, wq, log_wqe_num_of_strides,
2113                          mlx5e_mpwqe_get_log_num_strides(mdev, params, xsk) -
2114                          MLX5_MPWQE_LOG_NUM_STRIDES_BASE);
2115                 MLX5_SET(wq, wq, log_wqe_stride_size,
2116                          mlx5e_mpwqe_get_log_stride_size(mdev, params, xsk) -
2117                          MLX5_MPWQE_LOG_STRIDE_SZ_BASE);
2118                 MLX5_SET(wq, wq, log_wq_sz, mlx5e_mpwqe_get_log_rq_size(params, xsk));
2119                 break;
2120         default: /* MLX5_WQ_TYPE_CYCLIC */
2121                 MLX5_SET(wq, wq, log_wq_sz, params->log_rq_mtu_frames);
2122                 mlx5e_build_rq_frags_info(mdev, params, xsk, &param->frags_info);
2123                 ndsegs = param->frags_info.num_frags;
2124         }
2125
2126         MLX5_SET(wq, wq, wq_type,          params->rq_wq_type);
2127         MLX5_SET(wq, wq, end_padding_mode, MLX5_WQ_END_PAD_MODE_ALIGN);
2128         MLX5_SET(wq, wq, log_wq_stride,
2129                  mlx5e_get_rqwq_log_stride(params->rq_wq_type, ndsegs));
2130         MLX5_SET(wq, wq, pd,               mdev->mlx5e_res.pdn);
2131         MLX5_SET(rqc, rqc, counter_set_id, priv->q_counter);
2132         MLX5_SET(rqc, rqc, vsd,            params->vlan_strip_disable);
2133         MLX5_SET(rqc, rqc, scatter_fcs,    params->scatter_fcs_en);
2134
2135         param->wq.buf_numa_node = dev_to_node(mdev->device);
2136 }
2137
2138 static void mlx5e_build_drop_rq_param(struct mlx5e_priv *priv,
2139                                       struct mlx5e_rq_param *param)
2140 {
2141         struct mlx5_core_dev *mdev = priv->mdev;
2142         void *rqc = param->rqc;
2143         void *wq = MLX5_ADDR_OF(rqc, rqc, wq);
2144
2145         MLX5_SET(wq, wq, wq_type, MLX5_WQ_TYPE_CYCLIC);
2146         MLX5_SET(wq, wq, log_wq_stride,
2147                  mlx5e_get_rqwq_log_stride(MLX5_WQ_TYPE_CYCLIC, 1));
2148         MLX5_SET(rqc, rqc, counter_set_id, priv->drop_rq_q_counter);
2149
2150         param->wq.buf_numa_node = dev_to_node(mdev->device);
2151 }
2152
2153 void mlx5e_build_sq_param_common(struct mlx5e_priv *priv,
2154                                  struct mlx5e_sq_param *param)
2155 {
2156         void *sqc = param->sqc;
2157         void *wq = MLX5_ADDR_OF(sqc, sqc, wq);
2158
2159         MLX5_SET(wq, wq, log_wq_stride, ilog2(MLX5_SEND_WQE_BB));
2160         MLX5_SET(wq, wq, pd,            priv->mdev->mlx5e_res.pdn);
2161
2162         param->wq.buf_numa_node = dev_to_node(priv->mdev->device);
2163 }
2164
2165 static void mlx5e_build_sq_param(struct mlx5e_priv *priv,
2166                                  struct mlx5e_params *params,
2167                                  struct mlx5e_sq_param *param)
2168 {
2169         void *sqc = param->sqc;
2170         void *wq = MLX5_ADDR_OF(sqc, sqc, wq);
2171         bool allow_swp;
2172
2173         allow_swp = mlx5_geneve_tx_allowed(priv->mdev) ||
2174                     !!MLX5_IPSEC_DEV(priv->mdev);
2175         mlx5e_build_sq_param_common(priv, param);
2176         MLX5_SET(wq, wq, log_wq_sz, params->log_sq_size);
2177         MLX5_SET(sqc, sqc, allow_swp, allow_swp);
2178 }
2179
2180 static void mlx5e_build_common_cq_param(struct mlx5e_priv *priv,
2181                                         struct mlx5e_cq_param *param)
2182 {
2183         void *cqc = param->cqc;
2184
2185         MLX5_SET(cqc, cqc, uar_page, priv->mdev->priv.uar->index);
2186         if (MLX5_CAP_GEN(priv->mdev, cqe_128_always) && cache_line_size() >= 128)
2187                 MLX5_SET(cqc, cqc, cqe_sz, CQE_STRIDE_128_PAD);
2188 }
2189
2190 void mlx5e_build_rx_cq_param(struct mlx5e_priv *priv,
2191                              struct mlx5e_params *params,
2192                              struct mlx5e_xsk_param *xsk,
2193                              struct mlx5e_cq_param *param)
2194 {
2195         struct mlx5_core_dev *mdev = priv->mdev;
2196         void *cqc = param->cqc;
2197         u8 log_cq_size;
2198
2199         switch (params->rq_wq_type) {
2200         case MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ:
2201                 log_cq_size = mlx5e_mpwqe_get_log_rq_size(params, xsk) +
2202                         mlx5e_mpwqe_get_log_num_strides(mdev, params, xsk);
2203                 break;
2204         default: /* MLX5_WQ_TYPE_CYCLIC */
2205                 log_cq_size = params->log_rq_mtu_frames;
2206         }
2207
2208         MLX5_SET(cqc, cqc, log_cq_size, log_cq_size);
2209         if (MLX5E_GET_PFLAG(params, MLX5E_PFLAG_RX_CQE_COMPRESS)) {
2210                 MLX5_SET(cqc, cqc, mini_cqe_res_format, MLX5_CQE_FORMAT_CSUM);
2211                 MLX5_SET(cqc, cqc, cqe_comp_en, 1);
2212         }
2213
2214         mlx5e_build_common_cq_param(priv, param);
2215         param->cq_period_mode = params->rx_cq_moderation.cq_period_mode;
2216 }
2217
2218 void mlx5e_build_tx_cq_param(struct mlx5e_priv *priv,
2219                              struct mlx5e_params *params,
2220                              struct mlx5e_cq_param *param)
2221 {
2222         void *cqc = param->cqc;
2223
2224         MLX5_SET(cqc, cqc, log_cq_size, params->log_sq_size);
2225
2226         mlx5e_build_common_cq_param(priv, param);
2227         param->cq_period_mode = params->tx_cq_moderation.cq_period_mode;
2228 }
2229
2230 void mlx5e_build_ico_cq_param(struct mlx5e_priv *priv,
2231                               u8 log_wq_size,
2232                               struct mlx5e_cq_param *param)
2233 {
2234         void *cqc = param->cqc;
2235
2236         MLX5_SET(cqc, cqc, log_cq_size, log_wq_size);
2237
2238         mlx5e_build_common_cq_param(priv, param);
2239
2240         param->cq_period_mode = DIM_CQ_PERIOD_MODE_START_FROM_EQE;
2241 }
2242
2243 void mlx5e_build_icosq_param(struct mlx5e_priv *priv,
2244                              u8 log_wq_size,
2245                              struct mlx5e_sq_param *param)
2246 {
2247         void *sqc = param->sqc;
2248         void *wq = MLX5_ADDR_OF(sqc, sqc, wq);
2249
2250         mlx5e_build_sq_param_common(priv, param);
2251
2252         MLX5_SET(wq, wq, log_wq_sz, log_wq_size);
2253         MLX5_SET(sqc, sqc, reg_umr, MLX5_CAP_ETH(priv->mdev, reg_umr_sq));
2254 }
2255
2256 void mlx5e_build_xdpsq_param(struct mlx5e_priv *priv,
2257                              struct mlx5e_params *params,
2258                              struct mlx5e_sq_param *param)
2259 {
2260         void *sqc = param->sqc;
2261         void *wq = MLX5_ADDR_OF(sqc, sqc, wq);
2262
2263         mlx5e_build_sq_param_common(priv, param);
2264         MLX5_SET(wq, wq, log_wq_sz, params->log_sq_size);
2265         param->is_mpw = MLX5E_GET_PFLAG(params, MLX5E_PFLAG_XDP_TX_MPWQE);
2266 }
2267
2268 static u8 mlx5e_build_icosq_log_wq_sz(struct mlx5e_params *params,
2269                                       struct mlx5e_rq_param *rqp)
2270 {
2271         switch (params->rq_wq_type) {
2272         case MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ:
2273                 return order_base_2(MLX5E_UMR_WQEBBS) +
2274                         mlx5e_get_rq_log_wq_sz(rqp->rqc);
2275         default: /* MLX5_WQ_TYPE_CYCLIC */
2276                 return MLX5E_PARAMS_MINIMUM_LOG_SQ_SIZE;
2277         }
2278 }
2279
2280 static void mlx5e_build_channel_param(struct mlx5e_priv *priv,
2281                                       struct mlx5e_params *params,
2282                                       struct mlx5e_channel_param *cparam)
2283 {
2284         u8 icosq_log_wq_sz;
2285
2286         mlx5e_build_rq_param(priv, params, NULL, &cparam->rq);
2287
2288         icosq_log_wq_sz = mlx5e_build_icosq_log_wq_sz(params, &cparam->rq);
2289
2290         mlx5e_build_sq_param(priv, params, &cparam->sq);
2291         mlx5e_build_xdpsq_param(priv, params, &cparam->xdp_sq);
2292         mlx5e_build_icosq_param(priv, icosq_log_wq_sz, &cparam->icosq);
2293         mlx5e_build_rx_cq_param(priv, params, NULL, &cparam->rx_cq);
2294         mlx5e_build_tx_cq_param(priv, params, &cparam->tx_cq);
2295         mlx5e_build_ico_cq_param(priv, icosq_log_wq_sz, &cparam->icosq_cq);
2296 }
2297
2298 int mlx5e_open_channels(struct mlx5e_priv *priv,
2299                         struct mlx5e_channels *chs)
2300 {
2301         struct mlx5e_channel_param *cparam;
2302         int err = -ENOMEM;
2303         int i;
2304
2305         chs->num = chs->params.num_channels;
2306
2307         chs->c = kcalloc(chs->num, sizeof(struct mlx5e_channel *), GFP_KERNEL);
2308         cparam = kvzalloc(sizeof(struct mlx5e_channel_param), GFP_KERNEL);
2309         if (!chs->c || !cparam)
2310                 goto err_free;
2311
2312         mlx5e_build_channel_param(priv, &chs->params, cparam);
2313         for (i = 0; i < chs->num; i++) {
2314                 struct xdp_umem *umem = NULL;
2315
2316                 if (chs->params.xdp_prog)
2317                         umem = mlx5e_xsk_get_umem(&chs->params, chs->params.xsk, i);
2318
2319                 err = mlx5e_open_channel(priv, i, &chs->params, cparam, umem, &chs->c[i]);
2320                 if (err)
2321                         goto err_close_channels;
2322         }
2323
2324         if (!IS_ERR_OR_NULL(priv->tx_reporter))
2325                 devlink_health_reporter_state_update(priv->tx_reporter,
2326                                                      DEVLINK_HEALTH_REPORTER_STATE_HEALTHY);
2327
2328         kvfree(cparam);
2329         return 0;
2330
2331 err_close_channels:
2332         for (i--; i >= 0; i--)
2333                 mlx5e_close_channel(chs->c[i]);
2334
2335 err_free:
2336         kfree(chs->c);
2337         kvfree(cparam);
2338         chs->num = 0;
2339         return err;
2340 }
2341
2342 static void mlx5e_activate_channels(struct mlx5e_channels *chs)
2343 {
2344         int i;
2345
2346         for (i = 0; i < chs->num; i++)
2347                 mlx5e_activate_channel(chs->c[i]);
2348 }
2349
2350 #define MLX5E_RQ_WQES_TIMEOUT 20000 /* msecs */
2351
2352 static int mlx5e_wait_channels_min_rx_wqes(struct mlx5e_channels *chs)
2353 {
2354         int err = 0;
2355         int i;
2356
2357         for (i = 0; i < chs->num; i++) {
2358                 int timeout = err ? 0 : MLX5E_RQ_WQES_TIMEOUT;
2359
2360                 err |= mlx5e_wait_for_min_rx_wqes(&chs->c[i]->rq, timeout);
2361
2362                 /* Don't wait on the XSK RQ, because the newer xdpsock sample
2363                  * doesn't provide any Fill Ring entries at the setup stage.
2364                  */
2365         }
2366
2367         return err ? -ETIMEDOUT : 0;
2368 }
2369
2370 static void mlx5e_deactivate_channels(struct mlx5e_channels *chs)
2371 {
2372         int i;
2373
2374         for (i = 0; i < chs->num; i++)
2375                 mlx5e_deactivate_channel(chs->c[i]);
2376 }
2377
2378 void mlx5e_close_channels(struct mlx5e_channels *chs)
2379 {
2380         int i;
2381
2382         for (i = 0; i < chs->num; i++)
2383                 mlx5e_close_channel(chs->c[i]);
2384
2385         kfree(chs->c);
2386         chs->num = 0;
2387 }
2388
2389 static int
2390 mlx5e_create_rqt(struct mlx5e_priv *priv, int sz, struct mlx5e_rqt *rqt)
2391 {
2392         struct mlx5_core_dev *mdev = priv->mdev;
2393         void *rqtc;
2394         int inlen;
2395         int err;
2396         u32 *in;
2397         int i;
2398
2399         inlen = MLX5_ST_SZ_BYTES(create_rqt_in) + sizeof(u32) * sz;
2400         in = kvzalloc(inlen, GFP_KERNEL);
2401         if (!in)
2402                 return -ENOMEM;
2403
2404         rqtc = MLX5_ADDR_OF(create_rqt_in, in, rqt_context);
2405
2406         MLX5_SET(rqtc, rqtc, rqt_actual_size, sz);
2407         MLX5_SET(rqtc, rqtc, rqt_max_size, sz);
2408
2409         for (i = 0; i < sz; i++)
2410                 MLX5_SET(rqtc, rqtc, rq_num[i], priv->drop_rq.rqn);
2411
2412         err = mlx5_core_create_rqt(mdev, in, inlen, &rqt->rqtn);
2413         if (!err)
2414                 rqt->enabled = true;
2415
2416         kvfree(in);
2417         return err;
2418 }
2419
2420 void mlx5e_destroy_rqt(struct mlx5e_priv *priv, struct mlx5e_rqt *rqt)
2421 {
2422         rqt->enabled = false;
2423         mlx5_core_destroy_rqt(priv->mdev, rqt->rqtn);
2424 }
2425
2426 int mlx5e_create_indirect_rqt(struct mlx5e_priv *priv)
2427 {
2428         struct mlx5e_rqt *rqt = &priv->indir_rqt;
2429         int err;
2430
2431         err = mlx5e_create_rqt(priv, MLX5E_INDIR_RQT_SIZE, rqt);
2432         if (err)
2433                 mlx5_core_warn(priv->mdev, "create indirect rqts failed, %d\n", err);
2434         return err;
2435 }
2436
2437 int mlx5e_create_direct_rqts(struct mlx5e_priv *priv, struct mlx5e_tir *tirs)
2438 {
2439         int err;
2440         int ix;
2441
2442         for (ix = 0; ix < priv->max_nch; ix++) {
2443                 err = mlx5e_create_rqt(priv, 1 /*size */, &tirs[ix].rqt);
2444                 if (unlikely(err))
2445                         goto err_destroy_rqts;
2446         }
2447
2448         return 0;
2449
2450 err_destroy_rqts:
2451         mlx5_core_warn(priv->mdev, "create rqts failed, %d\n", err);
2452         for (ix--; ix >= 0; ix--)
2453                 mlx5e_destroy_rqt(priv, &tirs[ix].rqt);
2454
2455         return err;
2456 }
2457
2458 void mlx5e_destroy_direct_rqts(struct mlx5e_priv *priv, struct mlx5e_tir *tirs)
2459 {
2460         int i;
2461
2462         for (i = 0; i < priv->max_nch; i++)
2463                 mlx5e_destroy_rqt(priv, &tirs[i].rqt);
2464 }
2465
2466 static int mlx5e_rx_hash_fn(int hfunc)
2467 {
2468         return (hfunc == ETH_RSS_HASH_TOP) ?
2469                MLX5_RX_HASH_FN_TOEPLITZ :
2470                MLX5_RX_HASH_FN_INVERTED_XOR8;
2471 }
2472
2473 int mlx5e_bits_invert(unsigned long a, int size)
2474 {
2475         int inv = 0;
2476         int i;
2477
2478         for (i = 0; i < size; i++)
2479                 inv |= (test_bit(size - i - 1, &a) ? 1 : 0) << i;
2480
2481         return inv;
2482 }
2483
2484 static void mlx5e_fill_rqt_rqns(struct mlx5e_priv *priv, int sz,
2485                                 struct mlx5e_redirect_rqt_param rrp, void *rqtc)
2486 {
2487         int i;
2488
2489         for (i = 0; i < sz; i++) {
2490                 u32 rqn;
2491
2492                 if (rrp.is_rss) {
2493                         int ix = i;
2494
2495                         if (rrp.rss.hfunc == ETH_RSS_HASH_XOR)
2496                                 ix = mlx5e_bits_invert(i, ilog2(sz));
2497
2498                         ix = priv->rss_params.indirection_rqt[ix];
2499                         rqn = rrp.rss.channels->c[ix]->rq.rqn;
2500                 } else {
2501                         rqn = rrp.rqn;
2502                 }
2503                 MLX5_SET(rqtc, rqtc, rq_num[i], rqn);
2504         }
2505 }
2506
2507 int mlx5e_redirect_rqt(struct mlx5e_priv *priv, u32 rqtn, int sz,
2508                        struct mlx5e_redirect_rqt_param rrp)
2509 {
2510         struct mlx5_core_dev *mdev = priv->mdev;
2511         void *rqtc;
2512         int inlen;
2513         u32 *in;
2514         int err;
2515
2516         inlen = MLX5_ST_SZ_BYTES(modify_rqt_in) + sizeof(u32) * sz;
2517         in = kvzalloc(inlen, GFP_KERNEL);
2518         if (!in)
2519                 return -ENOMEM;
2520
2521         rqtc = MLX5_ADDR_OF(modify_rqt_in, in, ctx);
2522
2523         MLX5_SET(rqtc, rqtc, rqt_actual_size, sz);
2524         MLX5_SET(modify_rqt_in, in, bitmask.rqn_list, 1);
2525         mlx5e_fill_rqt_rqns(priv, sz, rrp, rqtc);
2526         err = mlx5_core_modify_rqt(mdev, rqtn, in, inlen);
2527
2528         kvfree(in);
2529         return err;
2530 }
2531
2532 static u32 mlx5e_get_direct_rqn(struct mlx5e_priv *priv, int ix,
2533                                 struct mlx5e_redirect_rqt_param rrp)
2534 {
2535         if (!rrp.is_rss)
2536                 return rrp.rqn;
2537
2538         if (ix >= rrp.rss.channels->num)
2539                 return priv->drop_rq.rqn;
2540
2541         return rrp.rss.channels->c[ix]->rq.rqn;
2542 }
2543
2544 static void mlx5e_redirect_rqts(struct mlx5e_priv *priv,
2545                                 struct mlx5e_redirect_rqt_param rrp)
2546 {
2547         u32 rqtn;
2548         int ix;
2549
2550         if (priv->indir_rqt.enabled) {
2551                 /* RSS RQ table */
2552                 rqtn = priv->indir_rqt.rqtn;
2553                 mlx5e_redirect_rqt(priv, rqtn, MLX5E_INDIR_RQT_SIZE, rrp);
2554         }
2555
2556         for (ix = 0; ix < priv->max_nch; ix++) {
2557                 struct mlx5e_redirect_rqt_param direct_rrp = {
2558                         .is_rss = false,
2559                         {
2560                                 .rqn    = mlx5e_get_direct_rqn(priv, ix, rrp)
2561                         },
2562                 };
2563
2564                 /* Direct RQ Tables */
2565                 if (!priv->direct_tir[ix].rqt.enabled)
2566                         continue;
2567
2568                 rqtn = priv->direct_tir[ix].rqt.rqtn;
2569                 mlx5e_redirect_rqt(priv, rqtn, 1, direct_rrp);
2570         }
2571 }
2572
2573 static void mlx5e_redirect_rqts_to_channels(struct mlx5e_priv *priv,
2574                                             struct mlx5e_channels *chs)
2575 {
2576         struct mlx5e_redirect_rqt_param rrp = {
2577                 .is_rss        = true,
2578                 {
2579                         .rss = {
2580                                 .channels  = chs,
2581                                 .hfunc     = priv->rss_params.hfunc,
2582                         }
2583                 },
2584         };
2585
2586         mlx5e_redirect_rqts(priv, rrp);
2587 }
2588
2589 static void mlx5e_redirect_rqts_to_drop(struct mlx5e_priv *priv)
2590 {
2591         struct mlx5e_redirect_rqt_param drop_rrp = {
2592                 .is_rss = false,
2593                 {
2594                         .rqn = priv->drop_rq.rqn,
2595                 },
2596         };
2597
2598         mlx5e_redirect_rqts(priv, drop_rrp);
2599 }
2600
2601 static const struct mlx5e_tirc_config tirc_default_config[MLX5E_NUM_INDIR_TIRS] = {
2602         [MLX5E_TT_IPV4_TCP] = { .l3_prot_type = MLX5_L3_PROT_TYPE_IPV4,
2603                                 .l4_prot_type = MLX5_L4_PROT_TYPE_TCP,
2604                                 .rx_hash_fields = MLX5_HASH_IP_L4PORTS,
2605         },
2606         [MLX5E_TT_IPV6_TCP] = { .l3_prot_type = MLX5_L3_PROT_TYPE_IPV6,
2607                                 .l4_prot_type = MLX5_L4_PROT_TYPE_TCP,
2608                                 .rx_hash_fields = MLX5_HASH_IP_L4PORTS,
2609         },
2610         [MLX5E_TT_IPV4_UDP] = { .l3_prot_type = MLX5_L3_PROT_TYPE_IPV4,
2611                                 .l4_prot_type = MLX5_L4_PROT_TYPE_UDP,
2612                                 .rx_hash_fields = MLX5_HASH_IP_L4PORTS,
2613         },
2614         [MLX5E_TT_IPV6_UDP] = { .l3_prot_type = MLX5_L3_PROT_TYPE_IPV6,
2615                                 .l4_prot_type = MLX5_L4_PROT_TYPE_UDP,
2616                                 .rx_hash_fields = MLX5_HASH_IP_L4PORTS,
2617         },
2618         [MLX5E_TT_IPV4_IPSEC_AH] = { .l3_prot_type = MLX5_L3_PROT_TYPE_IPV4,
2619                                      .l4_prot_type = 0,
2620                                      .rx_hash_fields = MLX5_HASH_IP_IPSEC_SPI,
2621         },
2622         [MLX5E_TT_IPV6_IPSEC_AH] = { .l3_prot_type = MLX5_L3_PROT_TYPE_IPV6,
2623                                      .l4_prot_type = 0,
2624                                      .rx_hash_fields = MLX5_HASH_IP_IPSEC_SPI,
2625         },
2626         [MLX5E_TT_IPV4_IPSEC_ESP] = { .l3_prot_type = MLX5_L3_PROT_TYPE_IPV4,
2627                                       .l4_prot_type = 0,
2628                                       .rx_hash_fields = MLX5_HASH_IP_IPSEC_SPI,
2629         },
2630         [MLX5E_TT_IPV6_IPSEC_ESP] = { .l3_prot_type = MLX5_L3_PROT_TYPE_IPV6,
2631                                       .l4_prot_type = 0,
2632                                       .rx_hash_fields = MLX5_HASH_IP_IPSEC_SPI,
2633         },
2634         [MLX5E_TT_IPV4] = { .l3_prot_type = MLX5_L3_PROT_TYPE_IPV4,
2635                             .l4_prot_type = 0,
2636                             .rx_hash_fields = MLX5_HASH_IP,
2637         },
2638         [MLX5E_TT_IPV6] = { .l3_prot_type = MLX5_L3_PROT_TYPE_IPV6,
2639                             .l4_prot_type = 0,
2640                             .rx_hash_fields = MLX5_HASH_IP,
2641         },
2642 };
2643
2644 struct mlx5e_tirc_config mlx5e_tirc_get_default_config(enum mlx5e_traffic_types tt)
2645 {
2646         return tirc_default_config[tt];
2647 }
2648
2649 static void mlx5e_build_tir_ctx_lro(struct mlx5e_params *params, void *tirc)
2650 {
2651         if (!params->lro_en)
2652                 return;
2653
2654 #define ROUGH_MAX_L2_L3_HDR_SZ 256
2655
2656         MLX5_SET(tirc, tirc, lro_enable_mask,
2657                  MLX5_TIRC_LRO_ENABLE_MASK_IPV4_LRO |
2658                  MLX5_TIRC_LRO_ENABLE_MASK_IPV6_LRO);
2659         MLX5_SET(tirc, tirc, lro_max_ip_payload_size,
2660                  (MLX5E_PARAMS_DEFAULT_LRO_WQE_SZ - ROUGH_MAX_L2_L3_HDR_SZ) >> 8);
2661         MLX5_SET(tirc, tirc, lro_timeout_period_usecs, params->lro_timeout);
2662 }
2663
2664 void mlx5e_build_indir_tir_ctx_hash(struct mlx5e_rss_params *rss_params,
2665                                     const struct mlx5e_tirc_config *ttconfig,
2666                                     void *tirc, bool inner)
2667 {
2668         void *hfso = inner ? MLX5_ADDR_OF(tirc, tirc, rx_hash_field_selector_inner) :
2669                              MLX5_ADDR_OF(tirc, tirc, rx_hash_field_selector_outer);
2670
2671         MLX5_SET(tirc, tirc, rx_hash_fn, mlx5e_rx_hash_fn(rss_params->hfunc));
2672         if (rss_params->hfunc == ETH_RSS_HASH_TOP) {
2673                 void *rss_key = MLX5_ADDR_OF(tirc, tirc,
2674                                              rx_hash_toeplitz_key);
2675                 size_t len = MLX5_FLD_SZ_BYTES(tirc,
2676                                                rx_hash_toeplitz_key);
2677
2678                 MLX5_SET(tirc, tirc, rx_hash_symmetric, 1);
2679                 memcpy(rss_key, rss_params->toeplitz_hash_key, len);
2680         }
2681         MLX5_SET(rx_hash_field_select, hfso, l3_prot_type,
2682                  ttconfig->l3_prot_type);
2683         MLX5_SET(rx_hash_field_select, hfso, l4_prot_type,
2684                  ttconfig->l4_prot_type);
2685         MLX5_SET(rx_hash_field_select, hfso, selected_fields,
2686                  ttconfig->rx_hash_fields);
2687 }
2688
2689 static void mlx5e_update_rx_hash_fields(struct mlx5e_tirc_config *ttconfig,
2690                                         enum mlx5e_traffic_types tt,
2691                                         u32 rx_hash_fields)
2692 {
2693         *ttconfig                = tirc_default_config[tt];
2694         ttconfig->rx_hash_fields = rx_hash_fields;
2695 }
2696
2697 void mlx5e_modify_tirs_hash(struct mlx5e_priv *priv, void *in, int inlen)
2698 {
2699         void *tirc = MLX5_ADDR_OF(modify_tir_in, in, ctx);
2700         struct mlx5e_rss_params *rss = &priv->rss_params;
2701         struct mlx5_core_dev *mdev = priv->mdev;
2702         int ctxlen = MLX5_ST_SZ_BYTES(tirc);
2703         struct mlx5e_tirc_config ttconfig;
2704         int tt;
2705
2706         MLX5_SET(modify_tir_in, in, bitmask.hash, 1);
2707
2708         for (tt = 0; tt < MLX5E_NUM_INDIR_TIRS; tt++) {
2709                 memset(tirc, 0, ctxlen);
2710                 mlx5e_update_rx_hash_fields(&ttconfig, tt,
2711                                             rss->rx_hash_fields[tt]);
2712                 mlx5e_build_indir_tir_ctx_hash(rss, &ttconfig, tirc, false);
2713                 mlx5_core_modify_tir(mdev, priv->indir_tir[tt].tirn, in, inlen);
2714         }
2715
2716         if (!mlx5e_tunnel_inner_ft_supported(priv->mdev))
2717                 return;
2718
2719         for (tt = 0; tt < MLX5E_NUM_INDIR_TIRS; tt++) {
2720                 memset(tirc, 0, ctxlen);
2721                 mlx5e_update_rx_hash_fields(&ttconfig, tt,
2722                                             rss->rx_hash_fields[tt]);
2723                 mlx5e_build_indir_tir_ctx_hash(rss, &ttconfig, tirc, true);
2724                 mlx5_core_modify_tir(mdev, priv->inner_indir_tir[tt].tirn, in,
2725                                      inlen);
2726         }
2727 }
2728
2729 static int mlx5e_modify_tirs_lro(struct mlx5e_priv *priv)
2730 {
2731         struct mlx5_core_dev *mdev = priv->mdev;
2732
2733         void *in;
2734         void *tirc;
2735         int inlen;
2736         int err;
2737         int tt;
2738         int ix;
2739
2740         inlen = MLX5_ST_SZ_BYTES(modify_tir_in);
2741         in = kvzalloc(inlen, GFP_KERNEL);
2742         if (!in)
2743                 return -ENOMEM;
2744
2745         MLX5_SET(modify_tir_in, in, bitmask.lro, 1);
2746         tirc = MLX5_ADDR_OF(modify_tir_in, in, ctx);
2747
2748         mlx5e_build_tir_ctx_lro(&priv->channels.params, tirc);
2749
2750         for (tt = 0; tt < MLX5E_NUM_INDIR_TIRS; tt++) {
2751                 err = mlx5_core_modify_tir(mdev, priv->indir_tir[tt].tirn, in,
2752                                            inlen);
2753                 if (err)
2754                         goto free_in;
2755         }
2756
2757         for (ix = 0; ix < priv->max_nch; ix++) {
2758                 err = mlx5_core_modify_tir(mdev, priv->direct_tir[ix].tirn,
2759                                            in, inlen);
2760                 if (err)
2761                         goto free_in;
2762         }
2763
2764 free_in:
2765         kvfree(in);
2766
2767         return err;
2768 }
2769
2770 static int mlx5e_set_mtu(struct mlx5_core_dev *mdev,
2771                          struct mlx5e_params *params, u16 mtu)
2772 {
2773         u16 hw_mtu = MLX5E_SW2HW_MTU(params, mtu);
2774         int err;
2775
2776         err = mlx5_set_port_mtu(mdev, hw_mtu, 1);
2777         if (err)
2778                 return err;
2779
2780         /* Update vport context MTU */
2781         mlx5_modify_nic_vport_mtu(mdev, hw_mtu);
2782         return 0;
2783 }
2784
2785 static void mlx5e_query_mtu(struct mlx5_core_dev *mdev,
2786                             struct mlx5e_params *params, u16 *mtu)
2787 {
2788         u16 hw_mtu = 0;
2789         int err;
2790
2791         err = mlx5_query_nic_vport_mtu(mdev, &hw_mtu);
2792         if (err || !hw_mtu) /* fallback to port oper mtu */
2793                 mlx5_query_port_oper_mtu(mdev, &hw_mtu, 1);
2794
2795         *mtu = MLX5E_HW2SW_MTU(params, hw_mtu);
2796 }
2797
2798 int mlx5e_set_dev_port_mtu(struct mlx5e_priv *priv)
2799 {
2800         struct mlx5e_params *params = &priv->channels.params;
2801         struct net_device *netdev = priv->netdev;
2802         struct mlx5_core_dev *mdev = priv->mdev;
2803         u16 mtu;
2804         int err;
2805
2806         err = mlx5e_set_mtu(mdev, params, params->sw_mtu);
2807         if (err)
2808                 return err;
2809
2810         mlx5e_query_mtu(mdev, params, &mtu);
2811         if (mtu != params->sw_mtu)
2812                 netdev_warn(netdev, "%s: VPort MTU %d is different than netdev mtu %d\n",
2813                             __func__, mtu, params->sw_mtu);
2814
2815         params->sw_mtu = mtu;
2816         return 0;
2817 }
2818
2819 void mlx5e_set_netdev_mtu_boundaries(struct mlx5e_priv *priv)
2820 {
2821         struct mlx5e_params *params = &priv->channels.params;
2822         struct net_device *netdev   = priv->netdev;
2823         struct mlx5_core_dev *mdev  = priv->mdev;
2824         u16 max_mtu;
2825
2826         /* MTU range: 68 - hw-specific max */
2827         netdev->min_mtu = ETH_MIN_MTU;
2828
2829         mlx5_query_port_max_mtu(mdev, &max_mtu, 1);
2830         netdev->max_mtu = min_t(unsigned int, MLX5E_HW2SW_MTU(params, max_mtu),
2831                                 ETH_MAX_MTU);
2832 }
2833
2834 static void mlx5e_netdev_set_tcs(struct net_device *netdev)
2835 {
2836         struct mlx5e_priv *priv = netdev_priv(netdev);
2837         int nch = priv->channels.params.num_channels;
2838         int ntc = priv->channels.params.num_tc;
2839         int tc;
2840
2841         netdev_reset_tc(netdev);
2842
2843         if (ntc == 1)
2844                 return;
2845
2846         netdev_set_num_tc(netdev, ntc);
2847
2848         /* Map netdev TCs to offset 0
2849          * We have our own UP to TXQ mapping for QoS
2850          */
2851         for (tc = 0; tc < ntc; tc++)
2852                 netdev_set_tc_queue(netdev, tc, nch, 0);
2853 }
2854
2855 static void mlx5e_build_tc2txq_maps(struct mlx5e_priv *priv)
2856 {
2857         int i, tc;
2858
2859         for (i = 0; i < priv->max_nch; i++)
2860                 for (tc = 0; tc < priv->profile->max_tc; tc++)
2861                         priv->channel_tc2txq[i][tc] = i + tc * priv->max_nch;
2862 }
2863
2864 static void mlx5e_build_tx2sq_maps(struct mlx5e_priv *priv)
2865 {
2866         struct mlx5e_channel *c;
2867         struct mlx5e_txqsq *sq;
2868         int i, tc;
2869
2870         for (i = 0; i < priv->channels.num; i++) {
2871                 c = priv->channels.c[i];
2872                 for (tc = 0; tc < c->num_tc; tc++) {
2873                         sq = &c->sq[tc];
2874                         priv->txq2sq[sq->txq_ix] = sq;
2875                 }
2876         }
2877 }
2878
2879 void mlx5e_activate_priv_channels(struct mlx5e_priv *priv)
2880 {
2881         int num_txqs = priv->channels.num * priv->channels.params.num_tc;
2882         int num_rxqs = priv->channels.num * priv->profile->rq_groups;
2883         struct net_device *netdev = priv->netdev;
2884
2885         mlx5e_netdev_set_tcs(netdev);
2886         netif_set_real_num_tx_queues(netdev, num_txqs);
2887         netif_set_real_num_rx_queues(netdev, num_rxqs);
2888
2889         mlx5e_build_tx2sq_maps(priv);
2890         mlx5e_activate_channels(&priv->channels);
2891         mlx5e_xdp_tx_enable(priv);
2892         netif_tx_start_all_queues(priv->netdev);
2893
2894         if (mlx5e_is_vport_rep(priv))
2895                 mlx5e_add_sqs_fwd_rules(priv);
2896
2897         mlx5e_wait_channels_min_rx_wqes(&priv->channels);
2898         mlx5e_redirect_rqts_to_channels(priv, &priv->channels);
2899
2900         mlx5e_xsk_redirect_rqts_to_channels(priv, &priv->channels);
2901 }
2902
2903 void mlx5e_deactivate_priv_channels(struct mlx5e_priv *priv)
2904 {
2905         mlx5e_xsk_redirect_rqts_to_drop(priv, &priv->channels);
2906
2907         mlx5e_redirect_rqts_to_drop(priv);
2908
2909         if (mlx5e_is_vport_rep(priv))
2910                 mlx5e_remove_sqs_fwd_rules(priv);
2911
2912         /* FIXME: This is a W/A only for tx timeout watch dog false alarm when
2913          * polling for inactive tx queues.
2914          */
2915         netif_tx_stop_all_queues(priv->netdev);
2916         netif_tx_disable(priv->netdev);
2917         mlx5e_xdp_tx_disable(priv);
2918         mlx5e_deactivate_channels(&priv->channels);
2919 }
2920
2921 static void mlx5e_switch_priv_channels(struct mlx5e_priv *priv,
2922                                        struct mlx5e_channels *new_chs,
2923                                        mlx5e_fp_hw_modify hw_modify)
2924 {
2925         struct net_device *netdev = priv->netdev;
2926         int new_num_txqs;
2927         int carrier_ok;
2928
2929         new_num_txqs = new_chs->num * new_chs->params.num_tc;
2930
2931         carrier_ok = netif_carrier_ok(netdev);
2932         netif_carrier_off(netdev);
2933
2934         if (new_num_txqs < netdev->real_num_tx_queues)
2935                 netif_set_real_num_tx_queues(netdev, new_num_txqs);
2936
2937         mlx5e_deactivate_priv_channels(priv);
2938         mlx5e_close_channels(&priv->channels);
2939
2940         priv->channels = *new_chs;
2941
2942         /* New channels are ready to roll, modify HW settings if needed */
2943         if (hw_modify)
2944                 hw_modify(priv);
2945
2946         priv->profile->update_rx(priv);
2947         mlx5e_activate_priv_channels(priv);
2948
2949         /* return carrier back if needed */
2950         if (carrier_ok)
2951                 netif_carrier_on(netdev);
2952 }
2953
2954 int mlx5e_safe_switch_channels(struct mlx5e_priv *priv,
2955                                struct mlx5e_channels *new_chs,
2956                                mlx5e_fp_hw_modify hw_modify)
2957 {
2958         int err;
2959
2960         err = mlx5e_open_channels(priv, new_chs);
2961         if (err)
2962                 return err;
2963
2964         mlx5e_switch_priv_channels(priv, new_chs, hw_modify);
2965         return 0;
2966 }
2967
2968 int mlx5e_safe_reopen_channels(struct mlx5e_priv *priv)
2969 {
2970         struct mlx5e_channels new_channels = {};
2971
2972         new_channels.params = priv->channels.params;
2973         return mlx5e_safe_switch_channels(priv, &new_channels, NULL);
2974 }
2975
2976 void mlx5e_timestamp_init(struct mlx5e_priv *priv)
2977 {
2978         priv->tstamp.tx_type   = HWTSTAMP_TX_OFF;
2979         priv->tstamp.rx_filter = HWTSTAMP_FILTER_NONE;
2980 }
2981
2982 int mlx5e_open_locked(struct net_device *netdev)
2983 {
2984         struct mlx5e_priv *priv = netdev_priv(netdev);
2985         bool is_xdp = priv->channels.params.xdp_prog;
2986         int err;
2987
2988         set_bit(MLX5E_STATE_OPENED, &priv->state);
2989         if (is_xdp)
2990                 mlx5e_xdp_set_open(priv);
2991
2992         err = mlx5e_open_channels(priv, &priv->channels);
2993         if (err)
2994                 goto err_clear_state_opened_flag;
2995
2996         priv->profile->update_rx(priv);
2997         mlx5e_activate_priv_channels(priv);
2998         if (priv->profile->update_carrier)
2999                 priv->profile->update_carrier(priv);
3000
3001         mlx5e_queue_update_stats(priv);
3002         return 0;
3003
3004 err_clear_state_opened_flag:
3005         if (is_xdp)
3006                 mlx5e_xdp_set_closed(priv);
3007         clear_bit(MLX5E_STATE_OPENED, &priv->state);
3008         return err;
3009 }
3010
3011 int mlx5e_open(struct net_device *netdev)
3012 {
3013         struct mlx5e_priv *priv = netdev_priv(netdev);
3014         int err;
3015
3016         mutex_lock(&priv->state_lock);
3017         err = mlx5e_open_locked(netdev);
3018         if (!err)
3019                 mlx5_set_port_admin_status(priv->mdev, MLX5_PORT_UP);
3020         mutex_unlock(&priv->state_lock);
3021
3022         if (mlx5_vxlan_allowed(priv->mdev->vxlan))
3023                 udp_tunnel_get_rx_info(netdev);
3024
3025         return err;
3026 }
3027
3028 int mlx5e_close_locked(struct net_device *netdev)
3029 {
3030         struct mlx5e_priv *priv = netdev_priv(netdev);
3031
3032         /* May already be CLOSED in case a previous configuration operation
3033          * (e.g RX/TX queue size change) that involves close&open failed.
3034          */
3035         if (!test_bit(MLX5E_STATE_OPENED, &priv->state))
3036                 return 0;
3037
3038         if (priv->channels.params.xdp_prog)
3039                 mlx5e_xdp_set_closed(priv);
3040         clear_bit(MLX5E_STATE_OPENED, &priv->state);
3041
3042         netif_carrier_off(priv->netdev);
3043         mlx5e_deactivate_priv_channels(priv);
3044         mlx5e_close_channels(&priv->channels);
3045
3046         return 0;
3047 }
3048
3049 int mlx5e_close(struct net_device *netdev)
3050 {
3051         struct mlx5e_priv *priv = netdev_priv(netdev);
3052         int err;
3053
3054         if (!netif_device_present(netdev))
3055                 return -ENODEV;
3056
3057         mutex_lock(&priv->state_lock);
3058         mlx5_set_port_admin_status(priv->mdev, MLX5_PORT_DOWN);
3059         err = mlx5e_close_locked(netdev);
3060         mutex_unlock(&priv->state_lock);
3061
3062         return err;
3063 }
3064
3065 static int mlx5e_alloc_drop_rq(struct mlx5_core_dev *mdev,
3066                                struct mlx5e_rq *rq,
3067                                struct mlx5e_rq_param *param)
3068 {
3069         void *rqc = param->rqc;
3070         void *rqc_wq = MLX5_ADDR_OF(rqc, rqc, wq);
3071         int err;
3072
3073         param->wq.db_numa_node = param->wq.buf_numa_node;
3074
3075         err = mlx5_wq_cyc_create(mdev, &param->wq, rqc_wq, &rq->wqe.wq,
3076                                  &rq->wq_ctrl);
3077         if (err)
3078                 return err;
3079
3080         /* Mark as unused given "Drop-RQ" packets never reach XDP */
3081         xdp_rxq_info_unused(&rq->xdp_rxq);
3082
3083         rq->mdev = mdev;
3084
3085         return 0;
3086 }
3087
3088 static int mlx5e_alloc_drop_cq(struct mlx5_core_dev *mdev,
3089                                struct mlx5e_cq *cq,
3090                                struct mlx5e_cq_param *param)
3091 {
3092         param->wq.buf_numa_node = dev_to_node(mdev->device);
3093         param->wq.db_numa_node  = dev_to_node(mdev->device);
3094
3095         return mlx5e_alloc_cq_common(mdev, param, cq);
3096 }
3097
3098 int mlx5e_open_drop_rq(struct mlx5e_priv *priv,
3099                        struct mlx5e_rq *drop_rq)
3100 {
3101         struct mlx5_core_dev *mdev = priv->mdev;
3102         struct mlx5e_cq_param cq_param = {};
3103         struct mlx5e_rq_param rq_param = {};
3104         struct mlx5e_cq *cq = &drop_rq->cq;
3105         int err;
3106
3107         mlx5e_build_drop_rq_param(priv, &rq_param);
3108
3109         err = mlx5e_alloc_drop_cq(mdev, cq, &cq_param);
3110         if (err)
3111                 return err;
3112
3113         err = mlx5e_create_cq(cq, &cq_param);
3114         if (err)
3115                 goto err_free_cq;
3116
3117         err = mlx5e_alloc_drop_rq(mdev, drop_rq, &rq_param);
3118         if (err)
3119                 goto err_destroy_cq;
3120
3121         err = mlx5e_create_rq(drop_rq, &rq_param);
3122         if (err)
3123                 goto err_free_rq;
3124
3125         err = mlx5e_modify_rq_state(drop_rq, MLX5_RQC_STATE_RST, MLX5_RQC_STATE_RDY);
3126         if (err)
3127                 mlx5_core_warn(priv->mdev, "modify_rq_state failed, rx_if_down_packets won't be counted %d\n", err);
3128
3129         return 0;
3130
3131 err_free_rq:
3132         mlx5e_free_rq(drop_rq);
3133
3134 err_destroy_cq:
3135         mlx5e_destroy_cq(cq);
3136
3137 err_free_cq:
3138         mlx5e_free_cq(cq);
3139
3140         return err;
3141 }
3142
3143 void mlx5e_close_drop_rq(struct mlx5e_rq *drop_rq)
3144 {
3145         mlx5e_destroy_rq(drop_rq);
3146         mlx5e_free_rq(drop_rq);
3147         mlx5e_destroy_cq(&drop_rq->cq);
3148         mlx5e_free_cq(&drop_rq->cq);
3149 }
3150
3151 int mlx5e_create_tis(struct mlx5_core_dev *mdev, void *in, u32 *tisn)
3152 {
3153         void *tisc = MLX5_ADDR_OF(create_tis_in, in, ctx);
3154
3155         MLX5_SET(tisc, tisc, transport_domain, mdev->mlx5e_res.td.tdn);
3156
3157         if (MLX5_GET(tisc, tisc, tls_en))
3158                 MLX5_SET(tisc, tisc, pd, mdev->mlx5e_res.pdn);
3159
3160         if (mlx5_lag_is_lacp_owner(mdev))
3161                 MLX5_SET(tisc, tisc, strict_lag_tx_port_affinity, 1);
3162
3163         return mlx5_core_create_tis(mdev, in, MLX5_ST_SZ_BYTES(create_tis_in), tisn);
3164 }
3165
3166 void mlx5e_destroy_tis(struct mlx5_core_dev *mdev, u32 tisn)
3167 {
3168         mlx5_core_destroy_tis(mdev, tisn);
3169 }
3170
3171 int mlx5e_create_tises(struct mlx5e_priv *priv)
3172 {
3173         int err;
3174         int tc;
3175
3176         for (tc = 0; tc < priv->profile->max_tc; tc++) {
3177                 u32 in[MLX5_ST_SZ_DW(create_tis_in)] = {};
3178                 void *tisc;
3179
3180                 tisc = MLX5_ADDR_OF(create_tis_in, in, ctx);
3181
3182                 MLX5_SET(tisc, tisc, prio, tc << 1);
3183
3184                 err = mlx5e_create_tis(priv->mdev, in, &priv->tisn[tc]);
3185                 if (err)
3186                         goto err_close_tises;
3187         }
3188
3189         return 0;
3190
3191 err_close_tises:
3192         for (tc--; tc >= 0; tc--)
3193                 mlx5e_destroy_tis(priv->mdev, priv->tisn[tc]);
3194
3195         return err;
3196 }
3197
3198 static void mlx5e_cleanup_nic_tx(struct mlx5e_priv *priv)
3199 {
3200         int tc;
3201
3202         mlx5e_tx_reporter_destroy(priv);
3203         for (tc = 0; tc < priv->profile->max_tc; tc++)
3204                 mlx5e_destroy_tis(priv->mdev, priv->tisn[tc]);
3205 }
3206
3207 static void mlx5e_build_indir_tir_ctx_common(struct mlx5e_priv *priv,
3208                                              u32 rqtn, u32 *tirc)
3209 {
3210         MLX5_SET(tirc, tirc, transport_domain, priv->mdev->mlx5e_res.td.tdn);
3211         MLX5_SET(tirc, tirc, disp_type, MLX5_TIRC_DISP_TYPE_INDIRECT);
3212         MLX5_SET(tirc, tirc, indirect_table, rqtn);
3213         MLX5_SET(tirc, tirc, tunneled_offload_en,
3214                  priv->channels.params.tunneled_offload_en);
3215
3216         mlx5e_build_tir_ctx_lro(&priv->channels.params, tirc);
3217 }
3218
3219 static void mlx5e_build_indir_tir_ctx(struct mlx5e_priv *priv,
3220                                       enum mlx5e_traffic_types tt,
3221                                       u32 *tirc)
3222 {
3223         mlx5e_build_indir_tir_ctx_common(priv, priv->indir_rqt.rqtn, tirc);
3224         mlx5e_build_indir_tir_ctx_hash(&priv->rss_params,
3225                                        &tirc_default_config[tt], tirc, false);
3226 }
3227
3228 static void mlx5e_build_direct_tir_ctx(struct mlx5e_priv *priv, u32 rqtn, u32 *tirc)
3229 {
3230         mlx5e_build_indir_tir_ctx_common(priv, rqtn, tirc);
3231         MLX5_SET(tirc, tirc, rx_hash_fn, MLX5_RX_HASH_FN_INVERTED_XOR8);
3232 }
3233
3234 static void mlx5e_build_inner_indir_tir_ctx(struct mlx5e_priv *priv,
3235                                             enum mlx5e_traffic_types tt,
3236                                             u32 *tirc)
3237 {
3238         mlx5e_build_indir_tir_ctx_common(priv, priv->indir_rqt.rqtn, tirc);
3239         mlx5e_build_indir_tir_ctx_hash(&priv->rss_params,
3240                                        &tirc_default_config[tt], tirc, true);
3241 }
3242
3243 int mlx5e_create_indirect_tirs(struct mlx5e_priv *priv, bool inner_ttc)
3244 {
3245         struct mlx5e_tir *tir;
3246         void *tirc;
3247         int inlen;
3248         int i = 0;
3249         int err;
3250         u32 *in;
3251         int tt;
3252
3253         inlen = MLX5_ST_SZ_BYTES(create_tir_in);
3254         in = kvzalloc(inlen, GFP_KERNEL);
3255         if (!in)
3256                 return -ENOMEM;
3257
3258         for (tt = 0; tt < MLX5E_NUM_INDIR_TIRS; tt++) {
3259                 memset(in, 0, inlen);
3260                 tir = &priv->indir_tir[tt];
3261                 tirc = MLX5_ADDR_OF(create_tir_in, in, ctx);
3262                 mlx5e_build_indir_tir_ctx(priv, tt, tirc);
3263                 err = mlx5e_create_tir(priv->mdev, tir, in, inlen);
3264                 if (err) {
3265                         mlx5_core_warn(priv->mdev, "create indirect tirs failed, %d\n", err);
3266                         goto err_destroy_inner_tirs;
3267                 }
3268         }
3269
3270         if (!inner_ttc || !mlx5e_tunnel_inner_ft_supported(priv->mdev))
3271                 goto out;
3272
3273         for (i = 0; i < MLX5E_NUM_INDIR_TIRS; i++) {
3274                 memset(in, 0, inlen);
3275                 tir = &priv->inner_indir_tir[i];
3276                 tirc = MLX5_ADDR_OF(create_tir_in, in, ctx);
3277                 mlx5e_build_inner_indir_tir_ctx(priv, i, tirc);
3278                 err = mlx5e_create_tir(priv->mdev, tir, in, inlen);
3279                 if (err) {
3280                         mlx5_core_warn(priv->mdev, "create inner indirect tirs failed, %d\n", err);
3281                         goto err_destroy_inner_tirs;
3282                 }
3283         }
3284
3285 out:
3286         kvfree(in);
3287
3288         return 0;
3289
3290 err_destroy_inner_tirs:
3291         for (i--; i >= 0; i--)
3292                 mlx5e_destroy_tir(priv->mdev, &priv->inner_indir_tir[i]);
3293
3294         for (tt--; tt >= 0; tt--)
3295                 mlx5e_destroy_tir(priv->mdev, &priv->indir_tir[tt]);
3296
3297         kvfree(in);
3298
3299         return err;
3300 }
3301
3302 int mlx5e_create_direct_tirs(struct mlx5e_priv *priv, struct mlx5e_tir *tirs)
3303 {
3304         struct mlx5e_tir *tir;
3305         void *tirc;
3306         int inlen;
3307         int err = 0;
3308         u32 *in;
3309         int ix;
3310
3311         inlen = MLX5_ST_SZ_BYTES(create_tir_in);
3312         in = kvzalloc(inlen, GFP_KERNEL);
3313         if (!in)
3314                 return -ENOMEM;
3315
3316         for (ix = 0; ix < priv->max_nch; ix++) {
3317                 memset(in, 0, inlen);
3318                 tir = &tirs[ix];
3319                 tirc = MLX5_ADDR_OF(create_tir_in, in, ctx);
3320                 mlx5e_build_direct_tir_ctx(priv, tir->rqt.rqtn, tirc);
3321                 err = mlx5e_create_tir(priv->mdev, tir, in, inlen);
3322                 if (unlikely(err))
3323                         goto err_destroy_ch_tirs;
3324         }
3325
3326         goto out;
3327
3328 err_destroy_ch_tirs:
3329         mlx5_core_warn(priv->mdev, "create tirs failed, %d\n", err);
3330         for (ix--; ix >= 0; ix--)
3331                 mlx5e_destroy_tir(priv->mdev, &tirs[ix]);
3332
3333 out:
3334         kvfree(in);
3335
3336         return err;
3337 }
3338
3339 void mlx5e_destroy_indirect_tirs(struct mlx5e_priv *priv, bool inner_ttc)
3340 {
3341         int i;
3342
3343         for (i = 0; i < MLX5E_NUM_INDIR_TIRS; i++)
3344                 mlx5e_destroy_tir(priv->mdev, &priv->indir_tir[i]);
3345
3346         if (!inner_ttc || !mlx5e_tunnel_inner_ft_supported(priv->mdev))
3347                 return;
3348
3349         for (i = 0; i < MLX5E_NUM_INDIR_TIRS; i++)
3350                 mlx5e_destroy_tir(priv->mdev, &priv->inner_indir_tir[i]);
3351 }
3352
3353 void mlx5e_destroy_direct_tirs(struct mlx5e_priv *priv, struct mlx5e_tir *tirs)
3354 {
3355         int i;
3356
3357         for (i = 0; i < priv->max_nch; i++)
3358                 mlx5e_destroy_tir(priv->mdev, &tirs[i]);
3359 }
3360
3361 static int mlx5e_modify_channels_scatter_fcs(struct mlx5e_channels *chs, bool enable)
3362 {
3363         int err = 0;
3364         int i;
3365
3366         for (i = 0; i < chs->num; i++) {
3367                 err = mlx5e_modify_rq_scatter_fcs(&chs->c[i]->rq, enable);
3368                 if (err)
3369                         return err;
3370         }
3371
3372         return 0;
3373 }
3374
3375 static int mlx5e_modify_channels_vsd(struct mlx5e_channels *chs, bool vsd)
3376 {
3377         int err = 0;
3378         int i;
3379
3380         for (i = 0; i < chs->num; i++) {
3381                 err = mlx5e_modify_rq_vsd(&chs->c[i]->rq, vsd);
3382                 if (err)
3383                         return err;
3384         }
3385
3386         return 0;
3387 }
3388
3389 static int mlx5e_setup_tc_mqprio(struct mlx5e_priv *priv,
3390                                  struct tc_mqprio_qopt *mqprio)
3391 {
3392         struct mlx5e_channels new_channels = {};
3393         u8 tc = mqprio->num_tc;
3394         int err = 0;
3395
3396         mqprio->hw = TC_MQPRIO_HW_OFFLOAD_TCS;
3397
3398         if (tc && tc != MLX5E_MAX_NUM_TC)
3399                 return -EINVAL;
3400
3401         mutex_lock(&priv->state_lock);
3402
3403         new_channels.params = priv->channels.params;
3404         new_channels.params.num_tc = tc ? tc : 1;
3405
3406         if (!test_bit(MLX5E_STATE_OPENED, &priv->state)) {
3407                 priv->channels.params = new_channels.params;
3408                 goto out;
3409         }
3410
3411         err = mlx5e_safe_switch_channels(priv, &new_channels, NULL);
3412         if (err)
3413                 goto out;
3414
3415         priv->max_opened_tc = max_t(u8, priv->max_opened_tc,
3416                                     new_channels.params.num_tc);
3417 out:
3418         mutex_unlock(&priv->state_lock);
3419         return err;
3420 }
3421
3422 #ifdef CONFIG_MLX5_ESWITCH
3423 static int mlx5e_setup_tc_cls_flower(struct mlx5e_priv *priv,
3424                                      struct flow_cls_offload *cls_flower,
3425                                      int flags)
3426 {
3427         switch (cls_flower->command) {
3428         case FLOW_CLS_REPLACE:
3429                 return mlx5e_configure_flower(priv->netdev, priv, cls_flower,
3430                                               flags);
3431         case FLOW_CLS_DESTROY:
3432                 return mlx5e_delete_flower(priv->netdev, priv, cls_flower,
3433                                            flags);
3434         case FLOW_CLS_STATS:
3435                 return mlx5e_stats_flower(priv->netdev, priv, cls_flower,
3436                                           flags);
3437         default:
3438                 return -EOPNOTSUPP;
3439         }
3440 }
3441
3442 static int mlx5e_setup_tc_block_cb(enum tc_setup_type type, void *type_data,
3443                                    void *cb_priv)
3444 {
3445         struct mlx5e_priv *priv = cb_priv;
3446
3447         switch (type) {
3448         case TC_SETUP_CLSFLOWER:
3449                 return mlx5e_setup_tc_cls_flower(priv, type_data, MLX5E_TC_INGRESS |
3450                                                  MLX5E_TC_NIC_OFFLOAD);
3451         default:
3452                 return -EOPNOTSUPP;
3453         }
3454 }
3455 #endif
3456
3457 static LIST_HEAD(mlx5e_block_cb_list);
3458
3459 static int mlx5e_setup_tc(struct net_device *dev, enum tc_setup_type type,
3460                           void *type_data)
3461 {
3462         struct mlx5e_priv *priv = netdev_priv(dev);
3463
3464         switch (type) {
3465 #ifdef CONFIG_MLX5_ESWITCH
3466         case TC_SETUP_BLOCK:
3467                 return flow_block_cb_setup_simple(type_data,
3468                                                   &mlx5e_block_cb_list,
3469                                                   mlx5e_setup_tc_block_cb,
3470                                                   priv, priv, true);
3471 #endif
3472         case TC_SETUP_QDISC_MQPRIO:
3473                 return mlx5e_setup_tc_mqprio(priv, type_data);
3474         default:
3475                 return -EOPNOTSUPP;
3476         }
3477 }
3478
3479 void mlx5e_fold_sw_stats64(struct mlx5e_priv *priv, struct rtnl_link_stats64 *s)
3480 {
3481         int i;
3482
3483         for (i = 0; i < priv->max_nch; i++) {
3484                 struct mlx5e_channel_stats *channel_stats = &priv->channel_stats[i];
3485                 struct mlx5e_rq_stats *xskrq_stats = &channel_stats->xskrq;
3486                 struct mlx5e_rq_stats *rq_stats = &channel_stats->rq;
3487                 int j;
3488
3489                 s->rx_packets   += rq_stats->packets + xskrq_stats->packets;
3490                 s->rx_bytes     += rq_stats->bytes + xskrq_stats->bytes;
3491
3492                 for (j = 0; j < priv->max_opened_tc; j++) {
3493                         struct mlx5e_sq_stats *sq_stats = &channel_stats->sq[j];
3494
3495                         s->tx_packets    += sq_stats->packets;
3496                         s->tx_bytes      += sq_stats->bytes;
3497                         s->tx_dropped    += sq_stats->dropped;
3498                 }
3499         }
3500 }
3501
3502 void
3503 mlx5e_get_stats(struct net_device *dev, struct rtnl_link_stats64 *stats)
3504 {
3505         struct mlx5e_priv *priv = netdev_priv(dev);
3506         struct mlx5e_vport_stats *vstats = &priv->stats.vport;
3507         struct mlx5e_pport_stats *pstats = &priv->stats.pport;
3508
3509         if (!mlx5e_monitor_counter_supported(priv)) {
3510                 /* update HW stats in background for next time */
3511                 mlx5e_queue_update_stats(priv);
3512         }
3513
3514         if (mlx5e_is_uplink_rep(priv)) {
3515                 stats->rx_packets = PPORT_802_3_GET(pstats, a_frames_received_ok);
3516                 stats->rx_bytes   = PPORT_802_3_GET(pstats, a_octets_received_ok);
3517                 stats->tx_packets = PPORT_802_3_GET(pstats, a_frames_transmitted_ok);
3518                 stats->tx_bytes   = PPORT_802_3_GET(pstats, a_octets_transmitted_ok);
3519         } else {
3520                 mlx5e_fold_sw_stats64(priv, stats);
3521         }
3522
3523         stats->rx_dropped = priv->stats.qcnt.rx_out_of_buffer;
3524
3525         stats->rx_length_errors =
3526                 PPORT_802_3_GET(pstats, a_in_range_length_errors) +
3527                 PPORT_802_3_GET(pstats, a_out_of_range_length_field) +
3528                 PPORT_802_3_GET(pstats, a_frame_too_long_errors);
3529         stats->rx_crc_errors =
3530                 PPORT_802_3_GET(pstats, a_frame_check_sequence_errors);
3531         stats->rx_frame_errors = PPORT_802_3_GET(pstats, a_alignment_errors);
3532         stats->tx_aborted_errors = PPORT_2863_GET(pstats, if_out_discards);
3533         stats->rx_errors = stats->rx_length_errors + stats->rx_crc_errors +
3534                            stats->rx_frame_errors;
3535         stats->tx_errors = stats->tx_aborted_errors + stats->tx_carrier_errors;
3536
3537         /* vport multicast also counts packets that are dropped due to steering
3538          * or rx out of buffer
3539          */
3540         stats->multicast =
3541                 VPORT_COUNTER_GET(vstats, received_eth_multicast.packets);
3542 }
3543
3544 static void mlx5e_set_rx_mode(struct net_device *dev)
3545 {
3546         struct mlx5e_priv *priv = netdev_priv(dev);
3547
3548         queue_work(priv->wq, &priv->set_rx_mode_work);
3549 }
3550
3551 static int mlx5e_set_mac(struct net_device *netdev, void *addr)
3552 {
3553         struct mlx5e_priv *priv = netdev_priv(netdev);
3554         struct sockaddr *saddr = addr;
3555
3556         if (!is_valid_ether_addr(saddr->sa_data))
3557                 return -EADDRNOTAVAIL;
3558
3559         netif_addr_lock_bh(netdev);
3560         ether_addr_copy(netdev->dev_addr, saddr->sa_data);
3561         netif_addr_unlock_bh(netdev);
3562
3563         queue_work(priv->wq, &priv->set_rx_mode_work);
3564
3565         return 0;
3566 }
3567
3568 #define MLX5E_SET_FEATURE(features, feature, enable)    \
3569         do {                                            \
3570                 if (enable)                             \
3571                         *features |= feature;           \
3572                 else                                    \
3573                         *features &= ~feature;          \
3574         } while (0)
3575
3576 typedef int (*mlx5e_feature_handler)(struct net_device *netdev, bool enable);
3577
3578 static int set_feature_lro(struct net_device *netdev, bool enable)
3579 {
3580         struct mlx5e_priv *priv = netdev_priv(netdev);
3581         struct mlx5_core_dev *mdev = priv->mdev;
3582         struct mlx5e_channels new_channels = {};
3583         struct mlx5e_params *old_params;
3584         int err = 0;
3585         bool reset;
3586
3587         mutex_lock(&priv->state_lock);
3588
3589         if (enable && priv->xsk.refcnt) {
3590                 netdev_warn(netdev, "LRO is incompatible with AF_XDP (%hu XSKs are active)\n",
3591                             priv->xsk.refcnt);
3592                 err = -EINVAL;
3593                 goto out;
3594         }
3595
3596         old_params = &priv->channels.params;
3597         if (enable && !MLX5E_GET_PFLAG(old_params, MLX5E_PFLAG_RX_STRIDING_RQ)) {
3598                 netdev_warn(netdev, "can't set LRO with legacy RQ\n");
3599                 err = -EINVAL;
3600                 goto out;
3601         }
3602
3603         reset = test_bit(MLX5E_STATE_OPENED, &priv->state);
3604
3605         new_channels.params = *old_params;
3606         new_channels.params.lro_en = enable;
3607
3608         if (old_params->rq_wq_type != MLX5_WQ_TYPE_CYCLIC) {
3609                 if (mlx5e_rx_mpwqe_is_linear_skb(mdev, old_params, NULL) ==
3610                     mlx5e_rx_mpwqe_is_linear_skb(mdev, &new_channels.params, NULL))
3611                         reset = false;
3612         }
3613
3614         if (!reset) {
3615                 *old_params = new_channels.params;
3616                 err = mlx5e_modify_tirs_lro(priv);
3617                 goto out;
3618         }
3619
3620         err = mlx5e_safe_switch_channels(priv, &new_channels, mlx5e_modify_tirs_lro);
3621 out:
3622         mutex_unlock(&priv->state_lock);
3623         return err;
3624 }
3625
3626 static int set_feature_cvlan_filter(struct net_device *netdev, bool enable)
3627 {
3628         struct mlx5e_priv *priv = netdev_priv(netdev);
3629
3630         if (enable)
3631                 mlx5e_enable_cvlan_filter(priv);
3632         else
3633                 mlx5e_disable_cvlan_filter(priv);
3634
3635         return 0;
3636 }
3637
3638 #ifdef CONFIG_MLX5_ESWITCH
3639 static int set_feature_tc_num_filters(struct net_device *netdev, bool enable)
3640 {
3641         struct mlx5e_priv *priv = netdev_priv(netdev);
3642
3643         if (!enable && mlx5e_tc_num_filters(priv, MLX5E_TC_NIC_OFFLOAD)) {
3644                 netdev_err(netdev,
3645                            "Active offloaded tc filters, can't turn hw_tc_offload off\n");
3646                 return -EINVAL;
3647         }
3648
3649         return 0;
3650 }
3651 #endif
3652
3653 static int set_feature_rx_all(struct net_device *netdev, bool enable)
3654 {
3655         struct mlx5e_priv *priv = netdev_priv(netdev);
3656         struct mlx5_core_dev *mdev = priv->mdev;
3657
3658         return mlx5_set_port_fcs(mdev, !enable);
3659 }
3660
3661 static int set_feature_rx_fcs(struct net_device *netdev, bool enable)
3662 {
3663         struct mlx5e_priv *priv = netdev_priv(netdev);
3664         int err;
3665
3666         mutex_lock(&priv->state_lock);
3667
3668         priv->channels.params.scatter_fcs_en = enable;
3669         err = mlx5e_modify_channels_scatter_fcs(&priv->channels, enable);
3670         if (err)
3671                 priv->channels.params.scatter_fcs_en = !enable;
3672
3673         mutex_unlock(&priv->state_lock);
3674
3675         return err;
3676 }
3677
3678 static int set_feature_rx_vlan(struct net_device *netdev, bool enable)
3679 {
3680         struct mlx5e_priv *priv = netdev_priv(netdev);
3681         int err = 0;
3682
3683         mutex_lock(&priv->state_lock);
3684
3685         priv->channels.params.vlan_strip_disable = !enable;
3686         if (!test_bit(MLX5E_STATE_OPENED, &priv->state))
3687                 goto unlock;
3688
3689         err = mlx5e_modify_channels_vsd(&priv->channels, !enable);
3690         if (err)
3691                 priv->channels.params.vlan_strip_disable = enable;
3692
3693 unlock:
3694         mutex_unlock(&priv->state_lock);
3695
3696         return err;
3697 }
3698
3699 #ifdef CONFIG_MLX5_EN_ARFS
3700 static int set_feature_arfs(struct net_device *netdev, bool enable)
3701 {
3702         struct mlx5e_priv *priv = netdev_priv(netdev);
3703         int err;
3704
3705         if (enable)
3706                 err = mlx5e_arfs_enable(priv);
3707         else
3708                 err = mlx5e_arfs_disable(priv);
3709
3710         return err;
3711 }
3712 #endif
3713
3714 static int mlx5e_handle_feature(struct net_device *netdev,
3715                                 netdev_features_t *features,
3716                                 netdev_features_t wanted_features,
3717                                 netdev_features_t feature,
3718                                 mlx5e_feature_handler feature_handler)
3719 {
3720         netdev_features_t changes = wanted_features ^ netdev->features;
3721         bool enable = !!(wanted_features & feature);
3722         int err;
3723
3724         if (!(changes & feature))
3725                 return 0;
3726
3727         err = feature_handler(netdev, enable);
3728         if (err) {
3729                 netdev_err(netdev, "%s feature %pNF failed, err %d\n",
3730                            enable ? "Enable" : "Disable", &feature, err);
3731                 return err;
3732         }
3733
3734         MLX5E_SET_FEATURE(features, feature, enable);
3735         return 0;
3736 }
3737
3738 int mlx5e_set_features(struct net_device *netdev, netdev_features_t features)
3739 {
3740         netdev_features_t oper_features = netdev->features;
3741         int err = 0;
3742
3743 #define MLX5E_HANDLE_FEATURE(feature, handler) \
3744         mlx5e_handle_feature(netdev, &oper_features, features, feature, handler)
3745
3746         err |= MLX5E_HANDLE_FEATURE(NETIF_F_LRO, set_feature_lro);
3747         err |= MLX5E_HANDLE_FEATURE(NETIF_F_HW_VLAN_CTAG_FILTER,
3748                                     set_feature_cvlan_filter);
3749 #ifdef CONFIG_MLX5_ESWITCH
3750         err |= MLX5E_HANDLE_FEATURE(NETIF_F_HW_TC, set_feature_tc_num_filters);
3751 #endif
3752         err |= MLX5E_HANDLE_FEATURE(NETIF_F_RXALL, set_feature_rx_all);
3753         err |= MLX5E_HANDLE_FEATURE(NETIF_F_RXFCS, set_feature_rx_fcs);
3754         err |= MLX5E_HANDLE_FEATURE(NETIF_F_HW_VLAN_CTAG_RX, set_feature_rx_vlan);
3755 #ifdef CONFIG_MLX5_EN_ARFS
3756         err |= MLX5E_HANDLE_FEATURE(NETIF_F_NTUPLE, set_feature_arfs);
3757 #endif
3758
3759         if (err) {
3760                 netdev->features = oper_features;
3761                 return -EINVAL;
3762         }
3763
3764         return 0;
3765 }
3766
3767 static netdev_features_t mlx5e_fix_features(struct net_device *netdev,
3768                                             netdev_features_t features)
3769 {
3770         struct mlx5e_priv *priv = netdev_priv(netdev);
3771         struct mlx5e_params *params;
3772
3773         mutex_lock(&priv->state_lock);
3774         params = &priv->channels.params;
3775         if (!bitmap_empty(priv->fs.vlan.active_svlans, VLAN_N_VID)) {
3776                 /* HW strips the outer C-tag header, this is a problem
3777                  * for S-tag traffic.
3778                  */
3779                 features &= ~NETIF_F_HW_VLAN_CTAG_RX;
3780                 if (!params->vlan_strip_disable)
3781                         netdev_warn(netdev, "Dropping C-tag vlan stripping offload due to S-tag vlan\n");
3782         }
3783         if (!MLX5E_GET_PFLAG(params, MLX5E_PFLAG_RX_STRIDING_RQ)) {
3784                 features &= ~NETIF_F_LRO;
3785                 if (params->lro_en)
3786                         netdev_warn(netdev, "Disabling LRO, not supported in legacy RQ\n");
3787         }
3788
3789         if (MLX5E_GET_PFLAG(params, MLX5E_PFLAG_RX_CQE_COMPRESS)) {
3790                 features &= ~NETIF_F_RXHASH;
3791                 if (netdev->features & NETIF_F_RXHASH)
3792                         netdev_warn(netdev, "Disabling rxhash, not supported when CQE compress is active\n");
3793         }
3794
3795         mutex_unlock(&priv->state_lock);
3796
3797         return features;
3798 }
3799
3800 static bool mlx5e_xsk_validate_mtu(struct net_device *netdev,
3801                                    struct mlx5e_channels *chs,
3802                                    struct mlx5e_params *new_params,
3803                                    struct mlx5_core_dev *mdev)
3804 {
3805         u16 ix;
3806
3807         for (ix = 0; ix < chs->params.num_channels; ix++) {
3808                 struct xdp_umem *umem = mlx5e_xsk_get_umem(&chs->params, chs->params.xsk, ix);
3809                 struct mlx5e_xsk_param xsk;
3810
3811                 if (!umem)
3812                         continue;
3813
3814                 mlx5e_build_xsk_param(umem, &xsk);
3815
3816                 if (!mlx5e_validate_xsk_param(new_params, &xsk, mdev)) {
3817                         u32 hr = mlx5e_get_linear_rq_headroom(new_params, &xsk);
3818                         int max_mtu_frame, max_mtu_page, max_mtu;
3819
3820                         /* Two criteria must be met:
3821                          * 1. HW MTU + all headrooms <= XSK frame size.
3822                          * 2. Size of SKBs allocated on XDP_PASS <= PAGE_SIZE.
3823                          */
3824                         max_mtu_frame = MLX5E_HW2SW_MTU(new_params, xsk.chunk_size - hr);
3825                         max_mtu_page = mlx5e_xdp_max_mtu(new_params, &xsk);
3826                         max_mtu = min(max_mtu_frame, max_mtu_page);
3827
3828                         netdev_err(netdev, "MTU %d is too big for an XSK running on channel %hu. Try MTU <= %d\n",
3829                                    new_params->sw_mtu, ix, max_mtu);
3830                         return false;
3831                 }
3832         }
3833
3834         return true;
3835 }
3836
3837 int mlx5e_change_mtu(struct net_device *netdev, int new_mtu,
3838                      change_hw_mtu_cb set_mtu_cb)
3839 {
3840         struct mlx5e_priv *priv = netdev_priv(netdev);
3841         struct mlx5e_channels new_channels = {};
3842         struct mlx5e_params *params;
3843         int err = 0;
3844         bool reset;
3845
3846         mutex_lock(&priv->state_lock);
3847
3848         params = &priv->channels.params;
3849
3850         reset = !params->lro_en;
3851         reset = reset && test_bit(MLX5E_STATE_OPENED, &priv->state);
3852
3853         new_channels.params = *params;
3854         new_channels.params.sw_mtu = new_mtu;
3855
3856         if (params->xdp_prog &&
3857             !mlx5e_rx_is_linear_skb(&new_channels.params, NULL)) {
3858                 netdev_err(netdev, "MTU(%d) > %d is not allowed while XDP enabled\n",
3859                            new_mtu, mlx5e_xdp_max_mtu(params, NULL));
3860                 err = -EINVAL;
3861                 goto out;
3862         }
3863
3864         if (priv->xsk.refcnt &&
3865             !mlx5e_xsk_validate_mtu(netdev, &priv->channels,
3866                                     &new_channels.params, priv->mdev)) {
3867                 err = -EINVAL;
3868                 goto out;
3869         }
3870
3871         if (params->rq_wq_type == MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ) {
3872                 bool is_linear = mlx5e_rx_mpwqe_is_linear_skb(priv->mdev,
3873                                                               &new_channels.params,
3874                                                               NULL);
3875                 u8 ppw_old = mlx5e_mpwqe_log_pkts_per_wqe(params, NULL);
3876                 u8 ppw_new = mlx5e_mpwqe_log_pkts_per_wqe(&new_channels.params, NULL);
3877
3878                 /* If XSK is active, XSK RQs are linear. */
3879                 is_linear |= priv->xsk.refcnt;
3880
3881                 /* Always reset in linear mode - hw_mtu is used in data path. */
3882                 reset = reset && (is_linear || (ppw_old != ppw_new));
3883         }
3884
3885         if (!reset) {
3886                 params->sw_mtu = new_mtu;
3887                 if (set_mtu_cb)
3888                         set_mtu_cb(priv);
3889                 netdev->mtu = params->sw_mtu;
3890                 goto out;
3891         }
3892
3893         err = mlx5e_safe_switch_channels(priv, &new_channels, set_mtu_cb);
3894         if (err)
3895                 goto out;
3896
3897         netdev->mtu = new_channels.params.sw_mtu;
3898
3899 out:
3900         mutex_unlock(&priv->state_lock);
3901         return err;
3902 }
3903
3904 static int mlx5e_change_nic_mtu(struct net_device *netdev, int new_mtu)
3905 {
3906         return mlx5e_change_mtu(netdev, new_mtu, mlx5e_set_dev_port_mtu);
3907 }
3908
3909 int mlx5e_hwstamp_set(struct mlx5e_priv *priv, struct ifreq *ifr)
3910 {
3911         struct hwtstamp_config config;
3912         int err;
3913
3914         if (!MLX5_CAP_GEN(priv->mdev, device_frequency_khz) ||
3915             (mlx5_clock_get_ptp_index(priv->mdev) == -1))
3916                 return -EOPNOTSUPP;
3917
3918         if (copy_from_user(&config, ifr->ifr_data, sizeof(config)))
3919                 return -EFAULT;
3920
3921         /* TX HW timestamp */
3922         switch (config.tx_type) {
3923         case HWTSTAMP_TX_OFF:
3924         case HWTSTAMP_TX_ON:
3925                 break;
3926         default:
3927                 return -ERANGE;
3928         }
3929
3930         mutex_lock(&priv->state_lock);
3931         /* RX HW timestamp */
3932         switch (config.rx_filter) {
3933         case HWTSTAMP_FILTER_NONE:
3934                 /* Reset CQE compression to Admin default */
3935                 mlx5e_modify_rx_cqe_compression_locked(priv, priv->channels.params.rx_cqe_compress_def);
3936                 break;
3937         case HWTSTAMP_FILTER_ALL:
3938         case HWTSTAMP_FILTER_SOME:
3939         case HWTSTAMP_FILTER_PTP_V1_L4_EVENT:
3940         case HWTSTAMP_FILTER_PTP_V1_L4_SYNC:
3941         case HWTSTAMP_FILTER_PTP_V1_L4_DELAY_REQ:
3942         case HWTSTAMP_FILTER_PTP_V2_L4_EVENT:
3943         case HWTSTAMP_FILTER_PTP_V2_L4_SYNC:
3944         case HWTSTAMP_FILTER_PTP_V2_L4_DELAY_REQ:
3945         case HWTSTAMP_FILTER_PTP_V2_L2_EVENT:
3946         case HWTSTAMP_FILTER_PTP_V2_L2_SYNC:
3947         case HWTSTAMP_FILTER_PTP_V2_L2_DELAY_REQ:
3948         case HWTSTAMP_FILTER_PTP_V2_EVENT:
3949         case HWTSTAMP_FILTER_PTP_V2_SYNC:
3950         case HWTSTAMP_FILTER_PTP_V2_DELAY_REQ:
3951         case HWTSTAMP_FILTER_NTP_ALL:
3952                 /* Disable CQE compression */
3953                 netdev_warn(priv->netdev, "Disabling cqe compression");
3954                 err = mlx5e_modify_rx_cqe_compression_locked(priv, false);
3955                 if (err) {
3956                         netdev_err(priv->netdev, "Failed disabling cqe compression err=%d\n", err);
3957                         mutex_unlock(&priv->state_lock);
3958                         return err;
3959                 }
3960                 config.rx_filter = HWTSTAMP_FILTER_ALL;
3961                 break;
3962         default:
3963                 mutex_unlock(&priv->state_lock);
3964                 return -ERANGE;
3965         }
3966
3967         memcpy(&priv->tstamp, &config, sizeof(config));
3968         mutex_unlock(&priv->state_lock);
3969
3970         /* might need to fix some features */
3971         netdev_update_features(priv->netdev);
3972
3973         return copy_to_user(ifr->ifr_data, &config,
3974                             sizeof(config)) ? -EFAULT : 0;
3975 }
3976
3977 int mlx5e_hwstamp_get(struct mlx5e_priv *priv, struct ifreq *ifr)
3978 {
3979         struct hwtstamp_config *cfg = &priv->tstamp;
3980
3981         if (!MLX5_CAP_GEN(priv->mdev, device_frequency_khz))
3982                 return -EOPNOTSUPP;
3983
3984         return copy_to_user(ifr->ifr_data, cfg, sizeof(*cfg)) ? -EFAULT : 0;
3985 }
3986
3987 static int mlx5e_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
3988 {
3989         struct mlx5e_priv *priv = netdev_priv(dev);
3990
3991         switch (cmd) {
3992         case SIOCSHWTSTAMP:
3993                 return mlx5e_hwstamp_set(priv, ifr);
3994         case SIOCGHWTSTAMP:
3995                 return mlx5e_hwstamp_get(priv, ifr);
3996         default:
3997                 return -EOPNOTSUPP;
3998         }
3999 }
4000
4001 #ifdef CONFIG_MLX5_ESWITCH
4002 int mlx5e_set_vf_mac(struct net_device *dev, int vf, u8 *mac)
4003 {
4004         struct mlx5e_priv *priv = netdev_priv(dev);
4005         struct mlx5_core_dev *mdev = priv->mdev;
4006
4007         return mlx5_eswitch_set_vport_mac(mdev->priv.eswitch, vf + 1, mac);
4008 }
4009
4010 static int mlx5e_set_vf_vlan(struct net_device *dev, int vf, u16 vlan, u8 qos,
4011                              __be16 vlan_proto)
4012 {
4013         struct mlx5e_priv *priv = netdev_priv(dev);
4014         struct mlx5_core_dev *mdev = priv->mdev;
4015
4016         if (vlan_proto != htons(ETH_P_8021Q))
4017                 return -EPROTONOSUPPORT;
4018
4019         return mlx5_eswitch_set_vport_vlan(mdev->priv.eswitch, vf + 1,
4020                                            vlan, qos);
4021 }
4022
4023 static int mlx5e_set_vf_spoofchk(struct net_device *dev, int vf, bool setting)
4024 {
4025         struct mlx5e_priv *priv = netdev_priv(dev);
4026         struct mlx5_core_dev *mdev = priv->mdev;
4027
4028         return mlx5_eswitch_set_vport_spoofchk(mdev->priv.eswitch, vf + 1, setting);
4029 }
4030
4031 static int mlx5e_set_vf_trust(struct net_device *dev, int vf, bool setting)
4032 {
4033         struct mlx5e_priv *priv = netdev_priv(dev);
4034         struct mlx5_core_dev *mdev = priv->mdev;
4035
4036         return mlx5_eswitch_set_vport_trust(mdev->priv.eswitch, vf + 1, setting);
4037 }
4038
4039 int mlx5e_set_vf_rate(struct net_device *dev, int vf, int min_tx_rate,
4040                       int max_tx_rate)
4041 {
4042         struct mlx5e_priv *priv = netdev_priv(dev);
4043         struct mlx5_core_dev *mdev = priv->mdev;
4044
4045         return mlx5_eswitch_set_vport_rate(mdev->priv.eswitch, vf + 1,
4046                                            max_tx_rate, min_tx_rate);
4047 }
4048
4049 static int mlx5_vport_link2ifla(u8 esw_link)
4050 {
4051         switch (esw_link) {
4052         case MLX5_VPORT_ADMIN_STATE_DOWN:
4053                 return IFLA_VF_LINK_STATE_DISABLE;
4054         case MLX5_VPORT_ADMIN_STATE_UP:
4055                 return IFLA_VF_LINK_STATE_ENABLE;
4056         }
4057         return IFLA_VF_LINK_STATE_AUTO;
4058 }
4059
4060 static int mlx5_ifla_link2vport(u8 ifla_link)
4061 {
4062         switch (ifla_link) {
4063         case IFLA_VF_LINK_STATE_DISABLE:
4064                 return MLX5_VPORT_ADMIN_STATE_DOWN;
4065         case IFLA_VF_LINK_STATE_ENABLE:
4066                 return MLX5_VPORT_ADMIN_STATE_UP;
4067         }
4068         return MLX5_VPORT_ADMIN_STATE_AUTO;
4069 }
4070
4071 static int mlx5e_set_vf_link_state(struct net_device *dev, int vf,
4072                                    int link_state)
4073 {
4074         struct mlx5e_priv *priv = netdev_priv(dev);
4075         struct mlx5_core_dev *mdev = priv->mdev;
4076
4077         return mlx5_eswitch_set_vport_state(mdev->priv.eswitch, vf + 1,
4078                                             mlx5_ifla_link2vport(link_state));
4079 }
4080
4081 int mlx5e_get_vf_config(struct net_device *dev,
4082                         int vf, struct ifla_vf_info *ivi)
4083 {
4084         struct mlx5e_priv *priv = netdev_priv(dev);
4085         struct mlx5_core_dev *mdev = priv->mdev;
4086         int err;
4087
4088         err = mlx5_eswitch_get_vport_config(mdev->priv.eswitch, vf + 1, ivi);
4089         if (err)
4090                 return err;
4091         ivi->linkstate = mlx5_vport_link2ifla(ivi->linkstate);
4092         return 0;
4093 }
4094
4095 int mlx5e_get_vf_stats(struct net_device *dev,
4096                        int vf, struct ifla_vf_stats *vf_stats)
4097 {
4098         struct mlx5e_priv *priv = netdev_priv(dev);
4099         struct mlx5_core_dev *mdev = priv->mdev;
4100
4101         return mlx5_eswitch_get_vport_stats(mdev->priv.eswitch, vf + 1,
4102                                             vf_stats);
4103 }
4104 #endif
4105
4106 struct mlx5e_vxlan_work {
4107         struct work_struct      work;
4108         struct mlx5e_priv       *priv;
4109         u16                     port;
4110 };
4111
4112 static void mlx5e_vxlan_add_work(struct work_struct *work)
4113 {
4114         struct mlx5e_vxlan_work *vxlan_work =
4115                 container_of(work, struct mlx5e_vxlan_work, work);
4116         struct mlx5e_priv *priv = vxlan_work->priv;
4117         u16 port = vxlan_work->port;
4118
4119         mutex_lock(&priv->state_lock);
4120         mlx5_vxlan_add_port(priv->mdev->vxlan, port);
4121         mutex_unlock(&priv->state_lock);
4122
4123         kfree(vxlan_work);
4124 }
4125
4126 static void mlx5e_vxlan_del_work(struct work_struct *work)
4127 {
4128         struct mlx5e_vxlan_work *vxlan_work =
4129                 container_of(work, struct mlx5e_vxlan_work, work);
4130         struct mlx5e_priv *priv         = vxlan_work->priv;
4131         u16 port = vxlan_work->port;
4132
4133         mutex_lock(&priv->state_lock);
4134         mlx5_vxlan_del_port(priv->mdev->vxlan, port);
4135         mutex_unlock(&priv->state_lock);
4136         kfree(vxlan_work);
4137 }
4138
4139 static void mlx5e_vxlan_queue_work(struct mlx5e_priv *priv, u16 port, int add)
4140 {
4141         struct mlx5e_vxlan_work *vxlan_work;
4142
4143         vxlan_work = kmalloc(sizeof(*vxlan_work), GFP_ATOMIC);
4144         if (!vxlan_work)
4145                 return;
4146
4147         if (add)
4148                 INIT_WORK(&vxlan_work->work, mlx5e_vxlan_add_work);
4149         else
4150                 INIT_WORK(&vxlan_work->work, mlx5e_vxlan_del_work);
4151
4152         vxlan_work->priv = priv;
4153         vxlan_work->port = port;
4154         queue_work(priv->wq, &vxlan_work->work);
4155 }
4156
4157 void mlx5e_add_vxlan_port(struct net_device *netdev, struct udp_tunnel_info *ti)
4158 {
4159         struct mlx5e_priv *priv = netdev_priv(netdev);
4160
4161         if (ti->type != UDP_TUNNEL_TYPE_VXLAN)
4162                 return;
4163
4164         if (!mlx5_vxlan_allowed(priv->mdev->vxlan))
4165                 return;
4166
4167         mlx5e_vxlan_queue_work(priv, be16_to_cpu(ti->port), 1);
4168 }
4169
4170 void mlx5e_del_vxlan_port(struct net_device *netdev, struct udp_tunnel_info *ti)
4171 {
4172         struct mlx5e_priv *priv = netdev_priv(netdev);
4173
4174         if (ti->type != UDP_TUNNEL_TYPE_VXLAN)
4175                 return;
4176
4177         if (!mlx5_vxlan_allowed(priv->mdev->vxlan))
4178                 return;
4179
4180         mlx5e_vxlan_queue_work(priv, be16_to_cpu(ti->port), 0);
4181 }
4182
4183 static netdev_features_t mlx5e_tunnel_features_check(struct mlx5e_priv *priv,
4184                                                      struct sk_buff *skb,
4185                                                      netdev_features_t features)
4186 {
4187         unsigned int offset = 0;
4188         struct udphdr *udph;
4189         u8 proto;
4190         u16 port;
4191
4192         switch (vlan_get_protocol(skb)) {
4193         case htons(ETH_P_IP):
4194                 proto = ip_hdr(skb)->protocol;
4195                 break;
4196         case htons(ETH_P_IPV6):
4197                 proto = ipv6_find_hdr(skb, &offset, -1, NULL, NULL);
4198                 break;
4199         default:
4200                 goto out;
4201         }
4202
4203         switch (proto) {
4204         case IPPROTO_GRE:
4205                 return features;
4206         case IPPROTO_UDP:
4207                 udph = udp_hdr(skb);
4208                 port = be16_to_cpu(udph->dest);
4209
4210                 /* Verify if UDP port is being offloaded by HW */
4211                 if (mlx5_vxlan_lookup_port(priv->mdev->vxlan, port))
4212                         return features;
4213
4214 #if IS_ENABLED(CONFIG_GENEVE)
4215                 /* Support Geneve offload for default UDP port */
4216                 if (port == GENEVE_UDP_PORT && mlx5_geneve_tx_allowed(priv->mdev))
4217                         return features;
4218 #endif
4219         }
4220
4221 out:
4222         /* Disable CSUM and GSO if the udp dport is not offloaded by HW */
4223         return features & ~(NETIF_F_CSUM_MASK | NETIF_F_GSO_MASK);
4224 }
4225
4226 netdev_features_t mlx5e_features_check(struct sk_buff *skb,
4227                                        struct net_device *netdev,
4228                                        netdev_features_t features)
4229 {
4230         struct mlx5e_priv *priv = netdev_priv(netdev);
4231
4232         features = vlan_features_check(skb, features);
4233         features = vxlan_features_check(skb, features);
4234
4235 #ifdef CONFIG_MLX5_EN_IPSEC
4236         if (mlx5e_ipsec_feature_check(skb, netdev, features))
4237                 return features;
4238 #endif
4239
4240         /* Validate if the tunneled packet is being offloaded by HW */
4241         if (skb->encapsulation &&
4242             (features & NETIF_F_CSUM_MASK || features & NETIF_F_GSO_MASK))
4243                 return mlx5e_tunnel_features_check(priv, skb, features);
4244
4245         return features;
4246 }
4247
4248 static void mlx5e_tx_timeout_work(struct work_struct *work)
4249 {
4250         struct mlx5e_priv *priv = container_of(work, struct mlx5e_priv,
4251                                                tx_timeout_work);
4252         bool report_failed = false;
4253         int err;
4254         int i;
4255
4256         rtnl_lock();
4257         mutex_lock(&priv->state_lock);
4258
4259         if (!test_bit(MLX5E_STATE_OPENED, &priv->state))
4260                 goto unlock;
4261
4262         for (i = 0; i < priv->channels.num * priv->channels.params.num_tc; i++) {
4263                 struct netdev_queue *dev_queue =
4264                         netdev_get_tx_queue(priv->netdev, i);
4265                 struct mlx5e_txqsq *sq = priv->txq2sq[i];
4266
4267                 if (!netif_xmit_stopped(dev_queue))
4268                         continue;
4269
4270                 if (mlx5e_tx_reporter_timeout(sq))
4271                         report_failed = true;
4272         }
4273
4274         if (!report_failed)
4275                 goto unlock;
4276
4277         err = mlx5e_safe_reopen_channels(priv);
4278         if (err)
4279                 netdev_err(priv->netdev,
4280                            "mlx5e_safe_reopen_channels failed recovering from a tx_timeout, err(%d).\n",
4281                            err);
4282
4283 unlock:
4284         mutex_unlock(&priv->state_lock);
4285         rtnl_unlock();
4286 }
4287
4288 static void mlx5e_tx_timeout(struct net_device *dev)
4289 {
4290         struct mlx5e_priv *priv = netdev_priv(dev);
4291
4292         netdev_err(dev, "TX timeout detected\n");
4293         queue_work(priv->wq, &priv->tx_timeout_work);
4294 }
4295
4296 static int mlx5e_xdp_allowed(struct mlx5e_priv *priv, struct bpf_prog *prog)
4297 {
4298         struct net_device *netdev = priv->netdev;
4299         struct mlx5e_channels new_channels = {};
4300
4301         if (priv->channels.params.lro_en) {
4302                 netdev_warn(netdev, "can't set XDP while LRO is on, disable LRO first\n");
4303                 return -EINVAL;
4304         }
4305
4306         if (MLX5_IPSEC_DEV(priv->mdev)) {
4307                 netdev_warn(netdev, "can't set XDP with IPSec offload\n");
4308                 return -EINVAL;
4309         }
4310
4311         new_channels.params = priv->channels.params;
4312         new_channels.params.xdp_prog = prog;
4313
4314         /* No XSK params: AF_XDP can't be enabled yet at the point of setting
4315          * the XDP program.
4316          */
4317         if (!mlx5e_rx_is_linear_skb(&new_channels.params, NULL)) {
4318                 netdev_warn(netdev, "XDP is not allowed with MTU(%d) > %d\n",
4319                             new_channels.params.sw_mtu,
4320                             mlx5e_xdp_max_mtu(&new_channels.params, NULL));
4321                 return -EINVAL;
4322         }
4323
4324         return 0;
4325 }
4326
4327 static int mlx5e_xdp_update_state(struct mlx5e_priv *priv)
4328 {
4329         if (priv->channels.params.xdp_prog)
4330                 mlx5e_xdp_set_open(priv);
4331         else
4332                 mlx5e_xdp_set_closed(priv);
4333
4334         return 0;
4335 }
4336
4337 static int mlx5e_xdp_set(struct net_device *netdev, struct bpf_prog *prog)
4338 {
4339         struct mlx5e_priv *priv = netdev_priv(netdev);
4340         struct bpf_prog *old_prog;
4341         bool reset, was_opened;
4342         int err = 0;
4343         int i;
4344
4345         mutex_lock(&priv->state_lock);
4346
4347         if (prog) {
4348                 err = mlx5e_xdp_allowed(priv, prog);
4349                 if (err)
4350                         goto unlock;
4351         }
4352
4353         was_opened = test_bit(MLX5E_STATE_OPENED, &priv->state);
4354         /* no need for full reset when exchanging programs */
4355         reset = (!priv->channels.params.xdp_prog || !prog);
4356
4357         if (was_opened && !reset) {
4358                 /* num_channels is invariant here, so we can take the
4359                  * batched reference right upfront.
4360                  */
4361                 prog = bpf_prog_add(prog, priv->channels.num);
4362                 if (IS_ERR(prog)) {
4363                         err = PTR_ERR(prog);
4364                         goto unlock;
4365                 }
4366         }
4367
4368         if (was_opened && reset) {
4369                 struct mlx5e_channels new_channels = {};
4370
4371                 new_channels.params = priv->channels.params;
4372                 new_channels.params.xdp_prog = prog;
4373                 mlx5e_set_rq_type(priv->mdev, &new_channels.params);
4374                 old_prog = priv->channels.params.xdp_prog;
4375
4376                 err = mlx5e_safe_switch_channels(priv, &new_channels, mlx5e_xdp_update_state);
4377                 if (err)
4378                         goto unlock;
4379         } else {
4380                 /* exchange programs, extra prog reference we got from caller
4381                  * as long as we don't fail from this point onwards.
4382                  */
4383                 old_prog = xchg(&priv->channels.params.xdp_prog, prog);
4384         }
4385
4386         if (old_prog)
4387                 bpf_prog_put(old_prog);
4388
4389         if (!was_opened && reset) /* change RQ type according to priv->xdp_prog */
4390                 mlx5e_set_rq_type(priv->mdev, &priv->channels.params);
4391
4392         if (!was_opened || reset)
4393                 goto unlock;
4394
4395         /* exchanging programs w/o reset, we update ref counts on behalf
4396          * of the channels RQs here.
4397          */
4398         for (i = 0; i < priv->channels.num; i++) {
4399                 struct mlx5e_channel *c = priv->channels.c[i];
4400                 bool xsk_open = test_bit(MLX5E_CHANNEL_STATE_XSK, c->state);
4401
4402                 clear_bit(MLX5E_RQ_STATE_ENABLED, &c->rq.state);
4403                 if (xsk_open)
4404                         clear_bit(MLX5E_RQ_STATE_ENABLED, &c->xskrq.state);
4405                 napi_synchronize(&c->napi);
4406                 /* prevent mlx5e_poll_rx_cq from accessing rq->xdp_prog */
4407
4408                 old_prog = xchg(&c->rq.xdp_prog, prog);
4409                 if (old_prog)
4410                         bpf_prog_put(old_prog);
4411
4412                 if (xsk_open) {
4413                         old_prog = xchg(&c->xskrq.xdp_prog, prog);
4414                         if (old_prog)
4415                                 bpf_prog_put(old_prog);
4416                 }
4417
4418                 set_bit(MLX5E_RQ_STATE_ENABLED, &c->rq.state);
4419                 if (xsk_open)
4420                         set_bit(MLX5E_RQ_STATE_ENABLED, &c->xskrq.state);
4421                 /* napi_schedule in case we have missed anything */
4422                 napi_schedule(&c->napi);
4423         }
4424
4425 unlock:
4426         mutex_unlock(&priv->state_lock);
4427         return err;
4428 }
4429
4430 static u32 mlx5e_xdp_query(struct net_device *dev)
4431 {
4432         struct mlx5e_priv *priv = netdev_priv(dev);
4433         const struct bpf_prog *xdp_prog;
4434         u32 prog_id = 0;
4435
4436         mutex_lock(&priv->state_lock);
4437         xdp_prog = priv->channels.params.xdp_prog;
4438         if (xdp_prog)
4439                 prog_id = xdp_prog->aux->id;
4440         mutex_unlock(&priv->state_lock);
4441
4442         return prog_id;
4443 }
4444
4445 static int mlx5e_xdp(struct net_device *dev, struct netdev_bpf *xdp)
4446 {
4447         switch (xdp->command) {
4448         case XDP_SETUP_PROG:
4449                 return mlx5e_xdp_set(dev, xdp->prog);
4450         case XDP_QUERY_PROG:
4451                 xdp->prog_id = mlx5e_xdp_query(dev);
4452                 return 0;
4453         case XDP_SETUP_XSK_UMEM:
4454                 return mlx5e_xsk_setup_umem(dev, xdp->xsk.umem,
4455                                             xdp->xsk.queue_id);
4456         default:
4457                 return -EINVAL;
4458         }
4459 }
4460
4461 #ifdef CONFIG_MLX5_ESWITCH
4462 static int mlx5e_bridge_getlink(struct sk_buff *skb, u32 pid, u32 seq,
4463                                 struct net_device *dev, u32 filter_mask,
4464                                 int nlflags)
4465 {
4466         struct mlx5e_priv *priv = netdev_priv(dev);
4467         struct mlx5_core_dev *mdev = priv->mdev;
4468         u8 mode, setting;
4469         int err;
4470
4471         err = mlx5_eswitch_get_vepa(mdev->priv.eswitch, &setting);
4472         if (err)
4473                 return err;
4474         mode = setting ? BRIDGE_MODE_VEPA : BRIDGE_MODE_VEB;
4475         return ndo_dflt_bridge_getlink(skb, pid, seq, dev,
4476                                        mode,
4477                                        0, 0, nlflags, filter_mask, NULL);
4478 }
4479
4480 static int mlx5e_bridge_setlink(struct net_device *dev, struct nlmsghdr *nlh,
4481                                 u16 flags, struct netlink_ext_ack *extack)
4482 {
4483         struct mlx5e_priv *priv = netdev_priv(dev);
4484         struct mlx5_core_dev *mdev = priv->mdev;
4485         struct nlattr *attr, *br_spec;
4486         u16 mode = BRIDGE_MODE_UNDEF;
4487         u8 setting;
4488         int rem;
4489
4490         br_spec = nlmsg_find_attr(nlh, sizeof(struct ifinfomsg), IFLA_AF_SPEC);
4491         if (!br_spec)
4492                 return -EINVAL;
4493
4494         nla_for_each_nested(attr, br_spec, rem) {
4495                 if (nla_type(attr) != IFLA_BRIDGE_MODE)
4496                         continue;
4497
4498                 if (nla_len(attr) < sizeof(mode))
4499                         return -EINVAL;
4500
4501                 mode = nla_get_u16(attr);
4502                 if (mode > BRIDGE_MODE_VEPA)
4503                         return -EINVAL;
4504
4505                 break;
4506         }
4507
4508         if (mode == BRIDGE_MODE_UNDEF)
4509                 return -EINVAL;
4510
4511         setting = (mode == BRIDGE_MODE_VEPA) ?  1 : 0;
4512         return mlx5_eswitch_set_vepa(mdev->priv.eswitch, setting);
4513 }
4514 #endif
4515
4516 const struct net_device_ops mlx5e_netdev_ops = {
4517         .ndo_open                = mlx5e_open,
4518         .ndo_stop                = mlx5e_close,
4519         .ndo_start_xmit          = mlx5e_xmit,
4520         .ndo_setup_tc            = mlx5e_setup_tc,
4521         .ndo_select_queue        = mlx5e_select_queue,
4522         .ndo_get_stats64         = mlx5e_get_stats,
4523         .ndo_set_rx_mode         = mlx5e_set_rx_mode,
4524         .ndo_set_mac_address     = mlx5e_set_mac,
4525         .ndo_vlan_rx_add_vid     = mlx5e_vlan_rx_add_vid,
4526         .ndo_vlan_rx_kill_vid    = mlx5e_vlan_rx_kill_vid,
4527         .ndo_set_features        = mlx5e_set_features,
4528         .ndo_fix_features        = mlx5e_fix_features,
4529         .ndo_change_mtu          = mlx5e_change_nic_mtu,
4530         .ndo_do_ioctl            = mlx5e_ioctl,
4531         .ndo_set_tx_maxrate      = mlx5e_set_tx_maxrate,
4532         .ndo_udp_tunnel_add      = mlx5e_add_vxlan_port,
4533         .ndo_udp_tunnel_del      = mlx5e_del_vxlan_port,
4534         .ndo_features_check      = mlx5e_features_check,
4535         .ndo_tx_timeout          = mlx5e_tx_timeout,
4536         .ndo_bpf                 = mlx5e_xdp,
4537         .ndo_xdp_xmit            = mlx5e_xdp_xmit,
4538         .ndo_xsk_async_xmit      = mlx5e_xsk_async_xmit,
4539 #ifdef CONFIG_MLX5_EN_ARFS
4540         .ndo_rx_flow_steer       = mlx5e_rx_flow_steer,
4541 #endif
4542 #ifdef CONFIG_MLX5_ESWITCH
4543         .ndo_bridge_setlink      = mlx5e_bridge_setlink,
4544         .ndo_bridge_getlink      = mlx5e_bridge_getlink,
4545
4546         /* SRIOV E-Switch NDOs */
4547         .ndo_set_vf_mac          = mlx5e_set_vf_mac,
4548         .ndo_set_vf_vlan         = mlx5e_set_vf_vlan,
4549         .ndo_set_vf_spoofchk     = mlx5e_set_vf_spoofchk,
4550         .ndo_set_vf_trust        = mlx5e_set_vf_trust,
4551         .ndo_set_vf_rate         = mlx5e_set_vf_rate,
4552         .ndo_get_vf_config       = mlx5e_get_vf_config,
4553         .ndo_set_vf_link_state   = mlx5e_set_vf_link_state,
4554         .ndo_get_vf_stats        = mlx5e_get_vf_stats,
4555 #endif
4556 };
4557
4558 static int mlx5e_check_required_hca_cap(struct mlx5_core_dev *mdev)
4559 {
4560         if (MLX5_CAP_GEN(mdev, port_type) != MLX5_CAP_PORT_TYPE_ETH)
4561                 return -EOPNOTSUPP;
4562         if (!MLX5_CAP_GEN(mdev, eth_net_offloads) ||
4563             !MLX5_CAP_GEN(mdev, nic_flow_table) ||
4564             !MLX5_CAP_ETH(mdev, csum_cap) ||
4565             !MLX5_CAP_ETH(mdev, max_lso_cap) ||
4566             !MLX5_CAP_ETH(mdev, vlan_cap) ||
4567             !MLX5_CAP_ETH(mdev, rss_ind_tbl_cap) ||
4568             MLX5_CAP_FLOWTABLE(mdev,
4569                                flow_table_properties_nic_receive.max_ft_level)
4570                                < 3) {
4571                 mlx5_core_warn(mdev,
4572                                "Not creating net device, some required device capabilities are missing\n");
4573                 return -EOPNOTSUPP;
4574         }
4575         if (!MLX5_CAP_ETH(mdev, self_lb_en_modifiable))
4576                 mlx5_core_warn(mdev, "Self loop back prevention is not supported\n");
4577         if (!MLX5_CAP_GEN(mdev, cq_moderation))
4578                 mlx5_core_warn(mdev, "CQ moderation is not supported\n");
4579
4580         return 0;
4581 }
4582
4583 void mlx5e_build_default_indir_rqt(u32 *indirection_rqt, int len,
4584                                    int num_channels)
4585 {
4586         int i;
4587
4588         for (i = 0; i < len; i++)
4589                 indirection_rqt[i] = i % num_channels;
4590 }
4591
4592 static bool slow_pci_heuristic(struct mlx5_core_dev *mdev)
4593 {
4594         u32 link_speed = 0;
4595         u32 pci_bw = 0;
4596
4597         mlx5e_port_max_linkspeed(mdev, &link_speed);
4598         pci_bw = pcie_bandwidth_available(mdev->pdev, NULL, NULL, NULL);
4599         mlx5_core_dbg_once(mdev, "Max link speed = %d, PCI BW = %d\n",
4600                            link_speed, pci_bw);
4601
4602 #define MLX5E_SLOW_PCI_RATIO (2)
4603
4604         return link_speed && pci_bw &&
4605                 link_speed > MLX5E_SLOW_PCI_RATIO * pci_bw;
4606 }
4607
4608 static struct dim_cq_moder mlx5e_get_def_tx_moderation(u8 cq_period_mode)
4609 {
4610         struct dim_cq_moder moder;
4611
4612         moder.cq_period_mode = cq_period_mode;
4613         moder.pkts = MLX5E_PARAMS_DEFAULT_TX_CQ_MODERATION_PKTS;
4614         moder.usec = MLX5E_PARAMS_DEFAULT_TX_CQ_MODERATION_USEC;
4615         if (cq_period_mode == MLX5_CQ_PERIOD_MODE_START_FROM_CQE)
4616                 moder.usec = MLX5E_PARAMS_DEFAULT_TX_CQ_MODERATION_USEC_FROM_CQE;
4617
4618         return moder;
4619 }
4620
4621 static struct dim_cq_moder mlx5e_get_def_rx_moderation(u8 cq_period_mode)
4622 {
4623         struct dim_cq_moder moder;
4624
4625         moder.cq_period_mode = cq_period_mode;
4626         moder.pkts = MLX5E_PARAMS_DEFAULT_RX_CQ_MODERATION_PKTS;
4627         moder.usec = MLX5E_PARAMS_DEFAULT_RX_CQ_MODERATION_USEC;
4628         if (cq_period_mode == MLX5_CQ_PERIOD_MODE_START_FROM_CQE)
4629                 moder.usec = MLX5E_PARAMS_DEFAULT_RX_CQ_MODERATION_USEC_FROM_CQE;
4630
4631         return moder;
4632 }
4633
4634 static u8 mlx5_to_net_dim_cq_period_mode(u8 cq_period_mode)
4635 {
4636         return cq_period_mode == MLX5_CQ_PERIOD_MODE_START_FROM_CQE ?
4637                 DIM_CQ_PERIOD_MODE_START_FROM_CQE :
4638                 DIM_CQ_PERIOD_MODE_START_FROM_EQE;
4639 }
4640
4641 void mlx5e_set_tx_cq_mode_params(struct mlx5e_params *params, u8 cq_period_mode)
4642 {
4643         if (params->tx_dim_enabled) {
4644                 u8 dim_period_mode = mlx5_to_net_dim_cq_period_mode(cq_period_mode);
4645
4646                 params->tx_cq_moderation = net_dim_get_def_tx_moderation(dim_period_mode);
4647         } else {
4648                 params->tx_cq_moderation = mlx5e_get_def_tx_moderation(cq_period_mode);
4649         }
4650
4651         MLX5E_SET_PFLAG(params, MLX5E_PFLAG_TX_CQE_BASED_MODER,
4652                         params->tx_cq_moderation.cq_period_mode ==
4653                                 MLX5_CQ_PERIOD_MODE_START_FROM_CQE);
4654 }
4655
4656 void mlx5e_set_rx_cq_mode_params(struct mlx5e_params *params, u8 cq_period_mode)
4657 {
4658         if (params->rx_dim_enabled) {
4659                 u8 dim_period_mode = mlx5_to_net_dim_cq_period_mode(cq_period_mode);
4660
4661                 params->rx_cq_moderation = net_dim_get_def_rx_moderation(dim_period_mode);
4662         } else {
4663                 params->rx_cq_moderation = mlx5e_get_def_rx_moderation(cq_period_mode);
4664         }
4665
4666         MLX5E_SET_PFLAG(params, MLX5E_PFLAG_RX_CQE_BASED_MODER,
4667                         params->rx_cq_moderation.cq_period_mode ==
4668                                 MLX5_CQ_PERIOD_MODE_START_FROM_CQE);
4669 }
4670
4671 static u32 mlx5e_choose_lro_timeout(struct mlx5_core_dev *mdev, u32 wanted_timeout)
4672 {
4673         int i;
4674
4675         /* The supported periods are organized in ascending order */
4676         for (i = 0; i < MLX5E_LRO_TIMEOUT_ARR_SIZE - 1; i++)
4677                 if (MLX5_CAP_ETH(mdev, lro_timer_supported_periods[i]) >= wanted_timeout)
4678                         break;
4679
4680         return MLX5_CAP_ETH(mdev, lro_timer_supported_periods[i]);
4681 }
4682
4683 void mlx5e_build_rq_params(struct mlx5_core_dev *mdev,
4684                            struct mlx5e_params *params)
4685 {
4686         /* Prefer Striding RQ, unless any of the following holds:
4687          * - Striding RQ configuration is not possible/supported.
4688          * - Slow PCI heuristic.
4689          * - Legacy RQ would use linear SKB while Striding RQ would use non-linear.
4690          *
4691          * No XSK params: checking the availability of striding RQ in general.
4692          */
4693         if (!slow_pci_heuristic(mdev) &&
4694             mlx5e_striding_rq_possible(mdev, params) &&
4695             (mlx5e_rx_mpwqe_is_linear_skb(mdev, params, NULL) ||
4696              !mlx5e_rx_is_linear_skb(params, NULL)))
4697                 MLX5E_SET_PFLAG(params, MLX5E_PFLAG_RX_STRIDING_RQ, true);
4698         mlx5e_set_rq_type(mdev, params);
4699         mlx5e_init_rq_type_params(mdev, params);
4700 }
4701
4702 void mlx5e_build_rss_params(struct mlx5e_rss_params *rss_params,
4703                             u16 num_channels)
4704 {
4705         enum mlx5e_traffic_types tt;
4706
4707         rss_params->hfunc = ETH_RSS_HASH_TOP;
4708         netdev_rss_key_fill(rss_params->toeplitz_hash_key,
4709                             sizeof(rss_params->toeplitz_hash_key));
4710         mlx5e_build_default_indir_rqt(rss_params->indirection_rqt,
4711                                       MLX5E_INDIR_RQT_SIZE, num_channels);
4712         for (tt = 0; tt < MLX5E_NUM_INDIR_TIRS; tt++)
4713                 rss_params->rx_hash_fields[tt] =
4714                         tirc_default_config[tt].rx_hash_fields;
4715 }
4716
4717 void mlx5e_build_nic_params(struct mlx5_core_dev *mdev,
4718                             struct mlx5e_xsk *xsk,
4719                             struct mlx5e_rss_params *rss_params,
4720                             struct mlx5e_params *params,
4721                             u16 max_channels, u16 mtu)
4722 {
4723         u8 rx_cq_period_mode;
4724
4725         params->sw_mtu = mtu;
4726         params->hard_mtu = MLX5E_ETH_HARD_MTU;
4727         params->num_channels = max_channels;
4728         params->num_tc       = 1;
4729
4730         /* SQ */
4731         params->log_sq_size = is_kdump_kernel() ?
4732                 MLX5E_PARAMS_MINIMUM_LOG_SQ_SIZE :
4733                 MLX5E_PARAMS_DEFAULT_LOG_SQ_SIZE;
4734
4735         /* XDP SQ */
4736         MLX5E_SET_PFLAG(params, MLX5E_PFLAG_XDP_TX_MPWQE,
4737                         MLX5_CAP_ETH(mdev, enhanced_multi_pkt_send_wqe));
4738
4739         /* set CQE compression */
4740         params->rx_cqe_compress_def = false;
4741         if (MLX5_CAP_GEN(mdev, cqe_compression) &&
4742             MLX5_CAP_GEN(mdev, vport_group_manager))
4743                 params->rx_cqe_compress_def = slow_pci_heuristic(mdev);
4744
4745         MLX5E_SET_PFLAG(params, MLX5E_PFLAG_RX_CQE_COMPRESS, params->rx_cqe_compress_def);
4746         MLX5E_SET_PFLAG(params, MLX5E_PFLAG_RX_NO_CSUM_COMPLETE, false);
4747
4748         /* RQ */
4749         mlx5e_build_rq_params(mdev, params);
4750
4751         /* HW LRO */
4752
4753         /* TODO: && MLX5_CAP_ETH(mdev, lro_cap) */
4754         if (params->rq_wq_type == MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ) {
4755                 /* No XSK params: checking the availability of striding RQ in general. */
4756                 if (!mlx5e_rx_mpwqe_is_linear_skb(mdev, params, NULL))
4757                         params->lro_en = !slow_pci_heuristic(mdev);
4758         }
4759         params->lro_timeout = mlx5e_choose_lro_timeout(mdev, MLX5E_DEFAULT_LRO_TIMEOUT);
4760
4761         /* CQ moderation params */
4762         rx_cq_period_mode = MLX5_CAP_GEN(mdev, cq_period_start_from_cqe) ?
4763                         MLX5_CQ_PERIOD_MODE_START_FROM_CQE :
4764                         MLX5_CQ_PERIOD_MODE_START_FROM_EQE;
4765         params->rx_dim_enabled = MLX5_CAP_GEN(mdev, cq_moderation);
4766         params->tx_dim_enabled = MLX5_CAP_GEN(mdev, cq_moderation);
4767         mlx5e_set_rx_cq_mode_params(params, rx_cq_period_mode);
4768         mlx5e_set_tx_cq_mode_params(params, MLX5_CQ_PERIOD_MODE_START_FROM_EQE);
4769
4770         /* TX inline */
4771         params->tx_min_inline_mode = mlx5e_params_calculate_tx_min_inline(mdev);
4772
4773         /* RSS */
4774         mlx5e_build_rss_params(rss_params, params->num_channels);
4775         params->tunneled_offload_en =
4776                 mlx5e_tunnel_inner_ft_supported(mdev);
4777
4778         /* AF_XDP */
4779         params->xsk = xsk;
4780 }
4781
4782 static void mlx5e_set_netdev_dev_addr(struct net_device *netdev)
4783 {
4784         struct mlx5e_priv *priv = netdev_priv(netdev);
4785
4786         mlx5_query_mac_address(priv->mdev, netdev->dev_addr);
4787         if (is_zero_ether_addr(netdev->dev_addr) &&
4788             !MLX5_CAP_GEN(priv->mdev, vport_group_manager)) {
4789                 eth_hw_addr_random(netdev);
4790                 mlx5_core_info(priv->mdev, "Assigned random MAC address %pM\n", netdev->dev_addr);
4791         }
4792 }
4793
4794 static void mlx5e_build_nic_netdev(struct net_device *netdev)
4795 {
4796         struct mlx5e_priv *priv = netdev_priv(netdev);
4797         struct mlx5_core_dev *mdev = priv->mdev;
4798         bool fcs_supported;
4799         bool fcs_enabled;
4800
4801         SET_NETDEV_DEV(netdev, mdev->device);
4802
4803         netdev->netdev_ops = &mlx5e_netdev_ops;
4804
4805 #ifdef CONFIG_MLX5_CORE_EN_DCB
4806         if (MLX5_CAP_GEN(mdev, vport_group_manager) && MLX5_CAP_GEN(mdev, qos))
4807                 netdev->dcbnl_ops = &mlx5e_dcbnl_ops;
4808 #endif
4809
4810         netdev->watchdog_timeo    = 15 * HZ;
4811
4812         netdev->ethtool_ops       = &mlx5e_ethtool_ops;
4813
4814         netdev->vlan_features    |= NETIF_F_SG;
4815         netdev->vlan_features    |= NETIF_F_HW_CSUM;
4816         netdev->vlan_features    |= NETIF_F_GRO;
4817         netdev->vlan_features    |= NETIF_F_TSO;
4818         netdev->vlan_features    |= NETIF_F_TSO6;
4819         netdev->vlan_features    |= NETIF_F_RXCSUM;
4820         netdev->vlan_features    |= NETIF_F_RXHASH;
4821
4822         netdev->mpls_features    |= NETIF_F_SG;
4823         netdev->mpls_features    |= NETIF_F_HW_CSUM;
4824         netdev->mpls_features    |= NETIF_F_TSO;
4825         netdev->mpls_features    |= NETIF_F_TSO6;
4826
4827         netdev->hw_enc_features  |= NETIF_F_HW_VLAN_CTAG_TX;
4828         netdev->hw_enc_features  |= NETIF_F_HW_VLAN_CTAG_RX;
4829
4830         if (!!MLX5_CAP_ETH(mdev, lro_cap) &&
4831             mlx5e_check_fragmented_striding_rq_cap(mdev))
4832                 netdev->vlan_features    |= NETIF_F_LRO;
4833
4834         netdev->hw_features       = netdev->vlan_features;
4835         netdev->hw_features      |= NETIF_F_HW_VLAN_CTAG_TX;
4836         netdev->hw_features      |= NETIF_F_HW_VLAN_CTAG_RX;
4837         netdev->hw_features      |= NETIF_F_HW_VLAN_CTAG_FILTER;
4838         netdev->hw_features      |= NETIF_F_HW_VLAN_STAG_TX;
4839
4840         if (mlx5_vxlan_allowed(mdev->vxlan) || mlx5_geneve_tx_allowed(mdev) ||
4841             MLX5_CAP_ETH(mdev, tunnel_stateless_gre)) {
4842                 netdev->hw_enc_features |= NETIF_F_HW_CSUM;
4843                 netdev->hw_enc_features |= NETIF_F_TSO;
4844                 netdev->hw_enc_features |= NETIF_F_TSO6;
4845                 netdev->hw_enc_features |= NETIF_F_GSO_PARTIAL;
4846         }
4847
4848         if (mlx5_vxlan_allowed(mdev->vxlan) || mlx5_geneve_tx_allowed(mdev)) {
4849                 netdev->hw_features     |= NETIF_F_GSO_UDP_TUNNEL |
4850                                            NETIF_F_GSO_UDP_TUNNEL_CSUM;
4851                 netdev->hw_enc_features |= NETIF_F_GSO_UDP_TUNNEL |
4852                                            NETIF_F_GSO_UDP_TUNNEL_CSUM;
4853                 netdev->gso_partial_features = NETIF_F_GSO_UDP_TUNNEL_CSUM;
4854         }
4855
4856         if (MLX5_CAP_ETH(mdev, tunnel_stateless_gre)) {
4857                 netdev->hw_features     |= NETIF_F_GSO_GRE |
4858                                            NETIF_F_GSO_GRE_CSUM;
4859                 netdev->hw_enc_features |= NETIF_F_GSO_GRE |
4860                                            NETIF_F_GSO_GRE_CSUM;
4861                 netdev->gso_partial_features |= NETIF_F_GSO_GRE |
4862                                                 NETIF_F_GSO_GRE_CSUM;
4863         }
4864
4865         netdev->hw_features                      |= NETIF_F_GSO_PARTIAL;
4866         netdev->gso_partial_features             |= NETIF_F_GSO_UDP_L4;
4867         netdev->hw_features                      |= NETIF_F_GSO_UDP_L4;
4868         netdev->features                         |= NETIF_F_GSO_UDP_L4;
4869
4870         mlx5_query_port_fcs(mdev, &fcs_supported, &fcs_enabled);
4871
4872         if (fcs_supported)
4873                 netdev->hw_features |= NETIF_F_RXALL;
4874
4875         if (MLX5_CAP_ETH(mdev, scatter_fcs))
4876                 netdev->hw_features |= NETIF_F_RXFCS;
4877
4878         netdev->features          = netdev->hw_features;
4879         if (!priv->channels.params.lro_en)
4880                 netdev->features  &= ~NETIF_F_LRO;
4881
4882         if (fcs_enabled)
4883                 netdev->features  &= ~NETIF_F_RXALL;
4884
4885         if (!priv->channels.params.scatter_fcs_en)
4886                 netdev->features  &= ~NETIF_F_RXFCS;
4887
4888         /* prefere CQE compression over rxhash */
4889         if (MLX5E_GET_PFLAG(&priv->channels.params, MLX5E_PFLAG_RX_CQE_COMPRESS))
4890                 netdev->features &= ~NETIF_F_RXHASH;
4891
4892 #define FT_CAP(f) MLX5_CAP_FLOWTABLE(mdev, flow_table_properties_nic_receive.f)
4893         if (FT_CAP(flow_modify_en) &&
4894             FT_CAP(modify_root) &&
4895             FT_CAP(identified_miss_table_mode) &&
4896             FT_CAP(flow_table_modify)) {
4897 #ifdef CONFIG_MLX5_ESWITCH
4898                 netdev->hw_features      |= NETIF_F_HW_TC;
4899 #endif
4900 #ifdef CONFIG_MLX5_EN_ARFS
4901                 netdev->hw_features      |= NETIF_F_NTUPLE;
4902 #endif
4903         }
4904
4905         netdev->features         |= NETIF_F_HIGHDMA;
4906         netdev->features         |= NETIF_F_HW_VLAN_STAG_FILTER;
4907
4908         netdev->priv_flags       |= IFF_UNICAST_FLT;
4909
4910         mlx5e_set_netdev_dev_addr(netdev);
4911         mlx5e_ipsec_build_netdev(priv);
4912         mlx5e_tls_build_netdev(priv);
4913 }
4914
4915 void mlx5e_create_q_counters(struct mlx5e_priv *priv)
4916 {
4917         struct mlx5_core_dev *mdev = priv->mdev;
4918         int err;
4919
4920         err = mlx5_core_alloc_q_counter(mdev, &priv->q_counter);
4921         if (err) {
4922                 mlx5_core_warn(mdev, "alloc queue counter failed, %d\n", err);
4923                 priv->q_counter = 0;
4924         }
4925
4926         err = mlx5_core_alloc_q_counter(mdev, &priv->drop_rq_q_counter);
4927         if (err) {
4928                 mlx5_core_warn(mdev, "alloc drop RQ counter failed, %d\n", err);
4929                 priv->drop_rq_q_counter = 0;
4930         }
4931 }
4932
4933 void mlx5e_destroy_q_counters(struct mlx5e_priv *priv)
4934 {
4935         if (priv->q_counter)
4936                 mlx5_core_dealloc_q_counter(priv->mdev, priv->q_counter);
4937
4938         if (priv->drop_rq_q_counter)
4939                 mlx5_core_dealloc_q_counter(priv->mdev, priv->drop_rq_q_counter);
4940 }
4941
4942 static int mlx5e_nic_init(struct mlx5_core_dev *mdev,
4943                           struct net_device *netdev,
4944                           const struct mlx5e_profile *profile,
4945                           void *ppriv)
4946 {
4947         struct mlx5e_priv *priv = netdev_priv(netdev);
4948         struct mlx5e_rss_params *rss = &priv->rss_params;
4949         int err;
4950
4951         err = mlx5e_netdev_init(netdev, priv, mdev, profile, ppriv);
4952         if (err)
4953                 return err;
4954
4955         mlx5e_build_nic_params(mdev, &priv->xsk, rss, &priv->channels.params,
4956                                priv->max_nch, netdev->mtu);
4957
4958         mlx5e_timestamp_init(priv);
4959
4960         err = mlx5e_ipsec_init(priv);
4961         if (err)
4962                 mlx5_core_err(mdev, "IPSec initialization failed, %d\n", err);
4963         err = mlx5e_tls_init(priv);
4964         if (err)
4965                 mlx5_core_err(mdev, "TLS initialization failed, %d\n", err);
4966         mlx5e_build_nic_netdev(netdev);
4967         mlx5e_build_tc2txq_maps(priv);
4968
4969         return 0;
4970 }
4971
4972 static void mlx5e_nic_cleanup(struct mlx5e_priv *priv)
4973 {
4974         mlx5e_tls_cleanup(priv);
4975         mlx5e_ipsec_cleanup(priv);
4976         mlx5e_netdev_cleanup(priv->netdev, priv);
4977 }
4978
4979 static int mlx5e_init_nic_rx(struct mlx5e_priv *priv)
4980 {
4981         struct mlx5_core_dev *mdev = priv->mdev;
4982         int err;
4983
4984         mlx5e_create_q_counters(priv);
4985
4986         err = mlx5e_open_drop_rq(priv, &priv->drop_rq);
4987         if (err) {
4988                 mlx5_core_err(mdev, "open drop rq failed, %d\n", err);
4989                 goto err_destroy_q_counters;
4990         }
4991
4992         err = mlx5e_create_indirect_rqt(priv);
4993         if (err)
4994                 goto err_close_drop_rq;
4995
4996         err = mlx5e_create_direct_rqts(priv, priv->direct_tir);
4997         if (err)
4998                 goto err_destroy_indirect_rqts;
4999
5000         err = mlx5e_create_indirect_tirs(priv, true);
5001         if (err)
5002                 goto err_destroy_direct_rqts;
5003
5004         err = mlx5e_create_direct_tirs(priv, priv->direct_tir);
5005         if (err)
5006                 goto err_destroy_indirect_tirs;
5007
5008         err = mlx5e_create_direct_rqts(priv, priv->xsk_tir);
5009         if (unlikely(err))
5010                 goto err_destroy_direct_tirs;
5011
5012         err = mlx5e_create_direct_tirs(priv, priv->xsk_tir);
5013         if (unlikely(err))
5014                 goto err_destroy_xsk_rqts;
5015
5016         err = mlx5e_create_flow_steering(priv);
5017         if (err) {
5018                 mlx5_core_warn(mdev, "create flow steering failed, %d\n", err);
5019                 goto err_destroy_xsk_tirs;
5020         }
5021
5022         err = mlx5e_tc_nic_init(priv);
5023         if (err)
5024                 goto err_destroy_flow_steering;
5025
5026         return 0;
5027
5028 err_destroy_flow_steering:
5029         mlx5e_destroy_flow_steering(priv);
5030 err_destroy_xsk_tirs:
5031         mlx5e_destroy_direct_tirs(priv, priv->xsk_tir);
5032 err_destroy_xsk_rqts:
5033         mlx5e_destroy_direct_rqts(priv, priv->xsk_tir);
5034 err_destroy_direct_tirs:
5035         mlx5e_destroy_direct_tirs(priv, priv->direct_tir);
5036 err_destroy_indirect_tirs:
5037         mlx5e_destroy_indirect_tirs(priv, true);
5038 err_destroy_direct_rqts:
5039         mlx5e_destroy_direct_rqts(priv, priv->direct_tir);
5040 err_destroy_indirect_rqts:
5041         mlx5e_destroy_rqt(priv, &priv->indir_rqt);
5042 err_close_drop_rq:
5043         mlx5e_close_drop_rq(&priv->drop_rq);
5044 err_destroy_q_counters:
5045         mlx5e_destroy_q_counters(priv);
5046         return err;
5047 }
5048
5049 static void mlx5e_cleanup_nic_rx(struct mlx5e_priv *priv)
5050 {
5051         mlx5e_tc_nic_cleanup(priv);
5052         mlx5e_destroy_flow_steering(priv);
5053         mlx5e_destroy_direct_tirs(priv, priv->xsk_tir);
5054         mlx5e_destroy_direct_rqts(priv, priv->xsk_tir);
5055         mlx5e_destroy_direct_tirs(priv, priv->direct_tir);
5056         mlx5e_destroy_indirect_tirs(priv, true);
5057         mlx5e_destroy_direct_rqts(priv, priv->direct_tir);
5058         mlx5e_destroy_rqt(priv, &priv->indir_rqt);
5059         mlx5e_close_drop_rq(&priv->drop_rq);
5060         mlx5e_destroy_q_counters(priv);
5061 }
5062
5063 static int mlx5e_init_nic_tx(struct mlx5e_priv *priv)
5064 {
5065         int err;
5066
5067         err = mlx5e_create_tises(priv);
5068         if (err) {
5069                 mlx5_core_warn(priv->mdev, "create tises failed, %d\n", err);
5070                 return err;
5071         }
5072
5073 #ifdef CONFIG_MLX5_CORE_EN_DCB
5074         mlx5e_dcbnl_initialize(priv);
5075 #endif
5076         mlx5e_tx_reporter_create(priv);
5077         return 0;
5078 }
5079
5080 static void mlx5e_nic_enable(struct mlx5e_priv *priv)
5081 {
5082         struct net_device *netdev = priv->netdev;
5083         struct mlx5_core_dev *mdev = priv->mdev;
5084
5085         mlx5e_init_l2_addr(priv);
5086
5087         /* Marking the link as currently not needed by the Driver */
5088         if (!netif_running(netdev))
5089                 mlx5_set_port_admin_status(mdev, MLX5_PORT_DOWN);
5090
5091         mlx5e_set_netdev_mtu_boundaries(priv);
5092         mlx5e_set_dev_port_mtu(priv);
5093
5094         mlx5_lag_add(mdev, netdev);
5095
5096         mlx5e_enable_async_events(priv);
5097         if (mlx5e_monitor_counter_supported(priv))
5098                 mlx5e_monitor_counter_init(priv);
5099
5100         if (netdev->reg_state != NETREG_REGISTERED)
5101                 return;
5102 #ifdef CONFIG_MLX5_CORE_EN_DCB
5103         mlx5e_dcbnl_init_app(priv);
5104 #endif
5105
5106         queue_work(priv->wq, &priv->set_rx_mode_work);
5107
5108         rtnl_lock();
5109         if (netif_running(netdev))
5110                 mlx5e_open(netdev);
5111         netif_device_attach(netdev);
5112         rtnl_unlock();
5113 }
5114
5115 static void mlx5e_nic_disable(struct mlx5e_priv *priv)
5116 {
5117         struct mlx5_core_dev *mdev = priv->mdev;
5118
5119 #ifdef CONFIG_MLX5_CORE_EN_DCB
5120         if (priv->netdev->reg_state == NETREG_REGISTERED)
5121                 mlx5e_dcbnl_delete_app(priv);
5122 #endif
5123
5124         rtnl_lock();
5125         if (netif_running(priv->netdev))
5126                 mlx5e_close(priv->netdev);
5127         netif_device_detach(priv->netdev);
5128         rtnl_unlock();
5129
5130         queue_work(priv->wq, &priv->set_rx_mode_work);
5131
5132         if (mlx5e_monitor_counter_supported(priv))
5133                 mlx5e_monitor_counter_cleanup(priv);
5134
5135         mlx5e_disable_async_events(priv);
5136         mlx5_lag_remove(mdev);
5137 }
5138
5139 int mlx5e_update_nic_rx(struct mlx5e_priv *priv)
5140 {
5141         return mlx5e_refresh_tirs(priv, false);
5142 }
5143
5144 static const struct mlx5e_profile mlx5e_nic_profile = {
5145         .init              = mlx5e_nic_init,
5146         .cleanup           = mlx5e_nic_cleanup,
5147         .init_rx           = mlx5e_init_nic_rx,
5148         .cleanup_rx        = mlx5e_cleanup_nic_rx,
5149         .init_tx           = mlx5e_init_nic_tx,
5150         .cleanup_tx        = mlx5e_cleanup_nic_tx,
5151         .enable            = mlx5e_nic_enable,
5152         .disable           = mlx5e_nic_disable,
5153         .update_rx         = mlx5e_update_nic_rx,
5154         .update_stats      = mlx5e_update_ndo_stats,
5155         .update_carrier    = mlx5e_update_carrier,
5156         .rx_handlers.handle_rx_cqe       = mlx5e_handle_rx_cqe,
5157         .rx_handlers.handle_rx_cqe_mpwqe = mlx5e_handle_rx_cqe_mpwrq,
5158         .max_tc            = MLX5E_MAX_NUM_TC,
5159         .rq_groups         = MLX5E_NUM_RQ_GROUPS(XSK),
5160 };
5161
5162 /* mlx5e generic netdev management API (move to en_common.c) */
5163
5164 /* mlx5e_netdev_init/cleanup must be called from profile->init/cleanup callbacks */
5165 int mlx5e_netdev_init(struct net_device *netdev,
5166                       struct mlx5e_priv *priv,
5167                       struct mlx5_core_dev *mdev,
5168                       const struct mlx5e_profile *profile,
5169                       void *ppriv)
5170 {
5171         /* priv init */
5172         priv->mdev        = mdev;
5173         priv->netdev      = netdev;
5174         priv->profile     = profile;
5175         priv->ppriv       = ppriv;
5176         priv->msglevel    = MLX5E_MSG_LEVEL;
5177         priv->max_nch     = netdev->num_rx_queues / max_t(u8, profile->rq_groups, 1);
5178         priv->max_opened_tc = 1;
5179
5180         mutex_init(&priv->state_lock);
5181         INIT_WORK(&priv->update_carrier_work, mlx5e_update_carrier_work);
5182         INIT_WORK(&priv->set_rx_mode_work, mlx5e_set_rx_mode_work);
5183         INIT_WORK(&priv->tx_timeout_work, mlx5e_tx_timeout_work);
5184         INIT_WORK(&priv->update_stats_work, mlx5e_update_stats_work);
5185
5186         priv->wq = create_singlethread_workqueue("mlx5e");
5187         if (!priv->wq)
5188                 return -ENOMEM;
5189
5190         /* netdev init */
5191         netif_carrier_off(netdev);
5192
5193 #ifdef CONFIG_MLX5_EN_ARFS
5194         netdev->rx_cpu_rmap =  mlx5_eq_table_get_rmap(mdev);
5195 #endif
5196
5197         return 0;
5198 }
5199
5200 void mlx5e_netdev_cleanup(struct net_device *netdev, struct mlx5e_priv *priv)
5201 {
5202         destroy_workqueue(priv->wq);
5203 }
5204
5205 struct net_device *mlx5e_create_netdev(struct mlx5_core_dev *mdev,
5206                                        const struct mlx5e_profile *profile,
5207                                        int nch,
5208                                        void *ppriv)
5209 {
5210         struct net_device *netdev;
5211         int err;
5212
5213         netdev = alloc_etherdev_mqs(sizeof(struct mlx5e_priv),
5214                                     nch * profile->max_tc,
5215                                     nch * profile->rq_groups);
5216         if (!netdev) {
5217                 mlx5_core_err(mdev, "alloc_etherdev_mqs() failed\n");
5218                 return NULL;
5219         }
5220
5221         err = profile->init(mdev, netdev, profile, ppriv);
5222         if (err) {
5223                 mlx5_core_err(mdev, "failed to init mlx5e profile %d\n", err);
5224                 goto err_free_netdev;
5225         }
5226
5227         return netdev;
5228
5229 err_free_netdev:
5230         free_netdev(netdev);
5231
5232         return NULL;
5233 }
5234
5235 int mlx5e_attach_netdev(struct mlx5e_priv *priv)
5236 {
5237         const struct mlx5e_profile *profile;
5238         int max_nch;
5239         int err;
5240
5241         profile = priv->profile;
5242         clear_bit(MLX5E_STATE_DESTROYING, &priv->state);
5243
5244         /* max number of channels may have changed */
5245         max_nch = mlx5e_get_max_num_channels(priv->mdev);
5246         if (priv->channels.params.num_channels > max_nch) {
5247                 mlx5_core_warn(priv->mdev, "MLX5E: Reducing number of channels to %d\n", max_nch);
5248                 priv->channels.params.num_channels = max_nch;
5249                 mlx5e_build_default_indir_rqt(priv->rss_params.indirection_rqt,
5250                                               MLX5E_INDIR_RQT_SIZE, max_nch);
5251         }
5252
5253         err = profile->init_tx(priv);
5254         if (err)
5255                 goto out;
5256
5257         err = profile->init_rx(priv);
5258         if (err)
5259                 goto err_cleanup_tx;
5260
5261         if (profile->enable)
5262                 profile->enable(priv);
5263
5264         return 0;
5265
5266 err_cleanup_tx:
5267         profile->cleanup_tx(priv);
5268
5269 out:
5270         return err;
5271 }
5272
5273 void mlx5e_detach_netdev(struct mlx5e_priv *priv)
5274 {
5275         const struct mlx5e_profile *profile = priv->profile;
5276
5277         set_bit(MLX5E_STATE_DESTROYING, &priv->state);
5278
5279         if (profile->disable)
5280                 profile->disable(priv);
5281         flush_workqueue(priv->wq);
5282
5283         profile->cleanup_rx(priv);
5284         profile->cleanup_tx(priv);
5285         cancel_work_sync(&priv->update_stats_work);
5286 }
5287
5288 void mlx5e_destroy_netdev(struct mlx5e_priv *priv)
5289 {
5290         const struct mlx5e_profile *profile = priv->profile;
5291         struct net_device *netdev = priv->netdev;
5292
5293         if (profile->cleanup)
5294                 profile->cleanup(priv);
5295         free_netdev(netdev);
5296 }
5297
5298 /* mlx5e_attach and mlx5e_detach scope should be only creating/destroying
5299  * hardware contexts and to connect it to the current netdev.
5300  */
5301 static int mlx5e_attach(struct mlx5_core_dev *mdev, void *vpriv)
5302 {
5303         struct mlx5e_priv *priv = vpriv;
5304         struct net_device *netdev = priv->netdev;
5305         int err;
5306
5307         if (netif_device_present(netdev))
5308                 return 0;
5309
5310         err = mlx5e_create_mdev_resources(mdev);
5311         if (err)
5312                 return err;
5313
5314         err = mlx5e_attach_netdev(priv);
5315         if (err) {
5316                 mlx5e_destroy_mdev_resources(mdev);
5317                 return err;
5318         }
5319
5320         return 0;
5321 }
5322
5323 static void mlx5e_detach(struct mlx5_core_dev *mdev, void *vpriv)
5324 {
5325         struct mlx5e_priv *priv = vpriv;
5326         struct net_device *netdev = priv->netdev;
5327
5328 #ifdef CONFIG_MLX5_ESWITCH
5329         if (MLX5_ESWITCH_MANAGER(mdev) && vpriv == mdev)
5330                 return;
5331 #endif
5332
5333         if (!netif_device_present(netdev))
5334                 return;
5335
5336         mlx5e_detach_netdev(priv);
5337         mlx5e_destroy_mdev_resources(mdev);
5338 }
5339
5340 static void *mlx5e_add(struct mlx5_core_dev *mdev)
5341 {
5342         struct net_device *netdev;
5343         void *priv;
5344         int err;
5345         int nch;
5346
5347         err = mlx5e_check_required_hca_cap(mdev);
5348         if (err)
5349                 return NULL;
5350
5351 #ifdef CONFIG_MLX5_ESWITCH
5352         if (MLX5_ESWITCH_MANAGER(mdev) &&
5353             mlx5_eswitch_mode(mdev->priv.eswitch) == MLX5_ESWITCH_OFFLOADS) {
5354                 mlx5e_rep_register_vport_reps(mdev);
5355                 return mdev;
5356         }
5357 #endif
5358
5359         nch = mlx5e_get_max_num_channels(mdev);
5360         netdev = mlx5e_create_netdev(mdev, &mlx5e_nic_profile, nch, NULL);
5361         if (!netdev) {
5362                 mlx5_core_err(mdev, "mlx5e_create_netdev failed\n");
5363                 return NULL;
5364         }
5365
5366         priv = netdev_priv(netdev);
5367
5368         err = mlx5e_attach(mdev, priv);
5369         if (err) {
5370                 mlx5_core_err(mdev, "mlx5e_attach failed, %d\n", err);
5371                 goto err_destroy_netdev;
5372         }
5373
5374         err = register_netdev(netdev);
5375         if (err) {
5376                 mlx5_core_err(mdev, "register_netdev failed, %d\n", err);
5377                 goto err_detach;
5378         }
5379
5380 #ifdef CONFIG_MLX5_CORE_EN_DCB
5381         mlx5e_dcbnl_init_app(priv);
5382 #endif
5383         return priv;
5384
5385 err_detach:
5386         mlx5e_detach(mdev, priv);
5387 err_destroy_netdev:
5388         mlx5e_destroy_netdev(priv);
5389         return NULL;
5390 }
5391
5392 static void mlx5e_remove(struct mlx5_core_dev *mdev, void *vpriv)
5393 {
5394         struct mlx5e_priv *priv;
5395
5396 #ifdef CONFIG_MLX5_ESWITCH
5397         if (MLX5_ESWITCH_MANAGER(mdev) && vpriv == mdev) {
5398                 mlx5e_rep_unregister_vport_reps(mdev);
5399                 return;
5400         }
5401 #endif
5402         priv = vpriv;
5403 #ifdef CONFIG_MLX5_CORE_EN_DCB
5404         mlx5e_dcbnl_delete_app(priv);
5405 #endif
5406         unregister_netdev(priv->netdev);
5407         mlx5e_detach(mdev, vpriv);
5408         mlx5e_destroy_netdev(priv);
5409 }
5410
5411 static struct mlx5_interface mlx5e_interface = {
5412         .add       = mlx5e_add,
5413         .remove    = mlx5e_remove,
5414         .attach    = mlx5e_attach,
5415         .detach    = mlx5e_detach,
5416         .protocol  = MLX5_INTERFACE_PROTOCOL_ETH,
5417 };
5418
5419 void mlx5e_init(void)
5420 {
5421         mlx5e_ipsec_build_inverse_table();
5422         mlx5e_build_ptys2ethtool_map();
5423         mlx5_register_interface(&mlx5e_interface);
5424 }
5425
5426 void mlx5e_cleanup(void)
5427 {
5428         mlx5_unregister_interface(&mlx5e_interface);
5429 }