2 * Copyright (c) 2015-2016, Mellanox Technologies. All rights reserved.
4 * This software is available to you under a choice of one of two
5 * licenses. You may choose to be licensed under the terms of the GNU
6 * General Public License (GPL) Version 2, available from the file
7 * COPYING in the main directory of this source tree, or the
8 * OpenIB.org BSD license below:
10 * Redistribution and use in source and binary forms, with or
11 * without modification, are permitted provided that the following
14 * - Redistributions of source code must retain the above
15 * copyright notice, this list of conditions and the following
18 * - Redistributions in binary form must reproduce the above
19 * copyright notice, this list of conditions and the following
20 * disclaimer in the documentation and/or other materials
21 * provided with the distribution.
23 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
24 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
25 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
26 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
27 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
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29 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
33 #include <net/tc_act/tc_gact.h>
34 #include <net/pkt_cls.h>
35 #include <linux/mlx5/fs.h>
36 #include <net/vxlan.h>
37 #include <linux/bpf.h>
43 struct mlx5e_rq_param {
44 u32 rqc[MLX5_ST_SZ_DW(rqc)];
45 struct mlx5_wq_param wq;
49 struct mlx5e_sq_param {
50 u32 sqc[MLX5_ST_SZ_DW(sqc)];
51 struct mlx5_wq_param wq;
54 enum mlx5e_sq_type type;
57 struct mlx5e_cq_param {
58 u32 cqc[MLX5_ST_SZ_DW(cqc)];
59 struct mlx5_wq_param wq;
64 struct mlx5e_channel_param {
65 struct mlx5e_rq_param rq;
66 struct mlx5e_sq_param sq;
67 struct mlx5e_sq_param xdp_sq;
68 struct mlx5e_sq_param icosq;
69 struct mlx5e_cq_param rx_cq;
70 struct mlx5e_cq_param tx_cq;
71 struct mlx5e_cq_param icosq_cq;
74 static bool mlx5e_check_fragmented_striding_rq_cap(struct mlx5_core_dev *mdev)
76 return MLX5_CAP_GEN(mdev, striding_rq) &&
77 MLX5_CAP_GEN(mdev, umr_ptr_rlky) &&
78 MLX5_CAP_ETH(mdev, reg_umr_sq);
81 static void mlx5e_set_rq_type_params(struct mlx5e_priv *priv, u8 rq_type)
83 priv->params.rq_wq_type = rq_type;
84 switch (priv->params.rq_wq_type) {
85 case MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ:
86 priv->params.log_rq_size = MLX5E_PARAMS_DEFAULT_LOG_RQ_SIZE_MPW;
87 priv->params.mpwqe_log_stride_sz =
88 MLX5E_GET_PFLAG(priv, MLX5E_PFLAG_RX_CQE_COMPRESS) ?
89 MLX5_MPWRQ_LOG_STRIDE_SIZE_CQE_COMPRESS :
90 MLX5_MPWRQ_LOG_STRIDE_SIZE;
91 priv->params.mpwqe_log_num_strides = MLX5_MPWRQ_LOG_WQE_SZ -
92 priv->params.mpwqe_log_stride_sz;
94 default: /* MLX5_WQ_TYPE_LINKED_LIST */
95 priv->params.log_rq_size = MLX5E_PARAMS_DEFAULT_LOG_RQ_SIZE;
97 priv->params.min_rx_wqes = mlx5_min_rx_wqes(priv->params.rq_wq_type,
98 BIT(priv->params.log_rq_size));
100 mlx5_core_info(priv->mdev,
101 "MLX5E: StrdRq(%d) RqSz(%ld) StrdSz(%ld) RxCqeCmprss(%d)\n",
102 priv->params.rq_wq_type == MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ,
103 BIT(priv->params.log_rq_size),
104 BIT(priv->params.mpwqe_log_stride_sz),
105 MLX5E_GET_PFLAG(priv, MLX5E_PFLAG_RX_CQE_COMPRESS));
108 static void mlx5e_set_rq_priv_params(struct mlx5e_priv *priv)
110 u8 rq_type = mlx5e_check_fragmented_striding_rq_cap(priv->mdev) &&
112 MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ :
113 MLX5_WQ_TYPE_LINKED_LIST;
114 mlx5e_set_rq_type_params(priv, rq_type);
117 static void mlx5e_update_carrier(struct mlx5e_priv *priv)
119 struct mlx5_core_dev *mdev = priv->mdev;
122 port_state = mlx5_query_vport_state(mdev,
123 MLX5_QUERY_VPORT_STATE_IN_OP_MOD_VNIC_VPORT, 0);
125 if (port_state == VPORT_STATE_UP) {
126 netdev_info(priv->netdev, "Link up\n");
127 netif_carrier_on(priv->netdev);
129 netdev_info(priv->netdev, "Link down\n");
130 netif_carrier_off(priv->netdev);
134 static void mlx5e_update_carrier_work(struct work_struct *work)
136 struct mlx5e_priv *priv = container_of(work, struct mlx5e_priv,
137 update_carrier_work);
139 mutex_lock(&priv->state_lock);
140 if (test_bit(MLX5E_STATE_OPENED, &priv->state))
141 mlx5e_update_carrier(priv);
142 mutex_unlock(&priv->state_lock);
145 static void mlx5e_tx_timeout_work(struct work_struct *work)
147 struct mlx5e_priv *priv = container_of(work, struct mlx5e_priv,
152 mutex_lock(&priv->state_lock);
153 if (!test_bit(MLX5E_STATE_OPENED, &priv->state))
155 mlx5e_close_locked(priv->netdev);
156 err = mlx5e_open_locked(priv->netdev);
158 netdev_err(priv->netdev, "mlx5e_open_locked failed recovering from a tx_timeout, err(%d).\n",
161 mutex_unlock(&priv->state_lock);
165 static void mlx5e_update_sw_counters(struct mlx5e_priv *priv)
167 struct mlx5e_sw_stats *s = &priv->stats.sw;
168 struct mlx5e_rq_stats *rq_stats;
169 struct mlx5e_sq_stats *sq_stats;
170 u64 tx_offload_none = 0;
173 memset(s, 0, sizeof(*s));
174 for (i = 0; i < priv->params.num_channels; i++) {
175 rq_stats = &priv->channel[i]->rq.stats;
177 s->rx_packets += rq_stats->packets;
178 s->rx_bytes += rq_stats->bytes;
179 s->rx_lro_packets += rq_stats->lro_packets;
180 s->rx_lro_bytes += rq_stats->lro_bytes;
181 s->rx_csum_none += rq_stats->csum_none;
182 s->rx_csum_complete += rq_stats->csum_complete;
183 s->rx_csum_unnecessary_inner += rq_stats->csum_unnecessary_inner;
184 s->rx_xdp_drop += rq_stats->xdp_drop;
185 s->rx_xdp_tx += rq_stats->xdp_tx;
186 s->rx_xdp_tx_full += rq_stats->xdp_tx_full;
187 s->rx_wqe_err += rq_stats->wqe_err;
188 s->rx_mpwqe_filler += rq_stats->mpwqe_filler;
189 s->rx_buff_alloc_err += rq_stats->buff_alloc_err;
190 s->rx_cqe_compress_blks += rq_stats->cqe_compress_blks;
191 s->rx_cqe_compress_pkts += rq_stats->cqe_compress_pkts;
192 s->rx_cache_reuse += rq_stats->cache_reuse;
193 s->rx_cache_full += rq_stats->cache_full;
194 s->rx_cache_empty += rq_stats->cache_empty;
195 s->rx_cache_busy += rq_stats->cache_busy;
197 for (j = 0; j < priv->params.num_tc; j++) {
198 sq_stats = &priv->channel[i]->sq[j].stats;
200 s->tx_packets += sq_stats->packets;
201 s->tx_bytes += sq_stats->bytes;
202 s->tx_tso_packets += sq_stats->tso_packets;
203 s->tx_tso_bytes += sq_stats->tso_bytes;
204 s->tx_tso_inner_packets += sq_stats->tso_inner_packets;
205 s->tx_tso_inner_bytes += sq_stats->tso_inner_bytes;
206 s->tx_queue_stopped += sq_stats->stopped;
207 s->tx_queue_wake += sq_stats->wake;
208 s->tx_queue_dropped += sq_stats->dropped;
209 s->tx_xmit_more += sq_stats->xmit_more;
210 s->tx_csum_partial_inner += sq_stats->csum_partial_inner;
211 tx_offload_none += sq_stats->csum_none;
215 /* Update calculated offload counters */
216 s->tx_csum_partial = s->tx_packets - tx_offload_none - s->tx_csum_partial_inner;
217 s->rx_csum_unnecessary = s->rx_packets - s->rx_csum_none - s->rx_csum_complete;
219 s->link_down_events_phy = MLX5_GET(ppcnt_reg,
220 priv->stats.pport.phy_counters,
221 counter_set.phys_layer_cntrs.link_down_events);
224 static void mlx5e_update_vport_counters(struct mlx5e_priv *priv)
226 int outlen = MLX5_ST_SZ_BYTES(query_vport_counter_out);
227 u32 *out = (u32 *)priv->stats.vport.query_vport_out;
228 u32 in[MLX5_ST_SZ_DW(query_vport_counter_in)] = {0};
229 struct mlx5_core_dev *mdev = priv->mdev;
231 MLX5_SET(query_vport_counter_in, in, opcode,
232 MLX5_CMD_OP_QUERY_VPORT_COUNTER);
233 MLX5_SET(query_vport_counter_in, in, op_mod, 0);
234 MLX5_SET(query_vport_counter_in, in, other_vport, 0);
236 memset(out, 0, outlen);
237 mlx5_cmd_exec(mdev, in, sizeof(in), out, outlen);
240 static void mlx5e_update_pport_counters(struct mlx5e_priv *priv)
242 struct mlx5e_pport_stats *pstats = &priv->stats.pport;
243 struct mlx5_core_dev *mdev = priv->mdev;
244 int sz = MLX5_ST_SZ_BYTES(ppcnt_reg);
249 in = mlx5_vzalloc(sz);
253 MLX5_SET(ppcnt_reg, in, local_port, 1);
255 out = pstats->IEEE_802_3_counters;
256 MLX5_SET(ppcnt_reg, in, grp, MLX5_IEEE_802_3_COUNTERS_GROUP);
257 mlx5_core_access_reg(mdev, in, sz, out, sz, MLX5_REG_PPCNT, 0, 0);
259 out = pstats->RFC_2863_counters;
260 MLX5_SET(ppcnt_reg, in, grp, MLX5_RFC_2863_COUNTERS_GROUP);
261 mlx5_core_access_reg(mdev, in, sz, out, sz, MLX5_REG_PPCNT, 0, 0);
263 out = pstats->RFC_2819_counters;
264 MLX5_SET(ppcnt_reg, in, grp, MLX5_RFC_2819_COUNTERS_GROUP);
265 mlx5_core_access_reg(mdev, in, sz, out, sz, MLX5_REG_PPCNT, 0, 0);
267 out = pstats->phy_counters;
268 MLX5_SET(ppcnt_reg, in, grp, MLX5_PHYSICAL_LAYER_COUNTERS_GROUP);
269 mlx5_core_access_reg(mdev, in, sz, out, sz, MLX5_REG_PPCNT, 0, 0);
271 if (MLX5_CAP_PCAM_FEATURE(mdev, ppcnt_statistical_group)) {
272 out = pstats->phy_statistical_counters;
273 MLX5_SET(ppcnt_reg, in, grp, MLX5_PHYSICAL_LAYER_STATISTICAL_GROUP);
274 mlx5_core_access_reg(mdev, in, sz, out, sz, MLX5_REG_PPCNT, 0, 0);
277 MLX5_SET(ppcnt_reg, in, grp, MLX5_PER_PRIORITY_COUNTERS_GROUP);
278 for (prio = 0; prio < NUM_PPORT_PRIO; prio++) {
279 out = pstats->per_prio_counters[prio];
280 MLX5_SET(ppcnt_reg, in, prio_tc, prio);
281 mlx5_core_access_reg(mdev, in, sz, out, sz,
282 MLX5_REG_PPCNT, 0, 0);
289 static void mlx5e_update_q_counter(struct mlx5e_priv *priv)
291 struct mlx5e_qcounter_stats *qcnt = &priv->stats.qcnt;
293 if (!priv->q_counter)
296 mlx5_core_query_out_of_buffer(priv->mdev, priv->q_counter,
297 &qcnt->rx_out_of_buffer);
300 static void mlx5e_update_pcie_counters(struct mlx5e_priv *priv)
302 struct mlx5e_pcie_stats *pcie_stats = &priv->stats.pcie;
303 struct mlx5_core_dev *mdev = priv->mdev;
304 int sz = MLX5_ST_SZ_BYTES(mpcnt_reg);
308 if (!MLX5_CAP_MCAM_FEATURE(mdev, pcie_performance_group))
311 in = mlx5_vzalloc(sz);
315 out = pcie_stats->pcie_perf_counters;
316 MLX5_SET(mpcnt_reg, in, grp, MLX5_PCIE_PERFORMANCE_COUNTERS_GROUP);
317 mlx5_core_access_reg(mdev, in, sz, out, sz, MLX5_REG_MPCNT, 0, 0);
322 void mlx5e_update_stats(struct mlx5e_priv *priv)
324 mlx5e_update_q_counter(priv);
325 mlx5e_update_vport_counters(priv);
326 mlx5e_update_pport_counters(priv);
327 mlx5e_update_sw_counters(priv);
328 mlx5e_update_pcie_counters(priv);
331 void mlx5e_update_stats_work(struct work_struct *work)
333 struct delayed_work *dwork = to_delayed_work(work);
334 struct mlx5e_priv *priv = container_of(dwork, struct mlx5e_priv,
336 mutex_lock(&priv->state_lock);
337 if (test_bit(MLX5E_STATE_OPENED, &priv->state)) {
338 priv->profile->update_stats(priv);
339 queue_delayed_work(priv->wq, dwork,
340 msecs_to_jiffies(MLX5E_UPDATE_STATS_INTERVAL));
342 mutex_unlock(&priv->state_lock);
345 static void mlx5e_async_event(struct mlx5_core_dev *mdev, void *vpriv,
346 enum mlx5_dev_event event, unsigned long param)
348 struct mlx5e_priv *priv = vpriv;
349 struct ptp_clock_event ptp_event;
350 struct mlx5_eqe *eqe = NULL;
352 if (!test_bit(MLX5E_STATE_ASYNC_EVENTS_ENABLED, &priv->state))
356 case MLX5_DEV_EVENT_PORT_UP:
357 case MLX5_DEV_EVENT_PORT_DOWN:
358 queue_work(priv->wq, &priv->update_carrier_work);
360 case MLX5_DEV_EVENT_PPS:
361 eqe = (struct mlx5_eqe *)param;
362 ptp_event.type = PTP_CLOCK_EXTTS;
363 ptp_event.index = eqe->data.pps.pin;
364 ptp_event.timestamp =
365 timecounter_cyc2time(&priv->tstamp.clock,
366 be64_to_cpu(eqe->data.pps.time_stamp));
367 mlx5e_pps_event_handler(vpriv, &ptp_event);
374 static void mlx5e_enable_async_events(struct mlx5e_priv *priv)
376 set_bit(MLX5E_STATE_ASYNC_EVENTS_ENABLED, &priv->state);
379 static void mlx5e_disable_async_events(struct mlx5e_priv *priv)
381 clear_bit(MLX5E_STATE_ASYNC_EVENTS_ENABLED, &priv->state);
382 synchronize_irq(mlx5_get_msix_vec(priv->mdev, MLX5_EQ_VEC_ASYNC));
385 static inline int mlx5e_get_wqe_mtt_sz(void)
387 /* UMR copies MTTs in units of MLX5_UMR_MTT_ALIGNMENT bytes.
388 * To avoid copying garbage after the mtt array, we allocate
391 return ALIGN(MLX5_MPWRQ_PAGES_PER_WQE * sizeof(__be64),
392 MLX5_UMR_MTT_ALIGNMENT);
395 static inline void mlx5e_build_umr_wqe(struct mlx5e_rq *rq, struct mlx5e_sq *sq,
396 struct mlx5e_umr_wqe *wqe, u16 ix)
398 struct mlx5_wqe_ctrl_seg *cseg = &wqe->ctrl;
399 struct mlx5_wqe_umr_ctrl_seg *ucseg = &wqe->uctrl;
400 struct mlx5_wqe_data_seg *dseg = &wqe->data;
401 struct mlx5e_mpw_info *wi = &rq->mpwqe.info[ix];
402 u8 ds_cnt = DIV_ROUND_UP(sizeof(*wqe), MLX5_SEND_WQE_DS);
403 u32 umr_wqe_mtt_offset = mlx5e_get_wqe_mtt_offset(rq, ix);
405 cseg->qpn_ds = cpu_to_be32((sq->sqn << MLX5_WQE_CTRL_QPN_SHIFT) |
407 cseg->fm_ce_se = MLX5_WQE_CTRL_CQ_UPDATE;
408 cseg->imm = rq->mkey_be;
410 ucseg->flags = MLX5_UMR_TRANSLATION_OFFSET_EN;
411 ucseg->xlt_octowords =
412 cpu_to_be16(MLX5_MTT_OCTW(MLX5_MPWRQ_PAGES_PER_WQE));
413 ucseg->bsf_octowords =
414 cpu_to_be16(MLX5_MTT_OCTW(umr_wqe_mtt_offset));
415 ucseg->mkey_mask = cpu_to_be64(MLX5_MKEY_MASK_FREE);
417 dseg->lkey = sq->mkey_be;
418 dseg->addr = cpu_to_be64(wi->umr.mtt_addr);
421 static int mlx5e_rq_alloc_mpwqe_info(struct mlx5e_rq *rq,
422 struct mlx5e_channel *c)
424 int wq_sz = mlx5_wq_ll_get_size(&rq->wq);
425 int mtt_sz = mlx5e_get_wqe_mtt_sz();
426 int mtt_alloc = mtt_sz + MLX5_UMR_ALIGN - 1;
429 rq->mpwqe.info = kzalloc_node(wq_sz * sizeof(*rq->mpwqe.info),
430 GFP_KERNEL, cpu_to_node(c->cpu));
434 /* We allocate more than mtt_sz as we will align the pointer */
435 rq->mpwqe.mtt_no_align = kzalloc_node(mtt_alloc * wq_sz, GFP_KERNEL,
436 cpu_to_node(c->cpu));
437 if (unlikely(!rq->mpwqe.mtt_no_align))
438 goto err_free_wqe_info;
440 for (i = 0; i < wq_sz; i++) {
441 struct mlx5e_mpw_info *wi = &rq->mpwqe.info[i];
443 wi->umr.mtt = PTR_ALIGN(rq->mpwqe.mtt_no_align + i * mtt_alloc,
445 wi->umr.mtt_addr = dma_map_single(c->pdev, wi->umr.mtt, mtt_sz,
447 if (unlikely(dma_mapping_error(c->pdev, wi->umr.mtt_addr)))
450 mlx5e_build_umr_wqe(rq, &c->icosq, &wi->umr.wqe, i);
457 struct mlx5e_mpw_info *wi = &rq->mpwqe.info[i];
459 dma_unmap_single(c->pdev, wi->umr.mtt_addr, mtt_sz,
462 kfree(rq->mpwqe.mtt_no_align);
464 kfree(rq->mpwqe.info);
470 static void mlx5e_rq_free_mpwqe_info(struct mlx5e_rq *rq)
472 int wq_sz = mlx5_wq_ll_get_size(&rq->wq);
473 int mtt_sz = mlx5e_get_wqe_mtt_sz();
476 for (i = 0; i < wq_sz; i++) {
477 struct mlx5e_mpw_info *wi = &rq->mpwqe.info[i];
479 dma_unmap_single(rq->pdev, wi->umr.mtt_addr, mtt_sz,
482 kfree(rq->mpwqe.mtt_no_align);
483 kfree(rq->mpwqe.info);
486 static int mlx5e_create_umr_mkey(struct mlx5e_priv *priv,
487 u64 npages, u8 page_shift,
488 struct mlx5_core_mkey *umr_mkey)
490 struct mlx5_core_dev *mdev = priv->mdev;
491 int inlen = MLX5_ST_SZ_BYTES(create_mkey_in);
496 if (!MLX5E_VALID_NUM_MTTS(npages))
499 in = mlx5_vzalloc(inlen);
503 mkc = MLX5_ADDR_OF(create_mkey_in, in, memory_key_mkey_entry);
505 MLX5_SET(mkc, mkc, free, 1);
506 MLX5_SET(mkc, mkc, umr_en, 1);
507 MLX5_SET(mkc, mkc, lw, 1);
508 MLX5_SET(mkc, mkc, lr, 1);
509 MLX5_SET(mkc, mkc, access_mode, MLX5_MKC_ACCESS_MODE_MTT);
511 MLX5_SET(mkc, mkc, qpn, 0xffffff);
512 MLX5_SET(mkc, mkc, pd, mdev->mlx5e_res.pdn);
513 MLX5_SET64(mkc, mkc, len, npages << page_shift);
514 MLX5_SET(mkc, mkc, translations_octword_size,
515 MLX5_MTT_OCTW(npages));
516 MLX5_SET(mkc, mkc, log_page_size, page_shift);
518 err = mlx5_core_create_mkey(mdev, umr_mkey, in, inlen);
524 static int mlx5e_create_rq_umr_mkey(struct mlx5e_rq *rq)
526 struct mlx5e_priv *priv = rq->priv;
527 u64 num_mtts = MLX5E_REQUIRED_MTTS(BIT(priv->params.log_rq_size));
529 return mlx5e_create_umr_mkey(priv, num_mtts, PAGE_SHIFT, &rq->umr_mkey);
532 static int mlx5e_create_rq(struct mlx5e_channel *c,
533 struct mlx5e_rq_param *param,
536 struct mlx5e_priv *priv = c->priv;
537 struct mlx5_core_dev *mdev = priv->mdev;
538 void *rqc = param->rqc;
539 void *rqc_wq = MLX5_ADDR_OF(rqc, rqc, wq);
547 param->wq.db_numa_node = cpu_to_node(c->cpu);
549 err = mlx5_wq_ll_create(mdev, ¶m->wq, rqc_wq, &rq->wq,
554 rq->wq.db = &rq->wq.db[MLX5_RCV_DBR];
556 wq_sz = mlx5_wq_ll_get_size(&rq->wq);
558 rq->wq_type = priv->params.rq_wq_type;
560 rq->netdev = c->netdev;
561 rq->tstamp = &priv->tstamp;
566 rq->xdp_prog = priv->xdp_prog ? bpf_prog_inc(priv->xdp_prog) : NULL;
567 if (IS_ERR(rq->xdp_prog)) {
568 err = PTR_ERR(rq->xdp_prog);
570 goto err_rq_wq_destroy;
574 rq->buff.map_dir = DMA_BIDIRECTIONAL;
575 rq->rx_headroom = XDP_PACKET_HEADROOM;
577 rq->buff.map_dir = DMA_FROM_DEVICE;
578 rq->rx_headroom = MLX5_RX_HEADROOM;
581 switch (priv->params.rq_wq_type) {
582 case MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ:
583 if (mlx5e_is_vf_vport_rep(priv)) {
585 goto err_rq_wq_destroy;
588 rq->handle_rx_cqe = mlx5e_handle_rx_cqe_mpwrq;
589 rq->alloc_wqe = mlx5e_alloc_rx_mpwqe;
590 rq->dealloc_wqe = mlx5e_dealloc_rx_mpwqe;
592 rq->mpwqe_stride_sz = BIT(priv->params.mpwqe_log_stride_sz);
593 rq->mpwqe_num_strides = BIT(priv->params.mpwqe_log_num_strides);
595 rq->buff.wqe_sz = rq->mpwqe_stride_sz * rq->mpwqe_num_strides;
596 byte_count = rq->buff.wqe_sz;
598 err = mlx5e_create_rq_umr_mkey(rq);
600 goto err_rq_wq_destroy;
601 rq->mkey_be = cpu_to_be32(rq->umr_mkey.key);
603 err = mlx5e_rq_alloc_mpwqe_info(rq, c);
605 goto err_destroy_umr_mkey;
607 default: /* MLX5_WQ_TYPE_LINKED_LIST */
608 rq->dma_info = kzalloc_node(wq_sz * sizeof(*rq->dma_info),
609 GFP_KERNEL, cpu_to_node(c->cpu));
612 goto err_rq_wq_destroy;
615 if (mlx5e_is_vf_vport_rep(priv))
616 rq->handle_rx_cqe = mlx5e_handle_rx_cqe_rep;
618 rq->handle_rx_cqe = mlx5e_handle_rx_cqe;
620 rq->alloc_wqe = mlx5e_alloc_rx_wqe;
621 rq->dealloc_wqe = mlx5e_dealloc_rx_wqe;
623 rq->buff.wqe_sz = (priv->params.lro_en) ?
624 priv->params.lro_wqe_sz :
625 MLX5E_SW2HW_MTU(priv->netdev->mtu);
626 byte_count = rq->buff.wqe_sz;
628 /* calc the required page order */
629 frag_sz = rq->rx_headroom +
630 byte_count /* packet data */ +
631 SKB_DATA_ALIGN(sizeof(struct skb_shared_info));
632 frag_sz = SKB_DATA_ALIGN(frag_sz);
634 npages = DIV_ROUND_UP(frag_sz, PAGE_SIZE);
635 rq->buff.page_order = order_base_2(npages);
637 byte_count |= MLX5_HW_START_PADDING;
638 rq->mkey_be = c->mkey_be;
641 for (i = 0; i < wq_sz; i++) {
642 struct mlx5e_rx_wqe *wqe = mlx5_wq_ll_get_wqe(&rq->wq, i);
644 wqe->data.byte_count = cpu_to_be32(byte_count);
645 wqe->data.lkey = rq->mkey_be;
648 INIT_WORK(&rq->am.work, mlx5e_rx_am_work);
649 rq->am.mode = priv->params.rx_cq_period_mode;
651 rq->page_cache.head = 0;
652 rq->page_cache.tail = 0;
656 err_destroy_umr_mkey:
657 mlx5_core_destroy_mkey(mdev, &rq->umr_mkey);
661 bpf_prog_put(rq->xdp_prog);
662 mlx5_wq_destroy(&rq->wq_ctrl);
667 static void mlx5e_destroy_rq(struct mlx5e_rq *rq)
672 bpf_prog_put(rq->xdp_prog);
674 switch (rq->wq_type) {
675 case MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ:
676 mlx5e_rq_free_mpwqe_info(rq);
677 mlx5_core_destroy_mkey(rq->priv->mdev, &rq->umr_mkey);
679 default: /* MLX5_WQ_TYPE_LINKED_LIST */
683 for (i = rq->page_cache.head; i != rq->page_cache.tail;
684 i = (i + 1) & (MLX5E_CACHE_SIZE - 1)) {
685 struct mlx5e_dma_info *dma_info = &rq->page_cache.page_cache[i];
687 mlx5e_page_release(rq, dma_info, false);
689 mlx5_wq_destroy(&rq->wq_ctrl);
692 static int mlx5e_enable_rq(struct mlx5e_rq *rq, struct mlx5e_rq_param *param)
694 struct mlx5e_priv *priv = rq->priv;
695 struct mlx5_core_dev *mdev = priv->mdev;
703 inlen = MLX5_ST_SZ_BYTES(create_rq_in) +
704 sizeof(u64) * rq->wq_ctrl.buf.npages;
705 in = mlx5_vzalloc(inlen);
709 rqc = MLX5_ADDR_OF(create_rq_in, in, ctx);
710 wq = MLX5_ADDR_OF(rqc, rqc, wq);
712 memcpy(rqc, param->rqc, sizeof(param->rqc));
714 MLX5_SET(rqc, rqc, cqn, rq->cq.mcq.cqn);
715 MLX5_SET(rqc, rqc, state, MLX5_RQC_STATE_RST);
716 MLX5_SET(rqc, rqc, vsd, priv->params.vlan_strip_disable);
717 MLX5_SET(wq, wq, log_wq_pg_sz, rq->wq_ctrl.buf.page_shift -
718 MLX5_ADAPTER_PAGE_SHIFT);
719 MLX5_SET64(wq, wq, dbr_addr, rq->wq_ctrl.db.dma);
721 mlx5_fill_page_array(&rq->wq_ctrl.buf,
722 (__be64 *)MLX5_ADDR_OF(wq, wq, pas));
724 err = mlx5_core_create_rq(mdev, in, inlen, &rq->rqn);
731 static int mlx5e_modify_rq_state(struct mlx5e_rq *rq, int curr_state,
734 struct mlx5e_channel *c = rq->channel;
735 struct mlx5e_priv *priv = c->priv;
736 struct mlx5_core_dev *mdev = priv->mdev;
743 inlen = MLX5_ST_SZ_BYTES(modify_rq_in);
744 in = mlx5_vzalloc(inlen);
748 rqc = MLX5_ADDR_OF(modify_rq_in, in, ctx);
750 MLX5_SET(modify_rq_in, in, rq_state, curr_state);
751 MLX5_SET(rqc, rqc, state, next_state);
753 err = mlx5_core_modify_rq(mdev, rq->rqn, in, inlen);
760 static int mlx5e_modify_rq_vsd(struct mlx5e_rq *rq, bool vsd)
762 struct mlx5e_channel *c = rq->channel;
763 struct mlx5e_priv *priv = c->priv;
764 struct mlx5_core_dev *mdev = priv->mdev;
771 inlen = MLX5_ST_SZ_BYTES(modify_rq_in);
772 in = mlx5_vzalloc(inlen);
776 rqc = MLX5_ADDR_OF(modify_rq_in, in, ctx);
778 MLX5_SET(modify_rq_in, in, rq_state, MLX5_RQC_STATE_RDY);
779 MLX5_SET64(modify_rq_in, in, modify_bitmask,
780 MLX5_MODIFY_RQ_IN_MODIFY_BITMASK_VSD);
781 MLX5_SET(rqc, rqc, vsd, vsd);
782 MLX5_SET(rqc, rqc, state, MLX5_RQC_STATE_RDY);
784 err = mlx5_core_modify_rq(mdev, rq->rqn, in, inlen);
791 static void mlx5e_disable_rq(struct mlx5e_rq *rq)
793 mlx5_core_destroy_rq(rq->priv->mdev, rq->rqn);
796 static int mlx5e_wait_for_min_rx_wqes(struct mlx5e_rq *rq)
798 unsigned long exp_time = jiffies + msecs_to_jiffies(20000);
799 struct mlx5e_channel *c = rq->channel;
800 struct mlx5e_priv *priv = c->priv;
801 struct mlx5_wq_ll *wq = &rq->wq;
803 while (time_before(jiffies, exp_time)) {
804 if (wq->cur_sz >= priv->params.min_rx_wqes)
813 static void mlx5e_free_rx_descs(struct mlx5e_rq *rq)
815 struct mlx5_wq_ll *wq = &rq->wq;
816 struct mlx5e_rx_wqe *wqe;
820 /* UMR WQE (if in progress) is always at wq->head */
821 if (test_bit(MLX5E_RQ_STATE_UMR_WQE_IN_PROGRESS, &rq->state))
822 mlx5e_free_rx_mpwqe(rq, &rq->mpwqe.info[wq->head]);
824 while (!mlx5_wq_ll_is_empty(wq)) {
825 wqe_ix_be = *wq->tail_next;
826 wqe_ix = be16_to_cpu(wqe_ix_be);
827 wqe = mlx5_wq_ll_get_wqe(&rq->wq, wqe_ix);
828 rq->dealloc_wqe(rq, wqe_ix);
829 mlx5_wq_ll_pop(&rq->wq, wqe_ix_be,
830 &wqe->next.next_wqe_index);
834 static int mlx5e_open_rq(struct mlx5e_channel *c,
835 struct mlx5e_rq_param *param,
838 struct mlx5e_sq *sq = &c->icosq;
839 u16 pi = sq->pc & sq->wq.sz_m1;
842 err = mlx5e_create_rq(c, param, rq);
846 err = mlx5e_enable_rq(rq, param);
850 set_bit(MLX5E_RQ_STATE_ENABLED, &rq->state);
851 err = mlx5e_modify_rq_state(rq, MLX5_RQC_STATE_RST, MLX5_RQC_STATE_RDY);
855 if (param->am_enabled)
856 set_bit(MLX5E_RQ_STATE_AM, &c->rq.state);
858 sq->db.ico_wqe[pi].opcode = MLX5_OPCODE_NOP;
859 sq->db.ico_wqe[pi].num_wqebbs = 1;
860 mlx5e_send_nop(sq, true); /* trigger mlx5e_post_rx_wqes() */
865 clear_bit(MLX5E_RQ_STATE_ENABLED, &rq->state);
866 mlx5e_disable_rq(rq);
868 mlx5e_destroy_rq(rq);
873 static void mlx5e_close_rq(struct mlx5e_rq *rq)
875 clear_bit(MLX5E_RQ_STATE_ENABLED, &rq->state);
876 napi_synchronize(&rq->channel->napi); /* prevent mlx5e_post_rx_wqes */
877 cancel_work_sync(&rq->am.work);
879 mlx5e_disable_rq(rq);
880 mlx5e_free_rx_descs(rq);
881 mlx5e_destroy_rq(rq);
884 static void mlx5e_free_sq_xdp_db(struct mlx5e_sq *sq)
886 kfree(sq->db.xdp.di);
887 kfree(sq->db.xdp.wqe_info);
890 static int mlx5e_alloc_sq_xdp_db(struct mlx5e_sq *sq, int numa)
892 int wq_sz = mlx5_wq_cyc_get_size(&sq->wq);
894 sq->db.xdp.di = kzalloc_node(sizeof(*sq->db.xdp.di) * wq_sz,
896 sq->db.xdp.wqe_info = kzalloc_node(sizeof(*sq->db.xdp.wqe_info) * wq_sz,
898 if (!sq->db.xdp.di || !sq->db.xdp.wqe_info) {
899 mlx5e_free_sq_xdp_db(sq);
906 static void mlx5e_free_sq_ico_db(struct mlx5e_sq *sq)
908 kfree(sq->db.ico_wqe);
911 static int mlx5e_alloc_sq_ico_db(struct mlx5e_sq *sq, int numa)
913 u8 wq_sz = mlx5_wq_cyc_get_size(&sq->wq);
915 sq->db.ico_wqe = kzalloc_node(sizeof(*sq->db.ico_wqe) * wq_sz,
923 static void mlx5e_free_sq_txq_db(struct mlx5e_sq *sq)
925 kfree(sq->db.txq.wqe_info);
926 kfree(sq->db.txq.dma_fifo);
927 kfree(sq->db.txq.skb);
930 static int mlx5e_alloc_sq_txq_db(struct mlx5e_sq *sq, int numa)
932 int wq_sz = mlx5_wq_cyc_get_size(&sq->wq);
933 int df_sz = wq_sz * MLX5_SEND_WQEBB_NUM_DS;
935 sq->db.txq.skb = kzalloc_node(wq_sz * sizeof(*sq->db.txq.skb),
937 sq->db.txq.dma_fifo = kzalloc_node(df_sz * sizeof(*sq->db.txq.dma_fifo),
939 sq->db.txq.wqe_info = kzalloc_node(wq_sz * sizeof(*sq->db.txq.wqe_info),
941 if (!sq->db.txq.skb || !sq->db.txq.dma_fifo || !sq->db.txq.wqe_info) {
942 mlx5e_free_sq_txq_db(sq);
946 sq->dma_fifo_mask = df_sz - 1;
951 static void mlx5e_free_sq_db(struct mlx5e_sq *sq)
955 mlx5e_free_sq_txq_db(sq);
958 mlx5e_free_sq_ico_db(sq);
961 mlx5e_free_sq_xdp_db(sq);
966 static int mlx5e_alloc_sq_db(struct mlx5e_sq *sq, int numa)
970 return mlx5e_alloc_sq_txq_db(sq, numa);
972 return mlx5e_alloc_sq_ico_db(sq, numa);
974 return mlx5e_alloc_sq_xdp_db(sq, numa);
980 static int mlx5e_sq_get_max_wqebbs(u8 sq_type)
984 return MLX5E_ICOSQ_MAX_WQEBBS;
986 return MLX5E_XDP_TX_WQEBBS;
988 return MLX5_SEND_WQE_MAX_WQEBBS;
991 static int mlx5e_create_sq(struct mlx5e_channel *c,
993 struct mlx5e_sq_param *param,
996 struct mlx5e_priv *priv = c->priv;
997 struct mlx5_core_dev *mdev = priv->mdev;
999 void *sqc = param->sqc;
1000 void *sqc_wq = MLX5_ADDR_OF(sqc, sqc, wq);
1003 sq->type = param->type;
1005 sq->tstamp = &priv->tstamp;
1006 sq->mkey_be = c->mkey_be;
1010 err = mlx5_alloc_bfreg(mdev, &sq->bfreg, MLX5_CAP_GEN(mdev, bf), false);
1014 param->wq.db_numa_node = cpu_to_node(c->cpu);
1016 err = mlx5_wq_cyc_create(mdev, ¶m->wq, sqc_wq, &sq->wq,
1019 goto err_unmap_free_uar;
1021 sq->wq.db = &sq->wq.db[MLX5_SND_DBR];
1023 set_bit(MLX5E_SQ_STATE_BF_ENABLE, &sq->state);
1025 sq->bf_buf_size = (1 << MLX5_CAP_GEN(mdev, log_bf_reg_size)) / 2;
1026 sq->max_inline = param->max_inline;
1027 sq->min_inline_mode =
1028 MLX5_CAP_ETH(mdev, wqe_inline_mode) == MLX5_CAP_INLINE_MODE_VPORT_CONTEXT ?
1029 param->min_inline_mode : 0;
1031 err = mlx5e_alloc_sq_db(sq, cpu_to_node(c->cpu));
1033 goto err_sq_wq_destroy;
1035 if (sq->type == MLX5E_SQ_TXQ) {
1038 txq_ix = c->ix + tc * priv->params.num_channels;
1039 sq->txq = netdev_get_tx_queue(priv->netdev, txq_ix);
1040 priv->txq_to_sq_map[txq_ix] = sq;
1043 sq->edge = (sq->wq.sz_m1 + 1) - mlx5e_sq_get_max_wqebbs(sq->type);
1044 sq->bf_budget = MLX5E_SQ_BF_BUDGET;
1049 mlx5_wq_destroy(&sq->wq_ctrl);
1052 mlx5_free_bfreg(mdev, &sq->bfreg);
1057 static void mlx5e_destroy_sq(struct mlx5e_sq *sq)
1059 struct mlx5e_channel *c = sq->channel;
1060 struct mlx5e_priv *priv = c->priv;
1062 mlx5e_free_sq_db(sq);
1063 mlx5_wq_destroy(&sq->wq_ctrl);
1064 mlx5_free_bfreg(priv->mdev, &sq->bfreg);
1067 static int mlx5e_enable_sq(struct mlx5e_sq *sq, struct mlx5e_sq_param *param)
1069 struct mlx5e_channel *c = sq->channel;
1070 struct mlx5e_priv *priv = c->priv;
1071 struct mlx5_core_dev *mdev = priv->mdev;
1079 inlen = MLX5_ST_SZ_BYTES(create_sq_in) +
1080 sizeof(u64) * sq->wq_ctrl.buf.npages;
1081 in = mlx5_vzalloc(inlen);
1085 sqc = MLX5_ADDR_OF(create_sq_in, in, ctx);
1086 wq = MLX5_ADDR_OF(sqc, sqc, wq);
1088 memcpy(sqc, param->sqc, sizeof(param->sqc));
1090 MLX5_SET(sqc, sqc, tis_num_0, param->type == MLX5E_SQ_ICO ?
1091 0 : priv->tisn[sq->tc]);
1092 MLX5_SET(sqc, sqc, cqn, sq->cq.mcq.cqn);
1093 MLX5_SET(sqc, sqc, min_wqe_inline_mode, sq->min_inline_mode);
1094 MLX5_SET(sqc, sqc, state, MLX5_SQC_STATE_RST);
1095 MLX5_SET(sqc, sqc, tis_lst_sz, param->type == MLX5E_SQ_ICO ? 0 : 1);
1097 MLX5_SET(wq, wq, wq_type, MLX5_WQ_TYPE_CYCLIC);
1098 MLX5_SET(wq, wq, uar_page, sq->bfreg.index);
1099 MLX5_SET(wq, wq, log_wq_pg_sz, sq->wq_ctrl.buf.page_shift -
1100 MLX5_ADAPTER_PAGE_SHIFT);
1101 MLX5_SET64(wq, wq, dbr_addr, sq->wq_ctrl.db.dma);
1103 mlx5_fill_page_array(&sq->wq_ctrl.buf,
1104 (__be64 *)MLX5_ADDR_OF(wq, wq, pas));
1106 err = mlx5_core_create_sq(mdev, in, inlen, &sq->sqn);
1113 static int mlx5e_modify_sq(struct mlx5e_sq *sq, int curr_state,
1114 int next_state, bool update_rl, int rl_index)
1116 struct mlx5e_channel *c = sq->channel;
1117 struct mlx5e_priv *priv = c->priv;
1118 struct mlx5_core_dev *mdev = priv->mdev;
1125 inlen = MLX5_ST_SZ_BYTES(modify_sq_in);
1126 in = mlx5_vzalloc(inlen);
1130 sqc = MLX5_ADDR_OF(modify_sq_in, in, ctx);
1132 MLX5_SET(modify_sq_in, in, sq_state, curr_state);
1133 MLX5_SET(sqc, sqc, state, next_state);
1134 if (update_rl && next_state == MLX5_SQC_STATE_RDY) {
1135 MLX5_SET64(modify_sq_in, in, modify_bitmask, 1);
1136 MLX5_SET(sqc, sqc, packet_pacing_rate_limit_index, rl_index);
1139 err = mlx5_core_modify_sq(mdev, sq->sqn, in, inlen);
1146 static void mlx5e_disable_sq(struct mlx5e_sq *sq)
1148 struct mlx5e_channel *c = sq->channel;
1149 struct mlx5e_priv *priv = c->priv;
1150 struct mlx5_core_dev *mdev = priv->mdev;
1152 mlx5_core_destroy_sq(mdev, sq->sqn);
1154 mlx5_rl_remove_rate(mdev, sq->rate_limit);
1157 static int mlx5e_open_sq(struct mlx5e_channel *c,
1159 struct mlx5e_sq_param *param,
1160 struct mlx5e_sq *sq)
1164 err = mlx5e_create_sq(c, tc, param, sq);
1168 err = mlx5e_enable_sq(sq, param);
1170 goto err_destroy_sq;
1172 set_bit(MLX5E_SQ_STATE_ENABLED, &sq->state);
1173 err = mlx5e_modify_sq(sq, MLX5_SQC_STATE_RST, MLX5_SQC_STATE_RDY,
1176 goto err_disable_sq;
1179 netdev_tx_reset_queue(sq->txq);
1180 netif_tx_start_queue(sq->txq);
1186 clear_bit(MLX5E_SQ_STATE_ENABLED, &sq->state);
1187 mlx5e_disable_sq(sq);
1189 mlx5e_destroy_sq(sq);
1194 static inline void netif_tx_disable_queue(struct netdev_queue *txq)
1196 __netif_tx_lock_bh(txq);
1197 netif_tx_stop_queue(txq);
1198 __netif_tx_unlock_bh(txq);
1201 static void mlx5e_close_sq(struct mlx5e_sq *sq)
1203 clear_bit(MLX5E_SQ_STATE_ENABLED, &sq->state);
1204 /* prevent netif_tx_wake_queue */
1205 napi_synchronize(&sq->channel->napi);
1208 netif_tx_disable_queue(sq->txq);
1210 /* last doorbell out, godspeed .. */
1211 if (mlx5e_sq_has_room_for(sq, 1)) {
1212 sq->db.txq.skb[(sq->pc & sq->wq.sz_m1)] = NULL;
1213 mlx5e_send_nop(sq, true);
1217 mlx5e_disable_sq(sq);
1218 mlx5e_free_sq_descs(sq);
1219 mlx5e_destroy_sq(sq);
1222 static int mlx5e_create_cq(struct mlx5e_channel *c,
1223 struct mlx5e_cq_param *param,
1224 struct mlx5e_cq *cq)
1226 struct mlx5e_priv *priv = c->priv;
1227 struct mlx5_core_dev *mdev = priv->mdev;
1228 struct mlx5_core_cq *mcq = &cq->mcq;
1234 param->wq.buf_numa_node = cpu_to_node(c->cpu);
1235 param->wq.db_numa_node = cpu_to_node(c->cpu);
1236 param->eq_ix = c->ix;
1238 err = mlx5_cqwq_create(mdev, ¶m->wq, param->cqc, &cq->wq,
1243 mlx5_vector2eqn(mdev, param->eq_ix, &eqn_not_used, &irqn);
1245 cq->napi = &c->napi;
1248 mcq->set_ci_db = cq->wq_ctrl.db.db;
1249 mcq->arm_db = cq->wq_ctrl.db.db + 1;
1250 *mcq->set_ci_db = 0;
1252 mcq->vector = param->eq_ix;
1253 mcq->comp = mlx5e_completion_event;
1254 mcq->event = mlx5e_cq_error_event;
1257 for (i = 0; i < mlx5_cqwq_get_size(&cq->wq); i++) {
1258 struct mlx5_cqe64 *cqe = mlx5_cqwq_get_wqe(&cq->wq, i);
1269 static void mlx5e_destroy_cq(struct mlx5e_cq *cq)
1271 mlx5_cqwq_destroy(&cq->wq_ctrl);
1274 static int mlx5e_enable_cq(struct mlx5e_cq *cq, struct mlx5e_cq_param *param)
1276 struct mlx5e_priv *priv = cq->priv;
1277 struct mlx5_core_dev *mdev = priv->mdev;
1278 struct mlx5_core_cq *mcq = &cq->mcq;
1283 unsigned int irqn_not_used;
1287 inlen = MLX5_ST_SZ_BYTES(create_cq_in) +
1288 sizeof(u64) * cq->wq_ctrl.frag_buf.npages;
1289 in = mlx5_vzalloc(inlen);
1293 cqc = MLX5_ADDR_OF(create_cq_in, in, cq_context);
1295 memcpy(cqc, param->cqc, sizeof(param->cqc));
1297 mlx5_fill_page_frag_array(&cq->wq_ctrl.frag_buf,
1298 (__be64 *)MLX5_ADDR_OF(create_cq_in, in, pas));
1300 mlx5_vector2eqn(mdev, param->eq_ix, &eqn, &irqn_not_used);
1302 MLX5_SET(cqc, cqc, cq_period_mode, param->cq_period_mode);
1303 MLX5_SET(cqc, cqc, c_eqn, eqn);
1304 MLX5_SET(cqc, cqc, uar_page, mdev->priv.uar->index);
1305 MLX5_SET(cqc, cqc, log_page_size, cq->wq_ctrl.frag_buf.page_shift -
1306 MLX5_ADAPTER_PAGE_SHIFT);
1307 MLX5_SET64(cqc, cqc, dbr_addr, cq->wq_ctrl.db.dma);
1309 err = mlx5_core_create_cq(mdev, mcq, in, inlen);
1321 static void mlx5e_disable_cq(struct mlx5e_cq *cq)
1323 struct mlx5e_priv *priv = cq->priv;
1324 struct mlx5_core_dev *mdev = priv->mdev;
1326 mlx5_core_destroy_cq(mdev, &cq->mcq);
1329 static int mlx5e_open_cq(struct mlx5e_channel *c,
1330 struct mlx5e_cq_param *param,
1331 struct mlx5e_cq *cq,
1332 struct mlx5e_cq_moder moderation)
1335 struct mlx5e_priv *priv = c->priv;
1336 struct mlx5_core_dev *mdev = priv->mdev;
1338 err = mlx5e_create_cq(c, param, cq);
1342 err = mlx5e_enable_cq(cq, param);
1344 goto err_destroy_cq;
1346 if (MLX5_CAP_GEN(mdev, cq_moderation))
1347 mlx5_core_modify_cq_moderation(mdev, &cq->mcq,
1353 mlx5e_destroy_cq(cq);
1358 static void mlx5e_close_cq(struct mlx5e_cq *cq)
1360 mlx5e_disable_cq(cq);
1361 mlx5e_destroy_cq(cq);
1364 static int mlx5e_get_cpu(struct mlx5e_priv *priv, int ix)
1366 return cpumask_first(priv->mdev->priv.irq_info[ix].mask);
1369 static int mlx5e_open_tx_cqs(struct mlx5e_channel *c,
1370 struct mlx5e_channel_param *cparam)
1372 struct mlx5e_priv *priv = c->priv;
1376 for (tc = 0; tc < c->num_tc; tc++) {
1377 err = mlx5e_open_cq(c, &cparam->tx_cq, &c->sq[tc].cq,
1378 priv->params.tx_cq_moderation);
1380 goto err_close_tx_cqs;
1386 for (tc--; tc >= 0; tc--)
1387 mlx5e_close_cq(&c->sq[tc].cq);
1392 static void mlx5e_close_tx_cqs(struct mlx5e_channel *c)
1396 for (tc = 0; tc < c->num_tc; tc++)
1397 mlx5e_close_cq(&c->sq[tc].cq);
1400 static int mlx5e_open_sqs(struct mlx5e_channel *c,
1401 struct mlx5e_channel_param *cparam)
1406 for (tc = 0; tc < c->num_tc; tc++) {
1407 err = mlx5e_open_sq(c, tc, &cparam->sq, &c->sq[tc]);
1415 for (tc--; tc >= 0; tc--)
1416 mlx5e_close_sq(&c->sq[tc]);
1421 static void mlx5e_close_sqs(struct mlx5e_channel *c)
1425 for (tc = 0; tc < c->num_tc; tc++)
1426 mlx5e_close_sq(&c->sq[tc]);
1429 static void mlx5e_build_channeltc_to_txq_map(struct mlx5e_priv *priv, int ix)
1433 for (i = 0; i < priv->profile->max_tc; i++)
1434 priv->channeltc_to_txq_map[ix][i] =
1435 ix + i * priv->params.num_channels;
1438 static int mlx5e_set_sq_maxrate(struct net_device *dev,
1439 struct mlx5e_sq *sq, u32 rate)
1441 struct mlx5e_priv *priv = netdev_priv(dev);
1442 struct mlx5_core_dev *mdev = priv->mdev;
1446 if (rate == sq->rate_limit)
1451 /* remove current rl index to free space to next ones */
1452 mlx5_rl_remove_rate(mdev, sq->rate_limit);
1457 err = mlx5_rl_add_rate(mdev, rate, &rl_index);
1459 netdev_err(dev, "Failed configuring rate %u: %d\n",
1465 err = mlx5e_modify_sq(sq, MLX5_SQC_STATE_RDY,
1466 MLX5_SQC_STATE_RDY, true, rl_index);
1468 netdev_err(dev, "Failed configuring rate %u: %d\n",
1470 /* remove the rate from the table */
1472 mlx5_rl_remove_rate(mdev, rate);
1476 sq->rate_limit = rate;
1480 static int mlx5e_set_tx_maxrate(struct net_device *dev, int index, u32 rate)
1482 struct mlx5e_priv *priv = netdev_priv(dev);
1483 struct mlx5_core_dev *mdev = priv->mdev;
1484 struct mlx5e_sq *sq = priv->txq_to_sq_map[index];
1487 if (!mlx5_rl_is_supported(mdev)) {
1488 netdev_err(dev, "Rate limiting is not supported on this device\n");
1492 /* rate is given in Mb/sec, HW config is in Kb/sec */
1495 /* Check whether rate in valid range, 0 is always valid */
1496 if (rate && !mlx5_rl_is_in_range(mdev, rate)) {
1497 netdev_err(dev, "TX rate %u, is not in range\n", rate);
1501 mutex_lock(&priv->state_lock);
1502 if (test_bit(MLX5E_STATE_OPENED, &priv->state))
1503 err = mlx5e_set_sq_maxrate(dev, sq, rate);
1505 priv->tx_rates[index] = rate;
1506 mutex_unlock(&priv->state_lock);
1511 static int mlx5e_open_channel(struct mlx5e_priv *priv, int ix,
1512 struct mlx5e_channel_param *cparam,
1513 struct mlx5e_channel **cp)
1515 struct mlx5e_cq_moder icosq_cq_moder = {0, 0};
1516 struct net_device *netdev = priv->netdev;
1517 struct mlx5e_cq_moder rx_cq_profile;
1518 int cpu = mlx5e_get_cpu(priv, ix);
1519 struct mlx5e_channel *c;
1520 struct mlx5e_sq *sq;
1524 c = kzalloc_node(sizeof(*c), GFP_KERNEL, cpu_to_node(cpu));
1531 c->pdev = &priv->mdev->pdev->dev;
1532 c->netdev = priv->netdev;
1533 c->mkey_be = cpu_to_be32(priv->mdev->mlx5e_res.mkey.key);
1534 c->num_tc = priv->params.num_tc;
1535 c->xdp = !!priv->xdp_prog;
1537 if (priv->params.rx_am_enabled)
1538 rx_cq_profile = mlx5e_am_get_def_profile(priv->params.rx_cq_period_mode);
1540 rx_cq_profile = priv->params.rx_cq_moderation;
1542 mlx5e_build_channeltc_to_txq_map(priv, ix);
1544 netif_napi_add(netdev, &c->napi, mlx5e_napi_poll, 64);
1546 err = mlx5e_open_cq(c, &cparam->icosq_cq, &c->icosq.cq, icosq_cq_moder);
1550 err = mlx5e_open_tx_cqs(c, cparam);
1552 goto err_close_icosq_cq;
1554 err = mlx5e_open_cq(c, &cparam->rx_cq, &c->rq.cq,
1557 goto err_close_tx_cqs;
1559 /* XDP SQ CQ params are same as normal TXQ sq CQ params */
1560 err = c->xdp ? mlx5e_open_cq(c, &cparam->tx_cq, &c->xdp_sq.cq,
1561 priv->params.tx_cq_moderation) : 0;
1563 goto err_close_rx_cq;
1565 napi_enable(&c->napi);
1567 err = mlx5e_open_sq(c, 0, &cparam->icosq, &c->icosq);
1569 goto err_disable_napi;
1571 err = mlx5e_open_sqs(c, cparam);
1573 goto err_close_icosq;
1575 for (i = 0; i < priv->params.num_tc; i++) {
1576 u32 txq_ix = priv->channeltc_to_txq_map[ix][i];
1578 if (priv->tx_rates[txq_ix]) {
1579 sq = priv->txq_to_sq_map[txq_ix];
1580 mlx5e_set_sq_maxrate(priv->netdev, sq,
1581 priv->tx_rates[txq_ix]);
1585 err = c->xdp ? mlx5e_open_sq(c, 0, &cparam->xdp_sq, &c->xdp_sq) : 0;
1589 err = mlx5e_open_rq(c, &cparam->rq, &c->rq);
1591 goto err_close_xdp_sq;
1593 netif_set_xps_queue(netdev, get_cpu_mask(c->cpu), ix);
1599 mlx5e_close_sq(&c->xdp_sq);
1605 mlx5e_close_sq(&c->icosq);
1608 napi_disable(&c->napi);
1610 mlx5e_close_cq(&c->xdp_sq.cq);
1613 mlx5e_close_cq(&c->rq.cq);
1616 mlx5e_close_tx_cqs(c);
1619 mlx5e_close_cq(&c->icosq.cq);
1622 netif_napi_del(&c->napi);
1628 static void mlx5e_close_channel(struct mlx5e_channel *c)
1630 mlx5e_close_rq(&c->rq);
1632 mlx5e_close_sq(&c->xdp_sq);
1634 mlx5e_close_sq(&c->icosq);
1635 napi_disable(&c->napi);
1637 mlx5e_close_cq(&c->xdp_sq.cq);
1638 mlx5e_close_cq(&c->rq.cq);
1639 mlx5e_close_tx_cqs(c);
1640 mlx5e_close_cq(&c->icosq.cq);
1641 netif_napi_del(&c->napi);
1646 static void mlx5e_build_rq_param(struct mlx5e_priv *priv,
1647 struct mlx5e_rq_param *param)
1649 void *rqc = param->rqc;
1650 void *wq = MLX5_ADDR_OF(rqc, rqc, wq);
1652 switch (priv->params.rq_wq_type) {
1653 case MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ:
1654 MLX5_SET(wq, wq, log_wqe_num_of_strides,
1655 priv->params.mpwqe_log_num_strides - 9);
1656 MLX5_SET(wq, wq, log_wqe_stride_size,
1657 priv->params.mpwqe_log_stride_sz - 6);
1658 MLX5_SET(wq, wq, wq_type, MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ);
1660 default: /* MLX5_WQ_TYPE_LINKED_LIST */
1661 MLX5_SET(wq, wq, wq_type, MLX5_WQ_TYPE_LINKED_LIST);
1664 MLX5_SET(wq, wq, end_padding_mode, MLX5_WQ_END_PAD_MODE_ALIGN);
1665 MLX5_SET(wq, wq, log_wq_stride, ilog2(sizeof(struct mlx5e_rx_wqe)));
1666 MLX5_SET(wq, wq, log_wq_sz, priv->params.log_rq_size);
1667 MLX5_SET(wq, wq, pd, priv->mdev->mlx5e_res.pdn);
1668 MLX5_SET(rqc, rqc, counter_set_id, priv->q_counter);
1670 param->wq.buf_numa_node = dev_to_node(&priv->mdev->pdev->dev);
1671 param->wq.linear = 1;
1673 param->am_enabled = priv->params.rx_am_enabled;
1676 static void mlx5e_build_drop_rq_param(struct mlx5e_rq_param *param)
1678 void *rqc = param->rqc;
1679 void *wq = MLX5_ADDR_OF(rqc, rqc, wq);
1681 MLX5_SET(wq, wq, wq_type, MLX5_WQ_TYPE_LINKED_LIST);
1682 MLX5_SET(wq, wq, log_wq_stride, ilog2(sizeof(struct mlx5e_rx_wqe)));
1685 static void mlx5e_build_sq_param_common(struct mlx5e_priv *priv,
1686 struct mlx5e_sq_param *param)
1688 void *sqc = param->sqc;
1689 void *wq = MLX5_ADDR_OF(sqc, sqc, wq);
1691 MLX5_SET(wq, wq, log_wq_stride, ilog2(MLX5_SEND_WQE_BB));
1692 MLX5_SET(wq, wq, pd, priv->mdev->mlx5e_res.pdn);
1694 param->wq.buf_numa_node = dev_to_node(&priv->mdev->pdev->dev);
1697 static void mlx5e_build_sq_param(struct mlx5e_priv *priv,
1698 struct mlx5e_sq_param *param)
1700 void *sqc = param->sqc;
1701 void *wq = MLX5_ADDR_OF(sqc, sqc, wq);
1703 mlx5e_build_sq_param_common(priv, param);
1704 MLX5_SET(wq, wq, log_wq_sz, priv->params.log_sq_size);
1706 param->max_inline = priv->params.tx_max_inline;
1707 param->min_inline_mode = priv->params.tx_min_inline_mode;
1708 param->type = MLX5E_SQ_TXQ;
1711 static void mlx5e_build_common_cq_param(struct mlx5e_priv *priv,
1712 struct mlx5e_cq_param *param)
1714 void *cqc = param->cqc;
1716 MLX5_SET(cqc, cqc, uar_page, priv->mdev->priv.uar->index);
1719 static void mlx5e_build_rx_cq_param(struct mlx5e_priv *priv,
1720 struct mlx5e_cq_param *param)
1722 void *cqc = param->cqc;
1725 switch (priv->params.rq_wq_type) {
1726 case MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ:
1727 log_cq_size = priv->params.log_rq_size +
1728 priv->params.mpwqe_log_num_strides;
1730 default: /* MLX5_WQ_TYPE_LINKED_LIST */
1731 log_cq_size = priv->params.log_rq_size;
1734 MLX5_SET(cqc, cqc, log_cq_size, log_cq_size);
1735 if (MLX5E_GET_PFLAG(priv, MLX5E_PFLAG_RX_CQE_COMPRESS)) {
1736 MLX5_SET(cqc, cqc, mini_cqe_res_format, MLX5_CQE_FORMAT_CSUM);
1737 MLX5_SET(cqc, cqc, cqe_comp_en, 1);
1740 mlx5e_build_common_cq_param(priv, param);
1742 param->cq_period_mode = priv->params.rx_cq_period_mode;
1745 static void mlx5e_build_tx_cq_param(struct mlx5e_priv *priv,
1746 struct mlx5e_cq_param *param)
1748 void *cqc = param->cqc;
1750 MLX5_SET(cqc, cqc, log_cq_size, priv->params.log_sq_size);
1752 mlx5e_build_common_cq_param(priv, param);
1754 param->cq_period_mode = MLX5_CQ_PERIOD_MODE_START_FROM_EQE;
1757 static void mlx5e_build_ico_cq_param(struct mlx5e_priv *priv,
1758 struct mlx5e_cq_param *param,
1761 void *cqc = param->cqc;
1763 MLX5_SET(cqc, cqc, log_cq_size, log_wq_size);
1765 mlx5e_build_common_cq_param(priv, param);
1767 param->cq_period_mode = MLX5_CQ_PERIOD_MODE_START_FROM_EQE;
1770 static void mlx5e_build_icosq_param(struct mlx5e_priv *priv,
1771 struct mlx5e_sq_param *param,
1774 void *sqc = param->sqc;
1775 void *wq = MLX5_ADDR_OF(sqc, sqc, wq);
1777 mlx5e_build_sq_param_common(priv, param);
1779 MLX5_SET(wq, wq, log_wq_sz, log_wq_size);
1780 MLX5_SET(sqc, sqc, reg_umr, MLX5_CAP_ETH(priv->mdev, reg_umr_sq));
1782 param->type = MLX5E_SQ_ICO;
1785 static void mlx5e_build_xdpsq_param(struct mlx5e_priv *priv,
1786 struct mlx5e_sq_param *param)
1788 void *sqc = param->sqc;
1789 void *wq = MLX5_ADDR_OF(sqc, sqc, wq);
1791 mlx5e_build_sq_param_common(priv, param);
1792 MLX5_SET(wq, wq, log_wq_sz, priv->params.log_sq_size);
1794 param->max_inline = priv->params.tx_max_inline;
1795 /* FOR XDP SQs will support only L2 inline mode */
1796 param->min_inline_mode = MLX5_INLINE_MODE_NONE;
1797 param->type = MLX5E_SQ_XDP;
1800 static void mlx5e_build_channel_param(struct mlx5e_priv *priv, struct mlx5e_channel_param *cparam)
1802 u8 icosq_log_wq_sz = MLX5E_PARAMS_MINIMUM_LOG_SQ_SIZE;
1804 mlx5e_build_rq_param(priv, &cparam->rq);
1805 mlx5e_build_sq_param(priv, &cparam->sq);
1806 mlx5e_build_xdpsq_param(priv, &cparam->xdp_sq);
1807 mlx5e_build_icosq_param(priv, &cparam->icosq, icosq_log_wq_sz);
1808 mlx5e_build_rx_cq_param(priv, &cparam->rx_cq);
1809 mlx5e_build_tx_cq_param(priv, &cparam->tx_cq);
1810 mlx5e_build_ico_cq_param(priv, &cparam->icosq_cq, icosq_log_wq_sz);
1813 static int mlx5e_open_channels(struct mlx5e_priv *priv)
1815 struct mlx5e_channel_param *cparam;
1816 int nch = priv->params.num_channels;
1821 priv->channel = kcalloc(nch, sizeof(struct mlx5e_channel *),
1824 priv->txq_to_sq_map = kcalloc(nch * priv->params.num_tc,
1825 sizeof(struct mlx5e_sq *), GFP_KERNEL);
1827 cparam = kzalloc(sizeof(struct mlx5e_channel_param), GFP_KERNEL);
1829 if (!priv->channel || !priv->txq_to_sq_map || !cparam)
1830 goto err_free_txq_to_sq_map;
1832 mlx5e_build_channel_param(priv, cparam);
1834 for (i = 0; i < nch; i++) {
1835 err = mlx5e_open_channel(priv, i, cparam, &priv->channel[i]);
1837 goto err_close_channels;
1840 for (j = 0; j < nch; j++) {
1841 err = mlx5e_wait_for_min_rx_wqes(&priv->channel[j]->rq);
1843 goto err_close_channels;
1846 /* FIXME: This is a W/A for tx timeout watch dog false alarm when
1847 * polling for inactive tx queues.
1849 netif_tx_start_all_queues(priv->netdev);
1855 for (i--; i >= 0; i--)
1856 mlx5e_close_channel(priv->channel[i]);
1858 err_free_txq_to_sq_map:
1859 kfree(priv->txq_to_sq_map);
1860 kfree(priv->channel);
1866 static void mlx5e_close_channels(struct mlx5e_priv *priv)
1870 /* FIXME: This is a W/A only for tx timeout watch dog false alarm when
1871 * polling for inactive tx queues.
1873 netif_tx_stop_all_queues(priv->netdev);
1874 netif_tx_disable(priv->netdev);
1876 for (i = 0; i < priv->params.num_channels; i++)
1877 mlx5e_close_channel(priv->channel[i]);
1879 kfree(priv->txq_to_sq_map);
1880 kfree(priv->channel);
1883 static int mlx5e_rx_hash_fn(int hfunc)
1885 return (hfunc == ETH_RSS_HASH_TOP) ?
1886 MLX5_RX_HASH_FN_TOEPLITZ :
1887 MLX5_RX_HASH_FN_INVERTED_XOR8;
1890 static int mlx5e_bits_invert(unsigned long a, int size)
1895 for (i = 0; i < size; i++)
1896 inv |= (test_bit(size - i - 1, &a) ? 1 : 0) << i;
1901 static void mlx5e_fill_indir_rqt_rqns(struct mlx5e_priv *priv, void *rqtc)
1905 for (i = 0; i < MLX5E_INDIR_RQT_SIZE; i++) {
1909 if (priv->params.rss_hfunc == ETH_RSS_HASH_XOR)
1910 ix = mlx5e_bits_invert(i, MLX5E_LOG_INDIR_RQT_SIZE);
1912 ix = priv->params.indirection_rqt[ix];
1913 rqn = test_bit(MLX5E_STATE_OPENED, &priv->state) ?
1914 priv->channel[ix]->rq.rqn :
1916 MLX5_SET(rqtc, rqtc, rq_num[i], rqn);
1920 static void mlx5e_fill_direct_rqt_rqn(struct mlx5e_priv *priv, void *rqtc,
1923 u32 rqn = test_bit(MLX5E_STATE_OPENED, &priv->state) ?
1924 priv->channel[ix]->rq.rqn :
1927 MLX5_SET(rqtc, rqtc, rq_num[0], rqn);
1930 static int mlx5e_create_rqt(struct mlx5e_priv *priv, int sz,
1931 int ix, struct mlx5e_rqt *rqt)
1933 struct mlx5_core_dev *mdev = priv->mdev;
1939 inlen = MLX5_ST_SZ_BYTES(create_rqt_in) + sizeof(u32) * sz;
1940 in = mlx5_vzalloc(inlen);
1944 rqtc = MLX5_ADDR_OF(create_rqt_in, in, rqt_context);
1946 MLX5_SET(rqtc, rqtc, rqt_actual_size, sz);
1947 MLX5_SET(rqtc, rqtc, rqt_max_size, sz);
1949 if (sz > 1) /* RSS */
1950 mlx5e_fill_indir_rqt_rqns(priv, rqtc);
1952 mlx5e_fill_direct_rqt_rqn(priv, rqtc, ix);
1954 err = mlx5_core_create_rqt(mdev, in, inlen, &rqt->rqtn);
1956 rqt->enabled = true;
1962 void mlx5e_destroy_rqt(struct mlx5e_priv *priv, struct mlx5e_rqt *rqt)
1964 rqt->enabled = false;
1965 mlx5_core_destroy_rqt(priv->mdev, rqt->rqtn);
1968 static int mlx5e_create_indirect_rqts(struct mlx5e_priv *priv)
1970 struct mlx5e_rqt *rqt = &priv->indir_rqt;
1972 return mlx5e_create_rqt(priv, MLX5E_INDIR_RQT_SIZE, 0, rqt);
1975 int mlx5e_create_direct_rqts(struct mlx5e_priv *priv)
1977 struct mlx5e_rqt *rqt;
1981 for (ix = 0; ix < priv->profile->max_nch(priv->mdev); ix++) {
1982 rqt = &priv->direct_tir[ix].rqt;
1983 err = mlx5e_create_rqt(priv, 1 /*size */, ix, rqt);
1985 goto err_destroy_rqts;
1991 for (ix--; ix >= 0; ix--)
1992 mlx5e_destroy_rqt(priv, &priv->direct_tir[ix].rqt);
1997 int mlx5e_redirect_rqt(struct mlx5e_priv *priv, u32 rqtn, int sz, int ix)
1999 struct mlx5_core_dev *mdev = priv->mdev;
2005 inlen = MLX5_ST_SZ_BYTES(modify_rqt_in) + sizeof(u32) * sz;
2006 in = mlx5_vzalloc(inlen);
2010 rqtc = MLX5_ADDR_OF(modify_rqt_in, in, ctx);
2012 MLX5_SET(rqtc, rqtc, rqt_actual_size, sz);
2013 if (sz > 1) /* RSS */
2014 mlx5e_fill_indir_rqt_rqns(priv, rqtc);
2016 mlx5e_fill_direct_rqt_rqn(priv, rqtc, ix);
2018 MLX5_SET(modify_rqt_in, in, bitmask.rqn_list, 1);
2020 err = mlx5_core_modify_rqt(mdev, rqtn, in, inlen);
2027 static void mlx5e_redirect_rqts(struct mlx5e_priv *priv)
2032 if (priv->indir_rqt.enabled) {
2033 rqtn = priv->indir_rqt.rqtn;
2034 mlx5e_redirect_rqt(priv, rqtn, MLX5E_INDIR_RQT_SIZE, 0);
2037 for (ix = 0; ix < priv->params.num_channels; ix++) {
2038 if (!priv->direct_tir[ix].rqt.enabled)
2040 rqtn = priv->direct_tir[ix].rqt.rqtn;
2041 mlx5e_redirect_rqt(priv, rqtn, 1, ix);
2045 static void mlx5e_build_tir_ctx_lro(void *tirc, struct mlx5e_priv *priv)
2047 if (!priv->params.lro_en)
2050 #define ROUGH_MAX_L2_L3_HDR_SZ 256
2052 MLX5_SET(tirc, tirc, lro_enable_mask,
2053 MLX5_TIRC_LRO_ENABLE_MASK_IPV4_LRO |
2054 MLX5_TIRC_LRO_ENABLE_MASK_IPV6_LRO);
2055 MLX5_SET(tirc, tirc, lro_max_ip_payload_size,
2056 (priv->params.lro_wqe_sz -
2057 ROUGH_MAX_L2_L3_HDR_SZ) >> 8);
2058 MLX5_SET(tirc, tirc, lro_timeout_period_usecs, priv->params.lro_timeout);
2061 void mlx5e_build_tir_ctx_hash(void *tirc, struct mlx5e_priv *priv)
2063 MLX5_SET(tirc, tirc, rx_hash_fn,
2064 mlx5e_rx_hash_fn(priv->params.rss_hfunc));
2065 if (priv->params.rss_hfunc == ETH_RSS_HASH_TOP) {
2066 void *rss_key = MLX5_ADDR_OF(tirc, tirc,
2067 rx_hash_toeplitz_key);
2068 size_t len = MLX5_FLD_SZ_BYTES(tirc,
2069 rx_hash_toeplitz_key);
2071 MLX5_SET(tirc, tirc, rx_hash_symmetric, 1);
2072 memcpy(rss_key, priv->params.toeplitz_hash_key, len);
2076 static int mlx5e_modify_tirs_lro(struct mlx5e_priv *priv)
2078 struct mlx5_core_dev *mdev = priv->mdev;
2087 inlen = MLX5_ST_SZ_BYTES(modify_tir_in);
2088 in = mlx5_vzalloc(inlen);
2092 MLX5_SET(modify_tir_in, in, bitmask.lro, 1);
2093 tirc = MLX5_ADDR_OF(modify_tir_in, in, ctx);
2095 mlx5e_build_tir_ctx_lro(tirc, priv);
2097 for (tt = 0; tt < MLX5E_NUM_INDIR_TIRS; tt++) {
2098 err = mlx5_core_modify_tir(mdev, priv->indir_tir[tt].tirn, in,
2104 for (ix = 0; ix < priv->profile->max_nch(priv->mdev); ix++) {
2105 err = mlx5_core_modify_tir(mdev, priv->direct_tir[ix].tirn,
2117 static int mlx5e_set_mtu(struct mlx5e_priv *priv, u16 mtu)
2119 struct mlx5_core_dev *mdev = priv->mdev;
2120 u16 hw_mtu = MLX5E_SW2HW_MTU(mtu);
2123 err = mlx5_set_port_mtu(mdev, hw_mtu, 1);
2127 /* Update vport context MTU */
2128 mlx5_modify_nic_vport_mtu(mdev, hw_mtu);
2132 static void mlx5e_query_mtu(struct mlx5e_priv *priv, u16 *mtu)
2134 struct mlx5_core_dev *mdev = priv->mdev;
2138 err = mlx5_query_nic_vport_mtu(mdev, &hw_mtu);
2139 if (err || !hw_mtu) /* fallback to port oper mtu */
2140 mlx5_query_port_oper_mtu(mdev, &hw_mtu, 1);
2142 *mtu = MLX5E_HW2SW_MTU(hw_mtu);
2145 static int mlx5e_set_dev_port_mtu(struct net_device *netdev)
2147 struct mlx5e_priv *priv = netdev_priv(netdev);
2151 err = mlx5e_set_mtu(priv, netdev->mtu);
2155 mlx5e_query_mtu(priv, &mtu);
2156 if (mtu != netdev->mtu)
2157 netdev_warn(netdev, "%s: VPort MTU %d is different than netdev mtu %d\n",
2158 __func__, mtu, netdev->mtu);
2164 static void mlx5e_netdev_set_tcs(struct net_device *netdev)
2166 struct mlx5e_priv *priv = netdev_priv(netdev);
2167 int nch = priv->params.num_channels;
2168 int ntc = priv->params.num_tc;
2171 netdev_reset_tc(netdev);
2176 netdev_set_num_tc(netdev, ntc);
2178 /* Map netdev TCs to offset 0
2179 * We have our own UP to TXQ mapping for QoS
2181 for (tc = 0; tc < ntc; tc++)
2182 netdev_set_tc_queue(netdev, tc, nch, 0);
2185 int mlx5e_open_locked(struct net_device *netdev)
2187 struct mlx5e_priv *priv = netdev_priv(netdev);
2188 struct mlx5_core_dev *mdev = priv->mdev;
2192 set_bit(MLX5E_STATE_OPENED, &priv->state);
2194 mlx5e_netdev_set_tcs(netdev);
2196 num_txqs = priv->params.num_channels * priv->params.num_tc;
2197 netif_set_real_num_tx_queues(netdev, num_txqs);
2198 netif_set_real_num_rx_queues(netdev, priv->params.num_channels);
2200 err = mlx5e_open_channels(priv);
2202 netdev_err(netdev, "%s: mlx5e_open_channels failed, %d\n",
2204 goto err_clear_state_opened_flag;
2207 err = mlx5e_refresh_tirs_self_loopback(priv->mdev, false);
2209 netdev_err(netdev, "%s: mlx5e_refresh_tirs_self_loopback_enable failed, %d\n",
2211 goto err_close_channels;
2214 mlx5e_redirect_rqts(priv);
2215 mlx5e_update_carrier(priv);
2216 mlx5e_timestamp_init(priv);
2217 #ifdef CONFIG_RFS_ACCEL
2218 priv->netdev->rx_cpu_rmap = priv->mdev->rmap;
2220 if (priv->profile->update_stats)
2221 queue_delayed_work(priv->wq, &priv->update_stats_work, 0);
2223 if (MLX5_CAP_GEN(mdev, vport_group_manager)) {
2224 err = mlx5e_add_sqs_fwd_rules(priv);
2226 goto err_close_channels;
2231 mlx5e_close_channels(priv);
2232 err_clear_state_opened_flag:
2233 clear_bit(MLX5E_STATE_OPENED, &priv->state);
2237 int mlx5e_open(struct net_device *netdev)
2239 struct mlx5e_priv *priv = netdev_priv(netdev);
2242 mutex_lock(&priv->state_lock);
2243 err = mlx5e_open_locked(netdev);
2244 mutex_unlock(&priv->state_lock);
2249 int mlx5e_close_locked(struct net_device *netdev)
2251 struct mlx5e_priv *priv = netdev_priv(netdev);
2252 struct mlx5_core_dev *mdev = priv->mdev;
2254 /* May already be CLOSED in case a previous configuration operation
2255 * (e.g RX/TX queue size change) that involves close&open failed.
2257 if (!test_bit(MLX5E_STATE_OPENED, &priv->state))
2260 clear_bit(MLX5E_STATE_OPENED, &priv->state);
2262 if (MLX5_CAP_GEN(mdev, vport_group_manager))
2263 mlx5e_remove_sqs_fwd_rules(priv);
2265 mlx5e_timestamp_cleanup(priv);
2266 netif_carrier_off(priv->netdev);
2267 mlx5e_redirect_rqts(priv);
2268 mlx5e_close_channels(priv);
2273 int mlx5e_close(struct net_device *netdev)
2275 struct mlx5e_priv *priv = netdev_priv(netdev);
2278 if (!netif_device_present(netdev))
2281 mutex_lock(&priv->state_lock);
2282 err = mlx5e_close_locked(netdev);
2283 mutex_unlock(&priv->state_lock);
2288 static int mlx5e_create_drop_rq(struct mlx5e_priv *priv,
2289 struct mlx5e_rq *rq,
2290 struct mlx5e_rq_param *param)
2292 struct mlx5_core_dev *mdev = priv->mdev;
2293 void *rqc = param->rqc;
2294 void *rqc_wq = MLX5_ADDR_OF(rqc, rqc, wq);
2297 param->wq.db_numa_node = param->wq.buf_numa_node;
2299 err = mlx5_wq_ll_create(mdev, ¶m->wq, rqc_wq, &rq->wq,
2309 static int mlx5e_create_drop_cq(struct mlx5e_priv *priv,
2310 struct mlx5e_cq *cq,
2311 struct mlx5e_cq_param *param)
2313 struct mlx5_core_dev *mdev = priv->mdev;
2314 struct mlx5_core_cq *mcq = &cq->mcq;
2319 err = mlx5_cqwq_create(mdev, ¶m->wq, param->cqc, &cq->wq,
2324 mlx5_vector2eqn(mdev, param->eq_ix, &eqn_not_used, &irqn);
2327 mcq->set_ci_db = cq->wq_ctrl.db.db;
2328 mcq->arm_db = cq->wq_ctrl.db.db + 1;
2329 *mcq->set_ci_db = 0;
2331 mcq->vector = param->eq_ix;
2332 mcq->comp = mlx5e_completion_event;
2333 mcq->event = mlx5e_cq_error_event;
2341 static int mlx5e_open_drop_rq(struct mlx5e_priv *priv)
2343 struct mlx5e_cq_param cq_param;
2344 struct mlx5e_rq_param rq_param;
2345 struct mlx5e_rq *rq = &priv->drop_rq;
2346 struct mlx5e_cq *cq = &priv->drop_rq.cq;
2349 memset(&cq_param, 0, sizeof(cq_param));
2350 memset(&rq_param, 0, sizeof(rq_param));
2351 mlx5e_build_drop_rq_param(&rq_param);
2353 err = mlx5e_create_drop_cq(priv, cq, &cq_param);
2357 err = mlx5e_enable_cq(cq, &cq_param);
2359 goto err_destroy_cq;
2361 err = mlx5e_create_drop_rq(priv, rq, &rq_param);
2363 goto err_disable_cq;
2365 err = mlx5e_enable_rq(rq, &rq_param);
2367 goto err_destroy_rq;
2372 mlx5e_destroy_rq(&priv->drop_rq);
2375 mlx5e_disable_cq(&priv->drop_rq.cq);
2378 mlx5e_destroy_cq(&priv->drop_rq.cq);
2383 static void mlx5e_close_drop_rq(struct mlx5e_priv *priv)
2385 mlx5e_disable_rq(&priv->drop_rq);
2386 mlx5e_destroy_rq(&priv->drop_rq);
2387 mlx5e_disable_cq(&priv->drop_rq.cq);
2388 mlx5e_destroy_cq(&priv->drop_rq.cq);
2391 static int mlx5e_create_tis(struct mlx5e_priv *priv, int tc)
2393 struct mlx5_core_dev *mdev = priv->mdev;
2394 u32 in[MLX5_ST_SZ_DW(create_tis_in)] = {0};
2395 void *tisc = MLX5_ADDR_OF(create_tis_in, in, ctx);
2397 MLX5_SET(tisc, tisc, prio, tc << 1);
2398 MLX5_SET(tisc, tisc, transport_domain, mdev->mlx5e_res.td.tdn);
2400 if (mlx5_lag_is_lacp_owner(mdev))
2401 MLX5_SET(tisc, tisc, strict_lag_tx_port_affinity, 1);
2403 return mlx5_core_create_tis(mdev, in, sizeof(in), &priv->tisn[tc]);
2406 static void mlx5e_destroy_tis(struct mlx5e_priv *priv, int tc)
2408 mlx5_core_destroy_tis(priv->mdev, priv->tisn[tc]);
2411 int mlx5e_create_tises(struct mlx5e_priv *priv)
2416 for (tc = 0; tc < priv->profile->max_tc; tc++) {
2417 err = mlx5e_create_tis(priv, tc);
2419 goto err_close_tises;
2425 for (tc--; tc >= 0; tc--)
2426 mlx5e_destroy_tis(priv, tc);
2431 void mlx5e_cleanup_nic_tx(struct mlx5e_priv *priv)
2435 for (tc = 0; tc < priv->profile->max_tc; tc++)
2436 mlx5e_destroy_tis(priv, tc);
2439 static void mlx5e_build_indir_tir_ctx(struct mlx5e_priv *priv, u32 *tirc,
2440 enum mlx5e_traffic_types tt)
2442 void *hfso = MLX5_ADDR_OF(tirc, tirc, rx_hash_field_selector_outer);
2444 MLX5_SET(tirc, tirc, transport_domain, priv->mdev->mlx5e_res.td.tdn);
2446 #define MLX5_HASH_IP (MLX5_HASH_FIELD_SEL_SRC_IP |\
2447 MLX5_HASH_FIELD_SEL_DST_IP)
2449 #define MLX5_HASH_IP_L4PORTS (MLX5_HASH_FIELD_SEL_SRC_IP |\
2450 MLX5_HASH_FIELD_SEL_DST_IP |\
2451 MLX5_HASH_FIELD_SEL_L4_SPORT |\
2452 MLX5_HASH_FIELD_SEL_L4_DPORT)
2454 #define MLX5_HASH_IP_IPSEC_SPI (MLX5_HASH_FIELD_SEL_SRC_IP |\
2455 MLX5_HASH_FIELD_SEL_DST_IP |\
2456 MLX5_HASH_FIELD_SEL_IPSEC_SPI)
2458 mlx5e_build_tir_ctx_lro(tirc, priv);
2460 MLX5_SET(tirc, tirc, disp_type, MLX5_TIRC_DISP_TYPE_INDIRECT);
2461 MLX5_SET(tirc, tirc, indirect_table, priv->indir_rqt.rqtn);
2462 mlx5e_build_tir_ctx_hash(tirc, priv);
2465 case MLX5E_TT_IPV4_TCP:
2466 MLX5_SET(rx_hash_field_select, hfso, l3_prot_type,
2467 MLX5_L3_PROT_TYPE_IPV4);
2468 MLX5_SET(rx_hash_field_select, hfso, l4_prot_type,
2469 MLX5_L4_PROT_TYPE_TCP);
2470 MLX5_SET(rx_hash_field_select, hfso, selected_fields,
2471 MLX5_HASH_IP_L4PORTS);
2474 case MLX5E_TT_IPV6_TCP:
2475 MLX5_SET(rx_hash_field_select, hfso, l3_prot_type,
2476 MLX5_L3_PROT_TYPE_IPV6);
2477 MLX5_SET(rx_hash_field_select, hfso, l4_prot_type,
2478 MLX5_L4_PROT_TYPE_TCP);
2479 MLX5_SET(rx_hash_field_select, hfso, selected_fields,
2480 MLX5_HASH_IP_L4PORTS);
2483 case MLX5E_TT_IPV4_UDP:
2484 MLX5_SET(rx_hash_field_select, hfso, l3_prot_type,
2485 MLX5_L3_PROT_TYPE_IPV4);
2486 MLX5_SET(rx_hash_field_select, hfso, l4_prot_type,
2487 MLX5_L4_PROT_TYPE_UDP);
2488 MLX5_SET(rx_hash_field_select, hfso, selected_fields,
2489 MLX5_HASH_IP_L4PORTS);
2492 case MLX5E_TT_IPV6_UDP:
2493 MLX5_SET(rx_hash_field_select, hfso, l3_prot_type,
2494 MLX5_L3_PROT_TYPE_IPV6);
2495 MLX5_SET(rx_hash_field_select, hfso, l4_prot_type,
2496 MLX5_L4_PROT_TYPE_UDP);
2497 MLX5_SET(rx_hash_field_select, hfso, selected_fields,
2498 MLX5_HASH_IP_L4PORTS);
2501 case MLX5E_TT_IPV4_IPSEC_AH:
2502 MLX5_SET(rx_hash_field_select, hfso, l3_prot_type,
2503 MLX5_L3_PROT_TYPE_IPV4);
2504 MLX5_SET(rx_hash_field_select, hfso, selected_fields,
2505 MLX5_HASH_IP_IPSEC_SPI);
2508 case MLX5E_TT_IPV6_IPSEC_AH:
2509 MLX5_SET(rx_hash_field_select, hfso, l3_prot_type,
2510 MLX5_L3_PROT_TYPE_IPV6);
2511 MLX5_SET(rx_hash_field_select, hfso, selected_fields,
2512 MLX5_HASH_IP_IPSEC_SPI);
2515 case MLX5E_TT_IPV4_IPSEC_ESP:
2516 MLX5_SET(rx_hash_field_select, hfso, l3_prot_type,
2517 MLX5_L3_PROT_TYPE_IPV4);
2518 MLX5_SET(rx_hash_field_select, hfso, selected_fields,
2519 MLX5_HASH_IP_IPSEC_SPI);
2522 case MLX5E_TT_IPV6_IPSEC_ESP:
2523 MLX5_SET(rx_hash_field_select, hfso, l3_prot_type,
2524 MLX5_L3_PROT_TYPE_IPV6);
2525 MLX5_SET(rx_hash_field_select, hfso, selected_fields,
2526 MLX5_HASH_IP_IPSEC_SPI);
2530 MLX5_SET(rx_hash_field_select, hfso, l3_prot_type,
2531 MLX5_L3_PROT_TYPE_IPV4);
2532 MLX5_SET(rx_hash_field_select, hfso, selected_fields,
2537 MLX5_SET(rx_hash_field_select, hfso, l3_prot_type,
2538 MLX5_L3_PROT_TYPE_IPV6);
2539 MLX5_SET(rx_hash_field_select, hfso, selected_fields,
2544 "mlx5e_build_indir_tir_ctx: bad traffic type!\n");
2548 static void mlx5e_build_direct_tir_ctx(struct mlx5e_priv *priv, u32 *tirc,
2551 MLX5_SET(tirc, tirc, transport_domain, priv->mdev->mlx5e_res.td.tdn);
2553 mlx5e_build_tir_ctx_lro(tirc, priv);
2555 MLX5_SET(tirc, tirc, disp_type, MLX5_TIRC_DISP_TYPE_INDIRECT);
2556 MLX5_SET(tirc, tirc, indirect_table, rqtn);
2557 MLX5_SET(tirc, tirc, rx_hash_fn, MLX5_RX_HASH_FN_INVERTED_XOR8);
2560 static int mlx5e_create_indirect_tirs(struct mlx5e_priv *priv)
2562 struct mlx5e_tir *tir;
2569 inlen = MLX5_ST_SZ_BYTES(create_tir_in);
2570 in = mlx5_vzalloc(inlen);
2574 for (tt = 0; tt < MLX5E_NUM_INDIR_TIRS; tt++) {
2575 memset(in, 0, inlen);
2576 tir = &priv->indir_tir[tt];
2577 tirc = MLX5_ADDR_OF(create_tir_in, in, ctx);
2578 mlx5e_build_indir_tir_ctx(priv, tirc, tt);
2579 err = mlx5e_create_tir(priv->mdev, tir, in, inlen);
2581 goto err_destroy_tirs;
2589 for (tt--; tt >= 0; tt--)
2590 mlx5e_destroy_tir(priv->mdev, &priv->indir_tir[tt]);
2597 int mlx5e_create_direct_tirs(struct mlx5e_priv *priv)
2599 int nch = priv->profile->max_nch(priv->mdev);
2600 struct mlx5e_tir *tir;
2607 inlen = MLX5_ST_SZ_BYTES(create_tir_in);
2608 in = mlx5_vzalloc(inlen);
2612 for (ix = 0; ix < nch; ix++) {
2613 memset(in, 0, inlen);
2614 tir = &priv->direct_tir[ix];
2615 tirc = MLX5_ADDR_OF(create_tir_in, in, ctx);
2616 mlx5e_build_direct_tir_ctx(priv, tirc,
2617 priv->direct_tir[ix].rqt.rqtn);
2618 err = mlx5e_create_tir(priv->mdev, tir, in, inlen);
2620 goto err_destroy_ch_tirs;
2627 err_destroy_ch_tirs:
2628 for (ix--; ix >= 0; ix--)
2629 mlx5e_destroy_tir(priv->mdev, &priv->direct_tir[ix]);
2636 static void mlx5e_destroy_indirect_tirs(struct mlx5e_priv *priv)
2640 for (i = 0; i < MLX5E_NUM_INDIR_TIRS; i++)
2641 mlx5e_destroy_tir(priv->mdev, &priv->indir_tir[i]);
2644 void mlx5e_destroy_direct_tirs(struct mlx5e_priv *priv)
2646 int nch = priv->profile->max_nch(priv->mdev);
2649 for (i = 0; i < nch; i++)
2650 mlx5e_destroy_tir(priv->mdev, &priv->direct_tir[i]);
2653 int mlx5e_modify_rqs_vsd(struct mlx5e_priv *priv, bool vsd)
2658 if (!test_bit(MLX5E_STATE_OPENED, &priv->state))
2661 for (i = 0; i < priv->params.num_channels; i++) {
2662 err = mlx5e_modify_rq_vsd(&priv->channel[i]->rq, vsd);
2670 static int mlx5e_setup_tc(struct net_device *netdev, u8 tc)
2672 struct mlx5e_priv *priv = netdev_priv(netdev);
2676 if (tc && tc != MLX5E_MAX_NUM_TC)
2679 mutex_lock(&priv->state_lock);
2681 was_opened = test_bit(MLX5E_STATE_OPENED, &priv->state);
2683 mlx5e_close_locked(priv->netdev);
2685 priv->params.num_tc = tc ? tc : 1;
2688 err = mlx5e_open_locked(priv->netdev);
2690 mutex_unlock(&priv->state_lock);
2695 static int mlx5e_ndo_setup_tc(struct net_device *dev, u32 handle,
2696 __be16 proto, struct tc_to_netdev *tc)
2698 struct mlx5e_priv *priv = netdev_priv(dev);
2700 if (TC_H_MAJ(handle) != TC_H_MAJ(TC_H_INGRESS))
2704 case TC_SETUP_CLSFLOWER:
2705 switch (tc->cls_flower->command) {
2706 case TC_CLSFLOWER_REPLACE:
2707 return mlx5e_configure_flower(priv, proto, tc->cls_flower);
2708 case TC_CLSFLOWER_DESTROY:
2709 return mlx5e_delete_flower(priv, tc->cls_flower);
2710 case TC_CLSFLOWER_STATS:
2711 return mlx5e_stats_flower(priv, tc->cls_flower);
2718 if (tc->type != TC_SETUP_MQPRIO)
2721 return mlx5e_setup_tc(dev, tc->tc);
2725 mlx5e_get_stats(struct net_device *dev, struct rtnl_link_stats64 *stats)
2727 struct mlx5e_priv *priv = netdev_priv(dev);
2728 struct mlx5e_sw_stats *sstats = &priv->stats.sw;
2729 struct mlx5e_vport_stats *vstats = &priv->stats.vport;
2730 struct mlx5e_pport_stats *pstats = &priv->stats.pport;
2732 if (mlx5e_is_uplink_rep(priv)) {
2733 stats->rx_packets = PPORT_802_3_GET(pstats, a_frames_received_ok);
2734 stats->rx_bytes = PPORT_802_3_GET(pstats, a_octets_received_ok);
2735 stats->tx_packets = PPORT_802_3_GET(pstats, a_frames_transmitted_ok);
2736 stats->tx_bytes = PPORT_802_3_GET(pstats, a_octets_transmitted_ok);
2738 stats->rx_packets = sstats->rx_packets;
2739 stats->rx_bytes = sstats->rx_bytes;
2740 stats->tx_packets = sstats->tx_packets;
2741 stats->tx_bytes = sstats->tx_bytes;
2742 stats->tx_dropped = sstats->tx_queue_dropped;
2745 stats->rx_dropped = priv->stats.qcnt.rx_out_of_buffer;
2747 stats->rx_length_errors =
2748 PPORT_802_3_GET(pstats, a_in_range_length_errors) +
2749 PPORT_802_3_GET(pstats, a_out_of_range_length_field) +
2750 PPORT_802_3_GET(pstats, a_frame_too_long_errors);
2751 stats->rx_crc_errors =
2752 PPORT_802_3_GET(pstats, a_frame_check_sequence_errors);
2753 stats->rx_frame_errors = PPORT_802_3_GET(pstats, a_alignment_errors);
2754 stats->tx_aborted_errors = PPORT_2863_GET(pstats, if_out_discards);
2755 stats->tx_carrier_errors =
2756 PPORT_802_3_GET(pstats, a_symbol_error_during_carrier);
2757 stats->rx_errors = stats->rx_length_errors + stats->rx_crc_errors +
2758 stats->rx_frame_errors;
2759 stats->tx_errors = stats->tx_aborted_errors + stats->tx_carrier_errors;
2761 /* vport multicast also counts packets that are dropped due to steering
2762 * or rx out of buffer
2765 VPORT_COUNTER_GET(vstats, received_eth_multicast.packets);
2769 static void mlx5e_set_rx_mode(struct net_device *dev)
2771 struct mlx5e_priv *priv = netdev_priv(dev);
2773 queue_work(priv->wq, &priv->set_rx_mode_work);
2776 static int mlx5e_set_mac(struct net_device *netdev, void *addr)
2778 struct mlx5e_priv *priv = netdev_priv(netdev);
2779 struct sockaddr *saddr = addr;
2781 if (!is_valid_ether_addr(saddr->sa_data))
2782 return -EADDRNOTAVAIL;
2784 netif_addr_lock_bh(netdev);
2785 ether_addr_copy(netdev->dev_addr, saddr->sa_data);
2786 netif_addr_unlock_bh(netdev);
2788 queue_work(priv->wq, &priv->set_rx_mode_work);
2793 #define MLX5E_SET_FEATURE(netdev, feature, enable) \
2796 netdev->features |= feature; \
2798 netdev->features &= ~feature; \
2801 typedef int (*mlx5e_feature_handler)(struct net_device *netdev, bool enable);
2803 static int set_feature_lro(struct net_device *netdev, bool enable)
2805 struct mlx5e_priv *priv = netdev_priv(netdev);
2806 bool was_opened = test_bit(MLX5E_STATE_OPENED, &priv->state);
2809 mutex_lock(&priv->state_lock);
2811 if (was_opened && (priv->params.rq_wq_type == MLX5_WQ_TYPE_LINKED_LIST))
2812 mlx5e_close_locked(priv->netdev);
2814 priv->params.lro_en = enable;
2815 err = mlx5e_modify_tirs_lro(priv);
2817 netdev_err(netdev, "lro modify failed, %d\n", err);
2818 priv->params.lro_en = !enable;
2821 if (was_opened && (priv->params.rq_wq_type == MLX5_WQ_TYPE_LINKED_LIST))
2822 mlx5e_open_locked(priv->netdev);
2824 mutex_unlock(&priv->state_lock);
2829 static int set_feature_vlan_filter(struct net_device *netdev, bool enable)
2831 struct mlx5e_priv *priv = netdev_priv(netdev);
2834 mlx5e_enable_vlan_filter(priv);
2836 mlx5e_disable_vlan_filter(priv);
2841 static int set_feature_tc_num_filters(struct net_device *netdev, bool enable)
2843 struct mlx5e_priv *priv = netdev_priv(netdev);
2845 if (!enable && mlx5e_tc_num_filters(priv)) {
2847 "Active offloaded tc filters, can't turn hw_tc_offload off\n");
2854 static int set_feature_rx_all(struct net_device *netdev, bool enable)
2856 struct mlx5e_priv *priv = netdev_priv(netdev);
2857 struct mlx5_core_dev *mdev = priv->mdev;
2859 return mlx5_set_port_fcs(mdev, !enable);
2862 static int set_feature_rx_vlan(struct net_device *netdev, bool enable)
2864 struct mlx5e_priv *priv = netdev_priv(netdev);
2867 mutex_lock(&priv->state_lock);
2869 priv->params.vlan_strip_disable = !enable;
2870 err = mlx5e_modify_rqs_vsd(priv, !enable);
2872 priv->params.vlan_strip_disable = enable;
2874 mutex_unlock(&priv->state_lock);
2879 #ifdef CONFIG_RFS_ACCEL
2880 static int set_feature_arfs(struct net_device *netdev, bool enable)
2882 struct mlx5e_priv *priv = netdev_priv(netdev);
2886 err = mlx5e_arfs_enable(priv);
2888 err = mlx5e_arfs_disable(priv);
2894 static int mlx5e_handle_feature(struct net_device *netdev,
2895 netdev_features_t wanted_features,
2896 netdev_features_t feature,
2897 mlx5e_feature_handler feature_handler)
2899 netdev_features_t changes = wanted_features ^ netdev->features;
2900 bool enable = !!(wanted_features & feature);
2903 if (!(changes & feature))
2906 err = feature_handler(netdev, enable);
2908 netdev_err(netdev, "%s feature 0x%llx failed err %d\n",
2909 enable ? "Enable" : "Disable", feature, err);
2913 MLX5E_SET_FEATURE(netdev, feature, enable);
2917 static int mlx5e_set_features(struct net_device *netdev,
2918 netdev_features_t features)
2922 err = mlx5e_handle_feature(netdev, features, NETIF_F_LRO,
2924 err |= mlx5e_handle_feature(netdev, features,
2925 NETIF_F_HW_VLAN_CTAG_FILTER,
2926 set_feature_vlan_filter);
2927 err |= mlx5e_handle_feature(netdev, features, NETIF_F_HW_TC,
2928 set_feature_tc_num_filters);
2929 err |= mlx5e_handle_feature(netdev, features, NETIF_F_RXALL,
2930 set_feature_rx_all);
2931 err |= mlx5e_handle_feature(netdev, features, NETIF_F_HW_VLAN_CTAG_RX,
2932 set_feature_rx_vlan);
2933 #ifdef CONFIG_RFS_ACCEL
2934 err |= mlx5e_handle_feature(netdev, features, NETIF_F_NTUPLE,
2938 return err ? -EINVAL : 0;
2941 static int mlx5e_change_mtu(struct net_device *netdev, int new_mtu)
2943 struct mlx5e_priv *priv = netdev_priv(netdev);
2948 mutex_lock(&priv->state_lock);
2950 reset = !priv->params.lro_en &&
2951 (priv->params.rq_wq_type !=
2952 MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ);
2954 was_opened = test_bit(MLX5E_STATE_OPENED, &priv->state);
2955 if (was_opened && reset)
2956 mlx5e_close_locked(netdev);
2958 netdev->mtu = new_mtu;
2959 mlx5e_set_dev_port_mtu(netdev);
2961 if (was_opened && reset)
2962 err = mlx5e_open_locked(netdev);
2964 mutex_unlock(&priv->state_lock);
2969 static int mlx5e_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
2973 return mlx5e_hwstamp_set(dev, ifr);
2975 return mlx5e_hwstamp_get(dev, ifr);
2981 static int mlx5e_set_vf_mac(struct net_device *dev, int vf, u8 *mac)
2983 struct mlx5e_priv *priv = netdev_priv(dev);
2984 struct mlx5_core_dev *mdev = priv->mdev;
2986 return mlx5_eswitch_set_vport_mac(mdev->priv.eswitch, vf + 1, mac);
2989 static int mlx5e_set_vf_vlan(struct net_device *dev, int vf, u16 vlan, u8 qos,
2992 struct mlx5e_priv *priv = netdev_priv(dev);
2993 struct mlx5_core_dev *mdev = priv->mdev;
2995 if (vlan_proto != htons(ETH_P_8021Q))
2996 return -EPROTONOSUPPORT;
2998 return mlx5_eswitch_set_vport_vlan(mdev->priv.eswitch, vf + 1,
3002 static int mlx5e_set_vf_spoofchk(struct net_device *dev, int vf, bool setting)
3004 struct mlx5e_priv *priv = netdev_priv(dev);
3005 struct mlx5_core_dev *mdev = priv->mdev;
3007 return mlx5_eswitch_set_vport_spoofchk(mdev->priv.eswitch, vf + 1, setting);
3010 static int mlx5e_set_vf_trust(struct net_device *dev, int vf, bool setting)
3012 struct mlx5e_priv *priv = netdev_priv(dev);
3013 struct mlx5_core_dev *mdev = priv->mdev;
3015 return mlx5_eswitch_set_vport_trust(mdev->priv.eswitch, vf + 1, setting);
3018 static int mlx5e_set_vf_rate(struct net_device *dev, int vf, int min_tx_rate,
3021 struct mlx5e_priv *priv = netdev_priv(dev);
3022 struct mlx5_core_dev *mdev = priv->mdev;
3027 return mlx5_eswitch_set_vport_rate(mdev->priv.eswitch, vf + 1,
3031 static int mlx5_vport_link2ifla(u8 esw_link)
3034 case MLX5_ESW_VPORT_ADMIN_STATE_DOWN:
3035 return IFLA_VF_LINK_STATE_DISABLE;
3036 case MLX5_ESW_VPORT_ADMIN_STATE_UP:
3037 return IFLA_VF_LINK_STATE_ENABLE;
3039 return IFLA_VF_LINK_STATE_AUTO;
3042 static int mlx5_ifla_link2vport(u8 ifla_link)
3044 switch (ifla_link) {
3045 case IFLA_VF_LINK_STATE_DISABLE:
3046 return MLX5_ESW_VPORT_ADMIN_STATE_DOWN;
3047 case IFLA_VF_LINK_STATE_ENABLE:
3048 return MLX5_ESW_VPORT_ADMIN_STATE_UP;
3050 return MLX5_ESW_VPORT_ADMIN_STATE_AUTO;
3053 static int mlx5e_set_vf_link_state(struct net_device *dev, int vf,
3056 struct mlx5e_priv *priv = netdev_priv(dev);
3057 struct mlx5_core_dev *mdev = priv->mdev;
3059 return mlx5_eswitch_set_vport_state(mdev->priv.eswitch, vf + 1,
3060 mlx5_ifla_link2vport(link_state));
3063 static int mlx5e_get_vf_config(struct net_device *dev,
3064 int vf, struct ifla_vf_info *ivi)
3066 struct mlx5e_priv *priv = netdev_priv(dev);
3067 struct mlx5_core_dev *mdev = priv->mdev;
3070 err = mlx5_eswitch_get_vport_config(mdev->priv.eswitch, vf + 1, ivi);
3073 ivi->linkstate = mlx5_vport_link2ifla(ivi->linkstate);
3077 static int mlx5e_get_vf_stats(struct net_device *dev,
3078 int vf, struct ifla_vf_stats *vf_stats)
3080 struct mlx5e_priv *priv = netdev_priv(dev);
3081 struct mlx5_core_dev *mdev = priv->mdev;
3083 return mlx5_eswitch_get_vport_stats(mdev->priv.eswitch, vf + 1,
3087 void mlx5e_add_vxlan_port(struct net_device *netdev,
3088 struct udp_tunnel_info *ti)
3090 struct mlx5e_priv *priv = netdev_priv(netdev);
3092 if (ti->type != UDP_TUNNEL_TYPE_VXLAN)
3095 if (!mlx5e_vxlan_allowed(priv->mdev))
3098 mlx5e_vxlan_queue_work(priv, ti->sa_family, be16_to_cpu(ti->port), 1);
3101 void mlx5e_del_vxlan_port(struct net_device *netdev,
3102 struct udp_tunnel_info *ti)
3104 struct mlx5e_priv *priv = netdev_priv(netdev);
3106 if (ti->type != UDP_TUNNEL_TYPE_VXLAN)
3109 if (!mlx5e_vxlan_allowed(priv->mdev))
3112 mlx5e_vxlan_queue_work(priv, ti->sa_family, be16_to_cpu(ti->port), 0);
3115 static netdev_features_t mlx5e_vxlan_features_check(struct mlx5e_priv *priv,
3116 struct sk_buff *skb,
3117 netdev_features_t features)
3119 struct udphdr *udph;
3123 switch (vlan_get_protocol(skb)) {
3124 case htons(ETH_P_IP):
3125 proto = ip_hdr(skb)->protocol;
3127 case htons(ETH_P_IPV6):
3128 proto = ipv6_hdr(skb)->nexthdr;
3134 if (proto == IPPROTO_UDP) {
3135 udph = udp_hdr(skb);
3136 port = be16_to_cpu(udph->dest);
3139 /* Verify if UDP port is being offloaded by HW */
3140 if (port && mlx5e_vxlan_lookup_port(priv, port))
3144 /* Disable CSUM and GSO if the udp dport is not offloaded by HW */
3145 return features & ~(NETIF_F_CSUM_MASK | NETIF_F_GSO_MASK);
3148 static netdev_features_t mlx5e_features_check(struct sk_buff *skb,
3149 struct net_device *netdev,
3150 netdev_features_t features)
3152 struct mlx5e_priv *priv = netdev_priv(netdev);
3154 features = vlan_features_check(skb, features);
3155 features = vxlan_features_check(skb, features);
3157 /* Validate if the tunneled packet is being offloaded by HW */
3158 if (skb->encapsulation &&
3159 (features & NETIF_F_CSUM_MASK || features & NETIF_F_GSO_MASK))
3160 return mlx5e_vxlan_features_check(priv, skb, features);
3165 static void mlx5e_tx_timeout(struct net_device *dev)
3167 struct mlx5e_priv *priv = netdev_priv(dev);
3168 bool sched_work = false;
3171 netdev_err(dev, "TX timeout detected\n");
3173 for (i = 0; i < priv->params.num_channels * priv->params.num_tc; i++) {
3174 struct mlx5e_sq *sq = priv->txq_to_sq_map[i];
3176 if (!netif_xmit_stopped(netdev_get_tx_queue(dev, i)))
3179 clear_bit(MLX5E_SQ_STATE_ENABLED, &sq->state);
3180 netdev_err(dev, "TX timeout on queue: %d, SQ: 0x%x, CQ: 0x%x, SQ Cons: 0x%x SQ Prod: 0x%x\n",
3181 i, sq->sqn, sq->cq.mcq.cqn, sq->cc, sq->pc);
3184 if (sched_work && test_bit(MLX5E_STATE_OPENED, &priv->state))
3185 schedule_work(&priv->tx_timeout_work);
3188 static int mlx5e_xdp_set(struct net_device *netdev, struct bpf_prog *prog)
3190 struct mlx5e_priv *priv = netdev_priv(netdev);
3191 struct bpf_prog *old_prog;
3193 bool reset, was_opened;
3196 mutex_lock(&priv->state_lock);
3198 if ((netdev->features & NETIF_F_LRO) && prog) {
3199 netdev_warn(netdev, "can't set XDP while LRO is on, disable LRO first\n");
3204 was_opened = test_bit(MLX5E_STATE_OPENED, &priv->state);
3205 /* no need for full reset when exchanging programs */
3206 reset = (!priv->xdp_prog || !prog);
3208 if (was_opened && reset)
3209 mlx5e_close_locked(netdev);
3210 if (was_opened && !reset) {
3211 /* num_channels is invariant here, so we can take the
3212 * batched reference right upfront.
3214 prog = bpf_prog_add(prog, priv->params.num_channels);
3216 err = PTR_ERR(prog);
3221 /* exchange programs, extra prog reference we got from caller
3222 * as long as we don't fail from this point onwards.
3224 old_prog = xchg(&priv->xdp_prog, prog);
3226 bpf_prog_put(old_prog);
3228 if (reset) /* change RQ type according to priv->xdp_prog */
3229 mlx5e_set_rq_priv_params(priv);
3231 if (was_opened && reset)
3232 mlx5e_open_locked(netdev);
3234 if (!test_bit(MLX5E_STATE_OPENED, &priv->state) || reset)
3237 /* exchanging programs w/o reset, we update ref counts on behalf
3238 * of the channels RQs here.
3240 for (i = 0; i < priv->params.num_channels; i++) {
3241 struct mlx5e_channel *c = priv->channel[i];
3243 clear_bit(MLX5E_RQ_STATE_ENABLED, &c->rq.state);
3244 napi_synchronize(&c->napi);
3245 /* prevent mlx5e_poll_rx_cq from accessing rq->xdp_prog */
3247 old_prog = xchg(&c->rq.xdp_prog, prog);
3249 set_bit(MLX5E_RQ_STATE_ENABLED, &c->rq.state);
3250 /* napi_schedule in case we have missed anything */
3251 set_bit(MLX5E_CHANNEL_NAPI_SCHED, &c->flags);
3252 napi_schedule(&c->napi);
3255 bpf_prog_put(old_prog);
3259 mutex_unlock(&priv->state_lock);
3263 static bool mlx5e_xdp_attached(struct net_device *dev)
3265 struct mlx5e_priv *priv = netdev_priv(dev);
3267 return !!priv->xdp_prog;
3270 static int mlx5e_xdp(struct net_device *dev, struct netdev_xdp *xdp)
3272 switch (xdp->command) {
3273 case XDP_SETUP_PROG:
3274 return mlx5e_xdp_set(dev, xdp->prog);
3275 case XDP_QUERY_PROG:
3276 xdp->prog_attached = mlx5e_xdp_attached(dev);
3283 #ifdef CONFIG_NET_POLL_CONTROLLER
3284 /* Fake "interrupt" called by netpoll (eg netconsole) to send skbs without
3285 * reenabling interrupts.
3287 static void mlx5e_netpoll(struct net_device *dev)
3289 struct mlx5e_priv *priv = netdev_priv(dev);
3292 for (i = 0; i < priv->params.num_channels; i++)
3293 napi_schedule(&priv->channel[i]->napi);
3297 static const struct net_device_ops mlx5e_netdev_ops_basic = {
3298 .ndo_open = mlx5e_open,
3299 .ndo_stop = mlx5e_close,
3300 .ndo_start_xmit = mlx5e_xmit,
3301 .ndo_setup_tc = mlx5e_ndo_setup_tc,
3302 .ndo_select_queue = mlx5e_select_queue,
3303 .ndo_get_stats64 = mlx5e_get_stats,
3304 .ndo_set_rx_mode = mlx5e_set_rx_mode,
3305 .ndo_set_mac_address = mlx5e_set_mac,
3306 .ndo_vlan_rx_add_vid = mlx5e_vlan_rx_add_vid,
3307 .ndo_vlan_rx_kill_vid = mlx5e_vlan_rx_kill_vid,
3308 .ndo_set_features = mlx5e_set_features,
3309 .ndo_change_mtu = mlx5e_change_mtu,
3310 .ndo_do_ioctl = mlx5e_ioctl,
3311 .ndo_set_tx_maxrate = mlx5e_set_tx_maxrate,
3312 #ifdef CONFIG_RFS_ACCEL
3313 .ndo_rx_flow_steer = mlx5e_rx_flow_steer,
3315 .ndo_tx_timeout = mlx5e_tx_timeout,
3316 .ndo_xdp = mlx5e_xdp,
3317 #ifdef CONFIG_NET_POLL_CONTROLLER
3318 .ndo_poll_controller = mlx5e_netpoll,
3322 static const struct net_device_ops mlx5e_netdev_ops_sriov = {
3323 .ndo_open = mlx5e_open,
3324 .ndo_stop = mlx5e_close,
3325 .ndo_start_xmit = mlx5e_xmit,
3326 .ndo_setup_tc = mlx5e_ndo_setup_tc,
3327 .ndo_select_queue = mlx5e_select_queue,
3328 .ndo_get_stats64 = mlx5e_get_stats,
3329 .ndo_set_rx_mode = mlx5e_set_rx_mode,
3330 .ndo_set_mac_address = mlx5e_set_mac,
3331 .ndo_vlan_rx_add_vid = mlx5e_vlan_rx_add_vid,
3332 .ndo_vlan_rx_kill_vid = mlx5e_vlan_rx_kill_vid,
3333 .ndo_set_features = mlx5e_set_features,
3334 .ndo_change_mtu = mlx5e_change_mtu,
3335 .ndo_do_ioctl = mlx5e_ioctl,
3336 .ndo_udp_tunnel_add = mlx5e_add_vxlan_port,
3337 .ndo_udp_tunnel_del = mlx5e_del_vxlan_port,
3338 .ndo_set_tx_maxrate = mlx5e_set_tx_maxrate,
3339 .ndo_features_check = mlx5e_features_check,
3340 #ifdef CONFIG_RFS_ACCEL
3341 .ndo_rx_flow_steer = mlx5e_rx_flow_steer,
3343 .ndo_set_vf_mac = mlx5e_set_vf_mac,
3344 .ndo_set_vf_vlan = mlx5e_set_vf_vlan,
3345 .ndo_set_vf_spoofchk = mlx5e_set_vf_spoofchk,
3346 .ndo_set_vf_trust = mlx5e_set_vf_trust,
3347 .ndo_set_vf_rate = mlx5e_set_vf_rate,
3348 .ndo_get_vf_config = mlx5e_get_vf_config,
3349 .ndo_set_vf_link_state = mlx5e_set_vf_link_state,
3350 .ndo_get_vf_stats = mlx5e_get_vf_stats,
3351 .ndo_tx_timeout = mlx5e_tx_timeout,
3352 .ndo_xdp = mlx5e_xdp,
3353 #ifdef CONFIG_NET_POLL_CONTROLLER
3354 .ndo_poll_controller = mlx5e_netpoll,
3356 .ndo_has_offload_stats = mlx5e_has_offload_stats,
3357 .ndo_get_offload_stats = mlx5e_get_offload_stats,
3360 static int mlx5e_check_required_hca_cap(struct mlx5_core_dev *mdev)
3362 if (MLX5_CAP_GEN(mdev, port_type) != MLX5_CAP_PORT_TYPE_ETH)
3364 if (!MLX5_CAP_GEN(mdev, eth_net_offloads) ||
3365 !MLX5_CAP_GEN(mdev, nic_flow_table) ||
3366 !MLX5_CAP_ETH(mdev, csum_cap) ||
3367 !MLX5_CAP_ETH(mdev, max_lso_cap) ||
3368 !MLX5_CAP_ETH(mdev, vlan_cap) ||
3369 !MLX5_CAP_ETH(mdev, rss_ind_tbl_cap) ||
3370 MLX5_CAP_FLOWTABLE(mdev,
3371 flow_table_properties_nic_receive.max_ft_level)
3373 mlx5_core_warn(mdev,
3374 "Not creating net device, some required device capabilities are missing\n");
3377 if (!MLX5_CAP_ETH(mdev, self_lb_en_modifiable))
3378 mlx5_core_warn(mdev, "Self loop back prevention is not supported\n");
3379 if (!MLX5_CAP_GEN(mdev, cq_moderation))
3380 mlx5_core_warn(mdev, "CQ modiration is not supported\n");
3385 u16 mlx5e_get_max_inline_cap(struct mlx5_core_dev *mdev)
3387 int bf_buf_size = (1 << MLX5_CAP_GEN(mdev, log_bf_reg_size)) / 2;
3389 return bf_buf_size -
3390 sizeof(struct mlx5e_tx_wqe) +
3391 2 /*sizeof(mlx5e_tx_wqe.inline_hdr_start)*/;
3394 void mlx5e_build_default_indir_rqt(struct mlx5_core_dev *mdev,
3395 u32 *indirection_rqt, int len,
3398 int node = mdev->priv.numa_node;
3399 int node_num_of_cores;
3403 node = first_online_node;
3405 node_num_of_cores = cpumask_weight(cpumask_of_node(node));
3407 if (node_num_of_cores)
3408 num_channels = min_t(int, num_channels, node_num_of_cores);
3410 for (i = 0; i < len; i++)
3411 indirection_rqt[i] = i % num_channels;
3414 static int mlx5e_get_pci_bw(struct mlx5_core_dev *mdev, u32 *pci_bw)
3416 enum pcie_link_width width;
3417 enum pci_bus_speed speed;
3420 err = pcie_get_minimum_link(mdev->pdev, &speed, &width);
3424 if (speed == PCI_SPEED_UNKNOWN || width == PCIE_LNK_WIDTH_UNKNOWN)
3428 case PCIE_SPEED_2_5GT:
3429 *pci_bw = 2500 * width;
3431 case PCIE_SPEED_5_0GT:
3432 *pci_bw = 5000 * width;
3434 case PCIE_SPEED_8_0GT:
3435 *pci_bw = 8000 * width;
3444 static bool cqe_compress_heuristic(u32 link_speed, u32 pci_bw)
3446 return (link_speed && pci_bw &&
3447 (pci_bw < 40000) && (pci_bw < link_speed));
3450 void mlx5e_set_rx_cq_mode_params(struct mlx5e_params *params, u8 cq_period_mode)
3452 params->rx_cq_period_mode = cq_period_mode;
3454 params->rx_cq_moderation.pkts =
3455 MLX5E_PARAMS_DEFAULT_RX_CQ_MODERATION_PKTS;
3456 params->rx_cq_moderation.usec =
3457 MLX5E_PARAMS_DEFAULT_RX_CQ_MODERATION_USEC;
3459 if (cq_period_mode == MLX5_CQ_PERIOD_MODE_START_FROM_CQE)
3460 params->rx_cq_moderation.usec =
3461 MLX5E_PARAMS_DEFAULT_RX_CQ_MODERATION_USEC_FROM_CQE;
3464 static void mlx5e_query_min_inline(struct mlx5_core_dev *mdev,
3465 u8 *min_inline_mode)
3467 switch (MLX5_CAP_ETH(mdev, wqe_inline_mode)) {
3468 case MLX5_CAP_INLINE_MODE_L2:
3469 *min_inline_mode = MLX5_INLINE_MODE_L2;
3471 case MLX5_CAP_INLINE_MODE_VPORT_CONTEXT:
3472 mlx5_query_nic_vport_min_inline(mdev, 0, min_inline_mode);
3474 case MLX5_CAP_INLINE_MODE_NOT_REQUIRED:
3475 *min_inline_mode = MLX5_INLINE_MODE_NONE;
3480 u32 mlx5e_choose_lro_timeout(struct mlx5_core_dev *mdev, u32 wanted_timeout)
3484 /* The supported periods are organized in ascending order */
3485 for (i = 0; i < MLX5E_LRO_TIMEOUT_ARR_SIZE - 1; i++)
3486 if (MLX5_CAP_ETH(mdev, lro_timer_supported_periods[i]) >= wanted_timeout)
3489 return MLX5_CAP_ETH(mdev, lro_timer_supported_periods[i]);
3492 static void mlx5e_build_nic_netdev_priv(struct mlx5_core_dev *mdev,
3493 struct net_device *netdev,
3494 const struct mlx5e_profile *profile,
3497 struct mlx5e_priv *priv = netdev_priv(netdev);
3500 u8 cq_period_mode = MLX5_CAP_GEN(mdev, cq_period_start_from_cqe) ?
3501 MLX5_CQ_PERIOD_MODE_START_FROM_CQE :
3502 MLX5_CQ_PERIOD_MODE_START_FROM_EQE;
3505 priv->netdev = netdev;
3506 priv->params.num_channels = profile->max_nch(mdev);
3507 priv->profile = profile;
3508 priv->ppriv = ppriv;
3510 priv->params.lro_timeout =
3511 mlx5e_choose_lro_timeout(mdev, MLX5E_DEFAULT_LRO_TIMEOUT);
3513 priv->params.log_sq_size = MLX5E_PARAMS_DEFAULT_LOG_SQ_SIZE;
3515 /* set CQE compression */
3516 priv->params.rx_cqe_compress_def = false;
3517 if (MLX5_CAP_GEN(mdev, cqe_compression) &&
3518 MLX5_CAP_GEN(mdev, vport_group_manager)) {
3519 mlx5e_get_max_linkspeed(mdev, &link_speed);
3520 mlx5e_get_pci_bw(mdev, &pci_bw);
3521 mlx5_core_dbg(mdev, "Max link speed = %d, PCI BW = %d\n",
3522 link_speed, pci_bw);
3523 priv->params.rx_cqe_compress_def =
3524 cqe_compress_heuristic(link_speed, pci_bw);
3527 mlx5e_set_rq_priv_params(priv);
3528 if (priv->params.rq_wq_type == MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ)
3529 priv->params.lro_en = true;
3531 priv->params.rx_am_enabled = MLX5_CAP_GEN(mdev, cq_moderation);
3532 mlx5e_set_rx_cq_mode_params(&priv->params, cq_period_mode);
3534 priv->params.tx_cq_moderation.usec =
3535 MLX5E_PARAMS_DEFAULT_TX_CQ_MODERATION_USEC;
3536 priv->params.tx_cq_moderation.pkts =
3537 MLX5E_PARAMS_DEFAULT_TX_CQ_MODERATION_PKTS;
3538 priv->params.tx_max_inline = mlx5e_get_max_inline_cap(mdev);
3539 mlx5e_query_min_inline(mdev, &priv->params.tx_min_inline_mode);
3540 priv->params.num_tc = 1;
3541 priv->params.rss_hfunc = ETH_RSS_HASH_XOR;
3543 netdev_rss_key_fill(priv->params.toeplitz_hash_key,
3544 sizeof(priv->params.toeplitz_hash_key));
3546 mlx5e_build_default_indir_rqt(mdev, priv->params.indirection_rqt,
3547 MLX5E_INDIR_RQT_SIZE, profile->max_nch(mdev));
3549 priv->params.lro_wqe_sz =
3550 MLX5E_PARAMS_DEFAULT_LRO_WQE_SZ -
3551 /* Extra room needed for build_skb */
3553 SKB_DATA_ALIGN(sizeof(struct skb_shared_info));
3555 /* Initialize pflags */
3556 MLX5E_SET_PFLAG(priv, MLX5E_PFLAG_RX_CQE_BASED_MODER,
3557 priv->params.rx_cq_period_mode == MLX5_CQ_PERIOD_MODE_START_FROM_CQE);
3558 MLX5E_SET_PFLAG(priv, MLX5E_PFLAG_RX_CQE_COMPRESS, priv->params.rx_cqe_compress_def);
3560 mutex_init(&priv->state_lock);
3562 INIT_WORK(&priv->update_carrier_work, mlx5e_update_carrier_work);
3563 INIT_WORK(&priv->set_rx_mode_work, mlx5e_set_rx_mode_work);
3564 INIT_WORK(&priv->tx_timeout_work, mlx5e_tx_timeout_work);
3565 INIT_DELAYED_WORK(&priv->update_stats_work, mlx5e_update_stats_work);
3568 static void mlx5e_set_netdev_dev_addr(struct net_device *netdev)
3570 struct mlx5e_priv *priv = netdev_priv(netdev);
3572 mlx5_query_nic_vport_mac_address(priv->mdev, 0, netdev->dev_addr);
3573 if (is_zero_ether_addr(netdev->dev_addr) &&
3574 !MLX5_CAP_GEN(priv->mdev, vport_group_manager)) {
3575 eth_hw_addr_random(netdev);
3576 mlx5_core_info(priv->mdev, "Assigned random MAC address %pM\n", netdev->dev_addr);
3580 static const struct switchdev_ops mlx5e_switchdev_ops = {
3581 .switchdev_port_attr_get = mlx5e_attr_get,
3584 static void mlx5e_build_nic_netdev(struct net_device *netdev)
3586 struct mlx5e_priv *priv = netdev_priv(netdev);
3587 struct mlx5_core_dev *mdev = priv->mdev;
3591 SET_NETDEV_DEV(netdev, &mdev->pdev->dev);
3593 if (MLX5_CAP_GEN(mdev, vport_group_manager)) {
3594 netdev->netdev_ops = &mlx5e_netdev_ops_sriov;
3595 #ifdef CONFIG_MLX5_CORE_EN_DCB
3596 if (MLX5_CAP_GEN(mdev, qos))
3597 netdev->dcbnl_ops = &mlx5e_dcbnl_ops;
3600 netdev->netdev_ops = &mlx5e_netdev_ops_basic;
3603 netdev->watchdog_timeo = 15 * HZ;
3605 netdev->ethtool_ops = &mlx5e_ethtool_ops;
3607 netdev->vlan_features |= NETIF_F_SG;
3608 netdev->vlan_features |= NETIF_F_IP_CSUM;
3609 netdev->vlan_features |= NETIF_F_IPV6_CSUM;
3610 netdev->vlan_features |= NETIF_F_GRO;
3611 netdev->vlan_features |= NETIF_F_TSO;
3612 netdev->vlan_features |= NETIF_F_TSO6;
3613 netdev->vlan_features |= NETIF_F_RXCSUM;
3614 netdev->vlan_features |= NETIF_F_RXHASH;
3616 if (!!MLX5_CAP_ETH(mdev, lro_cap))
3617 netdev->vlan_features |= NETIF_F_LRO;
3619 netdev->hw_features = netdev->vlan_features;
3620 netdev->hw_features |= NETIF_F_HW_VLAN_CTAG_TX;
3621 netdev->hw_features |= NETIF_F_HW_VLAN_CTAG_RX;
3622 netdev->hw_features |= NETIF_F_HW_VLAN_CTAG_FILTER;
3624 if (mlx5e_vxlan_allowed(mdev)) {
3625 netdev->hw_features |= NETIF_F_GSO_UDP_TUNNEL |
3626 NETIF_F_GSO_UDP_TUNNEL_CSUM |
3627 NETIF_F_GSO_PARTIAL;
3628 netdev->hw_enc_features |= NETIF_F_IP_CSUM;
3629 netdev->hw_enc_features |= NETIF_F_IPV6_CSUM;
3630 netdev->hw_enc_features |= NETIF_F_TSO;
3631 netdev->hw_enc_features |= NETIF_F_TSO6;
3632 netdev->hw_enc_features |= NETIF_F_GSO_UDP_TUNNEL;
3633 netdev->hw_enc_features |= NETIF_F_GSO_UDP_TUNNEL_CSUM |
3634 NETIF_F_GSO_PARTIAL;
3635 netdev->gso_partial_features = NETIF_F_GSO_UDP_TUNNEL_CSUM;
3638 mlx5_query_port_fcs(mdev, &fcs_supported, &fcs_enabled);
3641 netdev->hw_features |= NETIF_F_RXALL;
3643 netdev->features = netdev->hw_features;
3644 if (!priv->params.lro_en)
3645 netdev->features &= ~NETIF_F_LRO;
3648 netdev->features &= ~NETIF_F_RXALL;
3650 #define FT_CAP(f) MLX5_CAP_FLOWTABLE(mdev, flow_table_properties_nic_receive.f)
3651 if (FT_CAP(flow_modify_en) &&
3652 FT_CAP(modify_root) &&
3653 FT_CAP(identified_miss_table_mode) &&
3654 FT_CAP(flow_table_modify)) {
3655 netdev->hw_features |= NETIF_F_HW_TC;
3656 #ifdef CONFIG_RFS_ACCEL
3657 netdev->hw_features |= NETIF_F_NTUPLE;
3661 netdev->features |= NETIF_F_HIGHDMA;
3663 netdev->priv_flags |= IFF_UNICAST_FLT;
3665 mlx5e_set_netdev_dev_addr(netdev);
3667 #ifdef CONFIG_NET_SWITCHDEV
3668 if (MLX5_CAP_GEN(mdev, vport_group_manager))
3669 netdev->switchdev_ops = &mlx5e_switchdev_ops;
3673 static void mlx5e_create_q_counter(struct mlx5e_priv *priv)
3675 struct mlx5_core_dev *mdev = priv->mdev;
3678 err = mlx5_core_alloc_q_counter(mdev, &priv->q_counter);
3680 mlx5_core_warn(mdev, "alloc queue counter failed, %d\n", err);
3681 priv->q_counter = 0;
3685 static void mlx5e_destroy_q_counter(struct mlx5e_priv *priv)
3687 if (!priv->q_counter)
3690 mlx5_core_dealloc_q_counter(priv->mdev, priv->q_counter);
3693 static void mlx5e_nic_init(struct mlx5_core_dev *mdev,
3694 struct net_device *netdev,
3695 const struct mlx5e_profile *profile,
3698 struct mlx5e_priv *priv = netdev_priv(netdev);
3700 mlx5e_build_nic_netdev_priv(mdev, netdev, profile, ppriv);
3701 mlx5e_build_nic_netdev(netdev);
3702 mlx5e_vxlan_init(priv);
3705 static void mlx5e_nic_cleanup(struct mlx5e_priv *priv)
3707 mlx5e_vxlan_cleanup(priv);
3710 bpf_prog_put(priv->xdp_prog);
3713 static int mlx5e_init_nic_rx(struct mlx5e_priv *priv)
3715 struct mlx5_core_dev *mdev = priv->mdev;
3719 err = mlx5e_create_indirect_rqts(priv);
3721 mlx5_core_warn(mdev, "create indirect rqts failed, %d\n", err);
3725 err = mlx5e_create_direct_rqts(priv);
3727 mlx5_core_warn(mdev, "create direct rqts failed, %d\n", err);
3728 goto err_destroy_indirect_rqts;
3731 err = mlx5e_create_indirect_tirs(priv);
3733 mlx5_core_warn(mdev, "create indirect tirs failed, %d\n", err);
3734 goto err_destroy_direct_rqts;
3737 err = mlx5e_create_direct_tirs(priv);
3739 mlx5_core_warn(mdev, "create direct tirs failed, %d\n", err);
3740 goto err_destroy_indirect_tirs;
3743 err = mlx5e_create_flow_steering(priv);
3745 mlx5_core_warn(mdev, "create flow steering failed, %d\n", err);
3746 goto err_destroy_direct_tirs;
3749 err = mlx5e_tc_init(priv);
3751 goto err_destroy_flow_steering;
3755 err_destroy_flow_steering:
3756 mlx5e_destroy_flow_steering(priv);
3757 err_destroy_direct_tirs:
3758 mlx5e_destroy_direct_tirs(priv);
3759 err_destroy_indirect_tirs:
3760 mlx5e_destroy_indirect_tirs(priv);
3761 err_destroy_direct_rqts:
3762 for (i = 0; i < priv->profile->max_nch(mdev); i++)
3763 mlx5e_destroy_rqt(priv, &priv->direct_tir[i].rqt);
3764 err_destroy_indirect_rqts:
3765 mlx5e_destroy_rqt(priv, &priv->indir_rqt);
3769 static void mlx5e_cleanup_nic_rx(struct mlx5e_priv *priv)
3773 mlx5e_tc_cleanup(priv);
3774 mlx5e_destroy_flow_steering(priv);
3775 mlx5e_destroy_direct_tirs(priv);
3776 mlx5e_destroy_indirect_tirs(priv);
3777 for (i = 0; i < priv->profile->max_nch(priv->mdev); i++)
3778 mlx5e_destroy_rqt(priv, &priv->direct_tir[i].rqt);
3779 mlx5e_destroy_rqt(priv, &priv->indir_rqt);
3782 static int mlx5e_init_nic_tx(struct mlx5e_priv *priv)
3786 err = mlx5e_create_tises(priv);
3788 mlx5_core_warn(priv->mdev, "create tises failed, %d\n", err);
3792 #ifdef CONFIG_MLX5_CORE_EN_DCB
3793 mlx5e_dcbnl_initialize(priv);
3798 static void mlx5e_nic_enable(struct mlx5e_priv *priv)
3800 struct net_device *netdev = priv->netdev;
3801 struct mlx5_core_dev *mdev = priv->mdev;
3802 struct mlx5_eswitch *esw = mdev->priv.eswitch;
3803 struct mlx5_eswitch_rep rep;
3805 mlx5_lag_add(mdev, netdev);
3807 mlx5e_enable_async_events(priv);
3809 if (MLX5_CAP_GEN(mdev, vport_group_manager)) {
3810 mlx5_query_nic_vport_mac_address(mdev, 0, rep.hw_id);
3811 rep.load = mlx5e_nic_rep_load;
3812 rep.unload = mlx5e_nic_rep_unload;
3813 rep.vport = FDB_UPLINK_VPORT;
3814 rep.netdev = netdev;
3815 mlx5_eswitch_register_vport_rep(esw, 0, &rep);
3818 if (netdev->reg_state != NETREG_REGISTERED)
3821 /* Device already registered: sync netdev system state */
3822 if (mlx5e_vxlan_allowed(mdev)) {
3824 udp_tunnel_get_rx_info(netdev);
3828 queue_work(priv->wq, &priv->set_rx_mode_work);
3831 static void mlx5e_nic_disable(struct mlx5e_priv *priv)
3833 struct mlx5_core_dev *mdev = priv->mdev;
3834 struct mlx5_eswitch *esw = mdev->priv.eswitch;
3836 queue_work(priv->wq, &priv->set_rx_mode_work);
3837 if (MLX5_CAP_GEN(mdev, vport_group_manager))
3838 mlx5_eswitch_unregister_vport_rep(esw, 0);
3839 mlx5e_disable_async_events(priv);
3840 mlx5_lag_remove(mdev);
3843 static const struct mlx5e_profile mlx5e_nic_profile = {
3844 .init = mlx5e_nic_init,
3845 .cleanup = mlx5e_nic_cleanup,
3846 .init_rx = mlx5e_init_nic_rx,
3847 .cleanup_rx = mlx5e_cleanup_nic_rx,
3848 .init_tx = mlx5e_init_nic_tx,
3849 .cleanup_tx = mlx5e_cleanup_nic_tx,
3850 .enable = mlx5e_nic_enable,
3851 .disable = mlx5e_nic_disable,
3852 .update_stats = mlx5e_update_stats,
3853 .max_nch = mlx5e_get_max_num_channels,
3854 .max_tc = MLX5E_MAX_NUM_TC,
3857 struct net_device *mlx5e_create_netdev(struct mlx5_core_dev *mdev,
3858 const struct mlx5e_profile *profile,
3861 int nch = profile->max_nch(mdev);
3862 struct net_device *netdev;
3863 struct mlx5e_priv *priv;
3865 netdev = alloc_etherdev_mqs(sizeof(struct mlx5e_priv),
3866 nch * profile->max_tc,
3869 mlx5_core_err(mdev, "alloc_etherdev_mqs() failed\n");
3873 profile->init(mdev, netdev, profile, ppriv);
3875 netif_carrier_off(netdev);
3877 priv = netdev_priv(netdev);
3879 priv->wq = create_singlethread_workqueue("mlx5e");
3881 goto err_cleanup_nic;
3886 profile->cleanup(priv);
3887 free_netdev(netdev);
3892 int mlx5e_attach_netdev(struct mlx5_core_dev *mdev, struct net_device *netdev)
3894 const struct mlx5e_profile *profile;
3895 struct mlx5e_priv *priv;
3899 priv = netdev_priv(netdev);
3900 profile = priv->profile;
3901 clear_bit(MLX5E_STATE_DESTROYING, &priv->state);
3903 err = profile->init_tx(priv);
3907 err = mlx5e_open_drop_rq(priv);
3909 mlx5_core_err(mdev, "open drop rq failed, %d\n", err);
3910 goto err_cleanup_tx;
3913 err = profile->init_rx(priv);
3915 goto err_close_drop_rq;
3917 mlx5e_create_q_counter(priv);
3919 mlx5e_init_l2_addr(priv);
3921 /* MTU range: 68 - hw-specific max */
3922 netdev->min_mtu = ETH_MIN_MTU;
3923 mlx5_query_port_max_mtu(priv->mdev, &max_mtu, 1);
3924 netdev->max_mtu = MLX5E_HW2SW_MTU(max_mtu);
3926 mlx5e_set_dev_port_mtu(netdev);
3928 if (profile->enable)
3929 profile->enable(priv);
3932 if (netif_running(netdev))
3934 netif_device_attach(netdev);
3940 mlx5e_close_drop_rq(priv);
3943 profile->cleanup_tx(priv);
3949 static void mlx5e_register_vport_rep(struct mlx5_core_dev *mdev)
3951 struct mlx5_eswitch *esw = mdev->priv.eswitch;
3952 int total_vfs = MLX5_TOTAL_VPORTS(mdev);
3956 if (!MLX5_CAP_GEN(mdev, vport_group_manager))
3959 mlx5_query_nic_vport_mac_address(mdev, 0, mac);
3961 for (vport = 1; vport < total_vfs; vport++) {
3962 struct mlx5_eswitch_rep rep;
3964 rep.load = mlx5e_vport_rep_load;
3965 rep.unload = mlx5e_vport_rep_unload;
3967 ether_addr_copy(rep.hw_id, mac);
3968 mlx5_eswitch_register_vport_rep(esw, vport, &rep);
3972 void mlx5e_detach_netdev(struct mlx5_core_dev *mdev, struct net_device *netdev)
3974 struct mlx5e_priv *priv = netdev_priv(netdev);
3975 const struct mlx5e_profile *profile = priv->profile;
3977 set_bit(MLX5E_STATE_DESTROYING, &priv->state);
3980 if (netif_running(netdev))
3981 mlx5e_close(netdev);
3982 netif_device_detach(netdev);
3985 if (profile->disable)
3986 profile->disable(priv);
3987 flush_workqueue(priv->wq);
3989 mlx5e_destroy_q_counter(priv);
3990 profile->cleanup_rx(priv);
3991 mlx5e_close_drop_rq(priv);
3992 profile->cleanup_tx(priv);
3993 cancel_delayed_work_sync(&priv->update_stats_work);
3996 /* mlx5e_attach and mlx5e_detach scope should be only creating/destroying
3997 * hardware contexts and to connect it to the current netdev.
3999 static int mlx5e_attach(struct mlx5_core_dev *mdev, void *vpriv)
4001 struct mlx5e_priv *priv = vpriv;
4002 struct net_device *netdev = priv->netdev;
4005 if (netif_device_present(netdev))
4008 err = mlx5e_create_mdev_resources(mdev);
4012 err = mlx5e_attach_netdev(mdev, netdev);
4014 mlx5e_destroy_mdev_resources(mdev);
4021 static void mlx5e_detach(struct mlx5_core_dev *mdev, void *vpriv)
4023 struct mlx5e_priv *priv = vpriv;
4024 struct net_device *netdev = priv->netdev;
4026 if (!netif_device_present(netdev))
4029 mlx5e_detach_netdev(mdev, netdev);
4030 mlx5e_destroy_mdev_resources(mdev);
4033 static void *mlx5e_add(struct mlx5_core_dev *mdev)
4035 struct mlx5_eswitch *esw = mdev->priv.eswitch;
4036 int total_vfs = MLX5_TOTAL_VPORTS(mdev);
4041 struct net_device *netdev;
4043 err = mlx5e_check_required_hca_cap(mdev);
4047 mlx5e_register_vport_rep(mdev);
4049 if (MLX5_CAP_GEN(mdev, vport_group_manager))
4050 ppriv = &esw->offloads.vport_reps[0];
4052 netdev = mlx5e_create_netdev(mdev, &mlx5e_nic_profile, ppriv);
4054 mlx5_core_err(mdev, "mlx5e_create_netdev failed\n");
4055 goto err_unregister_reps;
4058 priv = netdev_priv(netdev);
4060 err = mlx5e_attach(mdev, priv);
4062 mlx5_core_err(mdev, "mlx5e_attach failed, %d\n", err);
4063 goto err_destroy_netdev;
4066 err = register_netdev(netdev);
4068 mlx5_core_err(mdev, "register_netdev failed, %d\n", err);
4075 mlx5e_detach(mdev, priv);
4078 mlx5e_destroy_netdev(mdev, priv);
4080 err_unregister_reps:
4081 for (vport = 1; vport < total_vfs; vport++)
4082 mlx5_eswitch_unregister_vport_rep(esw, vport);
4087 void mlx5e_destroy_netdev(struct mlx5_core_dev *mdev, struct mlx5e_priv *priv)
4089 const struct mlx5e_profile *profile = priv->profile;
4090 struct net_device *netdev = priv->netdev;
4092 destroy_workqueue(priv->wq);
4093 if (profile->cleanup)
4094 profile->cleanup(priv);
4095 free_netdev(netdev);
4098 static void mlx5e_remove(struct mlx5_core_dev *mdev, void *vpriv)
4100 struct mlx5_eswitch *esw = mdev->priv.eswitch;
4101 int total_vfs = MLX5_TOTAL_VPORTS(mdev);
4102 struct mlx5e_priv *priv = vpriv;
4105 for (vport = 1; vport < total_vfs; vport++)
4106 mlx5_eswitch_unregister_vport_rep(esw, vport);
4108 unregister_netdev(priv->netdev);
4109 mlx5e_detach(mdev, vpriv);
4110 mlx5e_destroy_netdev(mdev, priv);
4113 static void *mlx5e_get_netdev(void *vpriv)
4115 struct mlx5e_priv *priv = vpriv;
4117 return priv->netdev;
4120 static struct mlx5_interface mlx5e_interface = {
4122 .remove = mlx5e_remove,
4123 .attach = mlx5e_attach,
4124 .detach = mlx5e_detach,
4125 .event = mlx5e_async_event,
4126 .protocol = MLX5_INTERFACE_PROTOCOL_ETH,
4127 .get_dev = mlx5e_get_netdev,
4130 void mlx5e_init(void)
4132 mlx5e_build_ptys2ethtool_map();
4133 mlx5_register_interface(&mlx5e_interface);
4136 void mlx5e_cleanup(void)
4138 mlx5_unregister_interface(&mlx5e_interface);