drivers/net/ethernet/mellanox/mlx5/core/en_main.c

   1 /*
   2  * Copyright (c) 2015-2016, Mellanox Technologies. All rights reserved.
   3  *
   4  * This software is available to you under a choice of one of two
   5  * licenses.  You may choose to be licensed under the terms of the GNU
   6  * General Public License (GPL) Version 2, available from the file
   7  * COPYING in the main directory of this source tree, or the
   8  * OpenIB.org BSD license below:
   9  *
  10  *     Redistribution and use in source and binary forms, with or
  11  *     without modification, are permitted provided that the following
  12  *     conditions are met:
  13  *
  14  *      - Redistributions of source code must retain the above
  15  *        copyright notice, this list of conditions and the following
  16  *        disclaimer.
  17  *
  18  *      - Redistributions in binary form must reproduce the above
  19  *        copyright notice, this list of conditions and the following
  20  *        disclaimer in the documentation and/or other materials
  21  *        provided with the distribution.
  22  *
  23  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  24  * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  25  * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
  26  * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
  27  * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
  28  * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
  29  * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
  30  * SOFTWARE.
  31  */
  32
  33 #include <net/tc_act/tc_gact.h>
  34 #include <net/pkt_cls.h>
  35 #include <linux/mlx5/fs.h>
  36 #include <net/vxlan.h>
  37 #include <net/geneve.h>
  38 #include <linux/bpf.h>
  39 #include <linux/if_bridge.h>
  40 #include <net/page_pool.h>
  41 #include <net/xdp_sock_drv.h>
  42 #include "eswitch.h"
  43 #include "en.h"
  44 #include "en/txrx.h"
  45 #include "en_tc.h"
  46 #include "en_rep.h"
  47 #include "en_accel/ipsec.h"
  48 #include "en_accel/en_accel.h"
  49 #include "en_accel/tls.h"
  50 #include "accel/ipsec.h"
  51 #include "accel/tls.h"
  52 #include "lib/vxlan.h"
  53 #include "lib/clock.h"
  54 #include "en/port.h"
  55 #include "en/xdp.h"
  56 #include "lib/eq.h"
  57 #include "en/monitor_stats.h"
  58 #include "en/health.h"
  59 #include "en/params.h"
  60 #include "en/xsk/pool.h"
  61 #include "en/xsk/setup.h"
  62 #include "en/xsk/rx.h"
  63 #include "en/xsk/tx.h"
  64 #include "en/hv_vhca_stats.h"
  65 #include "en/devlink.h"
  66 #include "lib/mlx5.h"
  67 #include "en/ptp.h"
  68 #include "qos.h"
  69 #include "en/trap.h"
  70 #include "fpga/ipsec.h"
  71
  72 bool mlx5e_check_fragmented_striding_rq_cap(struct mlx5_core_dev *mdev)
  73 {
  74         bool striding_rq_umr = MLX5_CAP_GEN(mdev, striding_rq) &&
  75                 MLX5_CAP_GEN(mdev, umr_ptr_rlky) &&
  76                 MLX5_CAP_ETH(mdev, reg_umr_sq);
  77         u16 max_wqe_sz_cap = MLX5_CAP_GEN(mdev, max_wqe_sz_sq);
  78         bool inline_umr = MLX5E_UMR_WQE_INLINE_SZ <= max_wqe_sz_cap;
  79
  80         if (!striding_rq_umr)
  81                 return false;
  82         if (!inline_umr) {
  83                 mlx5_core_warn(mdev, "Cannot support Striding RQ: UMR WQE size (%d) exceeds maximum supported (%d).\n",
  84                                (int)MLX5E_UMR_WQE_INLINE_SZ, max_wqe_sz_cap);
  85                 return false;
  86         }
  87         return true;
  88 }
  89
  90 void mlx5e_update_carrier(struct mlx5e_priv *priv)
  91 {
  92         struct mlx5_core_dev *mdev = priv->mdev;
  93         u8 port_state;
  94         bool up;
  95
  96         port_state = mlx5_query_vport_state(mdev,
  97                                             MLX5_VPORT_STATE_OP_MOD_VNIC_VPORT,
  98                                             0);
  99
 100         up = port_state == VPORT_STATE_UP;
 101         if (up == netif_carrier_ok(priv->netdev))
 102                 netif_carrier_event(priv->netdev);
 103         if (up) {
 104                 netdev_info(priv->netdev, "Link up\n");
 105                 netif_carrier_on(priv->netdev);
 106         } else {
 107                 netdev_info(priv->netdev, "Link down\n");
 108                 netif_carrier_off(priv->netdev);
 109         }
 110 }
 111
 112 static void mlx5e_update_carrier_work(struct work_struct *work)
 113 {
 114         struct mlx5e_priv *priv = container_of(work, struct mlx5e_priv,
 115                                                update_carrier_work);
 116
 117         mutex_lock(&priv->state_lock);
 118         if (test_bit(MLX5E_STATE_OPENED, &priv->state))
 119                 if (priv->profile->update_carrier)
 120                         priv->profile->update_carrier(priv);
 121         mutex_unlock(&priv->state_lock);
 122 }
 123
 124 static void mlx5e_update_stats_work(struct work_struct *work)
 125 {
 126         struct mlx5e_priv *priv = container_of(work, struct mlx5e_priv,
 127                                                update_stats_work);
 128
 129         mutex_lock(&priv->state_lock);
 130         priv->profile->update_stats(priv);
 131         mutex_unlock(&priv->state_lock);
 132 }
 133
 134 void mlx5e_queue_update_stats(struct mlx5e_priv *priv)
 135 {
 136         if (!priv->profile->update_stats)
 137                 return;
 138
 139         if (unlikely(test_bit(MLX5E_STATE_DESTROYING, &priv->state)))
 140                 return;
 141
 142         queue_work(priv->wq, &priv->update_stats_work);
 143 }
 144
 145 static int async_event(struct notifier_block *nb, unsigned long event, void *data)
 146 {
 147         struct mlx5e_priv *priv = container_of(nb, struct mlx5e_priv, events_nb);
 148         struct mlx5_eqe   *eqe = data;
 149
 150         if (event != MLX5_EVENT_TYPE_PORT_CHANGE)
 151                 return NOTIFY_DONE;
 152
 153         switch (eqe->sub_type) {
 154         case MLX5_PORT_CHANGE_SUBTYPE_DOWN:
 155         case MLX5_PORT_CHANGE_SUBTYPE_ACTIVE:
 156                 queue_work(priv->wq, &priv->update_carrier_work);
 157                 break;
 158         default:
 159                 return NOTIFY_DONE;
 160         }
 161
 162         return NOTIFY_OK;
 163 }
 164
 165 static void mlx5e_enable_async_events(struct mlx5e_priv *priv)
 166 {
 167         priv->events_nb.notifier_call = async_event;
 168         mlx5_notifier_register(priv->mdev, &priv->events_nb);
 169 }
 170
 171 static void mlx5e_disable_async_events(struct mlx5e_priv *priv)
 172 {
 173         mlx5_notifier_unregister(priv->mdev, &priv->events_nb);
 174 }
 175
 176 static int blocking_event(struct notifier_block *nb, unsigned long event, void *data)
 177 {
 178         struct mlx5e_priv *priv = container_of(nb, struct mlx5e_priv, blocking_events_nb);
 179         int err;
 180
 181         switch (event) {
 182         case MLX5_DRIVER_EVENT_TYPE_TRAP:
 183                 err = mlx5e_handle_trap_event(priv, data);
 184                 break;
 185         default:
 186                 netdev_warn(priv->netdev, "Sync event: Unknown event %ld\n", event);
 187                 err = -EINVAL;
 188         }
 189         return err;
 190 }
 191
 192 static void mlx5e_enable_blocking_events(struct mlx5e_priv *priv)
 193 {
 194         priv->blocking_events_nb.notifier_call = blocking_event;
 195         mlx5_blocking_notifier_register(priv->mdev, &priv->blocking_events_nb);
 196 }
 197
 198 static void mlx5e_disable_blocking_events(struct mlx5e_priv *priv)
 199 {
 200         mlx5_blocking_notifier_unregister(priv->mdev, &priv->blocking_events_nb);
 201 }
 202
 203 static inline void mlx5e_build_umr_wqe(struct mlx5e_rq *rq,
 204                                        struct mlx5e_icosq *sq,
 205                                        struct mlx5e_umr_wqe *wqe)
 206 {
 207         struct mlx5_wqe_ctrl_seg      *cseg = &wqe->ctrl;
 208         struct mlx5_wqe_umr_ctrl_seg *ucseg = &wqe->uctrl;
 209         u8 ds_cnt = DIV_ROUND_UP(MLX5E_UMR_WQE_INLINE_SZ, MLX5_SEND_WQE_DS);
 210
 211         cseg->qpn_ds    = cpu_to_be32((sq->sqn << MLX5_WQE_CTRL_QPN_SHIFT) |
 212                                       ds_cnt);
 213         cseg->umr_mkey  = rq->mkey_be;
 214
 215         ucseg->flags = MLX5_UMR_TRANSLATION_OFFSET_EN | MLX5_UMR_INLINE;
 216         ucseg->xlt_octowords =
 217                 cpu_to_be16(MLX5_MTT_OCTW(MLX5_MPWRQ_PAGES_PER_WQE));
 218         ucseg->mkey_mask     = cpu_to_be64(MLX5_MKEY_MASK_FREE);
 219 }
 220
 221 static int mlx5e_rq_shampo_hd_alloc(struct mlx5e_rq *rq, int node)
 222 {
 223         rq->mpwqe.shampo = kvzalloc_node(sizeof(*rq->mpwqe.shampo),
 224                                          GFP_KERNEL, node);
 225         if (!rq->mpwqe.shampo)
 226                 return -ENOMEM;
 227         return 0;
 228 }
 229
 230 static void mlx5e_rq_shampo_hd_free(struct mlx5e_rq *rq)
 231 {
 232         kvfree(rq->mpwqe.shampo);
 233 }
 234
 235 static int mlx5e_rq_shampo_hd_info_alloc(struct mlx5e_rq *rq, int node)
 236 {
 237         struct mlx5e_shampo_hd *shampo = rq->mpwqe.shampo;
 238
 239         shampo->bitmap = bitmap_zalloc_node(shampo->hd_per_wq, GFP_KERNEL,
 240                                             node);
 241         if (!shampo->bitmap)
 242                 return -ENOMEM;
 243
 244         shampo->info = kvzalloc_node(array_size(shampo->hd_per_wq,
 245                                                 sizeof(*shampo->info)),
 246                                      GFP_KERNEL, node);
 247         if (!shampo->info) {
 248                 kvfree(shampo->bitmap);
 249                 return -ENOMEM;
 250         }
 251         return 0;
 252 }
 253
 254 static void mlx5e_rq_shampo_hd_info_free(struct mlx5e_rq *rq)
 255 {
 256         kvfree(rq->mpwqe.shampo->bitmap);
 257         kvfree(rq->mpwqe.shampo->info);
 258 }
 259
 260 static int mlx5e_rq_alloc_mpwqe_info(struct mlx5e_rq *rq, int node)
 261 {
 262         int wq_sz = mlx5_wq_ll_get_size(&rq->mpwqe.wq);
 263
 264         rq->mpwqe.info = kvzalloc_node(array_size(wq_sz,
 265                                                   sizeof(*rq->mpwqe.info)),
 266                                        GFP_KERNEL, node);
 267         if (!rq->mpwqe.info)
 268                 return -ENOMEM;
 269
 270         mlx5e_build_umr_wqe(rq, rq->icosq, &rq->mpwqe.umr_wqe);
 271
 272         return 0;
 273 }
 274
 275 static int mlx5e_create_umr_mtt_mkey(struct mlx5_core_dev *mdev,
 276                                      u64 npages, u8 page_shift, u32 *umr_mkey,
 277                                      dma_addr_t filler_addr)
 278 {
 279         struct mlx5_mtt *mtt;
 280         int inlen;
 281         void *mkc;
 282         u32 *in;
 283         int err;
 284         int i;
 285
 286         inlen = MLX5_ST_SZ_BYTES(create_mkey_in) + sizeof(*mtt) * npages;
 287
 288         in = kvzalloc(inlen, GFP_KERNEL);
 289         if (!in)
 290                 return -ENOMEM;
 291
 292         mkc = MLX5_ADDR_OF(create_mkey_in, in, memory_key_mkey_entry);
 293
 294         MLX5_SET(mkc, mkc, free, 1);
 295         MLX5_SET(mkc, mkc, umr_en, 1);
 296         MLX5_SET(mkc, mkc, lw, 1);
 297         MLX5_SET(mkc, mkc, lr, 1);
 298         MLX5_SET(mkc, mkc, access_mode_1_0, MLX5_MKC_ACCESS_MODE_MTT);
 299         mlx5e_mkey_set_relaxed_ordering(mdev, mkc);
 300         MLX5_SET(mkc, mkc, qpn, 0xffffff);
 301         MLX5_SET(mkc, mkc, pd, mdev->mlx5e_res.hw_objs.pdn);
 302         MLX5_SET64(mkc, mkc, len, npages << page_shift);
 303         MLX5_SET(mkc, mkc, translations_octword_size,
 304                  MLX5_MTT_OCTW(npages));
 305         MLX5_SET(mkc, mkc, log_page_size, page_shift);
 306         MLX5_SET(create_mkey_in, in, translations_octword_actual_size,
 307                  MLX5_MTT_OCTW(npages));
 308
 309         /* Initialize the mkey with all MTTs pointing to a default
 310          * page (filler_addr). When the channels are activated, UMR
 311          * WQEs will redirect the RX WQEs to the actual memory from
 312          * the RQ's pool, while the gaps (wqe_overflow) remain mapped
 313          * to the default page.
 314          */
 315         mtt = MLX5_ADDR_OF(create_mkey_in, in, klm_pas_mtt);
 316         for (i = 0 ; i < npages ; i++)
 317                 mtt[i].ptag = cpu_to_be64(filler_addr);
 318
 319         err = mlx5_core_create_mkey(mdev, umr_mkey, in, inlen);
 320
 321         kvfree(in);
 322         return err;
 323 }
 324
 325 static int mlx5e_create_umr_klm_mkey(struct mlx5_core_dev *mdev,
 326                                      u64 nentries,
 327                                      u32 *umr_mkey)
 328 {
 329         int inlen;
 330         void *mkc;
 331         u32 *in;
 332         int err;
 333
 334         inlen = MLX5_ST_SZ_BYTES(create_mkey_in);
 335
 336         in = kvzalloc(inlen, GFP_KERNEL);
 337         if (!in)
 338                 return -ENOMEM;
 339
 340         mkc = MLX5_ADDR_OF(create_mkey_in, in, memory_key_mkey_entry);
 341
 342         MLX5_SET(mkc, mkc, free, 1);
 343         MLX5_SET(mkc, mkc, umr_en, 1);
 344         MLX5_SET(mkc, mkc, lw, 1);
 345         MLX5_SET(mkc, mkc, lr, 1);
 346         MLX5_SET(mkc, mkc, access_mode_1_0, MLX5_MKC_ACCESS_MODE_KLMS);
 347         mlx5e_mkey_set_relaxed_ordering(mdev, mkc);
 348         MLX5_SET(mkc, mkc, qpn, 0xffffff);
 349         MLX5_SET(mkc, mkc, pd, mdev->mlx5e_res.hw_objs.pdn);
 350         MLX5_SET(mkc, mkc, translations_octword_size, nentries);
 351         MLX5_SET(mkc, mkc, length64, 1);
 352         err = mlx5_core_create_mkey(mdev, umr_mkey, in, inlen);
 353
 354         kvfree(in);
 355         return err;
 356 }
 357
 358 static int mlx5e_create_rq_umr_mkey(struct mlx5_core_dev *mdev, struct mlx5e_rq *rq)
 359 {
 360         u64 num_mtts = MLX5E_REQUIRED_MTTS(mlx5_wq_ll_get_size(&rq->mpwqe.wq));
 361
 362         return mlx5e_create_umr_mtt_mkey(mdev, num_mtts, PAGE_SHIFT,
 363                                          &rq->umr_mkey, rq->wqe_overflow.addr);
 364 }
 365
 366 static int mlx5e_create_rq_hd_umr_mkey(struct mlx5_core_dev *mdev,
 367                                        struct mlx5e_rq *rq)
 368 {
 369         u32 max_klm_size = BIT(MLX5_CAP_GEN(mdev, log_max_klm_list_size));
 370
 371         if (max_klm_size < rq->mpwqe.shampo->hd_per_wq) {
 372                 mlx5_core_err(mdev, "max klm list size 0x%x is smaller than shampo header buffer list size 0x%x\n",
 373                               max_klm_size, rq->mpwqe.shampo->hd_per_wq);
 374                 return -EINVAL;
 375         }
 376         return mlx5e_create_umr_klm_mkey(mdev, rq->mpwqe.shampo->hd_per_wq,
 377                                          &rq->mpwqe.shampo->mkey);
 378 }
 379
 380 static u64 mlx5e_get_mpwqe_offset(u16 wqe_ix)
 381 {
 382         return MLX5E_REQUIRED_MTTS(wqe_ix) << PAGE_SHIFT;
 383 }
 384
 385 static void mlx5e_init_frags_partition(struct mlx5e_rq *rq)
 386 {
 387         struct mlx5e_wqe_frag_info next_frag = {};
 388         struct mlx5e_wqe_frag_info *prev = NULL;
 389         int i;
 390
 391         next_frag.di = &rq->wqe.di[0];
 392
 393         for (i = 0; i < mlx5_wq_cyc_get_size(&rq->wqe.wq); i++) {
 394                 struct mlx5e_rq_frag_info *frag_info = &rq->wqe.info.arr[0];
 395                 struct mlx5e_wqe_frag_info *frag =
 396                         &rq->wqe.frags[i << rq->wqe.info.log_num_frags];
 397                 int f;
 398
 399                 for (f = 0; f < rq->wqe.info.num_frags; f++, frag++) {
 400                         if (next_frag.offset + frag_info[f].frag_stride > PAGE_SIZE) {
 401                                 next_frag.di++;
 402                                 next_frag.offset = 0;
 403                                 if (prev)
 404                                         prev->last_in_page = true;
 405                         }
 406                         *frag = next_frag;
 407
 408                         /* prepare next */
 409                         next_frag.offset += frag_info[f].frag_stride;
 410                         prev = frag;
 411                 }
 412         }
 413
 414         if (prev)
 415                 prev->last_in_page = true;
 416 }
 417
 418 int mlx5e_init_di_list(struct mlx5e_rq *rq, int wq_sz, int node)
 419 {
 420         int len = wq_sz << rq->wqe.info.log_num_frags;
 421
 422         rq->wqe.di = kvzalloc_node(array_size(len, sizeof(*rq->wqe.di)), GFP_KERNEL, node);
 423         if (!rq->wqe.di)
 424                 return -ENOMEM;
 425
 426         mlx5e_init_frags_partition(rq);
 427
 428         return 0;
 429 }
 430
 431 void mlx5e_free_di_list(struct mlx5e_rq *rq)
 432 {
 433         kvfree(rq->wqe.di);
 434 }
 435
 436 static void mlx5e_rq_err_cqe_work(struct work_struct *recover_work)
 437 {
 438         struct mlx5e_rq *rq = container_of(recover_work, struct mlx5e_rq, recover_work);
 439
 440         mlx5e_reporter_rq_cqe_err(rq);
 441 }
 442
 443 static int mlx5e_alloc_mpwqe_rq_drop_page(struct mlx5e_rq *rq)
 444 {
 445         rq->wqe_overflow.page = alloc_page(GFP_KERNEL);
 446         if (!rq->wqe_overflow.page)
 447                 return -ENOMEM;
 448
 449         rq->wqe_overflow.addr = dma_map_page(rq->pdev, rq->wqe_overflow.page, 0,
 450                                              PAGE_SIZE, rq->buff.map_dir);
 451         if (dma_mapping_error(rq->pdev, rq->wqe_overflow.addr)) {
 452                 __free_page(rq->wqe_overflow.page);
 453                 return -ENOMEM;
 454         }
 455         return 0;
 456 }
 457
 458 static void mlx5e_free_mpwqe_rq_drop_page(struct mlx5e_rq *rq)
 459 {
 460          dma_unmap_page(rq->pdev, rq->wqe_overflow.addr, PAGE_SIZE,
 461                         rq->buff.map_dir);
 462          __free_page(rq->wqe_overflow.page);
 463 }
 464
 465 static int mlx5e_init_rxq_rq(struct mlx5e_channel *c, struct mlx5e_params *params,
 466                              struct mlx5e_rq *rq)
 467 {
 468         struct mlx5_core_dev *mdev = c->mdev;
 469         int err;
 470
 471         rq->wq_type      = params->rq_wq_type;
 472         rq->pdev         = c->pdev;
 473         rq->netdev       = c->netdev;
 474         rq->priv         = c->priv;
 475         rq->tstamp       = c->tstamp;
 476         rq->clock        = &mdev->clock;
 477         rq->icosq        = &c->icosq;
 478         rq->ix           = c->ix;
 479         rq->mdev         = mdev;
 480         rq->hw_mtu       = MLX5E_SW2HW_MTU(params, params->sw_mtu);
 481         rq->xdpsq        = &c->rq_xdpsq;
 482         rq->stats        = &c->priv->channel_stats[c->ix].rq;
 483         rq->ptp_cyc2time = mlx5_rq_ts_translator(mdev);
 484         err = mlx5e_rq_set_handlers(rq, params, NULL);
 485         if (err)
 486                 return err;
 487
 488         return xdp_rxq_info_reg(&rq->xdp_rxq, rq->netdev, rq->ix, 0);
 489 }
 490
 491 static int mlx5_rq_shampo_alloc(struct mlx5_core_dev *mdev,
 492                                 struct mlx5e_params *params,
 493                                 struct mlx5e_rq_param *rqp,
 494                                 struct mlx5e_rq *rq,
 495                                 u32 *pool_size,
 496                                 int node)
 497 {
 498         void *wqc = MLX5_ADDR_OF(rqc, rqp->rqc, wq);
 499         int wq_size;
 500         int err;
 501
 502         if (!test_bit(MLX5E_RQ_STATE_SHAMPO, &rq->state))
 503                 return 0;
 504         err = mlx5e_rq_shampo_hd_alloc(rq, node);
 505         if (err)
 506                 goto out;
 507         rq->mpwqe.shampo->hd_per_wq =
 508                 mlx5e_shampo_hd_per_wq(mdev, params, rqp);
 509         err = mlx5e_create_rq_hd_umr_mkey(mdev, rq);
 510         if (err)
 511                 goto err_shampo_hd;
 512         err = mlx5e_rq_shampo_hd_info_alloc(rq, node);
 513         if (err)
 514                 goto err_shampo_info;
 515         rq->hw_gro_data = kvzalloc_node(sizeof(*rq->hw_gro_data), GFP_KERNEL, node);
 516         if (!rq->hw_gro_data) {
 517                 err = -ENOMEM;
 518                 goto err_hw_gro_data;
 519         }
 520         rq->mpwqe.shampo->key =
 521                 cpu_to_be32(rq->mpwqe.shampo->mkey);
 522         rq->mpwqe.shampo->hd_per_wqe =
 523                 mlx5e_shampo_hd_per_wqe(mdev, params, rqp);
 524         wq_size = BIT(MLX5_GET(wq, wqc, log_wq_sz));
 525         *pool_size += (rq->mpwqe.shampo->hd_per_wqe * wq_size) /
 526                      MLX5E_SHAMPO_WQ_HEADER_PER_PAGE;
 527         return 0;
 528
 529 err_hw_gro_data:
 530         mlx5e_rq_shampo_hd_info_free(rq);
 531 err_shampo_info:
 532         mlx5_core_destroy_mkey(mdev, rq->mpwqe.shampo->mkey);
 533 err_shampo_hd:
 534         mlx5e_rq_shampo_hd_free(rq);
 535 out:
 536         return err;
 537 }
 538
 539 static void mlx5e_rq_free_shampo(struct mlx5e_rq *rq)
 540 {
 541         if (!test_bit(MLX5E_RQ_STATE_SHAMPO, &rq->state))
 542                 return;
 543
 544         kvfree(rq->hw_gro_data);
 545         mlx5e_rq_shampo_hd_info_free(rq);
 546         mlx5_core_destroy_mkey(rq->mdev, rq->mpwqe.shampo->mkey);
 547         mlx5e_rq_shampo_hd_free(rq);
 548 }
 549
 550 static int mlx5e_alloc_rq(struct mlx5e_params *params,
 551                           struct mlx5e_xsk_param *xsk,
 552                           struct mlx5e_rq_param *rqp,
 553                           int node, struct mlx5e_rq *rq)
 554 {
 555         struct page_pool_params pp_params = { 0 };
 556         struct mlx5_core_dev *mdev = rq->mdev;
 557         void *rqc = rqp->rqc;
 558         void *rqc_wq = MLX5_ADDR_OF(rqc, rqc, wq);
 559         u32 pool_size;
 560         int wq_sz;
 561         int err;
 562         int i;
 563
 564         rqp->wq.db_numa_node = node;
 565         INIT_WORK(&rq->recover_work, mlx5e_rq_err_cqe_work);
 566
 567         if (params->xdp_prog)
 568                 bpf_prog_inc(params->xdp_prog);
 569         RCU_INIT_POINTER(rq->xdp_prog, params->xdp_prog);
 570
 571         rq->buff.map_dir = params->xdp_prog ? DMA_BIDIRECTIONAL : DMA_FROM_DEVICE;
 572         rq->buff.headroom = mlx5e_get_rq_headroom(mdev, params, xsk);
 573         pool_size = 1 << params->log_rq_mtu_frames;
 574
 575         switch (rq->wq_type) {
 576         case MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ:
 577                 err = mlx5_wq_ll_create(mdev, &rqp->wq, rqc_wq, &rq->mpwqe.wq,
 578                                         &rq->wq_ctrl);
 579                 if (err)
 580                         goto err_rq_xdp_prog;
 581
 582                 err = mlx5e_alloc_mpwqe_rq_drop_page(rq);
 583                 if (err)
 584                         goto err_rq_wq_destroy;
 585
 586                 rq->mpwqe.wq.db = &rq->mpwqe.wq.db[MLX5_RCV_DBR];
 587
 588                 wq_sz = mlx5_wq_ll_get_size(&rq->mpwqe.wq);
 589
 590                 pool_size = MLX5_MPWRQ_PAGES_PER_WQE <<
 591                         mlx5e_mpwqe_get_log_rq_size(params, xsk);
 592
 593                 rq->mpwqe.log_stride_sz = mlx5e_mpwqe_get_log_stride_size(mdev, params, xsk);
 594                 rq->mpwqe.num_strides =
 595                         BIT(mlx5e_mpwqe_get_log_num_strides(mdev, params, xsk));
 596
 597                 rq->buff.frame0_sz = (1 << rq->mpwqe.log_stride_sz);
 598
 599                 err = mlx5e_create_rq_umr_mkey(mdev, rq);
 600                 if (err)
 601                         goto err_rq_drop_page;
 602                 rq->mkey_be = cpu_to_be32(rq->umr_mkey);
 603
 604                 err = mlx5e_rq_alloc_mpwqe_info(rq, node);
 605                 if (err)
 606                         goto err_rq_mkey;
 607
 608                 err = mlx5_rq_shampo_alloc(mdev, params, rqp, rq, &pool_size, node);
 609                 if (err)
 610                         goto err_free_by_rq_type;
 611
 612                 break;
 613         default: /* MLX5_WQ_TYPE_CYCLIC */
 614                 err = mlx5_wq_cyc_create(mdev, &rqp->wq, rqc_wq, &rq->wqe.wq,
 615                                          &rq->wq_ctrl);
 616                 if (err)
 617                         goto err_rq_xdp_prog;
 618
 619                 rq->wqe.wq.db = &rq->wqe.wq.db[MLX5_RCV_DBR];
 620
 621                 wq_sz = mlx5_wq_cyc_get_size(&rq->wqe.wq);
 622
 623                 rq->wqe.info = rqp->frags_info;
 624                 rq->buff.frame0_sz = rq->wqe.info.arr[0].frag_stride;
 625
 626                 rq->wqe.frags =
 627                         kvzalloc_node(array_size(sizeof(*rq->wqe.frags),
 628                                         (wq_sz << rq->wqe.info.log_num_frags)),
 629                                       GFP_KERNEL, node);
 630                 if (!rq->wqe.frags) {
 631                         err = -ENOMEM;
 632                         goto err_rq_wq_destroy;
 633                 }
 634
 635                 err = mlx5e_init_di_list(rq, wq_sz, node);
 636                 if (err)
 637                         goto err_rq_frags;
 638
 639                 rq->mkey_be = cpu_to_be32(mdev->mlx5e_res.hw_objs.mkey);
 640         }
 641
 642         if (xsk) {
 643                 err = xdp_rxq_info_reg_mem_model(&rq->xdp_rxq,
 644                                                  MEM_TYPE_XSK_BUFF_POOL, NULL);
 645                 xsk_pool_set_rxq_info(rq->xsk_pool, &rq->xdp_rxq);
 646         } else {
 647                 /* Create a page_pool and register it with rxq */
 648                 pp_params.order     = 0;
 649                 pp_params.flags     = 0; /* No-internal DMA mapping in page_pool */
 650                 pp_params.pool_size = pool_size;
 651                 pp_params.nid       = node;
 652                 pp_params.dev       = rq->pdev;
 653                 pp_params.dma_dir   = rq->buff.map_dir;
 654
 655                 /* page_pool can be used even when there is no rq->xdp_prog,
 656                  * given page_pool does not handle DMA mapping there is no
 657                  * required state to clear. And page_pool gracefully handle
 658                  * elevated refcnt.
 659                  */
 660                 rq->page_pool = page_pool_create(&pp_params);
 661                 if (IS_ERR(rq->page_pool)) {
 662                         err = PTR_ERR(rq->page_pool);
 663                         rq->page_pool = NULL;
 664                         goto err_free_shampo;
 665                 }
 666                 if (xdp_rxq_info_is_reg(&rq->xdp_rxq))
 667                         err = xdp_rxq_info_reg_mem_model(&rq->xdp_rxq,
 668                                                          MEM_TYPE_PAGE_POOL, rq->page_pool);
 669         }
 670         if (err)
 671                 goto err_free_shampo;
 672
 673         for (i = 0; i < wq_sz; i++) {
 674                 if (rq->wq_type == MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ) {
 675                         struct mlx5e_rx_wqe_ll *wqe =
 676                                 mlx5_wq_ll_get_wqe(&rq->mpwqe.wq, i);
 677                         u32 byte_count =
 678                                 rq->mpwqe.num_strides << rq->mpwqe.log_stride_sz;
 679                         u64 dma_offset = mlx5e_get_mpwqe_offset(i);
 680                         u16 headroom = test_bit(MLX5E_RQ_STATE_SHAMPO, &rq->state) ?
 681                                        0 : rq->buff.headroom;
 682
 683                         wqe->data[0].addr = cpu_to_be64(dma_offset + headroom);
 684                         wqe->data[0].byte_count = cpu_to_be32(byte_count);
 685                         wqe->data[0].lkey = rq->mkey_be;
 686                 } else {
 687                         struct mlx5e_rx_wqe_cyc *wqe =
 688                                 mlx5_wq_cyc_get_wqe(&rq->wqe.wq, i);
 689                         int f;
 690
 691                         for (f = 0; f < rq->wqe.info.num_frags; f++) {
 692                                 u32 frag_size = rq->wqe.info.arr[f].frag_size |
 693                                         MLX5_HW_START_PADDING;
 694
 695                                 wqe->data[f].byte_count = cpu_to_be32(frag_size);
 696                                 wqe->data[f].lkey = rq->mkey_be;
 697                         }
 698                         /* check if num_frags is not a pow of two */
 699                         if (rq->wqe.info.num_frags < (1 << rq->wqe.info.log_num_frags)) {
 700                                 wqe->data[f].byte_count = 0;
 701                                 wqe->data[f].lkey = cpu_to_be32(MLX5_INVALID_LKEY);
 702                                 wqe->data[f].addr = 0;
 703                         }
 704                 }
 705         }
 706
 707         INIT_WORK(&rq->dim.work, mlx5e_rx_dim_work);
 708
 709         switch (params->rx_cq_moderation.cq_period_mode) {
 710         case MLX5_CQ_PERIOD_MODE_START_FROM_CQE:
 711                 rq->dim.mode = DIM_CQ_PERIOD_MODE_START_FROM_CQE;
 712                 break;
 713         case MLX5_CQ_PERIOD_MODE_START_FROM_EQE:
 714         default:
 715                 rq->dim.mode = DIM_CQ_PERIOD_MODE_START_FROM_EQE;
 716         }
 717
 718         rq->page_cache.head = 0;
 719         rq->page_cache.tail = 0;
 720
 721         return 0;
 722
 723 err_free_shampo:
 724         mlx5e_rq_free_shampo(rq);
 725 err_free_by_rq_type:
 726         switch (rq->wq_type) {
 727         case MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ:
 728                 kvfree(rq->mpwqe.info);
 729 err_rq_mkey:
 730                 mlx5_core_destroy_mkey(mdev, rq->umr_mkey);
 731 err_rq_drop_page:
 732                 mlx5e_free_mpwqe_rq_drop_page(rq);
 733                 break;
 734         default: /* MLX5_WQ_TYPE_CYCLIC */
 735                 mlx5e_free_di_list(rq);
 736 err_rq_frags:
 737                 kvfree(rq->wqe.frags);
 738         }
 739 err_rq_wq_destroy:
 740         mlx5_wq_destroy(&rq->wq_ctrl);
 741 err_rq_xdp_prog:
 742         if (params->xdp_prog)
 743                 bpf_prog_put(params->xdp_prog);
 744
 745         return err;
 746 }
 747
 748 static void mlx5e_free_rq(struct mlx5e_rq *rq)
 749 {
 750         struct bpf_prog *old_prog;
 751         int i;
 752
 753         if (xdp_rxq_info_is_reg(&rq->xdp_rxq)) {
 754                 old_prog = rcu_dereference_protected(rq->xdp_prog,
 755                                                      lockdep_is_held(&rq->priv->state_lock));
 756                 if (old_prog)
 757                         bpf_prog_put(old_prog);
 758         }
 759
 760         switch (rq->wq_type) {
 761         case MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ:
 762                 kvfree(rq->mpwqe.info);
 763                 mlx5_core_destroy_mkey(rq->mdev, rq->umr_mkey);
 764                 mlx5e_free_mpwqe_rq_drop_page(rq);
 765                 mlx5e_rq_free_shampo(rq);
 766                 break;
 767         default: /* MLX5_WQ_TYPE_CYCLIC */
 768                 kvfree(rq->wqe.frags);
 769                 mlx5e_free_di_list(rq);
 770         }
 771
 772         for (i = rq->page_cache.head; i != rq->page_cache.tail;
 773              i = (i + 1) & (MLX5E_CACHE_SIZE - 1)) {
 774                 struct mlx5e_dma_info *dma_info = &rq->page_cache.page_cache[i];
 775
 776                 /* With AF_XDP, page_cache is not used, so this loop is not
 777                  * entered, and it's safe to call mlx5e_page_release_dynamic
 778                  * directly.
 779                  */
 780                 mlx5e_page_release_dynamic(rq, dma_info, false);
 781         }
 782
 783         xdp_rxq_info_unreg(&rq->xdp_rxq);
 784         page_pool_destroy(rq->page_pool);
 785         mlx5_wq_destroy(&rq->wq_ctrl);
 786 }
 787
 788 int mlx5e_create_rq(struct mlx5e_rq *rq, struct mlx5e_rq_param *param)
 789 {
 790         struct mlx5_core_dev *mdev = rq->mdev;
 791         u8 ts_format;
 792         void *in;
 793         void *rqc;
 794         void *wq;
 795         int inlen;
 796         int err;
 797
 798         inlen = MLX5_ST_SZ_BYTES(create_rq_in) +
 799                 sizeof(u64) * rq->wq_ctrl.buf.npages;
 800         in = kvzalloc(inlen, GFP_KERNEL);
 801         if (!in)
 802                 return -ENOMEM;
 803
 804         ts_format = mlx5_is_real_time_rq(mdev) ?
 805                             MLX5_TIMESTAMP_FORMAT_REAL_TIME :
 806                             MLX5_TIMESTAMP_FORMAT_FREE_RUNNING;
 807         rqc = MLX5_ADDR_OF(create_rq_in, in, ctx);
 808         wq  = MLX5_ADDR_OF(rqc, rqc, wq);
 809
 810         memcpy(rqc, param->rqc, sizeof(param->rqc));
 811
 812         MLX5_SET(rqc,  rqc, cqn,                rq->cq.mcq.cqn);
 813         MLX5_SET(rqc,  rqc, state,              MLX5_RQC_STATE_RST);
 814         MLX5_SET(rqc,  rqc, ts_format,          ts_format);
 815         MLX5_SET(wq,   wq,  log_wq_pg_sz,       rq->wq_ctrl.buf.page_shift -
 816                                                 MLX5_ADAPTER_PAGE_SHIFT);
 817         MLX5_SET64(wq, wq,  dbr_addr,           rq->wq_ctrl.db.dma);
 818
 819         if (test_bit(MLX5E_RQ_STATE_SHAMPO, &rq->state)) {
 820                 MLX5_SET(wq, wq, log_headers_buffer_entry_num,
 821                          order_base_2(rq->mpwqe.shampo->hd_per_wq));
 822                 MLX5_SET(wq, wq, headers_mkey, rq->mpwqe.shampo->mkey);
 823         }
 824
 825         mlx5_fill_page_frag_array(&rq->wq_ctrl.buf,
 826                                   (__be64 *)MLX5_ADDR_OF(wq, wq, pas));
 827
 828         err = mlx5_core_create_rq(mdev, in, inlen, &rq->rqn);
 829
 830         kvfree(in);
 831
 832         return err;
 833 }
 834
 835 int mlx5e_modify_rq_state(struct mlx5e_rq *rq, int curr_state, int next_state)
 836 {
 837         struct mlx5_core_dev *mdev = rq->mdev;
 838
 839         void *in;
 840         void *rqc;
 841         int inlen;
 842         int err;
 843
 844         inlen = MLX5_ST_SZ_BYTES(modify_rq_in);
 845         in = kvzalloc(inlen, GFP_KERNEL);
 846         if (!in)
 847                 return -ENOMEM;
 848
 849         if (curr_state == MLX5_RQC_STATE_RST && next_state == MLX5_RQC_STATE_RDY)
 850                 mlx5e_rqwq_reset(rq);
 851
 852         rqc = MLX5_ADDR_OF(modify_rq_in, in, ctx);
 853
 854         MLX5_SET(modify_rq_in, in, rq_state, curr_state);
 855         MLX5_SET(rqc, rqc, state, next_state);
 856
 857         err = mlx5_core_modify_rq(mdev, rq->rqn, in);
 858
 859         kvfree(in);
 860
 861         return err;
 862 }
 863
 864 static int mlx5e_modify_rq_scatter_fcs(struct mlx5e_rq *rq, bool enable)
 865 {
 866         struct mlx5_core_dev *mdev = rq->mdev;
 867
 868         void *in;
 869         void *rqc;
 870         int inlen;
 871         int err;
 872
 873         inlen = MLX5_ST_SZ_BYTES(modify_rq_in);
 874         in = kvzalloc(inlen, GFP_KERNEL);
 875         if (!in)
 876                 return -ENOMEM;
 877
 878         rqc = MLX5_ADDR_OF(modify_rq_in, in, ctx);
 879
 880         MLX5_SET(modify_rq_in, in, rq_state, MLX5_RQC_STATE_RDY);
 881         MLX5_SET64(modify_rq_in, in, modify_bitmask,
 882                    MLX5_MODIFY_RQ_IN_MODIFY_BITMASK_SCATTER_FCS);
 883         MLX5_SET(rqc, rqc, scatter_fcs, enable);
 884         MLX5_SET(rqc, rqc, state, MLX5_RQC_STATE_RDY);
 885
 886         err = mlx5_core_modify_rq(mdev, rq->rqn, in);
 887
 888         kvfree(in);
 889
 890         return err;
 891 }
 892
 893 static int mlx5e_modify_rq_vsd(struct mlx5e_rq *rq, bool vsd)
 894 {
 895         struct mlx5_core_dev *mdev = rq->mdev;
 896         void *in;
 897         void *rqc;
 898         int inlen;
 899         int err;
 900
 901         inlen = MLX5_ST_SZ_BYTES(modify_rq_in);
 902         in = kvzalloc(inlen, GFP_KERNEL);
 903         if (!in)
 904                 return -ENOMEM;
 905
 906         rqc = MLX5_ADDR_OF(modify_rq_in, in, ctx);
 907
 908         MLX5_SET(modify_rq_in, in, rq_state, MLX5_RQC_STATE_RDY);
 909         MLX5_SET64(modify_rq_in, in, modify_bitmask,
 910                    MLX5_MODIFY_RQ_IN_MODIFY_BITMASK_VSD);
 911         MLX5_SET(rqc, rqc, vsd, vsd);
 912         MLX5_SET(rqc, rqc, state, MLX5_RQC_STATE_RDY);
 913
 914         err = mlx5_core_modify_rq(mdev, rq->rqn, in);
 915
 916         kvfree(in);
 917
 918         return err;
 919 }
 920
 921 void mlx5e_destroy_rq(struct mlx5e_rq *rq)
 922 {
 923         mlx5_core_destroy_rq(rq->mdev, rq->rqn);
 924 }
 925
 926 int mlx5e_wait_for_min_rx_wqes(struct mlx5e_rq *rq, int wait_time)
 927 {
 928         unsigned long exp_time = jiffies + msecs_to_jiffies(wait_time);
 929
 930         u16 min_wqes = mlx5_min_rx_wqes(rq->wq_type, mlx5e_rqwq_get_size(rq));
 931
 932         do {
 933                 if (mlx5e_rqwq_get_cur_sz(rq) >= min_wqes)
 934                         return 0;
 935
 936                 msleep(20);
 937         } while (time_before(jiffies, exp_time));
 938
 939         netdev_warn(rq->netdev, "Failed to get min RX wqes on Channel[%d] RQN[0x%x] wq cur_sz(%d) min_rx_wqes(%d)\n",
 940                     rq->ix, rq->rqn, mlx5e_rqwq_get_cur_sz(rq), min_wqes);
 941
 942         mlx5e_reporter_rx_timeout(rq);
 943         return -ETIMEDOUT;
 944 }
 945
 946 void mlx5e_free_rx_in_progress_descs(struct mlx5e_rq *rq)
 947 {
 948         struct mlx5_wq_ll *wq;
 949         u16 head;
 950         int i;
 951
 952         if (rq->wq_type != MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ)
 953                 return;
 954
 955         wq = &rq->mpwqe.wq;
 956         head = wq->head;
 957
 958         /* Outstanding UMR WQEs (in progress) start at wq->head */
 959         for (i = 0; i < rq->mpwqe.umr_in_progress; i++) {
 960                 rq->dealloc_wqe(rq, head);
 961                 head = mlx5_wq_ll_get_wqe_next_ix(wq, head);
 962         }
 963
 964         if (test_bit(MLX5E_RQ_STATE_SHAMPO, &rq->state)) {
 965                 u16 len;
 966
 967                 len = (rq->mpwqe.shampo->pi - rq->mpwqe.shampo->ci) &
 968                       (rq->mpwqe.shampo->hd_per_wq - 1);
 969                 mlx5e_shampo_dealloc_hd(rq, len, rq->mpwqe.shampo->ci, false);
 970                 rq->mpwqe.shampo->pi = rq->mpwqe.shampo->ci;
 971         }
 972
 973         rq->mpwqe.actual_wq_head = wq->head;
 974         rq->mpwqe.umr_in_progress = 0;
 975         rq->mpwqe.umr_completed = 0;
 976 }
 977
 978 void mlx5e_free_rx_descs(struct mlx5e_rq *rq)
 979 {
 980         __be16 wqe_ix_be;
 981         u16 wqe_ix;
 982
 983         if (rq->wq_type == MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ) {
 984                 struct mlx5_wq_ll *wq = &rq->mpwqe.wq;
 985
 986                 mlx5e_free_rx_in_progress_descs(rq);
 987
 988                 while (!mlx5_wq_ll_is_empty(wq)) {
 989                         struct mlx5e_rx_wqe_ll *wqe;
 990
 991                         wqe_ix_be = *wq->tail_next;
 992                         wqe_ix    = be16_to_cpu(wqe_ix_be);
 993                         wqe       = mlx5_wq_ll_get_wqe(wq, wqe_ix);
 994                         rq->dealloc_wqe(rq, wqe_ix);
 995                         mlx5_wq_ll_pop(wq, wqe_ix_be,
 996                                        &wqe->next.next_wqe_index);
 997                 }
 998
 999                 if (test_bit(MLX5E_RQ_STATE_SHAMPO, &rq->state))
1000                         mlx5e_shampo_dealloc_hd(rq, rq->mpwqe.shampo->hd_per_wq,
1001                                                 0, true);
1002         } else {
1003                 struct mlx5_wq_cyc *wq = &rq->wqe.wq;
1004
1005                 while (!mlx5_wq_cyc_is_empty(wq)) {
1006                         wqe_ix = mlx5_wq_cyc_get_tail(wq);
1007                         rq->dealloc_wqe(rq, wqe_ix);
1008                         mlx5_wq_cyc_pop(wq);
1009                 }
1010         }
1011
1012 }
1013
1014 int mlx5e_open_rq(struct mlx5e_params *params, struct mlx5e_rq_param *param,
1015                   struct mlx5e_xsk_param *xsk, int node,
1016                   struct mlx5e_rq *rq)
1017 {
1018         struct mlx5_core_dev *mdev = rq->mdev;
1019         int err;
1020
1021         if (params->packet_merge.type == MLX5E_PACKET_MERGE_SHAMPO)
1022                 __set_bit(MLX5E_RQ_STATE_SHAMPO, &rq->state);
1023
1024         err = mlx5e_alloc_rq(params, xsk, param, node, rq);
1025         if (err)
1026                 return err;
1027
1028         err = mlx5e_create_rq(rq, param);
1029         if (err)
1030                 goto err_free_rq;
1031
1032         err = mlx5e_modify_rq_state(rq, MLX5_RQC_STATE_RST, MLX5_RQC_STATE_RDY);
1033         if (err)
1034                 goto err_destroy_rq;
1035
1036         if (mlx5e_is_tls_on(rq->priv) && !mlx5e_accel_is_ktls_device(mdev))
1037                 __set_bit(MLX5E_RQ_STATE_FPGA_TLS, &rq->state); /* must be FPGA */
1038
1039         if (MLX5_CAP_ETH(mdev, cqe_checksum_full))
1040                 __set_bit(MLX5E_RQ_STATE_CSUM_FULL, &rq->state);
1041
1042         if (params->rx_dim_enabled)
1043                 __set_bit(MLX5E_RQ_STATE_AM, &rq->state);
1044
1045         /* We disable csum_complete when XDP is enabled since
1046          * XDP programs might manipulate packets which will render
1047          * skb->checksum incorrect.
1048          */
1049         if (MLX5E_GET_PFLAG(params, MLX5E_PFLAG_RX_NO_CSUM_COMPLETE) || params->xdp_prog)
1050                 __set_bit(MLX5E_RQ_STATE_NO_CSUM_COMPLETE, &rq->state);
1051
1052         /* For CQE compression on striding RQ, use stride index provided by
1053          * HW if capability is supported.
1054          */
1055         if (MLX5E_GET_PFLAG(params, MLX5E_PFLAG_RX_STRIDING_RQ) &&
1056             MLX5_CAP_GEN(mdev, mini_cqe_resp_stride_index))
1057                 __set_bit(MLX5E_RQ_STATE_MINI_CQE_HW_STRIDX, &rq->state);
1058
1059         return 0;
1060
1061 err_destroy_rq:
1062         mlx5e_destroy_rq(rq);
1063 err_free_rq:
1064         mlx5e_free_rq(rq);
1065
1066         return err;
1067 }
1068
1069 void mlx5e_activate_rq(struct mlx5e_rq *rq)
1070 {
1071         set_bit(MLX5E_RQ_STATE_ENABLED, &rq->state);
1072         if (rq->icosq) {
1073                 mlx5e_trigger_irq(rq->icosq);
1074         } else {
1075                 local_bh_disable();
1076                 napi_schedule(rq->cq.napi);
1077                 local_bh_enable();
1078         }
1079 }
1080
1081 void mlx5e_deactivate_rq(struct mlx5e_rq *rq)
1082 {
1083         clear_bit(MLX5E_RQ_STATE_ENABLED, &rq->state);
1084         synchronize_net(); /* Sync with NAPI to prevent mlx5e_post_rx_wqes. */
1085 }
1086
1087 void mlx5e_close_rq(struct mlx5e_rq *rq)
1088 {
1089         cancel_work_sync(&rq->dim.work);
1090         if (rq->icosq)
1091                 cancel_work_sync(&rq->icosq->recover_work);
1092         cancel_work_sync(&rq->recover_work);
1093         mlx5e_destroy_rq(rq);
1094         mlx5e_free_rx_descs(rq);
1095         mlx5e_free_rq(rq);
1096 }
1097
1098 static void mlx5e_free_xdpsq_db(struct mlx5e_xdpsq *sq)
1099 {
1100         kvfree(sq->db.xdpi_fifo.xi);
1101         kvfree(sq->db.wqe_info);
1102 }
1103
1104 static int mlx5e_alloc_xdpsq_fifo(struct mlx5e_xdpsq *sq, int numa)
1105 {
1106         struct mlx5e_xdp_info_fifo *xdpi_fifo = &sq->db.xdpi_fifo;
1107         int wq_sz        = mlx5_wq_cyc_get_size(&sq->wq);
1108         int dsegs_per_wq = wq_sz * MLX5_SEND_WQEBB_NUM_DS;
1109         size_t size;
1110
1111         size = array_size(sizeof(*xdpi_fifo->xi), dsegs_per_wq);
1112         xdpi_fifo->xi = kvzalloc_node(size, GFP_KERNEL, numa);
1113         if (!xdpi_fifo->xi)
1114                 return -ENOMEM;
1115
1116         xdpi_fifo->pc   = &sq->xdpi_fifo_pc;
1117         xdpi_fifo->cc   = &sq->xdpi_fifo_cc;
1118         xdpi_fifo->mask = dsegs_per_wq - 1;
1119
1120         return 0;
1121 }
1122
1123 static int mlx5e_alloc_xdpsq_db(struct mlx5e_xdpsq *sq, int numa)
1124 {
1125         int wq_sz = mlx5_wq_cyc_get_size(&sq->wq);
1126         size_t size;
1127         int err;
1128
1129         size = array_size(sizeof(*sq->db.wqe_info), wq_sz);
1130         sq->db.wqe_info = kvzalloc_node(size, GFP_KERNEL, numa);
1131         if (!sq->db.wqe_info)
1132                 return -ENOMEM;
1133
1134         err = mlx5e_alloc_xdpsq_fifo(sq, numa);
1135         if (err) {
1136                 mlx5e_free_xdpsq_db(sq);
1137                 return err;
1138         }
1139
1140         return 0;
1141 }
1142
1143 static int mlx5e_alloc_xdpsq(struct mlx5e_channel *c,
1144                              struct mlx5e_params *params,
1145                              struct xsk_buff_pool *xsk_pool,
1146                              struct mlx5e_sq_param *param,
1147                              struct mlx5e_xdpsq *sq,
1148                              bool is_redirect)
1149 {
1150         void *sqc_wq               = MLX5_ADDR_OF(sqc, param->sqc, wq);
1151         struct mlx5_core_dev *mdev = c->mdev;
1152         struct mlx5_wq_cyc *wq = &sq->wq;
1153         int err;
1154
1155         sq->pdev      = c->pdev;
1156         sq->mkey_be   = c->mkey_be;
1157         sq->channel   = c;
1158         sq->uar_map   = mdev->mlx5e_res.hw_objs.bfreg.map;
1159         sq->min_inline_mode = params->tx_min_inline_mode;
1160         sq->hw_mtu    = MLX5E_SW2HW_MTU(params, params->sw_mtu);
1161         sq->xsk_pool  = xsk_pool;
1162
1163         sq->stats = sq->xsk_pool ?
1164                 &c->priv->channel_stats[c->ix].xsksq :
1165                 is_redirect ?
1166                         &c->priv->channel_stats[c->ix].xdpsq :
1167                         &c->priv->channel_stats[c->ix].rq_xdpsq;
1168
1169         param->wq.db_numa_node = cpu_to_node(c->cpu);
1170         err = mlx5_wq_cyc_create(mdev, &param->wq, sqc_wq, wq, &sq->wq_ctrl);
1171         if (err)
1172                 return err;
1173         wq->db = &wq->db[MLX5_SND_DBR];
1174
1175         err = mlx5e_alloc_xdpsq_db(sq, cpu_to_node(c->cpu));
1176         if (err)
1177                 goto err_sq_wq_destroy;
1178
1179         return 0;
1180
1181 err_sq_wq_destroy:
1182         mlx5_wq_destroy(&sq->wq_ctrl);
1183
1184         return err;
1185 }
1186
1187 static void mlx5e_free_xdpsq(struct mlx5e_xdpsq *sq)
1188 {
1189         mlx5e_free_xdpsq_db(sq);
1190         mlx5_wq_destroy(&sq->wq_ctrl);
1191 }
1192
1193 static void mlx5e_free_icosq_db(struct mlx5e_icosq *sq)
1194 {
1195         kvfree(sq->db.wqe_info);
1196 }
1197
1198 static int mlx5e_alloc_icosq_db(struct mlx5e_icosq *sq, int numa)
1199 {
1200         int wq_sz = mlx5_wq_cyc_get_size(&sq->wq);
1201         size_t size;
1202
1203         size = array_size(wq_sz, sizeof(*sq->db.wqe_info));
1204         sq->db.wqe_info = kvzalloc_node(size, GFP_KERNEL, numa);
1205         if (!sq->db.wqe_info)
1206                 return -ENOMEM;
1207
1208         return 0;
1209 }
1210
1211 static void mlx5e_icosq_err_cqe_work(struct work_struct *recover_work)
1212 {
1213         struct mlx5e_icosq *sq = container_of(recover_work, struct mlx5e_icosq,
1214                                               recover_work);
1215
1216         mlx5e_reporter_icosq_cqe_err(sq);
1217 }
1218
1219 static int mlx5e_alloc_icosq(struct mlx5e_channel *c,
1220                              struct mlx5e_sq_param *param,
1221                              struct mlx5e_icosq *sq)
1222 {
1223         void *sqc_wq               = MLX5_ADDR_OF(sqc, param->sqc, wq);
1224         struct mlx5_core_dev *mdev = c->mdev;
1225         struct mlx5_wq_cyc *wq = &sq->wq;
1226         int err;
1227
1228         sq->channel   = c;
1229         sq->uar_map   = mdev->mlx5e_res.hw_objs.bfreg.map;
1230         sq->reserved_room = param->stop_room;
1231
1232         param->wq.db_numa_node = cpu_to_node(c->cpu);
1233         err = mlx5_wq_cyc_create(mdev, &param->wq, sqc_wq, wq, &sq->wq_ctrl);
1234         if (err)
1235                 return err;
1236         wq->db = &wq->db[MLX5_SND_DBR];
1237
1238         err = mlx5e_alloc_icosq_db(sq, cpu_to_node(c->cpu));
1239         if (err)
1240                 goto err_sq_wq_destroy;
1241
1242         INIT_WORK(&sq->recover_work, mlx5e_icosq_err_cqe_work);
1243
1244         return 0;
1245
1246 err_sq_wq_destroy:
1247         mlx5_wq_destroy(&sq->wq_ctrl);
1248
1249         return err;
1250 }
1251
1252 static void mlx5e_free_icosq(struct mlx5e_icosq *sq)
1253 {
1254         mlx5e_free_icosq_db(sq);
1255         mlx5_wq_destroy(&sq->wq_ctrl);
1256 }
1257
1258 void mlx5e_free_txqsq_db(struct mlx5e_txqsq *sq)
1259 {
1260         kvfree(sq->db.wqe_info);
1261         kvfree(sq->db.skb_fifo.fifo);
1262         kvfree(sq->db.dma_fifo);
1263 }
1264
1265 int mlx5e_alloc_txqsq_db(struct mlx5e_txqsq *sq, int numa)
1266 {
1267         int wq_sz = mlx5_wq_cyc_get_size(&sq->wq);
1268         int df_sz = wq_sz * MLX5_SEND_WQEBB_NUM_DS;
1269
1270         sq->db.dma_fifo = kvzalloc_node(array_size(df_sz,
1271                                                    sizeof(*sq->db.dma_fifo)),
1272                                         GFP_KERNEL, numa);
1273         sq->db.skb_fifo.fifo = kvzalloc_node(array_size(df_sz,
1274                                                         sizeof(*sq->db.skb_fifo.fifo)),
1275                                         GFP_KERNEL, numa);
1276         sq->db.wqe_info = kvzalloc_node(array_size(wq_sz,
1277                                                    sizeof(*sq->db.wqe_info)),
1278                                         GFP_KERNEL, numa);
1279         if (!sq->db.dma_fifo || !sq->db.skb_fifo.fifo || !sq->db.wqe_info) {
1280                 mlx5e_free_txqsq_db(sq);
1281                 return -ENOMEM;
1282         }
1283
1284         sq->dma_fifo_mask = df_sz - 1;
1285
1286         sq->db.skb_fifo.pc   = &sq->skb_fifo_pc;
1287         sq->db.skb_fifo.cc   = &sq->skb_fifo_cc;
1288         sq->db.skb_fifo.mask = df_sz - 1;
1289
1290         return 0;
1291 }
1292
1293 static int mlx5e_alloc_txqsq(struct mlx5e_channel *c,
1294                              int txq_ix,
1295                              struct mlx5e_params *params,
1296                              struct mlx5e_sq_param *param,
1297                              struct mlx5e_txqsq *sq,
1298                              int tc)
1299 {
1300         void *sqc_wq               = MLX5_ADDR_OF(sqc, param->sqc, wq);
1301         struct mlx5_core_dev *mdev = c->mdev;
1302         struct mlx5_wq_cyc *wq = &sq->wq;
1303         int err;
1304
1305         sq->pdev      = c->pdev;
1306         sq->tstamp    = c->tstamp;
1307         sq->clock     = &mdev->clock;
1308         sq->mkey_be   = c->mkey_be;
1309         sq->netdev    = c->netdev;
1310         sq->mdev      = c->mdev;
1311         sq->priv      = c->priv;
1312         sq->ch_ix     = c->ix;
1313         sq->txq_ix    = txq_ix;
1314         sq->uar_map   = mdev->mlx5e_res.hw_objs.bfreg.map;
1315         sq->min_inline_mode = params->tx_min_inline_mode;
1316         sq->hw_mtu    = MLX5E_SW2HW_MTU(params, params->sw_mtu);
1317         INIT_WORK(&sq->recover_work, mlx5e_tx_err_cqe_work);
1318         if (!MLX5_CAP_ETH(mdev, wqe_vlan_insert))
1319                 set_bit(MLX5E_SQ_STATE_VLAN_NEED_L2_INLINE, &sq->state);
1320         if (MLX5_IPSEC_DEV(c->priv->mdev))
1321                 set_bit(MLX5E_SQ_STATE_IPSEC, &sq->state);
1322         if (param->is_mpw)
1323                 set_bit(MLX5E_SQ_STATE_MPWQE, &sq->state);
1324         sq->stop_room = param->stop_room;
1325         sq->ptp_cyc2time = mlx5_sq_ts_translator(mdev);
1326
1327         param->wq.db_numa_node = cpu_to_node(c->cpu);
1328         err = mlx5_wq_cyc_create(mdev, &param->wq, sqc_wq, wq, &sq->wq_ctrl);
1329         if (err)
1330                 return err;
1331         wq->db    = &wq->db[MLX5_SND_DBR];
1332
1333         err = mlx5e_alloc_txqsq_db(sq, cpu_to_node(c->cpu));
1334         if (err)
1335                 goto err_sq_wq_destroy;
1336
1337         INIT_WORK(&sq->dim.work, mlx5e_tx_dim_work);
1338         sq->dim.mode = params->tx_cq_moderation.cq_period_mode;
1339
1340         return 0;
1341
1342 err_sq_wq_destroy:
1343         mlx5_wq_destroy(&sq->wq_ctrl);
1344
1345         return err;
1346 }
1347
1348 void mlx5e_free_txqsq(struct mlx5e_txqsq *sq)
1349 {
1350         mlx5e_free_txqsq_db(sq);
1351         mlx5_wq_destroy(&sq->wq_ctrl);
1352 }
1353
1354 static int mlx5e_create_sq(struct mlx5_core_dev *mdev,
1355                            struct mlx5e_sq_param *param,
1356                            struct mlx5e_create_sq_param *csp,
1357                            u32 *sqn)
1358 {
1359         u8 ts_format;
1360         void *in;
1361         void *sqc;
1362         void *wq;
1363         int inlen;
1364         int err;
1365
1366         inlen = MLX5_ST_SZ_BYTES(create_sq_in) +
1367                 sizeof(u64) * csp->wq_ctrl->buf.npages;
1368         in = kvzalloc(inlen, GFP_KERNEL);
1369         if (!in)
1370                 return -ENOMEM;
1371
1372         ts_format = mlx5_is_real_time_sq(mdev) ?
1373                             MLX5_TIMESTAMP_FORMAT_REAL_TIME :
1374                             MLX5_TIMESTAMP_FORMAT_FREE_RUNNING;
1375         sqc = MLX5_ADDR_OF(create_sq_in, in, ctx);
1376         wq = MLX5_ADDR_OF(sqc, sqc, wq);
1377
1378         memcpy(sqc, param->sqc, sizeof(param->sqc));
1379         MLX5_SET(sqc,  sqc, tis_lst_sz, csp->tis_lst_sz);
1380         MLX5_SET(sqc,  sqc, tis_num_0, csp->tisn);
1381         MLX5_SET(sqc,  sqc, cqn, csp->cqn);
1382         MLX5_SET(sqc,  sqc, ts_cqe_to_dest_cqn, csp->ts_cqe_to_dest_cqn);
1383         MLX5_SET(sqc,  sqc, ts_format, ts_format);
1384
1385
1386         if (MLX5_CAP_ETH(mdev, wqe_inline_mode) == MLX5_CAP_INLINE_MODE_VPORT_CONTEXT)
1387                 MLX5_SET(sqc,  sqc, min_wqe_inline_mode, csp->min_inline_mode);
1388
1389         MLX5_SET(sqc,  sqc, state, MLX5_SQC_STATE_RST);
1390         MLX5_SET(sqc,  sqc, flush_in_error_en, 1);
1391
1392         MLX5_SET(wq,   wq, wq_type,       MLX5_WQ_TYPE_CYCLIC);
1393         MLX5_SET(wq,   wq, uar_page,      mdev->mlx5e_res.hw_objs.bfreg.index);
1394         MLX5_SET(wq,   wq, log_wq_pg_sz,  csp->wq_ctrl->buf.page_shift -
1395                                           MLX5_ADAPTER_PAGE_SHIFT);
1396         MLX5_SET64(wq, wq, dbr_addr,      csp->wq_ctrl->db.dma);
1397
1398         mlx5_fill_page_frag_array(&csp->wq_ctrl->buf,
1399                                   (__be64 *)MLX5_ADDR_OF(wq, wq, pas));
1400
1401         err = mlx5_core_create_sq(mdev, in, inlen, sqn);
1402
1403         kvfree(in);
1404
1405         return err;
1406 }
1407
1408 int mlx5e_modify_sq(struct mlx5_core_dev *mdev, u32 sqn,
1409                     struct mlx5e_modify_sq_param *p)
1410 {
1411         u64 bitmask = 0;
1412         void *in;
1413         void *sqc;
1414         int inlen;
1415         int err;
1416
1417         inlen = MLX5_ST_SZ_BYTES(modify_sq_in);
1418         in = kvzalloc(inlen, GFP_KERNEL);
1419         if (!in)
1420                 return -ENOMEM;
1421
1422         sqc = MLX5_ADDR_OF(modify_sq_in, in, ctx);
1423
1424         MLX5_SET(modify_sq_in, in, sq_state, p->curr_state);
1425         MLX5_SET(sqc, sqc, state, p->next_state);
1426         if (p->rl_update && p->next_state == MLX5_SQC_STATE_RDY) {
1427                 bitmask |= 1;
1428                 MLX5_SET(sqc, sqc, packet_pacing_rate_limit_index, p->rl_index);
1429         }
1430         if (p->qos_update && p->next_state == MLX5_SQC_STATE_RDY) {
1431                 bitmask |= 1 << 2;
1432                 MLX5_SET(sqc, sqc, qos_queue_group_id, p->qos_queue_group_id);
1433         }
1434         MLX5_SET64(modify_sq_in, in, modify_bitmask, bitmask);
1435
1436         err = mlx5_core_modify_sq(mdev, sqn, in);
1437
1438         kvfree(in);
1439
1440         return err;
1441 }
1442
1443 static void mlx5e_destroy_sq(struct mlx5_core_dev *mdev, u32 sqn)
1444 {
1445         mlx5_core_destroy_sq(mdev, sqn);
1446 }
1447
1448 int mlx5e_create_sq_rdy(struct mlx5_core_dev *mdev,
1449                         struct mlx5e_sq_param *param,
1450                         struct mlx5e_create_sq_param *csp,
1451                         u16 qos_queue_group_id,
1452                         u32 *sqn)
1453 {
1454         struct mlx5e_modify_sq_param msp = {0};
1455         int err;
1456
1457         err = mlx5e_create_sq(mdev, param, csp, sqn);
1458         if (err)
1459                 return err;
1460
1461         msp.curr_state = MLX5_SQC_STATE_RST;
1462         msp.next_state = MLX5_SQC_STATE_RDY;
1463         if (qos_queue_group_id) {
1464                 msp.qos_update = true;
1465                 msp.qos_queue_group_id = qos_queue_group_id;
1466         }
1467         err = mlx5e_modify_sq(mdev, *sqn, &msp);
1468         if (err)
1469                 mlx5e_destroy_sq(mdev, *sqn);
1470
1471         return err;
1472 }
1473
1474 static int mlx5e_set_sq_maxrate(struct net_device *dev,
1475                                 struct mlx5e_txqsq *sq, u32 rate);
1476
1477 int mlx5e_open_txqsq(struct mlx5e_channel *c, u32 tisn, int txq_ix,
1478                      struct mlx5e_params *params, struct mlx5e_sq_param *param,
1479                      struct mlx5e_txqsq *sq, int tc, u16 qos_queue_group_id,
1480                      struct mlx5e_sq_stats *sq_stats)
1481 {
1482         struct mlx5e_create_sq_param csp = {};
1483         u32 tx_rate;
1484         int err;
1485
1486         err = mlx5e_alloc_txqsq(c, txq_ix, params, param, sq, tc);
1487         if (err)
1488                 return err;
1489
1490         sq->stats = sq_stats;
1491
1492         csp.tisn            = tisn;
1493         csp.tis_lst_sz      = 1;
1494         csp.cqn             = sq->cq.mcq.cqn;
1495         csp.wq_ctrl         = &sq->wq_ctrl;
1496         csp.min_inline_mode = sq->min_inline_mode;
1497         err = mlx5e_create_sq_rdy(c->mdev, param, &csp, qos_queue_group_id, &sq->sqn);
1498         if (err)
1499                 goto err_free_txqsq;
1500
1501         tx_rate = c->priv->tx_rates[sq->txq_ix];
1502         if (tx_rate)
1503                 mlx5e_set_sq_maxrate(c->netdev, sq, tx_rate);
1504
1505         if (params->tx_dim_enabled)
1506                 sq->state |= BIT(MLX5E_SQ_STATE_AM);
1507
1508         return 0;
1509
1510 err_free_txqsq:
1511         mlx5e_free_txqsq(sq);
1512
1513         return err;
1514 }
1515
1516 void mlx5e_activate_txqsq(struct mlx5e_txqsq *sq)
1517 {
1518         sq->txq = netdev_get_tx_queue(sq->netdev, sq->txq_ix);
1519         set_bit(MLX5E_SQ_STATE_ENABLED, &sq->state);
1520         netdev_tx_reset_queue(sq->txq);
1521         netif_tx_start_queue(sq->txq);
1522 }
1523
1524 void mlx5e_tx_disable_queue(struct netdev_queue *txq)
1525 {
1526         __netif_tx_lock_bh(txq);
1527         netif_tx_stop_queue(txq);
1528         __netif_tx_unlock_bh(txq);
1529 }
1530
1531 void mlx5e_deactivate_txqsq(struct mlx5e_txqsq *sq)
1532 {
1533         struct mlx5_wq_cyc *wq = &sq->wq;
1534
1535         clear_bit(MLX5E_SQ_STATE_ENABLED, &sq->state);
1536         synchronize_net(); /* Sync with NAPI to prevent netif_tx_wake_queue. */
1537
1538         mlx5e_tx_disable_queue(sq->txq);
1539
1540         /* last doorbell out, godspeed .. */
1541         if (mlx5e_wqc_has_room_for(wq, sq->cc, sq->pc, 1)) {
1542                 u16 pi = mlx5_wq_cyc_ctr2ix(wq, sq->pc);
1543                 struct mlx5e_tx_wqe *nop;
1544
1545                 sq->db.wqe_info[pi] = (struct mlx5e_tx_wqe_info) {
1546                         .num_wqebbs = 1,
1547                 };
1548
1549                 nop = mlx5e_post_nop(wq, sq->sqn, &sq->pc);
1550                 mlx5e_notify_hw(wq, sq->pc, sq->uar_map, &nop->ctrl);
1551         }
1552 }
1553
1554 void mlx5e_close_txqsq(struct mlx5e_txqsq *sq)
1555 {
1556         struct mlx5_core_dev *mdev = sq->mdev;
1557         struct mlx5_rate_limit rl = {0};
1558
1559         cancel_work_sync(&sq->dim.work);
1560         cancel_work_sync(&sq->recover_work);
1561         mlx5e_destroy_sq(mdev, sq->sqn);
1562         if (sq->rate_limit) {
1563                 rl.rate = sq->rate_limit;
1564                 mlx5_rl_remove_rate(mdev, &rl);
1565         }
1566         mlx5e_free_txqsq_descs(sq);
1567         mlx5e_free_txqsq(sq);
1568 }
1569
1570 void mlx5e_tx_err_cqe_work(struct work_struct *recover_work)
1571 {
1572         struct mlx5e_txqsq *sq = container_of(recover_work, struct mlx5e_txqsq,
1573                                               recover_work);
1574
1575         mlx5e_reporter_tx_err_cqe(sq);
1576 }
1577
1578 int mlx5e_open_icosq(struct mlx5e_channel *c, struct mlx5e_params *params,
1579                      struct mlx5e_sq_param *param, struct mlx5e_icosq *sq)
1580 {
1581         struct mlx5e_create_sq_param csp = {};
1582         int err;
1583
1584         err = mlx5e_alloc_icosq(c, param, sq);
1585         if (err)
1586                 return err;
1587
1588         csp.cqn             = sq->cq.mcq.cqn;
1589         csp.wq_ctrl         = &sq->wq_ctrl;
1590         csp.min_inline_mode = params->tx_min_inline_mode;
1591         err = mlx5e_create_sq_rdy(c->mdev, param, &csp, 0, &sq->sqn);
1592         if (err)
1593                 goto err_free_icosq;
1594
1595         if (param->is_tls) {
1596                 sq->ktls_resync = mlx5e_ktls_rx_resync_create_resp_list();
1597                 if (IS_ERR(sq->ktls_resync)) {
1598                         err = PTR_ERR(sq->ktls_resync);
1599                         goto err_destroy_icosq;
1600                 }
1601         }
1602         return 0;
1603
1604 err_destroy_icosq:
1605         mlx5e_destroy_sq(c->mdev, sq->sqn);
1606 err_free_icosq:
1607         mlx5e_free_icosq(sq);
1608
1609         return err;
1610 }
1611
1612 void mlx5e_activate_icosq(struct mlx5e_icosq *icosq)
1613 {
1614         set_bit(MLX5E_SQ_STATE_ENABLED, &icosq->state);
1615 }
1616
1617 void mlx5e_deactivate_icosq(struct mlx5e_icosq *icosq)
1618 {
1619         clear_bit(MLX5E_SQ_STATE_ENABLED, &icosq->state);
1620         synchronize_net(); /* Sync with NAPI. */
1621 }
1622
1623 void mlx5e_close_icosq(struct mlx5e_icosq *sq)
1624 {
1625         struct mlx5e_channel *c = sq->channel;
1626
1627         if (sq->ktls_resync)
1628                 mlx5e_ktls_rx_resync_destroy_resp_list(sq->ktls_resync);
1629         mlx5e_destroy_sq(c->mdev, sq->sqn);
1630         mlx5e_free_icosq_descs(sq);
1631         mlx5e_free_icosq(sq);
1632 }
1633
1634 int mlx5e_open_xdpsq(struct mlx5e_channel *c, struct mlx5e_params *params,
1635                      struct mlx5e_sq_param *param, struct xsk_buff_pool *xsk_pool,
1636                      struct mlx5e_xdpsq *sq, bool is_redirect)
1637 {
1638         struct mlx5e_create_sq_param csp = {};
1639         int err;
1640
1641         err = mlx5e_alloc_xdpsq(c, params, xsk_pool, param, sq, is_redirect);
1642         if (err)
1643                 return err;
1644
1645         csp.tis_lst_sz      = 1;
1646         csp.tisn            = c->priv->tisn[c->lag_port][0]; /* tc = 0 */
1647         csp.cqn             = sq->cq.mcq.cqn;
1648         csp.wq_ctrl         = &sq->wq_ctrl;
1649         csp.min_inline_mode = sq->min_inline_mode;
1650         set_bit(MLX5E_SQ_STATE_ENABLED, &sq->state);
1651         err = mlx5e_create_sq_rdy(c->mdev, param, &csp, 0, &sq->sqn);
1652         if (err)
1653                 goto err_free_xdpsq;
1654
1655         mlx5e_set_xmit_fp(sq, param->is_mpw);
1656
1657         if (!param->is_mpw) {
1658                 unsigned int ds_cnt = MLX5E_XDP_TX_DS_COUNT;
1659                 unsigned int inline_hdr_sz = 0;
1660                 int i;
1661
1662                 if (sq->min_inline_mode != MLX5_INLINE_MODE_NONE) {
1663                         inline_hdr_sz = MLX5E_XDP_MIN_INLINE;
1664                         ds_cnt++;
1665                 }
1666
1667                 /* Pre initialize fixed WQE fields */
1668                 for (i = 0; i < mlx5_wq_cyc_get_size(&sq->wq); i++) {
1669                         struct mlx5e_tx_wqe      *wqe  = mlx5_wq_cyc_get_wqe(&sq->wq, i);
1670                         struct mlx5_wqe_ctrl_seg *cseg = &wqe->ctrl;
1671                         struct mlx5_wqe_eth_seg  *eseg = &wqe->eth;
1672                         struct mlx5_wqe_data_seg *dseg;
1673
1674                         sq->db.wqe_info[i] = (struct mlx5e_xdp_wqe_info) {
1675                                 .num_wqebbs = 1,
1676                                 .num_pkts   = 1,
1677                         };
1678
1679                         cseg->qpn_ds = cpu_to_be32((sq->sqn << 8) | ds_cnt);
1680                         eseg->inline_hdr.sz = cpu_to_be16(inline_hdr_sz);
1681
1682                         dseg = (struct mlx5_wqe_data_seg *)cseg + (ds_cnt - 1);
1683                         dseg->lkey = sq->mkey_be;
1684                 }
1685         }
1686
1687         return 0;
1688
1689 err_free_xdpsq:
1690         clear_bit(MLX5E_SQ_STATE_ENABLED, &sq->state);
1691         mlx5e_free_xdpsq(sq);
1692
1693         return err;
1694 }
1695
1696 void mlx5e_close_xdpsq(struct mlx5e_xdpsq *sq)
1697 {
1698         struct mlx5e_channel *c = sq->channel;
1699
1700         clear_bit(MLX5E_SQ_STATE_ENABLED, &sq->state);
1701         synchronize_net(); /* Sync with NAPI. */
1702
1703         mlx5e_destroy_sq(c->mdev, sq->sqn);
1704         mlx5e_free_xdpsq_descs(sq);
1705         mlx5e_free_xdpsq(sq);
1706 }
1707
1708 static int mlx5e_alloc_cq_common(struct mlx5e_priv *priv,
1709                                  struct mlx5e_cq_param *param,
1710                                  struct mlx5e_cq *cq)
1711 {
1712         struct mlx5_core_dev *mdev = priv->mdev;
1713         struct mlx5_core_cq *mcq = &cq->mcq;
1714         int err;
1715         u32 i;
1716
1717         err = mlx5_cqwq_create(mdev, &param->wq, param->cqc, &cq->wq,
1718                                &cq->wq_ctrl);
1719         if (err)
1720                 return err;
1721
1722         mcq->cqe_sz     = 64;
1723         mcq->set_ci_db  = cq->wq_ctrl.db.db;
1724         mcq->arm_db     = cq->wq_ctrl.db.db + 1;
1725         *mcq->set_ci_db = 0;
1726         *mcq->arm_db    = 0;
1727         mcq->vector     = param->eq_ix;
1728         mcq->comp       = mlx5e_completion_event;
1729         mcq->event      = mlx5e_cq_error_event;
1730
1731         for (i = 0; i < mlx5_cqwq_get_size(&cq->wq); i++) {
1732                 struct mlx5_cqe64 *cqe = mlx5_cqwq_get_wqe(&cq->wq, i);
1733
1734                 cqe->op_own = 0xf1;
1735         }
1736
1737         cq->mdev = mdev;
1738         cq->netdev = priv->netdev;
1739         cq->priv = priv;
1740
1741         return 0;
1742 }
1743
1744 static int mlx5e_alloc_cq(struct mlx5e_priv *priv,
1745                           struct mlx5e_cq_param *param,
1746                           struct mlx5e_create_cq_param *ccp,
1747                           struct mlx5e_cq *cq)
1748 {
1749         int err;
1750
1751         param->wq.buf_numa_node = ccp->node;
1752         param->wq.db_numa_node  = ccp->node;
1753         param->eq_ix            = ccp->ix;
1754
1755         err = mlx5e_alloc_cq_common(priv, param, cq);
1756
1757         cq->napi     = ccp->napi;
1758         cq->ch_stats = ccp->ch_stats;
1759
1760         return err;
1761 }
1762
1763 static void mlx5e_free_cq(struct mlx5e_cq *cq)
1764 {
1765         mlx5_wq_destroy(&cq->wq_ctrl);
1766 }
1767
1768 static int mlx5e_create_cq(struct mlx5e_cq *cq, struct mlx5e_cq_param *param)
1769 {
1770         u32 out[MLX5_ST_SZ_DW(create_cq_out)];
1771         struct mlx5_core_dev *mdev = cq->mdev;
1772         struct mlx5_core_cq *mcq = &cq->mcq;
1773
1774         void *in;
1775         void *cqc;
1776         int inlen;
1777         int eqn;
1778         int err;
1779
1780         err = mlx5_vector2eqn(mdev, param->eq_ix, &eqn);
1781         if (err)
1782                 return err;
1783
1784         inlen = MLX5_ST_SZ_BYTES(create_cq_in) +
1785                 sizeof(u64) * cq->wq_ctrl.buf.npages;
1786         in = kvzalloc(inlen, GFP_KERNEL);
1787         if (!in)
1788                 return -ENOMEM;
1789
1790         cqc = MLX5_ADDR_OF(create_cq_in, in, cq_context);
1791
1792         memcpy(cqc, param->cqc, sizeof(param->cqc));
1793
1794         mlx5_fill_page_frag_array(&cq->wq_ctrl.buf,
1795                                   (__be64 *)MLX5_ADDR_OF(create_cq_in, in, pas));
1796
1797         MLX5_SET(cqc,   cqc, cq_period_mode, param->cq_period_mode);
1798         MLX5_SET(cqc,   cqc, c_eqn_or_apu_element, eqn);
1799         MLX5_SET(cqc,   cqc, uar_page,      mdev->priv.uar->index);
1800         MLX5_SET(cqc,   cqc, log_page_size, cq->wq_ctrl.buf.page_shift -
1801                                             MLX5_ADAPTER_PAGE_SHIFT);
1802         MLX5_SET64(cqc, cqc, dbr_addr,      cq->wq_ctrl.db.dma);
1803
1804         err = mlx5_core_create_cq(mdev, mcq, in, inlen, out, sizeof(out));
1805
1806         kvfree(in);
1807
1808         if (err)
1809                 return err;
1810
1811         mlx5e_cq_arm(cq);
1812
1813         return 0;
1814 }
1815
1816 static void mlx5e_destroy_cq(struct mlx5e_cq *cq)
1817 {
1818         mlx5_core_destroy_cq(cq->mdev, &cq->mcq);
1819 }
1820
1821 int mlx5e_open_cq(struct mlx5e_priv *priv, struct dim_cq_moder moder,
1822                   struct mlx5e_cq_param *param, struct mlx5e_create_cq_param *ccp,
1823                   struct mlx5e_cq *cq)
1824 {
1825         struct mlx5_core_dev *mdev = priv->mdev;
1826         int err;
1827
1828         err = mlx5e_alloc_cq(priv, param, ccp, cq);
1829         if (err)
1830                 return err;
1831
1832         err = mlx5e_create_cq(cq, param);
1833         if (err)
1834                 goto err_free_cq;
1835
1836         if (MLX5_CAP_GEN(mdev, cq_moderation))
1837                 mlx5_core_modify_cq_moderation(mdev, &cq->mcq, moder.usec, moder.pkts);
1838         return 0;
1839
1840 err_free_cq:
1841         mlx5e_free_cq(cq);
1842
1843         return err;
1844 }
1845
1846 void mlx5e_close_cq(struct mlx5e_cq *cq)
1847 {
1848         mlx5e_destroy_cq(cq);
1849         mlx5e_free_cq(cq);
1850 }
1851
1852 static int mlx5e_open_tx_cqs(struct mlx5e_channel *c,
1853                              struct mlx5e_params *params,
1854                              struct mlx5e_create_cq_param *ccp,
1855                              struct mlx5e_channel_param *cparam)
1856 {
1857         int err;
1858         int tc;
1859
1860         for (tc = 0; tc < c->num_tc; tc++) {
1861                 err = mlx5e_open_cq(c->priv, params->tx_cq_moderation, &cparam->txq_sq.cqp,
1862                                     ccp, &c->sq[tc].cq);
1863                 if (err)
1864                         goto err_close_tx_cqs;
1865         }
1866
1867         return 0;
1868
1869 err_close_tx_cqs:
1870         for (tc--; tc >= 0; tc--)
1871                 mlx5e_close_cq(&c->sq[tc].cq);
1872
1873         return err;
1874 }
1875
1876 static void mlx5e_close_tx_cqs(struct mlx5e_channel *c)
1877 {
1878         int tc;
1879
1880         for (tc = 0; tc < c->num_tc; tc++)
1881                 mlx5e_close_cq(&c->sq[tc].cq);
1882 }
1883
1884 static int mlx5e_mqprio_txq_to_tc(struct netdev_tc_txq *tc_to_txq, unsigned int txq)
1885 {
1886         int tc;
1887
1888         for (tc = 0; tc < TC_MAX_QUEUE; tc++)
1889                 if (txq - tc_to_txq[tc].offset < tc_to_txq[tc].count)
1890                         return tc;
1891
1892         WARN(1, "Unexpected TCs configuration. No match found for txq %u", txq);
1893         return -ENOENT;
1894 }
1895
1896 static int mlx5e_txq_get_qos_node_hw_id(struct mlx5e_params *params, int txq_ix,
1897                                         u32 *hw_id)
1898 {
1899         int tc;
1900
1901         if (params->mqprio.mode != TC_MQPRIO_MODE_CHANNEL ||
1902             !params->mqprio.channel.rl) {
1903                 *hw_id = 0;
1904                 return 0;
1905         }
1906
1907         tc = mlx5e_mqprio_txq_to_tc(params->mqprio.tc_to_txq, txq_ix);
1908         if (tc < 0)
1909                 return tc;
1910
1911         return mlx5e_mqprio_rl_get_node_hw_id(params->mqprio.channel.rl, tc, hw_id);
1912 }
1913
1914 static int mlx5e_open_sqs(struct mlx5e_channel *c,
1915                           struct mlx5e_params *params,
1916                           struct mlx5e_channel_param *cparam)
1917 {
1918         int err, tc;
1919
1920         for (tc = 0; tc < mlx5e_get_dcb_num_tc(params); tc++) {
1921                 int txq_ix = c->ix + tc * params->num_channels;
1922                 u32 qos_queue_group_id;
1923
1924                 err = mlx5e_txq_get_qos_node_hw_id(params, txq_ix, &qos_queue_group_id);
1925                 if (err)
1926                         goto err_close_sqs;
1927
1928                 err = mlx5e_open_txqsq(c, c->priv->tisn[c->lag_port][tc], txq_ix,
1929                                        params, &cparam->txq_sq, &c->sq[tc], tc,
1930                                        qos_queue_group_id,
1931                                        &c->priv->channel_stats[c->ix].sq[tc]);
1932                 if (err)
1933                         goto err_close_sqs;
1934         }
1935
1936         return 0;
1937
1938 err_close_sqs:
1939         for (tc--; tc >= 0; tc--)
1940                 mlx5e_close_txqsq(&c->sq[tc]);
1941
1942         return err;
1943 }
1944
1945 static void mlx5e_close_sqs(struct mlx5e_channel *c)
1946 {
1947         int tc;
1948
1949         for (tc = 0; tc < c->num_tc; tc++)
1950                 mlx5e_close_txqsq(&c->sq[tc]);
1951 }
1952
1953 static int mlx5e_set_sq_maxrate(struct net_device *dev,
1954                                 struct mlx5e_txqsq *sq, u32 rate)
1955 {
1956         struct mlx5e_priv *priv = netdev_priv(dev);
1957         struct mlx5_core_dev *mdev = priv->mdev;
1958         struct mlx5e_modify_sq_param msp = {0};
1959         struct mlx5_rate_limit rl = {0};
1960         u16 rl_index = 0;
1961         int err;
1962
1963         if (rate == sq->rate_limit)
1964                 /* nothing to do */
1965                 return 0;
1966
1967         if (sq->rate_limit) {
1968                 rl.rate = sq->rate_limit;
1969                 /* remove current rl index to free space to next ones */
1970                 mlx5_rl_remove_rate(mdev, &rl);
1971         }
1972
1973         sq->rate_limit = 0;
1974
1975         if (rate) {
1976                 rl.rate = rate;
1977                 err = mlx5_rl_add_rate(mdev, &rl_index, &rl);
1978                 if (err) {
1979                         netdev_err(dev, "Failed configuring rate %u: %d\n",
1980                                    rate, err);
1981                         return err;
1982                 }
1983         }
1984
1985         msp.curr_state = MLX5_SQC_STATE_RDY;
1986         msp.next_state = MLX5_SQC_STATE_RDY;
1987         msp.rl_index   = rl_index;
1988         msp.rl_update  = true;
1989         err = mlx5e_modify_sq(mdev, sq->sqn, &msp);
1990         if (err) {
1991                 netdev_err(dev, "Failed configuring rate %u: %d\n",
1992                            rate, err);
1993                 /* remove the rate from the table */
1994                 if (rate)
1995                         mlx5_rl_remove_rate(mdev, &rl);
1996                 return err;
1997         }
1998
1999         sq->rate_limit = rate;
2000         return 0;
2001 }
2002
2003 static int mlx5e_set_tx_maxrate(struct net_device *dev, int index, u32 rate)
2004 {
2005         struct mlx5e_priv *priv = netdev_priv(dev);
2006         struct mlx5_core_dev *mdev = priv->mdev;
2007         struct mlx5e_txqsq *sq = priv->txq2sq[index];
2008         int err = 0;
2009
2010         if (!mlx5_rl_is_supported(mdev)) {
2011                 netdev_err(dev, "Rate limiting is not supported on this device\n");
2012                 return -EINVAL;
2013         }
2014
2015         /* rate is given in Mb/sec, HW config is in Kb/sec */
2016         rate = rate << 10;
2017
2018         /* Check whether rate in valid range, 0 is always valid */
2019         if (rate && !mlx5_rl_is_in_range(mdev, rate)) {
2020                 netdev_err(dev, "TX rate %u, is not in range\n", rate);
2021                 return -ERANGE;
2022         }
2023
2024         mutex_lock(&priv->state_lock);
2025         if (test_bit(MLX5E_STATE_OPENED, &priv->state))
2026                 err = mlx5e_set_sq_maxrate(dev, sq, rate);
2027         if (!err)
2028                 priv->tx_rates[index] = rate;
2029         mutex_unlock(&priv->state_lock);
2030
2031         return err;
2032 }
2033
2034 static int mlx5e_open_rxq_rq(struct mlx5e_channel *c, struct mlx5e_params *params,
2035                              struct mlx5e_rq_param *rq_params)
2036 {
2037         int err;
2038
2039         err = mlx5e_init_rxq_rq(c, params, &c->rq);
2040         if (err)
2041                 return err;
2042
2043         return mlx5e_open_rq(params, rq_params, NULL, cpu_to_node(c->cpu), &c->rq);
2044 }
2045
2046 static int mlx5e_open_queues(struct mlx5e_channel *c,
2047                              struct mlx5e_params *params,
2048                              struct mlx5e_channel_param *cparam)
2049 {
2050         struct dim_cq_moder icocq_moder = {0, 0};
2051         struct mlx5e_create_cq_param ccp;
2052         int err;
2053
2054         mlx5e_build_create_cq_param(&ccp, c);
2055
2056         err = mlx5e_open_cq(c->priv, icocq_moder, &cparam->async_icosq.cqp, &ccp,
2057                             &c->async_icosq.cq);
2058         if (err)
2059                 return err;
2060
2061         err = mlx5e_open_cq(c->priv, icocq_moder, &cparam->icosq.cqp, &ccp,
2062                             &c->icosq.cq);
2063         if (err)
2064                 goto err_close_async_icosq_cq;
2065
2066         err = mlx5e_open_tx_cqs(c, params, &ccp, cparam);
2067         if (err)
2068                 goto err_close_icosq_cq;
2069
2070         err = mlx5e_open_cq(c->priv, params->tx_cq_moderation, &cparam->xdp_sq.cqp, &ccp,
2071                             &c->xdpsq.cq);
2072         if (err)
2073                 goto err_close_tx_cqs;
2074
2075         err = mlx5e_open_cq(c->priv, params->rx_cq_moderation, &cparam->rq.cqp, &ccp,
2076                             &c->rq.cq);
2077         if (err)
2078                 goto err_close_xdp_tx_cqs;
2079
2080         err = c->xdp ? mlx5e_open_cq(c->priv, params->tx_cq_moderation, &cparam->xdp_sq.cqp,
2081                                      &ccp, &c->rq_xdpsq.cq) : 0;
2082         if (err)
2083                 goto err_close_rx_cq;
2084
2085         spin_lock_init(&c->async_icosq_lock);
2086
2087         err = mlx5e_open_icosq(c, params, &cparam->async_icosq, &c->async_icosq);
2088         if (err)
2089                 goto err_close_xdpsq_cq;
2090
2091         err = mlx5e_open_icosq(c, params, &cparam->icosq, &c->icosq);
2092         if (err)
2093                 goto err_close_async_icosq;
2094
2095         err = mlx5e_open_sqs(c, params, cparam);
2096         if (err)
2097                 goto err_close_icosq;
2098
2099         err = mlx5e_open_rxq_rq(c, params, &cparam->rq);
2100         if (err)
2101                 goto err_close_sqs;
2102
2103         if (c->xdp) {
2104                 err = mlx5e_open_xdpsq(c, params, &cparam->xdp_sq, NULL,
2105                                        &c->rq_xdpsq, false);
2106                 if (err)
2107                         goto err_close_rq;
2108         }
2109
2110         err = mlx5e_open_xdpsq(c, params, &cparam->xdp_sq, NULL, &c->xdpsq, true);
2111         if (err)
2112                 goto err_close_xdp_sq;
2113
2114         return 0;
2115
2116 err_close_xdp_sq:
2117         if (c->xdp)
2118                 mlx5e_close_xdpsq(&c->rq_xdpsq);
2119
2120 err_close_rq:
2121         mlx5e_close_rq(&c->rq);
2122
2123 err_close_sqs:
2124         mlx5e_close_sqs(c);
2125
2126 err_close_icosq:
2127         mlx5e_close_icosq(&c->icosq);
2128
2129 err_close_async_icosq:
2130         mlx5e_close_icosq(&c->async_icosq);
2131
2132 err_close_xdpsq_cq:
2133         if (c->xdp)
2134                 mlx5e_close_cq(&c->rq_xdpsq.cq);
2135
2136 err_close_rx_cq:
2137         mlx5e_close_cq(&c->rq.cq);
2138
2139 err_close_xdp_tx_cqs:
2140         mlx5e_close_cq(&c->xdpsq.cq);
2141
2142 err_close_tx_cqs:
2143         mlx5e_close_tx_cqs(c);
2144
2145 err_close_icosq_cq:
2146         mlx5e_close_cq(&c->icosq.cq);
2147
2148 err_close_async_icosq_cq:
2149         mlx5e_close_cq(&c->async_icosq.cq);
2150
2151         return err;
2152 }
2153
2154 static void mlx5e_close_queues(struct mlx5e_channel *c)
2155 {
2156         mlx5e_close_xdpsq(&c->xdpsq);
2157         if (c->xdp)
2158                 mlx5e_close_xdpsq(&c->rq_xdpsq);
2159         mlx5e_close_rq(&c->rq);
2160         mlx5e_close_sqs(c);
2161         mlx5e_close_icosq(&c->icosq);
2162         mlx5e_close_icosq(&c->async_icosq);
2163         if (c->xdp)
2164                 mlx5e_close_cq(&c->rq_xdpsq.cq);
2165         mlx5e_close_cq(&c->rq.cq);
2166         mlx5e_close_cq(&c->xdpsq.cq);
2167         mlx5e_close_tx_cqs(c);
2168         mlx5e_close_cq(&c->icosq.cq);
2169         mlx5e_close_cq(&c->async_icosq.cq);
2170 }
2171
2172 static u8 mlx5e_enumerate_lag_port(struct mlx5_core_dev *mdev, int ix)
2173 {
2174         u16 port_aff_bias = mlx5_core_is_pf(mdev) ? 0 : MLX5_CAP_GEN(mdev, vhca_id);
2175
2176         return (ix + port_aff_bias) % mlx5e_get_num_lag_ports(mdev);
2177 }
2178
2179 static int mlx5e_open_channel(struct mlx5e_priv *priv, int ix,
2180                               struct mlx5e_params *params,
2181                               struct mlx5e_channel_param *cparam,
2182                               struct xsk_buff_pool *xsk_pool,
2183                               struct mlx5e_channel **cp)
2184 {
2185         int cpu = cpumask_first(mlx5_comp_irq_get_affinity_mask(priv->mdev, ix));
2186         struct net_device *netdev = priv->netdev;
2187         struct mlx5e_xsk_param xsk;
2188         struct mlx5e_channel *c;
2189         unsigned int irq;
2190         int err;
2191
2192         err = mlx5_vector2irqn(priv->mdev, ix, &irq);
2193         if (err)
2194                 return err;
2195
2196         c = kvzalloc_node(sizeof(*c), GFP_KERNEL, cpu_to_node(cpu));
2197         if (!c)
2198                 return -ENOMEM;
2199
2200         c->priv     = priv;
2201         c->mdev     = priv->mdev;
2202         c->tstamp   = &priv->tstamp;
2203         c->ix       = ix;
2204         c->cpu      = cpu;
2205         c->pdev     = mlx5_core_dma_dev(priv->mdev);
2206         c->netdev   = priv->netdev;
2207         c->mkey_be  = cpu_to_be32(priv->mdev->mlx5e_res.hw_objs.mkey);
2208         c->num_tc   = mlx5e_get_dcb_num_tc(params);
2209         c->xdp      = !!params->xdp_prog;
2210         c->stats    = &priv->channel_stats[ix].ch;
2211         c->aff_mask = irq_get_effective_affinity_mask(irq);
2212         c->lag_port = mlx5e_enumerate_lag_port(priv->mdev, ix);
2213
2214         netif_napi_add(netdev, &c->napi, mlx5e_napi_poll, 64);
2215
2216         err = mlx5e_open_queues(c, params, cparam);
2217         if (unlikely(err))
2218                 goto err_napi_del;
2219
2220         if (xsk_pool) {
2221                 mlx5e_build_xsk_param(xsk_pool, &xsk);
2222                 err = mlx5e_open_xsk(priv, params, &xsk, xsk_pool, c);
2223                 if (unlikely(err))
2224                         goto err_close_queues;
2225         }
2226
2227         *cp = c;
2228
2229         return 0;
2230
2231 err_close_queues:
2232         mlx5e_close_queues(c);
2233
2234 err_napi_del:
2235         netif_napi_del(&c->napi);
2236
2237         kvfree(c);
2238
2239         return err;
2240 }
2241
2242 static void mlx5e_activate_channel(struct mlx5e_channel *c)
2243 {
2244         int tc;
2245
2246         napi_enable(&c->napi);
2247
2248         for (tc = 0; tc < c->num_tc; tc++)
2249                 mlx5e_activate_txqsq(&c->sq[tc]);
2250         mlx5e_activate_icosq(&c->icosq);
2251         mlx5e_activate_icosq(&c->async_icosq);
2252         mlx5e_activate_rq(&c->rq);
2253
2254         if (test_bit(MLX5E_CHANNEL_STATE_XSK, c->state))
2255                 mlx5e_activate_xsk(c);
2256 }
2257
2258 static void mlx5e_deactivate_channel(struct mlx5e_channel *c)
2259 {
2260         int tc;
2261
2262         if (test_bit(MLX5E_CHANNEL_STATE_XSK, c->state))
2263                 mlx5e_deactivate_xsk(c);
2264
2265         mlx5e_deactivate_rq(&c->rq);
2266         mlx5e_deactivate_icosq(&c->async_icosq);
2267         mlx5e_deactivate_icosq(&c->icosq);
2268         for (tc = 0; tc < c->num_tc; tc++)
2269                 mlx5e_deactivate_txqsq(&c->sq[tc]);
2270         mlx5e_qos_deactivate_queues(c);
2271
2272         napi_disable(&c->napi);
2273 }
2274
2275 static void mlx5e_close_channel(struct mlx5e_channel *c)
2276 {
2277         if (test_bit(MLX5E_CHANNEL_STATE_XSK, c->state))
2278                 mlx5e_close_xsk(c);
2279         mlx5e_close_queues(c);
2280         mlx5e_qos_close_queues(c);
2281         netif_napi_del(&c->napi);
2282
2283         kvfree(c);
2284 }
2285
2286 int mlx5e_open_channels(struct mlx5e_priv *priv,
2287                         struct mlx5e_channels *chs)
2288 {
2289         struct mlx5e_channel_param *cparam;
2290         int err = -ENOMEM;
2291         int i;
2292
2293         chs->num = chs->params.num_channels;
2294
2295         chs->c = kcalloc(chs->num, sizeof(struct mlx5e_channel *), GFP_KERNEL);
2296         cparam = kvzalloc(sizeof(struct mlx5e_channel_param), GFP_KERNEL);
2297         if (!chs->c || !cparam)
2298                 goto err_free;
2299
2300         err = mlx5e_build_channel_param(priv->mdev, &chs->params, priv->q_counter, cparam);
2301         if (err)
2302                 goto err_free;
2303
2304         for (i = 0; i < chs->num; i++) {
2305                 struct xsk_buff_pool *xsk_pool = NULL;
2306
2307                 if (chs->params.xdp_prog)
2308                         xsk_pool = mlx5e_xsk_get_pool(&chs->params, chs->params.xsk, i);
2309
2310                 err = mlx5e_open_channel(priv, i, &chs->params, cparam, xsk_pool, &chs->c[i]);
2311                 if (err)
2312                         goto err_close_channels;
2313         }
2314
2315         if (MLX5E_GET_PFLAG(&chs->params, MLX5E_PFLAG_TX_PORT_TS) || chs->params.ptp_rx) {
2316                 err = mlx5e_ptp_open(priv, &chs->params, chs->c[0]->lag_port, &chs->ptp);
2317                 if (err)
2318                         goto err_close_channels;
2319         }
2320
2321         err = mlx5e_qos_open_queues(priv, chs);
2322         if (err)
2323                 goto err_close_ptp;
2324
2325         mlx5e_health_channels_update(priv);
2326         kvfree(cparam);
2327         return 0;
2328
2329 err_close_ptp:
2330         if (chs->ptp)
2331                 mlx5e_ptp_close(chs->ptp);
2332
2333 err_close_channels:
2334         for (i--; i >= 0; i--)
2335                 mlx5e_close_channel(chs->c[i]);
2336
2337 err_free:
2338         kfree(chs->c);
2339         kvfree(cparam);
2340         chs->num = 0;
2341         return err;
2342 }
2343
2344 static void mlx5e_activate_channels(struct mlx5e_channels *chs)
2345 {
2346         int i;
2347
2348         for (i = 0; i < chs->num; i++)
2349                 mlx5e_activate_channel(chs->c[i]);
2350
2351         if (chs->ptp)
2352                 mlx5e_ptp_activate_channel(chs->ptp);
2353 }
2354
2355 #define MLX5E_RQ_WQES_TIMEOUT 20000 /* msecs */
2356
2357 static int mlx5e_wait_channels_min_rx_wqes(struct mlx5e_channels *chs)
2358 {
2359         int err = 0;
2360         int i;
2361
2362         for (i = 0; i < chs->num; i++) {
2363                 int timeout = err ? 0 : MLX5E_RQ_WQES_TIMEOUT;
2364
2365                 err |= mlx5e_wait_for_min_rx_wqes(&chs->c[i]->rq, timeout);
2366
2367                 /* Don't wait on the XSK RQ, because the newer xdpsock sample
2368                  * doesn't provide any Fill Ring entries at the setup stage.
2369                  */
2370         }
2371
2372         return err ? -ETIMEDOUT : 0;
2373 }
2374
2375 static void mlx5e_deactivate_channels(struct mlx5e_channels *chs)
2376 {
2377         int i;
2378
2379         if (chs->ptp)
2380                 mlx5e_ptp_deactivate_channel(chs->ptp);
2381
2382         for (i = 0; i < chs->num; i++)
2383                 mlx5e_deactivate_channel(chs->c[i]);
2384 }
2385
2386 void mlx5e_close_channels(struct mlx5e_channels *chs)
2387 {
2388         int i;
2389
2390         if (chs->ptp) {
2391                 mlx5e_ptp_close(chs->ptp);
2392                 chs->ptp = NULL;
2393         }
2394         for (i = 0; i < chs->num; i++)
2395                 mlx5e_close_channel(chs->c[i]);
2396
2397         kfree(chs->c);
2398         chs->num = 0;
2399 }
2400
2401 static int mlx5e_modify_tirs_packet_merge(struct mlx5e_priv *priv)
2402 {
2403         struct mlx5e_rx_res *res = priv->rx_res;
2404
2405         return mlx5e_rx_res_packet_merge_set_param(res, &priv->channels.params.packet_merge);
2406 }
2407
2408 static MLX5E_DEFINE_PREACTIVATE_WRAPPER_CTX(mlx5e_modify_tirs_packet_merge);
2409
2410 static int mlx5e_set_mtu(struct mlx5_core_dev *mdev,
2411                          struct mlx5e_params *params, u16 mtu)
2412 {
2413         u16 hw_mtu = MLX5E_SW2HW_MTU(params, mtu);
2414         int err;
2415
2416         err = mlx5_set_port_mtu(mdev, hw_mtu, 1);
2417         if (err)
2418                 return err;
2419
2420         /* Update vport context MTU */
2421         mlx5_modify_nic_vport_mtu(mdev, hw_mtu);
2422         return 0;
2423 }
2424
2425 static void mlx5e_query_mtu(struct mlx5_core_dev *mdev,
2426                             struct mlx5e_params *params, u16 *mtu)
2427 {
2428         u16 hw_mtu = 0;
2429         int err;
2430
2431         err = mlx5_query_nic_vport_mtu(mdev, &hw_mtu);
2432         if (err || !hw_mtu) /* fallback to port oper mtu */
2433                 mlx5_query_port_oper_mtu(mdev, &hw_mtu, 1);
2434
2435         *mtu = MLX5E_HW2SW_MTU(params, hw_mtu);
2436 }
2437
2438 int mlx5e_set_dev_port_mtu(struct mlx5e_priv *priv)
2439 {
2440         struct mlx5e_params *params = &priv->channels.params;
2441         struct net_device *netdev = priv->netdev;
2442         struct mlx5_core_dev *mdev = priv->mdev;
2443         u16 mtu;
2444         int err;
2445
2446         err = mlx5e_set_mtu(mdev, params, params->sw_mtu);
2447         if (err)
2448                 return err;
2449
2450         mlx5e_query_mtu(mdev, params, &mtu);
2451         if (mtu != params->sw_mtu)
2452                 netdev_warn(netdev, "%s: VPort MTU %d is different than netdev mtu %d\n",
2453                             __func__, mtu, params->sw_mtu);
2454
2455         params->sw_mtu = mtu;
2456         return 0;
2457 }
2458
2459 MLX5E_DEFINE_PREACTIVATE_WRAPPER_CTX(mlx5e_set_dev_port_mtu);
2460
2461 void mlx5e_set_netdev_mtu_boundaries(struct mlx5e_priv *priv)
2462 {
2463         struct mlx5e_params *params = &priv->channels.params;
2464         struct net_device *netdev   = priv->netdev;
2465         struct mlx5_core_dev *mdev  = priv->mdev;
2466         u16 max_mtu;
2467
2468         /* MTU range: 68 - hw-specific max */
2469         netdev->min_mtu = ETH_MIN_MTU;
2470
2471         mlx5_query_port_max_mtu(mdev, &max_mtu, 1);
2472         netdev->max_mtu = min_t(unsigned int, MLX5E_HW2SW_MTU(params, max_mtu),
2473                                 ETH_MAX_MTU);
2474 }
2475
2476 static int mlx5e_netdev_set_tcs(struct net_device *netdev, u16 nch, u8 ntc,
2477                                 struct netdev_tc_txq *tc_to_txq)
2478 {
2479         int tc, err;
2480
2481         netdev_reset_tc(netdev);
2482
2483         if (ntc == 1)
2484                 return 0;
2485
2486         err = netdev_set_num_tc(netdev, ntc);
2487         if (err) {
2488                 netdev_WARN(netdev, "netdev_set_num_tc failed (%d), ntc = %d\n", err, ntc);
2489                 return err;
2490         }
2491
2492         for (tc = 0; tc < ntc; tc++) {
2493                 u16 count, offset;
2494
2495                 count = tc_to_txq[tc].count;
2496                 offset = tc_to_txq[tc].offset;
2497                 netdev_set_tc_queue(netdev, tc, count, offset);
2498         }
2499
2500         return 0;
2501 }
2502
2503 int mlx5e_update_tx_netdev_queues(struct mlx5e_priv *priv)
2504 {
2505         int qos_queues, nch, ntc, num_txqs, err;
2506
2507         qos_queues = mlx5e_qos_cur_leaf_nodes(priv);
2508
2509         nch = priv->channels.params.num_channels;
2510         ntc = mlx5e_get_dcb_num_tc(&priv->channels.params);
2511         num_txqs = nch * ntc + qos_queues;
2512         if (MLX5E_GET_PFLAG(&priv->channels.params, MLX5E_PFLAG_TX_PORT_TS))
2513                 num_txqs += ntc;
2514
2515         mlx5e_dbg(DRV, priv, "Setting num_txqs %d\n", num_txqs);
2516         err = netif_set_real_num_tx_queues(priv->netdev, num_txqs);
2517         if (err)
2518                 netdev_warn(priv->netdev, "netif_set_real_num_tx_queues failed, %d\n", err);
2519
2520         return err;
2521 }
2522
2523 static int mlx5e_update_netdev_queues(struct mlx5e_priv *priv)
2524 {
2525         struct netdev_tc_txq old_tc_to_txq[TC_MAX_QUEUE], *tc_to_txq;
2526         struct net_device *netdev = priv->netdev;
2527         int old_num_txqs, old_ntc;
2528         int num_rxqs, nch, ntc;
2529         int err;
2530         int i;
2531
2532         old_num_txqs = netdev->real_num_tx_queues;
2533         old_ntc = netdev->num_tc ? : 1;
2534         for (i = 0; i < ARRAY_SIZE(old_tc_to_txq); i++)
2535                 old_tc_to_txq[i] = netdev->tc_to_txq[i];
2536
2537         nch = priv->channels.params.num_channels;
2538         ntc = priv->channels.params.mqprio.num_tc;
2539         num_rxqs = nch * priv->profile->rq_groups;
2540         tc_to_txq = priv->channels.params.mqprio.tc_to_txq;
2541
2542         err = mlx5e_netdev_set_tcs(netdev, nch, ntc, tc_to_txq);
2543         if (err)
2544                 goto err_out;
2545         err = mlx5e_update_tx_netdev_queues(priv);
2546         if (err)
2547                 goto err_tcs;
2548         err = netif_set_real_num_rx_queues(netdev, num_rxqs);
2549         if (err) {
2550                 netdev_warn(netdev, "netif_set_real_num_rx_queues failed, %d\n", err);
2551                 goto err_txqs;
2552         }
2553         if (priv->mqprio_rl != priv->channels.params.mqprio.channel.rl) {
2554                 if (priv->mqprio_rl) {
2555                         mlx5e_mqprio_rl_cleanup(priv->mqprio_rl);
2556                         mlx5e_mqprio_rl_free(priv->mqprio_rl);
2557                 }
2558                 priv->mqprio_rl = priv->channels.params.mqprio.channel.rl;
2559         }
2560
2561         return 0;
2562
2563 err_txqs:
2564         /* netif_set_real_num_rx_queues could fail only when nch increased. Only
2565          * one of nch and ntc is changed in this function. That means, the call
2566          * to netif_set_real_num_tx_queues below should not fail, because it
2567          * decreases the number of TX queues.
2568          */
2569         WARN_ON_ONCE(netif_set_real_num_tx_queues(netdev, old_num_txqs));
2570
2571 err_tcs:
2572         WARN_ON_ONCE(mlx5e_netdev_set_tcs(netdev, old_num_txqs / old_ntc, old_ntc,
2573                                           old_tc_to_txq));
2574 err_out:
2575         return err;
2576 }
2577
2578 static MLX5E_DEFINE_PREACTIVATE_WRAPPER_CTX(mlx5e_update_netdev_queues);
2579
2580 static void mlx5e_set_default_xps_cpumasks(struct mlx5e_priv *priv,
2581                                            struct mlx5e_params *params)
2582 {
2583         struct mlx5_core_dev *mdev = priv->mdev;
2584         int num_comp_vectors, ix, irq;
2585
2586         num_comp_vectors = mlx5_comp_vectors_count(mdev);
2587
2588         for (ix = 0; ix < params->num_channels; ix++) {
2589                 cpumask_clear(priv->scratchpad.cpumask);
2590
2591                 for (irq = ix; irq < num_comp_vectors; irq += params->num_channels) {
2592                         int cpu = cpumask_first(mlx5_comp_irq_get_affinity_mask(mdev, irq));
2593
2594                         cpumask_set_cpu(cpu, priv->scratchpad.cpumask);
2595                 }
2596
2597                 netif_set_xps_queue(priv->netdev, priv->scratchpad.cpumask, ix);
2598         }
2599 }
2600
2601 int mlx5e_num_channels_changed(struct mlx5e_priv *priv)
2602 {
2603         u16 count = priv->channels.params.num_channels;
2604         int err;
2605
2606         err = mlx5e_update_netdev_queues(priv);
2607         if (err)
2608                 return err;
2609
2610         mlx5e_set_default_xps_cpumasks(priv, &priv->channels.params);
2611
2612         /* This function may be called on attach, before priv->rx_res is created. */
2613         if (!netif_is_rxfh_configured(priv->netdev) && priv->rx_res)
2614                 mlx5e_rx_res_rss_set_indir_uniform(priv->rx_res, count);
2615
2616         return 0;
2617 }
2618
2619 MLX5E_DEFINE_PREACTIVATE_WRAPPER_CTX(mlx5e_num_channels_changed);
2620
2621 static void mlx5e_build_txq_maps(struct mlx5e_priv *priv)
2622 {
2623         int i, ch, tc, num_tc;
2624
2625         ch = priv->channels.num;
2626         num_tc = mlx5e_get_dcb_num_tc(&priv->channels.params);
2627
2628         for (i = 0; i < ch; i++) {
2629                 for (tc = 0; tc < num_tc; tc++) {
2630                         struct mlx5e_channel *c = priv->channels.c[i];
2631                         struct mlx5e_txqsq *sq = &c->sq[tc];
2632
2633                         priv->txq2sq[sq->txq_ix] = sq;
2634                         priv->channel_tc2realtxq[i][tc] = i + tc * ch;
2635                 }
2636         }
2637
2638         if (!priv->channels.ptp)
2639                 return;
2640
2641         if (!test_bit(MLX5E_PTP_STATE_TX, priv->channels.ptp->state))
2642                 return;
2643
2644         for (tc = 0; tc < num_tc; tc++) {
2645                 struct mlx5e_ptp *c = priv->channels.ptp;
2646                 struct mlx5e_txqsq *sq = &c->ptpsq[tc].txqsq;
2647
2648                 priv->txq2sq[sq->txq_ix] = sq;
2649                 priv->port_ptp_tc2realtxq[tc] = priv->num_tc_x_num_ch + tc;
2650         }
2651 }
2652
2653 static void mlx5e_update_num_tc_x_num_ch(struct mlx5e_priv *priv)
2654 {
2655         /* Sync with mlx5e_select_queue. */
2656         WRITE_ONCE(priv->num_tc_x_num_ch,
2657                    mlx5e_get_dcb_num_tc(&priv->channels.params) * priv->channels.num);
2658 }
2659
2660 void mlx5e_activate_priv_channels(struct mlx5e_priv *priv)
2661 {
2662         mlx5e_update_num_tc_x_num_ch(priv);
2663         mlx5e_build_txq_maps(priv);
2664         mlx5e_activate_channels(&priv->channels);
2665         mlx5e_qos_activate_queues(priv);
2666         mlx5e_xdp_tx_enable(priv);
2667         netif_tx_start_all_queues(priv->netdev);
2668
2669         if (mlx5e_is_vport_rep(priv))
2670                 mlx5e_add_sqs_fwd_rules(priv);
2671
2672         mlx5e_wait_channels_min_rx_wqes(&priv->channels);
2673
2674         if (priv->rx_res)
2675                 mlx5e_rx_res_channels_activate(priv->rx_res, &priv->channels);
2676 }
2677
2678 void mlx5e_deactivate_priv_channels(struct mlx5e_priv *priv)
2679 {
2680         if (priv->rx_res)
2681                 mlx5e_rx_res_channels_deactivate(priv->rx_res);
2682
2683         if (mlx5e_is_vport_rep(priv))
2684                 mlx5e_remove_sqs_fwd_rules(priv);
2685
2686         /* FIXME: This is a W/A only for tx timeout watch dog false alarm when
2687          * polling for inactive tx queues.
2688          */
2689         netif_tx_stop_all_queues(priv->netdev);
2690         netif_tx_disable(priv->netdev);
2691         mlx5e_xdp_tx_disable(priv);
2692         mlx5e_deactivate_channels(&priv->channels);
2693 }
2694
2695 static int mlx5e_switch_priv_params(struct mlx5e_priv *priv,
2696                                     struct mlx5e_params *new_params,
2697                                     mlx5e_fp_preactivate preactivate,
2698                                     void *context)
2699 {
2700         struct mlx5e_params old_params;
2701
2702         old_params = priv->channels.params;
2703         priv->channels.params = *new_params;
2704
2705         if (preactivate) {
2706                 int err;
2707
2708                 err = preactivate(priv, context);
2709                 if (err) {
2710                         priv->channels.params = old_params;
2711                         return err;
2712                 }
2713         }
2714
2715         return 0;
2716 }
2717
2718 static int mlx5e_switch_priv_channels(struct mlx5e_priv *priv,
2719                                       struct mlx5e_channels *new_chs,
2720                                       mlx5e_fp_preactivate preactivate,
2721                                       void *context)
2722 {
2723         struct net_device *netdev = priv->netdev;
2724         struct mlx5e_channels old_chs;
2725         int carrier_ok;
2726         int err = 0;
2727
2728         carrier_ok = netif_carrier_ok(netdev);
2729         netif_carrier_off(netdev);
2730
2731         mlx5e_deactivate_priv_channels(priv);
2732
2733         old_chs = priv->channels;
2734         priv->channels = *new_chs;
2735
2736         /* New channels are ready to roll, call the preactivate hook if needed
2737          * to modify HW settings or update kernel parameters.
2738          */
2739         if (preactivate) {
2740                 err = preactivate(priv, context);
2741                 if (err) {
2742                         priv->channels = old_chs;
2743                         goto out;
2744                 }
2745         }
2746
2747         mlx5e_close_channels(&old_chs);
2748         priv->profile->update_rx(priv);
2749
2750 out:
2751         mlx5e_activate_priv_channels(priv);
2752
2753         /* return carrier back if needed */
2754         if (carrier_ok)
2755                 netif_carrier_on(netdev);
2756
2757         return err;
2758 }
2759
2760 int mlx5e_safe_switch_params(struct mlx5e_priv *priv,
2761                              struct mlx5e_params *params,
2762                              mlx5e_fp_preactivate preactivate,
2763                              void *context, bool reset)
2764 {
2765         struct mlx5e_channels new_chs = {};
2766         int err;
2767
2768         reset &= test_bit(MLX5E_STATE_OPENED, &priv->state);
2769         if (!reset)
2770                 return mlx5e_switch_priv_params(priv, params, preactivate, context);
2771
2772         new_chs.params = *params;
2773         err = mlx5e_open_channels(priv, &new_chs);
2774         if (err)
2775                 return err;
2776         err = mlx5e_switch_priv_channels(priv, &new_chs, preactivate, context);
2777         if (err)
2778                 mlx5e_close_channels(&new_chs);
2779
2780         return err;
2781 }
2782
2783 int mlx5e_safe_reopen_channels(struct mlx5e_priv *priv)
2784 {
2785         return mlx5e_safe_switch_params(priv, &priv->channels.params, NULL, NULL, true);
2786 }
2787
2788 void mlx5e_timestamp_init(struct mlx5e_priv *priv)
2789 {
2790         priv->tstamp.tx_type   = HWTSTAMP_TX_OFF;
2791         priv->tstamp.rx_filter = HWTSTAMP_FILTER_NONE;
2792 }
2793
2794 static void mlx5e_modify_admin_state(struct mlx5_core_dev *mdev,
2795                                      enum mlx5_port_status state)
2796 {
2797         struct mlx5_eswitch *esw = mdev->priv.eswitch;
2798         int vport_admin_state;
2799
2800         mlx5_set_port_admin_status(mdev, state);
2801
2802         if (mlx5_eswitch_mode(mdev) == MLX5_ESWITCH_OFFLOADS ||
2803             !MLX5_CAP_GEN(mdev, uplink_follow))
2804                 return;
2805
2806         if (state == MLX5_PORT_UP)
2807                 vport_admin_state = MLX5_VPORT_ADMIN_STATE_AUTO;
2808         else
2809                 vport_admin_state = MLX5_VPORT_ADMIN_STATE_DOWN;
2810
2811         mlx5_eswitch_set_vport_state(esw, MLX5_VPORT_UPLINK, vport_admin_state);
2812 }
2813
2814 int mlx5e_open_locked(struct net_device *netdev)
2815 {
2816         struct mlx5e_priv *priv = netdev_priv(netdev);
2817         int err;
2818
2819         set_bit(MLX5E_STATE_OPENED, &priv->state);
2820
2821         err = mlx5e_open_channels(priv, &priv->channels);
2822         if (err)
2823                 goto err_clear_state_opened_flag;
2824
2825         priv->profile->update_rx(priv);
2826         mlx5e_activate_priv_channels(priv);
2827         mlx5e_apply_traps(priv, true);
2828         if (priv->profile->update_carrier)
2829                 priv->profile->update_carrier(priv);
2830
2831         mlx5e_queue_update_stats(priv);
2832         return 0;
2833
2834 err_clear_state_opened_flag:
2835         clear_bit(MLX5E_STATE_OPENED, &priv->state);
2836         return err;
2837 }
2838
2839 int mlx5e_open(struct net_device *netdev)
2840 {
2841         struct mlx5e_priv *priv = netdev_priv(netdev);
2842         int err;
2843
2844         mutex_lock(&priv->state_lock);
2845         err = mlx5e_open_locked(netdev);
2846         if (!err)
2847                 mlx5e_modify_admin_state(priv->mdev, MLX5_PORT_UP);
2848         mutex_unlock(&priv->state_lock);
2849
2850         return err;
2851 }
2852
2853 int mlx5e_close_locked(struct net_device *netdev)
2854 {
2855         struct mlx5e_priv *priv = netdev_priv(netdev);
2856
2857         /* May already be CLOSED in case a previous configuration operation
2858          * (e.g RX/TX queue size change) that involves close&open failed.
2859          */
2860         if (!test_bit(MLX5E_STATE_OPENED, &priv->state))
2861                 return 0;
2862
2863         mlx5e_apply_traps(priv, false);
2864         clear_bit(MLX5E_STATE_OPENED, &priv->state);
2865
2866         netif_carrier_off(priv->netdev);
2867         mlx5e_deactivate_priv_channels(priv);
2868         mlx5e_close_channels(&priv->channels);
2869
2870         return 0;
2871 }
2872
2873 int mlx5e_close(struct net_device *netdev)
2874 {
2875         struct mlx5e_priv *priv = netdev_priv(netdev);
2876         int err;
2877
2878         if (!netif_device_present(netdev))
2879                 return -ENODEV;
2880
2881         mutex_lock(&priv->state_lock);
2882         mlx5e_modify_admin_state(priv->mdev, MLX5_PORT_DOWN);
2883         err = mlx5e_close_locked(netdev);
2884         mutex_unlock(&priv->state_lock);
2885
2886         return err;
2887 }
2888
2889 static void mlx5e_free_drop_rq(struct mlx5e_rq *rq)
2890 {
2891         mlx5_wq_destroy(&rq->wq_ctrl);
2892 }
2893
2894 static int mlx5e_alloc_drop_rq(struct mlx5_core_dev *mdev,
2895                                struct mlx5e_rq *rq,
2896                                struct mlx5e_rq_param *param)
2897 {
2898         void *rqc = param->rqc;
2899         void *rqc_wq = MLX5_ADDR_OF(rqc, rqc, wq);
2900         int err;
2901
2902         param->wq.db_numa_node = param->wq.buf_numa_node;
2903
2904         err = mlx5_wq_cyc_create(mdev, &param->wq, rqc_wq, &rq->wqe.wq,
2905                                  &rq->wq_ctrl);
2906         if (err)
2907                 return err;
2908
2909         /* Mark as unused given "Drop-RQ" packets never reach XDP */
2910         xdp_rxq_info_unused(&rq->xdp_rxq);
2911
2912         rq->mdev = mdev;
2913
2914         return 0;
2915 }
2916
2917 static int mlx5e_alloc_drop_cq(struct mlx5e_priv *priv,
2918                                struct mlx5e_cq *cq,
2919                                struct mlx5e_cq_param *param)
2920 {
2921         struct mlx5_core_dev *mdev = priv->mdev;
2922
2923         param->wq.buf_numa_node = dev_to_node(mlx5_core_dma_dev(mdev));
2924         param->wq.db_numa_node  = dev_to_node(mlx5_core_dma_dev(mdev));
2925
2926         return mlx5e_alloc_cq_common(priv, param, cq);
2927 }
2928
2929 int mlx5e_open_drop_rq(struct mlx5e_priv *priv,
2930                        struct mlx5e_rq *drop_rq)
2931 {
2932         struct mlx5_core_dev *mdev = priv->mdev;
2933         struct mlx5e_cq_param cq_param = {};
2934         struct mlx5e_rq_param rq_param = {};
2935         struct mlx5e_cq *cq = &drop_rq->cq;
2936         int err;
2937
2938         mlx5e_build_drop_rq_param(mdev, priv->drop_rq_q_counter, &rq_param);
2939
2940         err = mlx5e_alloc_drop_cq(priv, cq, &cq_param);
2941         if (err)
2942                 return err;
2943
2944         err = mlx5e_create_cq(cq, &cq_param);
2945         if (err)
2946                 goto err_free_cq;
2947
2948         err = mlx5e_alloc_drop_rq(mdev, drop_rq, &rq_param);
2949         if (err)
2950                 goto err_destroy_cq;
2951
2952         err = mlx5e_create_rq(drop_rq, &rq_param);
2953         if (err)
2954                 goto err_free_rq;
2955
2956         err = mlx5e_modify_rq_state(drop_rq, MLX5_RQC_STATE_RST, MLX5_RQC_STATE_RDY);
2957         if (err)
2958                 mlx5_core_warn(priv->mdev, "modify_rq_state failed, rx_if_down_packets won't be counted %d\n", err);
2959
2960         return 0;
2961
2962 err_free_rq:
2963         mlx5e_free_drop_rq(drop_rq);
2964
2965 err_destroy_cq:
2966         mlx5e_destroy_cq(cq);
2967
2968 err_free_cq:
2969         mlx5e_free_cq(cq);
2970
2971         return err;
2972 }
2973
2974 void mlx5e_close_drop_rq(struct mlx5e_rq *drop_rq)
2975 {
2976         mlx5e_destroy_rq(drop_rq);
2977         mlx5e_free_drop_rq(drop_rq);
2978         mlx5e_destroy_cq(&drop_rq->cq);
2979         mlx5e_free_cq(&drop_rq->cq);
2980 }
2981
2982 int mlx5e_create_tis(struct mlx5_core_dev *mdev, void *in, u32 *tisn)
2983 {
2984         void *tisc = MLX5_ADDR_OF(create_tis_in, in, ctx);
2985
2986         MLX5_SET(tisc, tisc, transport_domain, mdev->mlx5e_res.hw_objs.td.tdn);
2987
2988         if (MLX5_GET(tisc, tisc, tls_en))
2989                 MLX5_SET(tisc, tisc, pd, mdev->mlx5e_res.hw_objs.pdn);
2990
2991         if (mlx5_lag_is_lacp_owner(mdev))
2992                 MLX5_SET(tisc, tisc, strict_lag_tx_port_affinity, 1);
2993
2994         return mlx5_core_create_tis(mdev, in, tisn);
2995 }
2996
2997 void mlx5e_destroy_tis(struct mlx5_core_dev *mdev, u32 tisn)
2998 {
2999         mlx5_core_destroy_tis(mdev, tisn);
3000 }
3001
3002 void mlx5e_destroy_tises(struct mlx5e_priv *priv)
3003 {
3004         int tc, i;
3005
3006         for (i = 0; i < mlx5e_get_num_lag_ports(priv->mdev); i++)
3007                 for (tc = 0; tc < priv->profile->max_tc; tc++)
3008                         mlx5e_destroy_tis(priv->mdev, priv->tisn[i][tc]);
3009 }
3010
3011 static bool mlx5e_lag_should_assign_affinity(struct mlx5_core_dev *mdev)
3012 {
3013         return MLX5_CAP_GEN(mdev, lag_tx_port_affinity) && mlx5e_get_num_lag_ports(mdev) > 1;
3014 }
3015
3016 int mlx5e_create_tises(struct mlx5e_priv *priv)
3017 {
3018         int tc, i;
3019         int err;
3020
3021         for (i = 0; i < mlx5e_get_num_lag_ports(priv->mdev); i++) {
3022                 for (tc = 0; tc < priv->profile->max_tc; tc++) {
3023                         u32 in[MLX5_ST_SZ_DW(create_tis_in)] = {};
3024                         void *tisc;
3025
3026                         tisc = MLX5_ADDR_OF(create_tis_in, in, ctx);
3027
3028                         MLX5_SET(tisc, tisc, prio, tc << 1);
3029
3030                         if (mlx5e_lag_should_assign_affinity(priv->mdev))
3031                                 MLX5_SET(tisc, tisc, lag_tx_port_affinity, i + 1);
3032
3033                         err = mlx5e_create_tis(priv->mdev, in, &priv->tisn[i][tc]);
3034                         if (err)
3035                                 goto err_close_tises;
3036                 }
3037         }
3038
3039         return 0;
3040
3041 err_close_tises:
3042         for (; i >= 0; i--) {
3043                 for (tc--; tc >= 0; tc--)
3044                         mlx5e_destroy_tis(priv->mdev, priv->tisn[i][tc]);
3045                 tc = priv->profile->max_tc;
3046         }
3047
3048         return err;
3049 }
3050
3051 static void mlx5e_cleanup_nic_tx(struct mlx5e_priv *priv)
3052 {
3053         mlx5e_destroy_tises(priv);
3054 }
3055
3056 static int mlx5e_modify_channels_scatter_fcs(struct mlx5e_channels *chs, bool enable)
3057 {
3058         int err = 0;
3059         int i;
3060
3061         for (i = 0; i < chs->num; i++) {
3062                 err = mlx5e_modify_rq_scatter_fcs(&chs->c[i]->rq, enable);
3063                 if (err)
3064                         return err;
3065         }
3066
3067         return 0;
3068 }
3069
3070 static int mlx5e_modify_channels_vsd(struct mlx5e_channels *chs, bool vsd)
3071 {
3072         int err;
3073         int i;
3074
3075         for (i = 0; i < chs->num; i++) {
3076                 err = mlx5e_modify_rq_vsd(&chs->c[i]->rq, vsd);
3077                 if (err)
3078                         return err;
3079         }
3080         if (chs->ptp && test_bit(MLX5E_PTP_STATE_RX, chs->ptp->state))
3081                 return mlx5e_modify_rq_vsd(&chs->ptp->rq, vsd);
3082
3083         return 0;
3084 }
3085
3086 static void mlx5e_mqprio_build_default_tc_to_txq(struct netdev_tc_txq *tc_to_txq,
3087                                                  int ntc, int nch)
3088 {
3089         int tc;
3090
3091         memset(tc_to_txq, 0, sizeof(*tc_to_txq) * TC_MAX_QUEUE);
3092
3093         /* Map netdev TCs to offset 0.
3094          * We have our own UP to TXQ mapping for DCB mode of QoS
3095          */
3096         for (tc = 0; tc < ntc; tc++) {
3097                 tc_to_txq[tc] = (struct netdev_tc_txq) {
3098                         .count = nch,
3099                         .offset = 0,
3100                 };
3101         }
3102 }
3103
3104 static void mlx5e_mqprio_build_tc_to_txq(struct netdev_tc_txq *tc_to_txq,
3105                                          struct tc_mqprio_qopt *qopt)
3106 {
3107         int tc;
3108
3109         for (tc = 0; tc < TC_MAX_QUEUE; tc++) {
3110                 tc_to_txq[tc] = (struct netdev_tc_txq) {
3111                         .count = qopt->count[tc],
3112                         .offset = qopt->offset[tc],
3113                 };
3114         }
3115 }
3116
3117 static void mlx5e_params_mqprio_dcb_set(struct mlx5e_params *params, u8 num_tc)
3118 {
3119         params->mqprio.mode = TC_MQPRIO_MODE_DCB;
3120         params->mqprio.num_tc = num_tc;
3121         params->mqprio.channel.rl = NULL;
3122         mlx5e_mqprio_build_default_tc_to_txq(params->mqprio.tc_to_txq, num_tc,
3123                                              params->num_channels);
3124 }
3125
3126 static void mlx5e_params_mqprio_channel_set(struct mlx5e_params *params,
3127                                             struct tc_mqprio_qopt *qopt,
3128                                             struct mlx5e_mqprio_rl *rl)
3129 {
3130         params->mqprio.mode = TC_MQPRIO_MODE_CHANNEL;
3131         params->mqprio.num_tc = qopt->num_tc;
3132         params->mqprio.channel.rl = rl;
3133         mlx5e_mqprio_build_tc_to_txq(params->mqprio.tc_to_txq, qopt);
3134 }
3135
3136 static void mlx5e_params_mqprio_reset(struct mlx5e_params *params)
3137 {
3138         mlx5e_params_mqprio_dcb_set(params, 1);
3139 }
3140
3141 static int mlx5e_setup_tc_mqprio_dcb(struct mlx5e_priv *priv,
3142                                      struct tc_mqprio_qopt *mqprio)
3143 {
3144         struct mlx5e_params new_params;
3145         u8 tc = mqprio->num_tc;
3146         int err;
3147
3148         mqprio->hw = TC_MQPRIO_HW_OFFLOAD_TCS;
3149
3150         if (tc && tc != MLX5E_MAX_NUM_TC)
3151                 return -EINVAL;
3152
3153         new_params = priv->channels.params;
3154         mlx5e_params_mqprio_dcb_set(&new_params, tc ? tc : 1);
3155
3156         err = mlx5e_safe_switch_params(priv, &new_params,
3157                                        mlx5e_num_channels_changed_ctx, NULL, true);
3158
3159         priv->max_opened_tc = max_t(u8, priv->max_opened_tc,
3160                                     mlx5e_get_dcb_num_tc(&priv->channels.params));
3161         return err;
3162 }
3163
3164 static int mlx5e_mqprio_channel_validate(struct mlx5e_priv *priv,
3165                                          struct tc_mqprio_qopt_offload *mqprio)
3166 {
3167         struct net_device *netdev = priv->netdev;
3168         struct mlx5e_ptp *ptp_channel;
3169         int agg_count = 0;
3170         int i;
3171
3172         ptp_channel = priv->channels.ptp;
3173         if (ptp_channel && test_bit(MLX5E_PTP_STATE_TX, ptp_channel->state)) {
3174                 netdev_err(netdev,
3175                            "Cannot activate MQPRIO mode channel since it conflicts with TX port TS\n");
3176                 return -EINVAL;
3177         }
3178
3179         if (mqprio->qopt.offset[0] != 0 || mqprio->qopt.num_tc < 1 ||
3180             mqprio->qopt.num_tc > MLX5E_MAX_NUM_MQPRIO_CH_TC)
3181                 return -EINVAL;
3182
3183         for (i = 0; i < mqprio->qopt.num_tc; i++) {
3184                 if (!mqprio->qopt.count[i]) {
3185                         netdev_err(netdev, "Zero size for queue-group (%d) is not supported\n", i);
3186                         return -EINVAL;
3187                 }
3188                 if (mqprio->min_rate[i]) {
3189                         netdev_err(netdev, "Min tx rate is not supported\n");
3190                         return -EINVAL;
3191                 }
3192
3193                 if (mqprio->max_rate[i]) {
3194                         int err;
3195
3196                         err = mlx5e_qos_bytes_rate_check(priv->mdev, mqprio->max_rate[i]);
3197                         if (err)
3198                                 return err;
3199                 }
3200
3201                 if (mqprio->qopt.offset[i] != agg_count) {
3202                         netdev_err(netdev, "Discontinuous queues config is not supported\n");
3203                         return -EINVAL;
3204                 }
3205                 agg_count += mqprio->qopt.count[i];
3206         }
3207
3208         if (priv->channels.params.num_channels != agg_count) {
3209                 netdev_err(netdev, "Num of queues (%d) does not match available (%d)\n",
3210                            agg_count, priv->channels.params.num_channels);
3211                 return -EINVAL;
3212         }
3213
3214         return 0;
3215 }
3216
3217 static bool mlx5e_mqprio_rate_limit(struct tc_mqprio_qopt_offload *mqprio)
3218 {
3219         int tc;
3220
3221         for (tc = 0; tc < mqprio->qopt.num_tc; tc++)
3222                 if (mqprio->max_rate[tc])
3223                         return true;
3224         return false;
3225 }
3226
3227 static int mlx5e_setup_tc_mqprio_channel(struct mlx5e_priv *priv,
3228                                          struct tc_mqprio_qopt_offload *mqprio)
3229 {
3230         mlx5e_fp_preactivate preactivate;
3231         struct mlx5e_params new_params;
3232         struct mlx5e_mqprio_rl *rl;
3233         bool nch_changed;
3234         int err;
3235
3236         err = mlx5e_mqprio_channel_validate(priv, mqprio);
3237         if (err)
3238                 return err;
3239
3240         rl = NULL;
3241         if (mlx5e_mqprio_rate_limit(mqprio)) {
3242                 rl = mlx5e_mqprio_rl_alloc();
3243                 if (!rl)
3244                         return -ENOMEM;
3245                 err = mlx5e_mqprio_rl_init(rl, priv->mdev, mqprio->qopt.num_tc,
3246                                            mqprio->max_rate);
3247                 if (err) {
3248                         mlx5e_mqprio_rl_free(rl);
3249                         return err;
3250                 }
3251         }
3252
3253         new_params = priv->channels.params;
3254         mlx5e_params_mqprio_channel_set(&new_params, &mqprio->qopt, rl);
3255
3256         nch_changed = mlx5e_get_dcb_num_tc(&priv->channels.params) > 1;
3257         preactivate = nch_changed ? mlx5e_num_channels_changed_ctx :
3258                 mlx5e_update_netdev_queues_ctx;
3259         err = mlx5e_safe_switch_params(priv, &new_params, preactivate, NULL, true);
3260         if (err && rl) {
3261                 mlx5e_mqprio_rl_cleanup(rl);
3262                 mlx5e_mqprio_rl_free(rl);
3263         }
3264
3265         return err;
3266 }
3267
3268 static int mlx5e_setup_tc_mqprio(struct mlx5e_priv *priv,
3269                                  struct tc_mqprio_qopt_offload *mqprio)
3270 {
3271         /* MQPRIO is another toplevel qdisc that can't be attached
3272          * simultaneously with the offloaded HTB.
3273          */
3274         if (WARN_ON(priv->htb.maj_id))
3275                 return -EINVAL;
3276
3277         switch (mqprio->mode) {
3278         case TC_MQPRIO_MODE_DCB:
3279                 return mlx5e_setup_tc_mqprio_dcb(priv, &mqprio->qopt);
3280         case TC_MQPRIO_MODE_CHANNEL:
3281                 return mlx5e_setup_tc_mqprio_channel(priv, mqprio);
3282         default:
3283                 return -EOPNOTSUPP;
3284         }
3285 }
3286
3287 static int mlx5e_setup_tc_htb(struct mlx5e_priv *priv, struct tc_htb_qopt_offload *htb)
3288 {
3289         int res;
3290
3291         switch (htb->command) {
3292         case TC_HTB_CREATE:
3293                 return mlx5e_htb_root_add(priv, htb->parent_classid, htb->classid,
3294                                           htb->extack);
3295         case TC_HTB_DESTROY:
3296                 return mlx5e_htb_root_del(priv);
3297         case TC_HTB_LEAF_ALLOC_QUEUE:
3298                 res = mlx5e_htb_leaf_alloc_queue(priv, htb->classid, htb->parent_classid,
3299                                                  htb->rate, htb->ceil, htb->extack);
3300                 if (res < 0)
3301                         return res;
3302                 htb->qid = res;
3303                 return 0;
3304         case TC_HTB_LEAF_TO_INNER:
3305                 return mlx5e_htb_leaf_to_inner(priv, htb->parent_classid, htb->classid,
3306                                                htb->rate, htb->ceil, htb->extack);
3307         case TC_HTB_LEAF_DEL:
3308                 return mlx5e_htb_leaf_del(priv, &htb->classid, htb->extack);
3309         case TC_HTB_LEAF_DEL_LAST:
3310         case TC_HTB_LEAF_DEL_LAST_FORCE:
3311                 return mlx5e_htb_leaf_del_last(priv, htb->classid,
3312                                                htb->command == TC_HTB_LEAF_DEL_LAST_FORCE,
3313                                                htb->extack);
3314         case TC_HTB_NODE_MODIFY:
3315                 return mlx5e_htb_node_modify(priv, htb->classid, htb->rate, htb->ceil,
3316                                              htb->extack);
3317         case TC_HTB_LEAF_QUERY_QUEUE:
3318                 res = mlx5e_get_txq_by_classid(priv, htb->classid);
3319                 if (res < 0)
3320                         return res;
3321                 htb->qid = res;
3322                 return 0;
3323         default:
3324                 return -EOPNOTSUPP;
3325         }
3326 }
3327
3328 static LIST_HEAD(mlx5e_block_cb_list);
3329
3330 static int mlx5e_setup_tc(struct net_device *dev, enum tc_setup_type type,
3331                           void *type_data)
3332 {
3333         struct mlx5e_priv *priv = netdev_priv(dev);
3334         bool tc_unbind = false;
3335         int err;
3336
3337         if (type == TC_SETUP_BLOCK &&
3338             ((struct flow_block_offload *)type_data)->command == FLOW_BLOCK_UNBIND)
3339                 tc_unbind = true;
3340
3341         if (!netif_device_present(dev) && !tc_unbind)
3342                 return -ENODEV;
3343
3344         switch (type) {
3345         case TC_SETUP_BLOCK: {
3346                 struct flow_block_offload *f = type_data;
3347
3348                 f->unlocked_driver_cb = true;
3349                 return flow_block_cb_setup_simple(type_data,
3350                                                   &mlx5e_block_cb_list,
3351                                                   mlx5e_setup_tc_block_cb,
3352                                                   priv, priv, true);
3353         }
3354         case TC_SETUP_QDISC_MQPRIO:
3355                 mutex_lock(&priv->state_lock);
3356                 err = mlx5e_setup_tc_mqprio(priv, type_data);
3357                 mutex_unlock(&priv->state_lock);
3358                 return err;
3359         case TC_SETUP_QDISC_HTB:
3360                 mutex_lock(&priv->state_lock);
3361                 err = mlx5e_setup_tc_htb(priv, type_data);
3362                 mutex_unlock(&priv->state_lock);
3363                 return err;
3364         default:
3365                 return -EOPNOTSUPP;
3366         }
3367 }
3368
3369 void mlx5e_fold_sw_stats64(struct mlx5e_priv *priv, struct rtnl_link_stats64 *s)
3370 {
3371         int i;
3372
3373         for (i = 0; i < priv->stats_nch; i++) {
3374                 struct mlx5e_channel_stats *channel_stats = &priv->channel_stats[i];
3375                 struct mlx5e_rq_stats *xskrq_stats = &channel_stats->xskrq;
3376                 struct mlx5e_rq_stats *rq_stats = &channel_stats->rq;
3377                 int j;
3378
3379                 s->rx_packets   += rq_stats->packets + xskrq_stats->packets;
3380                 s->rx_bytes     += rq_stats->bytes + xskrq_stats->bytes;
3381                 s->multicast    += rq_stats->mcast_packets + xskrq_stats->mcast_packets;
3382
3383                 for (j = 0; j < priv->max_opened_tc; j++) {
3384                         struct mlx5e_sq_stats *sq_stats = &channel_stats->sq[j];
3385
3386                         s->tx_packets    += sq_stats->packets;
3387                         s->tx_bytes      += sq_stats->bytes;
3388                         s->tx_dropped    += sq_stats->dropped;
3389                 }
3390         }
3391         if (priv->tx_ptp_opened) {
3392                 for (i = 0; i < priv->max_opened_tc; i++) {
3393                         struct mlx5e_sq_stats *sq_stats = &priv->ptp_stats.sq[i];
3394
3395                         s->tx_packets    += sq_stats->packets;
3396                         s->tx_bytes      += sq_stats->bytes;
3397                         s->tx_dropped    += sq_stats->dropped;
3398                 }
3399         }
3400         if (priv->rx_ptp_opened) {
3401                 struct mlx5e_rq_stats *rq_stats = &priv->ptp_stats.rq;
3402
3403                 s->rx_packets   += rq_stats->packets;
3404                 s->rx_bytes     += rq_stats->bytes;
3405                 s->multicast    += rq_stats->mcast_packets;
3406         }
3407 }
3408
3409 void
3410 mlx5e_get_stats(struct net_device *dev, struct rtnl_link_stats64 *stats)
3411 {
3412         struct mlx5e_priv *priv = netdev_priv(dev);
3413         struct mlx5e_pport_stats *pstats = &priv->stats.pport;
3414
3415         if (!netif_device_present(dev))
3416                 return;
3417
3418         /* In switchdev mode, monitor counters doesn't monitor
3419          * rx/tx stats of 802_3. The update stats mechanism
3420          * should keep the 802_3 layout counters updated
3421          */
3422         if (!mlx5e_monitor_counter_supported(priv) ||
3423             mlx5e_is_uplink_rep(priv)) {
3424                 /* update HW stats in background for next time */
3425                 mlx5e_queue_update_stats(priv);
3426         }
3427
3428         if (mlx5e_is_uplink_rep(priv)) {
3429                 struct mlx5e_vport_stats *vstats = &priv->stats.vport;
3430
3431                 stats->rx_packets = PPORT_802_3_GET(pstats, a_frames_received_ok);
3432                 stats->rx_bytes   = PPORT_802_3_GET(pstats, a_octets_received_ok);
3433                 stats->tx_packets = PPORT_802_3_GET(pstats, a_frames_transmitted_ok);
3434                 stats->tx_bytes   = PPORT_802_3_GET(pstats, a_octets_transmitted_ok);
3435
3436                 /* vport multicast also counts packets that are dropped due to steering
3437                  * or rx out of buffer
3438                  */
3439                 stats->multicast = VPORT_COUNTER_GET(vstats, received_eth_multicast.packets);
3440         } else {
3441                 mlx5e_fold_sw_stats64(priv, stats);
3442         }
3443
3444         stats->rx_dropped = priv->stats.qcnt.rx_out_of_buffer;
3445
3446         stats->rx_length_errors =
3447                 PPORT_802_3_GET(pstats, a_in_range_length_errors) +
3448                 PPORT_802_3_GET(pstats, a_out_of_range_length_field) +
3449                 PPORT_802_3_GET(pstats, a_frame_too_long_errors);
3450         stats->rx_crc_errors =
3451                 PPORT_802_3_GET(pstats, a_frame_check_sequence_errors);
3452         stats->rx_frame_errors = PPORT_802_3_GET(pstats, a_alignment_errors);
3453         stats->tx_aborted_errors = PPORT_2863_GET(pstats, if_out_discards);
3454         stats->rx_errors = stats->rx_length_errors + stats->rx_crc_errors +
3455                            stats->rx_frame_errors;
3456         stats->tx_errors = stats->tx_aborted_errors + stats->tx_carrier_errors;
3457 }
3458
3459 static void mlx5e_nic_set_rx_mode(struct mlx5e_priv *priv)
3460 {
3461         if (mlx5e_is_uplink_rep(priv))
3462                 return; /* no rx mode for uplink rep */
3463
3464         queue_work(priv->wq, &priv->set_rx_mode_work);
3465 }
3466
3467 static void mlx5e_set_rx_mode(struct net_device *dev)
3468 {
3469         struct mlx5e_priv *priv = netdev_priv(dev);
3470
3471         mlx5e_nic_set_rx_mode(priv);
3472 }
3473
3474 static int mlx5e_set_mac(struct net_device *netdev, void *addr)
3475 {
3476         struct mlx5e_priv *priv = netdev_priv(netdev);
3477         struct sockaddr *saddr = addr;
3478
3479         if (!is_valid_ether_addr(saddr->sa_data))
3480                 return -EADDRNOTAVAIL;
3481
3482         netif_addr_lock_bh(netdev);
3483         eth_hw_addr_set(netdev, saddr->sa_data);
3484         netif_addr_unlock_bh(netdev);
3485
3486         mlx5e_nic_set_rx_mode(priv);
3487
3488         return 0;
3489 }
3490
3491 #define MLX5E_SET_FEATURE(features, feature, enable)    \
3492         do {                                            \
3493                 if (enable)                             \
3494                         *features |= feature;           \
3495                 else                                    \
3496                         *features &= ~feature;          \
3497         } while (0)
3498
3499 typedef int (*mlx5e_feature_handler)(struct net_device *netdev, bool enable);
3500
3501 static int set_feature_lro(struct net_device *netdev, bool enable)
3502 {
3503         struct mlx5e_priv *priv = netdev_priv(netdev);
3504         struct mlx5_core_dev *mdev = priv->mdev;
3505         struct mlx5e_params *cur_params;
3506         struct mlx5e_params new_params;
3507         bool reset = true;
3508         int err = 0;
3509
3510         mutex_lock(&priv->state_lock);
3511
3512         if (enable && priv->xsk.refcnt) {
3513                 netdev_warn(netdev, "LRO is incompatible with AF_XDP (%u XSKs are active)\n",
3514                             priv->xsk.refcnt);
3515                 err = -EINVAL;
3516                 goto out;
3517         }
3518
3519         cur_params = &priv->channels.params;
3520         if (enable && !MLX5E_GET_PFLAG(cur_params, MLX5E_PFLAG_RX_STRIDING_RQ)) {
3521                 netdev_warn(netdev, "can't set LRO with legacy RQ\n");
3522                 err = -EINVAL;
3523                 goto out;
3524         }
3525
3526         new_params = *cur_params;
3527
3528         if (enable)
3529                 new_params.packet_merge.type = MLX5E_PACKET_MERGE_LRO;
3530         else if (new_params.packet_merge.type == MLX5E_PACKET_MERGE_LRO)
3531                 new_params.packet_merge.type = MLX5E_PACKET_MERGE_NONE;
3532         else
3533                 goto out;
3534
3535         if (!(cur_params->packet_merge.type == MLX5E_PACKET_MERGE_SHAMPO &&
3536               new_params.packet_merge.type == MLX5E_PACKET_MERGE_LRO)) {
3537                 if (cur_params->rq_wq_type == MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ) {
3538                         if (mlx5e_rx_mpwqe_is_linear_skb(mdev, cur_params, NULL) ==
3539                             mlx5e_rx_mpwqe_is_linear_skb(mdev, &new_params, NULL))
3540                                 reset = false;
3541                 }
3542         }
3543
3544         err = mlx5e_safe_switch_params(priv, &new_params,
3545                                        mlx5e_modify_tirs_packet_merge_ctx, NULL, reset);
3546 out:
3547         mutex_unlock(&priv->state_lock);
3548         return err;
3549 }
3550
3551 static int set_feature_hw_gro(struct net_device *netdev, bool enable)
3552 {
3553         struct mlx5e_priv *priv = netdev_priv(netdev);
3554         struct mlx5e_params new_params;
3555         bool reset = true;
3556         int err = 0;
3557
3558         mutex_lock(&priv->state_lock);
3559         new_params = priv->channels.params;
3560
3561         if (enable) {
3562                 if (MLX5E_GET_PFLAG(&new_params, MLX5E_PFLAG_RX_CQE_COMPRESS)) {
3563                         netdev_warn(netdev, "Can't set HW-GRO when CQE compress is active\n");
3564                         err = -EINVAL;
3565                         goto out;
3566                 }
3567                 new_params.packet_merge.type = MLX5E_PACKET_MERGE_SHAMPO;
3568                 new_params.packet_merge.shampo.match_criteria_type =
3569                         MLX5_RQC_SHAMPO_MATCH_CRITERIA_TYPE_EXTENDED;
3570                 new_params.packet_merge.shampo.alignment_granularity =
3571                         MLX5_RQC_SHAMPO_NO_MATCH_ALIGNMENT_GRANULARITY_STRIDE;
3572         } else if (new_params.packet_merge.type == MLX5E_PACKET_MERGE_SHAMPO) {
3573                 new_params.packet_merge.type = MLX5E_PACKET_MERGE_NONE;
3574         } else {
3575                 goto out;
3576         }
3577
3578         err = mlx5e_safe_switch_params(priv, &new_params,
3579                                        mlx5e_modify_tirs_packet_merge_ctx, NULL, reset);
3580 out:
3581         mutex_unlock(&priv->state_lock);
3582         return err;
3583 }
3584
3585 static int set_feature_cvlan_filter(struct net_device *netdev, bool enable)
3586 {
3587         struct mlx5e_priv *priv = netdev_priv(netdev);
3588
3589         if (enable)
3590                 mlx5e_enable_cvlan_filter(priv);
3591         else
3592                 mlx5e_disable_cvlan_filter(priv);
3593
3594         return 0;
3595 }
3596
3597 static int set_feature_hw_tc(struct net_device *netdev, bool enable)
3598 {
3599         struct mlx5e_priv *priv = netdev_priv(netdev);
3600
3601 #if IS_ENABLED(CONFIG_MLX5_CLS_ACT)
3602         if (!enable && mlx5e_tc_num_filters(priv, MLX5_TC_FLAG(NIC_OFFLOAD))) {
3603                 netdev_err(netdev,
3604                            "Active offloaded tc filters, can't turn hw_tc_offload off\n");
3605                 return -EINVAL;
3606         }
3607 #endif
3608
3609         if (!enable && priv->htb.maj_id) {
3610                 netdev_err(netdev, "Active HTB offload, can't turn hw_tc_offload off\n");
3611                 return -EINVAL;
3612         }
3613
3614         return 0;
3615 }
3616
3617 static int set_feature_rx_all(struct net_device *netdev, bool enable)
3618 {
3619         struct mlx5e_priv *priv = netdev_priv(netdev);
3620         struct mlx5_core_dev *mdev = priv->mdev;
3621
3622         return mlx5_set_port_fcs(mdev, !enable);
3623 }
3624
3625 static int mlx5e_set_rx_port_ts(struct mlx5_core_dev *mdev, bool enable)
3626 {
3627         u32 in[MLX5_ST_SZ_DW(pcmr_reg)] = {};
3628         bool supported, curr_state;
3629         int err;
3630
3631         if (!MLX5_CAP_GEN(mdev, ports_check))
3632                 return 0;
3633
3634         err = mlx5_query_ports_check(mdev, in, sizeof(in));
3635         if (err)
3636                 return err;
3637
3638         supported = MLX5_GET(pcmr_reg, in, rx_ts_over_crc_cap);
3639         curr_state = MLX5_GET(pcmr_reg, in, rx_ts_over_crc);
3640
3641         if (!supported || enable == curr_state)
3642                 return 0;
3643
3644         MLX5_SET(pcmr_reg, in, local_port, 1);
3645         MLX5_SET(pcmr_reg, in, rx_ts_over_crc, enable);
3646
3647         return mlx5_set_ports_check(mdev, in, sizeof(in));
3648 }
3649
3650 static int set_feature_rx_fcs(struct net_device *netdev, bool enable)
3651 {
3652         struct mlx5e_priv *priv = netdev_priv(netdev);
3653         struct mlx5e_channels *chs = &priv->channels;
3654         struct mlx5_core_dev *mdev = priv->mdev;
3655         int err;
3656
3657         mutex_lock(&priv->state_lock);
3658
3659         if (enable) {
3660                 err = mlx5e_set_rx_port_ts(mdev, false);
3661                 if (err)
3662                         goto out;
3663
3664                 chs->params.scatter_fcs_en = true;
3665                 err = mlx5e_modify_channels_scatter_fcs(chs, true);
3666                 if (err) {
3667                         chs->params.scatter_fcs_en = false;
3668                         mlx5e_set_rx_port_ts(mdev, true);
3669                 }
3670         } else {
3671                 chs->params.scatter_fcs_en = false;
3672                 err = mlx5e_modify_channels_scatter_fcs(chs, false);
3673                 if (err) {
3674                         chs->params.scatter_fcs_en = true;
3675                         goto out;
3676                 }
3677                 err = mlx5e_set_rx_port_ts(mdev, true);
3678                 if (err) {
3679                         mlx5_core_warn(mdev, "Failed to set RX port timestamp %d\n", err);
3680                         err = 0;
3681                 }
3682         }
3683
3684 out:
3685         mutex_unlock(&priv->state_lock);
3686         return err;
3687 }
3688
3689 static int set_feature_rx_vlan(struct net_device *netdev, bool enable)
3690 {
3691         struct mlx5e_priv *priv = netdev_priv(netdev);
3692         int err = 0;
3693
3694         mutex_lock(&priv->state_lock);
3695
3696         priv->channels.params.vlan_strip_disable = !enable;
3697         if (!test_bit(MLX5E_STATE_OPENED, &priv->state))
3698                 goto unlock;
3699
3700         err = mlx5e_modify_channels_vsd(&priv->channels, !enable);
3701         if (err)
3702                 priv->channels.params.vlan_strip_disable = enable;
3703
3704 unlock:
3705         mutex_unlock(&priv->state_lock);
3706
3707         return err;
3708 }
3709
3710 #ifdef CONFIG_MLX5_EN_ARFS
3711 static int set_feature_arfs(struct net_device *netdev, bool enable)
3712 {
3713         struct mlx5e_priv *priv = netdev_priv(netdev);
3714         int err;
3715
3716         if (enable)
3717                 err = mlx5e_arfs_enable(priv);
3718         else
3719                 err = mlx5e_arfs_disable(priv);
3720
3721         return err;
3722 }
3723 #endif
3724
3725 static int mlx5e_handle_feature(struct net_device *netdev,
3726                                 netdev_features_t *features,
3727                                 netdev_features_t wanted_features,
3728                                 netdev_features_t feature,
3729                                 mlx5e_feature_handler feature_handler)
3730 {
3731         netdev_features_t changes = wanted_features ^ netdev->features;
3732         bool enable = !!(wanted_features & feature);
3733         int err;
3734
3735         if (!(changes & feature))
3736                 return 0;
3737
3738         err = feature_handler(netdev, enable);
3739         if (err) {
3740                 netdev_err(netdev, "%s feature %pNF failed, err %d\n",
3741                            enable ? "Enable" : "Disable", &feature, err);
3742                 return err;
3743         }
3744
3745         MLX5E_SET_FEATURE(features, feature, enable);
3746         return 0;
3747 }
3748
3749 int mlx5e_set_features(struct net_device *netdev, netdev_features_t features)
3750 {
3751         netdev_features_t oper_features = netdev->features;
3752         int err = 0;
3753
3754 #define MLX5E_HANDLE_FEATURE(feature, handler) \
3755         mlx5e_handle_feature(netdev, &oper_features, features, feature, handler)
3756
3757         err |= MLX5E_HANDLE_FEATURE(NETIF_F_LRO, set_feature_lro);
3758         err |= MLX5E_HANDLE_FEATURE(NETIF_F_GRO_HW, set_feature_hw_gro);
3759         err |= MLX5E_HANDLE_FEATURE(NETIF_F_HW_VLAN_CTAG_FILTER,
3760                                     set_feature_cvlan_filter);
3761         err |= MLX5E_HANDLE_FEATURE(NETIF_F_HW_TC, set_feature_hw_tc);
3762         err |= MLX5E_HANDLE_FEATURE(NETIF_F_RXALL, set_feature_rx_all);
3763         err |= MLX5E_HANDLE_FEATURE(NETIF_F_RXFCS, set_feature_rx_fcs);
3764         err |= MLX5E_HANDLE_FEATURE(NETIF_F_HW_VLAN_CTAG_RX, set_feature_rx_vlan);
3765 #ifdef CONFIG_MLX5_EN_ARFS
3766         err |= MLX5E_HANDLE_FEATURE(NETIF_F_NTUPLE, set_feature_arfs);
3767 #endif
3768         err |= MLX5E_HANDLE_FEATURE(NETIF_F_HW_TLS_RX, mlx5e_ktls_set_feature_rx);
3769
3770         if (err) {
3771                 netdev->features = oper_features;
3772                 return -EINVAL;
3773         }
3774
3775         return 0;
3776 }
3777
3778 static netdev_features_t mlx5e_fix_uplink_rep_features(struct net_device *netdev,
3779                                                        netdev_features_t features)
3780 {
3781         features &= ~NETIF_F_HW_TLS_RX;
3782         if (netdev->features & NETIF_F_HW_TLS_RX)
3783                 netdev_warn(netdev, "Disabling hw_tls_rx, not supported in switchdev mode\n");
3784
3785         features &= ~NETIF_F_HW_TLS_TX;
3786         if (netdev->features & NETIF_F_HW_TLS_TX)
3787                 netdev_warn(netdev, "Disabling hw_tls_tx, not supported in switchdev mode\n");
3788
3789         features &= ~NETIF_F_NTUPLE;
3790         if (netdev->features & NETIF_F_NTUPLE)
3791                 netdev_warn(netdev, "Disabling ntuple, not supported in switchdev mode\n");
3792
3793         return features;
3794 }
3795
3796 static netdev_features_t mlx5e_fix_features(struct net_device *netdev,
3797                                             netdev_features_t features)
3798 {
3799         struct mlx5e_priv *priv = netdev_priv(netdev);
3800         struct mlx5e_params *params;
3801
3802         mutex_lock(&priv->state_lock);
3803         params = &priv->channels.params;
3804         if (!priv->fs.vlan ||
3805             !bitmap_empty(mlx5e_vlan_get_active_svlans(priv->fs.vlan), VLAN_N_VID)) {
3806                 /* HW strips the outer C-tag header, this is a problem
3807                  * for S-tag traffic.
3808                  */
3809                 features &= ~NETIF_F_HW_VLAN_CTAG_RX;
3810                 if (!params->vlan_strip_disable)
3811                         netdev_warn(netdev, "Dropping C-tag vlan stripping offload due to S-tag vlan\n");
3812         }
3813
3814         if (!MLX5E_GET_PFLAG(params, MLX5E_PFLAG_RX_STRIDING_RQ)) {
3815                 if (features & NETIF_F_LRO) {
3816                         netdev_warn(netdev, "Disabling LRO, not supported in legacy RQ\n");
3817                         features &= ~NETIF_F_LRO;
3818                 }
3819                 if (features & NETIF_F_GRO_HW) {
3820                         netdev_warn(netdev, "Disabling HW-GRO, not supported in legacy RQ\n");
3821                         features &= ~NETIF_F_GRO_HW;
3822                 }
3823         }
3824
3825         if (MLX5E_GET_PFLAG(params, MLX5E_PFLAG_RX_CQE_COMPRESS)) {
3826                 features &= ~NETIF_F_RXHASH;
3827                 if (netdev->features & NETIF_F_RXHASH)
3828                         netdev_warn(netdev, "Disabling rxhash, not supported when CQE compress is active\n");
3829         }
3830
3831         if (mlx5e_is_uplink_rep(priv))
3832                 features = mlx5e_fix_uplink_rep_features(netdev, features);
3833
3834         mutex_unlock(&priv->state_lock);
3835
3836         return features;
3837 }
3838
3839 static bool mlx5e_xsk_validate_mtu(struct net_device *netdev,
3840                                    struct mlx5e_channels *chs,
3841                                    struct mlx5e_params *new_params,
3842                                    struct mlx5_core_dev *mdev)
3843 {
3844         u16 ix;
3845
3846         for (ix = 0; ix < chs->params.num_channels; ix++) {
3847                 struct xsk_buff_pool *xsk_pool =
3848                         mlx5e_xsk_get_pool(&chs->params, chs->params.xsk, ix);
3849                 struct mlx5e_xsk_param xsk;
3850
3851                 if (!xsk_pool)
3852                         continue;
3853
3854                 mlx5e_build_xsk_param(xsk_pool, &xsk);
3855
3856                 if (!mlx5e_validate_xsk_param(new_params, &xsk, mdev)) {
3857                         u32 hr = mlx5e_get_linear_rq_headroom(new_params, &xsk);
3858                         int max_mtu_frame, max_mtu_page, max_mtu;
3859
3860                         /* Two criteria must be met:
3861                          * 1. HW MTU + all headrooms <= XSK frame size.
3862                          * 2. Size of SKBs allocated on XDP_PASS <= PAGE_SIZE.
3863                          */
3864                         max_mtu_frame = MLX5E_HW2SW_MTU(new_params, xsk.chunk_size - hr);
3865                         max_mtu_page = mlx5e_xdp_max_mtu(new_params, &xsk);
3866                         max_mtu = min(max_mtu_frame, max_mtu_page);
3867
3868                         netdev_err(netdev, "MTU %d is too big for an XSK running on channel %u. Try MTU <= %d\n",
3869                                    new_params->sw_mtu, ix, max_mtu);
3870                         return false;
3871                 }
3872         }
3873
3874         return true;
3875 }
3876
3877 int mlx5e_change_mtu(struct net_device *netdev, int new_mtu,
3878                      mlx5e_fp_preactivate preactivate)
3879 {
3880         struct mlx5e_priv *priv = netdev_priv(netdev);
3881         struct mlx5e_params new_params;
3882         struct mlx5e_params *params;
3883         bool reset = true;
3884         int err = 0;
3885
3886         mutex_lock(&priv->state_lock);
3887
3888         params = &priv->channels.params;
3889
3890         new_params = *params;
3891         new_params.sw_mtu = new_mtu;
3892         err = mlx5e_validate_params(priv->mdev, &new_params);
3893         if (err)
3894                 goto out;
3895
3896         if (params->xdp_prog &&
3897             !mlx5e_rx_is_linear_skb(&new_params, NULL)) {
3898                 netdev_err(netdev, "MTU(%d) > %d is not allowed while XDP enabled\n",
3899                            new_mtu, mlx5e_xdp_max_mtu(params, NULL));
3900                 err = -EINVAL;
3901                 goto out;
3902         }
3903
3904         if (priv->xsk.refcnt &&
3905             !mlx5e_xsk_validate_mtu(netdev, &priv->channels,
3906                                     &new_params, priv->mdev)) {
3907                 err = -EINVAL;
3908                 goto out;
3909         }
3910
3911         if (params->packet_merge.type == MLX5E_PACKET_MERGE_LRO)
3912                 reset = false;
3913
3914         if (params->rq_wq_type == MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ) {
3915                 bool is_linear_old = mlx5e_rx_mpwqe_is_linear_skb(priv->mdev, params, NULL);
3916                 bool is_linear_new = mlx5e_rx_mpwqe_is_linear_skb(priv->mdev,
3917                                                                   &new_params, NULL);
3918                 u8 ppw_old = mlx5e_mpwqe_log_pkts_per_wqe(params, NULL);
3919                 u8 ppw_new = mlx5e_mpwqe_log_pkts_per_wqe(&new_params, NULL);
3920
3921                 /* Always reset in linear mode - hw_mtu is used in data path.
3922                  * Check that the mode was non-linear and didn't change.
3923                  * If XSK is active, XSK RQs are linear.
3924                  */
3925                 if (!is_linear_old && !is_linear_new && !priv->xsk.refcnt &&
3926                     ppw_old == ppw_new)
3927                         reset = false;
3928         }
3929
3930         err = mlx5e_safe_switch_params(priv, &new_params, preactivate, NULL, reset);
3931
3932 out:
3933         netdev->mtu = params->sw_mtu;
3934         mutex_unlock(&priv->state_lock);
3935         return err;
3936 }
3937
3938 static int mlx5e_change_nic_mtu(struct net_device *netdev, int new_mtu)
3939 {
3940         return mlx5e_change_mtu(netdev, new_mtu, mlx5e_set_dev_port_mtu_ctx);
3941 }
3942
3943 int mlx5e_ptp_rx_manage_fs_ctx(struct mlx5e_priv *priv, void *ctx)
3944 {
3945         bool set  = *(bool *)ctx;
3946
3947         return mlx5e_ptp_rx_manage_fs(priv, set);
3948 }
3949
3950 static int mlx5e_hwstamp_config_no_ptp_rx(struct mlx5e_priv *priv, bool rx_filter)
3951 {
3952         bool rx_cqe_compress_def = priv->channels.params.rx_cqe_compress_def;
3953         int err;
3954
3955         if (!rx_filter)
3956                 /* Reset CQE compression to Admin default */
3957                 return mlx5e_modify_rx_cqe_compression_locked(priv, rx_cqe_compress_def, false);
3958
3959         if (!MLX5E_GET_PFLAG(&priv->channels.params, MLX5E_PFLAG_RX_CQE_COMPRESS))
3960                 return 0;
3961
3962         /* Disable CQE compression */
3963         netdev_warn(priv->netdev, "Disabling RX cqe compression\n");
3964         err = mlx5e_modify_rx_cqe_compression_locked(priv, false, true);
3965         if (err)
3966                 netdev_err(priv->netdev, "Failed disabling cqe compression err=%d\n", err);
3967
3968         return err;
3969 }
3970
3971 static int mlx5e_hwstamp_config_ptp_rx(struct mlx5e_priv *priv, bool ptp_rx)
3972 {
3973         struct mlx5e_params new_params;
3974
3975         if (ptp_rx == priv->channels.params.ptp_rx)
3976                 return 0;
3977
3978         new_params = priv->channels.params;
3979         new_params.ptp_rx = ptp_rx;
3980         return mlx5e_safe_switch_params(priv, &new_params, mlx5e_ptp_rx_manage_fs_ctx,
3981                                         &new_params.ptp_rx, true);
3982 }
3983
3984 int mlx5e_hwstamp_set(struct mlx5e_priv *priv, struct ifreq *ifr)
3985 {
3986         struct hwtstamp_config config;
3987         bool rx_cqe_compress_def;
3988         bool ptp_rx;
3989         int err;
3990
3991         if (!MLX5_CAP_GEN(priv->mdev, device_frequency_khz) ||
3992             (mlx5_clock_get_ptp_index(priv->mdev) == -1))
3993                 return -EOPNOTSUPP;
3994
3995         if (copy_from_user(&config, ifr->ifr_data, sizeof(config)))
3996                 return -EFAULT;
3997
3998         /* TX HW timestamp */
3999         switch (config.tx_type) {
4000         case HWTSTAMP_TX_OFF:
4001         case HWTSTAMP_TX_ON:
4002                 break;
4003         default:
4004                 return -ERANGE;
4005         }
4006
4007         mutex_lock(&priv->state_lock);
4008         rx_cqe_compress_def = priv->channels.params.rx_cqe_compress_def;
4009
4010         /* RX HW timestamp */
4011         switch (config.rx_filter) {
4012         case HWTSTAMP_FILTER_NONE:
4013                 ptp_rx = false;
4014                 break;
4015         case HWTSTAMP_FILTER_ALL:
4016         case HWTSTAMP_FILTER_SOME:
4017         case HWTSTAMP_FILTER_PTP_V1_L4_EVENT:
4018         case HWTSTAMP_FILTER_PTP_V1_L4_SYNC:
4019         case HWTSTAMP_FILTER_PTP_V1_L4_DELAY_REQ:
4020         case HWTSTAMP_FILTER_PTP_V2_L4_EVENT:
4021         case HWTSTAMP_FILTER_PTP_V2_L4_SYNC:
4022         case HWTSTAMP_FILTER_PTP_V2_L4_DELAY_REQ:
4023         case HWTSTAMP_FILTER_PTP_V2_L2_EVENT:
4024         case HWTSTAMP_FILTER_PTP_V2_L2_SYNC:
4025         case HWTSTAMP_FILTER_PTP_V2_L2_DELAY_REQ:
4026         case HWTSTAMP_FILTER_PTP_V2_EVENT:
4027         case HWTSTAMP_FILTER_PTP_V2_SYNC:
4028         case HWTSTAMP_FILTER_PTP_V2_DELAY_REQ:
4029         case HWTSTAMP_FILTER_NTP_ALL:
4030                 config.rx_filter = HWTSTAMP_FILTER_ALL;
4031                 /* ptp_rx is set if both HW TS is set and CQE
4032                  * compression is set
4033                  */
4034                 ptp_rx = rx_cqe_compress_def;
4035                 break;
4036         default:
4037                 err = -ERANGE;
4038                 goto err_unlock;
4039         }
4040
4041         if (!priv->profile->rx_ptp_support)
4042                 err = mlx5e_hwstamp_config_no_ptp_rx(priv,
4043                                                      config.rx_filter != HWTSTAMP_FILTER_NONE);
4044         else
4045                 err = mlx5e_hwstamp_config_ptp_rx(priv, ptp_rx);
4046         if (err)
4047                 goto err_unlock;
4048
4049         memcpy(&priv->tstamp, &config, sizeof(config));
4050         mutex_unlock(&priv->state_lock);
4051
4052         /* might need to fix some features */
4053         netdev_update_features(priv->netdev);
4054
4055         return copy_to_user(ifr->ifr_data, &config,
4056                             sizeof(config)) ? -EFAULT : 0;
4057 err_unlock:
4058         mutex_unlock(&priv->state_lock);
4059         return err;
4060 }
4061
4062 int mlx5e_hwstamp_get(struct mlx5e_priv *priv, struct ifreq *ifr)
4063 {
4064         struct hwtstamp_config *cfg = &priv->tstamp;
4065
4066         if (!MLX5_CAP_GEN(priv->mdev, device_frequency_khz))
4067                 return -EOPNOTSUPP;
4068
4069         return copy_to_user(ifr->ifr_data, cfg, sizeof(*cfg)) ? -EFAULT : 0;
4070 }
4071
4072 static int mlx5e_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
4073 {
4074         struct mlx5e_priv *priv = netdev_priv(dev);
4075
4076         switch (cmd) {
4077         case SIOCSHWTSTAMP:
4078                 return mlx5e_hwstamp_set(priv, ifr);
4079         case SIOCGHWTSTAMP:
4080                 return mlx5e_hwstamp_get(priv, ifr);
4081         default:
4082                 return -EOPNOTSUPP;
4083         }
4084 }
4085
4086 #ifdef CONFIG_MLX5_ESWITCH
4087 int mlx5e_set_vf_mac(struct net_device *dev, int vf, u8 *mac)
4088 {
4089         struct mlx5e_priv *priv = netdev_priv(dev);
4090         struct mlx5_core_dev *mdev = priv->mdev;
4091
4092         return mlx5_eswitch_set_vport_mac(mdev->priv.eswitch, vf + 1, mac);
4093 }
4094
4095 static int mlx5e_set_vf_vlan(struct net_device *dev, int vf, u16 vlan, u8 qos,
4096                              __be16 vlan_proto)
4097 {
4098         struct mlx5e_priv *priv = netdev_priv(dev);
4099         struct mlx5_core_dev *mdev = priv->mdev;
4100
4101         if (vlan_proto != htons(ETH_P_8021Q))
4102                 return -EPROTONOSUPPORT;
4103
4104         return mlx5_eswitch_set_vport_vlan(mdev->priv.eswitch, vf + 1,
4105                                            vlan, qos);
4106 }
4107
4108 static int mlx5e_set_vf_spoofchk(struct net_device *dev, int vf, bool setting)
4109 {
4110         struct mlx5e_priv *priv = netdev_priv(dev);
4111         struct mlx5_core_dev *mdev = priv->mdev;
4112
4113         return mlx5_eswitch_set_vport_spoofchk(mdev->priv.eswitch, vf + 1, setting);
4114 }
4115
4116 static int mlx5e_set_vf_trust(struct net_device *dev, int vf, bool setting)
4117 {
4118         struct mlx5e_priv *priv = netdev_priv(dev);
4119         struct mlx5_core_dev *mdev = priv->mdev;
4120
4121         return mlx5_eswitch_set_vport_trust(mdev->priv.eswitch, vf + 1, setting);
4122 }
4123
4124 int mlx5e_set_vf_rate(struct net_device *dev, int vf, int min_tx_rate,
4125                       int max_tx_rate)
4126 {
4127         struct mlx5e_priv *priv = netdev_priv(dev);
4128         struct mlx5_core_dev *mdev = priv->mdev;
4129
4130         return mlx5_eswitch_set_vport_rate(mdev->priv.eswitch, vf + 1,
4131                                            max_tx_rate, min_tx_rate);
4132 }
4133
4134 static int mlx5_vport_link2ifla(u8 esw_link)
4135 {
4136         switch (esw_link) {
4137         case MLX5_VPORT_ADMIN_STATE_DOWN:
4138                 return IFLA_VF_LINK_STATE_DISABLE;
4139         case MLX5_VPORT_ADMIN_STATE_UP:
4140                 return IFLA_VF_LINK_STATE_ENABLE;
4141         }
4142         return IFLA_VF_LINK_STATE_AUTO;
4143 }
4144
4145 static int mlx5_ifla_link2vport(u8 ifla_link)
4146 {
4147         switch (ifla_link) {
4148         case IFLA_VF_LINK_STATE_DISABLE:
4149                 return MLX5_VPORT_ADMIN_STATE_DOWN;
4150         case IFLA_VF_LINK_STATE_ENABLE:
4151                 return MLX5_VPORT_ADMIN_STATE_UP;
4152         }
4153         return MLX5_VPORT_ADMIN_STATE_AUTO;
4154 }
4155
4156 static int mlx5e_set_vf_link_state(struct net_device *dev, int vf,
4157                                    int link_state)
4158 {
4159         struct mlx5e_priv *priv = netdev_priv(dev);
4160         struct mlx5_core_dev *mdev = priv->mdev;
4161
4162         if (mlx5e_is_uplink_rep(priv))
4163                 return -EOPNOTSUPP;
4164
4165         return mlx5_eswitch_set_vport_state(mdev->priv.eswitch, vf + 1,
4166                                             mlx5_ifla_link2vport(link_state));
4167 }
4168
4169 int mlx5e_get_vf_config(struct net_device *dev,
4170                         int vf, struct ifla_vf_info *ivi)
4171 {
4172         struct mlx5e_priv *priv = netdev_priv(dev);
4173         struct mlx5_core_dev *mdev = priv->mdev;
4174         int err;
4175
4176         if (!netif_device_present(dev))
4177                 return -EOPNOTSUPP;
4178
4179         err = mlx5_eswitch_get_vport_config(mdev->priv.eswitch, vf + 1, ivi);
4180         if (err)
4181                 return err;
4182         ivi->linkstate = mlx5_vport_link2ifla(ivi->linkstate);
4183         return 0;
4184 }
4185
4186 int mlx5e_get_vf_stats(struct net_device *dev,
4187                        int vf, struct ifla_vf_stats *vf_stats)
4188 {
4189         struct mlx5e_priv *priv = netdev_priv(dev);
4190         struct mlx5_core_dev *mdev = priv->mdev;
4191
4192         return mlx5_eswitch_get_vport_stats(mdev->priv.eswitch, vf + 1,
4193                                             vf_stats);
4194 }
4195
4196 static bool
4197 mlx5e_has_offload_stats(const struct net_device *dev, int attr_id)
4198 {
4199         struct mlx5e_priv *priv = netdev_priv(dev);
4200
4201         if (!netif_device_present(dev))
4202                 return false;
4203
4204         if (!mlx5e_is_uplink_rep(priv))
4205                 return false;
4206
4207         return mlx5e_rep_has_offload_stats(dev, attr_id);
4208 }
4209
4210 static int
4211 mlx5e_get_offload_stats(int attr_id, const struct net_device *dev,
4212                         void *sp)
4213 {
4214         struct mlx5e_priv *priv = netdev_priv(dev);
4215
4216         if (!mlx5e_is_uplink_rep(priv))
4217                 return -EOPNOTSUPP;
4218
4219         return mlx5e_rep_get_offload_stats(attr_id, dev, sp);
4220 }
4221 #endif
4222
4223 static bool mlx5e_tunnel_proto_supported_tx(struct mlx5_core_dev *mdev, u8 proto_type)
4224 {
4225         switch (proto_type) {
4226         case IPPROTO_GRE:
4227                 return MLX5_CAP_ETH(mdev, tunnel_stateless_gre);
4228         case IPPROTO_IPIP:
4229         case IPPROTO_IPV6:
4230                 return (MLX5_CAP_ETH(mdev, tunnel_stateless_ip_over_ip) ||
4231                         MLX5_CAP_ETH(mdev, tunnel_stateless_ip_over_ip_tx));
4232         default:
4233                 return false;
4234         }
4235 }
4236
4237 static bool mlx5e_gre_tunnel_inner_proto_offload_supported(struct mlx5_core_dev *mdev,
4238                                                            struct sk_buff *skb)
4239 {
4240         switch (skb->inner_protocol) {
4241         case htons(ETH_P_IP):
4242         case htons(ETH_P_IPV6):
4243         case htons(ETH_P_TEB):
4244                 return true;
4245         case htons(ETH_P_MPLS_UC):
4246         case htons(ETH_P_MPLS_MC):
4247                 return MLX5_CAP_ETH(mdev, tunnel_stateless_mpls_over_gre);
4248         }
4249         return false;
4250 }
4251
4252 static netdev_features_t mlx5e_tunnel_features_check(struct mlx5e_priv *priv,
4253                                                      struct sk_buff *skb,
4254                                                      netdev_features_t features)
4255 {
4256         unsigned int offset = 0;
4257         struct udphdr *udph;
4258         u8 proto;
4259         u16 port;
4260
4261         switch (vlan_get_protocol(skb)) {
4262         case htons(ETH_P_IP):
4263                 proto = ip_hdr(skb)->protocol;
4264                 break;
4265         case htons(ETH_P_IPV6):
4266                 proto = ipv6_find_hdr(skb, &offset, -1, NULL, NULL);
4267                 break;
4268         default:
4269                 goto out;
4270         }
4271
4272         switch (proto) {
4273         case IPPROTO_GRE:
4274                 if (mlx5e_gre_tunnel_inner_proto_offload_supported(priv->mdev, skb))
4275                         return features;
4276                 break;
4277         case IPPROTO_IPIP:
4278         case IPPROTO_IPV6:
4279                 if (mlx5e_tunnel_proto_supported_tx(priv->mdev, IPPROTO_IPIP))
4280                         return features;
4281                 break;
4282         case IPPROTO_UDP:
4283                 udph = udp_hdr(skb);
4284                 port = be16_to_cpu(udph->dest);
4285
4286                 /* Verify if UDP port is being offloaded by HW */
4287                 if (mlx5_vxlan_lookup_port(priv->mdev->vxlan, port))
4288                         return features;
4289
4290 #if IS_ENABLED(CONFIG_GENEVE)
4291                 /* Support Geneve offload for default UDP port */
4292                 if (port == GENEVE_UDP_PORT && mlx5_geneve_tx_allowed(priv->mdev))
4293                         return features;
4294 #endif
4295                 break;
4296 #ifdef CONFIG_MLX5_EN_IPSEC
4297         case IPPROTO_ESP:
4298                 return mlx5e_ipsec_feature_check(skb, features);
4299 #endif
4300         }
4301
4302 out:
4303         /* Disable CSUM and GSO if the udp dport is not offloaded by HW */
4304         return features & ~(NETIF_F_CSUM_MASK | NETIF_F_GSO_MASK);
4305 }
4306
4307 netdev_features_t mlx5e_features_check(struct sk_buff *skb,
4308                                        struct net_device *netdev,
4309                                        netdev_features_t features)
4310 {
4311         struct mlx5e_priv *priv = netdev_priv(netdev);
4312
4313         features = vlan_features_check(skb, features);
4314         features = vxlan_features_check(skb, features);
4315
4316         /* Validate if the tunneled packet is being offloaded by HW */
4317         if (skb->encapsulation &&
4318             (features & NETIF_F_CSUM_MASK || features & NETIF_F_GSO_MASK))
4319                 return mlx5e_tunnel_features_check(priv, skb, features);
4320
4321         return features;
4322 }
4323
4324 static void mlx5e_tx_timeout_work(struct work_struct *work)
4325 {
4326         struct mlx5e_priv *priv = container_of(work, struct mlx5e_priv,
4327                                                tx_timeout_work);
4328         struct net_device *netdev = priv->netdev;
4329         int i;
4330
4331         rtnl_lock();
4332         mutex_lock(&priv->state_lock);
4333
4334         if (!test_bit(MLX5E_STATE_OPENED, &priv->state))
4335                 goto unlock;
4336
4337         for (i = 0; i < netdev->real_num_tx_queues; i++) {
4338                 struct netdev_queue *dev_queue =
4339                         netdev_get_tx_queue(netdev, i);
4340                 struct mlx5e_txqsq *sq = priv->txq2sq[i];
4341
4342                 if (!netif_xmit_stopped(dev_queue))
4343                         continue;
4344
4345                 if (mlx5e_reporter_tx_timeout(sq))
4346                 /* break if tried to reopened channels */
4347                         break;
4348         }
4349
4350 unlock:
4351         mutex_unlock(&priv->state_lock);
4352         rtnl_unlock();
4353 }
4354
4355 static void mlx5e_tx_timeout(struct net_device *dev, unsigned int txqueue)
4356 {
4357         struct mlx5e_priv *priv = netdev_priv(dev);
4358
4359         netdev_err(dev, "TX timeout detected\n");
4360         queue_work(priv->wq, &priv->tx_timeout_work);
4361 }
4362
4363 static int mlx5e_xdp_allowed(struct mlx5e_priv *priv, struct bpf_prog *prog)
4364 {
4365         struct net_device *netdev = priv->netdev;
4366         struct mlx5e_params new_params;
4367
4368         if (priv->channels.params.packet_merge.type != MLX5E_PACKET_MERGE_NONE) {
4369                 netdev_warn(netdev, "can't set XDP while HW-GRO/LRO is on, disable them first\n");
4370                 return -EINVAL;
4371         }
4372
4373         if (mlx5_fpga_is_ipsec_device(priv->mdev)) {
4374                 netdev_warn(netdev,
4375                             "XDP is not available on Innova cards with IPsec support\n");
4376                 return -EINVAL;
4377         }
4378
4379         new_params = priv->channels.params;
4380         new_params.xdp_prog = prog;
4381
4382         /* No XSK params: AF_XDP can't be enabled yet at the point of setting
4383          * the XDP program.
4384          */
4385         if (!mlx5e_rx_is_linear_skb(&new_params, NULL)) {
4386                 netdev_warn(netdev, "XDP is not allowed with MTU(%d) > %d\n",
4387                             new_params.sw_mtu,
4388                             mlx5e_xdp_max_mtu(&new_params, NULL));
4389                 return -EINVAL;
4390         }
4391
4392         return 0;
4393 }
4394
4395 static void mlx5e_rq_replace_xdp_prog(struct mlx5e_rq *rq, struct bpf_prog *prog)
4396 {
4397         struct bpf_prog *old_prog;
4398
4399         old_prog = rcu_replace_pointer(rq->xdp_prog, prog,
4400                                        lockdep_is_held(&rq->priv->state_lock));
4401         if (old_prog)
4402                 bpf_prog_put(old_prog);
4403 }
4404
4405 static int mlx5e_xdp_set(struct net_device *netdev, struct bpf_prog *prog)
4406 {
4407         struct mlx5e_priv *priv = netdev_priv(netdev);
4408         struct mlx5e_params new_params;
4409         struct bpf_prog *old_prog;
4410         int err = 0;
4411         bool reset;
4412         int i;
4413
4414         mutex_lock(&priv->state_lock);
4415
4416         if (prog) {
4417                 err = mlx5e_xdp_allowed(priv, prog);
4418                 if (err)
4419                         goto unlock;
4420         }
4421
4422         /* no need for full reset when exchanging programs */
4423         reset = (!priv->channels.params.xdp_prog || !prog);
4424
4425         new_params = priv->channels.params;
4426         new_params.xdp_prog = prog;
4427         if (reset)
4428                 mlx5e_set_rq_type(priv->mdev, &new_params);
4429         old_prog = priv->channels.params.xdp_prog;
4430
4431         err = mlx5e_safe_switch_params(priv, &new_params, NULL, NULL, reset);
4432         if (err)
4433                 goto unlock;
4434
4435         if (old_prog)
4436                 bpf_prog_put(old_prog);
4437
4438         if (!test_bit(MLX5E_STATE_OPENED, &priv->state) || reset)
4439                 goto unlock;
4440
4441         /* exchanging programs w/o reset, we update ref counts on behalf
4442          * of the channels RQs here.
4443          */
4444         bpf_prog_add(prog, priv->channels.num);
4445         for (i = 0; i < priv->channels.num; i++) {
4446                 struct mlx5e_channel *c = priv->channels.c[i];
4447
4448                 mlx5e_rq_replace_xdp_prog(&c->rq, prog);
4449                 if (test_bit(MLX5E_CHANNEL_STATE_XSK, c->state)) {
4450                         bpf_prog_inc(prog);
4451                         mlx5e_rq_replace_xdp_prog(&c->xskrq, prog);
4452                 }
4453         }
4454
4455 unlock:
4456         mutex_unlock(&priv->state_lock);
4457         return err;
4458 }
4459
4460 static int mlx5e_xdp(struct net_device *dev, struct netdev_bpf *xdp)
4461 {
4462         switch (xdp->command) {
4463         case XDP_SETUP_PROG:
4464                 return mlx5e_xdp_set(dev, xdp->prog);
4465         case XDP_SETUP_XSK_POOL:
4466                 return mlx5e_xsk_setup_pool(dev, xdp->xsk.pool,
4467                                             xdp->xsk.queue_id);
4468         default:
4469                 return -EINVAL;
4470         }
4471 }
4472
4473 #ifdef CONFIG_MLX5_ESWITCH
4474 static int mlx5e_bridge_getlink(struct sk_buff *skb, u32 pid, u32 seq,
4475                                 struct net_device *dev, u32 filter_mask,
4476                                 int nlflags)
4477 {
4478         struct mlx5e_priv *priv = netdev_priv(dev);
4479         struct mlx5_core_dev *mdev = priv->mdev;
4480         u8 mode, setting;
4481         int err;
4482
4483         err = mlx5_eswitch_get_vepa(mdev->priv.eswitch, &setting);
4484         if (err)
4485                 return err;
4486         mode = setting ? BRIDGE_MODE_VEPA : BRIDGE_MODE_VEB;
4487         return ndo_dflt_bridge_getlink(skb, pid, seq, dev,
4488                                        mode,
4489                                        0, 0, nlflags, filter_mask, NULL);
4490 }
4491
4492 static int mlx5e_bridge_setlink(struct net_device *dev, struct nlmsghdr *nlh,
4493                                 u16 flags, struct netlink_ext_ack *extack)
4494 {
4495         struct mlx5e_priv *priv = netdev_priv(dev);
4496         struct mlx5_core_dev *mdev = priv->mdev;
4497         struct nlattr *attr, *br_spec;
4498         u16 mode = BRIDGE_MODE_UNDEF;
4499         u8 setting;
4500         int rem;
4501
4502         br_spec = nlmsg_find_attr(nlh, sizeof(struct ifinfomsg), IFLA_AF_SPEC);
4503         if (!br_spec)
4504                 return -EINVAL;
4505
4506         nla_for_each_nested(attr, br_spec, rem) {
4507                 if (nla_type(attr) != IFLA_BRIDGE_MODE)
4508                         continue;
4509
4510                 if (nla_len(attr) < sizeof(mode))
4511                         return -EINVAL;
4512
4513                 mode = nla_get_u16(attr);
4514                 if (mode > BRIDGE_MODE_VEPA)
4515                         return -EINVAL;
4516
4517                 break;
4518         }
4519
4520         if (mode == BRIDGE_MODE_UNDEF)
4521                 return -EINVAL;
4522
4523         setting = (mode == BRIDGE_MODE_VEPA) ?  1 : 0;
4524         return mlx5_eswitch_set_vepa(mdev->priv.eswitch, setting);
4525 }
4526 #endif
4527
4528 const struct net_device_ops mlx5e_netdev_ops = {
4529         .ndo_open                = mlx5e_open,
4530         .ndo_stop                = mlx5e_close,
4531         .ndo_start_xmit          = mlx5e_xmit,
4532         .ndo_setup_tc            = mlx5e_setup_tc,
4533         .ndo_select_queue        = mlx5e_select_queue,
4534         .ndo_get_stats64         = mlx5e_get_stats,
4535         .ndo_set_rx_mode         = mlx5e_set_rx_mode,
4536         .ndo_set_mac_address     = mlx5e_set_mac,
4537         .ndo_vlan_rx_add_vid     = mlx5e_vlan_rx_add_vid,
4538         .ndo_vlan_rx_kill_vid    = mlx5e_vlan_rx_kill_vid,
4539         .ndo_set_features        = mlx5e_set_features,
4540         .ndo_fix_features        = mlx5e_fix_features,
4541         .ndo_change_mtu          = mlx5e_change_nic_mtu,
4542         .ndo_eth_ioctl            = mlx5e_ioctl,
4543         .ndo_set_tx_maxrate      = mlx5e_set_tx_maxrate,
4544         .ndo_features_check      = mlx5e_features_check,
4545         .ndo_tx_timeout          = mlx5e_tx_timeout,
4546         .ndo_bpf                 = mlx5e_xdp,
4547         .ndo_xdp_xmit            = mlx5e_xdp_xmit,
4548         .ndo_xsk_wakeup          = mlx5e_xsk_wakeup,
4549 #ifdef CONFIG_MLX5_EN_ARFS
4550         .ndo_rx_flow_steer       = mlx5e_rx_flow_steer,
4551 #endif
4552 #ifdef CONFIG_MLX5_ESWITCH
4553         .ndo_bridge_setlink      = mlx5e_bridge_setlink,
4554         .ndo_bridge_getlink      = mlx5e_bridge_getlink,
4555
4556         /* SRIOV E-Switch NDOs */
4557         .ndo_set_vf_mac          = mlx5e_set_vf_mac,
4558         .ndo_set_vf_vlan         = mlx5e_set_vf_vlan,
4559         .ndo_set_vf_spoofchk     = mlx5e_set_vf_spoofchk,
4560         .ndo_set_vf_trust        = mlx5e_set_vf_trust,
4561         .ndo_set_vf_rate         = mlx5e_set_vf_rate,
4562         .ndo_get_vf_config       = mlx5e_get_vf_config,
4563         .ndo_set_vf_link_state   = mlx5e_set_vf_link_state,
4564         .ndo_get_vf_stats        = mlx5e_get_vf_stats,
4565         .ndo_has_offload_stats   = mlx5e_has_offload_stats,
4566         .ndo_get_offload_stats   = mlx5e_get_offload_stats,
4567 #endif
4568         .ndo_get_devlink_port    = mlx5e_get_devlink_port,
4569 };
4570
4571 static u32 mlx5e_choose_lro_timeout(struct mlx5_core_dev *mdev, u32 wanted_timeout)
4572 {
4573         int i;
4574
4575         /* The supported periods are organized in ascending order */
4576         for (i = 0; i < MLX5E_LRO_TIMEOUT_ARR_SIZE - 1; i++)
4577                 if (MLX5_CAP_ETH(mdev, lro_timer_supported_periods[i]) >= wanted_timeout)
4578                         break;
4579
4580         return MLX5_CAP_ETH(mdev, lro_timer_supported_periods[i]);
4581 }
4582
4583 void mlx5e_build_nic_params(struct mlx5e_priv *priv, struct mlx5e_xsk *xsk, u16 mtu)
4584 {
4585         struct mlx5e_params *params = &priv->channels.params;
4586         struct mlx5_core_dev *mdev = priv->mdev;
4587         u8 rx_cq_period_mode;
4588
4589         params->sw_mtu = mtu;
4590         params->hard_mtu = MLX5E_ETH_HARD_MTU;
4591         params->num_channels = min_t(unsigned int, MLX5E_MAX_NUM_CHANNELS / 2,
4592                                      priv->max_nch);
4593         mlx5e_params_mqprio_reset(params);
4594
4595         /* Set an initial non-zero value, so that mlx5e_select_queue won't
4596          * divide by zero if called before first activating channels.
4597          */
4598         priv->num_tc_x_num_ch = params->num_channels * params->mqprio.num_tc;
4599
4600         /* SQ */
4601         params->log_sq_size = is_kdump_kernel() ?
4602                 MLX5E_PARAMS_MINIMUM_LOG_SQ_SIZE :
4603                 MLX5E_PARAMS_DEFAULT_LOG_SQ_SIZE;
4604         MLX5E_SET_PFLAG(params, MLX5E_PFLAG_SKB_TX_MPWQE, mlx5e_tx_mpwqe_supported(mdev));
4605
4606         /* XDP SQ */
4607         MLX5E_SET_PFLAG(params, MLX5E_PFLAG_XDP_TX_MPWQE, mlx5e_tx_mpwqe_supported(mdev));
4608
4609         /* set CQE compression */
4610         params->rx_cqe_compress_def = false;
4611         if (MLX5_CAP_GEN(mdev, cqe_compression) &&
4612             MLX5_CAP_GEN(mdev, vport_group_manager))
4613                 params->rx_cqe_compress_def = slow_pci_heuristic(mdev);
4614
4615         MLX5E_SET_PFLAG(params, MLX5E_PFLAG_RX_CQE_COMPRESS, params->rx_cqe_compress_def);
4616         MLX5E_SET_PFLAG(params, MLX5E_PFLAG_RX_NO_CSUM_COMPLETE, false);
4617
4618         /* RQ */
4619         mlx5e_build_rq_params(mdev, params);
4620
4621         /* HW LRO */
4622         if (MLX5_CAP_ETH(mdev, lro_cap) &&
4623             params->rq_wq_type == MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ) {
4624                 /* No XSK params: checking the availability of striding RQ in general. */
4625                 if (!mlx5e_rx_mpwqe_is_linear_skb(mdev, params, NULL))
4626                         params->packet_merge.type = slow_pci_heuristic(mdev) ?
4627                                 MLX5E_PACKET_MERGE_NONE : MLX5E_PACKET_MERGE_LRO;
4628         }
4629         params->packet_merge.timeout = mlx5e_choose_lro_timeout(mdev, MLX5E_DEFAULT_LRO_TIMEOUT);
4630
4631         /* CQ moderation params */
4632         rx_cq_period_mode = MLX5_CAP_GEN(mdev, cq_period_start_from_cqe) ?
4633                         MLX5_CQ_PERIOD_MODE_START_FROM_CQE :
4634                         MLX5_CQ_PERIOD_MODE_START_FROM_EQE;
4635         params->rx_dim_enabled = MLX5_CAP_GEN(mdev, cq_moderation);
4636         params->tx_dim_enabled = MLX5_CAP_GEN(mdev, cq_moderation);
4637         mlx5e_set_rx_cq_mode_params(params, rx_cq_period_mode);
4638         mlx5e_set_tx_cq_mode_params(params, MLX5_CQ_PERIOD_MODE_START_FROM_EQE);
4639
4640         /* TX inline */
4641         mlx5_query_min_inline(mdev, &params->tx_min_inline_mode);
4642
4643         params->tunneled_offload_en = mlx5_tunnel_inner_ft_supported(mdev);
4644
4645         /* AF_XDP */
4646         params->xsk = xsk;
4647
4648         /* Do not update netdev->features directly in here
4649          * on mlx5e_attach_netdev() we will call mlx5e_update_features()
4650          * To update netdev->features please modify mlx5e_fix_features()
4651          */
4652 }
4653
4654 static void mlx5e_set_netdev_dev_addr(struct net_device *netdev)
4655 {
4656         struct mlx5e_priv *priv = netdev_priv(netdev);
4657         u8 addr[ETH_ALEN];
4658
4659         mlx5_query_mac_address(priv->mdev, addr);
4660         if (is_zero_ether_addr(addr) &&
4661             !MLX5_CAP_GEN(priv->mdev, vport_group_manager)) {
4662                 eth_hw_addr_random(netdev);
4663                 mlx5_core_info(priv->mdev, "Assigned random MAC address %pM\n", netdev->dev_addr);
4664                 return;
4665         }
4666
4667         eth_hw_addr_set(netdev, addr);
4668 }
4669
4670 static int mlx5e_vxlan_set_port(struct net_device *netdev, unsigned int table,
4671                                 unsigned int entry, struct udp_tunnel_info *ti)
4672 {
4673         struct mlx5e_priv *priv = netdev_priv(netdev);
4674
4675         return mlx5_vxlan_add_port(priv->mdev->vxlan, ntohs(ti->port));
4676 }
4677
4678 static int mlx5e_vxlan_unset_port(struct net_device *netdev, unsigned int table,
4679                                   unsigned int entry, struct udp_tunnel_info *ti)
4680 {
4681         struct mlx5e_priv *priv = netdev_priv(netdev);
4682
4683         return mlx5_vxlan_del_port(priv->mdev->vxlan, ntohs(ti->port));
4684 }
4685
4686 void mlx5e_vxlan_set_netdev_info(struct mlx5e_priv *priv)
4687 {
4688         if (!mlx5_vxlan_allowed(priv->mdev->vxlan))
4689                 return;
4690
4691         priv->nic_info.set_port = mlx5e_vxlan_set_port;
4692         priv->nic_info.unset_port = mlx5e_vxlan_unset_port;
4693         priv->nic_info.flags = UDP_TUNNEL_NIC_INFO_MAY_SLEEP |
4694                                 UDP_TUNNEL_NIC_INFO_STATIC_IANA_VXLAN;
4695         priv->nic_info.tables[0].tunnel_types = UDP_TUNNEL_TYPE_VXLAN;
4696         /* Don't count the space hard-coded to the IANA port */
4697         priv->nic_info.tables[0].n_entries =
4698                 mlx5_vxlan_max_udp_ports(priv->mdev) - 1;
4699
4700         priv->netdev->udp_tunnel_nic_info = &priv->nic_info;
4701 }
4702
4703 static bool mlx5e_tunnel_any_tx_proto_supported(struct mlx5_core_dev *mdev)
4704 {
4705         int tt;
4706
4707         for (tt = 0; tt < MLX5_NUM_TUNNEL_TT; tt++) {
4708                 if (mlx5e_tunnel_proto_supported_tx(mdev, mlx5_get_proto_by_tunnel_type(tt)))
4709                         return true;
4710         }
4711         return (mlx5_vxlan_allowed(mdev->vxlan) || mlx5_geneve_tx_allowed(mdev));
4712 }
4713
4714 static void mlx5e_build_nic_netdev(struct net_device *netdev)
4715 {
4716         struct mlx5e_priv *priv = netdev_priv(netdev);
4717         struct mlx5_core_dev *mdev = priv->mdev;
4718         bool fcs_supported;
4719         bool fcs_enabled;
4720
4721         SET_NETDEV_DEV(netdev, mdev->device);
4722
4723         netdev->netdev_ops = &mlx5e_netdev_ops;
4724
4725         mlx5e_dcbnl_build_netdev(netdev);
4726
4727         netdev->watchdog_timeo    = 15 * HZ;
4728
4729         netdev->ethtool_ops       = &mlx5e_ethtool_ops;
4730
4731         netdev->vlan_features    |= NETIF_F_SG;
4732         netdev->vlan_features    |= NETIF_F_HW_CSUM;
4733         netdev->vlan_features    |= NETIF_F_GRO;
4734         netdev->vlan_features    |= NETIF_F_TSO;
4735         netdev->vlan_features    |= NETIF_F_TSO6;
4736         netdev->vlan_features    |= NETIF_F_RXCSUM;
4737         netdev->vlan_features    |= NETIF_F_RXHASH;
4738
4739         netdev->mpls_features    |= NETIF_F_SG;
4740         netdev->mpls_features    |= NETIF_F_HW_CSUM;
4741         netdev->mpls_features    |= NETIF_F_TSO;
4742         netdev->mpls_features    |= NETIF_F_TSO6;
4743
4744         netdev->hw_enc_features  |= NETIF_F_HW_VLAN_CTAG_TX;
4745         netdev->hw_enc_features  |= NETIF_F_HW_VLAN_CTAG_RX;
4746
4747         /* Tunneled LRO is not supported in the driver, and the same RQs are
4748          * shared between inner and outer TIRs, so the driver can't disable LRO
4749          * for inner TIRs while having it enabled for outer TIRs. Due to this,
4750          * block LRO altogether if the firmware declares tunneled LRO support.
4751          */
4752         if (!!MLX5_CAP_ETH(mdev, lro_cap) &&
4753             !MLX5_CAP_ETH(mdev, tunnel_lro_vxlan) &&
4754             !MLX5_CAP_ETH(mdev, tunnel_lro_gre) &&
4755             mlx5e_check_fragmented_striding_rq_cap(mdev))
4756                 netdev->vlan_features    |= NETIF_F_LRO;
4757
4758         netdev->hw_features       = netdev->vlan_features;
4759         netdev->hw_features      |= NETIF_F_HW_VLAN_CTAG_TX;
4760         netdev->hw_features      |= NETIF_F_HW_VLAN_CTAG_RX;
4761         netdev->hw_features      |= NETIF_F_HW_VLAN_CTAG_FILTER;
4762         netdev->hw_features      |= NETIF_F_HW_VLAN_STAG_TX;
4763
4764         if (!!MLX5_CAP_GEN(mdev, shampo) &&
4765             mlx5e_check_fragmented_striding_rq_cap(mdev))
4766                 netdev->hw_features    |= NETIF_F_GRO_HW;
4767
4768         if (mlx5e_tunnel_any_tx_proto_supported(mdev)) {
4769                 netdev->hw_enc_features |= NETIF_F_HW_CSUM;
4770                 netdev->hw_enc_features |= NETIF_F_TSO;
4771                 netdev->hw_enc_features |= NETIF_F_TSO6;
4772                 netdev->hw_enc_features |= NETIF_F_GSO_PARTIAL;
4773         }
4774
4775         if (mlx5_vxlan_allowed(mdev->vxlan) || mlx5_geneve_tx_allowed(mdev)) {
4776                 netdev->hw_features     |= NETIF_F_GSO_UDP_TUNNEL;
4777                 netdev->hw_enc_features |= NETIF_F_GSO_UDP_TUNNEL;
4778                 netdev->vlan_features |= NETIF_F_GSO_UDP_TUNNEL;
4779         }
4780
4781         if (mlx5e_tunnel_proto_supported_tx(mdev, IPPROTO_GRE)) {
4782                 netdev->hw_features     |= NETIF_F_GSO_GRE;
4783                 netdev->hw_enc_features |= NETIF_F_GSO_GRE;
4784                 netdev->gso_partial_features |= NETIF_F_GSO_GRE;
4785         }
4786
4787         if (mlx5e_tunnel_proto_supported_tx(mdev, IPPROTO_IPIP)) {
4788                 netdev->hw_features |= NETIF_F_GSO_IPXIP4 |
4789                                        NETIF_F_GSO_IPXIP6;
4790                 netdev->hw_enc_features |= NETIF_F_GSO_IPXIP4 |
4791                                            NETIF_F_GSO_IPXIP6;
4792                 netdev->gso_partial_features |= NETIF_F_GSO_IPXIP4 |
4793                                                 NETIF_F_GSO_IPXIP6;
4794         }
4795
4796         netdev->hw_features                      |= NETIF_F_GSO_PARTIAL;
4797         netdev->gso_partial_features             |= NETIF_F_GSO_UDP_L4;
4798         netdev->hw_features                      |= NETIF_F_GSO_UDP_L4;
4799         netdev->features                         |= NETIF_F_GSO_UDP_L4;
4800
4801         mlx5_query_port_fcs(mdev, &fcs_supported, &fcs_enabled);
4802
4803         if (fcs_supported)
4804                 netdev->hw_features |= NETIF_F_RXALL;
4805
4806         if (MLX5_CAP_ETH(mdev, scatter_fcs))
4807                 netdev->hw_features |= NETIF_F_RXFCS;
4808
4809         if (mlx5_qos_is_supported(mdev))
4810                 netdev->hw_features |= NETIF_F_HW_TC;
4811
4812         netdev->features          = netdev->hw_features;
4813
4814         /* Defaults */
4815         if (fcs_enabled)
4816                 netdev->features  &= ~NETIF_F_RXALL;
4817         netdev->features  &= ~NETIF_F_LRO;
4818         netdev->features  &= ~NETIF_F_GRO_HW;
4819         netdev->features  &= ~NETIF_F_RXFCS;
4820
4821 #define FT_CAP(f) MLX5_CAP_FLOWTABLE(mdev, flow_table_properties_nic_receive.f)
4822         if (FT_CAP(flow_modify_en) &&
4823             FT_CAP(modify_root) &&
4824             FT_CAP(identified_miss_table_mode) &&
4825             FT_CAP(flow_table_modify)) {
4826 #if IS_ENABLED(CONFIG_MLX5_CLS_ACT)
4827                 netdev->hw_features      |= NETIF_F_HW_TC;
4828 #endif
4829 #ifdef CONFIG_MLX5_EN_ARFS
4830                 netdev->hw_features      |= NETIF_F_NTUPLE;
4831 #endif
4832         }
4833
4834         netdev->features         |= NETIF_F_HIGHDMA;
4835         netdev->features         |= NETIF_F_HW_VLAN_STAG_FILTER;
4836
4837         netdev->priv_flags       |= IFF_UNICAST_FLT;
4838
4839         mlx5e_set_netdev_dev_addr(netdev);
4840         mlx5e_ipsec_build_netdev(priv);
4841         mlx5e_tls_build_netdev(priv);
4842 }
4843
4844 void mlx5e_create_q_counters(struct mlx5e_priv *priv)
4845 {
4846         u32 out[MLX5_ST_SZ_DW(alloc_q_counter_out)] = {};
4847         u32 in[MLX5_ST_SZ_DW(alloc_q_counter_in)] = {};
4848         struct mlx5_core_dev *mdev = priv->mdev;
4849         int err;
4850
4851         MLX5_SET(alloc_q_counter_in, in, opcode, MLX5_CMD_OP_ALLOC_Q_COUNTER);
4852         err = mlx5_cmd_exec_inout(mdev, alloc_q_counter, in, out);
4853         if (!err)
4854                 priv->q_counter =
4855                         MLX5_GET(alloc_q_counter_out, out, counter_set_id);
4856
4857         err = mlx5_cmd_exec_inout(mdev, alloc_q_counter, in, out);
4858         if (!err)
4859                 priv->drop_rq_q_counter =
4860                         MLX5_GET(alloc_q_counter_out, out, counter_set_id);
4861 }
4862
4863 void mlx5e_destroy_q_counters(struct mlx5e_priv *priv)
4864 {
4865         u32 in[MLX5_ST_SZ_DW(dealloc_q_counter_in)] = {};
4866
4867         MLX5_SET(dealloc_q_counter_in, in, opcode,
4868                  MLX5_CMD_OP_DEALLOC_Q_COUNTER);
4869         if (priv->q_counter) {
4870                 MLX5_SET(dealloc_q_counter_in, in, counter_set_id,
4871                          priv->q_counter);
4872                 mlx5_cmd_exec_in(priv->mdev, dealloc_q_counter, in);
4873         }
4874
4875         if (priv->drop_rq_q_counter) {
4876                 MLX5_SET(dealloc_q_counter_in, in, counter_set_id,
4877                          priv->drop_rq_q_counter);
4878                 mlx5_cmd_exec_in(priv->mdev, dealloc_q_counter, in);
4879         }
4880 }
4881
4882 static int mlx5e_nic_init(struct mlx5_core_dev *mdev,
4883                           struct net_device *netdev)
4884 {
4885         struct mlx5e_priv *priv = netdev_priv(netdev);
4886         int err;
4887
4888         mlx5e_build_nic_params(priv, &priv->xsk, netdev->mtu);
4889         mlx5e_vxlan_set_netdev_info(priv);
4890
4891         mlx5e_timestamp_init(priv);
4892
4893         err = mlx5e_fs_init(priv);
4894         if (err) {
4895                 mlx5_core_err(mdev, "FS initialization failed, %d\n", err);
4896                 return err;
4897         }
4898
4899         err = mlx5e_ipsec_init(priv);
4900         if (err)
4901                 mlx5_core_err(mdev, "IPSec initialization failed, %d\n", err);
4902
4903         err = mlx5e_tls_init(priv);
4904         if (err)
4905                 mlx5_core_err(mdev, "TLS initialization failed, %d\n", err);
4906
4907         mlx5e_health_create_reporters(priv);
4908         return 0;
4909 }
4910
4911 static void mlx5e_nic_cleanup(struct mlx5e_priv *priv)
4912 {
4913         mlx5e_health_destroy_reporters(priv);
4914         mlx5e_tls_cleanup(priv);
4915         mlx5e_ipsec_cleanup(priv);
4916         mlx5e_fs_cleanup(priv);
4917 }
4918
4919 static int mlx5e_init_nic_rx(struct mlx5e_priv *priv)
4920 {
4921         struct mlx5_core_dev *mdev = priv->mdev;
4922         enum mlx5e_rx_res_features features;
4923         int err;
4924
4925         priv->rx_res = mlx5e_rx_res_alloc();
4926         if (!priv->rx_res)
4927                 return -ENOMEM;
4928
4929         mlx5e_create_q_counters(priv);
4930
4931         err = mlx5e_open_drop_rq(priv, &priv->drop_rq);
4932         if (err) {
4933                 mlx5_core_err(mdev, "open drop rq failed, %d\n", err);
4934                 goto err_destroy_q_counters;
4935         }
4936
4937         features = MLX5E_RX_RES_FEATURE_XSK | MLX5E_RX_RES_FEATURE_PTP;
4938         if (priv->channels.params.tunneled_offload_en)
4939                 features |= MLX5E_RX_RES_FEATURE_INNER_FT;
4940         err = mlx5e_rx_res_init(priv->rx_res, priv->mdev, features,
4941                                 priv->max_nch, priv->drop_rq.rqn,
4942                                 &priv->channels.params.packet_merge,
4943                                 priv->channels.params.num_channels);
4944         if (err)
4945                 goto err_close_drop_rq;
4946
4947         err = mlx5e_create_flow_steering(priv);
4948         if (err) {
4949                 mlx5_core_warn(mdev, "create flow steering failed, %d\n", err);
4950                 goto err_destroy_rx_res;
4951         }
4952
4953         err = mlx5e_tc_nic_init(priv);
4954         if (err)
4955                 goto err_destroy_flow_steering;
4956
4957         err = mlx5e_accel_init_rx(priv);
4958         if (err)
4959                 goto err_tc_nic_cleanup;
4960
4961 #ifdef CONFIG_MLX5_EN_ARFS
4962         priv->netdev->rx_cpu_rmap =  mlx5_eq_table_get_rmap(priv->mdev);
4963 #endif
4964
4965         return 0;
4966
4967 err_tc_nic_cleanup:
4968         mlx5e_tc_nic_cleanup(priv);
4969 err_destroy_flow_steering:
4970         mlx5e_destroy_flow_steering(priv);
4971 err_destroy_rx_res:
4972         mlx5e_rx_res_destroy(priv->rx_res);
4973 err_close_drop_rq:
4974         mlx5e_close_drop_rq(&priv->drop_rq);
4975 err_destroy_q_counters:
4976         mlx5e_destroy_q_counters(priv);
4977         mlx5e_rx_res_free(priv->rx_res);
4978         priv->rx_res = NULL;
4979         return err;
4980 }
4981
4982 static void mlx5e_cleanup_nic_rx(struct mlx5e_priv *priv)
4983 {
4984         mlx5e_accel_cleanup_rx(priv);
4985         mlx5e_tc_nic_cleanup(priv);
4986         mlx5e_destroy_flow_steering(priv);
4987         mlx5e_rx_res_destroy(priv->rx_res);
4988         mlx5e_close_drop_rq(&priv->drop_rq);
4989         mlx5e_destroy_q_counters(priv);
4990         mlx5e_rx_res_free(priv->rx_res);
4991         priv->rx_res = NULL;
4992 }
4993
4994 static int mlx5e_init_nic_tx(struct mlx5e_priv *priv)
4995 {
4996         int err;
4997
4998         err = mlx5e_create_tises(priv);
4999         if (err) {
5000                 mlx5_core_warn(priv->mdev, "create tises failed, %d\n", err);
5001                 return err;
5002         }
5003
5004         mlx5e_dcbnl_initialize(priv);
5005         return 0;
5006 }
5007
5008 static void mlx5e_nic_enable(struct mlx5e_priv *priv)
5009 {
5010         struct net_device *netdev = priv->netdev;
5011         struct mlx5_core_dev *mdev = priv->mdev;
5012
5013         mlx5e_init_l2_addr(priv);
5014
5015         /* Marking the link as currently not needed by the Driver */
5016         if (!netif_running(netdev))
5017                 mlx5e_modify_admin_state(mdev, MLX5_PORT_DOWN);
5018
5019         mlx5e_set_netdev_mtu_boundaries(priv);
5020         mlx5e_set_dev_port_mtu(priv);
5021
5022         mlx5_lag_add_netdev(mdev, netdev);
5023
5024         mlx5e_enable_async_events(priv);
5025         mlx5e_enable_blocking_events(priv);
5026         if (mlx5e_monitor_counter_supported(priv))
5027                 mlx5e_monitor_counter_init(priv);
5028
5029         mlx5e_hv_vhca_stats_create(priv);
5030         if (netdev->reg_state != NETREG_REGISTERED)
5031                 return;
5032         mlx5e_dcbnl_init_app(priv);
5033
5034         mlx5e_nic_set_rx_mode(priv);
5035
5036         rtnl_lock();
5037         if (netif_running(netdev))
5038                 mlx5e_open(netdev);
5039         udp_tunnel_nic_reset_ntf(priv->netdev);
5040         netif_device_attach(netdev);
5041         rtnl_unlock();
5042 }
5043
5044 static void mlx5e_nic_disable(struct mlx5e_priv *priv)
5045 {
5046         struct mlx5_core_dev *mdev = priv->mdev;
5047
5048         if (priv->netdev->reg_state == NETREG_REGISTERED)
5049                 mlx5e_dcbnl_delete_app(priv);
5050
5051         rtnl_lock();
5052         if (netif_running(priv->netdev))
5053                 mlx5e_close(priv->netdev);
5054         netif_device_detach(priv->netdev);
5055         rtnl_unlock();
5056
5057         mlx5e_nic_set_rx_mode(priv);
5058
5059         mlx5e_hv_vhca_stats_destroy(priv);
5060         if (mlx5e_monitor_counter_supported(priv))
5061                 mlx5e_monitor_counter_cleanup(priv);
5062
5063         mlx5e_disable_blocking_events(priv);
5064         if (priv->en_trap) {
5065                 mlx5e_deactivate_trap(priv);
5066                 mlx5e_close_trap(priv->en_trap);
5067                 priv->en_trap = NULL;
5068         }
5069         mlx5e_disable_async_events(priv);
5070         mlx5_lag_remove_netdev(mdev, priv->netdev);
5071         mlx5_vxlan_reset_to_default(mdev->vxlan);
5072 }
5073
5074 int mlx5e_update_nic_rx(struct mlx5e_priv *priv)
5075 {
5076         return mlx5e_refresh_tirs(priv, false, false);
5077 }
5078
5079 static const struct mlx5e_profile mlx5e_nic_profile = {
5080         .init              = mlx5e_nic_init,
5081         .cleanup           = mlx5e_nic_cleanup,
5082         .init_rx           = mlx5e_init_nic_rx,
5083         .cleanup_rx        = mlx5e_cleanup_nic_rx,
5084         .init_tx           = mlx5e_init_nic_tx,
5085         .cleanup_tx        = mlx5e_cleanup_nic_tx,
5086         .enable            = mlx5e_nic_enable,
5087         .disable           = mlx5e_nic_disable,
5088         .update_rx         = mlx5e_update_nic_rx,
5089         .update_stats      = mlx5e_stats_update_ndo_stats,
5090         .update_carrier    = mlx5e_update_carrier,
5091         .rx_handlers       = &mlx5e_rx_handlers_nic,
5092         .max_tc            = MLX5E_MAX_NUM_TC,
5093         .rq_groups         = MLX5E_NUM_RQ_GROUPS(XSK),
5094         .stats_grps        = mlx5e_nic_stats_grps,
5095         .stats_grps_num    = mlx5e_nic_stats_grps_num,
5096         .rx_ptp_support    = true,
5097 };
5098
5099 static unsigned int
5100 mlx5e_calc_max_nch(struct mlx5_core_dev *mdev, struct net_device *netdev,
5101                    const struct mlx5e_profile *profile)
5102
5103 {
5104         unsigned int max_nch, tmp;
5105
5106         /* core resources */
5107         max_nch = mlx5e_get_max_num_channels(mdev);
5108
5109         /* netdev rx queues */
5110         tmp = netdev->num_rx_queues / max_t(u8, profile->rq_groups, 1);
5111         max_nch = min_t(unsigned int, max_nch, tmp);
5112
5113         /* netdev tx queues */
5114         tmp = netdev->num_tx_queues;
5115         if (mlx5_qos_is_supported(mdev))
5116                 tmp -= mlx5e_qos_max_leaf_nodes(mdev);
5117         if (MLX5_CAP_GEN(mdev, ts_cqe_to_dest_cqn))
5118                 tmp -= profile->max_tc;
5119         tmp = tmp / profile->max_tc;
5120         max_nch = min_t(unsigned int, max_nch, tmp);
5121
5122         return max_nch;
5123 }
5124
5125 /* mlx5e generic netdev management API (move to en_common.c) */
5126 int mlx5e_priv_init(struct mlx5e_priv *priv,
5127                     const struct mlx5e_profile *profile,
5128                     struct net_device *netdev,
5129                     struct mlx5_core_dev *mdev)
5130 {
5131         /* priv init */
5132         priv->mdev        = mdev;
5133         priv->netdev      = netdev;
5134         priv->msglevel    = MLX5E_MSG_LEVEL;
5135         priv->max_nch     = mlx5e_calc_max_nch(mdev, netdev, profile);
5136         priv->stats_nch   = priv->max_nch;
5137         priv->max_opened_tc = 1;
5138
5139         if (!alloc_cpumask_var(&priv->scratchpad.cpumask, GFP_KERNEL))
5140                 return -ENOMEM;
5141
5142         mutex_init(&priv->state_lock);
5143         hash_init(priv->htb.qos_tc2node);
5144         INIT_WORK(&priv->update_carrier_work, mlx5e_update_carrier_work);
5145         INIT_WORK(&priv->set_rx_mode_work, mlx5e_set_rx_mode_work);
5146         INIT_WORK(&priv->tx_timeout_work, mlx5e_tx_timeout_work);
5147         INIT_WORK(&priv->update_stats_work, mlx5e_update_stats_work);
5148
5149         priv->wq = create_singlethread_workqueue("mlx5e");
5150         if (!priv->wq)
5151                 goto err_free_cpumask;
5152
5153         return 0;
5154
5155 err_free_cpumask:
5156         free_cpumask_var(priv->scratchpad.cpumask);
5157
5158         return -ENOMEM;
5159 }
5160
5161 void mlx5e_priv_cleanup(struct mlx5e_priv *priv)
5162 {
5163         int i;
5164
5165         /* bail if change profile failed and also rollback failed */
5166         if (!priv->mdev)
5167                 return;
5168
5169         destroy_workqueue(priv->wq);
5170         free_cpumask_var(priv->scratchpad.cpumask);
5171
5172         for (i = 0; i < priv->htb.max_qos_sqs; i++)
5173                 kfree(priv->htb.qos_sq_stats[i]);
5174         kvfree(priv->htb.qos_sq_stats);
5175
5176         if (priv->mqprio_rl) {
5177                 mlx5e_mqprio_rl_cleanup(priv->mqprio_rl);
5178                 mlx5e_mqprio_rl_free(priv->mqprio_rl);
5179         }
5180
5181         memset(priv, 0, sizeof(*priv));
5182 }
5183
5184 struct net_device *
5185 mlx5e_create_netdev(struct mlx5_core_dev *mdev, const struct mlx5e_profile *profile,
5186                     unsigned int txqs, unsigned int rxqs)
5187 {
5188         struct net_device *netdev;
5189         int err;
5190
5191         netdev = alloc_etherdev_mqs(sizeof(struct mlx5e_priv), txqs, rxqs);
5192         if (!netdev) {
5193                 mlx5_core_err(mdev, "alloc_etherdev_mqs() failed\n");
5194                 return NULL;
5195         }
5196
5197         err = mlx5e_priv_init(netdev_priv(netdev), profile, netdev, mdev);
5198         if (err) {
5199                 mlx5_core_err(mdev, "mlx5e_priv_init failed, err=%d\n", err);
5200                 goto err_free_netdev;
5201         }
5202
5203         netif_carrier_off(netdev);
5204         dev_net_set(netdev, mlx5_core_net(mdev));
5205
5206         return netdev;
5207
5208 err_free_netdev:
5209         free_netdev(netdev);
5210
5211         return NULL;
5212 }
5213
5214 static void mlx5e_update_features(struct net_device *netdev)
5215 {
5216         if (netdev->reg_state != NETREG_REGISTERED)
5217                 return; /* features will be updated on netdev registration */
5218
5219         rtnl_lock();
5220         netdev_update_features(netdev);
5221         rtnl_unlock();
5222 }
5223
5224 static void mlx5e_reset_channels(struct net_device *netdev)
5225 {
5226         netdev_reset_tc(netdev);
5227 }
5228
5229 int mlx5e_attach_netdev(struct mlx5e_priv *priv)
5230 {
5231         const bool take_rtnl = priv->netdev->reg_state == NETREG_REGISTERED;
5232         const struct mlx5e_profile *profile = priv->profile;
5233         int max_nch;
5234         int err;
5235
5236         clear_bit(MLX5E_STATE_DESTROYING, &priv->state);
5237
5238         /* max number of channels may have changed */
5239         max_nch = mlx5e_calc_max_nch(priv->mdev, priv->netdev, profile);
5240         if (priv->channels.params.num_channels > max_nch) {
5241                 mlx5_core_warn(priv->mdev, "MLX5E: Reducing number of channels to %d\n", max_nch);
5242                 /* Reducing the number of channels - RXFH has to be reset, and
5243                  * mlx5e_num_channels_changed below will build the RQT.
5244                  */
5245                 priv->netdev->priv_flags &= ~IFF_RXFH_CONFIGURED;
5246                 priv->channels.params.num_channels = max_nch;
5247                 if (priv->channels.params.mqprio.mode == TC_MQPRIO_MODE_CHANNEL) {
5248                         mlx5_core_warn(priv->mdev, "MLX5E: Disabling MQPRIO channel mode\n");
5249                         mlx5e_params_mqprio_reset(&priv->channels.params);
5250                 }
5251         }
5252         if (max_nch != priv->max_nch) {
5253                 mlx5_core_warn(priv->mdev,
5254                                "MLX5E: Updating max number of channels from %u to %u\n",
5255                                priv->max_nch, max_nch);
5256                 priv->max_nch = max_nch;
5257         }
5258
5259         /* 1. Set the real number of queues in the kernel the first time.
5260          * 2. Set our default XPS cpumask.
5261          * 3. Build the RQT.
5262          *
5263          * rtnl_lock is required by netif_set_real_num_*_queues in case the
5264          * netdev has been registered by this point (if this function was called
5265          * in the reload or resume flow).
5266          */
5267         if (take_rtnl)
5268                 rtnl_lock();
5269         err = mlx5e_num_channels_changed(priv);
5270         if (take_rtnl)
5271                 rtnl_unlock();
5272         if (err)
5273                 goto out;
5274
5275         err = profile->init_tx(priv);
5276         if (err)
5277                 goto out;
5278
5279         err = profile->init_rx(priv);
5280         if (err)
5281                 goto err_cleanup_tx;
5282
5283         if (profile->enable)
5284                 profile->enable(priv);
5285
5286         mlx5e_update_features(priv->netdev);
5287
5288         return 0;
5289
5290 err_cleanup_tx:
5291         profile->cleanup_tx(priv);
5292
5293 out:
5294         mlx5e_reset_channels(priv->netdev);
5295         set_bit(MLX5E_STATE_DESTROYING, &priv->state);
5296         cancel_work_sync(&priv->update_stats_work);
5297         return err;
5298 }
5299
5300 void mlx5e_detach_netdev(struct mlx5e_priv *priv)
5301 {
5302         const struct mlx5e_profile *profile = priv->profile;
5303
5304         set_bit(MLX5E_STATE_DESTROYING, &priv->state);
5305
5306         if (profile->disable)
5307                 profile->disable(priv);
5308         flush_workqueue(priv->wq);
5309
5310         profile->cleanup_rx(priv);
5311         profile->cleanup_tx(priv);
5312         mlx5e_reset_channels(priv->netdev);
5313         cancel_work_sync(&priv->update_stats_work);
5314 }
5315
5316 static int
5317 mlx5e_netdev_attach_profile(struct net_device *netdev, struct mlx5_core_dev *mdev,
5318                             const struct mlx5e_profile *new_profile, void *new_ppriv)
5319 {
5320         struct mlx5e_priv *priv = netdev_priv(netdev);
5321         int err;
5322
5323         err = mlx5e_priv_init(priv, new_profile, netdev, mdev);
5324         if (err) {
5325                 mlx5_core_err(mdev, "mlx5e_priv_init failed, err=%d\n", err);
5326                 return err;
5327         }
5328         netif_carrier_off(netdev);
5329         priv->profile = new_profile;
5330         priv->ppriv = new_ppriv;
5331         err = new_profile->init(priv->mdev, priv->netdev);
5332         if (err)
5333                 goto priv_cleanup;
5334         err = mlx5e_attach_netdev(priv);
5335         if (err)
5336                 goto profile_cleanup;
5337         return err;
5338
5339 profile_cleanup:
5340         new_profile->cleanup(priv);
5341 priv_cleanup:
5342         mlx5e_priv_cleanup(priv);
5343         return err;
5344 }
5345
5346 int mlx5e_netdev_change_profile(struct mlx5e_priv *priv,
5347                                 const struct mlx5e_profile *new_profile, void *new_ppriv)
5348 {
5349         const struct mlx5e_profile *orig_profile = priv->profile;
5350         struct net_device *netdev = priv->netdev;
5351         struct mlx5_core_dev *mdev = priv->mdev;
5352         void *orig_ppriv = priv->ppriv;
5353         int err, rollback_err;
5354
5355         /* cleanup old profile */
5356         mlx5e_detach_netdev(priv);
5357         priv->profile->cleanup(priv);
5358         mlx5e_priv_cleanup(priv);
5359
5360         err = mlx5e_netdev_attach_profile(netdev, mdev, new_profile, new_ppriv);
5361         if (err) { /* roll back to original profile */
5362                 netdev_warn(netdev, "%s: new profile init failed, %d\n", __func__, err);
5363                 goto rollback;
5364         }
5365
5366         return 0;
5367
5368 rollback:
5369         rollback_err = mlx5e_netdev_attach_profile(netdev, mdev, orig_profile, orig_ppriv);
5370         if (rollback_err)
5371                 netdev_err(netdev, "%s: failed to rollback to orig profile, %d\n",
5372                            __func__, rollback_err);
5373         return err;
5374 }
5375
5376 void mlx5e_netdev_attach_nic_profile(struct mlx5e_priv *priv)
5377 {
5378         mlx5e_netdev_change_profile(priv, &mlx5e_nic_profile, NULL);
5379 }
5380
5381 void mlx5e_destroy_netdev(struct mlx5e_priv *priv)
5382 {
5383         struct net_device *netdev = priv->netdev;
5384
5385         mlx5e_priv_cleanup(priv);
5386         free_netdev(netdev);
5387 }
5388
5389 static int mlx5e_resume(struct auxiliary_device *adev)
5390 {
5391         struct mlx5_adev *edev = container_of(adev, struct mlx5_adev, adev);
5392         struct mlx5e_priv *priv = dev_get_drvdata(&adev->dev);
5393         struct net_device *netdev = priv->netdev;
5394         struct mlx5_core_dev *mdev = edev->mdev;
5395         int err;
5396
5397         if (netif_device_present(netdev))
5398                 return 0;
5399
5400         err = mlx5e_create_mdev_resources(mdev);
5401         if (err)
5402                 return err;
5403
5404         err = mlx5e_attach_netdev(priv);
5405         if (err) {
5406                 mlx5e_destroy_mdev_resources(mdev);
5407                 return err;
5408         }
5409
5410         return 0;
5411 }
5412
5413 static int mlx5e_suspend(struct auxiliary_device *adev, pm_message_t state)
5414 {
5415         struct mlx5e_priv *priv = dev_get_drvdata(&adev->dev);
5416         struct net_device *netdev = priv->netdev;
5417         struct mlx5_core_dev *mdev = priv->mdev;
5418
5419         if (!netif_device_present(netdev))
5420                 return -ENODEV;
5421
5422         mlx5e_detach_netdev(priv);
5423         mlx5e_destroy_mdev_resources(mdev);
5424         return 0;
5425 }
5426
5427 static int mlx5e_probe(struct auxiliary_device *adev,
5428                        const struct auxiliary_device_id *id)
5429 {
5430         struct mlx5_adev *edev = container_of(adev, struct mlx5_adev, adev);
5431         const struct mlx5e_profile *profile = &mlx5e_nic_profile;
5432         struct mlx5_core_dev *mdev = edev->mdev;
5433         struct net_device *netdev;
5434         pm_message_t state = {};
5435         unsigned int txqs, rxqs, ptp_txqs = 0;
5436         struct mlx5e_priv *priv;
5437         int qos_sqs = 0;
5438         int err;
5439         int nch;
5440
5441         if (MLX5_CAP_GEN(mdev, ts_cqe_to_dest_cqn))
5442                 ptp_txqs = profile->max_tc;
5443
5444         if (mlx5_qos_is_supported(mdev))
5445                 qos_sqs = mlx5e_qos_max_leaf_nodes(mdev);
5446
5447         nch = mlx5e_get_max_num_channels(mdev);
5448         txqs = nch * profile->max_tc + ptp_txqs + qos_sqs;
5449         rxqs = nch * profile->rq_groups;
5450         netdev = mlx5e_create_netdev(mdev, profile, txqs, rxqs);
5451         if (!netdev) {
5452                 mlx5_core_err(mdev, "mlx5e_create_netdev failed\n");
5453                 return -ENOMEM;
5454         }
5455
5456         mlx5e_build_nic_netdev(netdev);
5457
5458         priv = netdev_priv(netdev);
5459         dev_set_drvdata(&adev->dev, priv);
5460
5461         priv->profile = profile;
5462         priv->ppriv = NULL;
5463
5464         err = mlx5e_devlink_port_register(priv);
5465         if (err) {
5466                 mlx5_core_err(mdev, "mlx5e_devlink_port_register failed, %d\n", err);
5467                 goto err_destroy_netdev;
5468         }
5469
5470         err = profile->init(mdev, netdev);
5471         if (err) {
5472                 mlx5_core_err(mdev, "mlx5e_nic_profile init failed, %d\n", err);
5473                 goto err_devlink_cleanup;
5474         }
5475
5476         err = mlx5e_resume(adev);
5477         if (err) {
5478                 mlx5_core_err(mdev, "mlx5e_resume failed, %d\n", err);
5479                 goto err_profile_cleanup;
5480         }
5481
5482         err = register_netdev(netdev);
5483         if (err) {
5484                 mlx5_core_err(mdev, "register_netdev failed, %d\n", err);
5485                 goto err_resume;
5486         }
5487
5488         mlx5e_devlink_port_type_eth_set(priv);
5489
5490         mlx5e_dcbnl_init_app(priv);
5491         mlx5_uplink_netdev_set(mdev, netdev);
5492         return 0;
5493
5494 err_resume:
5495         mlx5e_suspend(adev, state);
5496 err_profile_cleanup:
5497         profile->cleanup(priv);
5498 err_devlink_cleanup:
5499         mlx5e_devlink_port_unregister(priv);
5500 err_destroy_netdev:
5501         mlx5e_destroy_netdev(priv);
5502         return err;
5503 }
5504
5505 static void mlx5e_remove(struct auxiliary_device *adev)
5506 {
5507         struct mlx5e_priv *priv = dev_get_drvdata(&adev->dev);
5508         pm_message_t state = {};
5509
5510         mlx5e_dcbnl_delete_app(priv);
5511         unregister_netdev(priv->netdev);
5512         mlx5e_suspend(adev, state);
5513         priv->profile->cleanup(priv);
5514         mlx5e_devlink_port_unregister(priv);
5515         mlx5e_destroy_netdev(priv);
5516 }
5517
5518 static const struct auxiliary_device_id mlx5e_id_table[] = {
5519         { .name = MLX5_ADEV_NAME ".eth", },
5520         {},
5521 };
5522
5523 MODULE_DEVICE_TABLE(auxiliary, mlx5e_id_table);
5524
5525 static struct auxiliary_driver mlx5e_driver = {
5526         .name = "eth",
5527         .probe = mlx5e_probe,
5528         .remove = mlx5e_remove,
5529         .suspend = mlx5e_suspend,
5530         .resume = mlx5e_resume,
5531         .id_table = mlx5e_id_table,
5532 };
5533
5534 int mlx5e_init(void)
5535 {
5536         int ret;
5537
5538         mlx5e_ipsec_build_inverse_table();
5539         mlx5e_build_ptys2ethtool_map();
5540         ret = auxiliary_driver_register(&mlx5e_driver);
5541         if (ret)
5542                 return ret;
5543
5544         ret = mlx5e_rep_init();
5545         if (ret)
5546                 auxiliary_driver_unregister(&mlx5e_driver);
5547         return ret;
5548 }
5549
5550 void mlx5e_cleanup(void)
5551 {
5552         mlx5e_rep_cleanup();
5553         auxiliary_driver_unregister(&mlx5e_driver);
5554 }