drivers/net/ethernet/mellanox/mlx5/core/en_main.c

   1 /*
   2  * Copyright (c) 2015-2016, Mellanox Technologies. All rights reserved.
   3  *
   4  * This software is available to you under a choice of one of two
   5  * licenses.  You may choose to be licensed under the terms of the GNU
   6  * General Public License (GPL) Version 2, available from the file
   7  * COPYING in the main directory of this source tree, or the
   8  * OpenIB.org BSD license below:
   9  *
  10  *     Redistribution and use in source and binary forms, with or
  11  *     without modification, are permitted provided that the following
  12  *     conditions are met:
  13  *
  14  *      - Redistributions of source code must retain the above
  15  *        copyright notice, this list of conditions and the following
  16  *        disclaimer.
  17  *
  18  *      - Redistributions in binary form must reproduce the above
  19  *        copyright notice, this list of conditions and the following
  20  *        disclaimer in the documentation and/or other materials
  21  *        provided with the distribution.
  22  *
  23  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  24  * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  25  * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
  26  * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
  27  * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
  28  * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
  29  * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
  30  * SOFTWARE.
  31  */
  32
  33 #include <net/tc_act/tc_gact.h>
  34 #include <net/pkt_cls.h>
  35 #include <linux/mlx5/fs.h>
  36 #include <net/vxlan.h>
  37 #include <linux/bpf.h>
  38 #include "en.h"
  39 #include "en_tc.h"
  40 #include "eswitch.h"
  41 #include "vxlan.h"
  42
  43 struct mlx5e_rq_param {
  44         u32                     rqc[MLX5_ST_SZ_DW(rqc)];
  45         struct mlx5_wq_param    wq;
  46         bool                    am_enabled;
  47 };
  48
  49 struct mlx5e_sq_param {
  50         u32                        sqc[MLX5_ST_SZ_DW(sqc)];
  51         struct mlx5_wq_param       wq;
  52         u16                        max_inline;
  53         u8                         min_inline_mode;
  54         enum mlx5e_sq_type         type;
  55 };
  56
  57 struct mlx5e_cq_param {
  58         u32                        cqc[MLX5_ST_SZ_DW(cqc)];
  59         struct mlx5_wq_param       wq;
  60         u16                        eq_ix;
  61         u8                         cq_period_mode;
  62 };
  63
  64 struct mlx5e_channel_param {
  65         struct mlx5e_rq_param      rq;
  66         struct mlx5e_sq_param      sq;
  67         struct mlx5e_sq_param      xdp_sq;
  68         struct mlx5e_sq_param      icosq;
  69         struct mlx5e_cq_param      rx_cq;
  70         struct mlx5e_cq_param      tx_cq;
  71         struct mlx5e_cq_param      icosq_cq;
  72 };
  73
  74 static bool mlx5e_check_fragmented_striding_rq_cap(struct mlx5_core_dev *mdev)
  75 {
  76         return MLX5_CAP_GEN(mdev, striding_rq) &&
  77                 MLX5_CAP_GEN(mdev, umr_ptr_rlky) &&
  78                 MLX5_CAP_ETH(mdev, reg_umr_sq);
  79 }
  80
  81 static void mlx5e_set_rq_type_params(struct mlx5e_priv *priv, u8 rq_type)
  82 {
  83         priv->params.rq_wq_type = rq_type;
  84         switch (priv->params.rq_wq_type) {
  85         case MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ:
  86                 priv->params.log_rq_size = MLX5E_PARAMS_DEFAULT_LOG_RQ_SIZE_MPW;
  87                 priv->params.mpwqe_log_stride_sz = priv->params.rx_cqe_compress ?
  88                         MLX5_MPWRQ_LOG_STRIDE_SIZE_CQE_COMPRESS :
  89                         MLX5_MPWRQ_LOG_STRIDE_SIZE;
  90                 priv->params.mpwqe_log_num_strides = MLX5_MPWRQ_LOG_WQE_SZ -
  91                         priv->params.mpwqe_log_stride_sz;
  92                 break;
  93         default: /* MLX5_WQ_TYPE_LINKED_LIST */
  94                 priv->params.log_rq_size = MLX5E_PARAMS_DEFAULT_LOG_RQ_SIZE;
  95         }
  96         priv->params.min_rx_wqes = mlx5_min_rx_wqes(priv->params.rq_wq_type,
  97                                                BIT(priv->params.log_rq_size));
  98
  99         mlx5_core_info(priv->mdev,
 100                        "MLX5E: StrdRq(%d) RqSz(%ld) StrdSz(%ld) RxCqeCmprss(%d)\n",
 101                        priv->params.rq_wq_type == MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ,
 102                        BIT(priv->params.log_rq_size),
 103                        BIT(priv->params.mpwqe_log_stride_sz),
 104                        priv->params.rx_cqe_compress_admin);
 105 }
 106
 107 static void mlx5e_set_rq_priv_params(struct mlx5e_priv *priv)
 108 {
 109         u8 rq_type = mlx5e_check_fragmented_striding_rq_cap(priv->mdev) &&
 110                     !priv->xdp_prog ?
 111                     MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ :
 112                     MLX5_WQ_TYPE_LINKED_LIST;
 113         mlx5e_set_rq_type_params(priv, rq_type);
 114 }
 115
 116 static void mlx5e_update_carrier(struct mlx5e_priv *priv)
 117 {
 118         struct mlx5_core_dev *mdev = priv->mdev;
 119         u8 port_state;
 120
 121         port_state = mlx5_query_vport_state(mdev,
 122                 MLX5_QUERY_VPORT_STATE_IN_OP_MOD_VNIC_VPORT, 0);
 123
 124         if (port_state == VPORT_STATE_UP) {
 125                 netdev_info(priv->netdev, "Link up\n");
 126                 netif_carrier_on(priv->netdev);
 127         } else {
 128                 netdev_info(priv->netdev, "Link down\n");
 129                 netif_carrier_off(priv->netdev);
 130         }
 131 }
 132
 133 static void mlx5e_update_carrier_work(struct work_struct *work)
 134 {
 135         struct mlx5e_priv *priv = container_of(work, struct mlx5e_priv,
 136                                                update_carrier_work);
 137
 138         mutex_lock(&priv->state_lock);
 139         if (test_bit(MLX5E_STATE_OPENED, &priv->state))
 140                 mlx5e_update_carrier(priv);
 141         mutex_unlock(&priv->state_lock);
 142 }
 143
 144 static void mlx5e_tx_timeout_work(struct work_struct *work)
 145 {
 146         struct mlx5e_priv *priv = container_of(work, struct mlx5e_priv,
 147                                                tx_timeout_work);
 148         int err;
 149
 150         rtnl_lock();
 151         mutex_lock(&priv->state_lock);
 152         if (!test_bit(MLX5E_STATE_OPENED, &priv->state))
 153                 goto unlock;
 154         mlx5e_close_locked(priv->netdev);
 155         err = mlx5e_open_locked(priv->netdev);
 156         if (err)
 157                 netdev_err(priv->netdev, "mlx5e_open_locked failed recovering from a tx_timeout, err(%d).\n",
 158                            err);
 159 unlock:
 160         mutex_unlock(&priv->state_lock);
 161         rtnl_unlock();
 162 }
 163
 164 static void mlx5e_update_sw_counters(struct mlx5e_priv *priv)
 165 {
 166         struct mlx5e_sw_stats *s = &priv->stats.sw;
 167         struct mlx5e_rq_stats *rq_stats;
 168         struct mlx5e_sq_stats *sq_stats;
 169         u64 tx_offload_none = 0;
 170         int i, j;
 171
 172         memset(s, 0, sizeof(*s));
 173         for (i = 0; i < priv->params.num_channels; i++) {
 174                 rq_stats = &priv->channel[i]->rq.stats;
 175
 176                 s->rx_packets   += rq_stats->packets;
 177                 s->rx_bytes     += rq_stats->bytes;
 178                 s->rx_lro_packets += rq_stats->lro_packets;
 179                 s->rx_lro_bytes += rq_stats->lro_bytes;
 180                 s->rx_csum_none += rq_stats->csum_none;
 181                 s->rx_csum_complete += rq_stats->csum_complete;
 182                 s->rx_csum_unnecessary_inner += rq_stats->csum_unnecessary_inner;
 183                 s->rx_xdp_drop += rq_stats->xdp_drop;
 184                 s->rx_xdp_tx += rq_stats->xdp_tx;
 185                 s->rx_xdp_tx_full += rq_stats->xdp_tx_full;
 186                 s->rx_wqe_err   += rq_stats->wqe_err;
 187                 s->rx_mpwqe_filler += rq_stats->mpwqe_filler;
 188                 s->rx_buff_alloc_err += rq_stats->buff_alloc_err;
 189                 s->rx_cqe_compress_blks += rq_stats->cqe_compress_blks;
 190                 s->rx_cqe_compress_pkts += rq_stats->cqe_compress_pkts;
 191                 s->rx_cache_reuse += rq_stats->cache_reuse;
 192                 s->rx_cache_full  += rq_stats->cache_full;
 193                 s->rx_cache_empty += rq_stats->cache_empty;
 194                 s->rx_cache_busy  += rq_stats->cache_busy;
 195
 196                 for (j = 0; j < priv->params.num_tc; j++) {
 197                         sq_stats = &priv->channel[i]->sq[j].stats;
 198
 199                         s->tx_packets           += sq_stats->packets;
 200                         s->tx_bytes             += sq_stats->bytes;
 201                         s->tx_tso_packets       += sq_stats->tso_packets;
 202                         s->tx_tso_bytes         += sq_stats->tso_bytes;
 203                         s->tx_tso_inner_packets += sq_stats->tso_inner_packets;
 204                         s->tx_tso_inner_bytes   += sq_stats->tso_inner_bytes;
 205                         s->tx_queue_stopped     += sq_stats->stopped;
 206                         s->tx_queue_wake        += sq_stats->wake;
 207                         s->tx_queue_dropped     += sq_stats->dropped;
 208                         s->tx_xmit_more         += sq_stats->xmit_more;
 209                         s->tx_csum_partial_inner += sq_stats->csum_partial_inner;
 210                         tx_offload_none         += sq_stats->csum_none;
 211                 }
 212         }
 213
 214         /* Update calculated offload counters */
 215         s->tx_csum_partial = s->tx_packets - tx_offload_none - s->tx_csum_partial_inner;
 216         s->rx_csum_unnecessary = s->rx_packets - s->rx_csum_none - s->rx_csum_complete;
 217
 218         s->link_down_events_phy = MLX5_GET(ppcnt_reg,
 219                                 priv->stats.pport.phy_counters,
 220                                 counter_set.phys_layer_cntrs.link_down_events);
 221 }
 222
 223 static void mlx5e_update_vport_counters(struct mlx5e_priv *priv)
 224 {
 225         int outlen = MLX5_ST_SZ_BYTES(query_vport_counter_out);
 226         u32 *out = (u32 *)priv->stats.vport.query_vport_out;
 227         u32 in[MLX5_ST_SZ_DW(query_vport_counter_in)] = {0};
 228         struct mlx5_core_dev *mdev = priv->mdev;
 229
 230         MLX5_SET(query_vport_counter_in, in, opcode,
 231                  MLX5_CMD_OP_QUERY_VPORT_COUNTER);
 232         MLX5_SET(query_vport_counter_in, in, op_mod, 0);
 233         MLX5_SET(query_vport_counter_in, in, other_vport, 0);
 234
 235         memset(out, 0, outlen);
 236         mlx5_cmd_exec(mdev, in, sizeof(in), out, outlen);
 237 }
 238
 239 static void mlx5e_update_pport_counters(struct mlx5e_priv *priv)
 240 {
 241         struct mlx5e_pport_stats *pstats = &priv->stats.pport;
 242         struct mlx5_core_dev *mdev = priv->mdev;
 243         int sz = MLX5_ST_SZ_BYTES(ppcnt_reg);
 244         int prio;
 245         void *out;
 246         u32 *in;
 247
 248         in = mlx5_vzalloc(sz);
 249         if (!in)
 250                 goto free_out;
 251
 252         MLX5_SET(ppcnt_reg, in, local_port, 1);
 253
 254         out = pstats->IEEE_802_3_counters;
 255         MLX5_SET(ppcnt_reg, in, grp, MLX5_IEEE_802_3_COUNTERS_GROUP);
 256         mlx5_core_access_reg(mdev, in, sz, out, sz, MLX5_REG_PPCNT, 0, 0);
 257
 258         out = pstats->RFC_2863_counters;
 259         MLX5_SET(ppcnt_reg, in, grp, MLX5_RFC_2863_COUNTERS_GROUP);
 260         mlx5_core_access_reg(mdev, in, sz, out, sz, MLX5_REG_PPCNT, 0, 0);
 261
 262         out = pstats->RFC_2819_counters;
 263         MLX5_SET(ppcnt_reg, in, grp, MLX5_RFC_2819_COUNTERS_GROUP);
 264         mlx5_core_access_reg(mdev, in, sz, out, sz, MLX5_REG_PPCNT, 0, 0);
 265
 266         out = pstats->phy_counters;
 267         MLX5_SET(ppcnt_reg, in, grp, MLX5_PHYSICAL_LAYER_COUNTERS_GROUP);
 268         mlx5_core_access_reg(mdev, in, sz, out, sz, MLX5_REG_PPCNT, 0, 0);
 269
 270         MLX5_SET(ppcnt_reg, in, grp, MLX5_PER_PRIORITY_COUNTERS_GROUP);
 271         for (prio = 0; prio < NUM_PPORT_PRIO; prio++) {
 272                 out = pstats->per_prio_counters[prio];
 273                 MLX5_SET(ppcnt_reg, in, prio_tc, prio);
 274                 mlx5_core_access_reg(mdev, in, sz, out, sz,
 275                                      MLX5_REG_PPCNT, 0, 0);
 276         }
 277
 278 free_out:
 279         kvfree(in);
 280 }
 281
 282 static void mlx5e_update_q_counter(struct mlx5e_priv *priv)
 283 {
 284         struct mlx5e_qcounter_stats *qcnt = &priv->stats.qcnt;
 285
 286         if (!priv->q_counter)
 287                 return;
 288
 289         mlx5_core_query_out_of_buffer(priv->mdev, priv->q_counter,
 290                                       &qcnt->rx_out_of_buffer);
 291 }
 292
 293 void mlx5e_update_stats(struct mlx5e_priv *priv)
 294 {
 295         mlx5e_update_q_counter(priv);
 296         mlx5e_update_vport_counters(priv);
 297         mlx5e_update_pport_counters(priv);
 298         mlx5e_update_sw_counters(priv);
 299 }
 300
 301 void mlx5e_update_stats_work(struct work_struct *work)
 302 {
 303         struct delayed_work *dwork = to_delayed_work(work);
 304         struct mlx5e_priv *priv = container_of(dwork, struct mlx5e_priv,
 305                                                update_stats_work);
 306         mutex_lock(&priv->state_lock);
 307         if (test_bit(MLX5E_STATE_OPENED, &priv->state)) {
 308                 priv->profile->update_stats(priv);
 309                 queue_delayed_work(priv->wq, dwork,
 310                                    msecs_to_jiffies(MLX5E_UPDATE_STATS_INTERVAL));
 311         }
 312         mutex_unlock(&priv->state_lock);
 313 }
 314
 315 static void mlx5e_async_event(struct mlx5_core_dev *mdev, void *vpriv,
 316                               enum mlx5_dev_event event, unsigned long param)
 317 {
 318         struct mlx5e_priv *priv = vpriv;
 319
 320         if (!test_bit(MLX5E_STATE_ASYNC_EVENTS_ENABLED, &priv->state))
 321                 return;
 322
 323         switch (event) {
 324         case MLX5_DEV_EVENT_PORT_UP:
 325         case MLX5_DEV_EVENT_PORT_DOWN:
 326                 queue_work(priv->wq, &priv->update_carrier_work);
 327                 break;
 328
 329         default:
 330                 break;
 331         }
 332 }
 333
 334 static void mlx5e_enable_async_events(struct mlx5e_priv *priv)
 335 {
 336         set_bit(MLX5E_STATE_ASYNC_EVENTS_ENABLED, &priv->state);
 337 }
 338
 339 static void mlx5e_disable_async_events(struct mlx5e_priv *priv)
 340 {
 341         clear_bit(MLX5E_STATE_ASYNC_EVENTS_ENABLED, &priv->state);
 342         synchronize_irq(mlx5_get_msix_vec(priv->mdev, MLX5_EQ_VEC_ASYNC));
 343 }
 344
 345 #define MLX5E_HW2SW_MTU(hwmtu) (hwmtu - (ETH_HLEN + VLAN_HLEN + ETH_FCS_LEN))
 346 #define MLX5E_SW2HW_MTU(swmtu) (swmtu + (ETH_HLEN + VLAN_HLEN + ETH_FCS_LEN))
 347
 348 static inline int mlx5e_get_wqe_mtt_sz(void)
 349 {
 350         /* UMR copies MTTs in units of MLX5_UMR_MTT_ALIGNMENT bytes.
 351          * To avoid copying garbage after the mtt array, we allocate
 352          * a little more.
 353          */
 354         return ALIGN(MLX5_MPWRQ_PAGES_PER_WQE * sizeof(__be64),
 355                      MLX5_UMR_MTT_ALIGNMENT);
 356 }
 357
 358 static inline void mlx5e_build_umr_wqe(struct mlx5e_rq *rq, struct mlx5e_sq *sq,
 359                                        struct mlx5e_umr_wqe *wqe, u16 ix)
 360 {
 361         struct mlx5_wqe_ctrl_seg      *cseg = &wqe->ctrl;
 362         struct mlx5_wqe_umr_ctrl_seg *ucseg = &wqe->uctrl;
 363         struct mlx5_wqe_data_seg      *dseg = &wqe->data;
 364         struct mlx5e_mpw_info *wi = &rq->mpwqe.info[ix];
 365         u8 ds_cnt = DIV_ROUND_UP(sizeof(*wqe), MLX5_SEND_WQE_DS);
 366         u32 umr_wqe_mtt_offset = mlx5e_get_wqe_mtt_offset(rq, ix);
 367
 368         cseg->qpn_ds    = cpu_to_be32((sq->sqn << MLX5_WQE_CTRL_QPN_SHIFT) |
 369                                       ds_cnt);
 370         cseg->fm_ce_se  = MLX5_WQE_CTRL_CQ_UPDATE;
 371         cseg->imm       = rq->mkey_be;
 372
 373         ucseg->flags = MLX5_UMR_TRANSLATION_OFFSET_EN;
 374         ucseg->klm_octowords =
 375                 cpu_to_be16(MLX5_MTT_OCTW(MLX5_MPWRQ_PAGES_PER_WQE));
 376         ucseg->bsf_octowords =
 377                 cpu_to_be16(MLX5_MTT_OCTW(umr_wqe_mtt_offset));
 378         ucseg->mkey_mask     = cpu_to_be64(MLX5_MKEY_MASK_FREE);
 379
 380         dseg->lkey = sq->mkey_be;
 381         dseg->addr = cpu_to_be64(wi->umr.mtt_addr);
 382 }
 383
 384 static int mlx5e_rq_alloc_mpwqe_info(struct mlx5e_rq *rq,
 385                                      struct mlx5e_channel *c)
 386 {
 387         int wq_sz = mlx5_wq_ll_get_size(&rq->wq);
 388         int mtt_sz = mlx5e_get_wqe_mtt_sz();
 389         int mtt_alloc = mtt_sz + MLX5_UMR_ALIGN - 1;
 390         int i;
 391
 392         rq->mpwqe.info = kzalloc_node(wq_sz * sizeof(*rq->mpwqe.info),
 393                                       GFP_KERNEL, cpu_to_node(c->cpu));
 394         if (!rq->mpwqe.info)
 395                 goto err_out;
 396
 397         /* We allocate more than mtt_sz as we will align the pointer */
 398         rq->mpwqe.mtt_no_align = kzalloc_node(mtt_alloc * wq_sz, GFP_KERNEL,
 399                                         cpu_to_node(c->cpu));
 400         if (unlikely(!rq->mpwqe.mtt_no_align))
 401                 goto err_free_wqe_info;
 402
 403         for (i = 0; i < wq_sz; i++) {
 404                 struct mlx5e_mpw_info *wi = &rq->mpwqe.info[i];
 405
 406                 wi->umr.mtt = PTR_ALIGN(rq->mpwqe.mtt_no_align + i * mtt_alloc,
 407                                         MLX5_UMR_ALIGN);
 408                 wi->umr.mtt_addr = dma_map_single(c->pdev, wi->umr.mtt, mtt_sz,
 409                                                   PCI_DMA_TODEVICE);
 410                 if (unlikely(dma_mapping_error(c->pdev, wi->umr.mtt_addr)))
 411                         goto err_unmap_mtts;
 412
 413                 mlx5e_build_umr_wqe(rq, &c->icosq, &wi->umr.wqe, i);
 414         }
 415
 416         return 0;
 417
 418 err_unmap_mtts:
 419         while (--i >= 0) {
 420                 struct mlx5e_mpw_info *wi = &rq->mpwqe.info[i];
 421
 422                 dma_unmap_single(c->pdev, wi->umr.mtt_addr, mtt_sz,
 423                                  PCI_DMA_TODEVICE);
 424         }
 425         kfree(rq->mpwqe.mtt_no_align);
 426 err_free_wqe_info:
 427         kfree(rq->mpwqe.info);
 428
 429 err_out:
 430         return -ENOMEM;
 431 }
 432
 433 static void mlx5e_rq_free_mpwqe_info(struct mlx5e_rq *rq)
 434 {
 435         int wq_sz = mlx5_wq_ll_get_size(&rq->wq);
 436         int mtt_sz = mlx5e_get_wqe_mtt_sz();
 437         int i;
 438
 439         for (i = 0; i < wq_sz; i++) {
 440                 struct mlx5e_mpw_info *wi = &rq->mpwqe.info[i];
 441
 442                 dma_unmap_single(rq->pdev, wi->umr.mtt_addr, mtt_sz,
 443                                  PCI_DMA_TODEVICE);
 444         }
 445         kfree(rq->mpwqe.mtt_no_align);
 446         kfree(rq->mpwqe.info);
 447 }
 448
 449 static bool mlx5e_is_vf_vport_rep(struct mlx5e_priv *priv)
 450 {
 451         struct mlx5_eswitch_rep *rep = (struct mlx5_eswitch_rep *)priv->ppriv;
 452
 453         if (rep && rep->vport != FDB_UPLINK_VPORT)
 454                 return true;
 455
 456         return false;
 457 }
 458
 459 static int mlx5e_create_rq(struct mlx5e_channel *c,
 460                            struct mlx5e_rq_param *param,
 461                            struct mlx5e_rq *rq)
 462 {
 463         struct mlx5e_priv *priv = c->priv;
 464         struct mlx5_core_dev *mdev = priv->mdev;
 465         void *rqc = param->rqc;
 466         void *rqc_wq = MLX5_ADDR_OF(rqc, rqc, wq);
 467         u32 byte_count;
 468         u32 frag_sz;
 469         int npages;
 470         int wq_sz;
 471         int err;
 472         int i;
 473
 474         param->wq.db_numa_node = cpu_to_node(c->cpu);
 475
 476         err = mlx5_wq_ll_create(mdev, &param->wq, rqc_wq, &rq->wq,
 477                                 &rq->wq_ctrl);
 478         if (err)
 479                 return err;
 480
 481         rq->wq.db = &rq->wq.db[MLX5_RCV_DBR];
 482
 483         wq_sz = mlx5_wq_ll_get_size(&rq->wq);
 484
 485         rq->wq_type = priv->params.rq_wq_type;
 486         rq->pdev    = c->pdev;
 487         rq->netdev  = c->netdev;
 488         rq->tstamp  = &priv->tstamp;
 489         rq->channel = c;
 490         rq->ix      = c->ix;
 491         rq->priv    = c->priv;
 492         rq->xdp_prog = priv->xdp_prog;
 493
 494         rq->buff.map_dir = DMA_FROM_DEVICE;
 495         if (rq->xdp_prog)
 496                 rq->buff.map_dir = DMA_BIDIRECTIONAL;
 497
 498         switch (priv->params.rq_wq_type) {
 499         case MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ:
 500                 if (mlx5e_is_vf_vport_rep(priv)) {
 501                         err = -EINVAL;
 502                         goto err_rq_wq_destroy;
 503                 }
 504
 505                 rq->handle_rx_cqe = mlx5e_handle_rx_cqe_mpwrq;
 506                 rq->alloc_wqe = mlx5e_alloc_rx_mpwqe;
 507                 rq->dealloc_wqe = mlx5e_dealloc_rx_mpwqe;
 508
 509                 rq->mpwqe.mtt_offset = c->ix *
 510                         MLX5E_REQUIRED_MTTS(1, BIT(priv->params.log_rq_size));
 511
 512                 rq->mpwqe_stride_sz = BIT(priv->params.mpwqe_log_stride_sz);
 513                 rq->mpwqe_num_strides = BIT(priv->params.mpwqe_log_num_strides);
 514
 515                 rq->buff.wqe_sz = rq->mpwqe_stride_sz * rq->mpwqe_num_strides;
 516                 byte_count = rq->buff.wqe_sz;
 517                 rq->mkey_be = cpu_to_be32(c->priv->umr_mkey.key);
 518                 err = mlx5e_rq_alloc_mpwqe_info(rq, c);
 519                 if (err)
 520                         goto err_rq_wq_destroy;
 521                 break;
 522         default: /* MLX5_WQ_TYPE_LINKED_LIST */
 523                 rq->dma_info = kzalloc_node(wq_sz * sizeof(*rq->dma_info),
 524                                             GFP_KERNEL, cpu_to_node(c->cpu));
 525                 if (!rq->dma_info) {
 526                         err = -ENOMEM;
 527                         goto err_rq_wq_destroy;
 528                 }
 529
 530                 if (mlx5e_is_vf_vport_rep(priv))
 531                         rq->handle_rx_cqe = mlx5e_handle_rx_cqe_rep;
 532                 else
 533                         rq->handle_rx_cqe = mlx5e_handle_rx_cqe;
 534
 535                 rq->alloc_wqe = mlx5e_alloc_rx_wqe;
 536                 rq->dealloc_wqe = mlx5e_dealloc_rx_wqe;
 537
 538                 rq->buff.wqe_sz = (priv->params.lro_en) ?
 539                                 priv->params.lro_wqe_sz :
 540                                 MLX5E_SW2HW_MTU(priv->netdev->mtu);
 541                 byte_count = rq->buff.wqe_sz;
 542
 543                 /* calc the required page order */
 544                 frag_sz = MLX5_RX_HEADROOM +
 545                           byte_count /* packet data */ +
 546                           SKB_DATA_ALIGN(sizeof(struct skb_shared_info));
 547                 frag_sz = SKB_DATA_ALIGN(frag_sz);
 548
 549                 npages = DIV_ROUND_UP(frag_sz, PAGE_SIZE);
 550                 rq->buff.page_order = order_base_2(npages);
 551
 552                 byte_count |= MLX5_HW_START_PADDING;
 553                 rq->mkey_be = c->mkey_be;
 554         }
 555
 556         for (i = 0; i < wq_sz; i++) {
 557                 struct mlx5e_rx_wqe *wqe = mlx5_wq_ll_get_wqe(&rq->wq, i);
 558
 559                 wqe->data.byte_count = cpu_to_be32(byte_count);
 560                 wqe->data.lkey = rq->mkey_be;
 561         }
 562
 563         INIT_WORK(&rq->am.work, mlx5e_rx_am_work);
 564         rq->am.mode = priv->params.rx_cq_period_mode;
 565
 566         rq->page_cache.head = 0;
 567         rq->page_cache.tail = 0;
 568
 569         if (rq->xdp_prog)
 570                 bpf_prog_add(rq->xdp_prog, 1);
 571
 572         return 0;
 573
 574 err_rq_wq_destroy:
 575         mlx5_wq_destroy(&rq->wq_ctrl);
 576
 577         return err;
 578 }
 579
 580 static void mlx5e_destroy_rq(struct mlx5e_rq *rq)
 581 {
 582         int i;
 583
 584         if (rq->xdp_prog)
 585                 bpf_prog_put(rq->xdp_prog);
 586
 587         switch (rq->wq_type) {
 588         case MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ:
 589                 mlx5e_rq_free_mpwqe_info(rq);
 590                 break;
 591         default: /* MLX5_WQ_TYPE_LINKED_LIST */
 592                 kfree(rq->dma_info);
 593         }
 594
 595         for (i = rq->page_cache.head; i != rq->page_cache.tail;
 596              i = (i + 1) & (MLX5E_CACHE_SIZE - 1)) {
 597                 struct mlx5e_dma_info *dma_info = &rq->page_cache.page_cache[i];
 598
 599                 mlx5e_page_release(rq, dma_info, false);
 600         }
 601         mlx5_wq_destroy(&rq->wq_ctrl);
 602 }
 603
 604 static int mlx5e_enable_rq(struct mlx5e_rq *rq, struct mlx5e_rq_param *param)
 605 {
 606         struct mlx5e_priv *priv = rq->priv;
 607         struct mlx5_core_dev *mdev = priv->mdev;
 608
 609         void *in;
 610         void *rqc;
 611         void *wq;
 612         int inlen;
 613         int err;
 614
 615         inlen = MLX5_ST_SZ_BYTES(create_rq_in) +
 616                 sizeof(u64) * rq->wq_ctrl.buf.npages;
 617         in = mlx5_vzalloc(inlen);
 618         if (!in)
 619                 return -ENOMEM;
 620
 621         rqc = MLX5_ADDR_OF(create_rq_in, in, ctx);
 622         wq  = MLX5_ADDR_OF(rqc, rqc, wq);
 623
 624         memcpy(rqc, param->rqc, sizeof(param->rqc));
 625
 626         MLX5_SET(rqc,  rqc, cqn,                rq->cq.mcq.cqn);
 627         MLX5_SET(rqc,  rqc, state,              MLX5_RQC_STATE_RST);
 628         MLX5_SET(rqc,  rqc, vsd, priv->params.vlan_strip_disable);
 629         MLX5_SET(wq,   wq,  log_wq_pg_sz,       rq->wq_ctrl.buf.page_shift -
 630                                                 MLX5_ADAPTER_PAGE_SHIFT);
 631         MLX5_SET64(wq, wq,  dbr_addr,           rq->wq_ctrl.db.dma);
 632
 633         mlx5_fill_page_array(&rq->wq_ctrl.buf,
 634                              (__be64 *)MLX5_ADDR_OF(wq, wq, pas));
 635
 636         err = mlx5_core_create_rq(mdev, in, inlen, &rq->rqn);
 637
 638         kvfree(in);
 639
 640         return err;
 641 }
 642
 643 static int mlx5e_modify_rq_state(struct mlx5e_rq *rq, int curr_state,
 644                                  int next_state)
 645 {
 646         struct mlx5e_channel *c = rq->channel;
 647         struct mlx5e_priv *priv = c->priv;
 648         struct mlx5_core_dev *mdev = priv->mdev;
 649
 650         void *in;
 651         void *rqc;
 652         int inlen;
 653         int err;
 654
 655         inlen = MLX5_ST_SZ_BYTES(modify_rq_in);
 656         in = mlx5_vzalloc(inlen);
 657         if (!in)
 658                 return -ENOMEM;
 659
 660         rqc = MLX5_ADDR_OF(modify_rq_in, in, ctx);
 661
 662         MLX5_SET(modify_rq_in, in, rq_state, curr_state);
 663         MLX5_SET(rqc, rqc, state, next_state);
 664
 665         err = mlx5_core_modify_rq(mdev, rq->rqn, in, inlen);
 666
 667         kvfree(in);
 668
 669         return err;
 670 }
 671
 672 static int mlx5e_modify_rq_vsd(struct mlx5e_rq *rq, bool vsd)
 673 {
 674         struct mlx5e_channel *c = rq->channel;
 675         struct mlx5e_priv *priv = c->priv;
 676         struct mlx5_core_dev *mdev = priv->mdev;
 677
 678         void *in;
 679         void *rqc;
 680         int inlen;
 681         int err;
 682
 683         inlen = MLX5_ST_SZ_BYTES(modify_rq_in);
 684         in = mlx5_vzalloc(inlen);
 685         if (!in)
 686                 return -ENOMEM;
 687
 688         rqc = MLX5_ADDR_OF(modify_rq_in, in, ctx);
 689
 690         MLX5_SET(modify_rq_in, in, rq_state, MLX5_RQC_STATE_RDY);
 691         MLX5_SET64(modify_rq_in, in, modify_bitmask,
 692                    MLX5_MODIFY_RQ_IN_MODIFY_BITMASK_VSD);
 693         MLX5_SET(rqc, rqc, vsd, vsd);
 694         MLX5_SET(rqc, rqc, state, MLX5_RQC_STATE_RDY);
 695
 696         err = mlx5_core_modify_rq(mdev, rq->rqn, in, inlen);
 697
 698         kvfree(in);
 699
 700         return err;
 701 }
 702
 703 static void mlx5e_disable_rq(struct mlx5e_rq *rq)
 704 {
 705         mlx5_core_destroy_rq(rq->priv->mdev, rq->rqn);
 706 }
 707
 708 static int mlx5e_wait_for_min_rx_wqes(struct mlx5e_rq *rq)
 709 {
 710         unsigned long exp_time = jiffies + msecs_to_jiffies(20000);
 711         struct mlx5e_channel *c = rq->channel;
 712         struct mlx5e_priv *priv = c->priv;
 713         struct mlx5_wq_ll *wq = &rq->wq;
 714
 715         while (time_before(jiffies, exp_time)) {
 716                 if (wq->cur_sz >= priv->params.min_rx_wqes)
 717                         return 0;
 718
 719                 msleep(20);
 720         }
 721
 722         return -ETIMEDOUT;
 723 }
 724
 725 static void mlx5e_free_rx_descs(struct mlx5e_rq *rq)
 726 {
 727         struct mlx5_wq_ll *wq = &rq->wq;
 728         struct mlx5e_rx_wqe *wqe;
 729         __be16 wqe_ix_be;
 730         u16 wqe_ix;
 731
 732         /* UMR WQE (if in progress) is always at wq->head */
 733         if (test_bit(MLX5E_RQ_STATE_UMR_WQE_IN_PROGRESS, &rq->state))
 734                 mlx5e_free_rx_mpwqe(rq, &rq->mpwqe.info[wq->head]);
 735
 736         while (!mlx5_wq_ll_is_empty(wq)) {
 737                 wqe_ix_be = *wq->tail_next;
 738                 wqe_ix    = be16_to_cpu(wqe_ix_be);
 739                 wqe       = mlx5_wq_ll_get_wqe(&rq->wq, wqe_ix);
 740                 rq->dealloc_wqe(rq, wqe_ix);
 741                 mlx5_wq_ll_pop(&rq->wq, wqe_ix_be,
 742                                &wqe->next.next_wqe_index);
 743         }
 744 }
 745
 746 static int mlx5e_open_rq(struct mlx5e_channel *c,
 747                          struct mlx5e_rq_param *param,
 748                          struct mlx5e_rq *rq)
 749 {
 750         struct mlx5e_sq *sq = &c->icosq;
 751         u16 pi = sq->pc & sq->wq.sz_m1;
 752         int err;
 753
 754         err = mlx5e_create_rq(c, param, rq);
 755         if (err)
 756                 return err;
 757
 758         err = mlx5e_enable_rq(rq, param);
 759         if (err)
 760                 goto err_destroy_rq;
 761
 762         err = mlx5e_modify_rq_state(rq, MLX5_RQC_STATE_RST, MLX5_RQC_STATE_RDY);
 763         if (err)
 764                 goto err_disable_rq;
 765
 766         if (param->am_enabled)
 767                 set_bit(MLX5E_RQ_STATE_AM, &c->rq.state);
 768
 769         sq->db.ico_wqe[pi].opcode     = MLX5_OPCODE_NOP;
 770         sq->db.ico_wqe[pi].num_wqebbs = 1;
 771         mlx5e_send_nop(sq, true); /* trigger mlx5e_post_rx_wqes() */
 772
 773         return 0;
 774
 775 err_disable_rq:
 776         mlx5e_disable_rq(rq);
 777 err_destroy_rq:
 778         mlx5e_destroy_rq(rq);
 779
 780         return err;
 781 }
 782
 783 static void mlx5e_close_rq(struct mlx5e_rq *rq)
 784 {
 785         set_bit(MLX5E_RQ_STATE_FLUSH, &rq->state);
 786         napi_synchronize(&rq->channel->napi); /* prevent mlx5e_post_rx_wqes */
 787         cancel_work_sync(&rq->am.work);
 788
 789         mlx5e_disable_rq(rq);
 790         mlx5e_free_rx_descs(rq);
 791         mlx5e_destroy_rq(rq);
 792 }
 793
 794 static void mlx5e_free_sq_xdp_db(struct mlx5e_sq *sq)
 795 {
 796         kfree(sq->db.xdp.di);
 797         kfree(sq->db.xdp.wqe_info);
 798 }
 799
 800 static int mlx5e_alloc_sq_xdp_db(struct mlx5e_sq *sq, int numa)
 801 {
 802         int wq_sz = mlx5_wq_cyc_get_size(&sq->wq);
 803
 804         sq->db.xdp.di = kzalloc_node(sizeof(*sq->db.xdp.di) * wq_sz,
 805                                      GFP_KERNEL, numa);
 806         sq->db.xdp.wqe_info = kzalloc_node(sizeof(*sq->db.xdp.wqe_info) * wq_sz,
 807                                            GFP_KERNEL, numa);
 808         if (!sq->db.xdp.di || !sq->db.xdp.wqe_info) {
 809                 mlx5e_free_sq_xdp_db(sq);
 810                 return -ENOMEM;
 811         }
 812
 813         return 0;
 814 }
 815
 816 static void mlx5e_free_sq_ico_db(struct mlx5e_sq *sq)
 817 {
 818         kfree(sq->db.ico_wqe);
 819 }
 820
 821 static int mlx5e_alloc_sq_ico_db(struct mlx5e_sq *sq, int numa)
 822 {
 823         u8 wq_sz = mlx5_wq_cyc_get_size(&sq->wq);
 824
 825         sq->db.ico_wqe = kzalloc_node(sizeof(*sq->db.ico_wqe) * wq_sz,
 826                                       GFP_KERNEL, numa);
 827         if (!sq->db.ico_wqe)
 828                 return -ENOMEM;
 829
 830         return 0;
 831 }
 832
 833 static void mlx5e_free_sq_txq_db(struct mlx5e_sq *sq)
 834 {
 835         kfree(sq->db.txq.wqe_info);
 836         kfree(sq->db.txq.dma_fifo);
 837         kfree(sq->db.txq.skb);
 838 }
 839
 840 static int mlx5e_alloc_sq_txq_db(struct mlx5e_sq *sq, int numa)
 841 {
 842         int wq_sz = mlx5_wq_cyc_get_size(&sq->wq);
 843         int df_sz = wq_sz * MLX5_SEND_WQEBB_NUM_DS;
 844
 845         sq->db.txq.skb = kzalloc_node(wq_sz * sizeof(*sq->db.txq.skb),
 846                                       GFP_KERNEL, numa);
 847         sq->db.txq.dma_fifo = kzalloc_node(df_sz * sizeof(*sq->db.txq.dma_fifo),
 848                                            GFP_KERNEL, numa);
 849         sq->db.txq.wqe_info = kzalloc_node(wq_sz * sizeof(*sq->db.txq.wqe_info),
 850                                            GFP_KERNEL, numa);
 851         if (!sq->db.txq.skb || !sq->db.txq.dma_fifo || !sq->db.txq.wqe_info) {
 852                 mlx5e_free_sq_txq_db(sq);
 853                 return -ENOMEM;
 854         }
 855
 856         sq->dma_fifo_mask = df_sz - 1;
 857
 858         return 0;
 859 }
 860
 861 static void mlx5e_free_sq_db(struct mlx5e_sq *sq)
 862 {
 863         switch (sq->type) {
 864         case MLX5E_SQ_TXQ:
 865                 mlx5e_free_sq_txq_db(sq);
 866                 break;
 867         case MLX5E_SQ_ICO:
 868                 mlx5e_free_sq_ico_db(sq);
 869                 break;
 870         case MLX5E_SQ_XDP:
 871                 mlx5e_free_sq_xdp_db(sq);
 872                 break;
 873         }
 874 }
 875
 876 static int mlx5e_alloc_sq_db(struct mlx5e_sq *sq, int numa)
 877 {
 878         switch (sq->type) {
 879         case MLX5E_SQ_TXQ:
 880                 return mlx5e_alloc_sq_txq_db(sq, numa);
 881         case MLX5E_SQ_ICO:
 882                 return mlx5e_alloc_sq_ico_db(sq, numa);
 883         case MLX5E_SQ_XDP:
 884                 return mlx5e_alloc_sq_xdp_db(sq, numa);
 885         }
 886
 887         return 0;
 888 }
 889
 890 static int mlx5e_sq_get_max_wqebbs(u8 sq_type)
 891 {
 892         switch (sq_type) {
 893         case MLX5E_SQ_ICO:
 894                 return MLX5E_ICOSQ_MAX_WQEBBS;
 895         case MLX5E_SQ_XDP:
 896                 return MLX5E_XDP_TX_WQEBBS;
 897         }
 898         return MLX5_SEND_WQE_MAX_WQEBBS;
 899 }
 900
 901 static int mlx5e_create_sq(struct mlx5e_channel *c,
 902                            int tc,
 903                            struct mlx5e_sq_param *param,
 904                            struct mlx5e_sq *sq)
 905 {
 906         struct mlx5e_priv *priv = c->priv;
 907         struct mlx5_core_dev *mdev = priv->mdev;
 908
 909         void *sqc = param->sqc;
 910         void *sqc_wq = MLX5_ADDR_OF(sqc, sqc, wq);
 911         int err;
 912
 913         sq->type      = param->type;
 914         sq->pdev      = c->pdev;
 915         sq->tstamp    = &priv->tstamp;
 916         sq->mkey_be   = c->mkey_be;
 917         sq->channel   = c;
 918         sq->tc        = tc;
 919
 920         err = mlx5_alloc_map_uar(mdev, &sq->uar, !!MLX5_CAP_GEN(mdev, bf));
 921         if (err)
 922                 return err;
 923
 924         param->wq.db_numa_node = cpu_to_node(c->cpu);
 925
 926         err = mlx5_wq_cyc_create(mdev, &param->wq, sqc_wq, &sq->wq,
 927                                  &sq->wq_ctrl);
 928         if (err)
 929                 goto err_unmap_free_uar;
 930
 931         sq->wq.db       = &sq->wq.db[MLX5_SND_DBR];
 932         if (sq->uar.bf_map) {
 933                 set_bit(MLX5E_SQ_STATE_BF_ENABLE, &sq->state);
 934                 sq->uar_map = sq->uar.bf_map;
 935         } else {
 936                 sq->uar_map = sq->uar.map;
 937         }
 938         sq->bf_buf_size = (1 << MLX5_CAP_GEN(mdev, log_bf_reg_size)) / 2;
 939         sq->max_inline  = param->max_inline;
 940         sq->min_inline_mode =
 941                 MLX5_CAP_ETH(mdev, wqe_inline_mode) == MLX5E_INLINE_MODE_VPORT_CONTEXT ?
 942                 param->min_inline_mode : 0;
 943
 944         err = mlx5e_alloc_sq_db(sq, cpu_to_node(c->cpu));
 945         if (err)
 946                 goto err_sq_wq_destroy;
 947
 948         if (sq->type == MLX5E_SQ_TXQ) {
 949                 int txq_ix;
 950
 951                 txq_ix = c->ix + tc * priv->params.num_channels;
 952                 sq->txq = netdev_get_tx_queue(priv->netdev, txq_ix);
 953                 priv->txq_to_sq_map[txq_ix] = sq;
 954         }
 955
 956         sq->edge = (sq->wq.sz_m1 + 1) - mlx5e_sq_get_max_wqebbs(sq->type);
 957         sq->bf_budget = MLX5E_SQ_BF_BUDGET;
 958
 959         return 0;
 960
 961 err_sq_wq_destroy:
 962         mlx5_wq_destroy(&sq->wq_ctrl);
 963
 964 err_unmap_free_uar:
 965         mlx5_unmap_free_uar(mdev, &sq->uar);
 966
 967         return err;
 968 }
 969
 970 static void mlx5e_destroy_sq(struct mlx5e_sq *sq)
 971 {
 972         struct mlx5e_channel *c = sq->channel;
 973         struct mlx5e_priv *priv = c->priv;
 974
 975         mlx5e_free_sq_db(sq);
 976         mlx5_wq_destroy(&sq->wq_ctrl);
 977         mlx5_unmap_free_uar(priv->mdev, &sq->uar);
 978 }
 979
 980 static int mlx5e_enable_sq(struct mlx5e_sq *sq, struct mlx5e_sq_param *param)
 981 {
 982         struct mlx5e_channel *c = sq->channel;
 983         struct mlx5e_priv *priv = c->priv;
 984         struct mlx5_core_dev *mdev = priv->mdev;
 985
 986         void *in;
 987         void *sqc;
 988         void *wq;
 989         int inlen;
 990         int err;
 991
 992         inlen = MLX5_ST_SZ_BYTES(create_sq_in) +
 993                 sizeof(u64) * sq->wq_ctrl.buf.npages;
 994         in = mlx5_vzalloc(inlen);
 995         if (!in)
 996                 return -ENOMEM;
 997
 998         sqc = MLX5_ADDR_OF(create_sq_in, in, ctx);
 999         wq = MLX5_ADDR_OF(sqc, sqc, wq);
1000
1001         memcpy(sqc, param->sqc, sizeof(param->sqc));
1002
1003         MLX5_SET(sqc,  sqc, tis_num_0, param->type == MLX5E_SQ_ICO ?
1004                                        0 : priv->tisn[sq->tc]);
1005         MLX5_SET(sqc,  sqc, cqn,                sq->cq.mcq.cqn);
1006         MLX5_SET(sqc,  sqc, min_wqe_inline_mode, sq->min_inline_mode);
1007         MLX5_SET(sqc,  sqc, state,              MLX5_SQC_STATE_RST);
1008         MLX5_SET(sqc,  sqc, tis_lst_sz, param->type == MLX5E_SQ_ICO ? 0 : 1);
1009         MLX5_SET(sqc,  sqc, flush_in_error_en,  1);
1010
1011         MLX5_SET(wq,   wq, wq_type,       MLX5_WQ_TYPE_CYCLIC);
1012         MLX5_SET(wq,   wq, uar_page,      sq->uar.index);
1013         MLX5_SET(wq,   wq, log_wq_pg_sz,  sq->wq_ctrl.buf.page_shift -
1014                                           MLX5_ADAPTER_PAGE_SHIFT);
1015         MLX5_SET64(wq, wq, dbr_addr,      sq->wq_ctrl.db.dma);
1016
1017         mlx5_fill_page_array(&sq->wq_ctrl.buf,
1018                              (__be64 *)MLX5_ADDR_OF(wq, wq, pas));
1019
1020         err = mlx5_core_create_sq(mdev, in, inlen, &sq->sqn);
1021
1022         kvfree(in);
1023
1024         return err;
1025 }
1026
1027 static int mlx5e_modify_sq(struct mlx5e_sq *sq, int curr_state,
1028                            int next_state, bool update_rl, int rl_index)
1029 {
1030         struct mlx5e_channel *c = sq->channel;
1031         struct mlx5e_priv *priv = c->priv;
1032         struct mlx5_core_dev *mdev = priv->mdev;
1033
1034         void *in;
1035         void *sqc;
1036         int inlen;
1037         int err;
1038
1039         inlen = MLX5_ST_SZ_BYTES(modify_sq_in);
1040         in = mlx5_vzalloc(inlen);
1041         if (!in)
1042                 return -ENOMEM;
1043
1044         sqc = MLX5_ADDR_OF(modify_sq_in, in, ctx);
1045
1046         MLX5_SET(modify_sq_in, in, sq_state, curr_state);
1047         MLX5_SET(sqc, sqc, state, next_state);
1048         if (update_rl && next_state == MLX5_SQC_STATE_RDY) {
1049                 MLX5_SET64(modify_sq_in, in, modify_bitmask, 1);
1050                 MLX5_SET(sqc,  sqc, packet_pacing_rate_limit_index, rl_index);
1051         }
1052
1053         err = mlx5_core_modify_sq(mdev, sq->sqn, in, inlen);
1054
1055         kvfree(in);
1056
1057         return err;
1058 }
1059
1060 static void mlx5e_disable_sq(struct mlx5e_sq *sq)
1061 {
1062         struct mlx5e_channel *c = sq->channel;
1063         struct mlx5e_priv *priv = c->priv;
1064         struct mlx5_core_dev *mdev = priv->mdev;
1065
1066         mlx5_core_destroy_sq(mdev, sq->sqn);
1067         if (sq->rate_limit)
1068                 mlx5_rl_remove_rate(mdev, sq->rate_limit);
1069 }
1070
1071 static int mlx5e_open_sq(struct mlx5e_channel *c,
1072                          int tc,
1073                          struct mlx5e_sq_param *param,
1074                          struct mlx5e_sq *sq)
1075 {
1076         int err;
1077
1078         err = mlx5e_create_sq(c, tc, param, sq);
1079         if (err)
1080                 return err;
1081
1082         err = mlx5e_enable_sq(sq, param);
1083         if (err)
1084                 goto err_destroy_sq;
1085
1086         err = mlx5e_modify_sq(sq, MLX5_SQC_STATE_RST, MLX5_SQC_STATE_RDY,
1087                               false, 0);
1088         if (err)
1089                 goto err_disable_sq;
1090
1091         if (sq->txq) {
1092                 netdev_tx_reset_queue(sq->txq);
1093                 netif_tx_start_queue(sq->txq);
1094         }
1095
1096         return 0;
1097
1098 err_disable_sq:
1099         mlx5e_disable_sq(sq);
1100 err_destroy_sq:
1101         mlx5e_destroy_sq(sq);
1102
1103         return err;
1104 }
1105
1106 static inline void netif_tx_disable_queue(struct netdev_queue *txq)
1107 {
1108         __netif_tx_lock_bh(txq);
1109         netif_tx_stop_queue(txq);
1110         __netif_tx_unlock_bh(txq);
1111 }
1112
1113 static void mlx5e_close_sq(struct mlx5e_sq *sq)
1114 {
1115         set_bit(MLX5E_SQ_STATE_FLUSH, &sq->state);
1116         /* prevent netif_tx_wake_queue */
1117         napi_synchronize(&sq->channel->napi);
1118
1119         if (sq->txq) {
1120                 netif_tx_disable_queue(sq->txq);
1121
1122                 /* last doorbell out, godspeed .. */
1123                 if (mlx5e_sq_has_room_for(sq, 1)) {
1124                         sq->db.txq.skb[(sq->pc & sq->wq.sz_m1)] = NULL;
1125                         mlx5e_send_nop(sq, true);
1126                 }
1127         }
1128
1129         mlx5e_disable_sq(sq);
1130         mlx5e_free_sq_descs(sq);
1131         mlx5e_destroy_sq(sq);
1132 }
1133
1134 static int mlx5e_create_cq(struct mlx5e_channel *c,
1135                            struct mlx5e_cq_param *param,
1136                            struct mlx5e_cq *cq)
1137 {
1138         struct mlx5e_priv *priv = c->priv;
1139         struct mlx5_core_dev *mdev = priv->mdev;
1140         struct mlx5_core_cq *mcq = &cq->mcq;
1141         int eqn_not_used;
1142         unsigned int irqn;
1143         int err;
1144         u32 i;
1145
1146         param->wq.buf_numa_node = cpu_to_node(c->cpu);
1147         param->wq.db_numa_node  = cpu_to_node(c->cpu);
1148         param->eq_ix   = c->ix;
1149
1150         err = mlx5_cqwq_create(mdev, &param->wq, param->cqc, &cq->wq,
1151                                &cq->wq_ctrl);
1152         if (err)
1153                 return err;
1154
1155         mlx5_vector2eqn(mdev, param->eq_ix, &eqn_not_used, &irqn);
1156
1157         cq->napi        = &c->napi;
1158
1159         mcq->cqe_sz     = 64;
1160         mcq->set_ci_db  = cq->wq_ctrl.db.db;
1161         mcq->arm_db     = cq->wq_ctrl.db.db + 1;
1162         *mcq->set_ci_db = 0;
1163         *mcq->arm_db    = 0;
1164         mcq->vector     = param->eq_ix;
1165         mcq->comp       = mlx5e_completion_event;
1166         mcq->event      = mlx5e_cq_error_event;
1167         mcq->irqn       = irqn;
1168         mcq->uar        = &mdev->mlx5e_res.cq_uar;
1169
1170         for (i = 0; i < mlx5_cqwq_get_size(&cq->wq); i++) {
1171                 struct mlx5_cqe64 *cqe = mlx5_cqwq_get_wqe(&cq->wq, i);
1172
1173                 cqe->op_own = 0xf1;
1174         }
1175
1176         cq->channel = c;
1177         cq->priv = priv;
1178
1179         return 0;
1180 }
1181
1182 static void mlx5e_destroy_cq(struct mlx5e_cq *cq)
1183 {
1184         mlx5_wq_destroy(&cq->wq_ctrl);
1185 }
1186
1187 static int mlx5e_enable_cq(struct mlx5e_cq *cq, struct mlx5e_cq_param *param)
1188 {
1189         struct mlx5e_priv *priv = cq->priv;
1190         struct mlx5_core_dev *mdev = priv->mdev;
1191         struct mlx5_core_cq *mcq = &cq->mcq;
1192
1193         void *in;
1194         void *cqc;
1195         int inlen;
1196         unsigned int irqn_not_used;
1197         int eqn;
1198         int err;
1199
1200         inlen = MLX5_ST_SZ_BYTES(create_cq_in) +
1201                 sizeof(u64) * cq->wq_ctrl.buf.npages;
1202         in = mlx5_vzalloc(inlen);
1203         if (!in)
1204                 return -ENOMEM;
1205
1206         cqc = MLX5_ADDR_OF(create_cq_in, in, cq_context);
1207
1208         memcpy(cqc, param->cqc, sizeof(param->cqc));
1209
1210         mlx5_fill_page_array(&cq->wq_ctrl.buf,
1211                              (__be64 *)MLX5_ADDR_OF(create_cq_in, in, pas));
1212
1213         mlx5_vector2eqn(mdev, param->eq_ix, &eqn, &irqn_not_used);
1214
1215         MLX5_SET(cqc,   cqc, cq_period_mode, param->cq_period_mode);
1216         MLX5_SET(cqc,   cqc, c_eqn,         eqn);
1217         MLX5_SET(cqc,   cqc, uar_page,      mcq->uar->index);
1218         MLX5_SET(cqc,   cqc, log_page_size, cq->wq_ctrl.buf.page_shift -
1219                                             MLX5_ADAPTER_PAGE_SHIFT);
1220         MLX5_SET64(cqc, cqc, dbr_addr,      cq->wq_ctrl.db.dma);
1221
1222         err = mlx5_core_create_cq(mdev, mcq, in, inlen);
1223
1224         kvfree(in);
1225
1226         if (err)
1227                 return err;
1228
1229         mlx5e_cq_arm(cq);
1230
1231         return 0;
1232 }
1233
1234 static void mlx5e_disable_cq(struct mlx5e_cq *cq)
1235 {
1236         struct mlx5e_priv *priv = cq->priv;
1237         struct mlx5_core_dev *mdev = priv->mdev;
1238
1239         mlx5_core_destroy_cq(mdev, &cq->mcq);
1240 }
1241
1242 static int mlx5e_open_cq(struct mlx5e_channel *c,
1243                          struct mlx5e_cq_param *param,
1244                          struct mlx5e_cq *cq,
1245                          struct mlx5e_cq_moder moderation)
1246 {
1247         int err;
1248         struct mlx5e_priv *priv = c->priv;
1249         struct mlx5_core_dev *mdev = priv->mdev;
1250
1251         err = mlx5e_create_cq(c, param, cq);
1252         if (err)
1253                 return err;
1254
1255         err = mlx5e_enable_cq(cq, param);
1256         if (err)
1257                 goto err_destroy_cq;
1258
1259         if (MLX5_CAP_GEN(mdev, cq_moderation))
1260                 mlx5_core_modify_cq_moderation(mdev, &cq->mcq,
1261                                                moderation.usec,
1262                                                moderation.pkts);
1263         return 0;
1264
1265 err_destroy_cq:
1266         mlx5e_destroy_cq(cq);
1267
1268         return err;
1269 }
1270
1271 static void mlx5e_close_cq(struct mlx5e_cq *cq)
1272 {
1273         mlx5e_disable_cq(cq);
1274         mlx5e_destroy_cq(cq);
1275 }
1276
1277 static int mlx5e_get_cpu(struct mlx5e_priv *priv, int ix)
1278 {
1279         return cpumask_first(priv->mdev->priv.irq_info[ix].mask);
1280 }
1281
1282 static int mlx5e_open_tx_cqs(struct mlx5e_channel *c,
1283                              struct mlx5e_channel_param *cparam)
1284 {
1285         struct mlx5e_priv *priv = c->priv;
1286         int err;
1287         int tc;
1288
1289         for (tc = 0; tc < c->num_tc; tc++) {
1290                 err = mlx5e_open_cq(c, &cparam->tx_cq, &c->sq[tc].cq,
1291                                     priv->params.tx_cq_moderation);
1292                 if (err)
1293                         goto err_close_tx_cqs;
1294         }
1295
1296         return 0;
1297
1298 err_close_tx_cqs:
1299         for (tc--; tc >= 0; tc--)
1300                 mlx5e_close_cq(&c->sq[tc].cq);
1301
1302         return err;
1303 }
1304
1305 static void mlx5e_close_tx_cqs(struct mlx5e_channel *c)
1306 {
1307         int tc;
1308
1309         for (tc = 0; tc < c->num_tc; tc++)
1310                 mlx5e_close_cq(&c->sq[tc].cq);
1311 }
1312
1313 static int mlx5e_open_sqs(struct mlx5e_channel *c,
1314                           struct mlx5e_channel_param *cparam)
1315 {
1316         int err;
1317         int tc;
1318
1319         for (tc = 0; tc < c->num_tc; tc++) {
1320                 err = mlx5e_open_sq(c, tc, &cparam->sq, &c->sq[tc]);
1321                 if (err)
1322                         goto err_close_sqs;
1323         }
1324
1325         return 0;
1326
1327 err_close_sqs:
1328         for (tc--; tc >= 0; tc--)
1329                 mlx5e_close_sq(&c->sq[tc]);
1330
1331         return err;
1332 }
1333
1334 static void mlx5e_close_sqs(struct mlx5e_channel *c)
1335 {
1336         int tc;
1337
1338         for (tc = 0; tc < c->num_tc; tc++)
1339                 mlx5e_close_sq(&c->sq[tc]);
1340 }
1341
1342 static void mlx5e_build_channeltc_to_txq_map(struct mlx5e_priv *priv, int ix)
1343 {
1344         int i;
1345
1346         for (i = 0; i < priv->profile->max_tc; i++)
1347                 priv->channeltc_to_txq_map[ix][i] =
1348                         ix + i * priv->params.num_channels;
1349 }
1350
1351 static int mlx5e_set_sq_maxrate(struct net_device *dev,
1352                                 struct mlx5e_sq *sq, u32 rate)
1353 {
1354         struct mlx5e_priv *priv = netdev_priv(dev);
1355         struct mlx5_core_dev *mdev = priv->mdev;
1356         u16 rl_index = 0;
1357         int err;
1358
1359         if (rate == sq->rate_limit)
1360                 /* nothing to do */
1361                 return 0;
1362
1363         if (sq->rate_limit)
1364                 /* remove current rl index to free space to next ones */
1365                 mlx5_rl_remove_rate(mdev, sq->rate_limit);
1366
1367         sq->rate_limit = 0;
1368
1369         if (rate) {
1370                 err = mlx5_rl_add_rate(mdev, rate, &rl_index);
1371                 if (err) {
1372                         netdev_err(dev, "Failed configuring rate %u: %d\n",
1373                                    rate, err);
1374                         return err;
1375                 }
1376         }
1377
1378         err = mlx5e_modify_sq(sq, MLX5_SQC_STATE_RDY,
1379                               MLX5_SQC_STATE_RDY, true, rl_index);
1380         if (err) {
1381                 netdev_err(dev, "Failed configuring rate %u: %d\n",
1382                            rate, err);
1383                 /* remove the rate from the table */
1384                 if (rate)
1385                         mlx5_rl_remove_rate(mdev, rate);
1386                 return err;
1387         }
1388
1389         sq->rate_limit = rate;
1390         return 0;
1391 }
1392
1393 static int mlx5e_set_tx_maxrate(struct net_device *dev, int index, u32 rate)
1394 {
1395         struct mlx5e_priv *priv = netdev_priv(dev);
1396         struct mlx5_core_dev *mdev = priv->mdev;
1397         struct mlx5e_sq *sq = priv->txq_to_sq_map[index];
1398         int err = 0;
1399
1400         if (!mlx5_rl_is_supported(mdev)) {
1401                 netdev_err(dev, "Rate limiting is not supported on this device\n");
1402                 return -EINVAL;
1403         }
1404
1405         /* rate is given in Mb/sec, HW config is in Kb/sec */
1406         rate = rate << 10;
1407
1408         /* Check whether rate in valid range, 0 is always valid */
1409         if (rate && !mlx5_rl_is_in_range(mdev, rate)) {
1410                 netdev_err(dev, "TX rate %u, is not in range\n", rate);
1411                 return -ERANGE;
1412         }
1413
1414         mutex_lock(&priv->state_lock);
1415         if (test_bit(MLX5E_STATE_OPENED, &priv->state))
1416                 err = mlx5e_set_sq_maxrate(dev, sq, rate);
1417         if (!err)
1418                 priv->tx_rates[index] = rate;
1419         mutex_unlock(&priv->state_lock);
1420
1421         return err;
1422 }
1423
1424 static int mlx5e_open_channel(struct mlx5e_priv *priv, int ix,
1425                               struct mlx5e_channel_param *cparam,
1426                               struct mlx5e_channel **cp)
1427 {
1428         struct mlx5e_cq_moder icosq_cq_moder = {0, 0};
1429         struct net_device *netdev = priv->netdev;
1430         struct mlx5e_cq_moder rx_cq_profile;
1431         int cpu = mlx5e_get_cpu(priv, ix);
1432         struct mlx5e_channel *c;
1433         struct mlx5e_sq *sq;
1434         int err;
1435         int i;
1436
1437         c = kzalloc_node(sizeof(*c), GFP_KERNEL, cpu_to_node(cpu));
1438         if (!c)
1439                 return -ENOMEM;
1440
1441         c->priv     = priv;
1442         c->ix       = ix;
1443         c->cpu      = cpu;
1444         c->pdev     = &priv->mdev->pdev->dev;
1445         c->netdev   = priv->netdev;
1446         c->mkey_be  = cpu_to_be32(priv->mdev->mlx5e_res.mkey.key);
1447         c->num_tc   = priv->params.num_tc;
1448         c->xdp      = !!priv->xdp_prog;
1449
1450         if (priv->params.rx_am_enabled)
1451                 rx_cq_profile = mlx5e_am_get_def_profile(priv->params.rx_cq_period_mode);
1452         else
1453                 rx_cq_profile = priv->params.rx_cq_moderation;
1454
1455         mlx5e_build_channeltc_to_txq_map(priv, ix);
1456
1457         netif_napi_add(netdev, &c->napi, mlx5e_napi_poll, 64);
1458
1459         err = mlx5e_open_cq(c, &cparam->icosq_cq, &c->icosq.cq, icosq_cq_moder);
1460         if (err)
1461                 goto err_napi_del;
1462
1463         err = mlx5e_open_tx_cqs(c, cparam);
1464         if (err)
1465                 goto err_close_icosq_cq;
1466
1467         err = mlx5e_open_cq(c, &cparam->rx_cq, &c->rq.cq,
1468                             rx_cq_profile);
1469         if (err)
1470                 goto err_close_tx_cqs;
1471
1472         /* XDP SQ CQ params are same as normal TXQ sq CQ params */
1473         err = c->xdp ? mlx5e_open_cq(c, &cparam->tx_cq, &c->xdp_sq.cq,
1474                                      priv->params.tx_cq_moderation) : 0;
1475         if (err)
1476                 goto err_close_rx_cq;
1477
1478         napi_enable(&c->napi);
1479
1480         err = mlx5e_open_sq(c, 0, &cparam->icosq, &c->icosq);
1481         if (err)
1482                 goto err_disable_napi;
1483
1484         err = mlx5e_open_sqs(c, cparam);
1485         if (err)
1486                 goto err_close_icosq;
1487
1488         for (i = 0; i < priv->params.num_tc; i++) {
1489                 u32 txq_ix = priv->channeltc_to_txq_map[ix][i];
1490
1491                 if (priv->tx_rates[txq_ix]) {
1492                         sq = priv->txq_to_sq_map[txq_ix];
1493                         mlx5e_set_sq_maxrate(priv->netdev, sq,
1494                                              priv->tx_rates[txq_ix]);
1495                 }
1496         }
1497
1498         err = c->xdp ? mlx5e_open_sq(c, 0, &cparam->xdp_sq, &c->xdp_sq) : 0;
1499         if (err)
1500                 goto err_close_sqs;
1501
1502         err = mlx5e_open_rq(c, &cparam->rq, &c->rq);
1503         if (err)
1504                 goto err_close_xdp_sq;
1505
1506         netif_set_xps_queue(netdev, get_cpu_mask(c->cpu), ix);
1507         *cp = c;
1508
1509         return 0;
1510 err_close_xdp_sq:
1511         if (c->xdp)
1512                 mlx5e_close_sq(&c->xdp_sq);
1513
1514 err_close_sqs:
1515         mlx5e_close_sqs(c);
1516
1517 err_close_icosq:
1518         mlx5e_close_sq(&c->icosq);
1519
1520 err_disable_napi:
1521         napi_disable(&c->napi);
1522         if (c->xdp)
1523                 mlx5e_close_cq(&c->xdp_sq.cq);
1524
1525 err_close_rx_cq:
1526         mlx5e_close_cq(&c->rq.cq);
1527
1528 err_close_tx_cqs:
1529         mlx5e_close_tx_cqs(c);
1530
1531 err_close_icosq_cq:
1532         mlx5e_close_cq(&c->icosq.cq);
1533
1534 err_napi_del:
1535         netif_napi_del(&c->napi);
1536         napi_hash_del(&c->napi);
1537         kfree(c);
1538
1539         return err;
1540 }
1541
1542 static void mlx5e_close_channel(struct mlx5e_channel *c)
1543 {
1544         mlx5e_close_rq(&c->rq);
1545         if (c->xdp)
1546                 mlx5e_close_sq(&c->xdp_sq);
1547         mlx5e_close_sqs(c);
1548         mlx5e_close_sq(&c->icosq);
1549         napi_disable(&c->napi);
1550         if (c->xdp)
1551                 mlx5e_close_cq(&c->xdp_sq.cq);
1552         mlx5e_close_cq(&c->rq.cq);
1553         mlx5e_close_tx_cqs(c);
1554         mlx5e_close_cq(&c->icosq.cq);
1555         netif_napi_del(&c->napi);
1556
1557         napi_hash_del(&c->napi);
1558         synchronize_rcu();
1559
1560         kfree(c);
1561 }
1562
1563 static void mlx5e_build_rq_param(struct mlx5e_priv *priv,
1564                                  struct mlx5e_rq_param *param)
1565 {
1566         void *rqc = param->rqc;
1567         void *wq = MLX5_ADDR_OF(rqc, rqc, wq);
1568
1569         switch (priv->params.rq_wq_type) {
1570         case MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ:
1571                 MLX5_SET(wq, wq, log_wqe_num_of_strides,
1572                          priv->params.mpwqe_log_num_strides - 9);
1573                 MLX5_SET(wq, wq, log_wqe_stride_size,
1574                          priv->params.mpwqe_log_stride_sz - 6);
1575                 MLX5_SET(wq, wq, wq_type, MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ);
1576                 break;
1577         default: /* MLX5_WQ_TYPE_LINKED_LIST */
1578                 MLX5_SET(wq, wq, wq_type, MLX5_WQ_TYPE_LINKED_LIST);
1579         }
1580
1581         MLX5_SET(wq, wq, end_padding_mode, MLX5_WQ_END_PAD_MODE_ALIGN);
1582         MLX5_SET(wq, wq, log_wq_stride,    ilog2(sizeof(struct mlx5e_rx_wqe)));
1583         MLX5_SET(wq, wq, log_wq_sz,        priv->params.log_rq_size);
1584         MLX5_SET(wq, wq, pd,               priv->mdev->mlx5e_res.pdn);
1585         MLX5_SET(rqc, rqc, counter_set_id, priv->q_counter);
1586
1587         param->wq.buf_numa_node = dev_to_node(&priv->mdev->pdev->dev);
1588         param->wq.linear = 1;
1589
1590         param->am_enabled = priv->params.rx_am_enabled;
1591 }
1592
1593 static void mlx5e_build_drop_rq_param(struct mlx5e_rq_param *param)
1594 {
1595         void *rqc = param->rqc;
1596         void *wq = MLX5_ADDR_OF(rqc, rqc, wq);
1597
1598         MLX5_SET(wq, wq, wq_type, MLX5_WQ_TYPE_LINKED_LIST);
1599         MLX5_SET(wq, wq, log_wq_stride,    ilog2(sizeof(struct mlx5e_rx_wqe)));
1600 }
1601
1602 static void mlx5e_build_sq_param_common(struct mlx5e_priv *priv,
1603                                         struct mlx5e_sq_param *param)
1604 {
1605         void *sqc = param->sqc;
1606         void *wq = MLX5_ADDR_OF(sqc, sqc, wq);
1607
1608         MLX5_SET(wq, wq, log_wq_stride, ilog2(MLX5_SEND_WQE_BB));
1609         MLX5_SET(wq, wq, pd,            priv->mdev->mlx5e_res.pdn);
1610
1611         param->wq.buf_numa_node = dev_to_node(&priv->mdev->pdev->dev);
1612 }
1613
1614 static void mlx5e_build_sq_param(struct mlx5e_priv *priv,
1615                                  struct mlx5e_sq_param *param)
1616 {
1617         void *sqc = param->sqc;
1618         void *wq = MLX5_ADDR_OF(sqc, sqc, wq);
1619
1620         mlx5e_build_sq_param_common(priv, param);
1621         MLX5_SET(wq, wq, log_wq_sz,     priv->params.log_sq_size);
1622
1623         param->max_inline = priv->params.tx_max_inline;
1624         param->min_inline_mode = priv->params.tx_min_inline_mode;
1625         param->type = MLX5E_SQ_TXQ;
1626 }
1627
1628 static void mlx5e_build_common_cq_param(struct mlx5e_priv *priv,
1629                                         struct mlx5e_cq_param *param)
1630 {
1631         void *cqc = param->cqc;
1632
1633         MLX5_SET(cqc, cqc, uar_page, priv->mdev->mlx5e_res.cq_uar.index);
1634 }
1635
1636 static void mlx5e_build_rx_cq_param(struct mlx5e_priv *priv,
1637                                     struct mlx5e_cq_param *param)
1638 {
1639         void *cqc = param->cqc;
1640         u8 log_cq_size;
1641
1642         switch (priv->params.rq_wq_type) {
1643         case MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ:
1644                 log_cq_size = priv->params.log_rq_size +
1645                         priv->params.mpwqe_log_num_strides;
1646                 break;
1647         default: /* MLX5_WQ_TYPE_LINKED_LIST */
1648                 log_cq_size = priv->params.log_rq_size;
1649         }
1650
1651         MLX5_SET(cqc, cqc, log_cq_size, log_cq_size);
1652         if (priv->params.rx_cqe_compress) {
1653                 MLX5_SET(cqc, cqc, mini_cqe_res_format, MLX5_CQE_FORMAT_CSUM);
1654                 MLX5_SET(cqc, cqc, cqe_comp_en, 1);
1655         }
1656
1657         mlx5e_build_common_cq_param(priv, param);
1658
1659         param->cq_period_mode = priv->params.rx_cq_period_mode;
1660 }
1661
1662 static void mlx5e_build_tx_cq_param(struct mlx5e_priv *priv,
1663                                     struct mlx5e_cq_param *param)
1664 {
1665         void *cqc = param->cqc;
1666
1667         MLX5_SET(cqc, cqc, log_cq_size, priv->params.log_sq_size);
1668
1669         mlx5e_build_common_cq_param(priv, param);
1670
1671         param->cq_period_mode = MLX5_CQ_PERIOD_MODE_START_FROM_EQE;
1672 }
1673
1674 static void mlx5e_build_ico_cq_param(struct mlx5e_priv *priv,
1675                                      struct mlx5e_cq_param *param,
1676                                      u8 log_wq_size)
1677 {
1678         void *cqc = param->cqc;
1679
1680         MLX5_SET(cqc, cqc, log_cq_size, log_wq_size);
1681
1682         mlx5e_build_common_cq_param(priv, param);
1683
1684         param->cq_period_mode = MLX5_CQ_PERIOD_MODE_START_FROM_EQE;
1685 }
1686
1687 static void mlx5e_build_icosq_param(struct mlx5e_priv *priv,
1688                                     struct mlx5e_sq_param *param,
1689                                     u8 log_wq_size)
1690 {
1691         void *sqc = param->sqc;
1692         void *wq = MLX5_ADDR_OF(sqc, sqc, wq);
1693
1694         mlx5e_build_sq_param_common(priv, param);
1695
1696         MLX5_SET(wq, wq, log_wq_sz, log_wq_size);
1697         MLX5_SET(sqc, sqc, reg_umr, MLX5_CAP_ETH(priv->mdev, reg_umr_sq));
1698
1699         param->type = MLX5E_SQ_ICO;
1700 }
1701
1702 static void mlx5e_build_xdpsq_param(struct mlx5e_priv *priv,
1703                                     struct mlx5e_sq_param *param)
1704 {
1705         void *sqc = param->sqc;
1706         void *wq = MLX5_ADDR_OF(sqc, sqc, wq);
1707
1708         mlx5e_build_sq_param_common(priv, param);
1709         MLX5_SET(wq, wq, log_wq_sz,     priv->params.log_sq_size);
1710
1711         param->max_inline = priv->params.tx_max_inline;
1712         /* FOR XDP SQs will support only L2 inline mode */
1713         param->min_inline_mode = MLX5_INLINE_MODE_NONE;
1714         param->type = MLX5E_SQ_XDP;
1715 }
1716
1717 static void mlx5e_build_channel_param(struct mlx5e_priv *priv, struct mlx5e_channel_param *cparam)
1718 {
1719         u8 icosq_log_wq_sz = MLX5E_PARAMS_MINIMUM_LOG_SQ_SIZE;
1720
1721         mlx5e_build_rq_param(priv, &cparam->rq);
1722         mlx5e_build_sq_param(priv, &cparam->sq);
1723         mlx5e_build_xdpsq_param(priv, &cparam->xdp_sq);
1724         mlx5e_build_icosq_param(priv, &cparam->icosq, icosq_log_wq_sz);
1725         mlx5e_build_rx_cq_param(priv, &cparam->rx_cq);
1726         mlx5e_build_tx_cq_param(priv, &cparam->tx_cq);
1727         mlx5e_build_ico_cq_param(priv, &cparam->icosq_cq, icosq_log_wq_sz);
1728 }
1729
1730 static int mlx5e_open_channels(struct mlx5e_priv *priv)
1731 {
1732         struct mlx5e_channel_param *cparam;
1733         int nch = priv->params.num_channels;
1734         int err = -ENOMEM;
1735         int i;
1736         int j;
1737
1738         priv->channel = kcalloc(nch, sizeof(struct mlx5e_channel *),
1739                                 GFP_KERNEL);
1740
1741         priv->txq_to_sq_map = kcalloc(nch * priv->params.num_tc,
1742                                       sizeof(struct mlx5e_sq *), GFP_KERNEL);
1743
1744         cparam = kzalloc(sizeof(struct mlx5e_channel_param), GFP_KERNEL);
1745
1746         if (!priv->channel || !priv->txq_to_sq_map || !cparam)
1747                 goto err_free_txq_to_sq_map;
1748
1749         mlx5e_build_channel_param(priv, cparam);
1750
1751         for (i = 0; i < nch; i++) {
1752                 err = mlx5e_open_channel(priv, i, cparam, &priv->channel[i]);
1753                 if (err)
1754                         goto err_close_channels;
1755         }
1756
1757         for (j = 0; j < nch; j++) {
1758                 err = mlx5e_wait_for_min_rx_wqes(&priv->channel[j]->rq);
1759                 if (err)
1760                         goto err_close_channels;
1761         }
1762
1763         /* FIXME: This is a W/A for tx timeout watch dog false alarm when
1764          * polling for inactive tx queues.
1765          */
1766         netif_tx_start_all_queues(priv->netdev);
1767
1768         kfree(cparam);
1769         return 0;
1770
1771 err_close_channels:
1772         for (i--; i >= 0; i--)
1773                 mlx5e_close_channel(priv->channel[i]);
1774
1775 err_free_txq_to_sq_map:
1776         kfree(priv->txq_to_sq_map);
1777         kfree(priv->channel);
1778         kfree(cparam);
1779
1780         return err;
1781 }
1782
1783 static void mlx5e_close_channels(struct mlx5e_priv *priv)
1784 {
1785         int i;
1786
1787         /* FIXME: This is a W/A only for tx timeout watch dog false alarm when
1788          * polling for inactive tx queues.
1789          */
1790         netif_tx_stop_all_queues(priv->netdev);
1791         netif_tx_disable(priv->netdev);
1792
1793         for (i = 0; i < priv->params.num_channels; i++)
1794                 mlx5e_close_channel(priv->channel[i]);
1795
1796         kfree(priv->txq_to_sq_map);
1797         kfree(priv->channel);
1798 }
1799
1800 static int mlx5e_rx_hash_fn(int hfunc)
1801 {
1802         return (hfunc == ETH_RSS_HASH_TOP) ?
1803                MLX5_RX_HASH_FN_TOEPLITZ :
1804                MLX5_RX_HASH_FN_INVERTED_XOR8;
1805 }
1806
1807 static int mlx5e_bits_invert(unsigned long a, int size)
1808 {
1809         int inv = 0;
1810         int i;
1811
1812         for (i = 0; i < size; i++)
1813                 inv |= (test_bit(size - i - 1, &a) ? 1 : 0) << i;
1814
1815         return inv;
1816 }
1817
1818 static void mlx5e_fill_indir_rqt_rqns(struct mlx5e_priv *priv, void *rqtc)
1819 {
1820         int i;
1821
1822         for (i = 0; i < MLX5E_INDIR_RQT_SIZE; i++) {
1823                 int ix = i;
1824                 u32 rqn;
1825
1826                 if (priv->params.rss_hfunc == ETH_RSS_HASH_XOR)
1827                         ix = mlx5e_bits_invert(i, MLX5E_LOG_INDIR_RQT_SIZE);
1828
1829                 ix = priv->params.indirection_rqt[ix];
1830                 rqn = test_bit(MLX5E_STATE_OPENED, &priv->state) ?
1831                                 priv->channel[ix]->rq.rqn :
1832                                 priv->drop_rq.rqn;
1833                 MLX5_SET(rqtc, rqtc, rq_num[i], rqn);
1834         }
1835 }
1836
1837 static void mlx5e_fill_direct_rqt_rqn(struct mlx5e_priv *priv, void *rqtc,
1838                                       int ix)
1839 {
1840         u32 rqn = test_bit(MLX5E_STATE_OPENED, &priv->state) ?
1841                         priv->channel[ix]->rq.rqn :
1842                         priv->drop_rq.rqn;
1843
1844         MLX5_SET(rqtc, rqtc, rq_num[0], rqn);
1845 }
1846
1847 static int mlx5e_create_rqt(struct mlx5e_priv *priv, int sz,
1848                             int ix, struct mlx5e_rqt *rqt)
1849 {
1850         struct mlx5_core_dev *mdev = priv->mdev;
1851         void *rqtc;
1852         int inlen;
1853         int err;
1854         u32 *in;
1855
1856         inlen = MLX5_ST_SZ_BYTES(create_rqt_in) + sizeof(u32) * sz;
1857         in = mlx5_vzalloc(inlen);
1858         if (!in)
1859                 return -ENOMEM;
1860
1861         rqtc = MLX5_ADDR_OF(create_rqt_in, in, rqt_context);
1862
1863         MLX5_SET(rqtc, rqtc, rqt_actual_size, sz);
1864         MLX5_SET(rqtc, rqtc, rqt_max_size, sz);
1865
1866         if (sz > 1) /* RSS */
1867                 mlx5e_fill_indir_rqt_rqns(priv, rqtc);
1868         else
1869                 mlx5e_fill_direct_rqt_rqn(priv, rqtc, ix);
1870
1871         err = mlx5_core_create_rqt(mdev, in, inlen, &rqt->rqtn);
1872         if (!err)
1873                 rqt->enabled = true;
1874
1875         kvfree(in);
1876         return err;
1877 }
1878
1879 void mlx5e_destroy_rqt(struct mlx5e_priv *priv, struct mlx5e_rqt *rqt)
1880 {
1881         rqt->enabled = false;
1882         mlx5_core_destroy_rqt(priv->mdev, rqt->rqtn);
1883 }
1884
1885 static int mlx5e_create_indirect_rqts(struct mlx5e_priv *priv)
1886 {
1887         struct mlx5e_rqt *rqt = &priv->indir_rqt;
1888
1889         return mlx5e_create_rqt(priv, MLX5E_INDIR_RQT_SIZE, 0, rqt);
1890 }
1891
1892 int mlx5e_create_direct_rqts(struct mlx5e_priv *priv)
1893 {
1894         struct mlx5e_rqt *rqt;
1895         int err;
1896         int ix;
1897
1898         for (ix = 0; ix < priv->profile->max_nch(priv->mdev); ix++) {
1899                 rqt = &priv->direct_tir[ix].rqt;
1900                 err = mlx5e_create_rqt(priv, 1 /*size */, ix, rqt);
1901                 if (err)
1902                         goto err_destroy_rqts;
1903         }
1904
1905         return 0;
1906
1907 err_destroy_rqts:
1908         for (ix--; ix >= 0; ix--)
1909                 mlx5e_destroy_rqt(priv, &priv->direct_tir[ix].rqt);
1910
1911         return err;
1912 }
1913
1914 int mlx5e_redirect_rqt(struct mlx5e_priv *priv, u32 rqtn, int sz, int ix)
1915 {
1916         struct mlx5_core_dev *mdev = priv->mdev;
1917         void *rqtc;
1918         int inlen;
1919         u32 *in;
1920         int err;
1921
1922         inlen = MLX5_ST_SZ_BYTES(modify_rqt_in) + sizeof(u32) * sz;
1923         in = mlx5_vzalloc(inlen);
1924         if (!in)
1925                 return -ENOMEM;
1926
1927         rqtc = MLX5_ADDR_OF(modify_rqt_in, in, ctx);
1928
1929         MLX5_SET(rqtc, rqtc, rqt_actual_size, sz);
1930         if (sz > 1) /* RSS */
1931                 mlx5e_fill_indir_rqt_rqns(priv, rqtc);
1932         else
1933                 mlx5e_fill_direct_rqt_rqn(priv, rqtc, ix);
1934
1935         MLX5_SET(modify_rqt_in, in, bitmask.rqn_list, 1);
1936
1937         err = mlx5_core_modify_rqt(mdev, rqtn, in, inlen);
1938
1939         kvfree(in);
1940
1941         return err;
1942 }
1943
1944 static void mlx5e_redirect_rqts(struct mlx5e_priv *priv)
1945 {
1946         u32 rqtn;
1947         int ix;
1948
1949         if (priv->indir_rqt.enabled) {
1950                 rqtn = priv->indir_rqt.rqtn;
1951                 mlx5e_redirect_rqt(priv, rqtn, MLX5E_INDIR_RQT_SIZE, 0);
1952         }
1953
1954         for (ix = 0; ix < priv->params.num_channels; ix++) {
1955                 if (!priv->direct_tir[ix].rqt.enabled)
1956                         continue;
1957                 rqtn = priv->direct_tir[ix].rqt.rqtn;
1958                 mlx5e_redirect_rqt(priv, rqtn, 1, ix);
1959         }
1960 }
1961
1962 static void mlx5e_build_tir_ctx_lro(void *tirc, struct mlx5e_priv *priv)
1963 {
1964         if (!priv->params.lro_en)
1965                 return;
1966
1967 #define ROUGH_MAX_L2_L3_HDR_SZ 256
1968
1969         MLX5_SET(tirc, tirc, lro_enable_mask,
1970                  MLX5_TIRC_LRO_ENABLE_MASK_IPV4_LRO |
1971                  MLX5_TIRC_LRO_ENABLE_MASK_IPV6_LRO);
1972         MLX5_SET(tirc, tirc, lro_max_ip_payload_size,
1973                  (priv->params.lro_wqe_sz -
1974                   ROUGH_MAX_L2_L3_HDR_SZ) >> 8);
1975         MLX5_SET(tirc, tirc, lro_timeout_period_usecs, priv->params.lro_timeout);
1976 }
1977
1978 void mlx5e_build_tir_ctx_hash(void *tirc, struct mlx5e_priv *priv)
1979 {
1980         MLX5_SET(tirc, tirc, rx_hash_fn,
1981                  mlx5e_rx_hash_fn(priv->params.rss_hfunc));
1982         if (priv->params.rss_hfunc == ETH_RSS_HASH_TOP) {
1983                 void *rss_key = MLX5_ADDR_OF(tirc, tirc,
1984                                              rx_hash_toeplitz_key);
1985                 size_t len = MLX5_FLD_SZ_BYTES(tirc,
1986                                                rx_hash_toeplitz_key);
1987
1988                 MLX5_SET(tirc, tirc, rx_hash_symmetric, 1);
1989                 memcpy(rss_key, priv->params.toeplitz_hash_key, len);
1990         }
1991 }
1992
1993 static int mlx5e_modify_tirs_lro(struct mlx5e_priv *priv)
1994 {
1995         struct mlx5_core_dev *mdev = priv->mdev;
1996
1997         void *in;
1998         void *tirc;
1999         int inlen;
2000         int err;
2001         int tt;
2002         int ix;
2003
2004         inlen = MLX5_ST_SZ_BYTES(modify_tir_in);
2005         in = mlx5_vzalloc(inlen);
2006         if (!in)
2007                 return -ENOMEM;
2008
2009         MLX5_SET(modify_tir_in, in, bitmask.lro, 1);
2010         tirc = MLX5_ADDR_OF(modify_tir_in, in, ctx);
2011
2012         mlx5e_build_tir_ctx_lro(tirc, priv);
2013
2014         for (tt = 0; tt < MLX5E_NUM_INDIR_TIRS; tt++) {
2015                 err = mlx5_core_modify_tir(mdev, priv->indir_tir[tt].tirn, in,
2016                                            inlen);
2017                 if (err)
2018                         goto free_in;
2019         }
2020
2021         for (ix = 0; ix < priv->profile->max_nch(priv->mdev); ix++) {
2022                 err = mlx5_core_modify_tir(mdev, priv->direct_tir[ix].tirn,
2023                                            in, inlen);
2024                 if (err)
2025                         goto free_in;
2026         }
2027
2028 free_in:
2029         kvfree(in);
2030
2031         return err;
2032 }
2033
2034 static int mlx5e_set_mtu(struct mlx5e_priv *priv, u16 mtu)
2035 {
2036         struct mlx5_core_dev *mdev = priv->mdev;
2037         u16 hw_mtu = MLX5E_SW2HW_MTU(mtu);
2038         int err;
2039
2040         err = mlx5_set_port_mtu(mdev, hw_mtu, 1);
2041         if (err)
2042                 return err;
2043
2044         /* Update vport context MTU */
2045         mlx5_modify_nic_vport_mtu(mdev, hw_mtu);
2046         return 0;
2047 }
2048
2049 static void mlx5e_query_mtu(struct mlx5e_priv *priv, u16 *mtu)
2050 {
2051         struct mlx5_core_dev *mdev = priv->mdev;
2052         u16 hw_mtu = 0;
2053         int err;
2054
2055         err = mlx5_query_nic_vport_mtu(mdev, &hw_mtu);
2056         if (err || !hw_mtu) /* fallback to port oper mtu */
2057                 mlx5_query_port_oper_mtu(mdev, &hw_mtu, 1);
2058
2059         *mtu = MLX5E_HW2SW_MTU(hw_mtu);
2060 }
2061
2062 static int mlx5e_set_dev_port_mtu(struct net_device *netdev)
2063 {
2064         struct mlx5e_priv *priv = netdev_priv(netdev);
2065         u16 mtu;
2066         int err;
2067
2068         err = mlx5e_set_mtu(priv, netdev->mtu);
2069         if (err)
2070                 return err;
2071
2072         mlx5e_query_mtu(priv, &mtu);
2073         if (mtu != netdev->mtu)
2074                 netdev_warn(netdev, "%s: VPort MTU %d is different than netdev mtu %d\n",
2075                             __func__, mtu, netdev->mtu);
2076
2077         netdev->mtu = mtu;
2078         return 0;
2079 }
2080
2081 static void mlx5e_netdev_set_tcs(struct net_device *netdev)
2082 {
2083         struct mlx5e_priv *priv = netdev_priv(netdev);
2084         int nch = priv->params.num_channels;
2085         int ntc = priv->params.num_tc;
2086         int tc;
2087
2088         netdev_reset_tc(netdev);
2089
2090         if (ntc == 1)
2091                 return;
2092
2093         netdev_set_num_tc(netdev, ntc);
2094
2095         /* Map netdev TCs to offset 0
2096          * We have our own UP to TXQ mapping for QoS
2097          */
2098         for (tc = 0; tc < ntc; tc++)
2099                 netdev_set_tc_queue(netdev, tc, nch, 0);
2100 }
2101
2102 int mlx5e_open_locked(struct net_device *netdev)
2103 {
2104         struct mlx5e_priv *priv = netdev_priv(netdev);
2105         struct mlx5_core_dev *mdev = priv->mdev;
2106         int num_txqs;
2107         int err;
2108
2109         set_bit(MLX5E_STATE_OPENED, &priv->state);
2110
2111         mlx5e_netdev_set_tcs(netdev);
2112
2113         num_txqs = priv->params.num_channels * priv->params.num_tc;
2114         netif_set_real_num_tx_queues(netdev, num_txqs);
2115         netif_set_real_num_rx_queues(netdev, priv->params.num_channels);
2116
2117         err = mlx5e_open_channels(priv);
2118         if (err) {
2119                 netdev_err(netdev, "%s: mlx5e_open_channels failed, %d\n",
2120                            __func__, err);
2121                 goto err_clear_state_opened_flag;
2122         }
2123
2124         err = mlx5e_refresh_tirs_self_loopback_enable(priv->mdev);
2125         if (err) {
2126                 netdev_err(netdev, "%s: mlx5e_refresh_tirs_self_loopback_enable failed, %d\n",
2127                            __func__, err);
2128                 goto err_close_channels;
2129         }
2130
2131         mlx5e_redirect_rqts(priv);
2132         mlx5e_update_carrier(priv);
2133         mlx5e_timestamp_init(priv);
2134 #ifdef CONFIG_RFS_ACCEL
2135         priv->netdev->rx_cpu_rmap = priv->mdev->rmap;
2136 #endif
2137         if (priv->profile->update_stats)
2138                 queue_delayed_work(priv->wq, &priv->update_stats_work, 0);
2139
2140         if (MLX5_CAP_GEN(mdev, vport_group_manager)) {
2141                 err = mlx5e_add_sqs_fwd_rules(priv);
2142                 if (err)
2143                         goto err_close_channels;
2144         }
2145         return 0;
2146
2147 err_close_channels:
2148         mlx5e_close_channels(priv);
2149 err_clear_state_opened_flag:
2150         clear_bit(MLX5E_STATE_OPENED, &priv->state);
2151         return err;
2152 }
2153
2154 int mlx5e_open(struct net_device *netdev)
2155 {
2156         struct mlx5e_priv *priv = netdev_priv(netdev);
2157         int err;
2158
2159         mutex_lock(&priv->state_lock);
2160         err = mlx5e_open_locked(netdev);
2161         mutex_unlock(&priv->state_lock);
2162
2163         return err;
2164 }
2165
2166 int mlx5e_close_locked(struct net_device *netdev)
2167 {
2168         struct mlx5e_priv *priv = netdev_priv(netdev);
2169         struct mlx5_core_dev *mdev = priv->mdev;
2170
2171         /* May already be CLOSED in case a previous configuration operation
2172          * (e.g RX/TX queue size change) that involves close&open failed.
2173          */
2174         if (!test_bit(MLX5E_STATE_OPENED, &priv->state))
2175                 return 0;
2176
2177         clear_bit(MLX5E_STATE_OPENED, &priv->state);
2178
2179         if (MLX5_CAP_GEN(mdev, vport_group_manager))
2180                 mlx5e_remove_sqs_fwd_rules(priv);
2181
2182         mlx5e_timestamp_cleanup(priv);
2183         netif_carrier_off(priv->netdev);
2184         mlx5e_redirect_rqts(priv);
2185         mlx5e_close_channels(priv);
2186
2187         return 0;
2188 }
2189
2190 int mlx5e_close(struct net_device *netdev)
2191 {
2192         struct mlx5e_priv *priv = netdev_priv(netdev);
2193         int err;
2194
2195         if (!netif_device_present(netdev))
2196                 return -ENODEV;
2197
2198         mutex_lock(&priv->state_lock);
2199         err = mlx5e_close_locked(netdev);
2200         mutex_unlock(&priv->state_lock);
2201
2202         return err;
2203 }
2204
2205 static int mlx5e_create_drop_rq(struct mlx5e_priv *priv,
2206                                 struct mlx5e_rq *rq,
2207                                 struct mlx5e_rq_param *param)
2208 {
2209         struct mlx5_core_dev *mdev = priv->mdev;
2210         void *rqc = param->rqc;
2211         void *rqc_wq = MLX5_ADDR_OF(rqc, rqc, wq);
2212         int err;
2213
2214         param->wq.db_numa_node = param->wq.buf_numa_node;
2215
2216         err = mlx5_wq_ll_create(mdev, &param->wq, rqc_wq, &rq->wq,
2217                                 &rq->wq_ctrl);
2218         if (err)
2219                 return err;
2220
2221         rq->priv = priv;
2222
2223         return 0;
2224 }
2225
2226 static int mlx5e_create_drop_cq(struct mlx5e_priv *priv,
2227                                 struct mlx5e_cq *cq,
2228                                 struct mlx5e_cq_param *param)
2229 {
2230         struct mlx5_core_dev *mdev = priv->mdev;
2231         struct mlx5_core_cq *mcq = &cq->mcq;
2232         int eqn_not_used;
2233         unsigned int irqn;
2234         int err;
2235
2236         err = mlx5_cqwq_create(mdev, &param->wq, param->cqc, &cq->wq,
2237                                &cq->wq_ctrl);
2238         if (err)
2239                 return err;
2240
2241         mlx5_vector2eqn(mdev, param->eq_ix, &eqn_not_used, &irqn);
2242
2243         mcq->cqe_sz     = 64;
2244         mcq->set_ci_db  = cq->wq_ctrl.db.db;
2245         mcq->arm_db     = cq->wq_ctrl.db.db + 1;
2246         *mcq->set_ci_db = 0;
2247         *mcq->arm_db    = 0;
2248         mcq->vector     = param->eq_ix;
2249         mcq->comp       = mlx5e_completion_event;
2250         mcq->event      = mlx5e_cq_error_event;
2251         mcq->irqn       = irqn;
2252         mcq->uar        = &mdev->mlx5e_res.cq_uar;
2253
2254         cq->priv = priv;
2255
2256         return 0;
2257 }
2258
2259 static int mlx5e_open_drop_rq(struct mlx5e_priv *priv)
2260 {
2261         struct mlx5e_cq_param cq_param;
2262         struct mlx5e_rq_param rq_param;
2263         struct mlx5e_rq *rq = &priv->drop_rq;
2264         struct mlx5e_cq *cq = &priv->drop_rq.cq;
2265         int err;
2266
2267         memset(&cq_param, 0, sizeof(cq_param));
2268         memset(&rq_param, 0, sizeof(rq_param));
2269         mlx5e_build_drop_rq_param(&rq_param);
2270
2271         err = mlx5e_create_drop_cq(priv, cq, &cq_param);
2272         if (err)
2273                 return err;
2274
2275         err = mlx5e_enable_cq(cq, &cq_param);
2276         if (err)
2277                 goto err_destroy_cq;
2278
2279         err = mlx5e_create_drop_rq(priv, rq, &rq_param);
2280         if (err)
2281                 goto err_disable_cq;
2282
2283         err = mlx5e_enable_rq(rq, &rq_param);
2284         if (err)
2285                 goto err_destroy_rq;
2286
2287         return 0;
2288
2289 err_destroy_rq:
2290         mlx5e_destroy_rq(&priv->drop_rq);
2291
2292 err_disable_cq:
2293         mlx5e_disable_cq(&priv->drop_rq.cq);
2294
2295 err_destroy_cq:
2296         mlx5e_destroy_cq(&priv->drop_rq.cq);
2297
2298         return err;
2299 }
2300
2301 static void mlx5e_close_drop_rq(struct mlx5e_priv *priv)
2302 {
2303         mlx5e_disable_rq(&priv->drop_rq);
2304         mlx5e_destroy_rq(&priv->drop_rq);
2305         mlx5e_disable_cq(&priv->drop_rq.cq);
2306         mlx5e_destroy_cq(&priv->drop_rq.cq);
2307 }
2308
2309 static int mlx5e_create_tis(struct mlx5e_priv *priv, int tc)
2310 {
2311         struct mlx5_core_dev *mdev = priv->mdev;
2312         u32 in[MLX5_ST_SZ_DW(create_tis_in)] = {0};
2313         void *tisc = MLX5_ADDR_OF(create_tis_in, in, ctx);
2314
2315         MLX5_SET(tisc, tisc, prio, tc << 1);
2316         MLX5_SET(tisc, tisc, transport_domain, mdev->mlx5e_res.td.tdn);
2317
2318         if (mlx5_lag_is_lacp_owner(mdev))
2319                 MLX5_SET(tisc, tisc, strict_lag_tx_port_affinity, 1);
2320
2321         return mlx5_core_create_tis(mdev, in, sizeof(in), &priv->tisn[tc]);
2322 }
2323
2324 static void mlx5e_destroy_tis(struct mlx5e_priv *priv, int tc)
2325 {
2326         mlx5_core_destroy_tis(priv->mdev, priv->tisn[tc]);
2327 }
2328
2329 int mlx5e_create_tises(struct mlx5e_priv *priv)
2330 {
2331         int err;
2332         int tc;
2333
2334         for (tc = 0; tc < priv->profile->max_tc; tc++) {
2335                 err = mlx5e_create_tis(priv, tc);
2336                 if (err)
2337                         goto err_close_tises;
2338         }
2339
2340         return 0;
2341
2342 err_close_tises:
2343         for (tc--; tc >= 0; tc--)
2344                 mlx5e_destroy_tis(priv, tc);
2345
2346         return err;
2347 }
2348
2349 void mlx5e_cleanup_nic_tx(struct mlx5e_priv *priv)
2350 {
2351         int tc;
2352
2353         for (tc = 0; tc < priv->profile->max_tc; tc++)
2354                 mlx5e_destroy_tis(priv, tc);
2355 }
2356
2357 static void mlx5e_build_indir_tir_ctx(struct mlx5e_priv *priv, u32 *tirc,
2358                                       enum mlx5e_traffic_types tt)
2359 {
2360         void *hfso = MLX5_ADDR_OF(tirc, tirc, rx_hash_field_selector_outer);
2361
2362         MLX5_SET(tirc, tirc, transport_domain, priv->mdev->mlx5e_res.td.tdn);
2363
2364 #define MLX5_HASH_IP            (MLX5_HASH_FIELD_SEL_SRC_IP   |\
2365                                  MLX5_HASH_FIELD_SEL_DST_IP)
2366
2367 #define MLX5_HASH_IP_L4PORTS    (MLX5_HASH_FIELD_SEL_SRC_IP   |\
2368                                  MLX5_HASH_FIELD_SEL_DST_IP   |\
2369                                  MLX5_HASH_FIELD_SEL_L4_SPORT |\
2370                                  MLX5_HASH_FIELD_SEL_L4_DPORT)
2371
2372 #define MLX5_HASH_IP_IPSEC_SPI  (MLX5_HASH_FIELD_SEL_SRC_IP   |\
2373                                  MLX5_HASH_FIELD_SEL_DST_IP   |\
2374                                  MLX5_HASH_FIELD_SEL_IPSEC_SPI)
2375
2376         mlx5e_build_tir_ctx_lro(tirc, priv);
2377
2378         MLX5_SET(tirc, tirc, disp_type, MLX5_TIRC_DISP_TYPE_INDIRECT);
2379         MLX5_SET(tirc, tirc, indirect_table, priv->indir_rqt.rqtn);
2380         mlx5e_build_tir_ctx_hash(tirc, priv);
2381
2382         switch (tt) {
2383         case MLX5E_TT_IPV4_TCP:
2384                 MLX5_SET(rx_hash_field_select, hfso, l3_prot_type,
2385                          MLX5_L3_PROT_TYPE_IPV4);
2386                 MLX5_SET(rx_hash_field_select, hfso, l4_prot_type,
2387                          MLX5_L4_PROT_TYPE_TCP);
2388                 MLX5_SET(rx_hash_field_select, hfso, selected_fields,
2389                          MLX5_HASH_IP_L4PORTS);
2390                 break;
2391
2392         case MLX5E_TT_IPV6_TCP:
2393                 MLX5_SET(rx_hash_field_select, hfso, l3_prot_type,
2394                          MLX5_L3_PROT_TYPE_IPV6);
2395                 MLX5_SET(rx_hash_field_select, hfso, l4_prot_type,
2396                          MLX5_L4_PROT_TYPE_TCP);
2397                 MLX5_SET(rx_hash_field_select, hfso, selected_fields,
2398                          MLX5_HASH_IP_L4PORTS);
2399                 break;
2400
2401         case MLX5E_TT_IPV4_UDP:
2402                 MLX5_SET(rx_hash_field_select, hfso, l3_prot_type,
2403                          MLX5_L3_PROT_TYPE_IPV4);
2404                 MLX5_SET(rx_hash_field_select, hfso, l4_prot_type,
2405                          MLX5_L4_PROT_TYPE_UDP);
2406                 MLX5_SET(rx_hash_field_select, hfso, selected_fields,
2407                          MLX5_HASH_IP_L4PORTS);
2408                 break;
2409
2410         case MLX5E_TT_IPV6_UDP:
2411                 MLX5_SET(rx_hash_field_select, hfso, l3_prot_type,
2412                          MLX5_L3_PROT_TYPE_IPV6);
2413                 MLX5_SET(rx_hash_field_select, hfso, l4_prot_type,
2414                          MLX5_L4_PROT_TYPE_UDP);
2415                 MLX5_SET(rx_hash_field_select, hfso, selected_fields,
2416                          MLX5_HASH_IP_L4PORTS);
2417                 break;
2418
2419         case MLX5E_TT_IPV4_IPSEC_AH:
2420                 MLX5_SET(rx_hash_field_select, hfso, l3_prot_type,
2421                          MLX5_L3_PROT_TYPE_IPV4);
2422                 MLX5_SET(rx_hash_field_select, hfso, selected_fields,
2423                          MLX5_HASH_IP_IPSEC_SPI);
2424                 break;
2425
2426         case MLX5E_TT_IPV6_IPSEC_AH:
2427                 MLX5_SET(rx_hash_field_select, hfso, l3_prot_type,
2428                          MLX5_L3_PROT_TYPE_IPV6);
2429                 MLX5_SET(rx_hash_field_select, hfso, selected_fields,
2430                          MLX5_HASH_IP_IPSEC_SPI);
2431                 break;
2432
2433         case MLX5E_TT_IPV4_IPSEC_ESP:
2434                 MLX5_SET(rx_hash_field_select, hfso, l3_prot_type,
2435                          MLX5_L3_PROT_TYPE_IPV4);
2436                 MLX5_SET(rx_hash_field_select, hfso, selected_fields,
2437                          MLX5_HASH_IP_IPSEC_SPI);
2438                 break;
2439
2440         case MLX5E_TT_IPV6_IPSEC_ESP:
2441                 MLX5_SET(rx_hash_field_select, hfso, l3_prot_type,
2442                          MLX5_L3_PROT_TYPE_IPV6);
2443                 MLX5_SET(rx_hash_field_select, hfso, selected_fields,
2444                          MLX5_HASH_IP_IPSEC_SPI);
2445                 break;
2446
2447         case MLX5E_TT_IPV4:
2448                 MLX5_SET(rx_hash_field_select, hfso, l3_prot_type,
2449                          MLX5_L3_PROT_TYPE_IPV4);
2450                 MLX5_SET(rx_hash_field_select, hfso, selected_fields,
2451                          MLX5_HASH_IP);
2452                 break;
2453
2454         case MLX5E_TT_IPV6:
2455                 MLX5_SET(rx_hash_field_select, hfso, l3_prot_type,
2456                          MLX5_L3_PROT_TYPE_IPV6);
2457                 MLX5_SET(rx_hash_field_select, hfso, selected_fields,
2458                          MLX5_HASH_IP);
2459                 break;
2460         default:
2461                 WARN_ONCE(true,
2462                           "mlx5e_build_indir_tir_ctx: bad traffic type!\n");
2463         }
2464 }
2465
2466 static void mlx5e_build_direct_tir_ctx(struct mlx5e_priv *priv, u32 *tirc,
2467                                        u32 rqtn)
2468 {
2469         MLX5_SET(tirc, tirc, transport_domain, priv->mdev->mlx5e_res.td.tdn);
2470
2471         mlx5e_build_tir_ctx_lro(tirc, priv);
2472
2473         MLX5_SET(tirc, tirc, disp_type, MLX5_TIRC_DISP_TYPE_INDIRECT);
2474         MLX5_SET(tirc, tirc, indirect_table, rqtn);
2475         MLX5_SET(tirc, tirc, rx_hash_fn, MLX5_RX_HASH_FN_INVERTED_XOR8);
2476 }
2477
2478 static int mlx5e_create_indirect_tirs(struct mlx5e_priv *priv)
2479 {
2480         struct mlx5e_tir *tir;
2481         void *tirc;
2482         int inlen;
2483         int err;
2484         u32 *in;
2485         int tt;
2486
2487         inlen = MLX5_ST_SZ_BYTES(create_tir_in);
2488         in = mlx5_vzalloc(inlen);
2489         if (!in)
2490                 return -ENOMEM;
2491
2492         for (tt = 0; tt < MLX5E_NUM_INDIR_TIRS; tt++) {
2493                 memset(in, 0, inlen);
2494                 tir = &priv->indir_tir[tt];
2495                 tirc = MLX5_ADDR_OF(create_tir_in, in, ctx);
2496                 mlx5e_build_indir_tir_ctx(priv, tirc, tt);
2497                 err = mlx5e_create_tir(priv->mdev, tir, in, inlen);
2498                 if (err)
2499                         goto err_destroy_tirs;
2500         }
2501
2502         kvfree(in);
2503
2504         return 0;
2505
2506 err_destroy_tirs:
2507         for (tt--; tt >= 0; tt--)
2508                 mlx5e_destroy_tir(priv->mdev, &priv->indir_tir[tt]);
2509
2510         kvfree(in);
2511
2512         return err;
2513 }
2514
2515 int mlx5e_create_direct_tirs(struct mlx5e_priv *priv)
2516 {
2517         int nch = priv->profile->max_nch(priv->mdev);
2518         struct mlx5e_tir *tir;
2519         void *tirc;
2520         int inlen;
2521         int err;
2522         u32 *in;
2523         int ix;
2524
2525         inlen = MLX5_ST_SZ_BYTES(create_tir_in);
2526         in = mlx5_vzalloc(inlen);
2527         if (!in)
2528                 return -ENOMEM;
2529
2530         for (ix = 0; ix < nch; ix++) {
2531                 memset(in, 0, inlen);
2532                 tir = &priv->direct_tir[ix];
2533                 tirc = MLX5_ADDR_OF(create_tir_in, in, ctx);
2534                 mlx5e_build_direct_tir_ctx(priv, tirc,
2535                                            priv->direct_tir[ix].rqt.rqtn);
2536                 err = mlx5e_create_tir(priv->mdev, tir, in, inlen);
2537                 if (err)
2538                         goto err_destroy_ch_tirs;
2539         }
2540
2541         kvfree(in);
2542
2543         return 0;
2544
2545 err_destroy_ch_tirs:
2546         for (ix--; ix >= 0; ix--)
2547                 mlx5e_destroy_tir(priv->mdev, &priv->direct_tir[ix]);
2548
2549         kvfree(in);
2550
2551         return err;
2552 }
2553
2554 static void mlx5e_destroy_indirect_tirs(struct mlx5e_priv *priv)
2555 {
2556         int i;
2557
2558         for (i = 0; i < MLX5E_NUM_INDIR_TIRS; i++)
2559                 mlx5e_destroy_tir(priv->mdev, &priv->indir_tir[i]);
2560 }
2561
2562 void mlx5e_destroy_direct_tirs(struct mlx5e_priv *priv)
2563 {
2564         int nch = priv->profile->max_nch(priv->mdev);
2565         int i;
2566
2567         for (i = 0; i < nch; i++)
2568                 mlx5e_destroy_tir(priv->mdev, &priv->direct_tir[i]);
2569 }
2570
2571 int mlx5e_modify_rqs_vsd(struct mlx5e_priv *priv, bool vsd)
2572 {
2573         int err = 0;
2574         int i;
2575
2576         if (!test_bit(MLX5E_STATE_OPENED, &priv->state))
2577                 return 0;
2578
2579         for (i = 0; i < priv->params.num_channels; i++) {
2580                 err = mlx5e_modify_rq_vsd(&priv->channel[i]->rq, vsd);
2581                 if (err)
2582                         return err;
2583         }
2584
2585         return 0;
2586 }
2587
2588 static int mlx5e_setup_tc(struct net_device *netdev, u8 tc)
2589 {
2590         struct mlx5e_priv *priv = netdev_priv(netdev);
2591         bool was_opened;
2592         int err = 0;
2593
2594         if (tc && tc != MLX5E_MAX_NUM_TC)
2595                 return -EINVAL;
2596
2597         mutex_lock(&priv->state_lock);
2598
2599         was_opened = test_bit(MLX5E_STATE_OPENED, &priv->state);
2600         if (was_opened)
2601                 mlx5e_close_locked(priv->netdev);
2602
2603         priv->params.num_tc = tc ? tc : 1;
2604
2605         if (was_opened)
2606                 err = mlx5e_open_locked(priv->netdev);
2607
2608         mutex_unlock(&priv->state_lock);
2609
2610         return err;
2611 }
2612
2613 static int mlx5e_ndo_setup_tc(struct net_device *dev, u32 handle,
2614                               __be16 proto, struct tc_to_netdev *tc)
2615 {
2616         struct mlx5e_priv *priv = netdev_priv(dev);
2617
2618         if (TC_H_MAJ(handle) != TC_H_MAJ(TC_H_INGRESS))
2619                 goto mqprio;
2620
2621         switch (tc->type) {
2622         case TC_SETUP_CLSFLOWER:
2623                 switch (tc->cls_flower->command) {
2624                 case TC_CLSFLOWER_REPLACE:
2625                         return mlx5e_configure_flower(priv, proto, tc->cls_flower);
2626                 case TC_CLSFLOWER_DESTROY:
2627                         return mlx5e_delete_flower(priv, tc->cls_flower);
2628                 case TC_CLSFLOWER_STATS:
2629                         return mlx5e_stats_flower(priv, tc->cls_flower);
2630                 }
2631         default:
2632                 return -EOPNOTSUPP;
2633         }
2634
2635 mqprio:
2636         if (tc->type != TC_SETUP_MQPRIO)
2637                 return -EINVAL;
2638
2639         return mlx5e_setup_tc(dev, tc->tc);
2640 }
2641
2642 struct rtnl_link_stats64 *
2643 mlx5e_get_stats(struct net_device *dev, struct rtnl_link_stats64 *stats)
2644 {
2645         struct mlx5e_priv *priv = netdev_priv(dev);
2646         struct mlx5e_sw_stats *sstats = &priv->stats.sw;
2647         struct mlx5e_vport_stats *vstats = &priv->stats.vport;
2648         struct mlx5e_pport_stats *pstats = &priv->stats.pport;
2649
2650         stats->rx_packets = sstats->rx_packets;
2651         stats->rx_bytes   = sstats->rx_bytes;
2652         stats->tx_packets = sstats->tx_packets;
2653         stats->tx_bytes   = sstats->tx_bytes;
2654
2655         stats->rx_dropped = priv->stats.qcnt.rx_out_of_buffer;
2656         stats->tx_dropped = sstats->tx_queue_dropped;
2657
2658         stats->rx_length_errors =
2659                 PPORT_802_3_GET(pstats, a_in_range_length_errors) +
2660                 PPORT_802_3_GET(pstats, a_out_of_range_length_field) +
2661                 PPORT_802_3_GET(pstats, a_frame_too_long_errors);
2662         stats->rx_crc_errors =
2663                 PPORT_802_3_GET(pstats, a_frame_check_sequence_errors);
2664         stats->rx_frame_errors = PPORT_802_3_GET(pstats, a_alignment_errors);
2665         stats->tx_aborted_errors = PPORT_2863_GET(pstats, if_out_discards);
2666         stats->tx_carrier_errors =
2667                 PPORT_802_3_GET(pstats, a_symbol_error_during_carrier);
2668         stats->rx_errors = stats->rx_length_errors + stats->rx_crc_errors +
2669                            stats->rx_frame_errors;
2670         stats->tx_errors = stats->tx_aborted_errors + stats->tx_carrier_errors;
2671
2672         /* vport multicast also counts packets that are dropped due to steering
2673          * or rx out of buffer
2674          */
2675         stats->multicast =
2676                 VPORT_COUNTER_GET(vstats, received_eth_multicast.packets);
2677
2678         return stats;
2679 }
2680
2681 static void mlx5e_set_rx_mode(struct net_device *dev)
2682 {
2683         struct mlx5e_priv *priv = netdev_priv(dev);
2684
2685         queue_work(priv->wq, &priv->set_rx_mode_work);
2686 }
2687
2688 static int mlx5e_set_mac(struct net_device *netdev, void *addr)
2689 {
2690         struct mlx5e_priv *priv = netdev_priv(netdev);
2691         struct sockaddr *saddr = addr;
2692
2693         if (!is_valid_ether_addr(saddr->sa_data))
2694                 return -EADDRNOTAVAIL;
2695
2696         netif_addr_lock_bh(netdev);
2697         ether_addr_copy(netdev->dev_addr, saddr->sa_data);
2698         netif_addr_unlock_bh(netdev);
2699
2700         queue_work(priv->wq, &priv->set_rx_mode_work);
2701
2702         return 0;
2703 }
2704
2705 #define MLX5E_SET_FEATURE(netdev, feature, enable)      \
2706         do {                                            \
2707                 if (enable)                             \
2708                         netdev->features |= feature;    \
2709                 else                                    \
2710                         netdev->features &= ~feature;   \
2711         } while (0)
2712
2713 typedef int (*mlx5e_feature_handler)(struct net_device *netdev, bool enable);
2714
2715 static int set_feature_lro(struct net_device *netdev, bool enable)
2716 {
2717         struct mlx5e_priv *priv = netdev_priv(netdev);
2718         bool was_opened = test_bit(MLX5E_STATE_OPENED, &priv->state);
2719         int err;
2720
2721         mutex_lock(&priv->state_lock);
2722
2723         if (was_opened && (priv->params.rq_wq_type == MLX5_WQ_TYPE_LINKED_LIST))
2724                 mlx5e_close_locked(priv->netdev);
2725
2726         priv->params.lro_en = enable;
2727         err = mlx5e_modify_tirs_lro(priv);
2728         if (err) {
2729                 netdev_err(netdev, "lro modify failed, %d\n", err);
2730                 priv->params.lro_en = !enable;
2731         }
2732
2733         if (was_opened && (priv->params.rq_wq_type == MLX5_WQ_TYPE_LINKED_LIST))
2734                 mlx5e_open_locked(priv->netdev);
2735
2736         mutex_unlock(&priv->state_lock);
2737
2738         return err;
2739 }
2740
2741 static int set_feature_vlan_filter(struct net_device *netdev, bool enable)
2742 {
2743         struct mlx5e_priv *priv = netdev_priv(netdev);
2744
2745         if (enable)
2746                 mlx5e_enable_vlan_filter(priv);
2747         else
2748                 mlx5e_disable_vlan_filter(priv);
2749
2750         return 0;
2751 }
2752
2753 static int set_feature_tc_num_filters(struct net_device *netdev, bool enable)
2754 {
2755         struct mlx5e_priv *priv = netdev_priv(netdev);
2756
2757         if (!enable && mlx5e_tc_num_filters(priv)) {
2758                 netdev_err(netdev,
2759                            "Active offloaded tc filters, can't turn hw_tc_offload off\n");
2760                 return -EINVAL;
2761         }
2762
2763         return 0;
2764 }
2765
2766 static int set_feature_rx_all(struct net_device *netdev, bool enable)
2767 {
2768         struct mlx5e_priv *priv = netdev_priv(netdev);
2769         struct mlx5_core_dev *mdev = priv->mdev;
2770
2771         return mlx5_set_port_fcs(mdev, !enable);
2772 }
2773
2774 static int set_feature_rx_vlan(struct net_device *netdev, bool enable)
2775 {
2776         struct mlx5e_priv *priv = netdev_priv(netdev);
2777         int err;
2778
2779         mutex_lock(&priv->state_lock);
2780
2781         priv->params.vlan_strip_disable = !enable;
2782         err = mlx5e_modify_rqs_vsd(priv, !enable);
2783         if (err)
2784                 priv->params.vlan_strip_disable = enable;
2785
2786         mutex_unlock(&priv->state_lock);
2787
2788         return err;
2789 }
2790
2791 #ifdef CONFIG_RFS_ACCEL
2792 static int set_feature_arfs(struct net_device *netdev, bool enable)
2793 {
2794         struct mlx5e_priv *priv = netdev_priv(netdev);
2795         int err;
2796
2797         if (enable)
2798                 err = mlx5e_arfs_enable(priv);
2799         else
2800                 err = mlx5e_arfs_disable(priv);
2801
2802         return err;
2803 }
2804 #endif
2805
2806 static int mlx5e_handle_feature(struct net_device *netdev,
2807                                 netdev_features_t wanted_features,
2808                                 netdev_features_t feature,
2809                                 mlx5e_feature_handler feature_handler)
2810 {
2811         netdev_features_t changes = wanted_features ^ netdev->features;
2812         bool enable = !!(wanted_features & feature);
2813         int err;
2814
2815         if (!(changes & feature))
2816                 return 0;
2817
2818         err = feature_handler(netdev, enable);
2819         if (err) {
2820                 netdev_err(netdev, "%s feature 0x%llx failed err %d\n",
2821                            enable ? "Enable" : "Disable", feature, err);
2822                 return err;
2823         }
2824
2825         MLX5E_SET_FEATURE(netdev, feature, enable);
2826         return 0;
2827 }
2828
2829 static int mlx5e_set_features(struct net_device *netdev,
2830                               netdev_features_t features)
2831 {
2832         int err;
2833
2834         err  = mlx5e_handle_feature(netdev, features, NETIF_F_LRO,
2835                                     set_feature_lro);
2836         err |= mlx5e_handle_feature(netdev, features,
2837                                     NETIF_F_HW_VLAN_CTAG_FILTER,
2838                                     set_feature_vlan_filter);
2839         err |= mlx5e_handle_feature(netdev, features, NETIF_F_HW_TC,
2840                                     set_feature_tc_num_filters);
2841         err |= mlx5e_handle_feature(netdev, features, NETIF_F_RXALL,
2842                                     set_feature_rx_all);
2843         err |= mlx5e_handle_feature(netdev, features, NETIF_F_HW_VLAN_CTAG_RX,
2844                                     set_feature_rx_vlan);
2845 #ifdef CONFIG_RFS_ACCEL
2846         err |= mlx5e_handle_feature(netdev, features, NETIF_F_NTUPLE,
2847                                     set_feature_arfs);
2848 #endif
2849
2850         return err ? -EINVAL : 0;
2851 }
2852
2853 static int mlx5e_change_mtu(struct net_device *netdev, int new_mtu)
2854 {
2855         struct mlx5e_priv *priv = netdev_priv(netdev);
2856         bool was_opened;
2857         int err = 0;
2858         bool reset;
2859
2860         mutex_lock(&priv->state_lock);
2861
2862         reset = !priv->params.lro_en &&
2863                 (priv->params.rq_wq_type !=
2864                  MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ);
2865
2866         was_opened = test_bit(MLX5E_STATE_OPENED, &priv->state);
2867         if (was_opened && reset)
2868                 mlx5e_close_locked(netdev);
2869
2870         netdev->mtu = new_mtu;
2871         mlx5e_set_dev_port_mtu(netdev);
2872
2873         if (was_opened && reset)
2874                 err = mlx5e_open_locked(netdev);
2875
2876         mutex_unlock(&priv->state_lock);
2877
2878         return err;
2879 }
2880
2881 static int mlx5e_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
2882 {
2883         switch (cmd) {
2884         case SIOCSHWTSTAMP:
2885                 return mlx5e_hwstamp_set(dev, ifr);
2886         case SIOCGHWTSTAMP:
2887                 return mlx5e_hwstamp_get(dev, ifr);
2888         default:
2889                 return -EOPNOTSUPP;
2890         }
2891 }
2892
2893 static int mlx5e_set_vf_mac(struct net_device *dev, int vf, u8 *mac)
2894 {
2895         struct mlx5e_priv *priv = netdev_priv(dev);
2896         struct mlx5_core_dev *mdev = priv->mdev;
2897
2898         return mlx5_eswitch_set_vport_mac(mdev->priv.eswitch, vf + 1, mac);
2899 }
2900
2901 static int mlx5e_set_vf_vlan(struct net_device *dev, int vf, u16 vlan, u8 qos,
2902                              __be16 vlan_proto)
2903 {
2904         struct mlx5e_priv *priv = netdev_priv(dev);
2905         struct mlx5_core_dev *mdev = priv->mdev;
2906
2907         if (vlan_proto != htons(ETH_P_8021Q))
2908                 return -EPROTONOSUPPORT;
2909
2910         return mlx5_eswitch_set_vport_vlan(mdev->priv.eswitch, vf + 1,
2911                                            vlan, qos);
2912 }
2913
2914 static int mlx5e_set_vf_spoofchk(struct net_device *dev, int vf, bool setting)
2915 {
2916         struct mlx5e_priv *priv = netdev_priv(dev);
2917         struct mlx5_core_dev *mdev = priv->mdev;
2918
2919         return mlx5_eswitch_set_vport_spoofchk(mdev->priv.eswitch, vf + 1, setting);
2920 }
2921
2922 static int mlx5e_set_vf_trust(struct net_device *dev, int vf, bool setting)
2923 {
2924         struct mlx5e_priv *priv = netdev_priv(dev);
2925         struct mlx5_core_dev *mdev = priv->mdev;
2926
2927         return mlx5_eswitch_set_vport_trust(mdev->priv.eswitch, vf + 1, setting);
2928 }
2929
2930 static int mlx5e_set_vf_rate(struct net_device *dev, int vf, int min_tx_rate,
2931                              int max_tx_rate)
2932 {
2933         struct mlx5e_priv *priv = netdev_priv(dev);
2934         struct mlx5_core_dev *mdev = priv->mdev;
2935
2936         if (min_tx_rate)
2937                 return -EOPNOTSUPP;
2938
2939         return mlx5_eswitch_set_vport_rate(mdev->priv.eswitch, vf + 1,
2940                                            max_tx_rate);
2941 }
2942
2943 static int mlx5_vport_link2ifla(u8 esw_link)
2944 {
2945         switch (esw_link) {
2946         case MLX5_ESW_VPORT_ADMIN_STATE_DOWN:
2947                 return IFLA_VF_LINK_STATE_DISABLE;
2948         case MLX5_ESW_VPORT_ADMIN_STATE_UP:
2949                 return IFLA_VF_LINK_STATE_ENABLE;
2950         }
2951         return IFLA_VF_LINK_STATE_AUTO;
2952 }
2953
2954 static int mlx5_ifla_link2vport(u8 ifla_link)
2955 {
2956         switch (ifla_link) {
2957         case IFLA_VF_LINK_STATE_DISABLE:
2958                 return MLX5_ESW_VPORT_ADMIN_STATE_DOWN;
2959         case IFLA_VF_LINK_STATE_ENABLE:
2960                 return MLX5_ESW_VPORT_ADMIN_STATE_UP;
2961         }
2962         return MLX5_ESW_VPORT_ADMIN_STATE_AUTO;
2963 }
2964
2965 static int mlx5e_set_vf_link_state(struct net_device *dev, int vf,
2966                                    int link_state)
2967 {
2968         struct mlx5e_priv *priv = netdev_priv(dev);
2969         struct mlx5_core_dev *mdev = priv->mdev;
2970
2971         return mlx5_eswitch_set_vport_state(mdev->priv.eswitch, vf + 1,
2972                                             mlx5_ifla_link2vport(link_state));
2973 }
2974
2975 static int mlx5e_get_vf_config(struct net_device *dev,
2976                                int vf, struct ifla_vf_info *ivi)
2977 {
2978         struct mlx5e_priv *priv = netdev_priv(dev);
2979         struct mlx5_core_dev *mdev = priv->mdev;
2980         int err;
2981
2982         err = mlx5_eswitch_get_vport_config(mdev->priv.eswitch, vf + 1, ivi);
2983         if (err)
2984                 return err;
2985         ivi->linkstate = mlx5_vport_link2ifla(ivi->linkstate);
2986         return 0;
2987 }
2988
2989 static int mlx5e_get_vf_stats(struct net_device *dev,
2990                               int vf, struct ifla_vf_stats *vf_stats)
2991 {
2992         struct mlx5e_priv *priv = netdev_priv(dev);
2993         struct mlx5_core_dev *mdev = priv->mdev;
2994
2995         return mlx5_eswitch_get_vport_stats(mdev->priv.eswitch, vf + 1,
2996                                             vf_stats);
2997 }
2998
2999 void mlx5e_add_vxlan_port(struct net_device *netdev,
3000                           struct udp_tunnel_info *ti)
3001 {
3002         struct mlx5e_priv *priv = netdev_priv(netdev);
3003
3004         if (ti->type != UDP_TUNNEL_TYPE_VXLAN)
3005                 return;
3006
3007         if (!mlx5e_vxlan_allowed(priv->mdev))
3008                 return;
3009
3010         mlx5e_vxlan_queue_work(priv, ti->sa_family, be16_to_cpu(ti->port), 1);
3011 }
3012
3013 void mlx5e_del_vxlan_port(struct net_device *netdev,
3014                           struct udp_tunnel_info *ti)
3015 {
3016         struct mlx5e_priv *priv = netdev_priv(netdev);
3017
3018         if (ti->type != UDP_TUNNEL_TYPE_VXLAN)
3019                 return;
3020
3021         if (!mlx5e_vxlan_allowed(priv->mdev))
3022                 return;
3023
3024         mlx5e_vxlan_queue_work(priv, ti->sa_family, be16_to_cpu(ti->port), 0);
3025 }
3026
3027 static netdev_features_t mlx5e_vxlan_features_check(struct mlx5e_priv *priv,
3028                                                     struct sk_buff *skb,
3029                                                     netdev_features_t features)
3030 {
3031         struct udphdr *udph;
3032         u16 proto;
3033         u16 port = 0;
3034
3035         switch (vlan_get_protocol(skb)) {
3036         case htons(ETH_P_IP):
3037                 proto = ip_hdr(skb)->protocol;
3038                 break;
3039         case htons(ETH_P_IPV6):
3040                 proto = ipv6_hdr(skb)->nexthdr;
3041                 break;
3042         default:
3043                 goto out;
3044         }
3045
3046         if (proto == IPPROTO_UDP) {
3047                 udph = udp_hdr(skb);
3048                 port = be16_to_cpu(udph->dest);
3049         }
3050
3051         /* Verify if UDP port is being offloaded by HW */
3052         if (port && mlx5e_vxlan_lookup_port(priv, port))
3053                 return features;
3054
3055 out:
3056         /* Disable CSUM and GSO if the udp dport is not offloaded by HW */
3057         return features & ~(NETIF_F_CSUM_MASK | NETIF_F_GSO_MASK);
3058 }
3059
3060 static netdev_features_t mlx5e_features_check(struct sk_buff *skb,
3061                                               struct net_device *netdev,
3062                                               netdev_features_t features)
3063 {
3064         struct mlx5e_priv *priv = netdev_priv(netdev);
3065
3066         features = vlan_features_check(skb, features);
3067         features = vxlan_features_check(skb, features);
3068
3069         /* Validate if the tunneled packet is being offloaded by HW */
3070         if (skb->encapsulation &&
3071             (features & NETIF_F_CSUM_MASK || features & NETIF_F_GSO_MASK))
3072                 return mlx5e_vxlan_features_check(priv, skb, features);
3073
3074         return features;
3075 }
3076
3077 static void mlx5e_tx_timeout(struct net_device *dev)
3078 {
3079         struct mlx5e_priv *priv = netdev_priv(dev);
3080         bool sched_work = false;
3081         int i;
3082
3083         netdev_err(dev, "TX timeout detected\n");
3084
3085         for (i = 0; i < priv->params.num_channels * priv->params.num_tc; i++) {
3086                 struct mlx5e_sq *sq = priv->txq_to_sq_map[i];
3087
3088                 if (!netif_xmit_stopped(netdev_get_tx_queue(dev, i)))
3089                         continue;
3090                 sched_work = true;
3091                 set_bit(MLX5E_SQ_STATE_FLUSH, &sq->state);
3092                 netdev_err(dev, "TX timeout on queue: %d, SQ: 0x%x, CQ: 0x%x, SQ Cons: 0x%x SQ Prod: 0x%x\n",
3093                            i, sq->sqn, sq->cq.mcq.cqn, sq->cc, sq->pc);
3094         }
3095
3096         if (sched_work && test_bit(MLX5E_STATE_OPENED, &priv->state))
3097                 schedule_work(&priv->tx_timeout_work);
3098 }
3099
3100 static int mlx5e_xdp_set(struct net_device *netdev, struct bpf_prog *prog)
3101 {
3102         struct mlx5e_priv *priv = netdev_priv(netdev);
3103         struct bpf_prog *old_prog;
3104         int err = 0;
3105         bool reset, was_opened;
3106         int i;
3107
3108         mutex_lock(&priv->state_lock);
3109
3110         if ((netdev->features & NETIF_F_LRO) && prog) {
3111                 netdev_warn(netdev, "can't set XDP while LRO is on, disable LRO first\n");
3112                 err = -EINVAL;
3113                 goto unlock;
3114         }
3115
3116         was_opened = test_bit(MLX5E_STATE_OPENED, &priv->state);
3117         /* no need for full reset when exchanging programs */
3118         reset = (!priv->xdp_prog || !prog);
3119
3120         if (was_opened && reset)
3121                 mlx5e_close_locked(netdev);
3122
3123         /* exchange programs */
3124         old_prog = xchg(&priv->xdp_prog, prog);
3125         if (prog)
3126                 bpf_prog_add(prog, 1);
3127         if (old_prog)
3128                 bpf_prog_put(old_prog);
3129
3130         if (reset) /* change RQ type according to priv->xdp_prog */
3131                 mlx5e_set_rq_priv_params(priv);
3132
3133         if (was_opened && reset)
3134                 mlx5e_open_locked(netdev);
3135
3136         if (!test_bit(MLX5E_STATE_OPENED, &priv->state) || reset)
3137                 goto unlock;
3138
3139         /* exchanging programs w/o reset, we update ref counts on behalf
3140          * of the channels RQs here.
3141          */
3142         bpf_prog_add(prog, priv->params.num_channels);
3143         for (i = 0; i < priv->params.num_channels; i++) {
3144                 struct mlx5e_channel *c = priv->channel[i];
3145
3146                 set_bit(MLX5E_RQ_STATE_FLUSH, &c->rq.state);
3147                 napi_synchronize(&c->napi);
3148                 /* prevent mlx5e_poll_rx_cq from accessing rq->xdp_prog */
3149
3150                 old_prog = xchg(&c->rq.xdp_prog, prog);
3151
3152                 clear_bit(MLX5E_RQ_STATE_FLUSH, &c->rq.state);
3153                 /* napi_schedule in case we have missed anything */
3154                 set_bit(MLX5E_CHANNEL_NAPI_SCHED, &c->flags);
3155                 napi_schedule(&c->napi);
3156
3157                 if (old_prog)
3158                         bpf_prog_put(old_prog);
3159         }
3160
3161 unlock:
3162         mutex_unlock(&priv->state_lock);
3163         return err;
3164 }
3165
3166 static bool mlx5e_xdp_attached(struct net_device *dev)
3167 {
3168         struct mlx5e_priv *priv = netdev_priv(dev);
3169
3170         return !!priv->xdp_prog;
3171 }
3172
3173 static int mlx5e_xdp(struct net_device *dev, struct netdev_xdp *xdp)
3174 {
3175         switch (xdp->command) {
3176         case XDP_SETUP_PROG:
3177                 return mlx5e_xdp_set(dev, xdp->prog);
3178         case XDP_QUERY_PROG:
3179                 xdp->prog_attached = mlx5e_xdp_attached(dev);
3180                 return 0;
3181         default:
3182                 return -EINVAL;
3183         }
3184 }
3185
3186 #ifdef CONFIG_NET_POLL_CONTROLLER
3187 /* Fake "interrupt" called by netpoll (eg netconsole) to send skbs without
3188  * reenabling interrupts.
3189  */
3190 static void mlx5e_netpoll(struct net_device *dev)
3191 {
3192         struct mlx5e_priv *priv = netdev_priv(dev);
3193         int i;
3194
3195         for (i = 0; i < priv->params.num_channels; i++)
3196                 napi_schedule(&priv->channel[i]->napi);
3197 }
3198 #endif
3199
3200 static const struct net_device_ops mlx5e_netdev_ops_basic = {
3201         .ndo_open                = mlx5e_open,
3202         .ndo_stop                = mlx5e_close,
3203         .ndo_start_xmit          = mlx5e_xmit,
3204         .ndo_setup_tc            = mlx5e_ndo_setup_tc,
3205         .ndo_select_queue        = mlx5e_select_queue,
3206         .ndo_get_stats64         = mlx5e_get_stats,
3207         .ndo_set_rx_mode         = mlx5e_set_rx_mode,
3208         .ndo_set_mac_address     = mlx5e_set_mac,
3209         .ndo_vlan_rx_add_vid     = mlx5e_vlan_rx_add_vid,
3210         .ndo_vlan_rx_kill_vid    = mlx5e_vlan_rx_kill_vid,
3211         .ndo_set_features        = mlx5e_set_features,
3212         .ndo_change_mtu          = mlx5e_change_mtu,
3213         .ndo_do_ioctl            = mlx5e_ioctl,
3214         .ndo_set_tx_maxrate      = mlx5e_set_tx_maxrate,
3215 #ifdef CONFIG_RFS_ACCEL
3216         .ndo_rx_flow_steer       = mlx5e_rx_flow_steer,
3217 #endif
3218         .ndo_tx_timeout          = mlx5e_tx_timeout,
3219         .ndo_xdp                 = mlx5e_xdp,
3220 #ifdef CONFIG_NET_POLL_CONTROLLER
3221         .ndo_poll_controller     = mlx5e_netpoll,
3222 #endif
3223 };
3224
3225 static const struct net_device_ops mlx5e_netdev_ops_sriov = {
3226         .ndo_open                = mlx5e_open,
3227         .ndo_stop                = mlx5e_close,
3228         .ndo_start_xmit          = mlx5e_xmit,
3229         .ndo_setup_tc            = mlx5e_ndo_setup_tc,
3230         .ndo_select_queue        = mlx5e_select_queue,
3231         .ndo_get_stats64         = mlx5e_get_stats,
3232         .ndo_set_rx_mode         = mlx5e_set_rx_mode,
3233         .ndo_set_mac_address     = mlx5e_set_mac,
3234         .ndo_vlan_rx_add_vid     = mlx5e_vlan_rx_add_vid,
3235         .ndo_vlan_rx_kill_vid    = mlx5e_vlan_rx_kill_vid,
3236         .ndo_set_features        = mlx5e_set_features,
3237         .ndo_change_mtu          = mlx5e_change_mtu,
3238         .ndo_do_ioctl            = mlx5e_ioctl,
3239         .ndo_udp_tunnel_add      = mlx5e_add_vxlan_port,
3240         .ndo_udp_tunnel_del      = mlx5e_del_vxlan_port,
3241         .ndo_set_tx_maxrate      = mlx5e_set_tx_maxrate,
3242         .ndo_features_check      = mlx5e_features_check,
3243 #ifdef CONFIG_RFS_ACCEL
3244         .ndo_rx_flow_steer       = mlx5e_rx_flow_steer,
3245 #endif
3246         .ndo_set_vf_mac          = mlx5e_set_vf_mac,
3247         .ndo_set_vf_vlan         = mlx5e_set_vf_vlan,
3248         .ndo_set_vf_spoofchk     = mlx5e_set_vf_spoofchk,
3249         .ndo_set_vf_trust        = mlx5e_set_vf_trust,
3250         .ndo_set_vf_rate         = mlx5e_set_vf_rate,
3251         .ndo_get_vf_config       = mlx5e_get_vf_config,
3252         .ndo_set_vf_link_state   = mlx5e_set_vf_link_state,
3253         .ndo_get_vf_stats        = mlx5e_get_vf_stats,
3254         .ndo_tx_timeout          = mlx5e_tx_timeout,
3255         .ndo_xdp                 = mlx5e_xdp,
3256 #ifdef CONFIG_NET_POLL_CONTROLLER
3257         .ndo_poll_controller     = mlx5e_netpoll,
3258 #endif
3259 };
3260
3261 static int mlx5e_check_required_hca_cap(struct mlx5_core_dev *mdev)
3262 {
3263         if (MLX5_CAP_GEN(mdev, port_type) != MLX5_CAP_PORT_TYPE_ETH)
3264                 return -ENOTSUPP;
3265         if (!MLX5_CAP_GEN(mdev, eth_net_offloads) ||
3266             !MLX5_CAP_GEN(mdev, nic_flow_table) ||
3267             !MLX5_CAP_ETH(mdev, csum_cap) ||
3268             !MLX5_CAP_ETH(mdev, max_lso_cap) ||
3269             !MLX5_CAP_ETH(mdev, vlan_cap) ||
3270             !MLX5_CAP_ETH(mdev, rss_ind_tbl_cap) ||
3271             MLX5_CAP_FLOWTABLE(mdev,
3272                                flow_table_properties_nic_receive.max_ft_level)
3273                                < 3) {
3274                 mlx5_core_warn(mdev,
3275                                "Not creating net device, some required device capabilities are missing\n");
3276                 return -ENOTSUPP;
3277         }
3278         if (!MLX5_CAP_ETH(mdev, self_lb_en_modifiable))
3279                 mlx5_core_warn(mdev, "Self loop back prevention is not supported\n");
3280         if (!MLX5_CAP_GEN(mdev, cq_moderation))
3281                 mlx5_core_warn(mdev, "CQ modiration is not supported\n");
3282
3283         return 0;
3284 }
3285
3286 u16 mlx5e_get_max_inline_cap(struct mlx5_core_dev *mdev)
3287 {
3288         int bf_buf_size = (1 << MLX5_CAP_GEN(mdev, log_bf_reg_size)) / 2;
3289
3290         return bf_buf_size -
3291                sizeof(struct mlx5e_tx_wqe) +
3292                2 /*sizeof(mlx5e_tx_wqe.inline_hdr_start)*/;
3293 }
3294
3295 #ifdef CONFIG_MLX5_CORE_EN_DCB
3296 static void mlx5e_ets_init(struct mlx5e_priv *priv)
3297 {
3298         int i;
3299
3300         priv->params.ets.ets_cap = mlx5_max_tc(priv->mdev) + 1;
3301         for (i = 0; i < priv->params.ets.ets_cap; i++) {
3302                 priv->params.ets.tc_tx_bw[i] = MLX5E_MAX_BW_ALLOC;
3303                 priv->params.ets.tc_tsa[i] = IEEE_8021QAZ_TSA_VENDOR;
3304                 priv->params.ets.prio_tc[i] = i;
3305         }
3306
3307         /* tclass[prio=0]=1, tclass[prio=1]=0, tclass[prio=i]=i (for i>1) */
3308         priv->params.ets.prio_tc[0] = 1;
3309         priv->params.ets.prio_tc[1] = 0;
3310 }
3311 #endif
3312
3313 void mlx5e_build_default_indir_rqt(struct mlx5_core_dev *mdev,
3314                                    u32 *indirection_rqt, int len,
3315                                    int num_channels)
3316 {
3317         int node = mdev->priv.numa_node;
3318         int node_num_of_cores;
3319         int i;
3320
3321         if (node == -1)
3322                 node = first_online_node;
3323
3324         node_num_of_cores = cpumask_weight(cpumask_of_node(node));
3325
3326         if (node_num_of_cores)
3327                 num_channels = min_t(int, num_channels, node_num_of_cores);
3328
3329         for (i = 0; i < len; i++)
3330                 indirection_rqt[i] = i % num_channels;
3331 }
3332
3333 static int mlx5e_get_pci_bw(struct mlx5_core_dev *mdev, u32 *pci_bw)
3334 {
3335         enum pcie_link_width width;
3336         enum pci_bus_speed speed;
3337         int err = 0;
3338
3339         err = pcie_get_minimum_link(mdev->pdev, &speed, &width);
3340         if (err)
3341                 return err;
3342
3343         if (speed == PCI_SPEED_UNKNOWN || width == PCIE_LNK_WIDTH_UNKNOWN)
3344                 return -EINVAL;
3345
3346         switch (speed) {
3347         case PCIE_SPEED_2_5GT:
3348                 *pci_bw = 2500 * width;
3349                 break;
3350         case PCIE_SPEED_5_0GT:
3351                 *pci_bw = 5000 * width;
3352                 break;
3353         case PCIE_SPEED_8_0GT:
3354                 *pci_bw = 8000 * width;
3355                 break;
3356         default:
3357                 return -EINVAL;
3358         }
3359
3360         return 0;
3361 }
3362
3363 static bool cqe_compress_heuristic(u32 link_speed, u32 pci_bw)
3364 {
3365         return (link_speed && pci_bw &&
3366                 (pci_bw < 40000) && (pci_bw < link_speed));
3367 }
3368
3369 void mlx5e_set_rx_cq_mode_params(struct mlx5e_params *params, u8 cq_period_mode)
3370 {
3371         params->rx_cq_period_mode = cq_period_mode;
3372
3373         params->rx_cq_moderation.pkts =
3374                 MLX5E_PARAMS_DEFAULT_RX_CQ_MODERATION_PKTS;
3375         params->rx_cq_moderation.usec =
3376                         MLX5E_PARAMS_DEFAULT_RX_CQ_MODERATION_USEC;
3377
3378         if (cq_period_mode == MLX5_CQ_PERIOD_MODE_START_FROM_CQE)
3379                 params->rx_cq_moderation.usec =
3380                         MLX5E_PARAMS_DEFAULT_RX_CQ_MODERATION_USEC_FROM_CQE;
3381 }
3382
3383 static void mlx5e_query_min_inline(struct mlx5_core_dev *mdev,
3384                                    u8 *min_inline_mode)
3385 {
3386         switch (MLX5_CAP_ETH(mdev, wqe_inline_mode)) {
3387         case MLX5E_INLINE_MODE_L2:
3388                 *min_inline_mode = MLX5_INLINE_MODE_L2;
3389                 break;
3390         case MLX5E_INLINE_MODE_VPORT_CONTEXT:
3391                 mlx5_query_nic_vport_min_inline(mdev,
3392                                                 min_inline_mode);
3393                 break;
3394         case MLX5_INLINE_MODE_NOT_REQUIRED:
3395                 *min_inline_mode = MLX5_INLINE_MODE_NONE;
3396                 break;
3397         }
3398 }
3399
3400 u32 mlx5e_choose_lro_timeout(struct mlx5_core_dev *mdev, u32 wanted_timeout)
3401 {
3402         int i;
3403
3404         /* The supported periods are organized in ascending order */
3405         for (i = 0; i < MLX5E_LRO_TIMEOUT_ARR_SIZE - 1; i++)
3406                 if (MLX5_CAP_ETH(mdev, lro_timer_supported_periods[i]) >= wanted_timeout)
3407                         break;
3408
3409         return MLX5_CAP_ETH(mdev, lro_timer_supported_periods[i]);
3410 }
3411
3412 static void mlx5e_build_nic_netdev_priv(struct mlx5_core_dev *mdev,
3413                                         struct net_device *netdev,
3414                                         const struct mlx5e_profile *profile,
3415                                         void *ppriv)
3416 {
3417         struct mlx5e_priv *priv = netdev_priv(netdev);
3418         u32 link_speed = 0;
3419         u32 pci_bw = 0;
3420         u8 cq_period_mode = MLX5_CAP_GEN(mdev, cq_period_start_from_cqe) ?
3421                                          MLX5_CQ_PERIOD_MODE_START_FROM_CQE :
3422                                          MLX5_CQ_PERIOD_MODE_START_FROM_EQE;
3423
3424         priv->mdev                         = mdev;
3425         priv->netdev                       = netdev;
3426         priv->params.num_channels          = profile->max_nch(mdev);
3427         priv->profile                      = profile;
3428         priv->ppriv                        = ppriv;
3429
3430         priv->params.lro_timeout =
3431                 mlx5e_choose_lro_timeout(mdev, MLX5E_DEFAULT_LRO_TIMEOUT);
3432
3433         priv->params.log_sq_size = MLX5E_PARAMS_DEFAULT_LOG_SQ_SIZE;
3434
3435         /* set CQE compression */
3436         priv->params.rx_cqe_compress_admin = false;
3437         if (MLX5_CAP_GEN(mdev, cqe_compression) &&
3438             MLX5_CAP_GEN(mdev, vport_group_manager)) {
3439                 mlx5e_get_max_linkspeed(mdev, &link_speed);
3440                 mlx5e_get_pci_bw(mdev, &pci_bw);
3441                 mlx5_core_dbg(mdev, "Max link speed = %d, PCI BW = %d\n",
3442                               link_speed, pci_bw);
3443                 priv->params.rx_cqe_compress_admin =
3444                         cqe_compress_heuristic(link_speed, pci_bw);
3445         }
3446         priv->params.rx_cqe_compress = priv->params.rx_cqe_compress_admin;
3447
3448         mlx5e_set_rq_priv_params(priv);
3449         if (priv->params.rq_wq_type == MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ)
3450                 priv->params.lro_en = true;
3451
3452         priv->params.rx_am_enabled = MLX5_CAP_GEN(mdev, cq_moderation);
3453         mlx5e_set_rx_cq_mode_params(&priv->params, cq_period_mode);
3454
3455         priv->params.tx_cq_moderation.usec =
3456                 MLX5E_PARAMS_DEFAULT_TX_CQ_MODERATION_USEC;
3457         priv->params.tx_cq_moderation.pkts =
3458                 MLX5E_PARAMS_DEFAULT_TX_CQ_MODERATION_PKTS;
3459         priv->params.tx_max_inline         = mlx5e_get_max_inline_cap(mdev);
3460         mlx5e_query_min_inline(mdev, &priv->params.tx_min_inline_mode);
3461         priv->params.num_tc                = 1;
3462         priv->params.rss_hfunc             = ETH_RSS_HASH_XOR;
3463
3464         netdev_rss_key_fill(priv->params.toeplitz_hash_key,
3465                             sizeof(priv->params.toeplitz_hash_key));
3466
3467         mlx5e_build_default_indir_rqt(mdev, priv->params.indirection_rqt,
3468                                       MLX5E_INDIR_RQT_SIZE, profile->max_nch(mdev));
3469
3470         priv->params.lro_wqe_sz =
3471                 MLX5E_PARAMS_DEFAULT_LRO_WQE_SZ -
3472                 /* Extra room needed for build_skb */
3473                 MLX5_RX_HEADROOM -
3474                 SKB_DATA_ALIGN(sizeof(struct skb_shared_info));
3475
3476         /* Initialize pflags */
3477         MLX5E_SET_PRIV_FLAG(priv, MLX5E_PFLAG_RX_CQE_BASED_MODER,
3478                             priv->params.rx_cq_period_mode == MLX5_CQ_PERIOD_MODE_START_FROM_CQE);
3479
3480 #ifdef CONFIG_MLX5_CORE_EN_DCB
3481         mlx5e_ets_init(priv);
3482 #endif
3483
3484         mutex_init(&priv->state_lock);
3485
3486         INIT_WORK(&priv->update_carrier_work, mlx5e_update_carrier_work);
3487         INIT_WORK(&priv->set_rx_mode_work, mlx5e_set_rx_mode_work);
3488         INIT_WORK(&priv->tx_timeout_work, mlx5e_tx_timeout_work);
3489         INIT_DELAYED_WORK(&priv->update_stats_work, mlx5e_update_stats_work);
3490 }
3491
3492 static void mlx5e_set_netdev_dev_addr(struct net_device *netdev)
3493 {
3494         struct mlx5e_priv *priv = netdev_priv(netdev);
3495
3496         mlx5_query_nic_vport_mac_address(priv->mdev, 0, netdev->dev_addr);
3497         if (is_zero_ether_addr(netdev->dev_addr) &&
3498             !MLX5_CAP_GEN(priv->mdev, vport_group_manager)) {
3499                 eth_hw_addr_random(netdev);
3500                 mlx5_core_info(priv->mdev, "Assigned random MAC address %pM\n", netdev->dev_addr);
3501         }
3502 }
3503
3504 static const struct switchdev_ops mlx5e_switchdev_ops = {
3505         .switchdev_port_attr_get        = mlx5e_attr_get,
3506 };
3507
3508 static void mlx5e_build_nic_netdev(struct net_device *netdev)
3509 {
3510         struct mlx5e_priv *priv = netdev_priv(netdev);
3511         struct mlx5_core_dev *mdev = priv->mdev;
3512         bool fcs_supported;
3513         bool fcs_enabled;
3514
3515         SET_NETDEV_DEV(netdev, &mdev->pdev->dev);
3516
3517         if (MLX5_CAP_GEN(mdev, vport_group_manager)) {
3518                 netdev->netdev_ops = &mlx5e_netdev_ops_sriov;
3519 #ifdef CONFIG_MLX5_CORE_EN_DCB
3520                 netdev->dcbnl_ops = &mlx5e_dcbnl_ops;
3521 #endif
3522         } else {
3523                 netdev->netdev_ops = &mlx5e_netdev_ops_basic;
3524         }
3525
3526         netdev->watchdog_timeo    = 15 * HZ;
3527
3528         netdev->ethtool_ops       = &mlx5e_ethtool_ops;
3529
3530         netdev->vlan_features    |= NETIF_F_SG;
3531         netdev->vlan_features    |= NETIF_F_IP_CSUM;
3532         netdev->vlan_features    |= NETIF_F_IPV6_CSUM;
3533         netdev->vlan_features    |= NETIF_F_GRO;
3534         netdev->vlan_features    |= NETIF_F_TSO;
3535         netdev->vlan_features    |= NETIF_F_TSO6;
3536         netdev->vlan_features    |= NETIF_F_RXCSUM;
3537         netdev->vlan_features    |= NETIF_F_RXHASH;
3538
3539         if (!!MLX5_CAP_ETH(mdev, lro_cap))
3540                 netdev->vlan_features    |= NETIF_F_LRO;
3541
3542         netdev->hw_features       = netdev->vlan_features;
3543         netdev->hw_features      |= NETIF_F_HW_VLAN_CTAG_TX;
3544         netdev->hw_features      |= NETIF_F_HW_VLAN_CTAG_RX;
3545         netdev->hw_features      |= NETIF_F_HW_VLAN_CTAG_FILTER;
3546
3547         if (mlx5e_vxlan_allowed(mdev)) {
3548                 netdev->hw_features     |= NETIF_F_GSO_UDP_TUNNEL |
3549                                            NETIF_F_GSO_UDP_TUNNEL_CSUM |
3550                                            NETIF_F_GSO_PARTIAL;
3551                 netdev->hw_enc_features |= NETIF_F_IP_CSUM;
3552                 netdev->hw_enc_features |= NETIF_F_IPV6_CSUM;
3553                 netdev->hw_enc_features |= NETIF_F_TSO;
3554                 netdev->hw_enc_features |= NETIF_F_TSO6;
3555                 netdev->hw_enc_features |= NETIF_F_GSO_UDP_TUNNEL;
3556                 netdev->hw_enc_features |= NETIF_F_GSO_UDP_TUNNEL_CSUM |
3557                                            NETIF_F_GSO_PARTIAL;
3558                 netdev->gso_partial_features = NETIF_F_GSO_UDP_TUNNEL_CSUM;
3559         }
3560
3561         mlx5_query_port_fcs(mdev, &fcs_supported, &fcs_enabled);
3562
3563         if (fcs_supported)
3564                 netdev->hw_features |= NETIF_F_RXALL;
3565
3566         netdev->features          = netdev->hw_features;
3567         if (!priv->params.lro_en)
3568                 netdev->features  &= ~NETIF_F_LRO;
3569
3570         if (fcs_enabled)
3571                 netdev->features  &= ~NETIF_F_RXALL;
3572
3573 #define FT_CAP(f) MLX5_CAP_FLOWTABLE(mdev, flow_table_properties_nic_receive.f)
3574         if (FT_CAP(flow_modify_en) &&
3575             FT_CAP(modify_root) &&
3576             FT_CAP(identified_miss_table_mode) &&
3577             FT_CAP(flow_table_modify)) {
3578                 netdev->hw_features      |= NETIF_F_HW_TC;
3579 #ifdef CONFIG_RFS_ACCEL
3580                 netdev->hw_features      |= NETIF_F_NTUPLE;
3581 #endif
3582         }
3583
3584         netdev->features         |= NETIF_F_HIGHDMA;
3585
3586         netdev->priv_flags       |= IFF_UNICAST_FLT;
3587
3588         mlx5e_set_netdev_dev_addr(netdev);
3589
3590 #ifdef CONFIG_NET_SWITCHDEV
3591         if (MLX5_CAP_GEN(mdev, vport_group_manager))
3592                 netdev->switchdev_ops = &mlx5e_switchdev_ops;
3593 #endif
3594 }
3595
3596 static void mlx5e_create_q_counter(struct mlx5e_priv *priv)
3597 {
3598         struct mlx5_core_dev *mdev = priv->mdev;
3599         int err;
3600
3601         err = mlx5_core_alloc_q_counter(mdev, &priv->q_counter);
3602         if (err) {
3603                 mlx5_core_warn(mdev, "alloc queue counter failed, %d\n", err);
3604                 priv->q_counter = 0;
3605         }
3606 }
3607
3608 static void mlx5e_destroy_q_counter(struct mlx5e_priv *priv)
3609 {
3610         if (!priv->q_counter)
3611                 return;
3612
3613         mlx5_core_dealloc_q_counter(priv->mdev, priv->q_counter);
3614 }
3615
3616 static int mlx5e_create_umr_mkey(struct mlx5e_priv *priv)
3617 {
3618         struct mlx5_core_dev *mdev = priv->mdev;
3619         u64 npages = MLX5E_REQUIRED_MTTS(priv->profile->max_nch(mdev),
3620                                          BIT(MLX5E_PARAMS_MAXIMUM_LOG_RQ_SIZE_MPW));
3621         int inlen = MLX5_ST_SZ_BYTES(create_mkey_in);
3622         void *mkc;
3623         u32 *in;
3624         int err;
3625
3626         in = mlx5_vzalloc(inlen);
3627         if (!in)
3628                 return -ENOMEM;
3629
3630         mkc = MLX5_ADDR_OF(create_mkey_in, in, memory_key_mkey_entry);
3631
3632         npages = min_t(u32, ALIGN(U16_MAX, 4) * 2, npages);
3633
3634         MLX5_SET(mkc, mkc, free, 1);
3635         MLX5_SET(mkc, mkc, umr_en, 1);
3636         MLX5_SET(mkc, mkc, lw, 1);
3637         MLX5_SET(mkc, mkc, lr, 1);
3638         MLX5_SET(mkc, mkc, access_mode, MLX5_MKC_ACCESS_MODE_MTT);
3639
3640         MLX5_SET(mkc, mkc, qpn, 0xffffff);
3641         MLX5_SET(mkc, mkc, pd, mdev->mlx5e_res.pdn);
3642         MLX5_SET64(mkc, mkc, len, npages << PAGE_SHIFT);
3643         MLX5_SET(mkc, mkc, translations_octword_size,
3644                  MLX5_MTT_OCTW(npages));
3645         MLX5_SET(mkc, mkc, log_page_size, PAGE_SHIFT);
3646
3647         err = mlx5_core_create_mkey(mdev, &priv->umr_mkey, in, inlen);
3648
3649         kvfree(in);
3650         return err;
3651 }
3652
3653 static void mlx5e_nic_init(struct mlx5_core_dev *mdev,
3654                            struct net_device *netdev,
3655                            const struct mlx5e_profile *profile,
3656                            void *ppriv)
3657 {
3658         struct mlx5e_priv *priv = netdev_priv(netdev);
3659
3660         mlx5e_build_nic_netdev_priv(mdev, netdev, profile, ppriv);
3661         mlx5e_build_nic_netdev(netdev);
3662         mlx5e_vxlan_init(priv);
3663 }
3664
3665 static void mlx5e_nic_cleanup(struct mlx5e_priv *priv)
3666 {
3667         struct mlx5_core_dev *mdev = priv->mdev;
3668         struct mlx5_eswitch *esw = mdev->priv.eswitch;
3669
3670         mlx5e_vxlan_cleanup(priv);
3671
3672         if (MLX5_CAP_GEN(mdev, vport_group_manager))
3673                 mlx5_eswitch_unregister_vport_rep(esw, 0);
3674 }
3675
3676 static int mlx5e_init_nic_rx(struct mlx5e_priv *priv)
3677 {
3678         struct mlx5_core_dev *mdev = priv->mdev;
3679         int err;
3680         int i;
3681
3682         err = mlx5e_create_indirect_rqts(priv);
3683         if (err) {
3684                 mlx5_core_warn(mdev, "create indirect rqts failed, %d\n", err);
3685                 return err;
3686         }
3687
3688         err = mlx5e_create_direct_rqts(priv);
3689         if (err) {
3690                 mlx5_core_warn(mdev, "create direct rqts failed, %d\n", err);
3691                 goto err_destroy_indirect_rqts;
3692         }
3693
3694         err = mlx5e_create_indirect_tirs(priv);
3695         if (err) {
3696                 mlx5_core_warn(mdev, "create indirect tirs failed, %d\n", err);
3697                 goto err_destroy_direct_rqts;
3698         }
3699
3700         err = mlx5e_create_direct_tirs(priv);
3701         if (err) {
3702                 mlx5_core_warn(mdev, "create direct tirs failed, %d\n", err);
3703                 goto err_destroy_indirect_tirs;
3704         }
3705
3706         err = mlx5e_create_flow_steering(priv);
3707         if (err) {
3708                 mlx5_core_warn(mdev, "create flow steering failed, %d\n", err);
3709                 goto err_destroy_direct_tirs;
3710         }
3711
3712         err = mlx5e_tc_init(priv);
3713         if (err)
3714                 goto err_destroy_flow_steering;
3715
3716         return 0;
3717
3718 err_destroy_flow_steering:
3719         mlx5e_destroy_flow_steering(priv);
3720 err_destroy_direct_tirs:
3721         mlx5e_destroy_direct_tirs(priv);
3722 err_destroy_indirect_tirs:
3723         mlx5e_destroy_indirect_tirs(priv);
3724 err_destroy_direct_rqts:
3725         for (i = 0; i < priv->profile->max_nch(mdev); i++)
3726                 mlx5e_destroy_rqt(priv, &priv->direct_tir[i].rqt);
3727 err_destroy_indirect_rqts:
3728         mlx5e_destroy_rqt(priv, &priv->indir_rqt);
3729         return err;
3730 }
3731
3732 static void mlx5e_cleanup_nic_rx(struct mlx5e_priv *priv)
3733 {
3734         int i;
3735
3736         mlx5e_tc_cleanup(priv);
3737         mlx5e_destroy_flow_steering(priv);
3738         mlx5e_destroy_direct_tirs(priv);
3739         mlx5e_destroy_indirect_tirs(priv);
3740         for (i = 0; i < priv->profile->max_nch(priv->mdev); i++)
3741                 mlx5e_destroy_rqt(priv, &priv->direct_tir[i].rqt);
3742         mlx5e_destroy_rqt(priv, &priv->indir_rqt);
3743 }
3744
3745 static int mlx5e_init_nic_tx(struct mlx5e_priv *priv)
3746 {
3747         int err;
3748
3749         err = mlx5e_create_tises(priv);
3750         if (err) {
3751                 mlx5_core_warn(priv->mdev, "create tises failed, %d\n", err);
3752                 return err;
3753         }
3754
3755 #ifdef CONFIG_MLX5_CORE_EN_DCB
3756         mlx5e_dcbnl_ieee_setets_core(priv, &priv->params.ets);
3757 #endif
3758         return 0;
3759 }
3760
3761 static void mlx5e_nic_enable(struct mlx5e_priv *priv)
3762 {
3763         struct net_device *netdev = priv->netdev;
3764         struct mlx5_core_dev *mdev = priv->mdev;
3765         struct mlx5_eswitch *esw = mdev->priv.eswitch;
3766         struct mlx5_eswitch_rep rep;
3767
3768         mlx5_lag_add(mdev, netdev);
3769
3770         if (mlx5e_vxlan_allowed(mdev)) {
3771                 rtnl_lock();
3772                 udp_tunnel_get_rx_info(netdev);
3773                 rtnl_unlock();
3774         }
3775
3776         mlx5e_enable_async_events(priv);
3777         queue_work(priv->wq, &priv->set_rx_mode_work);
3778
3779         if (MLX5_CAP_GEN(mdev, vport_group_manager)) {
3780                 mlx5_query_nic_vport_mac_address(mdev, 0, rep.hw_id);
3781                 rep.load = mlx5e_nic_rep_load;
3782                 rep.unload = mlx5e_nic_rep_unload;
3783                 rep.vport = FDB_UPLINK_VPORT;
3784                 rep.priv_data = priv;
3785                 mlx5_eswitch_register_vport_rep(esw, 0, &rep);
3786         }
3787 }
3788
3789 static void mlx5e_nic_disable(struct mlx5e_priv *priv)
3790 {
3791         queue_work(priv->wq, &priv->set_rx_mode_work);
3792         mlx5e_disable_async_events(priv);
3793         mlx5_lag_remove(priv->mdev);
3794 }
3795
3796 static const struct mlx5e_profile mlx5e_nic_profile = {
3797         .init              = mlx5e_nic_init,
3798         .cleanup           = mlx5e_nic_cleanup,
3799         .init_rx           = mlx5e_init_nic_rx,
3800         .cleanup_rx        = mlx5e_cleanup_nic_rx,
3801         .init_tx           = mlx5e_init_nic_tx,
3802         .cleanup_tx        = mlx5e_cleanup_nic_tx,
3803         .enable            = mlx5e_nic_enable,
3804         .disable           = mlx5e_nic_disable,
3805         .update_stats      = mlx5e_update_stats,
3806         .max_nch           = mlx5e_get_max_num_channels,
3807         .max_tc            = MLX5E_MAX_NUM_TC,
3808 };
3809
3810 struct net_device *mlx5e_create_netdev(struct mlx5_core_dev *mdev,
3811                                        const struct mlx5e_profile *profile,
3812                                        void *ppriv)
3813 {
3814         int nch = profile->max_nch(mdev);
3815         struct net_device *netdev;
3816         struct mlx5e_priv *priv;
3817
3818         netdev = alloc_etherdev_mqs(sizeof(struct mlx5e_priv),
3819                                     nch * profile->max_tc,
3820                                     nch);
3821         if (!netdev) {
3822                 mlx5_core_err(mdev, "alloc_etherdev_mqs() failed\n");
3823                 return NULL;
3824         }
3825
3826         profile->init(mdev, netdev, profile, ppriv);
3827
3828         netif_carrier_off(netdev);
3829
3830         priv = netdev_priv(netdev);
3831
3832         priv->wq = create_singlethread_workqueue("mlx5e");
3833         if (!priv->wq)
3834                 goto err_cleanup_nic;
3835
3836         return netdev;
3837
3838 err_cleanup_nic:
3839         profile->cleanup(priv);
3840         free_netdev(netdev);
3841
3842         return NULL;
3843 }
3844
3845 int mlx5e_attach_netdev(struct mlx5_core_dev *mdev, struct net_device *netdev)
3846 {
3847         const struct mlx5e_profile *profile;
3848         struct mlx5e_priv *priv;
3849         u16 max_mtu;
3850         int err;
3851
3852         priv = netdev_priv(netdev);
3853         profile = priv->profile;
3854         clear_bit(MLX5E_STATE_DESTROYING, &priv->state);
3855
3856         err = mlx5e_create_umr_mkey(priv);
3857         if (err) {
3858                 mlx5_core_err(mdev, "create umr mkey failed, %d\n", err);
3859                 goto out;
3860         }
3861
3862         err = profile->init_tx(priv);
3863         if (err)
3864                 goto err_destroy_umr_mkey;
3865
3866         err = mlx5e_open_drop_rq(priv);
3867         if (err) {
3868                 mlx5_core_err(mdev, "open drop rq failed, %d\n", err);
3869                 goto err_cleanup_tx;
3870         }
3871
3872         err = profile->init_rx(priv);
3873         if (err)
3874                 goto err_close_drop_rq;
3875
3876         mlx5e_create_q_counter(priv);
3877
3878         mlx5e_init_l2_addr(priv);
3879
3880         /* MTU range: 68 - hw-specific max */
3881         netdev->min_mtu = ETH_MIN_MTU;
3882         mlx5_query_port_max_mtu(priv->mdev, &max_mtu, 1);
3883         netdev->max_mtu = MLX5E_HW2SW_MTU(max_mtu);
3884
3885         mlx5e_set_dev_port_mtu(netdev);
3886
3887         if (profile->enable)
3888                 profile->enable(priv);
3889
3890         rtnl_lock();
3891         if (netif_running(netdev))
3892                 mlx5e_open(netdev);
3893         netif_device_attach(netdev);
3894         rtnl_unlock();
3895
3896         return 0;
3897
3898 err_close_drop_rq:
3899         mlx5e_close_drop_rq(priv);
3900
3901 err_cleanup_tx:
3902         profile->cleanup_tx(priv);
3903
3904 err_destroy_umr_mkey:
3905         mlx5_core_destroy_mkey(mdev, &priv->umr_mkey);
3906
3907 out:
3908         return err;
3909 }
3910
3911 static void mlx5e_register_vport_rep(struct mlx5_core_dev *mdev)
3912 {
3913         struct mlx5_eswitch *esw = mdev->priv.eswitch;
3914         int total_vfs = MLX5_TOTAL_VPORTS(mdev);
3915         int vport;
3916         u8 mac[ETH_ALEN];
3917
3918         if (!MLX5_CAP_GEN(mdev, vport_group_manager))
3919                 return;
3920
3921         mlx5_query_nic_vport_mac_address(mdev, 0, mac);
3922
3923         for (vport = 1; vport < total_vfs; vport++) {
3924                 struct mlx5_eswitch_rep rep;
3925
3926                 rep.load = mlx5e_vport_rep_load;
3927                 rep.unload = mlx5e_vport_rep_unload;
3928                 rep.vport = vport;
3929                 ether_addr_copy(rep.hw_id, mac);
3930                 mlx5_eswitch_register_vport_rep(esw, vport, &rep);
3931         }
3932 }
3933
3934 void mlx5e_detach_netdev(struct mlx5_core_dev *mdev, struct net_device *netdev)
3935 {
3936         struct mlx5e_priv *priv = netdev_priv(netdev);
3937         const struct mlx5e_profile *profile = priv->profile;
3938
3939         set_bit(MLX5E_STATE_DESTROYING, &priv->state);
3940         if (profile->disable)
3941                 profile->disable(priv);
3942
3943         flush_workqueue(priv->wq);
3944
3945         rtnl_lock();
3946         if (netif_running(netdev))
3947                 mlx5e_close(netdev);
3948         netif_device_detach(netdev);
3949         rtnl_unlock();
3950
3951         mlx5e_destroy_q_counter(priv);
3952         profile->cleanup_rx(priv);
3953         mlx5e_close_drop_rq(priv);
3954         profile->cleanup_tx(priv);
3955         mlx5_core_destroy_mkey(priv->mdev, &priv->umr_mkey);
3956         cancel_delayed_work_sync(&priv->update_stats_work);
3957 }
3958
3959 /* mlx5e_attach and mlx5e_detach scope should be only creating/destroying
3960  * hardware contexts and to connect it to the current netdev.
3961  */
3962 static int mlx5e_attach(struct mlx5_core_dev *mdev, void *vpriv)
3963 {
3964         struct mlx5e_priv *priv = vpriv;
3965         struct net_device *netdev = priv->netdev;
3966         int err;
3967
3968         if (netif_device_present(netdev))
3969                 return 0;
3970
3971         err = mlx5e_create_mdev_resources(mdev);
3972         if (err)
3973                 return err;
3974
3975         err = mlx5e_attach_netdev(mdev, netdev);
3976         if (err) {
3977                 mlx5e_destroy_mdev_resources(mdev);
3978                 return err;
3979         }
3980
3981         return 0;
3982 }
3983
3984 static void mlx5e_detach(struct mlx5_core_dev *mdev, void *vpriv)
3985 {
3986         struct mlx5e_priv *priv = vpriv;
3987         struct net_device *netdev = priv->netdev;
3988
3989         if (!netif_device_present(netdev))
3990                 return;
3991
3992         mlx5e_detach_netdev(mdev, netdev);
3993         mlx5e_destroy_mdev_resources(mdev);
3994 }
3995
3996 static void *mlx5e_add(struct mlx5_core_dev *mdev)
3997 {
3998         struct mlx5_eswitch *esw = mdev->priv.eswitch;
3999         int total_vfs = MLX5_TOTAL_VPORTS(mdev);
4000         void *ppriv = NULL;
4001         void *priv;
4002         int vport;
4003         int err;
4004         struct net_device *netdev;
4005
4006         err = mlx5e_check_required_hca_cap(mdev);
4007         if (err)
4008                 return NULL;
4009
4010         mlx5e_register_vport_rep(mdev);
4011
4012         if (MLX5_CAP_GEN(mdev, vport_group_manager))
4013                 ppriv = &esw->offloads.vport_reps[0];
4014
4015         netdev = mlx5e_create_netdev(mdev, &mlx5e_nic_profile, ppriv);
4016         if (!netdev) {
4017                 mlx5_core_err(mdev, "mlx5e_create_netdev failed\n");
4018                 goto err_unregister_reps;
4019         }
4020
4021         priv = netdev_priv(netdev);
4022
4023         err = mlx5e_attach(mdev, priv);
4024         if (err) {
4025                 mlx5_core_err(mdev, "mlx5e_attach failed, %d\n", err);
4026                 goto err_destroy_netdev;
4027         }
4028
4029         err = register_netdev(netdev);
4030         if (err) {
4031                 mlx5_core_err(mdev, "register_netdev failed, %d\n", err);
4032                 goto err_detach;
4033         }
4034
4035         return priv;
4036
4037 err_detach:
4038         mlx5e_detach(mdev, priv);
4039
4040 err_destroy_netdev:
4041         mlx5e_destroy_netdev(mdev, priv);
4042
4043 err_unregister_reps:
4044         for (vport = 1; vport < total_vfs; vport++)
4045                 mlx5_eswitch_unregister_vport_rep(esw, vport);
4046
4047         return NULL;
4048 }
4049
4050 void mlx5e_destroy_netdev(struct mlx5_core_dev *mdev, struct mlx5e_priv *priv)
4051 {
4052         const struct mlx5e_profile *profile = priv->profile;
4053         struct net_device *netdev = priv->netdev;
4054
4055         destroy_workqueue(priv->wq);
4056         if (profile->cleanup)
4057                 profile->cleanup(priv);
4058         free_netdev(netdev);
4059 }
4060
4061 static void mlx5e_remove(struct mlx5_core_dev *mdev, void *vpriv)
4062 {
4063         struct mlx5_eswitch *esw = mdev->priv.eswitch;
4064         int total_vfs = MLX5_TOTAL_VPORTS(mdev);
4065         struct mlx5e_priv *priv = vpriv;
4066         int vport;
4067
4068         for (vport = 1; vport < total_vfs; vport++)
4069                 mlx5_eswitch_unregister_vport_rep(esw, vport);
4070
4071         unregister_netdev(priv->netdev);
4072         mlx5e_detach(mdev, vpriv);
4073         mlx5e_destroy_netdev(mdev, priv);
4074 }
4075
4076 static void *mlx5e_get_netdev(void *vpriv)
4077 {
4078         struct mlx5e_priv *priv = vpriv;
4079
4080         return priv->netdev;
4081 }
4082
4083 static struct mlx5_interface mlx5e_interface = {
4084         .add       = mlx5e_add,
4085         .remove    = mlx5e_remove,
4086         .attach    = mlx5e_attach,
4087         .detach    = mlx5e_detach,
4088         .event     = mlx5e_async_event,
4089         .protocol  = MLX5_INTERFACE_PROTOCOL_ETH,
4090         .get_dev   = mlx5e_get_netdev,
4091 };
4092
4093 void mlx5e_init(void)
4094 {
4095         mlx5e_build_ptys2ethtool_map();
4096         mlx5_register_interface(&mlx5e_interface);
4097 }
4098
4099 void mlx5e_cleanup(void)
4100 {
4101         mlx5_unregister_interface(&mlx5e_interface);
4102 }