2 * Copyright (c) 2015-2016, Mellanox Technologies. All rights reserved.
4 * This software is available to you under a choice of one of two
5 * licenses. You may choose to be licensed under the terms of the GNU
6 * General Public License (GPL) Version 2, available from the file
7 * COPYING in the main directory of this source tree, or the
8 * OpenIB.org BSD license below:
10 * Redistribution and use in source and binary forms, with or
11 * without modification, are permitted provided that the following
14 * - Redistributions of source code must retain the above
15 * copyright notice, this list of conditions and the following
18 * - Redistributions in binary form must reproduce the above
19 * copyright notice, this list of conditions and the following
20 * disclaimer in the documentation and/or other materials
21 * provided with the distribution.
23 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
24 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
25 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
26 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
27 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
28 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
29 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
33 #include <net/tc_act/tc_gact.h>
34 #include <net/pkt_cls.h>
35 #include <linux/mlx5/fs.h>
36 #include <net/vxlan.h>
37 #include <net/geneve.h>
38 #include <linux/bpf.h>
39 #include <linux/if_bridge.h>
40 #include <net/page_pool.h>
41 #include <net/xdp_sock_drv.h>
47 #include "en_accel/ipsec.h"
48 #include "en_accel/en_accel.h"
49 #include "en_accel/tls.h"
50 #include "accel/ipsec.h"
51 #include "accel/tls.h"
52 #include "lib/vxlan.h"
53 #include "lib/clock.h"
57 #include "en/monitor_stats.h"
58 #include "en/health.h"
59 #include "en/params.h"
60 #include "en/xsk/pool.h"
61 #include "en/xsk/setup.h"
62 #include "en/xsk/rx.h"
63 #include "en/xsk/tx.h"
64 #include "en/hv_vhca_stats.h"
65 #include "en/devlink.h"
71 bool mlx5e_check_fragmented_striding_rq_cap(struct mlx5_core_dev *mdev)
73 bool striding_rq_umr = MLX5_CAP_GEN(mdev, striding_rq) &&
74 MLX5_CAP_GEN(mdev, umr_ptr_rlky) &&
75 MLX5_CAP_ETH(mdev, reg_umr_sq);
76 u16 max_wqe_sz_cap = MLX5_CAP_GEN(mdev, max_wqe_sz_sq);
77 bool inline_umr = MLX5E_UMR_WQE_INLINE_SZ <= max_wqe_sz_cap;
82 mlx5_core_warn(mdev, "Cannot support Striding RQ: UMR WQE size (%d) exceeds maximum supported (%d).\n",
83 (int)MLX5E_UMR_WQE_INLINE_SZ, max_wqe_sz_cap);
89 void mlx5e_init_rq_type_params(struct mlx5_core_dev *mdev,
90 struct mlx5e_params *params)
92 params->log_rq_mtu_frames = is_kdump_kernel() ?
93 MLX5E_PARAMS_MINIMUM_LOG_RQ_SIZE :
94 MLX5E_PARAMS_DEFAULT_LOG_RQ_SIZE;
96 mlx5_core_info(mdev, "MLX5E: StrdRq(%d) RqSz(%ld) StrdSz(%ld) RxCqeCmprss(%d)\n",
97 params->rq_wq_type == MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ,
98 params->rq_wq_type == MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ ?
99 BIT(mlx5e_mpwqe_get_log_rq_size(params, NULL)) :
100 BIT(params->log_rq_mtu_frames),
101 BIT(mlx5e_mpwqe_get_log_stride_size(mdev, params, NULL)),
102 MLX5E_GET_PFLAG(params, MLX5E_PFLAG_RX_CQE_COMPRESS));
105 bool mlx5e_striding_rq_possible(struct mlx5_core_dev *mdev,
106 struct mlx5e_params *params)
108 if (!mlx5e_check_fragmented_striding_rq_cap(mdev))
111 if (MLX5_IPSEC_DEV(mdev))
114 if (params->xdp_prog) {
115 /* XSK params are not considered here. If striding RQ is in use,
116 * and an XSK is being opened, mlx5e_rx_mpwqe_is_linear_skb will
117 * be called with the known XSK params.
119 if (!mlx5e_rx_mpwqe_is_linear_skb(mdev, params, NULL))
126 void mlx5e_set_rq_type(struct mlx5_core_dev *mdev, struct mlx5e_params *params)
128 params->rq_wq_type = mlx5e_striding_rq_possible(mdev, params) &&
129 MLX5E_GET_PFLAG(params, MLX5E_PFLAG_RX_STRIDING_RQ) ?
130 MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ :
134 void mlx5e_update_carrier(struct mlx5e_priv *priv)
136 struct mlx5_core_dev *mdev = priv->mdev;
139 port_state = mlx5_query_vport_state(mdev,
140 MLX5_VPORT_STATE_OP_MOD_VNIC_VPORT,
143 if (port_state == VPORT_STATE_UP) {
144 netdev_info(priv->netdev, "Link up\n");
145 netif_carrier_on(priv->netdev);
147 netdev_info(priv->netdev, "Link down\n");
148 netif_carrier_off(priv->netdev);
152 static void mlx5e_update_carrier_work(struct work_struct *work)
154 struct mlx5e_priv *priv = container_of(work, struct mlx5e_priv,
155 update_carrier_work);
157 mutex_lock(&priv->state_lock);
158 if (test_bit(MLX5E_STATE_OPENED, &priv->state))
159 if (priv->profile->update_carrier)
160 priv->profile->update_carrier(priv);
161 mutex_unlock(&priv->state_lock);
164 static void mlx5e_update_stats_work(struct work_struct *work)
166 struct mlx5e_priv *priv = container_of(work, struct mlx5e_priv,
169 mutex_lock(&priv->state_lock);
170 priv->profile->update_stats(priv);
171 mutex_unlock(&priv->state_lock);
174 void mlx5e_queue_update_stats(struct mlx5e_priv *priv)
176 if (!priv->profile->update_stats)
179 if (unlikely(test_bit(MLX5E_STATE_DESTROYING, &priv->state)))
182 queue_work(priv->wq, &priv->update_stats_work);
185 static int async_event(struct notifier_block *nb, unsigned long event, void *data)
187 struct mlx5e_priv *priv = container_of(nb, struct mlx5e_priv, events_nb);
188 struct mlx5_eqe *eqe = data;
190 if (event != MLX5_EVENT_TYPE_PORT_CHANGE)
193 switch (eqe->sub_type) {
194 case MLX5_PORT_CHANGE_SUBTYPE_DOWN:
195 case MLX5_PORT_CHANGE_SUBTYPE_ACTIVE:
196 queue_work(priv->wq, &priv->update_carrier_work);
205 static void mlx5e_enable_async_events(struct mlx5e_priv *priv)
207 priv->events_nb.notifier_call = async_event;
208 mlx5_notifier_register(priv->mdev, &priv->events_nb);
211 static void mlx5e_disable_async_events(struct mlx5e_priv *priv)
213 mlx5_notifier_unregister(priv->mdev, &priv->events_nb);
216 static int blocking_event(struct notifier_block *nb, unsigned long event, void *data)
218 struct mlx5e_priv *priv = container_of(nb, struct mlx5e_priv, blocking_events_nb);
222 case MLX5_DRIVER_EVENT_TYPE_TRAP:
223 err = mlx5e_handle_trap_event(priv, data);
226 netdev_warn(priv->netdev, "Sync event: Unknouwn event %ld\n", event);
232 static void mlx5e_enable_blocking_events(struct mlx5e_priv *priv)
234 priv->blocking_events_nb.notifier_call = blocking_event;
235 mlx5_blocking_notifier_register(priv->mdev, &priv->blocking_events_nb);
238 static void mlx5e_disable_blocking_events(struct mlx5e_priv *priv)
240 mlx5_blocking_notifier_unregister(priv->mdev, &priv->blocking_events_nb);
243 static inline void mlx5e_build_umr_wqe(struct mlx5e_rq *rq,
244 struct mlx5e_icosq *sq,
245 struct mlx5e_umr_wqe *wqe)
247 struct mlx5_wqe_ctrl_seg *cseg = &wqe->ctrl;
248 struct mlx5_wqe_umr_ctrl_seg *ucseg = &wqe->uctrl;
249 u8 ds_cnt = DIV_ROUND_UP(MLX5E_UMR_WQE_INLINE_SZ, MLX5_SEND_WQE_DS);
251 cseg->qpn_ds = cpu_to_be32((sq->sqn << MLX5_WQE_CTRL_QPN_SHIFT) |
253 cseg->umr_mkey = rq->mkey_be;
255 ucseg->flags = MLX5_UMR_TRANSLATION_OFFSET_EN | MLX5_UMR_INLINE;
256 ucseg->xlt_octowords =
257 cpu_to_be16(MLX5_MTT_OCTW(MLX5_MPWRQ_PAGES_PER_WQE));
258 ucseg->mkey_mask = cpu_to_be64(MLX5_MKEY_MASK_FREE);
261 static int mlx5e_rq_alloc_mpwqe_info(struct mlx5e_rq *rq,
262 struct mlx5e_channel *c)
264 int wq_sz = mlx5_wq_ll_get_size(&rq->mpwqe.wq);
266 rq->mpwqe.info = kvzalloc_node(array_size(wq_sz,
267 sizeof(*rq->mpwqe.info)),
268 GFP_KERNEL, cpu_to_node(c->cpu));
272 mlx5e_build_umr_wqe(rq, &c->icosq, &rq->mpwqe.umr_wqe);
277 static int mlx5e_create_umr_mkey(struct mlx5_core_dev *mdev,
278 u64 npages, u8 page_shift,
279 struct mlx5_core_mkey *umr_mkey,
280 dma_addr_t filler_addr)
282 struct mlx5_mtt *mtt;
289 inlen = MLX5_ST_SZ_BYTES(create_mkey_in) + sizeof(*mtt) * npages;
291 in = kvzalloc(inlen, GFP_KERNEL);
295 mkc = MLX5_ADDR_OF(create_mkey_in, in, memory_key_mkey_entry);
297 MLX5_SET(mkc, mkc, free, 1);
298 MLX5_SET(mkc, mkc, umr_en, 1);
299 MLX5_SET(mkc, mkc, lw, 1);
300 MLX5_SET(mkc, mkc, lr, 1);
301 MLX5_SET(mkc, mkc, access_mode_1_0, MLX5_MKC_ACCESS_MODE_MTT);
302 mlx5e_mkey_set_relaxed_ordering(mdev, mkc);
303 MLX5_SET(mkc, mkc, qpn, 0xffffff);
304 MLX5_SET(mkc, mkc, pd, mdev->mlx5e_res.pdn);
305 MLX5_SET64(mkc, mkc, len, npages << page_shift);
306 MLX5_SET(mkc, mkc, translations_octword_size,
307 MLX5_MTT_OCTW(npages));
308 MLX5_SET(mkc, mkc, log_page_size, page_shift);
309 MLX5_SET(create_mkey_in, in, translations_octword_actual_size,
310 MLX5_MTT_OCTW(npages));
312 /* Initialize the mkey with all MTTs pointing to a default
313 * page (filler_addr). When the channels are activated, UMR
314 * WQEs will redirect the RX WQEs to the actual memory from
315 * the RQ's pool, while the gaps (wqe_overflow) remain mapped
316 * to the default page.
318 mtt = MLX5_ADDR_OF(create_mkey_in, in, klm_pas_mtt);
319 for (i = 0 ; i < npages ; i++)
320 mtt[i].ptag = cpu_to_be64(filler_addr);
322 err = mlx5_core_create_mkey(mdev, umr_mkey, in, inlen);
328 static int mlx5e_create_rq_umr_mkey(struct mlx5_core_dev *mdev, struct mlx5e_rq *rq)
330 u64 num_mtts = MLX5E_REQUIRED_MTTS(mlx5_wq_ll_get_size(&rq->mpwqe.wq));
332 return mlx5e_create_umr_mkey(mdev, num_mtts, PAGE_SHIFT, &rq->umr_mkey,
333 rq->wqe_overflow.addr);
336 static inline u64 mlx5e_get_mpwqe_offset(struct mlx5e_rq *rq, u16 wqe_ix)
338 return (wqe_ix << MLX5E_LOG_ALIGNED_MPWQE_PPW) << PAGE_SHIFT;
341 static void mlx5e_init_frags_partition(struct mlx5e_rq *rq)
343 struct mlx5e_wqe_frag_info next_frag = {};
344 struct mlx5e_wqe_frag_info *prev = NULL;
347 next_frag.di = &rq->wqe.di[0];
349 for (i = 0; i < mlx5_wq_cyc_get_size(&rq->wqe.wq); i++) {
350 struct mlx5e_rq_frag_info *frag_info = &rq->wqe.info.arr[0];
351 struct mlx5e_wqe_frag_info *frag =
352 &rq->wqe.frags[i << rq->wqe.info.log_num_frags];
355 for (f = 0; f < rq->wqe.info.num_frags; f++, frag++) {
356 if (next_frag.offset + frag_info[f].frag_stride > PAGE_SIZE) {
358 next_frag.offset = 0;
360 prev->last_in_page = true;
365 next_frag.offset += frag_info[f].frag_stride;
371 prev->last_in_page = true;
374 int mlx5e_init_di_list(struct mlx5e_rq *rq, int wq_sz, int node)
376 int len = wq_sz << rq->wqe.info.log_num_frags;
378 rq->wqe.di = kvzalloc_node(array_size(len, sizeof(*rq->wqe.di)), GFP_KERNEL, node);
382 mlx5e_init_frags_partition(rq);
387 void mlx5e_free_di_list(struct mlx5e_rq *rq)
392 static void mlx5e_rq_err_cqe_work(struct work_struct *recover_work)
394 struct mlx5e_rq *rq = container_of(recover_work, struct mlx5e_rq, recover_work);
396 mlx5e_reporter_rq_cqe_err(rq);
399 static int mlx5e_alloc_mpwqe_rq_drop_page(struct mlx5e_rq *rq)
401 rq->wqe_overflow.page = alloc_page(GFP_KERNEL);
402 if (!rq->wqe_overflow.page)
405 rq->wqe_overflow.addr = dma_map_page(rq->pdev, rq->wqe_overflow.page, 0,
406 PAGE_SIZE, rq->buff.map_dir);
407 if (dma_mapping_error(rq->pdev, rq->wqe_overflow.addr)) {
408 __free_page(rq->wqe_overflow.page);
414 static void mlx5e_free_mpwqe_rq_drop_page(struct mlx5e_rq *rq)
416 dma_unmap_page(rq->pdev, rq->wqe_overflow.addr, PAGE_SIZE,
418 __free_page(rq->wqe_overflow.page);
421 static int mlx5e_alloc_rq(struct mlx5e_channel *c,
422 struct mlx5e_params *params,
423 struct mlx5e_xsk_param *xsk,
424 struct xsk_buff_pool *xsk_pool,
425 struct mlx5e_rq_param *rqp,
428 struct page_pool_params pp_params = { 0 };
429 struct mlx5_core_dev *mdev = c->mdev;
430 void *rqc = rqp->rqc;
431 void *rqc_wq = MLX5_ADDR_OF(rqc, rqc, wq);
438 rqp->wq.db_numa_node = cpu_to_node(c->cpu);
440 rq->wq_type = params->rq_wq_type;
442 rq->netdev = c->netdev;
444 rq->tstamp = c->tstamp;
445 rq->clock = &mdev->clock;
446 rq->icosq = &c->icosq;
449 rq->hw_mtu = MLX5E_SW2HW_MTU(params, params->sw_mtu);
450 rq->xdpsq = &c->rq_xdpsq;
451 rq->xsk_pool = xsk_pool;
454 rq->stats = &c->priv->channel_stats[c->ix].xskrq;
456 rq->stats = &c->priv->channel_stats[c->ix].rq;
457 INIT_WORK(&rq->recover_work, mlx5e_rq_err_cqe_work);
459 if (params->xdp_prog)
460 bpf_prog_inc(params->xdp_prog);
461 RCU_INIT_POINTER(rq->xdp_prog, params->xdp_prog);
465 rq_xdp_ix += params->num_channels * MLX5E_RQ_GROUP_XSK;
466 err = xdp_rxq_info_reg(&rq->xdp_rxq, rq->netdev, rq_xdp_ix, 0);
468 goto err_rq_xdp_prog;
470 rq->buff.map_dir = params->xdp_prog ? DMA_BIDIRECTIONAL : DMA_FROM_DEVICE;
471 rq->buff.headroom = mlx5e_get_rq_headroom(mdev, params, xsk);
472 pool_size = 1 << params->log_rq_mtu_frames;
474 switch (rq->wq_type) {
475 case MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ:
476 err = mlx5_wq_ll_create(mdev, &rqp->wq, rqc_wq, &rq->mpwqe.wq,
481 err = mlx5e_alloc_mpwqe_rq_drop_page(rq);
483 goto err_rq_wq_destroy;
485 rq->mpwqe.wq.db = &rq->mpwqe.wq.db[MLX5_RCV_DBR];
487 wq_sz = mlx5_wq_ll_get_size(&rq->mpwqe.wq);
489 pool_size = MLX5_MPWRQ_PAGES_PER_WQE <<
490 mlx5e_mpwqe_get_log_rq_size(params, xsk);
492 rq->mpwqe.log_stride_sz = mlx5e_mpwqe_get_log_stride_size(mdev, params, xsk);
493 rq->mpwqe.num_strides =
494 BIT(mlx5e_mpwqe_get_log_num_strides(mdev, params, xsk));
496 rq->buff.frame0_sz = (1 << rq->mpwqe.log_stride_sz);
498 err = mlx5e_create_rq_umr_mkey(mdev, rq);
500 goto err_rq_drop_page;
501 rq->mkey_be = cpu_to_be32(rq->umr_mkey.key);
503 err = mlx5e_rq_alloc_mpwqe_info(rq, c);
507 default: /* MLX5_WQ_TYPE_CYCLIC */
508 err = mlx5_wq_cyc_create(mdev, &rqp->wq, rqc_wq, &rq->wqe.wq,
513 rq->wqe.wq.db = &rq->wqe.wq.db[MLX5_RCV_DBR];
515 wq_sz = mlx5_wq_cyc_get_size(&rq->wqe.wq);
517 rq->wqe.info = rqp->frags_info;
518 rq->buff.frame0_sz = rq->wqe.info.arr[0].frag_stride;
521 kvzalloc_node(array_size(sizeof(*rq->wqe.frags),
522 (wq_sz << rq->wqe.info.log_num_frags)),
523 GFP_KERNEL, cpu_to_node(c->cpu));
524 if (!rq->wqe.frags) {
526 goto err_rq_wq_destroy;
529 err = mlx5e_init_di_list(rq, wq_sz, cpu_to_node(c->cpu));
533 rq->mkey_be = c->mkey_be;
536 err = mlx5e_rq_set_handlers(rq, params, xsk);
538 goto err_free_by_rq_type;
541 err = xdp_rxq_info_reg_mem_model(&rq->xdp_rxq,
542 MEM_TYPE_XSK_BUFF_POOL, NULL);
543 xsk_pool_set_rxq_info(rq->xsk_pool, &rq->xdp_rxq);
545 /* Create a page_pool and register it with rxq */
547 pp_params.flags = 0; /* No-internal DMA mapping in page_pool */
548 pp_params.pool_size = pool_size;
549 pp_params.nid = cpu_to_node(c->cpu);
550 pp_params.dev = c->pdev;
551 pp_params.dma_dir = rq->buff.map_dir;
553 /* page_pool can be used even when there is no rq->xdp_prog,
554 * given page_pool does not handle DMA mapping there is no
555 * required state to clear. And page_pool gracefully handle
558 rq->page_pool = page_pool_create(&pp_params);
559 if (IS_ERR(rq->page_pool)) {
560 err = PTR_ERR(rq->page_pool);
561 rq->page_pool = NULL;
562 goto err_free_by_rq_type;
564 err = xdp_rxq_info_reg_mem_model(&rq->xdp_rxq,
565 MEM_TYPE_PAGE_POOL, rq->page_pool);
568 goto err_free_by_rq_type;
570 for (i = 0; i < wq_sz; i++) {
571 if (rq->wq_type == MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ) {
572 struct mlx5e_rx_wqe_ll *wqe =
573 mlx5_wq_ll_get_wqe(&rq->mpwqe.wq, i);
575 rq->mpwqe.num_strides << rq->mpwqe.log_stride_sz;
576 u64 dma_offset = mlx5e_get_mpwqe_offset(rq, i);
578 wqe->data[0].addr = cpu_to_be64(dma_offset + rq->buff.headroom);
579 wqe->data[0].byte_count = cpu_to_be32(byte_count);
580 wqe->data[0].lkey = rq->mkey_be;
582 struct mlx5e_rx_wqe_cyc *wqe =
583 mlx5_wq_cyc_get_wqe(&rq->wqe.wq, i);
586 for (f = 0; f < rq->wqe.info.num_frags; f++) {
587 u32 frag_size = rq->wqe.info.arr[f].frag_size |
588 MLX5_HW_START_PADDING;
590 wqe->data[f].byte_count = cpu_to_be32(frag_size);
591 wqe->data[f].lkey = rq->mkey_be;
593 /* check if num_frags is not a pow of two */
594 if (rq->wqe.info.num_frags < (1 << rq->wqe.info.log_num_frags)) {
595 wqe->data[f].byte_count = 0;
596 wqe->data[f].lkey = cpu_to_be32(MLX5_INVALID_LKEY);
597 wqe->data[f].addr = 0;
602 INIT_WORK(&rq->dim.work, mlx5e_rx_dim_work);
604 switch (params->rx_cq_moderation.cq_period_mode) {
605 case MLX5_CQ_PERIOD_MODE_START_FROM_CQE:
606 rq->dim.mode = DIM_CQ_PERIOD_MODE_START_FROM_CQE;
608 case MLX5_CQ_PERIOD_MODE_START_FROM_EQE:
610 rq->dim.mode = DIM_CQ_PERIOD_MODE_START_FROM_EQE;
613 rq->page_cache.head = 0;
614 rq->page_cache.tail = 0;
619 switch (rq->wq_type) {
620 case MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ:
621 kvfree(rq->mpwqe.info);
623 mlx5_core_destroy_mkey(mdev, &rq->umr_mkey);
625 mlx5e_free_mpwqe_rq_drop_page(rq);
627 default: /* MLX5_WQ_TYPE_CYCLIC */
628 mlx5e_free_di_list(rq);
630 kvfree(rq->wqe.frags);
633 mlx5_wq_destroy(&rq->wq_ctrl);
635 xdp_rxq_info_unreg(&rq->xdp_rxq);
637 if (params->xdp_prog)
638 bpf_prog_put(params->xdp_prog);
643 static void mlx5e_free_rq(struct mlx5e_rq *rq)
645 struct bpf_prog *old_prog;
648 old_prog = rcu_dereference_protected(rq->xdp_prog,
649 lockdep_is_held(&rq->priv->state_lock));
651 bpf_prog_put(old_prog);
653 switch (rq->wq_type) {
654 case MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ:
655 kvfree(rq->mpwqe.info);
656 mlx5_core_destroy_mkey(rq->mdev, &rq->umr_mkey);
657 mlx5e_free_mpwqe_rq_drop_page(rq);
659 default: /* MLX5_WQ_TYPE_CYCLIC */
660 kvfree(rq->wqe.frags);
661 mlx5e_free_di_list(rq);
664 for (i = rq->page_cache.head; i != rq->page_cache.tail;
665 i = (i + 1) & (MLX5E_CACHE_SIZE - 1)) {
666 struct mlx5e_dma_info *dma_info = &rq->page_cache.page_cache[i];
668 /* With AF_XDP, page_cache is not used, so this loop is not
669 * entered, and it's safe to call mlx5e_page_release_dynamic
672 mlx5e_page_release_dynamic(rq, dma_info, false);
675 xdp_rxq_info_unreg(&rq->xdp_rxq);
676 page_pool_destroy(rq->page_pool);
677 mlx5_wq_destroy(&rq->wq_ctrl);
680 int mlx5e_create_rq(struct mlx5e_rq *rq, struct mlx5e_rq_param *param)
682 struct mlx5_core_dev *mdev = rq->mdev;
690 inlen = MLX5_ST_SZ_BYTES(create_rq_in) +
691 sizeof(u64) * rq->wq_ctrl.buf.npages;
692 in = kvzalloc(inlen, GFP_KERNEL);
696 rqc = MLX5_ADDR_OF(create_rq_in, in, ctx);
697 wq = MLX5_ADDR_OF(rqc, rqc, wq);
699 memcpy(rqc, param->rqc, sizeof(param->rqc));
701 MLX5_SET(rqc, rqc, cqn, rq->cq.mcq.cqn);
702 MLX5_SET(rqc, rqc, state, MLX5_RQC_STATE_RST);
703 MLX5_SET(wq, wq, log_wq_pg_sz, rq->wq_ctrl.buf.page_shift -
704 MLX5_ADAPTER_PAGE_SHIFT);
705 MLX5_SET64(wq, wq, dbr_addr, rq->wq_ctrl.db.dma);
707 mlx5_fill_page_frag_array(&rq->wq_ctrl.buf,
708 (__be64 *)MLX5_ADDR_OF(wq, wq, pas));
710 err = mlx5_core_create_rq(mdev, in, inlen, &rq->rqn);
717 int mlx5e_modify_rq_state(struct mlx5e_rq *rq, int curr_state, int next_state)
719 struct mlx5_core_dev *mdev = rq->mdev;
726 inlen = MLX5_ST_SZ_BYTES(modify_rq_in);
727 in = kvzalloc(inlen, GFP_KERNEL);
731 if (curr_state == MLX5_RQC_STATE_RST && next_state == MLX5_RQC_STATE_RDY)
732 mlx5e_rqwq_reset(rq);
734 rqc = MLX5_ADDR_OF(modify_rq_in, in, ctx);
736 MLX5_SET(modify_rq_in, in, rq_state, curr_state);
737 MLX5_SET(rqc, rqc, state, next_state);
739 err = mlx5_core_modify_rq(mdev, rq->rqn, in);
746 static int mlx5e_modify_rq_scatter_fcs(struct mlx5e_rq *rq, bool enable)
748 struct mlx5_core_dev *mdev = rq->mdev;
755 inlen = MLX5_ST_SZ_BYTES(modify_rq_in);
756 in = kvzalloc(inlen, GFP_KERNEL);
760 rqc = MLX5_ADDR_OF(modify_rq_in, in, ctx);
762 MLX5_SET(modify_rq_in, in, rq_state, MLX5_RQC_STATE_RDY);
763 MLX5_SET64(modify_rq_in, in, modify_bitmask,
764 MLX5_MODIFY_RQ_IN_MODIFY_BITMASK_SCATTER_FCS);
765 MLX5_SET(rqc, rqc, scatter_fcs, enable);
766 MLX5_SET(rqc, rqc, state, MLX5_RQC_STATE_RDY);
768 err = mlx5_core_modify_rq(mdev, rq->rqn, in);
775 static int mlx5e_modify_rq_vsd(struct mlx5e_rq *rq, bool vsd)
777 struct mlx5_core_dev *mdev = rq->mdev;
783 inlen = MLX5_ST_SZ_BYTES(modify_rq_in);
784 in = kvzalloc(inlen, GFP_KERNEL);
788 rqc = MLX5_ADDR_OF(modify_rq_in, in, ctx);
790 MLX5_SET(modify_rq_in, in, rq_state, MLX5_RQC_STATE_RDY);
791 MLX5_SET64(modify_rq_in, in, modify_bitmask,
792 MLX5_MODIFY_RQ_IN_MODIFY_BITMASK_VSD);
793 MLX5_SET(rqc, rqc, vsd, vsd);
794 MLX5_SET(rqc, rqc, state, MLX5_RQC_STATE_RDY);
796 err = mlx5_core_modify_rq(mdev, rq->rqn, in);
803 void mlx5e_destroy_rq(struct mlx5e_rq *rq)
805 mlx5_core_destroy_rq(rq->mdev, rq->rqn);
808 int mlx5e_wait_for_min_rx_wqes(struct mlx5e_rq *rq, int wait_time)
810 unsigned long exp_time = jiffies + msecs_to_jiffies(wait_time);
812 u16 min_wqes = mlx5_min_rx_wqes(rq->wq_type, mlx5e_rqwq_get_size(rq));
815 if (mlx5e_rqwq_get_cur_sz(rq) >= min_wqes)
819 } while (time_before(jiffies, exp_time));
821 netdev_warn(rq->netdev, "Failed to get min RX wqes on Channel[%d] RQN[0x%x] wq cur_sz(%d) min_rx_wqes(%d)\n",
822 rq->ix, rq->rqn, mlx5e_rqwq_get_cur_sz(rq), min_wqes);
824 mlx5e_reporter_rx_timeout(rq);
828 void mlx5e_free_rx_in_progress_descs(struct mlx5e_rq *rq)
830 struct mlx5_wq_ll *wq;
834 if (rq->wq_type != MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ)
840 /* Outstanding UMR WQEs (in progress) start at wq->head */
841 for (i = 0; i < rq->mpwqe.umr_in_progress; i++) {
842 rq->dealloc_wqe(rq, head);
843 head = mlx5_wq_ll_get_wqe_next_ix(wq, head);
846 rq->mpwqe.actual_wq_head = wq->head;
847 rq->mpwqe.umr_in_progress = 0;
848 rq->mpwqe.umr_completed = 0;
851 void mlx5e_free_rx_descs(struct mlx5e_rq *rq)
856 if (rq->wq_type == MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ) {
857 struct mlx5_wq_ll *wq = &rq->mpwqe.wq;
859 mlx5e_free_rx_in_progress_descs(rq);
861 while (!mlx5_wq_ll_is_empty(wq)) {
862 struct mlx5e_rx_wqe_ll *wqe;
864 wqe_ix_be = *wq->tail_next;
865 wqe_ix = be16_to_cpu(wqe_ix_be);
866 wqe = mlx5_wq_ll_get_wqe(wq, wqe_ix);
867 rq->dealloc_wqe(rq, wqe_ix);
868 mlx5_wq_ll_pop(wq, wqe_ix_be,
869 &wqe->next.next_wqe_index);
872 struct mlx5_wq_cyc *wq = &rq->wqe.wq;
874 while (!mlx5_wq_cyc_is_empty(wq)) {
875 wqe_ix = mlx5_wq_cyc_get_tail(wq);
876 rq->dealloc_wqe(rq, wqe_ix);
883 int mlx5e_open_rq(struct mlx5e_channel *c, struct mlx5e_params *params,
884 struct mlx5e_rq_param *param, struct mlx5e_xsk_param *xsk,
885 struct xsk_buff_pool *xsk_pool, struct mlx5e_rq *rq)
889 err = mlx5e_alloc_rq(c, params, xsk, xsk_pool, param, rq);
893 err = mlx5e_create_rq(rq, param);
897 err = mlx5e_modify_rq_state(rq, MLX5_RQC_STATE_RST, MLX5_RQC_STATE_RDY);
901 if (mlx5e_is_tls_on(c->priv) && !mlx5_accel_is_ktls_device(c->mdev))
902 __set_bit(MLX5E_RQ_STATE_FPGA_TLS, &c->rq.state); /* must be FPGA */
904 if (MLX5_CAP_ETH(c->mdev, cqe_checksum_full))
905 __set_bit(MLX5E_RQ_STATE_CSUM_FULL, &c->rq.state);
907 if (params->rx_dim_enabled)
908 __set_bit(MLX5E_RQ_STATE_AM, &c->rq.state);
910 /* We disable csum_complete when XDP is enabled since
911 * XDP programs might manipulate packets which will render
912 * skb->checksum incorrect.
914 if (MLX5E_GET_PFLAG(params, MLX5E_PFLAG_RX_NO_CSUM_COMPLETE) || c->xdp)
915 __set_bit(MLX5E_RQ_STATE_NO_CSUM_COMPLETE, &c->rq.state);
917 /* For CQE compression on striding RQ, use stride index provided by
918 * HW if capability is supported.
920 if (MLX5E_GET_PFLAG(params, MLX5E_PFLAG_RX_STRIDING_RQ) &&
921 MLX5_CAP_GEN(c->mdev, mini_cqe_resp_stride_index))
922 __set_bit(MLX5E_RQ_STATE_MINI_CQE_HW_STRIDX, &c->rq.state);
927 mlx5e_destroy_rq(rq);
934 void mlx5e_activate_rq(struct mlx5e_rq *rq)
936 set_bit(MLX5E_RQ_STATE_ENABLED, &rq->state);
937 mlx5e_trigger_irq(rq->icosq);
940 void mlx5e_deactivate_rq(struct mlx5e_rq *rq)
942 clear_bit(MLX5E_RQ_STATE_ENABLED, &rq->state);
943 synchronize_rcu(); /* Sync with NAPI to prevent mlx5e_post_rx_wqes. */
946 void mlx5e_close_rq(struct mlx5e_rq *rq)
948 cancel_work_sync(&rq->dim.work);
949 cancel_work_sync(&rq->icosq->recover_work);
950 cancel_work_sync(&rq->recover_work);
951 mlx5e_destroy_rq(rq);
952 mlx5e_free_rx_descs(rq);
956 static void mlx5e_free_xdpsq_db(struct mlx5e_xdpsq *sq)
958 kvfree(sq->db.xdpi_fifo.xi);
959 kvfree(sq->db.wqe_info);
962 static int mlx5e_alloc_xdpsq_fifo(struct mlx5e_xdpsq *sq, int numa)
964 struct mlx5e_xdp_info_fifo *xdpi_fifo = &sq->db.xdpi_fifo;
965 int wq_sz = mlx5_wq_cyc_get_size(&sq->wq);
966 int dsegs_per_wq = wq_sz * MLX5_SEND_WQEBB_NUM_DS;
968 xdpi_fifo->xi = kvzalloc_node(sizeof(*xdpi_fifo->xi) * dsegs_per_wq,
973 xdpi_fifo->pc = &sq->xdpi_fifo_pc;
974 xdpi_fifo->cc = &sq->xdpi_fifo_cc;
975 xdpi_fifo->mask = dsegs_per_wq - 1;
980 static int mlx5e_alloc_xdpsq_db(struct mlx5e_xdpsq *sq, int numa)
982 int wq_sz = mlx5_wq_cyc_get_size(&sq->wq);
985 sq->db.wqe_info = kvzalloc_node(sizeof(*sq->db.wqe_info) * wq_sz,
987 if (!sq->db.wqe_info)
990 err = mlx5e_alloc_xdpsq_fifo(sq, numa);
992 mlx5e_free_xdpsq_db(sq);
999 static int mlx5e_alloc_xdpsq(struct mlx5e_channel *c,
1000 struct mlx5e_params *params,
1001 struct xsk_buff_pool *xsk_pool,
1002 struct mlx5e_sq_param *param,
1003 struct mlx5e_xdpsq *sq,
1006 void *sqc_wq = MLX5_ADDR_OF(sqc, param->sqc, wq);
1007 struct mlx5_core_dev *mdev = c->mdev;
1008 struct mlx5_wq_cyc *wq = &sq->wq;
1012 sq->mkey_be = c->mkey_be;
1014 sq->uar_map = mdev->mlx5e_res.bfreg.map;
1015 sq->min_inline_mode = params->tx_min_inline_mode;
1016 sq->hw_mtu = MLX5E_SW2HW_MTU(params, params->sw_mtu);
1017 sq->xsk_pool = xsk_pool;
1019 sq->stats = sq->xsk_pool ?
1020 &c->priv->channel_stats[c->ix].xsksq :
1022 &c->priv->channel_stats[c->ix].xdpsq :
1023 &c->priv->channel_stats[c->ix].rq_xdpsq;
1025 param->wq.db_numa_node = cpu_to_node(c->cpu);
1026 err = mlx5_wq_cyc_create(mdev, ¶m->wq, sqc_wq, wq, &sq->wq_ctrl);
1029 wq->db = &wq->db[MLX5_SND_DBR];
1031 err = mlx5e_alloc_xdpsq_db(sq, cpu_to_node(c->cpu));
1033 goto err_sq_wq_destroy;
1038 mlx5_wq_destroy(&sq->wq_ctrl);
1043 static void mlx5e_free_xdpsq(struct mlx5e_xdpsq *sq)
1045 mlx5e_free_xdpsq_db(sq);
1046 mlx5_wq_destroy(&sq->wq_ctrl);
1049 static void mlx5e_free_icosq_db(struct mlx5e_icosq *sq)
1051 kvfree(sq->db.wqe_info);
1054 static int mlx5e_alloc_icosq_db(struct mlx5e_icosq *sq, int numa)
1056 int wq_sz = mlx5_wq_cyc_get_size(&sq->wq);
1059 size = array_size(wq_sz, sizeof(*sq->db.wqe_info));
1060 sq->db.wqe_info = kvzalloc_node(size, GFP_KERNEL, numa);
1061 if (!sq->db.wqe_info)
1067 static void mlx5e_icosq_err_cqe_work(struct work_struct *recover_work)
1069 struct mlx5e_icosq *sq = container_of(recover_work, struct mlx5e_icosq,
1072 mlx5e_reporter_icosq_cqe_err(sq);
1075 static int mlx5e_alloc_icosq(struct mlx5e_channel *c,
1076 struct mlx5e_sq_param *param,
1077 struct mlx5e_icosq *sq)
1079 void *sqc_wq = MLX5_ADDR_OF(sqc, param->sqc, wq);
1080 struct mlx5_core_dev *mdev = c->mdev;
1081 struct mlx5_wq_cyc *wq = &sq->wq;
1085 sq->uar_map = mdev->mlx5e_res.bfreg.map;
1087 param->wq.db_numa_node = cpu_to_node(c->cpu);
1088 err = mlx5_wq_cyc_create(mdev, ¶m->wq, sqc_wq, wq, &sq->wq_ctrl);
1091 wq->db = &wq->db[MLX5_SND_DBR];
1093 err = mlx5e_alloc_icosq_db(sq, cpu_to_node(c->cpu));
1095 goto err_sq_wq_destroy;
1097 INIT_WORK(&sq->recover_work, mlx5e_icosq_err_cqe_work);
1102 mlx5_wq_destroy(&sq->wq_ctrl);
1107 static void mlx5e_free_icosq(struct mlx5e_icosq *sq)
1109 mlx5e_free_icosq_db(sq);
1110 mlx5_wq_destroy(&sq->wq_ctrl);
1113 void mlx5e_free_txqsq_db(struct mlx5e_txqsq *sq)
1115 kvfree(sq->db.wqe_info);
1116 kvfree(sq->db.skb_fifo.fifo);
1117 kvfree(sq->db.dma_fifo);
1120 int mlx5e_alloc_txqsq_db(struct mlx5e_txqsq *sq, int numa)
1122 int wq_sz = mlx5_wq_cyc_get_size(&sq->wq);
1123 int df_sz = wq_sz * MLX5_SEND_WQEBB_NUM_DS;
1125 sq->db.dma_fifo = kvzalloc_node(array_size(df_sz,
1126 sizeof(*sq->db.dma_fifo)),
1128 sq->db.skb_fifo.fifo = kvzalloc_node(array_size(df_sz,
1129 sizeof(*sq->db.skb_fifo.fifo)),
1131 sq->db.wqe_info = kvzalloc_node(array_size(wq_sz,
1132 sizeof(*sq->db.wqe_info)),
1134 if (!sq->db.dma_fifo || !sq->db.skb_fifo.fifo || !sq->db.wqe_info) {
1135 mlx5e_free_txqsq_db(sq);
1139 sq->dma_fifo_mask = df_sz - 1;
1141 sq->db.skb_fifo.pc = &sq->skb_fifo_pc;
1142 sq->db.skb_fifo.cc = &sq->skb_fifo_cc;
1143 sq->db.skb_fifo.mask = df_sz - 1;
1148 static int mlx5e_alloc_txqsq(struct mlx5e_channel *c,
1150 struct mlx5e_params *params,
1151 struct mlx5e_sq_param *param,
1152 struct mlx5e_txqsq *sq,
1155 void *sqc_wq = MLX5_ADDR_OF(sqc, param->sqc, wq);
1156 struct mlx5_core_dev *mdev = c->mdev;
1157 struct mlx5_wq_cyc *wq = &sq->wq;
1161 sq->tstamp = c->tstamp;
1162 sq->clock = &mdev->clock;
1163 sq->mkey_be = c->mkey_be;
1164 sq->netdev = c->netdev;
1168 sq->txq_ix = txq_ix;
1169 sq->uar_map = mdev->mlx5e_res.bfreg.map;
1170 sq->min_inline_mode = params->tx_min_inline_mode;
1171 sq->hw_mtu = MLX5E_SW2HW_MTU(params, params->sw_mtu);
1172 INIT_WORK(&sq->recover_work, mlx5e_tx_err_cqe_work);
1173 if (!MLX5_CAP_ETH(mdev, wqe_vlan_insert))
1174 set_bit(MLX5E_SQ_STATE_VLAN_NEED_L2_INLINE, &sq->state);
1175 if (MLX5_IPSEC_DEV(c->priv->mdev))
1176 set_bit(MLX5E_SQ_STATE_IPSEC, &sq->state);
1177 if (mlx5_accel_is_tls_device(c->priv->mdev))
1178 set_bit(MLX5E_SQ_STATE_TLS, &sq->state);
1180 set_bit(MLX5E_SQ_STATE_MPWQE, &sq->state);
1181 sq->stop_room = param->stop_room;
1183 param->wq.db_numa_node = cpu_to_node(c->cpu);
1184 err = mlx5_wq_cyc_create(mdev, ¶m->wq, sqc_wq, wq, &sq->wq_ctrl);
1187 wq->db = &wq->db[MLX5_SND_DBR];
1189 err = mlx5e_alloc_txqsq_db(sq, cpu_to_node(c->cpu));
1191 goto err_sq_wq_destroy;
1193 INIT_WORK(&sq->dim.work, mlx5e_tx_dim_work);
1194 sq->dim.mode = params->tx_cq_moderation.cq_period_mode;
1199 mlx5_wq_destroy(&sq->wq_ctrl);
1204 void mlx5e_free_txqsq(struct mlx5e_txqsq *sq)
1206 mlx5e_free_txqsq_db(sq);
1207 mlx5_wq_destroy(&sq->wq_ctrl);
1210 static int mlx5e_create_sq(struct mlx5_core_dev *mdev,
1211 struct mlx5e_sq_param *param,
1212 struct mlx5e_create_sq_param *csp,
1221 inlen = MLX5_ST_SZ_BYTES(create_sq_in) +
1222 sizeof(u64) * csp->wq_ctrl->buf.npages;
1223 in = kvzalloc(inlen, GFP_KERNEL);
1227 sqc = MLX5_ADDR_OF(create_sq_in, in, ctx);
1228 wq = MLX5_ADDR_OF(sqc, sqc, wq);
1230 memcpy(sqc, param->sqc, sizeof(param->sqc));
1231 MLX5_SET(sqc, sqc, tis_lst_sz, csp->tis_lst_sz);
1232 MLX5_SET(sqc, sqc, tis_num_0, csp->tisn);
1233 MLX5_SET(sqc, sqc, cqn, csp->cqn);
1234 MLX5_SET(sqc, sqc, ts_cqe_to_dest_cqn, csp->ts_cqe_to_dest_cqn);
1236 if (MLX5_CAP_ETH(mdev, wqe_inline_mode) == MLX5_CAP_INLINE_MODE_VPORT_CONTEXT)
1237 MLX5_SET(sqc, sqc, min_wqe_inline_mode, csp->min_inline_mode);
1239 MLX5_SET(sqc, sqc, state, MLX5_SQC_STATE_RST);
1240 MLX5_SET(sqc, sqc, flush_in_error_en, 1);
1242 MLX5_SET(wq, wq, wq_type, MLX5_WQ_TYPE_CYCLIC);
1243 MLX5_SET(wq, wq, uar_page, mdev->mlx5e_res.bfreg.index);
1244 MLX5_SET(wq, wq, log_wq_pg_sz, csp->wq_ctrl->buf.page_shift -
1245 MLX5_ADAPTER_PAGE_SHIFT);
1246 MLX5_SET64(wq, wq, dbr_addr, csp->wq_ctrl->db.dma);
1248 mlx5_fill_page_frag_array(&csp->wq_ctrl->buf,
1249 (__be64 *)MLX5_ADDR_OF(wq, wq, pas));
1251 err = mlx5_core_create_sq(mdev, in, inlen, sqn);
1258 int mlx5e_modify_sq(struct mlx5_core_dev *mdev, u32 sqn,
1259 struct mlx5e_modify_sq_param *p)
1267 inlen = MLX5_ST_SZ_BYTES(modify_sq_in);
1268 in = kvzalloc(inlen, GFP_KERNEL);
1272 sqc = MLX5_ADDR_OF(modify_sq_in, in, ctx);
1274 MLX5_SET(modify_sq_in, in, sq_state, p->curr_state);
1275 MLX5_SET(sqc, sqc, state, p->next_state);
1276 if (p->rl_update && p->next_state == MLX5_SQC_STATE_RDY) {
1278 MLX5_SET(sqc, sqc, packet_pacing_rate_limit_index, p->rl_index);
1280 if (p->qos_update && p->next_state == MLX5_SQC_STATE_RDY) {
1282 MLX5_SET(sqc, sqc, qos_queue_group_id, p->qos_queue_group_id);
1284 MLX5_SET64(modify_sq_in, in, modify_bitmask, bitmask);
1286 err = mlx5_core_modify_sq(mdev, sqn, in);
1293 static void mlx5e_destroy_sq(struct mlx5_core_dev *mdev, u32 sqn)
1295 mlx5_core_destroy_sq(mdev, sqn);
1298 int mlx5e_create_sq_rdy(struct mlx5_core_dev *mdev,
1299 struct mlx5e_sq_param *param,
1300 struct mlx5e_create_sq_param *csp,
1301 u16 qos_queue_group_id,
1304 struct mlx5e_modify_sq_param msp = {0};
1307 err = mlx5e_create_sq(mdev, param, csp, sqn);
1311 msp.curr_state = MLX5_SQC_STATE_RST;
1312 msp.next_state = MLX5_SQC_STATE_RDY;
1313 if (qos_queue_group_id) {
1314 msp.qos_update = true;
1315 msp.qos_queue_group_id = qos_queue_group_id;
1317 err = mlx5e_modify_sq(mdev, *sqn, &msp);
1319 mlx5e_destroy_sq(mdev, *sqn);
1324 static int mlx5e_set_sq_maxrate(struct net_device *dev,
1325 struct mlx5e_txqsq *sq, u32 rate);
1327 int mlx5e_open_txqsq(struct mlx5e_channel *c, u32 tisn, int txq_ix,
1328 struct mlx5e_params *params, struct mlx5e_sq_param *param,
1329 struct mlx5e_txqsq *sq, int tc, u16 qos_queue_group_id, u16 qos_qid)
1331 struct mlx5e_create_sq_param csp = {};
1335 err = mlx5e_alloc_txqsq(c, txq_ix, params, param, sq, tc);
1339 if (qos_queue_group_id)
1340 sq->stats = c->priv->htb.qos_sq_stats[qos_qid];
1342 sq->stats = &c->priv->channel_stats[c->ix].sq[tc];
1346 csp.cqn = sq->cq.mcq.cqn;
1347 csp.wq_ctrl = &sq->wq_ctrl;
1348 csp.min_inline_mode = sq->min_inline_mode;
1349 err = mlx5e_create_sq_rdy(c->mdev, param, &csp, qos_queue_group_id, &sq->sqn);
1351 goto err_free_txqsq;
1353 tx_rate = c->priv->tx_rates[sq->txq_ix];
1355 mlx5e_set_sq_maxrate(c->netdev, sq, tx_rate);
1357 if (params->tx_dim_enabled)
1358 sq->state |= BIT(MLX5E_SQ_STATE_AM);
1363 mlx5e_free_txqsq(sq);
1368 void mlx5e_activate_txqsq(struct mlx5e_txqsq *sq)
1370 sq->txq = netdev_get_tx_queue(sq->netdev, sq->txq_ix);
1371 set_bit(MLX5E_SQ_STATE_ENABLED, &sq->state);
1372 netdev_tx_reset_queue(sq->txq);
1373 netif_tx_start_queue(sq->txq);
1376 void mlx5e_tx_disable_queue(struct netdev_queue *txq)
1378 __netif_tx_lock_bh(txq);
1379 netif_tx_stop_queue(txq);
1380 __netif_tx_unlock_bh(txq);
1383 void mlx5e_deactivate_txqsq(struct mlx5e_txqsq *sq)
1385 struct mlx5_wq_cyc *wq = &sq->wq;
1387 clear_bit(MLX5E_SQ_STATE_ENABLED, &sq->state);
1388 synchronize_rcu(); /* Sync with NAPI to prevent netif_tx_wake_queue. */
1390 mlx5e_tx_disable_queue(sq->txq);
1392 /* last doorbell out, godspeed .. */
1393 if (mlx5e_wqc_has_room_for(wq, sq->cc, sq->pc, 1)) {
1394 u16 pi = mlx5_wq_cyc_ctr2ix(wq, sq->pc);
1395 struct mlx5e_tx_wqe *nop;
1397 sq->db.wqe_info[pi] = (struct mlx5e_tx_wqe_info) {
1401 nop = mlx5e_post_nop(wq, sq->sqn, &sq->pc);
1402 mlx5e_notify_hw(wq, sq->pc, sq->uar_map, &nop->ctrl);
1406 void mlx5e_close_txqsq(struct mlx5e_txqsq *sq)
1408 struct mlx5_core_dev *mdev = sq->mdev;
1409 struct mlx5_rate_limit rl = {0};
1411 cancel_work_sync(&sq->dim.work);
1412 cancel_work_sync(&sq->recover_work);
1413 mlx5e_destroy_sq(mdev, sq->sqn);
1414 if (sq->rate_limit) {
1415 rl.rate = sq->rate_limit;
1416 mlx5_rl_remove_rate(mdev, &rl);
1418 mlx5e_free_txqsq_descs(sq);
1419 mlx5e_free_txqsq(sq);
1422 void mlx5e_tx_err_cqe_work(struct work_struct *recover_work)
1424 struct mlx5e_txqsq *sq = container_of(recover_work, struct mlx5e_txqsq,
1427 mlx5e_reporter_tx_err_cqe(sq);
1430 int mlx5e_open_icosq(struct mlx5e_channel *c, struct mlx5e_params *params,
1431 struct mlx5e_sq_param *param, struct mlx5e_icosq *sq)
1433 struct mlx5e_create_sq_param csp = {};
1436 err = mlx5e_alloc_icosq(c, param, sq);
1440 csp.cqn = sq->cq.mcq.cqn;
1441 csp.wq_ctrl = &sq->wq_ctrl;
1442 csp.min_inline_mode = params->tx_min_inline_mode;
1443 err = mlx5e_create_sq_rdy(c->mdev, param, &csp, 0, &sq->sqn);
1445 goto err_free_icosq;
1450 mlx5e_free_icosq(sq);
1455 void mlx5e_activate_icosq(struct mlx5e_icosq *icosq)
1457 set_bit(MLX5E_SQ_STATE_ENABLED, &icosq->state);
1460 void mlx5e_deactivate_icosq(struct mlx5e_icosq *icosq)
1462 clear_bit(MLX5E_SQ_STATE_ENABLED, &icosq->state);
1463 synchronize_rcu(); /* Sync with NAPI. */
1466 void mlx5e_close_icosq(struct mlx5e_icosq *sq)
1468 struct mlx5e_channel *c = sq->channel;
1470 mlx5e_destroy_sq(c->mdev, sq->sqn);
1471 mlx5e_free_icosq_descs(sq);
1472 mlx5e_free_icosq(sq);
1475 int mlx5e_open_xdpsq(struct mlx5e_channel *c, struct mlx5e_params *params,
1476 struct mlx5e_sq_param *param, struct xsk_buff_pool *xsk_pool,
1477 struct mlx5e_xdpsq *sq, bool is_redirect)
1479 struct mlx5e_create_sq_param csp = {};
1482 err = mlx5e_alloc_xdpsq(c, params, xsk_pool, param, sq, is_redirect);
1487 csp.tisn = c->priv->tisn[c->lag_port][0]; /* tc = 0 */
1488 csp.cqn = sq->cq.mcq.cqn;
1489 csp.wq_ctrl = &sq->wq_ctrl;
1490 csp.min_inline_mode = sq->min_inline_mode;
1491 set_bit(MLX5E_SQ_STATE_ENABLED, &sq->state);
1492 err = mlx5e_create_sq_rdy(c->mdev, param, &csp, 0, &sq->sqn);
1494 goto err_free_xdpsq;
1496 mlx5e_set_xmit_fp(sq, param->is_mpw);
1498 if (!param->is_mpw) {
1499 unsigned int ds_cnt = MLX5E_XDP_TX_DS_COUNT;
1500 unsigned int inline_hdr_sz = 0;
1503 if (sq->min_inline_mode != MLX5_INLINE_MODE_NONE) {
1504 inline_hdr_sz = MLX5E_XDP_MIN_INLINE;
1508 /* Pre initialize fixed WQE fields */
1509 for (i = 0; i < mlx5_wq_cyc_get_size(&sq->wq); i++) {
1510 struct mlx5e_tx_wqe *wqe = mlx5_wq_cyc_get_wqe(&sq->wq, i);
1511 struct mlx5_wqe_ctrl_seg *cseg = &wqe->ctrl;
1512 struct mlx5_wqe_eth_seg *eseg = &wqe->eth;
1513 struct mlx5_wqe_data_seg *dseg;
1515 sq->db.wqe_info[i] = (struct mlx5e_xdp_wqe_info) {
1520 cseg->qpn_ds = cpu_to_be32((sq->sqn << 8) | ds_cnt);
1521 eseg->inline_hdr.sz = cpu_to_be16(inline_hdr_sz);
1523 dseg = (struct mlx5_wqe_data_seg *)cseg + (ds_cnt - 1);
1524 dseg->lkey = sq->mkey_be;
1531 clear_bit(MLX5E_SQ_STATE_ENABLED, &sq->state);
1532 mlx5e_free_xdpsq(sq);
1537 void mlx5e_close_xdpsq(struct mlx5e_xdpsq *sq)
1539 struct mlx5e_channel *c = sq->channel;
1541 clear_bit(MLX5E_SQ_STATE_ENABLED, &sq->state);
1542 synchronize_rcu(); /* Sync with NAPI. */
1544 mlx5e_destroy_sq(c->mdev, sq->sqn);
1545 mlx5e_free_xdpsq_descs(sq);
1546 mlx5e_free_xdpsq(sq);
1549 static int mlx5e_alloc_cq_common(struct mlx5e_priv *priv,
1550 struct mlx5e_cq_param *param,
1551 struct mlx5e_cq *cq)
1553 struct mlx5_core_dev *mdev = priv->mdev;
1554 struct mlx5_core_cq *mcq = &cq->mcq;
1560 err = mlx5_vector2eqn(mdev, param->eq_ix, &eqn_not_used, &irqn);
1564 err = mlx5_cqwq_create(mdev, ¶m->wq, param->cqc, &cq->wq,
1570 mcq->set_ci_db = cq->wq_ctrl.db.db;
1571 mcq->arm_db = cq->wq_ctrl.db.db + 1;
1572 *mcq->set_ci_db = 0;
1574 mcq->vector = param->eq_ix;
1575 mcq->comp = mlx5e_completion_event;
1576 mcq->event = mlx5e_cq_error_event;
1579 for (i = 0; i < mlx5_cqwq_get_size(&cq->wq); i++) {
1580 struct mlx5_cqe64 *cqe = mlx5_cqwq_get_wqe(&cq->wq, i);
1586 cq->netdev = priv->netdev;
1592 static int mlx5e_alloc_cq(struct mlx5e_priv *priv,
1593 struct mlx5e_cq_param *param,
1594 struct mlx5e_create_cq_param *ccp,
1595 struct mlx5e_cq *cq)
1599 param->wq.buf_numa_node = ccp->node;
1600 param->wq.db_numa_node = ccp->node;
1601 param->eq_ix = ccp->ix;
1603 err = mlx5e_alloc_cq_common(priv, param, cq);
1605 cq->napi = ccp->napi;
1606 cq->ch_stats = ccp->ch_stats;
1611 static void mlx5e_free_cq(struct mlx5e_cq *cq)
1613 mlx5_wq_destroy(&cq->wq_ctrl);
1616 static int mlx5e_create_cq(struct mlx5e_cq *cq, struct mlx5e_cq_param *param)
1618 u32 out[MLX5_ST_SZ_DW(create_cq_out)];
1619 struct mlx5_core_dev *mdev = cq->mdev;
1620 struct mlx5_core_cq *mcq = &cq->mcq;
1625 unsigned int irqn_not_used;
1629 err = mlx5_vector2eqn(mdev, param->eq_ix, &eqn, &irqn_not_used);
1633 inlen = MLX5_ST_SZ_BYTES(create_cq_in) +
1634 sizeof(u64) * cq->wq_ctrl.buf.npages;
1635 in = kvzalloc(inlen, GFP_KERNEL);
1639 cqc = MLX5_ADDR_OF(create_cq_in, in, cq_context);
1641 memcpy(cqc, param->cqc, sizeof(param->cqc));
1643 mlx5_fill_page_frag_array(&cq->wq_ctrl.buf,
1644 (__be64 *)MLX5_ADDR_OF(create_cq_in, in, pas));
1646 MLX5_SET(cqc, cqc, cq_period_mode, param->cq_period_mode);
1647 MLX5_SET(cqc, cqc, c_eqn, eqn);
1648 MLX5_SET(cqc, cqc, uar_page, mdev->priv.uar->index);
1649 MLX5_SET(cqc, cqc, log_page_size, cq->wq_ctrl.buf.page_shift -
1650 MLX5_ADAPTER_PAGE_SHIFT);
1651 MLX5_SET64(cqc, cqc, dbr_addr, cq->wq_ctrl.db.dma);
1653 err = mlx5_core_create_cq(mdev, mcq, in, inlen, out, sizeof(out));
1665 static void mlx5e_destroy_cq(struct mlx5e_cq *cq)
1667 mlx5_core_destroy_cq(cq->mdev, &cq->mcq);
1670 int mlx5e_open_cq(struct mlx5e_priv *priv, struct dim_cq_moder moder,
1671 struct mlx5e_cq_param *param, struct mlx5e_create_cq_param *ccp,
1672 struct mlx5e_cq *cq)
1674 struct mlx5_core_dev *mdev = priv->mdev;
1677 err = mlx5e_alloc_cq(priv, param, ccp, cq);
1681 err = mlx5e_create_cq(cq, param);
1685 if (MLX5_CAP_GEN(mdev, cq_moderation))
1686 mlx5_core_modify_cq_moderation(mdev, &cq->mcq, moder.usec, moder.pkts);
1695 void mlx5e_close_cq(struct mlx5e_cq *cq)
1697 mlx5e_destroy_cq(cq);
1701 static int mlx5e_open_tx_cqs(struct mlx5e_channel *c,
1702 struct mlx5e_params *params,
1703 struct mlx5e_create_cq_param *ccp,
1704 struct mlx5e_channel_param *cparam)
1709 for (tc = 0; tc < c->num_tc; tc++) {
1710 err = mlx5e_open_cq(c->priv, params->tx_cq_moderation, &cparam->txq_sq.cqp,
1711 ccp, &c->sq[tc].cq);
1713 goto err_close_tx_cqs;
1719 for (tc--; tc >= 0; tc--)
1720 mlx5e_close_cq(&c->sq[tc].cq);
1725 static void mlx5e_close_tx_cqs(struct mlx5e_channel *c)
1729 for (tc = 0; tc < c->num_tc; tc++)
1730 mlx5e_close_cq(&c->sq[tc].cq);
1733 static int mlx5e_open_sqs(struct mlx5e_channel *c,
1734 struct mlx5e_params *params,
1735 struct mlx5e_channel_param *cparam)
1739 for (tc = 0; tc < params->num_tc; tc++) {
1740 int txq_ix = c->ix + tc * params->num_channels;
1742 err = mlx5e_open_txqsq(c, c->priv->tisn[c->lag_port][tc], txq_ix,
1743 params, &cparam->txq_sq, &c->sq[tc], tc, 0, 0);
1751 for (tc--; tc >= 0; tc--)
1752 mlx5e_close_txqsq(&c->sq[tc]);
1757 static void mlx5e_close_sqs(struct mlx5e_channel *c)
1761 for (tc = 0; tc < c->num_tc; tc++)
1762 mlx5e_close_txqsq(&c->sq[tc]);
1765 static int mlx5e_set_sq_maxrate(struct net_device *dev,
1766 struct mlx5e_txqsq *sq, u32 rate)
1768 struct mlx5e_priv *priv = netdev_priv(dev);
1769 struct mlx5_core_dev *mdev = priv->mdev;
1770 struct mlx5e_modify_sq_param msp = {0};
1771 struct mlx5_rate_limit rl = {0};
1775 if (rate == sq->rate_limit)
1779 if (sq->rate_limit) {
1780 rl.rate = sq->rate_limit;
1781 /* remove current rl index to free space to next ones */
1782 mlx5_rl_remove_rate(mdev, &rl);
1789 err = mlx5_rl_add_rate(mdev, &rl_index, &rl);
1791 netdev_err(dev, "Failed configuring rate %u: %d\n",
1797 msp.curr_state = MLX5_SQC_STATE_RDY;
1798 msp.next_state = MLX5_SQC_STATE_RDY;
1799 msp.rl_index = rl_index;
1800 msp.rl_update = true;
1801 err = mlx5e_modify_sq(mdev, sq->sqn, &msp);
1803 netdev_err(dev, "Failed configuring rate %u: %d\n",
1805 /* remove the rate from the table */
1807 mlx5_rl_remove_rate(mdev, &rl);
1811 sq->rate_limit = rate;
1815 static int mlx5e_set_tx_maxrate(struct net_device *dev, int index, u32 rate)
1817 struct mlx5e_priv *priv = netdev_priv(dev);
1818 struct mlx5_core_dev *mdev = priv->mdev;
1819 struct mlx5e_txqsq *sq = priv->txq2sq[index];
1822 if (!mlx5_rl_is_supported(mdev)) {
1823 netdev_err(dev, "Rate limiting is not supported on this device\n");
1827 /* rate is given in Mb/sec, HW config is in Kb/sec */
1830 /* Check whether rate in valid range, 0 is always valid */
1831 if (rate && !mlx5_rl_is_in_range(mdev, rate)) {
1832 netdev_err(dev, "TX rate %u, is not in range\n", rate);
1836 mutex_lock(&priv->state_lock);
1837 if (test_bit(MLX5E_STATE_OPENED, &priv->state))
1838 err = mlx5e_set_sq_maxrate(dev, sq, rate);
1840 priv->tx_rates[index] = rate;
1841 mutex_unlock(&priv->state_lock);
1846 void mlx5e_build_create_cq_param(struct mlx5e_create_cq_param *ccp, struct mlx5e_channel *c)
1848 *ccp = (struct mlx5e_create_cq_param) {
1850 .ch_stats = c->stats,
1851 .node = cpu_to_node(c->cpu),
1856 static int mlx5e_open_queues(struct mlx5e_channel *c,
1857 struct mlx5e_params *params,
1858 struct mlx5e_channel_param *cparam)
1860 struct dim_cq_moder icocq_moder = {0, 0};
1861 struct mlx5e_create_cq_param ccp;
1864 mlx5e_build_create_cq_param(&ccp, c);
1866 err = mlx5e_open_cq(c->priv, icocq_moder, &cparam->icosq.cqp, &ccp,
1867 &c->async_icosq.cq);
1871 err = mlx5e_open_cq(c->priv, icocq_moder, &cparam->async_icosq.cqp, &ccp,
1874 goto err_close_async_icosq_cq;
1876 err = mlx5e_open_tx_cqs(c, params, &ccp, cparam);
1878 goto err_close_icosq_cq;
1880 err = mlx5e_open_cq(c->priv, params->tx_cq_moderation, &cparam->xdp_sq.cqp, &ccp,
1883 goto err_close_tx_cqs;
1885 err = mlx5e_open_cq(c->priv, params->rx_cq_moderation, &cparam->rq.cqp, &ccp,
1888 goto err_close_xdp_tx_cqs;
1890 err = c->xdp ? mlx5e_open_cq(c->priv, params->tx_cq_moderation, &cparam->xdp_sq.cqp,
1891 &ccp, &c->rq_xdpsq.cq) : 0;
1893 goto err_close_rx_cq;
1895 spin_lock_init(&c->async_icosq_lock);
1897 err = mlx5e_open_icosq(c, params, &cparam->async_icosq, &c->async_icosq);
1899 goto err_close_xdpsq_cq;
1901 err = mlx5e_open_icosq(c, params, &cparam->icosq, &c->icosq);
1903 goto err_close_async_icosq;
1905 err = mlx5e_open_sqs(c, params, cparam);
1907 goto err_close_icosq;
1910 err = mlx5e_open_xdpsq(c, params, &cparam->xdp_sq, NULL,
1911 &c->rq_xdpsq, false);
1916 err = mlx5e_open_rq(c, params, &cparam->rq, NULL, NULL, &c->rq);
1918 goto err_close_xdp_sq;
1920 err = mlx5e_open_xdpsq(c, params, &cparam->xdp_sq, NULL, &c->xdpsq, true);
1927 mlx5e_close_rq(&c->rq);
1931 mlx5e_close_xdpsq(&c->rq_xdpsq);
1937 mlx5e_close_icosq(&c->icosq);
1939 err_close_async_icosq:
1940 mlx5e_close_icosq(&c->async_icosq);
1944 mlx5e_close_cq(&c->rq_xdpsq.cq);
1947 mlx5e_close_cq(&c->rq.cq);
1949 err_close_xdp_tx_cqs:
1950 mlx5e_close_cq(&c->xdpsq.cq);
1953 mlx5e_close_tx_cqs(c);
1956 mlx5e_close_cq(&c->icosq.cq);
1958 err_close_async_icosq_cq:
1959 mlx5e_close_cq(&c->async_icosq.cq);
1964 static void mlx5e_close_queues(struct mlx5e_channel *c)
1966 mlx5e_close_xdpsq(&c->xdpsq);
1967 mlx5e_close_rq(&c->rq);
1969 mlx5e_close_xdpsq(&c->rq_xdpsq);
1971 mlx5e_close_icosq(&c->icosq);
1972 mlx5e_close_icosq(&c->async_icosq);
1974 mlx5e_close_cq(&c->rq_xdpsq.cq);
1975 mlx5e_close_cq(&c->rq.cq);
1976 mlx5e_close_cq(&c->xdpsq.cq);
1977 mlx5e_close_tx_cqs(c);
1978 mlx5e_close_cq(&c->icosq.cq);
1979 mlx5e_close_cq(&c->async_icosq.cq);
1982 static u8 mlx5e_enumerate_lag_port(struct mlx5_core_dev *mdev, int ix)
1984 u16 port_aff_bias = mlx5_core_is_pf(mdev) ? 0 : MLX5_CAP_GEN(mdev, vhca_id);
1986 return (ix + port_aff_bias) % mlx5e_get_num_lag_ports(mdev);
1989 static int mlx5e_open_channel(struct mlx5e_priv *priv, int ix,
1990 struct mlx5e_params *params,
1991 struct mlx5e_channel_param *cparam,
1992 struct xsk_buff_pool *xsk_pool,
1993 struct mlx5e_channel **cp)
1995 int cpu = cpumask_first(mlx5_comp_irq_get_affinity_mask(priv->mdev, ix));
1996 struct net_device *netdev = priv->netdev;
1997 struct mlx5e_xsk_param xsk;
1998 struct mlx5e_channel *c;
2003 err = mlx5_vector2eqn(priv->mdev, ix, &eqn, &irq);
2007 c = kvzalloc_node(sizeof(*c), GFP_KERNEL, cpu_to_node(cpu));
2012 c->mdev = priv->mdev;
2013 c->tstamp = &priv->tstamp;
2016 c->pdev = mlx5_core_dma_dev(priv->mdev);
2017 c->netdev = priv->netdev;
2018 c->mkey_be = cpu_to_be32(priv->mdev->mlx5e_res.mkey.key);
2019 c->num_tc = params->num_tc;
2020 c->xdp = !!params->xdp_prog;
2021 c->stats = &priv->channel_stats[ix].ch;
2022 c->aff_mask = irq_get_effective_affinity_mask(irq);
2023 c->lag_port = mlx5e_enumerate_lag_port(priv->mdev, ix);
2025 netif_napi_add(netdev, &c->napi, mlx5e_napi_poll, 64);
2027 err = mlx5e_open_queues(c, params, cparam);
2032 mlx5e_build_xsk_param(xsk_pool, &xsk);
2033 err = mlx5e_open_xsk(priv, params, &xsk, xsk_pool, c);
2035 goto err_close_queues;
2043 mlx5e_close_queues(c);
2046 netif_napi_del(&c->napi);
2053 static void mlx5e_activate_channel(struct mlx5e_channel *c)
2057 napi_enable(&c->napi);
2059 for (tc = 0; tc < c->num_tc; tc++)
2060 mlx5e_activate_txqsq(&c->sq[tc]);
2061 mlx5e_activate_icosq(&c->icosq);
2062 mlx5e_activate_icosq(&c->async_icosq);
2063 mlx5e_activate_rq(&c->rq);
2065 if (test_bit(MLX5E_CHANNEL_STATE_XSK, c->state))
2066 mlx5e_activate_xsk(c);
2069 static void mlx5e_deactivate_channel(struct mlx5e_channel *c)
2073 if (test_bit(MLX5E_CHANNEL_STATE_XSK, c->state))
2074 mlx5e_deactivate_xsk(c);
2076 mlx5e_deactivate_rq(&c->rq);
2077 mlx5e_deactivate_icosq(&c->async_icosq);
2078 mlx5e_deactivate_icosq(&c->icosq);
2079 for (tc = 0; tc < c->num_tc; tc++)
2080 mlx5e_deactivate_txqsq(&c->sq[tc]);
2081 mlx5e_qos_deactivate_queues(c);
2083 napi_disable(&c->napi);
2086 static void mlx5e_close_channel(struct mlx5e_channel *c)
2088 if (test_bit(MLX5E_CHANNEL_STATE_XSK, c->state))
2090 mlx5e_close_queues(c);
2091 mlx5e_qos_close_queues(c);
2092 netif_napi_del(&c->napi);
2097 #define DEFAULT_FRAG_SIZE (2048)
2099 static void mlx5e_build_rq_frags_info(struct mlx5_core_dev *mdev,
2100 struct mlx5e_params *params,
2101 struct mlx5e_xsk_param *xsk,
2102 struct mlx5e_rq_frags_info *info)
2104 u32 byte_count = MLX5E_SW2HW_MTU(params, params->sw_mtu);
2105 int frag_size_max = DEFAULT_FRAG_SIZE;
2109 if (MLX5_IPSEC_DEV(mdev))
2110 byte_count += MLX5E_METADATA_ETHER_LEN;
2112 if (mlx5e_rx_is_linear_skb(params, xsk)) {
2115 frag_stride = mlx5e_rx_get_linear_frag_sz(params, xsk);
2116 frag_stride = roundup_pow_of_two(frag_stride);
2118 info->arr[0].frag_size = byte_count;
2119 info->arr[0].frag_stride = frag_stride;
2120 info->num_frags = 1;
2121 info->wqe_bulk = PAGE_SIZE / frag_stride;
2125 if (byte_count > PAGE_SIZE +
2126 (MLX5E_MAX_RX_FRAGS - 1) * frag_size_max)
2127 frag_size_max = PAGE_SIZE;
2130 while (buf_size < byte_count) {
2131 int frag_size = byte_count - buf_size;
2133 if (i < MLX5E_MAX_RX_FRAGS - 1)
2134 frag_size = min(frag_size, frag_size_max);
2136 info->arr[i].frag_size = frag_size;
2137 info->arr[i].frag_stride = roundup_pow_of_two(frag_size);
2139 buf_size += frag_size;
2142 info->num_frags = i;
2143 /* number of different wqes sharing a page */
2144 info->wqe_bulk = 1 + (info->num_frags % 2);
2147 info->wqe_bulk = max_t(u8, info->wqe_bulk, 8);
2148 info->log_num_frags = order_base_2(info->num_frags);
2151 static inline u8 mlx5e_get_rqwq_log_stride(u8 wq_type, int ndsegs)
2153 int sz = sizeof(struct mlx5_wqe_data_seg) * ndsegs;
2156 case MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ:
2157 sz += sizeof(struct mlx5e_rx_wqe_ll);
2159 default: /* MLX5_WQ_TYPE_CYCLIC */
2160 sz += sizeof(struct mlx5e_rx_wqe_cyc);
2163 return order_base_2(sz);
2166 static u8 mlx5e_get_rq_log_wq_sz(void *rqc)
2168 void *wq = MLX5_ADDR_OF(rqc, rqc, wq);
2170 return MLX5_GET(wq, wq, log_wq_sz);
2173 void mlx5e_build_rq_param(struct mlx5e_priv *priv,
2174 struct mlx5e_params *params,
2175 struct mlx5e_xsk_param *xsk,
2176 struct mlx5e_rq_param *param)
2178 struct mlx5_core_dev *mdev = priv->mdev;
2179 void *rqc = param->rqc;
2180 void *wq = MLX5_ADDR_OF(rqc, rqc, wq);
2183 switch (params->rq_wq_type) {
2184 case MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ:
2185 MLX5_SET(wq, wq, log_wqe_num_of_strides,
2186 mlx5e_mpwqe_get_log_num_strides(mdev, params, xsk) -
2187 MLX5_MPWQE_LOG_NUM_STRIDES_BASE);
2188 MLX5_SET(wq, wq, log_wqe_stride_size,
2189 mlx5e_mpwqe_get_log_stride_size(mdev, params, xsk) -
2190 MLX5_MPWQE_LOG_STRIDE_SZ_BASE);
2191 MLX5_SET(wq, wq, log_wq_sz, mlx5e_mpwqe_get_log_rq_size(params, xsk));
2193 default: /* MLX5_WQ_TYPE_CYCLIC */
2194 MLX5_SET(wq, wq, log_wq_sz, params->log_rq_mtu_frames);
2195 mlx5e_build_rq_frags_info(mdev, params, xsk, ¶m->frags_info);
2196 ndsegs = param->frags_info.num_frags;
2199 MLX5_SET(wq, wq, wq_type, params->rq_wq_type);
2200 MLX5_SET(wq, wq, end_padding_mode, MLX5_WQ_END_PAD_MODE_ALIGN);
2201 MLX5_SET(wq, wq, log_wq_stride,
2202 mlx5e_get_rqwq_log_stride(params->rq_wq_type, ndsegs));
2203 MLX5_SET(wq, wq, pd, mdev->mlx5e_res.pdn);
2204 MLX5_SET(rqc, rqc, counter_set_id, priv->q_counter);
2205 MLX5_SET(rqc, rqc, vsd, params->vlan_strip_disable);
2206 MLX5_SET(rqc, rqc, scatter_fcs, params->scatter_fcs_en);
2208 param->wq.buf_numa_node = dev_to_node(mlx5_core_dma_dev(mdev));
2209 mlx5e_build_rx_cq_param(priv, params, xsk, ¶m->cqp);
2212 static void mlx5e_build_drop_rq_param(struct mlx5e_priv *priv,
2213 struct mlx5e_rq_param *param)
2215 struct mlx5_core_dev *mdev = priv->mdev;
2216 void *rqc = param->rqc;
2217 void *wq = MLX5_ADDR_OF(rqc, rqc, wq);
2219 MLX5_SET(wq, wq, wq_type, MLX5_WQ_TYPE_CYCLIC);
2220 MLX5_SET(wq, wq, log_wq_stride,
2221 mlx5e_get_rqwq_log_stride(MLX5_WQ_TYPE_CYCLIC, 1));
2222 MLX5_SET(rqc, rqc, counter_set_id, priv->drop_rq_q_counter);
2224 param->wq.buf_numa_node = dev_to_node(mlx5_core_dma_dev(mdev));
2227 void mlx5e_build_sq_param_common(struct mlx5e_priv *priv,
2228 struct mlx5e_sq_param *param)
2230 void *sqc = param->sqc;
2231 void *wq = MLX5_ADDR_OF(sqc, sqc, wq);
2233 MLX5_SET(wq, wq, log_wq_stride, ilog2(MLX5_SEND_WQE_BB));
2234 MLX5_SET(wq, wq, pd, priv->mdev->mlx5e_res.pdn);
2236 param->wq.buf_numa_node = dev_to_node(mlx5_core_dma_dev(priv->mdev));
2239 void mlx5e_build_sq_param(struct mlx5e_priv *priv, struct mlx5e_params *params,
2240 struct mlx5e_sq_param *param)
2242 void *sqc = param->sqc;
2243 void *wq = MLX5_ADDR_OF(sqc, sqc, wq);
2246 allow_swp = mlx5_geneve_tx_allowed(priv->mdev) ||
2247 !!MLX5_IPSEC_DEV(priv->mdev);
2248 mlx5e_build_sq_param_common(priv, param);
2249 MLX5_SET(wq, wq, log_wq_sz, params->log_sq_size);
2250 MLX5_SET(sqc, sqc, allow_swp, allow_swp);
2251 param->is_mpw = MLX5E_GET_PFLAG(params, MLX5E_PFLAG_SKB_TX_MPWQE);
2252 param->stop_room = mlx5e_calc_sq_stop_room(priv->mdev, params);
2253 mlx5e_build_tx_cq_param(priv, params, ¶m->cqp);
2256 static void mlx5e_build_common_cq_param(struct mlx5e_priv *priv,
2257 struct mlx5e_cq_param *param)
2259 void *cqc = param->cqc;
2261 MLX5_SET(cqc, cqc, uar_page, priv->mdev->priv.uar->index);
2262 if (MLX5_CAP_GEN(priv->mdev, cqe_128_always) && cache_line_size() >= 128)
2263 MLX5_SET(cqc, cqc, cqe_sz, CQE_STRIDE_128_PAD);
2266 void mlx5e_build_rx_cq_param(struct mlx5e_priv *priv,
2267 struct mlx5e_params *params,
2268 struct mlx5e_xsk_param *xsk,
2269 struct mlx5e_cq_param *param)
2271 struct mlx5_core_dev *mdev = priv->mdev;
2272 bool hw_stridx = false;
2273 void *cqc = param->cqc;
2276 switch (params->rq_wq_type) {
2277 case MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ:
2278 log_cq_size = mlx5e_mpwqe_get_log_rq_size(params, xsk) +
2279 mlx5e_mpwqe_get_log_num_strides(mdev, params, xsk);
2280 hw_stridx = MLX5_CAP_GEN(mdev, mini_cqe_resp_stride_index);
2282 default: /* MLX5_WQ_TYPE_CYCLIC */
2283 log_cq_size = params->log_rq_mtu_frames;
2286 MLX5_SET(cqc, cqc, log_cq_size, log_cq_size);
2287 if (MLX5E_GET_PFLAG(params, MLX5E_PFLAG_RX_CQE_COMPRESS)) {
2288 MLX5_SET(cqc, cqc, mini_cqe_res_format, hw_stridx ?
2289 MLX5_CQE_FORMAT_CSUM_STRIDX : MLX5_CQE_FORMAT_CSUM);
2290 MLX5_SET(cqc, cqc, cqe_comp_en, 1);
2293 mlx5e_build_common_cq_param(priv, param);
2294 param->cq_period_mode = params->rx_cq_moderation.cq_period_mode;
2297 void mlx5e_build_tx_cq_param(struct mlx5e_priv *priv,
2298 struct mlx5e_params *params,
2299 struct mlx5e_cq_param *param)
2301 void *cqc = param->cqc;
2303 MLX5_SET(cqc, cqc, log_cq_size, params->log_sq_size);
2305 mlx5e_build_common_cq_param(priv, param);
2306 param->cq_period_mode = params->tx_cq_moderation.cq_period_mode;
2309 void mlx5e_build_ico_cq_param(struct mlx5e_priv *priv,
2311 struct mlx5e_cq_param *param)
2313 void *cqc = param->cqc;
2315 MLX5_SET(cqc, cqc, log_cq_size, log_wq_size);
2317 mlx5e_build_common_cq_param(priv, param);
2319 param->cq_period_mode = DIM_CQ_PERIOD_MODE_START_FROM_EQE;
2322 void mlx5e_build_icosq_param(struct mlx5e_priv *priv,
2324 struct mlx5e_sq_param *param)
2326 void *sqc = param->sqc;
2327 void *wq = MLX5_ADDR_OF(sqc, sqc, wq);
2329 mlx5e_build_sq_param_common(priv, param);
2331 MLX5_SET(wq, wq, log_wq_sz, log_wq_size);
2332 MLX5_SET(sqc, sqc, reg_umr, MLX5_CAP_ETH(priv->mdev, reg_umr_sq));
2333 mlx5e_build_ico_cq_param(priv, log_wq_size, ¶m->cqp);
2336 void mlx5e_build_xdpsq_param(struct mlx5e_priv *priv,
2337 struct mlx5e_params *params,
2338 struct mlx5e_sq_param *param)
2340 void *sqc = param->sqc;
2341 void *wq = MLX5_ADDR_OF(sqc, sqc, wq);
2343 mlx5e_build_sq_param_common(priv, param);
2344 MLX5_SET(wq, wq, log_wq_sz, params->log_sq_size);
2345 param->is_mpw = MLX5E_GET_PFLAG(params, MLX5E_PFLAG_XDP_TX_MPWQE);
2346 mlx5e_build_tx_cq_param(priv, params, ¶m->cqp);
2349 static u8 mlx5e_build_icosq_log_wq_sz(struct mlx5e_params *params,
2350 struct mlx5e_rq_param *rqp)
2352 switch (params->rq_wq_type) {
2353 case MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ:
2354 return order_base_2(MLX5E_UMR_WQEBBS) +
2355 mlx5e_get_rq_log_wq_sz(rqp->rqc);
2356 default: /* MLX5_WQ_TYPE_CYCLIC */
2357 return MLX5E_PARAMS_MINIMUM_LOG_SQ_SIZE;
2361 static u8 mlx5e_build_async_icosq_log_wq_sz(struct net_device *netdev)
2363 if (netdev->hw_features & NETIF_F_HW_TLS_RX)
2364 return MLX5E_PARAMS_DEFAULT_LOG_SQ_SIZE;
2366 return MLX5E_PARAMS_MINIMUM_LOG_SQ_SIZE;
2369 static void mlx5e_build_channel_param(struct mlx5e_priv *priv,
2370 struct mlx5e_params *params,
2371 struct mlx5e_channel_param *cparam)
2373 u8 icosq_log_wq_sz, async_icosq_log_wq_sz;
2375 mlx5e_build_rq_param(priv, params, NULL, &cparam->rq);
2377 icosq_log_wq_sz = mlx5e_build_icosq_log_wq_sz(params, &cparam->rq);
2378 async_icosq_log_wq_sz = mlx5e_build_async_icosq_log_wq_sz(priv->netdev);
2380 mlx5e_build_sq_param(priv, params, &cparam->txq_sq);
2381 mlx5e_build_xdpsq_param(priv, params, &cparam->xdp_sq);
2382 mlx5e_build_icosq_param(priv, icosq_log_wq_sz, &cparam->icosq);
2383 mlx5e_build_icosq_param(priv, async_icosq_log_wq_sz, &cparam->async_icosq);
2386 int mlx5e_open_channels(struct mlx5e_priv *priv,
2387 struct mlx5e_channels *chs)
2389 struct mlx5e_channel_param *cparam;
2393 chs->num = chs->params.num_channels;
2395 chs->c = kcalloc(chs->num, sizeof(struct mlx5e_channel *), GFP_KERNEL);
2396 cparam = kvzalloc(sizeof(struct mlx5e_channel_param), GFP_KERNEL);
2397 if (!chs->c || !cparam)
2400 mlx5e_build_channel_param(priv, &chs->params, cparam);
2401 for (i = 0; i < chs->num; i++) {
2402 struct xsk_buff_pool *xsk_pool = NULL;
2404 if (chs->params.xdp_prog)
2405 xsk_pool = mlx5e_xsk_get_pool(&chs->params, chs->params.xsk, i);
2407 err = mlx5e_open_channel(priv, i, &chs->params, cparam, xsk_pool, &chs->c[i]);
2409 goto err_close_channels;
2412 if (MLX5E_GET_PFLAG(&chs->params, MLX5E_PFLAG_TX_PORT_TS)) {
2413 err = mlx5e_port_ptp_open(priv, &chs->params, chs->c[0]->lag_port,
2416 goto err_close_channels;
2419 err = mlx5e_qos_open_queues(priv, chs);
2423 mlx5e_health_channels_update(priv);
2429 mlx5e_port_ptp_close(chs->port_ptp);
2432 for (i--; i >= 0; i--)
2433 mlx5e_close_channel(chs->c[i]);
2442 static void mlx5e_activate_channels(struct mlx5e_channels *chs)
2446 for (i = 0; i < chs->num; i++)
2447 mlx5e_activate_channel(chs->c[i]);
2450 mlx5e_ptp_activate_channel(chs->port_ptp);
2453 #define MLX5E_RQ_WQES_TIMEOUT 20000 /* msecs */
2455 static int mlx5e_wait_channels_min_rx_wqes(struct mlx5e_channels *chs)
2460 for (i = 0; i < chs->num; i++) {
2461 int timeout = err ? 0 : MLX5E_RQ_WQES_TIMEOUT;
2463 err |= mlx5e_wait_for_min_rx_wqes(&chs->c[i]->rq, timeout);
2465 /* Don't wait on the XSK RQ, because the newer xdpsock sample
2466 * doesn't provide any Fill Ring entries at the setup stage.
2470 return err ? -ETIMEDOUT : 0;
2473 static void mlx5e_deactivate_channels(struct mlx5e_channels *chs)
2478 mlx5e_ptp_deactivate_channel(chs->port_ptp);
2480 for (i = 0; i < chs->num; i++)
2481 mlx5e_deactivate_channel(chs->c[i]);
2484 void mlx5e_close_channels(struct mlx5e_channels *chs)
2489 mlx5e_port_ptp_close(chs->port_ptp);
2491 for (i = 0; i < chs->num; i++)
2492 mlx5e_close_channel(chs->c[i]);
2499 mlx5e_create_rqt(struct mlx5e_priv *priv, int sz, struct mlx5e_rqt *rqt)
2501 struct mlx5_core_dev *mdev = priv->mdev;
2508 inlen = MLX5_ST_SZ_BYTES(create_rqt_in) + sizeof(u32) * sz;
2509 in = kvzalloc(inlen, GFP_KERNEL);
2513 rqtc = MLX5_ADDR_OF(create_rqt_in, in, rqt_context);
2515 MLX5_SET(rqtc, rqtc, rqt_actual_size, sz);
2516 MLX5_SET(rqtc, rqtc, rqt_max_size, sz);
2518 for (i = 0; i < sz; i++)
2519 MLX5_SET(rqtc, rqtc, rq_num[i], priv->drop_rq.rqn);
2521 err = mlx5_core_create_rqt(mdev, in, inlen, &rqt->rqtn);
2523 rqt->enabled = true;
2529 void mlx5e_destroy_rqt(struct mlx5e_priv *priv, struct mlx5e_rqt *rqt)
2531 rqt->enabled = false;
2532 mlx5_core_destroy_rqt(priv->mdev, rqt->rqtn);
2535 int mlx5e_create_indirect_rqt(struct mlx5e_priv *priv)
2537 struct mlx5e_rqt *rqt = &priv->indir_rqt;
2540 err = mlx5e_create_rqt(priv, MLX5E_INDIR_RQT_SIZE, rqt);
2542 mlx5_core_warn(priv->mdev, "create indirect rqts failed, %d\n", err);
2546 int mlx5e_create_direct_rqts(struct mlx5e_priv *priv, struct mlx5e_tir *tirs)
2551 for (ix = 0; ix < priv->max_nch; ix++) {
2552 err = mlx5e_create_rqt(priv, 1 /*size */, &tirs[ix].rqt);
2554 goto err_destroy_rqts;
2560 mlx5_core_warn(priv->mdev, "create rqts failed, %d\n", err);
2561 for (ix--; ix >= 0; ix--)
2562 mlx5e_destroy_rqt(priv, &tirs[ix].rqt);
2567 void mlx5e_destroy_direct_rqts(struct mlx5e_priv *priv, struct mlx5e_tir *tirs)
2571 for (i = 0; i < priv->max_nch; i++)
2572 mlx5e_destroy_rqt(priv, &tirs[i].rqt);
2575 static int mlx5e_rx_hash_fn(int hfunc)
2577 return (hfunc == ETH_RSS_HASH_TOP) ?
2578 MLX5_RX_HASH_FN_TOEPLITZ :
2579 MLX5_RX_HASH_FN_INVERTED_XOR8;
2582 int mlx5e_bits_invert(unsigned long a, int size)
2587 for (i = 0; i < size; i++)
2588 inv |= (test_bit(size - i - 1, &a) ? 1 : 0) << i;
2593 static void mlx5e_fill_rqt_rqns(struct mlx5e_priv *priv, int sz,
2594 struct mlx5e_redirect_rqt_param rrp, void *rqtc)
2598 for (i = 0; i < sz; i++) {
2604 if (rrp.rss.hfunc == ETH_RSS_HASH_XOR)
2605 ix = mlx5e_bits_invert(i, ilog2(sz));
2607 ix = priv->rss_params.indirection_rqt[ix];
2608 rqn = rrp.rss.channels->c[ix]->rq.rqn;
2612 MLX5_SET(rqtc, rqtc, rq_num[i], rqn);
2616 int mlx5e_redirect_rqt(struct mlx5e_priv *priv, u32 rqtn, int sz,
2617 struct mlx5e_redirect_rqt_param rrp)
2619 struct mlx5_core_dev *mdev = priv->mdev;
2625 inlen = MLX5_ST_SZ_BYTES(modify_rqt_in) + sizeof(u32) * sz;
2626 in = kvzalloc(inlen, GFP_KERNEL);
2630 rqtc = MLX5_ADDR_OF(modify_rqt_in, in, ctx);
2632 MLX5_SET(rqtc, rqtc, rqt_actual_size, sz);
2633 MLX5_SET(modify_rqt_in, in, bitmask.rqn_list, 1);
2634 mlx5e_fill_rqt_rqns(priv, sz, rrp, rqtc);
2635 err = mlx5_core_modify_rqt(mdev, rqtn, in, inlen);
2641 static u32 mlx5e_get_direct_rqn(struct mlx5e_priv *priv, int ix,
2642 struct mlx5e_redirect_rqt_param rrp)
2647 if (ix >= rrp.rss.channels->num)
2648 return priv->drop_rq.rqn;
2650 return rrp.rss.channels->c[ix]->rq.rqn;
2653 static void mlx5e_redirect_rqts(struct mlx5e_priv *priv,
2654 struct mlx5e_redirect_rqt_param rrp)
2659 if (priv->indir_rqt.enabled) {
2661 rqtn = priv->indir_rqt.rqtn;
2662 mlx5e_redirect_rqt(priv, rqtn, MLX5E_INDIR_RQT_SIZE, rrp);
2665 for (ix = 0; ix < priv->max_nch; ix++) {
2666 struct mlx5e_redirect_rqt_param direct_rrp = {
2669 .rqn = mlx5e_get_direct_rqn(priv, ix, rrp)
2673 /* Direct RQ Tables */
2674 if (!priv->direct_tir[ix].rqt.enabled)
2677 rqtn = priv->direct_tir[ix].rqt.rqtn;
2678 mlx5e_redirect_rqt(priv, rqtn, 1, direct_rrp);
2682 static void mlx5e_redirect_rqts_to_channels(struct mlx5e_priv *priv,
2683 struct mlx5e_channels *chs)
2685 struct mlx5e_redirect_rqt_param rrp = {
2690 .hfunc = priv->rss_params.hfunc,
2695 mlx5e_redirect_rqts(priv, rrp);
2698 static void mlx5e_redirect_rqts_to_drop(struct mlx5e_priv *priv)
2700 struct mlx5e_redirect_rqt_param drop_rrp = {
2703 .rqn = priv->drop_rq.rqn,
2707 mlx5e_redirect_rqts(priv, drop_rrp);
2710 static const struct mlx5e_tirc_config tirc_default_config[MLX5E_NUM_INDIR_TIRS] = {
2711 [MLX5E_TT_IPV4_TCP] = { .l3_prot_type = MLX5_L3_PROT_TYPE_IPV4,
2712 .l4_prot_type = MLX5_L4_PROT_TYPE_TCP,
2713 .rx_hash_fields = MLX5_HASH_IP_L4PORTS,
2715 [MLX5E_TT_IPV6_TCP] = { .l3_prot_type = MLX5_L3_PROT_TYPE_IPV6,
2716 .l4_prot_type = MLX5_L4_PROT_TYPE_TCP,
2717 .rx_hash_fields = MLX5_HASH_IP_L4PORTS,
2719 [MLX5E_TT_IPV4_UDP] = { .l3_prot_type = MLX5_L3_PROT_TYPE_IPV4,
2720 .l4_prot_type = MLX5_L4_PROT_TYPE_UDP,
2721 .rx_hash_fields = MLX5_HASH_IP_L4PORTS,
2723 [MLX5E_TT_IPV6_UDP] = { .l3_prot_type = MLX5_L3_PROT_TYPE_IPV6,
2724 .l4_prot_type = MLX5_L4_PROT_TYPE_UDP,
2725 .rx_hash_fields = MLX5_HASH_IP_L4PORTS,
2727 [MLX5E_TT_IPV4_IPSEC_AH] = { .l3_prot_type = MLX5_L3_PROT_TYPE_IPV4,
2729 .rx_hash_fields = MLX5_HASH_IP_IPSEC_SPI,
2731 [MLX5E_TT_IPV6_IPSEC_AH] = { .l3_prot_type = MLX5_L3_PROT_TYPE_IPV6,
2733 .rx_hash_fields = MLX5_HASH_IP_IPSEC_SPI,
2735 [MLX5E_TT_IPV4_IPSEC_ESP] = { .l3_prot_type = MLX5_L3_PROT_TYPE_IPV4,
2737 .rx_hash_fields = MLX5_HASH_IP_IPSEC_SPI,
2739 [MLX5E_TT_IPV6_IPSEC_ESP] = { .l3_prot_type = MLX5_L3_PROT_TYPE_IPV6,
2741 .rx_hash_fields = MLX5_HASH_IP_IPSEC_SPI,
2743 [MLX5E_TT_IPV4] = { .l3_prot_type = MLX5_L3_PROT_TYPE_IPV4,
2745 .rx_hash_fields = MLX5_HASH_IP,
2747 [MLX5E_TT_IPV6] = { .l3_prot_type = MLX5_L3_PROT_TYPE_IPV6,
2749 .rx_hash_fields = MLX5_HASH_IP,
2753 struct mlx5e_tirc_config mlx5e_tirc_get_default_config(enum mlx5e_traffic_types tt)
2755 return tirc_default_config[tt];
2758 static void mlx5e_build_tir_ctx_lro(struct mlx5e_params *params, void *tirc)
2760 if (!params->lro_en)
2763 #define ROUGH_MAX_L2_L3_HDR_SZ 256
2765 MLX5_SET(tirc, tirc, lro_enable_mask,
2766 MLX5_TIRC_LRO_ENABLE_MASK_IPV4_LRO |
2767 MLX5_TIRC_LRO_ENABLE_MASK_IPV6_LRO);
2768 MLX5_SET(tirc, tirc, lro_max_ip_payload_size,
2769 (MLX5E_PARAMS_DEFAULT_LRO_WQE_SZ - ROUGH_MAX_L2_L3_HDR_SZ) >> 8);
2770 MLX5_SET(tirc, tirc, lro_timeout_period_usecs, params->lro_timeout);
2773 void mlx5e_build_indir_tir_ctx_hash(struct mlx5e_rss_params *rss_params,
2774 const struct mlx5e_tirc_config *ttconfig,
2775 void *tirc, bool inner)
2777 void *hfso = inner ? MLX5_ADDR_OF(tirc, tirc, rx_hash_field_selector_inner) :
2778 MLX5_ADDR_OF(tirc, tirc, rx_hash_field_selector_outer);
2780 MLX5_SET(tirc, tirc, rx_hash_fn, mlx5e_rx_hash_fn(rss_params->hfunc));
2781 if (rss_params->hfunc == ETH_RSS_HASH_TOP) {
2782 void *rss_key = MLX5_ADDR_OF(tirc, tirc,
2783 rx_hash_toeplitz_key);
2784 size_t len = MLX5_FLD_SZ_BYTES(tirc,
2785 rx_hash_toeplitz_key);
2787 MLX5_SET(tirc, tirc, rx_hash_symmetric, 1);
2788 memcpy(rss_key, rss_params->toeplitz_hash_key, len);
2790 MLX5_SET(rx_hash_field_select, hfso, l3_prot_type,
2791 ttconfig->l3_prot_type);
2792 MLX5_SET(rx_hash_field_select, hfso, l4_prot_type,
2793 ttconfig->l4_prot_type);
2794 MLX5_SET(rx_hash_field_select, hfso, selected_fields,
2795 ttconfig->rx_hash_fields);
2798 static void mlx5e_update_rx_hash_fields(struct mlx5e_tirc_config *ttconfig,
2799 enum mlx5e_traffic_types tt,
2802 *ttconfig = tirc_default_config[tt];
2803 ttconfig->rx_hash_fields = rx_hash_fields;
2806 void mlx5e_modify_tirs_hash(struct mlx5e_priv *priv, void *in)
2808 void *tirc = MLX5_ADDR_OF(modify_tir_in, in, ctx);
2809 struct mlx5e_rss_params *rss = &priv->rss_params;
2810 struct mlx5_core_dev *mdev = priv->mdev;
2811 int ctxlen = MLX5_ST_SZ_BYTES(tirc);
2812 struct mlx5e_tirc_config ttconfig;
2815 MLX5_SET(modify_tir_in, in, bitmask.hash, 1);
2817 for (tt = 0; tt < MLX5E_NUM_INDIR_TIRS; tt++) {
2818 memset(tirc, 0, ctxlen);
2819 mlx5e_update_rx_hash_fields(&ttconfig, tt,
2820 rss->rx_hash_fields[tt]);
2821 mlx5e_build_indir_tir_ctx_hash(rss, &ttconfig, tirc, false);
2822 mlx5_core_modify_tir(mdev, priv->indir_tir[tt].tirn, in);
2825 /* Verify inner tirs resources allocated */
2826 if (!priv->inner_indir_tir[0].tirn)
2829 for (tt = 0; tt < MLX5E_NUM_INDIR_TIRS; tt++) {
2830 memset(tirc, 0, ctxlen);
2831 mlx5e_update_rx_hash_fields(&ttconfig, tt,
2832 rss->rx_hash_fields[tt]);
2833 mlx5e_build_indir_tir_ctx_hash(rss, &ttconfig, tirc, true);
2834 mlx5_core_modify_tir(mdev, priv->inner_indir_tir[tt].tirn, in);
2838 static int mlx5e_modify_tirs_lro(struct mlx5e_priv *priv)
2840 struct mlx5_core_dev *mdev = priv->mdev;
2849 inlen = MLX5_ST_SZ_BYTES(modify_tir_in);
2850 in = kvzalloc(inlen, GFP_KERNEL);
2854 MLX5_SET(modify_tir_in, in, bitmask.lro, 1);
2855 tirc = MLX5_ADDR_OF(modify_tir_in, in, ctx);
2857 mlx5e_build_tir_ctx_lro(&priv->channels.params, tirc);
2859 for (tt = 0; tt < MLX5E_NUM_INDIR_TIRS; tt++) {
2860 err = mlx5_core_modify_tir(mdev, priv->indir_tir[tt].tirn, in);
2865 for (ix = 0; ix < priv->max_nch; ix++) {
2866 err = mlx5_core_modify_tir(mdev, priv->direct_tir[ix].tirn, in);
2877 static MLX5E_DEFINE_PREACTIVATE_WRAPPER_CTX(mlx5e_modify_tirs_lro);
2879 static int mlx5e_set_mtu(struct mlx5_core_dev *mdev,
2880 struct mlx5e_params *params, u16 mtu)
2882 u16 hw_mtu = MLX5E_SW2HW_MTU(params, mtu);
2885 err = mlx5_set_port_mtu(mdev, hw_mtu, 1);
2889 /* Update vport context MTU */
2890 mlx5_modify_nic_vport_mtu(mdev, hw_mtu);
2894 static void mlx5e_query_mtu(struct mlx5_core_dev *mdev,
2895 struct mlx5e_params *params, u16 *mtu)
2900 err = mlx5_query_nic_vport_mtu(mdev, &hw_mtu);
2901 if (err || !hw_mtu) /* fallback to port oper mtu */
2902 mlx5_query_port_oper_mtu(mdev, &hw_mtu, 1);
2904 *mtu = MLX5E_HW2SW_MTU(params, hw_mtu);
2907 int mlx5e_set_dev_port_mtu(struct mlx5e_priv *priv)
2909 struct mlx5e_params *params = &priv->channels.params;
2910 struct net_device *netdev = priv->netdev;
2911 struct mlx5_core_dev *mdev = priv->mdev;
2915 err = mlx5e_set_mtu(mdev, params, params->sw_mtu);
2919 mlx5e_query_mtu(mdev, params, &mtu);
2920 if (mtu != params->sw_mtu)
2921 netdev_warn(netdev, "%s: VPort MTU %d is different than netdev mtu %d\n",
2922 __func__, mtu, params->sw_mtu);
2924 params->sw_mtu = mtu;
2928 MLX5E_DEFINE_PREACTIVATE_WRAPPER_CTX(mlx5e_set_dev_port_mtu);
2930 void mlx5e_set_netdev_mtu_boundaries(struct mlx5e_priv *priv)
2932 struct mlx5e_params *params = &priv->channels.params;
2933 struct net_device *netdev = priv->netdev;
2934 struct mlx5_core_dev *mdev = priv->mdev;
2937 /* MTU range: 68 - hw-specific max */
2938 netdev->min_mtu = ETH_MIN_MTU;
2940 mlx5_query_port_max_mtu(mdev, &max_mtu, 1);
2941 netdev->max_mtu = min_t(unsigned int, MLX5E_HW2SW_MTU(params, max_mtu),
2945 static void mlx5e_netdev_set_tcs(struct net_device *netdev, u16 nch, u8 ntc)
2949 netdev_reset_tc(netdev);
2954 netdev_set_num_tc(netdev, ntc);
2956 /* Map netdev TCs to offset 0
2957 * We have our own UP to TXQ mapping for QoS
2959 for (tc = 0; tc < ntc; tc++)
2960 netdev_set_tc_queue(netdev, tc, nch, 0);
2963 int mlx5e_update_tx_netdev_queues(struct mlx5e_priv *priv)
2965 int qos_queues, nch, ntc, num_txqs, err;
2967 qos_queues = mlx5e_qos_cur_leaf_nodes(priv);
2969 nch = priv->channels.params.num_channels;
2970 ntc = priv->channels.params.num_tc;
2971 num_txqs = nch * ntc + qos_queues;
2972 if (MLX5E_GET_PFLAG(&priv->channels.params, MLX5E_PFLAG_TX_PORT_TS))
2975 mlx5e_dbg(DRV, priv, "Setting num_txqs %d\n", num_txqs);
2976 err = netif_set_real_num_tx_queues(priv->netdev, num_txqs);
2978 netdev_warn(priv->netdev, "netif_set_real_num_tx_queues failed, %d\n", err);
2983 static int mlx5e_update_netdev_queues(struct mlx5e_priv *priv)
2985 struct net_device *netdev = priv->netdev;
2986 int old_num_txqs, old_ntc;
2987 int num_rxqs, nch, ntc;
2990 old_num_txqs = netdev->real_num_tx_queues;
2991 old_ntc = netdev->num_tc;
2993 nch = priv->channels.params.num_channels;
2994 ntc = priv->channels.params.num_tc;
2995 num_rxqs = nch * priv->profile->rq_groups;
2997 mlx5e_netdev_set_tcs(netdev, nch, ntc);
2999 err = mlx5e_update_tx_netdev_queues(priv);
3002 err = netif_set_real_num_rx_queues(netdev, num_rxqs);
3004 netdev_warn(netdev, "netif_set_real_num_rx_queues failed, %d\n", err);
3011 /* netif_set_real_num_rx_queues could fail only when nch increased. Only
3012 * one of nch and ntc is changed in this function. That means, the call
3013 * to netif_set_real_num_tx_queues below should not fail, because it
3014 * decreases the number of TX queues.
3016 WARN_ON_ONCE(netif_set_real_num_tx_queues(netdev, old_num_txqs));
3019 mlx5e_netdev_set_tcs(netdev, old_num_txqs / old_ntc, old_ntc);
3023 static void mlx5e_set_default_xps_cpumasks(struct mlx5e_priv *priv,
3024 struct mlx5e_params *params)
3026 struct mlx5_core_dev *mdev = priv->mdev;
3027 int num_comp_vectors, ix, irq;
3029 num_comp_vectors = mlx5_comp_vectors_count(mdev);
3031 for (ix = 0; ix < params->num_channels; ix++) {
3032 cpumask_clear(priv->scratchpad.cpumask);
3034 for (irq = ix; irq < num_comp_vectors; irq += params->num_channels) {
3035 int cpu = cpumask_first(mlx5_comp_irq_get_affinity_mask(mdev, irq));
3037 cpumask_set_cpu(cpu, priv->scratchpad.cpumask);
3040 netif_set_xps_queue(priv->netdev, priv->scratchpad.cpumask, ix);
3044 int mlx5e_num_channels_changed(struct mlx5e_priv *priv)
3046 u16 count = priv->channels.params.num_channels;
3049 err = mlx5e_update_netdev_queues(priv);
3053 mlx5e_set_default_xps_cpumasks(priv, &priv->channels.params);
3055 if (!netif_is_rxfh_configured(priv->netdev))
3056 mlx5e_build_default_indir_rqt(priv->rss_params.indirection_rqt,
3057 MLX5E_INDIR_RQT_SIZE, count);
3062 MLX5E_DEFINE_PREACTIVATE_WRAPPER_CTX(mlx5e_num_channels_changed);
3064 static void mlx5e_build_txq_maps(struct mlx5e_priv *priv)
3066 int i, ch, tc, num_tc;
3068 ch = priv->channels.num;
3069 num_tc = priv->channels.params.num_tc;
3071 for (i = 0; i < ch; i++) {
3072 for (tc = 0; tc < num_tc; tc++) {
3073 struct mlx5e_channel *c = priv->channels.c[i];
3074 struct mlx5e_txqsq *sq = &c->sq[tc];
3076 priv->txq2sq[sq->txq_ix] = sq;
3077 priv->channel_tc2realtxq[i][tc] = i + tc * ch;
3081 if (!priv->channels.port_ptp)
3084 for (tc = 0; tc < num_tc; tc++) {
3085 struct mlx5e_port_ptp *c = priv->channels.port_ptp;
3086 struct mlx5e_txqsq *sq = &c->ptpsq[tc].txqsq;
3088 priv->txq2sq[sq->txq_ix] = sq;
3089 priv->port_ptp_tc2realtxq[tc] = priv->num_tc_x_num_ch + tc;
3093 static void mlx5e_update_num_tc_x_num_ch(struct mlx5e_priv *priv)
3095 /* Sync with mlx5e_select_queue. */
3096 WRITE_ONCE(priv->num_tc_x_num_ch,
3097 priv->channels.params.num_tc * priv->channels.num);
3100 void mlx5e_activate_priv_channels(struct mlx5e_priv *priv)
3102 mlx5e_update_num_tc_x_num_ch(priv);
3103 mlx5e_build_txq_maps(priv);
3104 mlx5e_activate_channels(&priv->channels);
3105 mlx5e_qos_activate_queues(priv);
3106 mlx5e_xdp_tx_enable(priv);
3107 netif_tx_start_all_queues(priv->netdev);
3109 if (mlx5e_is_vport_rep(priv))
3110 mlx5e_add_sqs_fwd_rules(priv);
3112 mlx5e_wait_channels_min_rx_wqes(&priv->channels);
3113 mlx5e_redirect_rqts_to_channels(priv, &priv->channels);
3115 mlx5e_xsk_redirect_rqts_to_channels(priv, &priv->channels);
3118 void mlx5e_deactivate_priv_channels(struct mlx5e_priv *priv)
3120 mlx5e_xsk_redirect_rqts_to_drop(priv, &priv->channels);
3122 mlx5e_redirect_rqts_to_drop(priv);
3124 if (mlx5e_is_vport_rep(priv))
3125 mlx5e_remove_sqs_fwd_rules(priv);
3127 /* FIXME: This is a W/A only for tx timeout watch dog false alarm when
3128 * polling for inactive tx queues.
3130 netif_tx_stop_all_queues(priv->netdev);
3131 netif_tx_disable(priv->netdev);
3132 mlx5e_xdp_tx_disable(priv);
3133 mlx5e_deactivate_channels(&priv->channels);
3136 static int mlx5e_switch_priv_channels(struct mlx5e_priv *priv,
3137 struct mlx5e_channels *new_chs,
3138 mlx5e_fp_preactivate preactivate,
3141 struct net_device *netdev = priv->netdev;
3142 struct mlx5e_channels old_chs;
3146 carrier_ok = netif_carrier_ok(netdev);
3147 netif_carrier_off(netdev);
3149 mlx5e_deactivate_priv_channels(priv);
3151 old_chs = priv->channels;
3152 priv->channels = *new_chs;
3154 /* New channels are ready to roll, call the preactivate hook if needed
3155 * to modify HW settings or update kernel parameters.
3158 err = preactivate(priv, context);
3160 priv->channels = old_chs;
3165 mlx5e_close_channels(&old_chs);
3166 priv->profile->update_rx(priv);
3169 mlx5e_activate_priv_channels(priv);
3171 /* return carrier back if needed */
3173 netif_carrier_on(netdev);
3178 int mlx5e_safe_switch_channels(struct mlx5e_priv *priv,
3179 struct mlx5e_channels *new_chs,
3180 mlx5e_fp_preactivate preactivate,
3185 err = mlx5e_open_channels(priv, new_chs);
3189 err = mlx5e_switch_priv_channels(priv, new_chs, preactivate, context);
3196 mlx5e_close_channels(new_chs);
3201 int mlx5e_safe_reopen_channels(struct mlx5e_priv *priv)
3203 struct mlx5e_channels new_channels = {};
3205 new_channels.params = priv->channels.params;
3206 return mlx5e_safe_switch_channels(priv, &new_channels, NULL, NULL);
3209 void mlx5e_timestamp_init(struct mlx5e_priv *priv)
3211 priv->tstamp.tx_type = HWTSTAMP_TX_OFF;
3212 priv->tstamp.rx_filter = HWTSTAMP_FILTER_NONE;
3215 static void mlx5e_modify_admin_state(struct mlx5_core_dev *mdev,
3216 enum mlx5_port_status state)
3218 struct mlx5_eswitch *esw = mdev->priv.eswitch;
3219 int vport_admin_state;
3221 mlx5_set_port_admin_status(mdev, state);
3223 if (mlx5_eswitch_mode(mdev) == MLX5_ESWITCH_OFFLOADS ||
3224 !MLX5_CAP_GEN(mdev, uplink_follow))
3227 if (state == MLX5_PORT_UP)
3228 vport_admin_state = MLX5_VPORT_ADMIN_STATE_AUTO;
3230 vport_admin_state = MLX5_VPORT_ADMIN_STATE_DOWN;
3232 mlx5_eswitch_set_vport_state(esw, MLX5_VPORT_UPLINK, vport_admin_state);
3235 int mlx5e_open_locked(struct net_device *netdev)
3237 struct mlx5e_priv *priv = netdev_priv(netdev);
3240 set_bit(MLX5E_STATE_OPENED, &priv->state);
3242 err = mlx5e_open_channels(priv, &priv->channels);
3244 goto err_clear_state_opened_flag;
3246 priv->profile->update_rx(priv);
3247 mlx5e_activate_priv_channels(priv);
3248 mlx5e_apply_traps(priv, true);
3249 if (priv->profile->update_carrier)
3250 priv->profile->update_carrier(priv);
3252 mlx5e_queue_update_stats(priv);
3255 err_clear_state_opened_flag:
3256 clear_bit(MLX5E_STATE_OPENED, &priv->state);
3260 int mlx5e_open(struct net_device *netdev)
3262 struct mlx5e_priv *priv = netdev_priv(netdev);
3265 mutex_lock(&priv->state_lock);
3266 err = mlx5e_open_locked(netdev);
3268 mlx5e_modify_admin_state(priv->mdev, MLX5_PORT_UP);
3269 mutex_unlock(&priv->state_lock);
3274 int mlx5e_close_locked(struct net_device *netdev)
3276 struct mlx5e_priv *priv = netdev_priv(netdev);
3278 /* May already be CLOSED in case a previous configuration operation
3279 * (e.g RX/TX queue size change) that involves close&open failed.
3281 if (!test_bit(MLX5E_STATE_OPENED, &priv->state))
3284 mlx5e_apply_traps(priv, false);
3285 clear_bit(MLX5E_STATE_OPENED, &priv->state);
3287 netif_carrier_off(priv->netdev);
3288 mlx5e_deactivate_priv_channels(priv);
3289 mlx5e_close_channels(&priv->channels);
3294 int mlx5e_close(struct net_device *netdev)
3296 struct mlx5e_priv *priv = netdev_priv(netdev);
3299 if (!netif_device_present(netdev))
3302 mutex_lock(&priv->state_lock);
3303 mlx5e_modify_admin_state(priv->mdev, MLX5_PORT_DOWN);
3304 err = mlx5e_close_locked(netdev);
3305 mutex_unlock(&priv->state_lock);
3310 static void mlx5e_free_drop_rq(struct mlx5e_rq *rq)
3312 mlx5_wq_destroy(&rq->wq_ctrl);
3315 static int mlx5e_alloc_drop_rq(struct mlx5_core_dev *mdev,
3316 struct mlx5e_rq *rq,
3317 struct mlx5e_rq_param *param)
3319 void *rqc = param->rqc;
3320 void *rqc_wq = MLX5_ADDR_OF(rqc, rqc, wq);
3323 param->wq.db_numa_node = param->wq.buf_numa_node;
3325 err = mlx5_wq_cyc_create(mdev, ¶m->wq, rqc_wq, &rq->wqe.wq,
3330 /* Mark as unused given "Drop-RQ" packets never reach XDP */
3331 xdp_rxq_info_unused(&rq->xdp_rxq);
3338 static int mlx5e_alloc_drop_cq(struct mlx5e_priv *priv,
3339 struct mlx5e_cq *cq,
3340 struct mlx5e_cq_param *param)
3342 struct mlx5_core_dev *mdev = priv->mdev;
3344 param->wq.buf_numa_node = dev_to_node(mlx5_core_dma_dev(mdev));
3345 param->wq.db_numa_node = dev_to_node(mlx5_core_dma_dev(mdev));
3347 return mlx5e_alloc_cq_common(priv, param, cq);
3350 int mlx5e_open_drop_rq(struct mlx5e_priv *priv,
3351 struct mlx5e_rq *drop_rq)
3353 struct mlx5_core_dev *mdev = priv->mdev;
3354 struct mlx5e_cq_param cq_param = {};
3355 struct mlx5e_rq_param rq_param = {};
3356 struct mlx5e_cq *cq = &drop_rq->cq;
3359 mlx5e_build_drop_rq_param(priv, &rq_param);
3361 err = mlx5e_alloc_drop_cq(priv, cq, &cq_param);
3365 err = mlx5e_create_cq(cq, &cq_param);
3369 err = mlx5e_alloc_drop_rq(mdev, drop_rq, &rq_param);
3371 goto err_destroy_cq;
3373 err = mlx5e_create_rq(drop_rq, &rq_param);
3377 err = mlx5e_modify_rq_state(drop_rq, MLX5_RQC_STATE_RST, MLX5_RQC_STATE_RDY);
3379 mlx5_core_warn(priv->mdev, "modify_rq_state failed, rx_if_down_packets won't be counted %d\n", err);
3384 mlx5e_free_drop_rq(drop_rq);
3387 mlx5e_destroy_cq(cq);
3395 void mlx5e_close_drop_rq(struct mlx5e_rq *drop_rq)
3397 mlx5e_destroy_rq(drop_rq);
3398 mlx5e_free_drop_rq(drop_rq);
3399 mlx5e_destroy_cq(&drop_rq->cq);
3400 mlx5e_free_cq(&drop_rq->cq);
3403 int mlx5e_create_tis(struct mlx5_core_dev *mdev, void *in, u32 *tisn)
3405 void *tisc = MLX5_ADDR_OF(create_tis_in, in, ctx);
3407 MLX5_SET(tisc, tisc, transport_domain, mdev->mlx5e_res.td.tdn);
3409 if (MLX5_GET(tisc, tisc, tls_en))
3410 MLX5_SET(tisc, tisc, pd, mdev->mlx5e_res.pdn);
3412 if (mlx5_lag_is_lacp_owner(mdev))
3413 MLX5_SET(tisc, tisc, strict_lag_tx_port_affinity, 1);
3415 return mlx5_core_create_tis(mdev, in, tisn);
3418 void mlx5e_destroy_tis(struct mlx5_core_dev *mdev, u32 tisn)
3420 mlx5_core_destroy_tis(mdev, tisn);
3423 void mlx5e_destroy_tises(struct mlx5e_priv *priv)
3427 for (i = 0; i < mlx5e_get_num_lag_ports(priv->mdev); i++)
3428 for (tc = 0; tc < priv->profile->max_tc; tc++)
3429 mlx5e_destroy_tis(priv->mdev, priv->tisn[i][tc]);
3432 static bool mlx5e_lag_should_assign_affinity(struct mlx5_core_dev *mdev)
3434 return MLX5_CAP_GEN(mdev, lag_tx_port_affinity) && mlx5e_get_num_lag_ports(mdev) > 1;
3437 int mlx5e_create_tises(struct mlx5e_priv *priv)
3442 for (i = 0; i < mlx5e_get_num_lag_ports(priv->mdev); i++) {
3443 for (tc = 0; tc < priv->profile->max_tc; tc++) {
3444 u32 in[MLX5_ST_SZ_DW(create_tis_in)] = {};
3447 tisc = MLX5_ADDR_OF(create_tis_in, in, ctx);
3449 MLX5_SET(tisc, tisc, prio, tc << 1);
3451 if (mlx5e_lag_should_assign_affinity(priv->mdev))
3452 MLX5_SET(tisc, tisc, lag_tx_port_affinity, i + 1);
3454 err = mlx5e_create_tis(priv->mdev, in, &priv->tisn[i][tc]);
3456 goto err_close_tises;
3463 for (; i >= 0; i--) {
3464 for (tc--; tc >= 0; tc--)
3465 mlx5e_destroy_tis(priv->mdev, priv->tisn[i][tc]);
3466 tc = priv->profile->max_tc;
3472 static void mlx5e_cleanup_nic_tx(struct mlx5e_priv *priv)
3474 mlx5e_destroy_tises(priv);
3477 static void mlx5e_build_indir_tir_ctx_common(struct mlx5e_priv *priv,
3478 u32 rqtn, u32 *tirc)
3480 MLX5_SET(tirc, tirc, transport_domain, priv->mdev->mlx5e_res.td.tdn);
3481 MLX5_SET(tirc, tirc, disp_type, MLX5_TIRC_DISP_TYPE_INDIRECT);
3482 MLX5_SET(tirc, tirc, indirect_table, rqtn);
3483 MLX5_SET(tirc, tirc, tunneled_offload_en,
3484 priv->channels.params.tunneled_offload_en);
3486 mlx5e_build_tir_ctx_lro(&priv->channels.params, tirc);
3489 static void mlx5e_build_indir_tir_ctx(struct mlx5e_priv *priv,
3490 enum mlx5e_traffic_types tt,
3493 mlx5e_build_indir_tir_ctx_common(priv, priv->indir_rqt.rqtn, tirc);
3494 mlx5e_build_indir_tir_ctx_hash(&priv->rss_params,
3495 &tirc_default_config[tt], tirc, false);
3498 static void mlx5e_build_direct_tir_ctx(struct mlx5e_priv *priv, u32 rqtn, u32 *tirc)
3500 mlx5e_build_indir_tir_ctx_common(priv, rqtn, tirc);
3501 MLX5_SET(tirc, tirc, rx_hash_fn, MLX5_RX_HASH_FN_INVERTED_XOR8);
3504 static void mlx5e_build_inner_indir_tir_ctx(struct mlx5e_priv *priv,
3505 enum mlx5e_traffic_types tt,
3508 mlx5e_build_indir_tir_ctx_common(priv, priv->indir_rqt.rqtn, tirc);
3509 mlx5e_build_indir_tir_ctx_hash(&priv->rss_params,
3510 &tirc_default_config[tt], tirc, true);
3513 int mlx5e_create_indirect_tirs(struct mlx5e_priv *priv, bool inner_ttc)
3515 struct mlx5e_tir *tir;
3523 inlen = MLX5_ST_SZ_BYTES(create_tir_in);
3524 in = kvzalloc(inlen, GFP_KERNEL);
3528 for (tt = 0; tt < MLX5E_NUM_INDIR_TIRS; tt++) {
3529 memset(in, 0, inlen);
3530 tir = &priv->indir_tir[tt];
3531 tirc = MLX5_ADDR_OF(create_tir_in, in, ctx);
3532 mlx5e_build_indir_tir_ctx(priv, tt, tirc);
3533 err = mlx5e_create_tir(priv->mdev, tir, in);
3535 mlx5_core_warn(priv->mdev, "create indirect tirs failed, %d\n", err);
3536 goto err_destroy_inner_tirs;
3540 if (!inner_ttc || !mlx5e_tunnel_inner_ft_supported(priv->mdev))
3543 for (i = 0; i < MLX5E_NUM_INDIR_TIRS; i++) {
3544 memset(in, 0, inlen);
3545 tir = &priv->inner_indir_tir[i];
3546 tirc = MLX5_ADDR_OF(create_tir_in, in, ctx);
3547 mlx5e_build_inner_indir_tir_ctx(priv, i, tirc);
3548 err = mlx5e_create_tir(priv->mdev, tir, in);
3550 mlx5_core_warn(priv->mdev, "create inner indirect tirs failed, %d\n", err);
3551 goto err_destroy_inner_tirs;
3560 err_destroy_inner_tirs:
3561 for (i--; i >= 0; i--)
3562 mlx5e_destroy_tir(priv->mdev, &priv->inner_indir_tir[i]);
3564 for (tt--; tt >= 0; tt--)
3565 mlx5e_destroy_tir(priv->mdev, &priv->indir_tir[tt]);
3572 int mlx5e_create_direct_tirs(struct mlx5e_priv *priv, struct mlx5e_tir *tirs)
3574 struct mlx5e_tir *tir;
3581 inlen = MLX5_ST_SZ_BYTES(create_tir_in);
3582 in = kvzalloc(inlen, GFP_KERNEL);
3586 for (ix = 0; ix < priv->max_nch; ix++) {
3587 memset(in, 0, inlen);
3589 tirc = MLX5_ADDR_OF(create_tir_in, in, ctx);
3590 mlx5e_build_direct_tir_ctx(priv, tir->rqt.rqtn, tirc);
3591 err = mlx5e_create_tir(priv->mdev, tir, in);
3593 goto err_destroy_ch_tirs;
3598 err_destroy_ch_tirs:
3599 mlx5_core_warn(priv->mdev, "create tirs failed, %d\n", err);
3600 for (ix--; ix >= 0; ix--)
3601 mlx5e_destroy_tir(priv->mdev, &tirs[ix]);
3609 void mlx5e_destroy_indirect_tirs(struct mlx5e_priv *priv)
3613 for (i = 0; i < MLX5E_NUM_INDIR_TIRS; i++)
3614 mlx5e_destroy_tir(priv->mdev, &priv->indir_tir[i]);
3616 /* Verify inner tirs resources allocated */
3617 if (!priv->inner_indir_tir[0].tirn)
3620 for (i = 0; i < MLX5E_NUM_INDIR_TIRS; i++)
3621 mlx5e_destroy_tir(priv->mdev, &priv->inner_indir_tir[i]);
3624 void mlx5e_destroy_direct_tirs(struct mlx5e_priv *priv, struct mlx5e_tir *tirs)
3628 for (i = 0; i < priv->max_nch; i++)
3629 mlx5e_destroy_tir(priv->mdev, &tirs[i]);
3632 static int mlx5e_modify_channels_scatter_fcs(struct mlx5e_channels *chs, bool enable)
3637 for (i = 0; i < chs->num; i++) {
3638 err = mlx5e_modify_rq_scatter_fcs(&chs->c[i]->rq, enable);
3646 static int mlx5e_modify_channels_vsd(struct mlx5e_channels *chs, bool vsd)
3651 for (i = 0; i < chs->num; i++) {
3652 err = mlx5e_modify_rq_vsd(&chs->c[i]->rq, vsd);
3660 static int mlx5e_setup_tc_mqprio(struct mlx5e_priv *priv,
3661 struct tc_mqprio_qopt *mqprio)
3663 struct mlx5e_channels new_channels = {};
3664 u8 tc = mqprio->num_tc;
3667 mqprio->hw = TC_MQPRIO_HW_OFFLOAD_TCS;
3669 if (tc && tc != MLX5E_MAX_NUM_TC)
3672 mutex_lock(&priv->state_lock);
3674 /* MQPRIO is another toplevel qdisc that can't be attached
3675 * simultaneously with the offloaded HTB.
3677 if (WARN_ON(priv->htb.maj_id)) {
3682 new_channels.params = priv->channels.params;
3683 new_channels.params.num_tc = tc ? tc : 1;
3685 if (!test_bit(MLX5E_STATE_OPENED, &priv->state)) {
3686 struct mlx5e_params old_params;
3688 old_params = priv->channels.params;
3689 priv->channels.params = new_channels.params;
3690 err = mlx5e_num_channels_changed(priv);
3692 priv->channels.params = old_params;
3697 err = mlx5e_safe_switch_channels(priv, &new_channels,
3698 mlx5e_num_channels_changed_ctx, NULL);
3701 priv->max_opened_tc = max_t(u8, priv->max_opened_tc,
3702 priv->channels.params.num_tc);
3703 mutex_unlock(&priv->state_lock);
3707 static int mlx5e_setup_tc_htb(struct mlx5e_priv *priv, struct tc_htb_qopt_offload *htb)
3711 switch (htb->command) {
3713 return mlx5e_htb_root_add(priv, htb->parent_classid, htb->classid,
3715 case TC_HTB_DESTROY:
3716 return mlx5e_htb_root_del(priv);
3717 case TC_HTB_LEAF_ALLOC_QUEUE:
3718 res = mlx5e_htb_leaf_alloc_queue(priv, htb->classid, htb->parent_classid,
3719 htb->rate, htb->ceil, htb->extack);
3724 case TC_HTB_LEAF_TO_INNER:
3725 return mlx5e_htb_leaf_to_inner(priv, htb->parent_classid, htb->classid,
3726 htb->rate, htb->ceil, htb->extack);
3727 case TC_HTB_LEAF_DEL:
3728 return mlx5e_htb_leaf_del(priv, htb->classid, &htb->moved_qid, &htb->qid,
3730 case TC_HTB_LEAF_DEL_LAST:
3731 case TC_HTB_LEAF_DEL_LAST_FORCE:
3732 return mlx5e_htb_leaf_del_last(priv, htb->classid,
3733 htb->command == TC_HTB_LEAF_DEL_LAST_FORCE,
3735 case TC_HTB_NODE_MODIFY:
3736 return mlx5e_htb_node_modify(priv, htb->classid, htb->rate, htb->ceil,
3738 case TC_HTB_LEAF_QUERY_QUEUE:
3739 res = mlx5e_get_txq_by_classid(priv, htb->classid);
3749 static LIST_HEAD(mlx5e_block_cb_list);
3751 static int mlx5e_setup_tc(struct net_device *dev, enum tc_setup_type type,
3754 struct mlx5e_priv *priv = netdev_priv(dev);
3758 case TC_SETUP_BLOCK: {
3759 struct flow_block_offload *f = type_data;
3761 f->unlocked_driver_cb = true;
3762 return flow_block_cb_setup_simple(type_data,
3763 &mlx5e_block_cb_list,
3764 mlx5e_setup_tc_block_cb,
3767 case TC_SETUP_QDISC_MQPRIO:
3768 return mlx5e_setup_tc_mqprio(priv, type_data);
3769 case TC_SETUP_QDISC_HTB:
3770 mutex_lock(&priv->state_lock);
3771 err = mlx5e_setup_tc_htb(priv, type_data);
3772 mutex_unlock(&priv->state_lock);
3779 void mlx5e_fold_sw_stats64(struct mlx5e_priv *priv, struct rtnl_link_stats64 *s)
3783 for (i = 0; i < priv->max_nch; i++) {
3784 struct mlx5e_channel_stats *channel_stats = &priv->channel_stats[i];
3785 struct mlx5e_rq_stats *xskrq_stats = &channel_stats->xskrq;
3786 struct mlx5e_rq_stats *rq_stats = &channel_stats->rq;
3789 s->rx_packets += rq_stats->packets + xskrq_stats->packets;
3790 s->rx_bytes += rq_stats->bytes + xskrq_stats->bytes;
3791 s->multicast += rq_stats->mcast_packets + xskrq_stats->mcast_packets;
3793 for (j = 0; j < priv->max_opened_tc; j++) {
3794 struct mlx5e_sq_stats *sq_stats = &channel_stats->sq[j];
3796 s->tx_packets += sq_stats->packets;
3797 s->tx_bytes += sq_stats->bytes;
3798 s->tx_dropped += sq_stats->dropped;
3804 mlx5e_get_stats(struct net_device *dev, struct rtnl_link_stats64 *stats)
3806 struct mlx5e_priv *priv = netdev_priv(dev);
3807 struct mlx5e_pport_stats *pstats = &priv->stats.pport;
3809 /* In switchdev mode, monitor counters doesn't monitor
3810 * rx/tx stats of 802_3. The update stats mechanism
3811 * should keep the 802_3 layout counters updated
3813 if (!mlx5e_monitor_counter_supported(priv) ||
3814 mlx5e_is_uplink_rep(priv)) {
3815 /* update HW stats in background for next time */
3816 mlx5e_queue_update_stats(priv);
3819 if (mlx5e_is_uplink_rep(priv)) {
3820 stats->rx_packets = PPORT_802_3_GET(pstats, a_frames_received_ok);
3821 stats->rx_bytes = PPORT_802_3_GET(pstats, a_octets_received_ok);
3822 stats->tx_packets = PPORT_802_3_GET(pstats, a_frames_transmitted_ok);
3823 stats->tx_bytes = PPORT_802_3_GET(pstats, a_octets_transmitted_ok);
3825 mlx5e_fold_sw_stats64(priv, stats);
3828 stats->rx_dropped = priv->stats.qcnt.rx_out_of_buffer;
3830 stats->rx_length_errors =
3831 PPORT_802_3_GET(pstats, a_in_range_length_errors) +
3832 PPORT_802_3_GET(pstats, a_out_of_range_length_field) +
3833 PPORT_802_3_GET(pstats, a_frame_too_long_errors);
3834 stats->rx_crc_errors =
3835 PPORT_802_3_GET(pstats, a_frame_check_sequence_errors);
3836 stats->rx_frame_errors = PPORT_802_3_GET(pstats, a_alignment_errors);
3837 stats->tx_aborted_errors = PPORT_2863_GET(pstats, if_out_discards);
3838 stats->rx_errors = stats->rx_length_errors + stats->rx_crc_errors +
3839 stats->rx_frame_errors;
3840 stats->tx_errors = stats->tx_aborted_errors + stats->tx_carrier_errors;
3843 static void mlx5e_set_rx_mode(struct net_device *dev)
3845 struct mlx5e_priv *priv = netdev_priv(dev);
3847 queue_work(priv->wq, &priv->set_rx_mode_work);
3850 static int mlx5e_set_mac(struct net_device *netdev, void *addr)
3852 struct mlx5e_priv *priv = netdev_priv(netdev);
3853 struct sockaddr *saddr = addr;
3855 if (!is_valid_ether_addr(saddr->sa_data))
3856 return -EADDRNOTAVAIL;
3858 netif_addr_lock_bh(netdev);
3859 ether_addr_copy(netdev->dev_addr, saddr->sa_data);
3860 netif_addr_unlock_bh(netdev);
3862 queue_work(priv->wq, &priv->set_rx_mode_work);
3867 #define MLX5E_SET_FEATURE(features, feature, enable) \
3870 *features |= feature; \
3872 *features &= ~feature; \
3875 typedef int (*mlx5e_feature_handler)(struct net_device *netdev, bool enable);
3877 static int set_feature_lro(struct net_device *netdev, bool enable)
3879 struct mlx5e_priv *priv = netdev_priv(netdev);
3880 struct mlx5_core_dev *mdev = priv->mdev;
3881 struct mlx5e_channels new_channels = {};
3882 struct mlx5e_params *cur_params;
3886 mutex_lock(&priv->state_lock);
3888 if (enable && priv->xsk.refcnt) {
3889 netdev_warn(netdev, "LRO is incompatible with AF_XDP (%u XSKs are active)\n",
3895 cur_params = &priv->channels.params;
3896 if (enable && !MLX5E_GET_PFLAG(cur_params, MLX5E_PFLAG_RX_STRIDING_RQ)) {
3897 netdev_warn(netdev, "can't set LRO with legacy RQ\n");
3902 reset = test_bit(MLX5E_STATE_OPENED, &priv->state);
3904 new_channels.params = *cur_params;
3905 new_channels.params.lro_en = enable;
3907 if (cur_params->rq_wq_type != MLX5_WQ_TYPE_CYCLIC) {
3908 if (mlx5e_rx_mpwqe_is_linear_skb(mdev, cur_params, NULL) ==
3909 mlx5e_rx_mpwqe_is_linear_skb(mdev, &new_channels.params, NULL))
3914 struct mlx5e_params old_params;
3916 old_params = *cur_params;
3917 *cur_params = new_channels.params;
3918 err = mlx5e_modify_tirs_lro(priv);
3920 *cur_params = old_params;
3924 err = mlx5e_safe_switch_channels(priv, &new_channels,
3925 mlx5e_modify_tirs_lro_ctx, NULL);
3927 mutex_unlock(&priv->state_lock);
3931 static int set_feature_cvlan_filter(struct net_device *netdev, bool enable)
3933 struct mlx5e_priv *priv = netdev_priv(netdev);
3936 mlx5e_enable_cvlan_filter(priv);
3938 mlx5e_disable_cvlan_filter(priv);
3943 static int set_feature_hw_tc(struct net_device *netdev, bool enable)
3945 struct mlx5e_priv *priv = netdev_priv(netdev);
3947 #if IS_ENABLED(CONFIG_MLX5_CLS_ACT)
3948 if (!enable && mlx5e_tc_num_filters(priv, MLX5_TC_FLAG(NIC_OFFLOAD))) {
3950 "Active offloaded tc filters, can't turn hw_tc_offload off\n");
3955 if (!enable && priv->htb.maj_id) {
3956 netdev_err(netdev, "Active HTB offload, can't turn hw_tc_offload off\n");
3963 static int set_feature_rx_all(struct net_device *netdev, bool enable)
3965 struct mlx5e_priv *priv = netdev_priv(netdev);
3966 struct mlx5_core_dev *mdev = priv->mdev;
3968 return mlx5_set_port_fcs(mdev, !enable);
3971 static int set_feature_rx_fcs(struct net_device *netdev, bool enable)
3973 struct mlx5e_priv *priv = netdev_priv(netdev);
3976 mutex_lock(&priv->state_lock);
3978 priv->channels.params.scatter_fcs_en = enable;
3979 err = mlx5e_modify_channels_scatter_fcs(&priv->channels, enable);
3981 priv->channels.params.scatter_fcs_en = !enable;
3983 mutex_unlock(&priv->state_lock);
3988 static int set_feature_rx_vlan(struct net_device *netdev, bool enable)
3990 struct mlx5e_priv *priv = netdev_priv(netdev);
3993 mutex_lock(&priv->state_lock);
3995 priv->channels.params.vlan_strip_disable = !enable;
3996 if (!test_bit(MLX5E_STATE_OPENED, &priv->state))
3999 err = mlx5e_modify_channels_vsd(&priv->channels, !enable);
4001 priv->channels.params.vlan_strip_disable = enable;
4004 mutex_unlock(&priv->state_lock);
4009 #ifdef CONFIG_MLX5_EN_ARFS
4010 static int set_feature_arfs(struct net_device *netdev, bool enable)
4012 struct mlx5e_priv *priv = netdev_priv(netdev);
4016 err = mlx5e_arfs_enable(priv);
4018 err = mlx5e_arfs_disable(priv);
4024 static int mlx5e_handle_feature(struct net_device *netdev,
4025 netdev_features_t *features,
4026 netdev_features_t wanted_features,
4027 netdev_features_t feature,
4028 mlx5e_feature_handler feature_handler)
4030 netdev_features_t changes = wanted_features ^ netdev->features;
4031 bool enable = !!(wanted_features & feature);
4034 if (!(changes & feature))
4037 err = feature_handler(netdev, enable);
4039 netdev_err(netdev, "%s feature %pNF failed, err %d\n",
4040 enable ? "Enable" : "Disable", &feature, err);
4044 MLX5E_SET_FEATURE(features, feature, enable);
4048 int mlx5e_set_features(struct net_device *netdev, netdev_features_t features)
4050 netdev_features_t oper_features = netdev->features;
4053 #define MLX5E_HANDLE_FEATURE(feature, handler) \
4054 mlx5e_handle_feature(netdev, &oper_features, features, feature, handler)
4056 err |= MLX5E_HANDLE_FEATURE(NETIF_F_LRO, set_feature_lro);
4057 err |= MLX5E_HANDLE_FEATURE(NETIF_F_HW_VLAN_CTAG_FILTER,
4058 set_feature_cvlan_filter);
4059 err |= MLX5E_HANDLE_FEATURE(NETIF_F_HW_TC, set_feature_hw_tc);
4060 err |= MLX5E_HANDLE_FEATURE(NETIF_F_RXALL, set_feature_rx_all);
4061 err |= MLX5E_HANDLE_FEATURE(NETIF_F_RXFCS, set_feature_rx_fcs);
4062 err |= MLX5E_HANDLE_FEATURE(NETIF_F_HW_VLAN_CTAG_RX, set_feature_rx_vlan);
4063 #ifdef CONFIG_MLX5_EN_ARFS
4064 err |= MLX5E_HANDLE_FEATURE(NETIF_F_NTUPLE, set_feature_arfs);
4066 err |= MLX5E_HANDLE_FEATURE(NETIF_F_HW_TLS_RX, mlx5e_ktls_set_feature_rx);
4069 netdev->features = oper_features;
4076 static netdev_features_t mlx5e_fix_features(struct net_device *netdev,
4077 netdev_features_t features)
4079 struct mlx5e_priv *priv = netdev_priv(netdev);
4080 struct mlx5e_params *params;
4082 mutex_lock(&priv->state_lock);
4083 params = &priv->channels.params;
4084 if (!bitmap_empty(priv->fs.vlan.active_svlans, VLAN_N_VID)) {
4085 /* HW strips the outer C-tag header, this is a problem
4086 * for S-tag traffic.
4088 features &= ~NETIF_F_HW_VLAN_CTAG_RX;
4089 if (!params->vlan_strip_disable)
4090 netdev_warn(netdev, "Dropping C-tag vlan stripping offload due to S-tag vlan\n");
4093 if (!MLX5E_GET_PFLAG(params, MLX5E_PFLAG_RX_STRIDING_RQ)) {
4094 if (features & NETIF_F_LRO) {
4095 netdev_warn(netdev, "Disabling LRO, not supported in legacy RQ\n");
4096 features &= ~NETIF_F_LRO;
4100 if (MLX5E_GET_PFLAG(params, MLX5E_PFLAG_RX_CQE_COMPRESS)) {
4101 features &= ~NETIF_F_RXHASH;
4102 if (netdev->features & NETIF_F_RXHASH)
4103 netdev_warn(netdev, "Disabling rxhash, not supported when CQE compress is active\n");
4106 mutex_unlock(&priv->state_lock);
4111 static bool mlx5e_xsk_validate_mtu(struct net_device *netdev,
4112 struct mlx5e_channels *chs,
4113 struct mlx5e_params *new_params,
4114 struct mlx5_core_dev *mdev)
4118 for (ix = 0; ix < chs->params.num_channels; ix++) {
4119 struct xsk_buff_pool *xsk_pool =
4120 mlx5e_xsk_get_pool(&chs->params, chs->params.xsk, ix);
4121 struct mlx5e_xsk_param xsk;
4126 mlx5e_build_xsk_param(xsk_pool, &xsk);
4128 if (!mlx5e_validate_xsk_param(new_params, &xsk, mdev)) {
4129 u32 hr = mlx5e_get_linear_rq_headroom(new_params, &xsk);
4130 int max_mtu_frame, max_mtu_page, max_mtu;
4132 /* Two criteria must be met:
4133 * 1. HW MTU + all headrooms <= XSK frame size.
4134 * 2. Size of SKBs allocated on XDP_PASS <= PAGE_SIZE.
4136 max_mtu_frame = MLX5E_HW2SW_MTU(new_params, xsk.chunk_size - hr);
4137 max_mtu_page = mlx5e_xdp_max_mtu(new_params, &xsk);
4138 max_mtu = min(max_mtu_frame, max_mtu_page);
4140 netdev_err(netdev, "MTU %d is too big for an XSK running on channel %u. Try MTU <= %d\n",
4141 new_params->sw_mtu, ix, max_mtu);
4149 int mlx5e_change_mtu(struct net_device *netdev, int new_mtu,
4150 mlx5e_fp_preactivate preactivate)
4152 struct mlx5e_priv *priv = netdev_priv(netdev);
4153 struct mlx5e_channels new_channels = {};
4154 struct mlx5e_params *params;
4158 mutex_lock(&priv->state_lock);
4160 params = &priv->channels.params;
4162 reset = !params->lro_en;
4163 reset = reset && test_bit(MLX5E_STATE_OPENED, &priv->state);
4165 new_channels.params = *params;
4166 new_channels.params.sw_mtu = new_mtu;
4167 err = mlx5e_validate_params(priv, &new_channels.params);
4171 if (params->xdp_prog &&
4172 !mlx5e_rx_is_linear_skb(&new_channels.params, NULL)) {
4173 netdev_err(netdev, "MTU(%d) > %d is not allowed while XDP enabled\n",
4174 new_mtu, mlx5e_xdp_max_mtu(params, NULL));
4179 if (priv->xsk.refcnt &&
4180 !mlx5e_xsk_validate_mtu(netdev, &priv->channels,
4181 &new_channels.params, priv->mdev)) {
4186 if (params->rq_wq_type == MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ) {
4187 bool is_linear = mlx5e_rx_mpwqe_is_linear_skb(priv->mdev,
4188 &new_channels.params,
4190 u8 ppw_old = mlx5e_mpwqe_log_pkts_per_wqe(params, NULL);
4191 u8 ppw_new = mlx5e_mpwqe_log_pkts_per_wqe(&new_channels.params, NULL);
4193 /* If XSK is active, XSK RQs are linear. */
4194 is_linear |= priv->xsk.refcnt;
4196 /* Always reset in linear mode - hw_mtu is used in data path. */
4197 reset = reset && (is_linear || (ppw_old != ppw_new));
4201 unsigned int old_mtu = params->sw_mtu;
4203 params->sw_mtu = new_mtu;
4205 err = preactivate(priv, NULL);
4207 params->sw_mtu = old_mtu;
4211 netdev->mtu = params->sw_mtu;
4215 err = mlx5e_safe_switch_channels(priv, &new_channels, preactivate, NULL);
4219 netdev->mtu = new_channels.params.sw_mtu;
4222 mutex_unlock(&priv->state_lock);
4226 static int mlx5e_change_nic_mtu(struct net_device *netdev, int new_mtu)
4228 return mlx5e_change_mtu(netdev, new_mtu, mlx5e_set_dev_port_mtu_ctx);
4231 int mlx5e_hwstamp_set(struct mlx5e_priv *priv, struct ifreq *ifr)
4233 struct hwtstamp_config config;
4236 if (!MLX5_CAP_GEN(priv->mdev, device_frequency_khz) ||
4237 (mlx5_clock_get_ptp_index(priv->mdev) == -1))
4240 if (copy_from_user(&config, ifr->ifr_data, sizeof(config)))
4243 /* TX HW timestamp */
4244 switch (config.tx_type) {
4245 case HWTSTAMP_TX_OFF:
4246 case HWTSTAMP_TX_ON:
4252 mutex_lock(&priv->state_lock);
4253 /* RX HW timestamp */
4254 switch (config.rx_filter) {
4255 case HWTSTAMP_FILTER_NONE:
4256 /* Reset CQE compression to Admin default */
4257 mlx5e_modify_rx_cqe_compression_locked(priv, priv->channels.params.rx_cqe_compress_def);
4259 case HWTSTAMP_FILTER_ALL:
4260 case HWTSTAMP_FILTER_SOME:
4261 case HWTSTAMP_FILTER_PTP_V1_L4_EVENT:
4262 case HWTSTAMP_FILTER_PTP_V1_L4_SYNC:
4263 case HWTSTAMP_FILTER_PTP_V1_L4_DELAY_REQ:
4264 case HWTSTAMP_FILTER_PTP_V2_L4_EVENT:
4265 case HWTSTAMP_FILTER_PTP_V2_L4_SYNC:
4266 case HWTSTAMP_FILTER_PTP_V2_L4_DELAY_REQ:
4267 case HWTSTAMP_FILTER_PTP_V2_L2_EVENT:
4268 case HWTSTAMP_FILTER_PTP_V2_L2_SYNC:
4269 case HWTSTAMP_FILTER_PTP_V2_L2_DELAY_REQ:
4270 case HWTSTAMP_FILTER_PTP_V2_EVENT:
4271 case HWTSTAMP_FILTER_PTP_V2_SYNC:
4272 case HWTSTAMP_FILTER_PTP_V2_DELAY_REQ:
4273 case HWTSTAMP_FILTER_NTP_ALL:
4274 /* Disable CQE compression */
4275 if (MLX5E_GET_PFLAG(&priv->channels.params, MLX5E_PFLAG_RX_CQE_COMPRESS))
4276 netdev_warn(priv->netdev, "Disabling RX cqe compression\n");
4277 err = mlx5e_modify_rx_cqe_compression_locked(priv, false);
4279 netdev_err(priv->netdev, "Failed disabling cqe compression err=%d\n", err);
4280 mutex_unlock(&priv->state_lock);
4283 config.rx_filter = HWTSTAMP_FILTER_ALL;
4286 mutex_unlock(&priv->state_lock);
4290 memcpy(&priv->tstamp, &config, sizeof(config));
4291 mutex_unlock(&priv->state_lock);
4293 /* might need to fix some features */
4294 netdev_update_features(priv->netdev);
4296 return copy_to_user(ifr->ifr_data, &config,
4297 sizeof(config)) ? -EFAULT : 0;
4300 int mlx5e_hwstamp_get(struct mlx5e_priv *priv, struct ifreq *ifr)
4302 struct hwtstamp_config *cfg = &priv->tstamp;
4304 if (!MLX5_CAP_GEN(priv->mdev, device_frequency_khz))
4307 return copy_to_user(ifr->ifr_data, cfg, sizeof(*cfg)) ? -EFAULT : 0;
4310 static int mlx5e_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
4312 struct mlx5e_priv *priv = netdev_priv(dev);
4316 return mlx5e_hwstamp_set(priv, ifr);
4318 return mlx5e_hwstamp_get(priv, ifr);
4324 #ifdef CONFIG_MLX5_ESWITCH
4325 int mlx5e_set_vf_mac(struct net_device *dev, int vf, u8 *mac)
4327 struct mlx5e_priv *priv = netdev_priv(dev);
4328 struct mlx5_core_dev *mdev = priv->mdev;
4330 return mlx5_eswitch_set_vport_mac(mdev->priv.eswitch, vf + 1, mac);
4333 static int mlx5e_set_vf_vlan(struct net_device *dev, int vf, u16 vlan, u8 qos,
4336 struct mlx5e_priv *priv = netdev_priv(dev);
4337 struct mlx5_core_dev *mdev = priv->mdev;
4339 if (vlan_proto != htons(ETH_P_8021Q))
4340 return -EPROTONOSUPPORT;
4342 return mlx5_eswitch_set_vport_vlan(mdev->priv.eswitch, vf + 1,
4346 static int mlx5e_set_vf_spoofchk(struct net_device *dev, int vf, bool setting)
4348 struct mlx5e_priv *priv = netdev_priv(dev);
4349 struct mlx5_core_dev *mdev = priv->mdev;
4351 return mlx5_eswitch_set_vport_spoofchk(mdev->priv.eswitch, vf + 1, setting);
4354 static int mlx5e_set_vf_trust(struct net_device *dev, int vf, bool setting)
4356 struct mlx5e_priv *priv = netdev_priv(dev);
4357 struct mlx5_core_dev *mdev = priv->mdev;
4359 return mlx5_eswitch_set_vport_trust(mdev->priv.eswitch, vf + 1, setting);
4362 int mlx5e_set_vf_rate(struct net_device *dev, int vf, int min_tx_rate,
4365 struct mlx5e_priv *priv = netdev_priv(dev);
4366 struct mlx5_core_dev *mdev = priv->mdev;
4368 return mlx5_eswitch_set_vport_rate(mdev->priv.eswitch, vf + 1,
4369 max_tx_rate, min_tx_rate);
4372 static int mlx5_vport_link2ifla(u8 esw_link)
4375 case MLX5_VPORT_ADMIN_STATE_DOWN:
4376 return IFLA_VF_LINK_STATE_DISABLE;
4377 case MLX5_VPORT_ADMIN_STATE_UP:
4378 return IFLA_VF_LINK_STATE_ENABLE;
4380 return IFLA_VF_LINK_STATE_AUTO;
4383 static int mlx5_ifla_link2vport(u8 ifla_link)
4385 switch (ifla_link) {
4386 case IFLA_VF_LINK_STATE_DISABLE:
4387 return MLX5_VPORT_ADMIN_STATE_DOWN;
4388 case IFLA_VF_LINK_STATE_ENABLE:
4389 return MLX5_VPORT_ADMIN_STATE_UP;
4391 return MLX5_VPORT_ADMIN_STATE_AUTO;
4394 static int mlx5e_set_vf_link_state(struct net_device *dev, int vf,
4397 struct mlx5e_priv *priv = netdev_priv(dev);
4398 struct mlx5_core_dev *mdev = priv->mdev;
4400 return mlx5_eswitch_set_vport_state(mdev->priv.eswitch, vf + 1,
4401 mlx5_ifla_link2vport(link_state));
4404 int mlx5e_get_vf_config(struct net_device *dev,
4405 int vf, struct ifla_vf_info *ivi)
4407 struct mlx5e_priv *priv = netdev_priv(dev);
4408 struct mlx5_core_dev *mdev = priv->mdev;
4411 err = mlx5_eswitch_get_vport_config(mdev->priv.eswitch, vf + 1, ivi);
4414 ivi->linkstate = mlx5_vport_link2ifla(ivi->linkstate);
4418 int mlx5e_get_vf_stats(struct net_device *dev,
4419 int vf, struct ifla_vf_stats *vf_stats)
4421 struct mlx5e_priv *priv = netdev_priv(dev);
4422 struct mlx5_core_dev *mdev = priv->mdev;
4424 return mlx5_eswitch_get_vport_stats(mdev->priv.eswitch, vf + 1,
4429 static bool mlx5e_tunnel_proto_supported_tx(struct mlx5_core_dev *mdev, u8 proto_type)
4431 switch (proto_type) {
4433 return MLX5_CAP_ETH(mdev, tunnel_stateless_gre);
4436 return (MLX5_CAP_ETH(mdev, tunnel_stateless_ip_over_ip) ||
4437 MLX5_CAP_ETH(mdev, tunnel_stateless_ip_over_ip_tx));
4443 static bool mlx5e_gre_tunnel_inner_proto_offload_supported(struct mlx5_core_dev *mdev,
4444 struct sk_buff *skb)
4446 switch (skb->inner_protocol) {
4447 case htons(ETH_P_IP):
4448 case htons(ETH_P_IPV6):
4449 case htons(ETH_P_TEB):
4451 case htons(ETH_P_MPLS_UC):
4452 case htons(ETH_P_MPLS_MC):
4453 return MLX5_CAP_ETH(mdev, tunnel_stateless_mpls_over_gre);
4458 static netdev_features_t mlx5e_tunnel_features_check(struct mlx5e_priv *priv,
4459 struct sk_buff *skb,
4460 netdev_features_t features)
4462 unsigned int offset = 0;
4463 struct udphdr *udph;
4467 switch (vlan_get_protocol(skb)) {
4468 case htons(ETH_P_IP):
4469 proto = ip_hdr(skb)->protocol;
4471 case htons(ETH_P_IPV6):
4472 proto = ipv6_find_hdr(skb, &offset, -1, NULL, NULL);
4480 if (mlx5e_gre_tunnel_inner_proto_offload_supported(priv->mdev, skb))
4485 if (mlx5e_tunnel_proto_supported_tx(priv->mdev, IPPROTO_IPIP))
4489 udph = udp_hdr(skb);
4490 port = be16_to_cpu(udph->dest);
4492 /* Verify if UDP port is being offloaded by HW */
4493 if (mlx5_vxlan_lookup_port(priv->mdev->vxlan, port))
4496 #if IS_ENABLED(CONFIG_GENEVE)
4497 /* Support Geneve offload for default UDP port */
4498 if (port == GENEVE_UDP_PORT && mlx5_geneve_tx_allowed(priv->mdev))
4504 /* Disable CSUM and GSO if the udp dport is not offloaded by HW */
4505 return features & ~(NETIF_F_CSUM_MASK | NETIF_F_GSO_MASK);
4508 netdev_features_t mlx5e_features_check(struct sk_buff *skb,
4509 struct net_device *netdev,
4510 netdev_features_t features)
4512 struct mlx5e_priv *priv = netdev_priv(netdev);
4514 features = vlan_features_check(skb, features);
4515 features = vxlan_features_check(skb, features);
4517 if (mlx5e_ipsec_feature_check(skb, netdev, features))
4520 /* Validate if the tunneled packet is being offloaded by HW */
4521 if (skb->encapsulation &&
4522 (features & NETIF_F_CSUM_MASK || features & NETIF_F_GSO_MASK))
4523 return mlx5e_tunnel_features_check(priv, skb, features);
4528 static void mlx5e_tx_timeout_work(struct work_struct *work)
4530 struct mlx5e_priv *priv = container_of(work, struct mlx5e_priv,
4532 struct net_device *netdev = priv->netdev;
4536 mutex_lock(&priv->state_lock);
4538 if (!test_bit(MLX5E_STATE_OPENED, &priv->state))
4541 for (i = 0; i < netdev->real_num_tx_queues; i++) {
4542 struct netdev_queue *dev_queue =
4543 netdev_get_tx_queue(netdev, i);
4544 struct mlx5e_txqsq *sq = priv->txq2sq[i];
4546 if (!netif_xmit_stopped(dev_queue))
4549 if (mlx5e_reporter_tx_timeout(sq))
4550 /* break if tried to reopened channels */
4555 mutex_unlock(&priv->state_lock);
4559 static void mlx5e_tx_timeout(struct net_device *dev, unsigned int txqueue)
4561 struct mlx5e_priv *priv = netdev_priv(dev);
4563 netdev_err(dev, "TX timeout detected\n");
4564 queue_work(priv->wq, &priv->tx_timeout_work);
4567 static int mlx5e_xdp_allowed(struct mlx5e_priv *priv, struct bpf_prog *prog)
4569 struct net_device *netdev = priv->netdev;
4570 struct mlx5e_channels new_channels = {};
4572 if (priv->channels.params.lro_en) {
4573 netdev_warn(netdev, "can't set XDP while LRO is on, disable LRO first\n");
4577 if (MLX5_IPSEC_DEV(priv->mdev)) {
4578 netdev_warn(netdev, "can't set XDP with IPSec offload\n");
4582 new_channels.params = priv->channels.params;
4583 new_channels.params.xdp_prog = prog;
4585 /* No XSK params: AF_XDP can't be enabled yet at the point of setting
4588 if (!mlx5e_rx_is_linear_skb(&new_channels.params, NULL)) {
4589 netdev_warn(netdev, "XDP is not allowed with MTU(%d) > %d\n",
4590 new_channels.params.sw_mtu,
4591 mlx5e_xdp_max_mtu(&new_channels.params, NULL));
4598 static void mlx5e_rq_replace_xdp_prog(struct mlx5e_rq *rq, struct bpf_prog *prog)
4600 struct bpf_prog *old_prog;
4602 old_prog = rcu_replace_pointer(rq->xdp_prog, prog,
4603 lockdep_is_held(&rq->priv->state_lock));
4605 bpf_prog_put(old_prog);
4608 static int mlx5e_xdp_set(struct net_device *netdev, struct bpf_prog *prog)
4610 struct mlx5e_priv *priv = netdev_priv(netdev);
4611 struct bpf_prog *old_prog;
4612 bool reset, was_opened;
4616 mutex_lock(&priv->state_lock);
4619 err = mlx5e_xdp_allowed(priv, prog);
4624 was_opened = test_bit(MLX5E_STATE_OPENED, &priv->state);
4625 /* no need for full reset when exchanging programs */
4626 reset = (!priv->channels.params.xdp_prog || !prog);
4628 if (was_opened && !reset)
4629 /* num_channels is invariant here, so we can take the
4630 * batched reference right upfront.
4632 bpf_prog_add(prog, priv->channels.num);
4634 if (was_opened && reset) {
4635 struct mlx5e_channels new_channels = {};
4637 new_channels.params = priv->channels.params;
4638 new_channels.params.xdp_prog = prog;
4639 mlx5e_set_rq_type(priv->mdev, &new_channels.params);
4640 old_prog = priv->channels.params.xdp_prog;
4642 err = mlx5e_safe_switch_channels(priv, &new_channels, NULL, NULL);
4646 /* exchange programs, extra prog reference we got from caller
4647 * as long as we don't fail from this point onwards.
4649 old_prog = xchg(&priv->channels.params.xdp_prog, prog);
4653 bpf_prog_put(old_prog);
4655 if (!was_opened && reset) /* change RQ type according to priv->xdp_prog */
4656 mlx5e_set_rq_type(priv->mdev, &priv->channels.params);
4658 if (!was_opened || reset)
4661 /* exchanging programs w/o reset, we update ref counts on behalf
4662 * of the channels RQs here.
4664 for (i = 0; i < priv->channels.num; i++) {
4665 struct mlx5e_channel *c = priv->channels.c[i];
4667 mlx5e_rq_replace_xdp_prog(&c->rq, prog);
4668 if (test_bit(MLX5E_CHANNEL_STATE_XSK, c->state))
4669 mlx5e_rq_replace_xdp_prog(&c->xskrq, prog);
4673 mutex_unlock(&priv->state_lock);
4677 static int mlx5e_xdp(struct net_device *dev, struct netdev_bpf *xdp)
4679 switch (xdp->command) {
4680 case XDP_SETUP_PROG:
4681 return mlx5e_xdp_set(dev, xdp->prog);
4682 case XDP_SETUP_XSK_POOL:
4683 return mlx5e_xsk_setup_pool(dev, xdp->xsk.pool,
4690 #ifdef CONFIG_MLX5_ESWITCH
4691 static int mlx5e_bridge_getlink(struct sk_buff *skb, u32 pid, u32 seq,
4692 struct net_device *dev, u32 filter_mask,
4695 struct mlx5e_priv *priv = netdev_priv(dev);
4696 struct mlx5_core_dev *mdev = priv->mdev;
4700 err = mlx5_eswitch_get_vepa(mdev->priv.eswitch, &setting);
4703 mode = setting ? BRIDGE_MODE_VEPA : BRIDGE_MODE_VEB;
4704 return ndo_dflt_bridge_getlink(skb, pid, seq, dev,
4706 0, 0, nlflags, filter_mask, NULL);
4709 static int mlx5e_bridge_setlink(struct net_device *dev, struct nlmsghdr *nlh,
4710 u16 flags, struct netlink_ext_ack *extack)
4712 struct mlx5e_priv *priv = netdev_priv(dev);
4713 struct mlx5_core_dev *mdev = priv->mdev;
4714 struct nlattr *attr, *br_spec;
4715 u16 mode = BRIDGE_MODE_UNDEF;
4719 br_spec = nlmsg_find_attr(nlh, sizeof(struct ifinfomsg), IFLA_AF_SPEC);
4723 nla_for_each_nested(attr, br_spec, rem) {
4724 if (nla_type(attr) != IFLA_BRIDGE_MODE)
4727 if (nla_len(attr) < sizeof(mode))
4730 mode = nla_get_u16(attr);
4731 if (mode > BRIDGE_MODE_VEPA)
4737 if (mode == BRIDGE_MODE_UNDEF)
4740 setting = (mode == BRIDGE_MODE_VEPA) ? 1 : 0;
4741 return mlx5_eswitch_set_vepa(mdev->priv.eswitch, setting);
4745 const struct net_device_ops mlx5e_netdev_ops = {
4746 .ndo_open = mlx5e_open,
4747 .ndo_stop = mlx5e_close,
4748 .ndo_start_xmit = mlx5e_xmit,
4749 .ndo_setup_tc = mlx5e_setup_tc,
4750 .ndo_select_queue = mlx5e_select_queue,
4751 .ndo_get_stats64 = mlx5e_get_stats,
4752 .ndo_set_rx_mode = mlx5e_set_rx_mode,
4753 .ndo_set_mac_address = mlx5e_set_mac,
4754 .ndo_vlan_rx_add_vid = mlx5e_vlan_rx_add_vid,
4755 .ndo_vlan_rx_kill_vid = mlx5e_vlan_rx_kill_vid,
4756 .ndo_set_features = mlx5e_set_features,
4757 .ndo_fix_features = mlx5e_fix_features,
4758 .ndo_change_mtu = mlx5e_change_nic_mtu,
4759 .ndo_do_ioctl = mlx5e_ioctl,
4760 .ndo_set_tx_maxrate = mlx5e_set_tx_maxrate,
4761 .ndo_features_check = mlx5e_features_check,
4762 .ndo_tx_timeout = mlx5e_tx_timeout,
4763 .ndo_bpf = mlx5e_xdp,
4764 .ndo_xdp_xmit = mlx5e_xdp_xmit,
4765 .ndo_xsk_wakeup = mlx5e_xsk_wakeup,
4766 #ifdef CONFIG_MLX5_EN_ARFS
4767 .ndo_rx_flow_steer = mlx5e_rx_flow_steer,
4769 #ifdef CONFIG_MLX5_ESWITCH
4770 .ndo_bridge_setlink = mlx5e_bridge_setlink,
4771 .ndo_bridge_getlink = mlx5e_bridge_getlink,
4773 /* SRIOV E-Switch NDOs */
4774 .ndo_set_vf_mac = mlx5e_set_vf_mac,
4775 .ndo_set_vf_vlan = mlx5e_set_vf_vlan,
4776 .ndo_set_vf_spoofchk = mlx5e_set_vf_spoofchk,
4777 .ndo_set_vf_trust = mlx5e_set_vf_trust,
4778 .ndo_set_vf_rate = mlx5e_set_vf_rate,
4779 .ndo_get_vf_config = mlx5e_get_vf_config,
4780 .ndo_set_vf_link_state = mlx5e_set_vf_link_state,
4781 .ndo_get_vf_stats = mlx5e_get_vf_stats,
4783 .ndo_get_devlink_port = mlx5e_get_devlink_port,
4786 void mlx5e_build_default_indir_rqt(u32 *indirection_rqt, int len,
4791 for (i = 0; i < len; i++)
4792 indirection_rqt[i] = i % num_channels;
4795 static bool slow_pci_heuristic(struct mlx5_core_dev *mdev)
4800 mlx5e_port_max_linkspeed(mdev, &link_speed);
4801 pci_bw = pcie_bandwidth_available(mdev->pdev, NULL, NULL, NULL);
4802 mlx5_core_dbg_once(mdev, "Max link speed = %d, PCI BW = %d\n",
4803 link_speed, pci_bw);
4805 #define MLX5E_SLOW_PCI_RATIO (2)
4807 return link_speed && pci_bw &&
4808 link_speed > MLX5E_SLOW_PCI_RATIO * pci_bw;
4811 static struct dim_cq_moder mlx5e_get_def_tx_moderation(u8 cq_period_mode)
4813 struct dim_cq_moder moder;
4815 moder.cq_period_mode = cq_period_mode;
4816 moder.pkts = MLX5E_PARAMS_DEFAULT_TX_CQ_MODERATION_PKTS;
4817 moder.usec = MLX5E_PARAMS_DEFAULT_TX_CQ_MODERATION_USEC;
4818 if (cq_period_mode == MLX5_CQ_PERIOD_MODE_START_FROM_CQE)
4819 moder.usec = MLX5E_PARAMS_DEFAULT_TX_CQ_MODERATION_USEC_FROM_CQE;
4824 static struct dim_cq_moder mlx5e_get_def_rx_moderation(u8 cq_period_mode)
4826 struct dim_cq_moder moder;
4828 moder.cq_period_mode = cq_period_mode;
4829 moder.pkts = MLX5E_PARAMS_DEFAULT_RX_CQ_MODERATION_PKTS;
4830 moder.usec = MLX5E_PARAMS_DEFAULT_RX_CQ_MODERATION_USEC;
4831 if (cq_period_mode == MLX5_CQ_PERIOD_MODE_START_FROM_CQE)
4832 moder.usec = MLX5E_PARAMS_DEFAULT_RX_CQ_MODERATION_USEC_FROM_CQE;
4837 static u8 mlx5_to_net_dim_cq_period_mode(u8 cq_period_mode)
4839 return cq_period_mode == MLX5_CQ_PERIOD_MODE_START_FROM_CQE ?
4840 DIM_CQ_PERIOD_MODE_START_FROM_CQE :
4841 DIM_CQ_PERIOD_MODE_START_FROM_EQE;
4844 void mlx5e_reset_tx_moderation(struct mlx5e_params *params, u8 cq_period_mode)
4846 if (params->tx_dim_enabled) {
4847 u8 dim_period_mode = mlx5_to_net_dim_cq_period_mode(cq_period_mode);
4849 params->tx_cq_moderation = net_dim_get_def_tx_moderation(dim_period_mode);
4851 params->tx_cq_moderation = mlx5e_get_def_tx_moderation(cq_period_mode);
4855 void mlx5e_reset_rx_moderation(struct mlx5e_params *params, u8 cq_period_mode)
4857 if (params->rx_dim_enabled) {
4858 u8 dim_period_mode = mlx5_to_net_dim_cq_period_mode(cq_period_mode);
4860 params->rx_cq_moderation = net_dim_get_def_rx_moderation(dim_period_mode);
4862 params->rx_cq_moderation = mlx5e_get_def_rx_moderation(cq_period_mode);
4866 void mlx5e_set_tx_cq_mode_params(struct mlx5e_params *params, u8 cq_period_mode)
4868 mlx5e_reset_tx_moderation(params, cq_period_mode);
4869 MLX5E_SET_PFLAG(params, MLX5E_PFLAG_TX_CQE_BASED_MODER,
4870 params->tx_cq_moderation.cq_period_mode ==
4871 MLX5_CQ_PERIOD_MODE_START_FROM_CQE);
4874 void mlx5e_set_rx_cq_mode_params(struct mlx5e_params *params, u8 cq_period_mode)
4876 mlx5e_reset_rx_moderation(params, cq_period_mode);
4877 MLX5E_SET_PFLAG(params, MLX5E_PFLAG_RX_CQE_BASED_MODER,
4878 params->rx_cq_moderation.cq_period_mode ==
4879 MLX5_CQ_PERIOD_MODE_START_FROM_CQE);
4882 static u32 mlx5e_choose_lro_timeout(struct mlx5_core_dev *mdev, u32 wanted_timeout)
4886 /* The supported periods are organized in ascending order */
4887 for (i = 0; i < MLX5E_LRO_TIMEOUT_ARR_SIZE - 1; i++)
4888 if (MLX5_CAP_ETH(mdev, lro_timer_supported_periods[i]) >= wanted_timeout)
4891 return MLX5_CAP_ETH(mdev, lro_timer_supported_periods[i]);
4894 void mlx5e_build_rq_params(struct mlx5_core_dev *mdev,
4895 struct mlx5e_params *params)
4897 /* Prefer Striding RQ, unless any of the following holds:
4898 * - Striding RQ configuration is not possible/supported.
4899 * - Slow PCI heuristic.
4900 * - Legacy RQ would use linear SKB while Striding RQ would use non-linear.
4902 * No XSK params: checking the availability of striding RQ in general.
4904 if (!slow_pci_heuristic(mdev) &&
4905 mlx5e_striding_rq_possible(mdev, params) &&
4906 (mlx5e_rx_mpwqe_is_linear_skb(mdev, params, NULL) ||
4907 !mlx5e_rx_is_linear_skb(params, NULL)))
4908 MLX5E_SET_PFLAG(params, MLX5E_PFLAG_RX_STRIDING_RQ, true);
4909 mlx5e_set_rq_type(mdev, params);
4910 mlx5e_init_rq_type_params(mdev, params);
4913 void mlx5e_build_rss_params(struct mlx5e_rss_params *rss_params,
4916 enum mlx5e_traffic_types tt;
4918 rss_params->hfunc = ETH_RSS_HASH_TOP;
4919 netdev_rss_key_fill(rss_params->toeplitz_hash_key,
4920 sizeof(rss_params->toeplitz_hash_key));
4921 mlx5e_build_default_indir_rqt(rss_params->indirection_rqt,
4922 MLX5E_INDIR_RQT_SIZE, num_channels);
4923 for (tt = 0; tt < MLX5E_NUM_INDIR_TIRS; tt++)
4924 rss_params->rx_hash_fields[tt] =
4925 tirc_default_config[tt].rx_hash_fields;
4928 void mlx5e_build_nic_params(struct mlx5e_priv *priv, struct mlx5e_xsk *xsk, u16 mtu)
4930 struct mlx5e_rss_params *rss_params = &priv->rss_params;
4931 struct mlx5e_params *params = &priv->channels.params;
4932 struct mlx5_core_dev *mdev = priv->mdev;
4933 u8 rx_cq_period_mode;
4935 priv->max_nch = mlx5e_calc_max_nch(priv, priv->profile);
4937 params->sw_mtu = mtu;
4938 params->hard_mtu = MLX5E_ETH_HARD_MTU;
4939 params->num_channels = min_t(unsigned int, MLX5E_MAX_NUM_CHANNELS / 2,
4944 params->log_sq_size = is_kdump_kernel() ?
4945 MLX5E_PARAMS_MINIMUM_LOG_SQ_SIZE :
4946 MLX5E_PARAMS_DEFAULT_LOG_SQ_SIZE;
4947 MLX5E_SET_PFLAG(params, MLX5E_PFLAG_SKB_TX_MPWQE,
4948 MLX5_CAP_ETH(mdev, enhanced_multi_pkt_send_wqe));
4951 MLX5E_SET_PFLAG(params, MLX5E_PFLAG_XDP_TX_MPWQE,
4952 MLX5_CAP_ETH(mdev, enhanced_multi_pkt_send_wqe));
4954 /* set CQE compression */
4955 params->rx_cqe_compress_def = false;
4956 if (MLX5_CAP_GEN(mdev, cqe_compression) &&
4957 MLX5_CAP_GEN(mdev, vport_group_manager))
4958 params->rx_cqe_compress_def = slow_pci_heuristic(mdev);
4960 MLX5E_SET_PFLAG(params, MLX5E_PFLAG_RX_CQE_COMPRESS, params->rx_cqe_compress_def);
4961 MLX5E_SET_PFLAG(params, MLX5E_PFLAG_RX_NO_CSUM_COMPLETE, false);
4964 mlx5e_build_rq_params(mdev, params);
4967 if (MLX5_CAP_ETH(mdev, lro_cap) &&
4968 params->rq_wq_type == MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ) {
4969 /* No XSK params: checking the availability of striding RQ in general. */
4970 if (!mlx5e_rx_mpwqe_is_linear_skb(mdev, params, NULL))
4971 params->lro_en = !slow_pci_heuristic(mdev);
4973 params->lro_timeout = mlx5e_choose_lro_timeout(mdev, MLX5E_DEFAULT_LRO_TIMEOUT);
4975 /* CQ moderation params */
4976 rx_cq_period_mode = MLX5_CAP_GEN(mdev, cq_period_start_from_cqe) ?
4977 MLX5_CQ_PERIOD_MODE_START_FROM_CQE :
4978 MLX5_CQ_PERIOD_MODE_START_FROM_EQE;
4979 params->rx_dim_enabled = MLX5_CAP_GEN(mdev, cq_moderation);
4980 params->tx_dim_enabled = MLX5_CAP_GEN(mdev, cq_moderation);
4981 mlx5e_set_rx_cq_mode_params(params, rx_cq_period_mode);
4982 mlx5e_set_tx_cq_mode_params(params, MLX5_CQ_PERIOD_MODE_START_FROM_EQE);
4985 mlx5_query_min_inline(mdev, ¶ms->tx_min_inline_mode);
4988 mlx5e_build_rss_params(rss_params, params->num_channels);
4989 params->tunneled_offload_en =
4990 mlx5e_tunnel_inner_ft_supported(mdev);
4995 /* Do not update netdev->features directly in here
4996 * on mlx5e_attach_netdev() we will call mlx5e_update_features()
4997 * To update netdev->features please modify mlx5e_fix_features()
5001 static void mlx5e_set_netdev_dev_addr(struct net_device *netdev)
5003 struct mlx5e_priv *priv = netdev_priv(netdev);
5005 mlx5_query_mac_address(priv->mdev, netdev->dev_addr);
5006 if (is_zero_ether_addr(netdev->dev_addr) &&
5007 !MLX5_CAP_GEN(priv->mdev, vport_group_manager)) {
5008 eth_hw_addr_random(netdev);
5009 mlx5_core_info(priv->mdev, "Assigned random MAC address %pM\n", netdev->dev_addr);
5013 static int mlx5e_vxlan_set_port(struct net_device *netdev, unsigned int table,
5014 unsigned int entry, struct udp_tunnel_info *ti)
5016 struct mlx5e_priv *priv = netdev_priv(netdev);
5018 return mlx5_vxlan_add_port(priv->mdev->vxlan, ntohs(ti->port));
5021 static int mlx5e_vxlan_unset_port(struct net_device *netdev, unsigned int table,
5022 unsigned int entry, struct udp_tunnel_info *ti)
5024 struct mlx5e_priv *priv = netdev_priv(netdev);
5026 return mlx5_vxlan_del_port(priv->mdev->vxlan, ntohs(ti->port));
5029 void mlx5e_vxlan_set_netdev_info(struct mlx5e_priv *priv)
5031 if (!mlx5_vxlan_allowed(priv->mdev->vxlan))
5034 priv->nic_info.set_port = mlx5e_vxlan_set_port;
5035 priv->nic_info.unset_port = mlx5e_vxlan_unset_port;
5036 priv->nic_info.flags = UDP_TUNNEL_NIC_INFO_MAY_SLEEP |
5037 UDP_TUNNEL_NIC_INFO_STATIC_IANA_VXLAN;
5038 priv->nic_info.tables[0].tunnel_types = UDP_TUNNEL_TYPE_VXLAN;
5039 /* Don't count the space hard-coded to the IANA port */
5040 priv->nic_info.tables[0].n_entries =
5041 mlx5_vxlan_max_udp_ports(priv->mdev) - 1;
5043 priv->netdev->udp_tunnel_nic_info = &priv->nic_info;
5046 static bool mlx5e_tunnel_any_tx_proto_supported(struct mlx5_core_dev *mdev)
5050 for (tt = 0; tt < MLX5E_NUM_TUNNEL_TT; tt++) {
5051 if (mlx5e_tunnel_proto_supported_tx(mdev, mlx5e_get_proto_by_tunnel_type(tt)))
5054 return (mlx5_vxlan_allowed(mdev->vxlan) || mlx5_geneve_tx_allowed(mdev));
5057 static void mlx5e_build_nic_netdev(struct net_device *netdev)
5059 struct mlx5e_priv *priv = netdev_priv(netdev);
5060 struct mlx5_core_dev *mdev = priv->mdev;
5064 SET_NETDEV_DEV(netdev, mdev->device);
5066 netdev->netdev_ops = &mlx5e_netdev_ops;
5068 mlx5e_dcbnl_build_netdev(netdev);
5070 netdev->watchdog_timeo = 15 * HZ;
5072 netdev->ethtool_ops = &mlx5e_ethtool_ops;
5074 netdev->vlan_features |= NETIF_F_SG;
5075 netdev->vlan_features |= NETIF_F_HW_CSUM;
5076 netdev->vlan_features |= NETIF_F_GRO;
5077 netdev->vlan_features |= NETIF_F_TSO;
5078 netdev->vlan_features |= NETIF_F_TSO6;
5079 netdev->vlan_features |= NETIF_F_RXCSUM;
5080 netdev->vlan_features |= NETIF_F_RXHASH;
5082 netdev->mpls_features |= NETIF_F_SG;
5083 netdev->mpls_features |= NETIF_F_HW_CSUM;
5084 netdev->mpls_features |= NETIF_F_TSO;
5085 netdev->mpls_features |= NETIF_F_TSO6;
5087 netdev->hw_enc_features |= NETIF_F_HW_VLAN_CTAG_TX;
5088 netdev->hw_enc_features |= NETIF_F_HW_VLAN_CTAG_RX;
5090 if (!!MLX5_CAP_ETH(mdev, lro_cap) &&
5091 mlx5e_check_fragmented_striding_rq_cap(mdev))
5092 netdev->vlan_features |= NETIF_F_LRO;
5094 netdev->hw_features = netdev->vlan_features;
5095 netdev->hw_features |= NETIF_F_HW_VLAN_CTAG_TX;
5096 netdev->hw_features |= NETIF_F_HW_VLAN_CTAG_RX;
5097 netdev->hw_features |= NETIF_F_HW_VLAN_CTAG_FILTER;
5098 netdev->hw_features |= NETIF_F_HW_VLAN_STAG_TX;
5100 if (mlx5e_tunnel_any_tx_proto_supported(mdev)) {
5101 netdev->hw_enc_features |= NETIF_F_HW_CSUM;
5102 netdev->hw_enc_features |= NETIF_F_TSO;
5103 netdev->hw_enc_features |= NETIF_F_TSO6;
5104 netdev->hw_enc_features |= NETIF_F_GSO_PARTIAL;
5107 if (mlx5_vxlan_allowed(mdev->vxlan) || mlx5_geneve_tx_allowed(mdev)) {
5108 netdev->hw_features |= NETIF_F_GSO_UDP_TUNNEL |
5109 NETIF_F_GSO_UDP_TUNNEL_CSUM;
5110 netdev->hw_enc_features |= NETIF_F_GSO_UDP_TUNNEL |
5111 NETIF_F_GSO_UDP_TUNNEL_CSUM;
5112 netdev->gso_partial_features = NETIF_F_GSO_UDP_TUNNEL_CSUM;
5113 netdev->vlan_features |= NETIF_F_GSO_UDP_TUNNEL |
5114 NETIF_F_GSO_UDP_TUNNEL_CSUM;
5117 if (mlx5e_tunnel_proto_supported_tx(mdev, IPPROTO_GRE)) {
5118 netdev->hw_features |= NETIF_F_GSO_GRE |
5119 NETIF_F_GSO_GRE_CSUM;
5120 netdev->hw_enc_features |= NETIF_F_GSO_GRE |
5121 NETIF_F_GSO_GRE_CSUM;
5122 netdev->gso_partial_features |= NETIF_F_GSO_GRE |
5123 NETIF_F_GSO_GRE_CSUM;
5126 if (mlx5e_tunnel_proto_supported_tx(mdev, IPPROTO_IPIP)) {
5127 netdev->hw_features |= NETIF_F_GSO_IPXIP4 |
5129 netdev->hw_enc_features |= NETIF_F_GSO_IPXIP4 |
5131 netdev->gso_partial_features |= NETIF_F_GSO_IPXIP4 |
5135 netdev->hw_features |= NETIF_F_GSO_PARTIAL;
5136 netdev->gso_partial_features |= NETIF_F_GSO_UDP_L4;
5137 netdev->hw_features |= NETIF_F_GSO_UDP_L4;
5138 netdev->features |= NETIF_F_GSO_UDP_L4;
5140 mlx5_query_port_fcs(mdev, &fcs_supported, &fcs_enabled);
5143 netdev->hw_features |= NETIF_F_RXALL;
5145 if (MLX5_CAP_ETH(mdev, scatter_fcs))
5146 netdev->hw_features |= NETIF_F_RXFCS;
5148 netdev->features = netdev->hw_features;
5152 netdev->features &= ~NETIF_F_RXALL;
5153 netdev->features &= ~NETIF_F_LRO;
5154 netdev->features &= ~NETIF_F_RXFCS;
5156 #define FT_CAP(f) MLX5_CAP_FLOWTABLE(mdev, flow_table_properties_nic_receive.f)
5157 if (FT_CAP(flow_modify_en) &&
5158 FT_CAP(modify_root) &&
5159 FT_CAP(identified_miss_table_mode) &&
5160 FT_CAP(flow_table_modify)) {
5161 #if IS_ENABLED(CONFIG_MLX5_CLS_ACT)
5162 netdev->hw_features |= NETIF_F_HW_TC;
5164 #ifdef CONFIG_MLX5_EN_ARFS
5165 netdev->hw_features |= NETIF_F_NTUPLE;
5168 if (mlx5_qos_is_supported(mdev))
5169 netdev->features |= NETIF_F_HW_TC;
5171 netdev->features |= NETIF_F_HIGHDMA;
5172 netdev->features |= NETIF_F_HW_VLAN_STAG_FILTER;
5174 netdev->priv_flags |= IFF_UNICAST_FLT;
5176 mlx5e_set_netdev_dev_addr(netdev);
5177 mlx5e_ipsec_build_netdev(priv);
5178 mlx5e_tls_build_netdev(priv);
5181 void mlx5e_create_q_counters(struct mlx5e_priv *priv)
5183 u32 out[MLX5_ST_SZ_DW(alloc_q_counter_out)] = {};
5184 u32 in[MLX5_ST_SZ_DW(alloc_q_counter_in)] = {};
5185 struct mlx5_core_dev *mdev = priv->mdev;
5188 MLX5_SET(alloc_q_counter_in, in, opcode, MLX5_CMD_OP_ALLOC_Q_COUNTER);
5189 err = mlx5_cmd_exec_inout(mdev, alloc_q_counter, in, out);
5192 MLX5_GET(alloc_q_counter_out, out, counter_set_id);
5194 err = mlx5_cmd_exec_inout(mdev, alloc_q_counter, in, out);
5196 priv->drop_rq_q_counter =
5197 MLX5_GET(alloc_q_counter_out, out, counter_set_id);
5200 void mlx5e_destroy_q_counters(struct mlx5e_priv *priv)
5202 u32 in[MLX5_ST_SZ_DW(dealloc_q_counter_in)] = {};
5204 MLX5_SET(dealloc_q_counter_in, in, opcode,
5205 MLX5_CMD_OP_DEALLOC_Q_COUNTER);
5206 if (priv->q_counter) {
5207 MLX5_SET(dealloc_q_counter_in, in, counter_set_id,
5209 mlx5_cmd_exec_in(priv->mdev, dealloc_q_counter, in);
5212 if (priv->drop_rq_q_counter) {
5213 MLX5_SET(dealloc_q_counter_in, in, counter_set_id,
5214 priv->drop_rq_q_counter);
5215 mlx5_cmd_exec_in(priv->mdev, dealloc_q_counter, in);
5219 static int mlx5e_nic_init(struct mlx5_core_dev *mdev,
5220 struct net_device *netdev)
5222 struct mlx5e_priv *priv = netdev_priv(netdev);
5225 mlx5e_build_nic_params(priv, &priv->xsk, netdev->mtu);
5226 mlx5e_vxlan_set_netdev_info(priv);
5228 mlx5e_timestamp_init(priv);
5230 err = mlx5e_ipsec_init(priv);
5232 mlx5_core_err(mdev, "IPSec initialization failed, %d\n", err);
5234 err = mlx5e_tls_init(priv);
5236 mlx5_core_err(mdev, "TLS initialization failed, %d\n", err);
5238 err = mlx5e_devlink_port_register(priv);
5240 mlx5_core_err(mdev, "mlx5e_devlink_port_register failed, %d\n", err);
5242 mlx5e_health_create_reporters(priv);
5247 static void mlx5e_nic_cleanup(struct mlx5e_priv *priv)
5249 mlx5e_health_destroy_reporters(priv);
5250 mlx5e_devlink_port_unregister(priv);
5251 mlx5e_tls_cleanup(priv);
5252 mlx5e_ipsec_cleanup(priv);
5255 static int mlx5e_init_nic_rx(struct mlx5e_priv *priv)
5257 struct mlx5_core_dev *mdev = priv->mdev;
5260 mlx5e_create_q_counters(priv);
5262 err = mlx5e_open_drop_rq(priv, &priv->drop_rq);
5264 mlx5_core_err(mdev, "open drop rq failed, %d\n", err);
5265 goto err_destroy_q_counters;
5268 err = mlx5e_create_indirect_rqt(priv);
5270 goto err_close_drop_rq;
5272 err = mlx5e_create_direct_rqts(priv, priv->direct_tir);
5274 goto err_destroy_indirect_rqts;
5276 err = mlx5e_create_indirect_tirs(priv, true);
5278 goto err_destroy_direct_rqts;
5280 err = mlx5e_create_direct_tirs(priv, priv->direct_tir);
5282 goto err_destroy_indirect_tirs;
5284 err = mlx5e_create_direct_rqts(priv, priv->xsk_tir);
5286 goto err_destroy_direct_tirs;
5288 err = mlx5e_create_direct_tirs(priv, priv->xsk_tir);
5290 goto err_destroy_xsk_rqts;
5292 err = mlx5e_create_flow_steering(priv);
5294 mlx5_core_warn(mdev, "create flow steering failed, %d\n", err);
5295 goto err_destroy_xsk_tirs;
5298 err = mlx5e_tc_nic_init(priv);
5300 goto err_destroy_flow_steering;
5302 err = mlx5e_accel_init_rx(priv);
5304 goto err_tc_nic_cleanup;
5306 #ifdef CONFIG_MLX5_EN_ARFS
5307 priv->netdev->rx_cpu_rmap = mlx5_eq_table_get_rmap(priv->mdev);
5313 mlx5e_tc_nic_cleanup(priv);
5314 err_destroy_flow_steering:
5315 mlx5e_destroy_flow_steering(priv);
5316 err_destroy_xsk_tirs:
5317 mlx5e_destroy_direct_tirs(priv, priv->xsk_tir);
5318 err_destroy_xsk_rqts:
5319 mlx5e_destroy_direct_rqts(priv, priv->xsk_tir);
5320 err_destroy_direct_tirs:
5321 mlx5e_destroy_direct_tirs(priv, priv->direct_tir);
5322 err_destroy_indirect_tirs:
5323 mlx5e_destroy_indirect_tirs(priv);
5324 err_destroy_direct_rqts:
5325 mlx5e_destroy_direct_rqts(priv, priv->direct_tir);
5326 err_destroy_indirect_rqts:
5327 mlx5e_destroy_rqt(priv, &priv->indir_rqt);
5329 mlx5e_close_drop_rq(&priv->drop_rq);
5330 err_destroy_q_counters:
5331 mlx5e_destroy_q_counters(priv);
5335 static void mlx5e_cleanup_nic_rx(struct mlx5e_priv *priv)
5337 mlx5e_accel_cleanup_rx(priv);
5338 mlx5e_tc_nic_cleanup(priv);
5339 mlx5e_destroy_flow_steering(priv);
5340 mlx5e_destroy_direct_tirs(priv, priv->xsk_tir);
5341 mlx5e_destroy_direct_rqts(priv, priv->xsk_tir);
5342 mlx5e_destroy_direct_tirs(priv, priv->direct_tir);
5343 mlx5e_destroy_indirect_tirs(priv);
5344 mlx5e_destroy_direct_rqts(priv, priv->direct_tir);
5345 mlx5e_destroy_rqt(priv, &priv->indir_rqt);
5346 mlx5e_close_drop_rq(&priv->drop_rq);
5347 mlx5e_destroy_q_counters(priv);
5350 static int mlx5e_init_nic_tx(struct mlx5e_priv *priv)
5354 err = mlx5e_create_tises(priv);
5356 mlx5_core_warn(priv->mdev, "create tises failed, %d\n", err);
5360 mlx5e_dcbnl_initialize(priv);
5364 static void mlx5e_nic_enable(struct mlx5e_priv *priv)
5366 struct net_device *netdev = priv->netdev;
5367 struct mlx5_core_dev *mdev = priv->mdev;
5369 mlx5e_init_l2_addr(priv);
5371 /* Marking the link as currently not needed by the Driver */
5372 if (!netif_running(netdev))
5373 mlx5e_modify_admin_state(mdev, MLX5_PORT_DOWN);
5375 mlx5e_set_netdev_mtu_boundaries(priv);
5376 mlx5e_set_dev_port_mtu(priv);
5378 mlx5_lag_add(mdev, netdev);
5380 mlx5e_enable_async_events(priv);
5381 mlx5e_enable_blocking_events(priv);
5382 if (mlx5e_monitor_counter_supported(priv))
5383 mlx5e_monitor_counter_init(priv);
5385 mlx5e_hv_vhca_stats_create(priv);
5386 if (netdev->reg_state != NETREG_REGISTERED)
5388 mlx5e_dcbnl_init_app(priv);
5390 queue_work(priv->wq, &priv->set_rx_mode_work);
5393 if (netif_running(netdev))
5395 udp_tunnel_nic_reset_ntf(priv->netdev);
5396 netif_device_attach(netdev);
5400 static void mlx5e_nic_disable(struct mlx5e_priv *priv)
5402 struct mlx5_core_dev *mdev = priv->mdev;
5404 if (priv->netdev->reg_state == NETREG_REGISTERED)
5405 mlx5e_dcbnl_delete_app(priv);
5408 if (netif_running(priv->netdev))
5409 mlx5e_close(priv->netdev);
5410 netif_device_detach(priv->netdev);
5413 queue_work(priv->wq, &priv->set_rx_mode_work);
5415 mlx5e_hv_vhca_stats_destroy(priv);
5416 if (mlx5e_monitor_counter_supported(priv))
5417 mlx5e_monitor_counter_cleanup(priv);
5419 mlx5e_disable_blocking_events(priv);
5420 if (priv->en_trap) {
5421 mlx5e_deactivate_trap(priv);
5422 mlx5e_close_trap(priv->en_trap);
5423 priv->en_trap = NULL;
5425 mlx5e_disable_async_events(priv);
5426 mlx5_lag_remove(mdev);
5427 mlx5_vxlan_reset_to_default(mdev->vxlan);
5430 int mlx5e_update_nic_rx(struct mlx5e_priv *priv)
5432 return mlx5e_refresh_tirs(priv, false, false);
5435 static const struct mlx5e_profile mlx5e_nic_profile = {
5436 .init = mlx5e_nic_init,
5437 .cleanup = mlx5e_nic_cleanup,
5438 .init_rx = mlx5e_init_nic_rx,
5439 .cleanup_rx = mlx5e_cleanup_nic_rx,
5440 .init_tx = mlx5e_init_nic_tx,
5441 .cleanup_tx = mlx5e_cleanup_nic_tx,
5442 .enable = mlx5e_nic_enable,
5443 .disable = mlx5e_nic_disable,
5444 .update_rx = mlx5e_update_nic_rx,
5445 .update_stats = mlx5e_stats_update_ndo_stats,
5446 .update_carrier = mlx5e_update_carrier,
5447 .rx_handlers = &mlx5e_rx_handlers_nic,
5448 .max_tc = MLX5E_MAX_NUM_TC,
5449 .rq_groups = MLX5E_NUM_RQ_GROUPS(XSK),
5450 .stats_grps = mlx5e_nic_stats_grps,
5451 .stats_grps_num = mlx5e_nic_stats_grps_num,
5454 /* mlx5e generic netdev management API (move to en_common.c) */
5455 int mlx5e_priv_init(struct mlx5e_priv *priv,
5456 struct net_device *netdev,
5457 struct mlx5_core_dev *mdev)
5459 memset(priv, 0, sizeof(*priv));
5463 priv->netdev = netdev;
5464 priv->msglevel = MLX5E_MSG_LEVEL;
5465 priv->max_opened_tc = 1;
5467 if (!alloc_cpumask_var(&priv->scratchpad.cpumask, GFP_KERNEL))
5470 mutex_init(&priv->state_lock);
5471 hash_init(priv->htb.qos_tc2node);
5472 INIT_WORK(&priv->update_carrier_work, mlx5e_update_carrier_work);
5473 INIT_WORK(&priv->set_rx_mode_work, mlx5e_set_rx_mode_work);
5474 INIT_WORK(&priv->tx_timeout_work, mlx5e_tx_timeout_work);
5475 INIT_WORK(&priv->update_stats_work, mlx5e_update_stats_work);
5477 priv->wq = create_singlethread_workqueue("mlx5e");
5479 goto err_free_cpumask;
5484 free_cpumask_var(priv->scratchpad.cpumask);
5489 void mlx5e_priv_cleanup(struct mlx5e_priv *priv)
5493 destroy_workqueue(priv->wq);
5494 free_cpumask_var(priv->scratchpad.cpumask);
5496 for (i = 0; i < priv->htb.max_qos_sqs; i++)
5497 kfree(priv->htb.qos_sq_stats[i]);
5498 kvfree(priv->htb.qos_sq_stats);
5502 mlx5e_create_netdev(struct mlx5_core_dev *mdev, unsigned int txqs, unsigned int rxqs)
5504 struct net_device *netdev;
5507 netdev = alloc_etherdev_mqs(sizeof(struct mlx5e_priv), txqs, rxqs);
5509 mlx5_core_err(mdev, "alloc_etherdev_mqs() failed\n");
5513 err = mlx5e_priv_init(netdev_priv(netdev), netdev, mdev);
5515 mlx5_core_err(mdev, "mlx5e_priv_init failed, err=%d\n", err);
5516 goto err_free_netdev;
5519 netif_carrier_off(netdev);
5520 dev_net_set(netdev, mlx5_core_net(mdev));
5525 free_netdev(netdev);
5530 static void mlx5e_update_features(struct net_device *netdev)
5532 if (netdev->reg_state != NETREG_REGISTERED)
5533 return; /* features will be updated on netdev registration */
5536 netdev_update_features(netdev);
5540 int mlx5e_attach_netdev(struct mlx5e_priv *priv)
5542 const bool take_rtnl = priv->netdev->reg_state == NETREG_REGISTERED;
5543 const struct mlx5e_profile *profile = priv->profile;
5547 clear_bit(MLX5E_STATE_DESTROYING, &priv->state);
5549 /* max number of channels may have changed */
5550 max_nch = mlx5e_get_max_num_channels(priv->mdev);
5551 if (priv->channels.params.num_channels > max_nch) {
5552 mlx5_core_warn(priv->mdev, "MLX5E: Reducing number of channels to %d\n", max_nch);
5553 /* Reducing the number of channels - RXFH has to be reset, and
5554 * mlx5e_num_channels_changed below will build the RQT.
5556 priv->netdev->priv_flags &= ~IFF_RXFH_CONFIGURED;
5557 priv->channels.params.num_channels = max_nch;
5559 /* 1. Set the real number of queues in the kernel the first time.
5560 * 2. Set our default XPS cpumask.
5563 * rtnl_lock is required by netif_set_real_num_*_queues in case the
5564 * netdev has been registered by this point (if this function was called
5565 * in the reload or resume flow).
5569 err = mlx5e_num_channels_changed(priv);
5575 err = profile->init_tx(priv);
5579 err = profile->init_rx(priv);
5581 goto err_cleanup_tx;
5583 if (profile->enable)
5584 profile->enable(priv);
5586 mlx5e_update_features(priv->netdev);
5591 profile->cleanup_tx(priv);
5594 set_bit(MLX5E_STATE_DESTROYING, &priv->state);
5595 cancel_work_sync(&priv->update_stats_work);
5599 void mlx5e_detach_netdev(struct mlx5e_priv *priv)
5601 const struct mlx5e_profile *profile = priv->profile;
5603 set_bit(MLX5E_STATE_DESTROYING, &priv->state);
5605 if (profile->disable)
5606 profile->disable(priv);
5607 flush_workqueue(priv->wq);
5609 profile->cleanup_rx(priv);
5610 profile->cleanup_tx(priv);
5611 cancel_work_sync(&priv->update_stats_work);
5615 mlx5e_netdev_attach_profile(struct mlx5e_priv *priv,
5616 const struct mlx5e_profile *new_profile, void *new_ppriv)
5618 struct net_device *netdev = priv->netdev;
5619 struct mlx5_core_dev *mdev = priv->mdev;
5622 err = mlx5e_priv_init(priv, netdev, mdev);
5624 mlx5_core_err(mdev, "mlx5e_priv_init failed, err=%d\n", err);
5627 netif_carrier_off(netdev);
5628 priv->profile = new_profile;
5629 priv->ppriv = new_ppriv;
5630 err = new_profile->init(priv->mdev, priv->netdev);
5633 err = mlx5e_attach_netdev(priv);
5635 new_profile->cleanup(priv);
5639 int mlx5e_netdev_change_profile(struct mlx5e_priv *priv,
5640 const struct mlx5e_profile *new_profile, void *new_ppriv)
5642 unsigned int new_max_nch = mlx5e_calc_max_nch(priv, new_profile);
5643 const struct mlx5e_profile *orig_profile = priv->profile;
5644 void *orig_ppriv = priv->ppriv;
5645 int err, rollback_err;
5648 if (new_max_nch != priv->max_nch) {
5649 netdev_warn(priv->netdev,
5650 "%s: Replacing profile with different max channles\n",
5655 /* cleanup old profile */
5656 mlx5e_detach_netdev(priv);
5657 priv->profile->cleanup(priv);
5658 mlx5e_priv_cleanup(priv);
5660 err = mlx5e_netdev_attach_profile(priv, new_profile, new_ppriv);
5661 if (err) { /* roll back to original profile */
5662 netdev_warn(priv->netdev, "%s: new profile init failed, %d\n",
5670 rollback_err = mlx5e_netdev_attach_profile(priv, orig_profile, orig_ppriv);
5672 netdev_err(priv->netdev,
5673 "%s: failed to rollback to orig profile, %d\n",
5674 __func__, rollback_err);
5679 void mlx5e_destroy_netdev(struct mlx5e_priv *priv)
5681 struct net_device *netdev = priv->netdev;
5683 mlx5e_priv_cleanup(priv);
5684 free_netdev(netdev);
5687 static int mlx5e_resume(struct auxiliary_device *adev)
5689 struct mlx5_adev *edev = container_of(adev, struct mlx5_adev, adev);
5690 struct mlx5e_priv *priv = dev_get_drvdata(&adev->dev);
5691 struct net_device *netdev = priv->netdev;
5692 struct mlx5_core_dev *mdev = edev->mdev;
5695 if (netif_device_present(netdev))
5698 err = mlx5e_create_mdev_resources(mdev);
5702 err = mlx5e_attach_netdev(priv);
5704 mlx5e_destroy_mdev_resources(mdev);
5711 static int mlx5e_suspend(struct auxiliary_device *adev, pm_message_t state)
5713 struct mlx5e_priv *priv = dev_get_drvdata(&adev->dev);
5714 struct net_device *netdev = priv->netdev;
5715 struct mlx5_core_dev *mdev = priv->mdev;
5717 if (!netif_device_present(netdev))
5720 mlx5e_detach_netdev(priv);
5721 mlx5e_destroy_mdev_resources(mdev);
5725 static int mlx5e_probe(struct auxiliary_device *adev,
5726 const struct auxiliary_device_id *id)
5728 struct mlx5_adev *edev = container_of(adev, struct mlx5_adev, adev);
5729 const struct mlx5e_profile *profile = &mlx5e_nic_profile;
5730 struct mlx5_core_dev *mdev = edev->mdev;
5731 struct net_device *netdev;
5732 pm_message_t state = {};
5733 unsigned int txqs, rxqs, ptp_txqs = 0;
5734 struct mlx5e_priv *priv;
5739 if (MLX5_CAP_GEN(mdev, ts_cqe_to_dest_cqn))
5740 ptp_txqs = profile->max_tc;
5742 if (mlx5_qos_is_supported(mdev))
5743 qos_sqs = mlx5e_qos_max_leaf_nodes(mdev);
5745 nch = mlx5e_get_max_num_channels(mdev);
5746 txqs = nch * profile->max_tc + ptp_txqs + qos_sqs;
5747 rxqs = nch * profile->rq_groups;
5748 netdev = mlx5e_create_netdev(mdev, txqs, rxqs);
5750 mlx5_core_err(mdev, "mlx5e_create_netdev failed\n");
5754 mlx5e_build_nic_netdev(netdev);
5756 priv = netdev_priv(netdev);
5757 dev_set_drvdata(&adev->dev, priv);
5759 priv->profile = profile;
5761 err = profile->init(mdev, netdev);
5763 mlx5_core_err(mdev, "mlx5e_nic_profile init failed, %d\n", err);
5764 goto err_destroy_netdev;
5767 err = mlx5e_resume(adev);
5769 mlx5_core_err(mdev, "mlx5e_resume failed, %d\n", err);
5770 goto err_profile_cleanup;
5773 err = register_netdev(netdev);
5775 mlx5_core_err(mdev, "register_netdev failed, %d\n", err);
5779 mlx5e_devlink_port_type_eth_set(priv);
5781 mlx5e_dcbnl_init_app(priv);
5785 mlx5e_suspend(adev, state);
5786 err_profile_cleanup:
5787 profile->cleanup(priv);
5789 mlx5e_destroy_netdev(priv);
5793 static void mlx5e_remove(struct auxiliary_device *adev)
5795 struct mlx5e_priv *priv = dev_get_drvdata(&adev->dev);
5796 pm_message_t state = {};
5798 mlx5e_dcbnl_delete_app(priv);
5799 unregister_netdev(priv->netdev);
5800 mlx5e_suspend(adev, state);
5801 priv->profile->cleanup(priv);
5802 mlx5e_destroy_netdev(priv);
5805 static const struct auxiliary_device_id mlx5e_id_table[] = {
5806 { .name = MLX5_ADEV_NAME ".eth", },
5810 MODULE_DEVICE_TABLE(auxiliary, mlx5e_id_table);
5812 static struct auxiliary_driver mlx5e_driver = {
5814 .probe = mlx5e_probe,
5815 .remove = mlx5e_remove,
5816 .suspend = mlx5e_suspend,
5817 .resume = mlx5e_resume,
5818 .id_table = mlx5e_id_table,
5821 int mlx5e_init(void)
5825 mlx5e_ipsec_build_inverse_table();
5826 mlx5e_build_ptys2ethtool_map();
5827 ret = mlx5e_rep_init();
5831 ret = auxiliary_driver_register(&mlx5e_driver);
5833 mlx5e_rep_cleanup();
5837 void mlx5e_cleanup(void)
5839 auxiliary_driver_unregister(&mlx5e_driver);
5840 mlx5e_rep_cleanup();