drivers/net/ethernet/mellanox/mlx5/core/en_main.c

   1 /*
   2  * Copyright (c) 2015-2016, Mellanox Technologies. All rights reserved.
   3  *
   4  * This software is available to you under a choice of one of two
   5  * licenses.  You may choose to be licensed under the terms of the GNU
   6  * General Public License (GPL) Version 2, available from the file
   7  * COPYING in the main directory of this source tree, or the
   8  * OpenIB.org BSD license below:
   9  *
  10  *     Redistribution and use in source and binary forms, with or
  11  *     without modification, are permitted provided that the following
  12  *     conditions are met:
  13  *
  14  *      - Redistributions of source code must retain the above
  15  *        copyright notice, this list of conditions and the following
  16  *        disclaimer.
  17  *
  18  *      - Redistributions in binary form must reproduce the above
  19  *        copyright notice, this list of conditions and the following
  20  *        disclaimer in the documentation and/or other materials
  21  *        provided with the distribution.
  22  *
  23  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  24  * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  25  * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
  26  * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
  27  * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
  28  * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
  29  * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
  30  * SOFTWARE.
  31  */
  32
  33 #include <net/tc_act/tc_gact.h>
  34 #include <net/pkt_cls.h>
  35 #include <linux/mlx5/fs.h>
  36 #include <net/vxlan.h>
  37 #include <net/geneve.h>
  38 #include <linux/bpf.h>
  39 #include <linux/if_bridge.h>
  40 #include <net/page_pool.h>
  41 #include <net/xdp_sock.h>
  42 #include "eswitch.h"
  43 #include "en.h"
  44 #include "en/txrx.h"
  45 #include "en_tc.h"
  46 #include "en_rep.h"
  47 #include "en_accel/ipsec.h"
  48 #include "en_accel/ipsec_rxtx.h"
  49 #include "en_accel/en_accel.h"
  50 #include "en_accel/tls.h"
  51 #include "accel/ipsec.h"
  52 #include "accel/tls.h"
  53 #include "lib/vxlan.h"
  54 #include "lib/clock.h"
  55 #include "en/port.h"
  56 #include "en/xdp.h"
  57 #include "lib/eq.h"
  58 #include "en/monitor_stats.h"
  59 #include "en/health.h"
  60 #include "en/params.h"
  61 #include "en/xsk/umem.h"
  62 #include "en/xsk/setup.h"
  63 #include "en/xsk/rx.h"
  64 #include "en/xsk/tx.h"
  65 #include "en/hv_vhca_stats.h"
  66 #include "lib/mlx5.h"
  67
  68
  69 bool mlx5e_check_fragmented_striding_rq_cap(struct mlx5_core_dev *mdev)
  70 {
  71         bool striding_rq_umr = MLX5_CAP_GEN(mdev, striding_rq) &&
  72                 MLX5_CAP_GEN(mdev, umr_ptr_rlky) &&
  73                 MLX5_CAP_ETH(mdev, reg_umr_sq);
  74         u16 max_wqe_sz_cap = MLX5_CAP_GEN(mdev, max_wqe_sz_sq);
  75         bool inline_umr = MLX5E_UMR_WQE_INLINE_SZ <= max_wqe_sz_cap;
  76
  77         if (!striding_rq_umr)
  78                 return false;
  79         if (!inline_umr) {
  80                 mlx5_core_warn(mdev, "Cannot support Striding RQ: UMR WQE size (%d) exceeds maximum supported (%d).\n",
  81                                (int)MLX5E_UMR_WQE_INLINE_SZ, max_wqe_sz_cap);
  82                 return false;
  83         }
  84         return true;
  85 }
  86
  87 void mlx5e_init_rq_type_params(struct mlx5_core_dev *mdev,
  88                                struct mlx5e_params *params)
  89 {
  90         params->log_rq_mtu_frames = is_kdump_kernel() ?
  91                 MLX5E_PARAMS_MINIMUM_LOG_RQ_SIZE :
  92                 MLX5E_PARAMS_DEFAULT_LOG_RQ_SIZE;
  93
  94         mlx5_core_info(mdev, "MLX5E: StrdRq(%d) RqSz(%ld) StrdSz(%ld) RxCqeCmprss(%d)\n",
  95                        params->rq_wq_type == MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ,
  96                        params->rq_wq_type == MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ ?
  97                        BIT(mlx5e_mpwqe_get_log_rq_size(params, NULL)) :
  98                        BIT(params->log_rq_mtu_frames),
  99                        BIT(mlx5e_mpwqe_get_log_stride_size(mdev, params, NULL)),
 100                        MLX5E_GET_PFLAG(params, MLX5E_PFLAG_RX_CQE_COMPRESS));
 101 }
 102
 103 bool mlx5e_striding_rq_possible(struct mlx5_core_dev *mdev,
 104                                 struct mlx5e_params *params)
 105 {
 106         if (!mlx5e_check_fragmented_striding_rq_cap(mdev))
 107                 return false;
 108
 109         if (MLX5_IPSEC_DEV(mdev))
 110                 return false;
 111
 112         if (params->xdp_prog) {
 113                 /* XSK params are not considered here. If striding RQ is in use,
 114                  * and an XSK is being opened, mlx5e_rx_mpwqe_is_linear_skb will
 115                  * be called with the known XSK params.
 116                  */
 117                 if (!mlx5e_rx_mpwqe_is_linear_skb(mdev, params, NULL))
 118                         return false;
 119         }
 120
 121         return true;
 122 }
 123
 124 void mlx5e_set_rq_type(struct mlx5_core_dev *mdev, struct mlx5e_params *params)
 125 {
 126         params->rq_wq_type = mlx5e_striding_rq_possible(mdev, params) &&
 127                 MLX5E_GET_PFLAG(params, MLX5E_PFLAG_RX_STRIDING_RQ) ?
 128                 MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ :
 129                 MLX5_WQ_TYPE_CYCLIC;
 130 }
 131
 132 void mlx5e_update_carrier(struct mlx5e_priv *priv)
 133 {
 134         struct mlx5_core_dev *mdev = priv->mdev;
 135         u8 port_state;
 136
 137         port_state = mlx5_query_vport_state(mdev,
 138                                             MLX5_VPORT_STATE_OP_MOD_VNIC_VPORT,
 139                                             0);
 140
 141         if (port_state == VPORT_STATE_UP) {
 142                 netdev_info(priv->netdev, "Link up\n");
 143                 netif_carrier_on(priv->netdev);
 144         } else {
 145                 netdev_info(priv->netdev, "Link down\n");
 146                 netif_carrier_off(priv->netdev);
 147         }
 148 }
 149
 150 static void mlx5e_update_carrier_work(struct work_struct *work)
 151 {
 152         struct mlx5e_priv *priv = container_of(work, struct mlx5e_priv,
 153                                                update_carrier_work);
 154
 155         mutex_lock(&priv->state_lock);
 156         if (test_bit(MLX5E_STATE_OPENED, &priv->state))
 157                 if (priv->profile->update_carrier)
 158                         priv->profile->update_carrier(priv);
 159         mutex_unlock(&priv->state_lock);
 160 }
 161
 162 void mlx5e_update_ndo_stats(struct mlx5e_priv *priv)
 163 {
 164         int i;
 165
 166         for (i = mlx5e_nic_stats_grps_num(priv) - 1; i >= 0; i--)
 167                 if (mlx5e_nic_stats_grps[i]->update_stats_mask &
 168                     MLX5E_NDO_UPDATE_STATS)
 169                         mlx5e_nic_stats_grps[i]->update_stats(priv);
 170 }
 171
 172 static void mlx5e_update_stats_work(struct work_struct *work)
 173 {
 174         struct mlx5e_priv *priv = container_of(work, struct mlx5e_priv,
 175                                                update_stats_work);
 176
 177         mutex_lock(&priv->state_lock);
 178         priv->profile->update_stats(priv);
 179         mutex_unlock(&priv->state_lock);
 180 }
 181
 182 void mlx5e_queue_update_stats(struct mlx5e_priv *priv)
 183 {
 184         if (!priv->profile->update_stats)
 185                 return;
 186
 187         if (unlikely(test_bit(MLX5E_STATE_DESTROYING, &priv->state)))
 188                 return;
 189
 190         queue_work(priv->wq, &priv->update_stats_work);
 191 }
 192
 193 static int async_event(struct notifier_block *nb, unsigned long event, void *data)
 194 {
 195         struct mlx5e_priv *priv = container_of(nb, struct mlx5e_priv, events_nb);
 196         struct mlx5_eqe   *eqe = data;
 197
 198         if (event != MLX5_EVENT_TYPE_PORT_CHANGE)
 199                 return NOTIFY_DONE;
 200
 201         switch (eqe->sub_type) {
 202         case MLX5_PORT_CHANGE_SUBTYPE_DOWN:
 203         case MLX5_PORT_CHANGE_SUBTYPE_ACTIVE:
 204                 queue_work(priv->wq, &priv->update_carrier_work);
 205                 break;
 206         default:
 207                 return NOTIFY_DONE;
 208         }
 209
 210         return NOTIFY_OK;
 211 }
 212
 213 static void mlx5e_enable_async_events(struct mlx5e_priv *priv)
 214 {
 215         priv->events_nb.notifier_call = async_event;
 216         mlx5_notifier_register(priv->mdev, &priv->events_nb);
 217 }
 218
 219 static void mlx5e_disable_async_events(struct mlx5e_priv *priv)
 220 {
 221         mlx5_notifier_unregister(priv->mdev, &priv->events_nb);
 222 }
 223
 224 static inline void mlx5e_build_umr_wqe(struct mlx5e_rq *rq,
 225                                        struct mlx5e_icosq *sq,
 226                                        struct mlx5e_umr_wqe *wqe)
 227 {
 228         struct mlx5_wqe_ctrl_seg      *cseg = &wqe->ctrl;
 229         struct mlx5_wqe_umr_ctrl_seg *ucseg = &wqe->uctrl;
 230         u8 ds_cnt = DIV_ROUND_UP(MLX5E_UMR_WQE_INLINE_SZ, MLX5_SEND_WQE_DS);
 231
 232         cseg->qpn_ds    = cpu_to_be32((sq->sqn << MLX5_WQE_CTRL_QPN_SHIFT) |
 233                                       ds_cnt);
 234         cseg->fm_ce_se  = MLX5_WQE_CTRL_CQ_UPDATE;
 235         cseg->imm       = rq->mkey_be;
 236
 237         ucseg->flags = MLX5_UMR_TRANSLATION_OFFSET_EN | MLX5_UMR_INLINE;
 238         ucseg->xlt_octowords =
 239                 cpu_to_be16(MLX5_MTT_OCTW(MLX5_MPWRQ_PAGES_PER_WQE));
 240         ucseg->mkey_mask     = cpu_to_be64(MLX5_MKEY_MASK_FREE);
 241 }
 242
 243 static int mlx5e_rq_alloc_mpwqe_info(struct mlx5e_rq *rq,
 244                                      struct mlx5e_channel *c)
 245 {
 246         int wq_sz = mlx5_wq_ll_get_size(&rq->mpwqe.wq);
 247
 248         rq->mpwqe.info = kvzalloc_node(array_size(wq_sz,
 249                                                   sizeof(*rq->mpwqe.info)),
 250                                        GFP_KERNEL, cpu_to_node(c->cpu));
 251         if (!rq->mpwqe.info)
 252                 return -ENOMEM;
 253
 254         mlx5e_build_umr_wqe(rq, &c->icosq, &rq->mpwqe.umr_wqe);
 255
 256         return 0;
 257 }
 258
 259 static int mlx5e_create_umr_mkey(struct mlx5_core_dev *mdev,
 260                                  u64 npages, u8 page_shift,
 261                                  struct mlx5_core_mkey *umr_mkey)
 262 {
 263         int inlen = MLX5_ST_SZ_BYTES(create_mkey_in);
 264         void *mkc;
 265         u32 *in;
 266         int err;
 267
 268         in = kvzalloc(inlen, GFP_KERNEL);
 269         if (!in)
 270                 return -ENOMEM;
 271
 272         mkc = MLX5_ADDR_OF(create_mkey_in, in, memory_key_mkey_entry);
 273
 274         MLX5_SET(mkc, mkc, free, 1);
 275         MLX5_SET(mkc, mkc, umr_en, 1);
 276         MLX5_SET(mkc, mkc, lw, 1);
 277         MLX5_SET(mkc, mkc, lr, 1);
 278         MLX5_SET(mkc, mkc, access_mode_1_0, MLX5_MKC_ACCESS_MODE_MTT);
 279
 280         MLX5_SET(mkc, mkc, qpn, 0xffffff);
 281         MLX5_SET(mkc, mkc, pd, mdev->mlx5e_res.pdn);
 282         MLX5_SET64(mkc, mkc, len, npages << page_shift);
 283         MLX5_SET(mkc, mkc, translations_octword_size,
 284                  MLX5_MTT_OCTW(npages));
 285         MLX5_SET(mkc, mkc, log_page_size, page_shift);
 286
 287         err = mlx5_core_create_mkey(mdev, umr_mkey, in, inlen);
 288
 289         kvfree(in);
 290         return err;
 291 }
 292
 293 static int mlx5e_create_rq_umr_mkey(struct mlx5_core_dev *mdev, struct mlx5e_rq *rq)
 294 {
 295         u64 num_mtts = MLX5E_REQUIRED_MTTS(mlx5_wq_ll_get_size(&rq->mpwqe.wq));
 296
 297         return mlx5e_create_umr_mkey(mdev, num_mtts, PAGE_SHIFT, &rq->umr_mkey);
 298 }
 299
 300 static inline u64 mlx5e_get_mpwqe_offset(struct mlx5e_rq *rq, u16 wqe_ix)
 301 {
 302         return (wqe_ix << MLX5E_LOG_ALIGNED_MPWQE_PPW) << PAGE_SHIFT;
 303 }
 304
 305 static void mlx5e_init_frags_partition(struct mlx5e_rq *rq)
 306 {
 307         struct mlx5e_wqe_frag_info next_frag = {};
 308         struct mlx5e_wqe_frag_info *prev = NULL;
 309         int i;
 310
 311         next_frag.di = &rq->wqe.di[0];
 312
 313         for (i = 0; i < mlx5_wq_cyc_get_size(&rq->wqe.wq); i++) {
 314                 struct mlx5e_rq_frag_info *frag_info = &rq->wqe.info.arr[0];
 315                 struct mlx5e_wqe_frag_info *frag =
 316                         &rq->wqe.frags[i << rq->wqe.info.log_num_frags];
 317                 int f;
 318
 319                 for (f = 0; f < rq->wqe.info.num_frags; f++, frag++) {
 320                         if (next_frag.offset + frag_info[f].frag_stride > PAGE_SIZE) {
 321                                 next_frag.di++;
 322                                 next_frag.offset = 0;
 323                                 if (prev)
 324                                         prev->last_in_page = true;
 325                         }
 326                         *frag = next_frag;
 327
 328                         /* prepare next */
 329                         next_frag.offset += frag_info[f].frag_stride;
 330                         prev = frag;
 331                 }
 332         }
 333
 334         if (prev)
 335                 prev->last_in_page = true;
 336 }
 337
 338 static int mlx5e_init_di_list(struct mlx5e_rq *rq,
 339                               int wq_sz, int cpu)
 340 {
 341         int len = wq_sz << rq->wqe.info.log_num_frags;
 342
 343         rq->wqe.di = kvzalloc_node(array_size(len, sizeof(*rq->wqe.di)),
 344                                    GFP_KERNEL, cpu_to_node(cpu));
 345         if (!rq->wqe.di)
 346                 return -ENOMEM;
 347
 348         mlx5e_init_frags_partition(rq);
 349
 350         return 0;
 351 }
 352
 353 static void mlx5e_free_di_list(struct mlx5e_rq *rq)
 354 {
 355         kvfree(rq->wqe.di);
 356 }
 357
 358 static void mlx5e_rq_err_cqe_work(struct work_struct *recover_work)
 359 {
 360         struct mlx5e_rq *rq = container_of(recover_work, struct mlx5e_rq, recover_work);
 361
 362         mlx5e_reporter_rq_cqe_err(rq);
 363 }
 364
 365 static int mlx5e_alloc_rq(struct mlx5e_channel *c,
 366                           struct mlx5e_params *params,
 367                           struct mlx5e_xsk_param *xsk,
 368                           struct xdp_umem *umem,
 369                           struct mlx5e_rq_param *rqp,
 370                           struct mlx5e_rq *rq)
 371 {
 372         struct page_pool_params pp_params = { 0 };
 373         struct mlx5_core_dev *mdev = c->mdev;
 374         void *rqc = rqp->rqc;
 375         void *rqc_wq = MLX5_ADDR_OF(rqc, rqc, wq);
 376         u32 num_xsk_frames = 0;
 377         u32 rq_xdp_ix;
 378         u32 pool_size;
 379         int wq_sz;
 380         int err;
 381         int i;
 382
 383         rqp->wq.db_numa_node = cpu_to_node(c->cpu);
 384
 385         rq->wq_type = params->rq_wq_type;
 386         rq->pdev    = c->pdev;
 387         rq->netdev  = c->netdev;
 388         rq->tstamp  = c->tstamp;
 389         rq->clock   = &mdev->clock;
 390         rq->channel = c;
 391         rq->ix      = c->ix;
 392         rq->mdev    = mdev;
 393         rq->hw_mtu  = MLX5E_SW2HW_MTU(params, params->sw_mtu);
 394         rq->xdpsq   = &c->rq_xdpsq;
 395         rq->umem    = umem;
 396
 397         if (rq->umem)
 398                 rq->stats = &c->priv->channel_stats[c->ix].xskrq;
 399         else
 400                 rq->stats = &c->priv->channel_stats[c->ix].rq;
 401         INIT_WORK(&rq->recover_work, mlx5e_rq_err_cqe_work);
 402
 403         if (params->xdp_prog)
 404                 bpf_prog_inc(params->xdp_prog);
 405         rq->xdp_prog = params->xdp_prog;
 406
 407         rq_xdp_ix = rq->ix;
 408         if (xsk)
 409                 rq_xdp_ix += params->num_channels * MLX5E_RQ_GROUP_XSK;
 410         err = xdp_rxq_info_reg(&rq->xdp_rxq, rq->netdev, rq_xdp_ix);
 411         if (err < 0)
 412                 goto err_rq_wq_destroy;
 413
 414         rq->buff.map_dir = rq->xdp_prog ? DMA_BIDIRECTIONAL : DMA_FROM_DEVICE;
 415         rq->buff.headroom = mlx5e_get_rq_headroom(mdev, params, xsk);
 416         rq->buff.umem_headroom = xsk ? xsk->headroom : 0;
 417         pool_size = 1 << params->log_rq_mtu_frames;
 418
 419         switch (rq->wq_type) {
 420         case MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ:
 421                 err = mlx5_wq_ll_create(mdev, &rqp->wq, rqc_wq, &rq->mpwqe.wq,
 422                                         &rq->wq_ctrl);
 423                 if (err)
 424                         return err;
 425
 426                 rq->mpwqe.wq.db = &rq->mpwqe.wq.db[MLX5_RCV_DBR];
 427
 428                 wq_sz = mlx5_wq_ll_get_size(&rq->mpwqe.wq);
 429
 430                 if (xsk)
 431                         num_xsk_frames = wq_sz <<
 432                                 mlx5e_mpwqe_get_log_num_strides(mdev, params, xsk);
 433
 434                 pool_size = MLX5_MPWRQ_PAGES_PER_WQE <<
 435                         mlx5e_mpwqe_get_log_rq_size(params, xsk);
 436
 437                 rq->post_wqes = mlx5e_post_rx_mpwqes;
 438                 rq->dealloc_wqe = mlx5e_dealloc_rx_mpwqe;
 439
 440                 rq->handle_rx_cqe = c->priv->profile->rx_handlers.handle_rx_cqe_mpwqe;
 441 #ifdef CONFIG_MLX5_EN_IPSEC
 442                 if (MLX5_IPSEC_DEV(mdev)) {
 443                         err = -EINVAL;
 444                         netdev_err(c->netdev, "MPWQE RQ with IPSec offload not supported\n");
 445                         goto err_rq_wq_destroy;
 446                 }
 447 #endif
 448                 if (!rq->handle_rx_cqe) {
 449                         err = -EINVAL;
 450                         netdev_err(c->netdev, "RX handler of MPWQE RQ is not set, err %d\n", err);
 451                         goto err_rq_wq_destroy;
 452                 }
 453
 454                 rq->mpwqe.skb_from_cqe_mpwrq = xsk ?
 455                         mlx5e_xsk_skb_from_cqe_mpwrq_linear :
 456                         mlx5e_rx_mpwqe_is_linear_skb(mdev, params, NULL) ?
 457                                 mlx5e_skb_from_cqe_mpwrq_linear :
 458                                 mlx5e_skb_from_cqe_mpwrq_nonlinear;
 459
 460                 rq->mpwqe.log_stride_sz = mlx5e_mpwqe_get_log_stride_size(mdev, params, xsk);
 461                 rq->mpwqe.num_strides =
 462                         BIT(mlx5e_mpwqe_get_log_num_strides(mdev, params, xsk));
 463
 464                 err = mlx5e_create_rq_umr_mkey(mdev, rq);
 465                 if (err)
 466                         goto err_rq_wq_destroy;
 467                 rq->mkey_be = cpu_to_be32(rq->umr_mkey.key);
 468
 469                 err = mlx5e_rq_alloc_mpwqe_info(rq, c);
 470                 if (err)
 471                         goto err_free;
 472                 break;
 473         default: /* MLX5_WQ_TYPE_CYCLIC */
 474                 err = mlx5_wq_cyc_create(mdev, &rqp->wq, rqc_wq, &rq->wqe.wq,
 475                                          &rq->wq_ctrl);
 476                 if (err)
 477                         return err;
 478
 479                 rq->wqe.wq.db = &rq->wqe.wq.db[MLX5_RCV_DBR];
 480
 481                 wq_sz = mlx5_wq_cyc_get_size(&rq->wqe.wq);
 482
 483                 if (xsk)
 484                         num_xsk_frames = wq_sz << rq->wqe.info.log_num_frags;
 485
 486                 rq->wqe.info = rqp->frags_info;
 487                 rq->wqe.frags =
 488                         kvzalloc_node(array_size(sizeof(*rq->wqe.frags),
 489                                         (wq_sz << rq->wqe.info.log_num_frags)),
 490                                       GFP_KERNEL, cpu_to_node(c->cpu));
 491                 if (!rq->wqe.frags) {
 492                         err = -ENOMEM;
 493                         goto err_free;
 494                 }
 495
 496                 err = mlx5e_init_di_list(rq, wq_sz, c->cpu);
 497                 if (err)
 498                         goto err_free;
 499
 500                 rq->post_wqes = mlx5e_post_rx_wqes;
 501                 rq->dealloc_wqe = mlx5e_dealloc_rx_wqe;
 502
 503 #ifdef CONFIG_MLX5_EN_IPSEC
 504                 if (c->priv->ipsec)
 505                         rq->handle_rx_cqe = mlx5e_ipsec_handle_rx_cqe;
 506                 else
 507 #endif
 508                         rq->handle_rx_cqe = c->priv->profile->rx_handlers.handle_rx_cqe;
 509                 if (!rq->handle_rx_cqe) {
 510                         err = -EINVAL;
 511                         netdev_err(c->netdev, "RX handler of RQ is not set, err %d\n", err);
 512                         goto err_free;
 513                 }
 514
 515                 rq->wqe.skb_from_cqe = xsk ?
 516                         mlx5e_xsk_skb_from_cqe_linear :
 517                         mlx5e_rx_is_linear_skb(params, NULL) ?
 518                                 mlx5e_skb_from_cqe_linear :
 519                                 mlx5e_skb_from_cqe_nonlinear;
 520                 rq->mkey_be = c->mkey_be;
 521         }
 522
 523         if (xsk) {
 524                 err = mlx5e_xsk_resize_reuseq(umem, num_xsk_frames);
 525                 if (unlikely(err)) {
 526                         mlx5_core_err(mdev, "Unable to allocate the Reuse Ring for %u frames\n",
 527                                       num_xsk_frames);
 528                         goto err_free;
 529                 }
 530
 531                 rq->zca.free = mlx5e_xsk_zca_free;
 532                 err = xdp_rxq_info_reg_mem_model(&rq->xdp_rxq,
 533                                                  MEM_TYPE_ZERO_COPY,
 534                                                  &rq->zca);
 535         } else {
 536                 /* Create a page_pool and register it with rxq */
 537                 pp_params.order     = 0;
 538                 pp_params.flags     = 0; /* No-internal DMA mapping in page_pool */
 539                 pp_params.pool_size = pool_size;
 540                 pp_params.nid       = cpu_to_node(c->cpu);
 541                 pp_params.dev       = c->pdev;
 542                 pp_params.dma_dir   = rq->buff.map_dir;
 543
 544                 /* page_pool can be used even when there is no rq->xdp_prog,
 545                  * given page_pool does not handle DMA mapping there is no
 546                  * required state to clear. And page_pool gracefully handle
 547                  * elevated refcnt.
 548                  */
 549                 rq->page_pool = page_pool_create(&pp_params);
 550                 if (IS_ERR(rq->page_pool)) {
 551                         err = PTR_ERR(rq->page_pool);
 552                         rq->page_pool = NULL;
 553                         goto err_free;
 554                 }
 555                 err = xdp_rxq_info_reg_mem_model(&rq->xdp_rxq,
 556                                                  MEM_TYPE_PAGE_POOL, rq->page_pool);
 557         }
 558         if (err)
 559                 goto err_free;
 560
 561         for (i = 0; i < wq_sz; i++) {
 562                 if (rq->wq_type == MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ) {
 563                         struct mlx5e_rx_wqe_ll *wqe =
 564                                 mlx5_wq_ll_get_wqe(&rq->mpwqe.wq, i);
 565                         u32 byte_count =
 566                                 rq->mpwqe.num_strides << rq->mpwqe.log_stride_sz;
 567                         u64 dma_offset = mlx5e_get_mpwqe_offset(rq, i);
 568
 569                         wqe->data[0].addr = cpu_to_be64(dma_offset + rq->buff.headroom);
 570                         wqe->data[0].byte_count = cpu_to_be32(byte_count);
 571                         wqe->data[0].lkey = rq->mkey_be;
 572                 } else {
 573                         struct mlx5e_rx_wqe_cyc *wqe =
 574                                 mlx5_wq_cyc_get_wqe(&rq->wqe.wq, i);
 575                         int f;
 576
 577                         for (f = 0; f < rq->wqe.info.num_frags; f++) {
 578                                 u32 frag_size = rq->wqe.info.arr[f].frag_size |
 579                                         MLX5_HW_START_PADDING;
 580
 581                                 wqe->data[f].byte_count = cpu_to_be32(frag_size);
 582                                 wqe->data[f].lkey = rq->mkey_be;
 583                         }
 584                         /* check if num_frags is not a pow of two */
 585                         if (rq->wqe.info.num_frags < (1 << rq->wqe.info.log_num_frags)) {
 586                                 wqe->data[f].byte_count = 0;
 587                                 wqe->data[f].lkey = cpu_to_be32(MLX5_INVALID_LKEY);
 588                                 wqe->data[f].addr = 0;
 589                         }
 590                 }
 591         }
 592
 593         INIT_WORK(&rq->dim.work, mlx5e_rx_dim_work);
 594
 595         switch (params->rx_cq_moderation.cq_period_mode) {
 596         case MLX5_CQ_PERIOD_MODE_START_FROM_CQE:
 597                 rq->dim.mode = DIM_CQ_PERIOD_MODE_START_FROM_CQE;
 598                 break;
 599         case MLX5_CQ_PERIOD_MODE_START_FROM_EQE:
 600         default:
 601                 rq->dim.mode = DIM_CQ_PERIOD_MODE_START_FROM_EQE;
 602         }
 603
 604         rq->page_cache.head = 0;
 605         rq->page_cache.tail = 0;
 606
 607         return 0;
 608
 609 err_free:
 610         switch (rq->wq_type) {
 611         case MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ:
 612                 kvfree(rq->mpwqe.info);
 613                 mlx5_core_destroy_mkey(mdev, &rq->umr_mkey);
 614                 break;
 615         default: /* MLX5_WQ_TYPE_CYCLIC */
 616                 kvfree(rq->wqe.frags);
 617                 mlx5e_free_di_list(rq);
 618         }
 619
 620 err_rq_wq_destroy:
 621         if (rq->xdp_prog)
 622                 bpf_prog_put(rq->xdp_prog);
 623         xdp_rxq_info_unreg(&rq->xdp_rxq);
 624         page_pool_destroy(rq->page_pool);
 625         mlx5_wq_destroy(&rq->wq_ctrl);
 626
 627         return err;
 628 }
 629
 630 static void mlx5e_free_rq(struct mlx5e_rq *rq)
 631 {
 632         int i;
 633
 634         if (rq->xdp_prog)
 635                 bpf_prog_put(rq->xdp_prog);
 636
 637         switch (rq->wq_type) {
 638         case MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ:
 639                 kvfree(rq->mpwqe.info);
 640                 mlx5_core_destroy_mkey(rq->mdev, &rq->umr_mkey);
 641                 break;
 642         default: /* MLX5_WQ_TYPE_CYCLIC */
 643                 kvfree(rq->wqe.frags);
 644                 mlx5e_free_di_list(rq);
 645         }
 646
 647         for (i = rq->page_cache.head; i != rq->page_cache.tail;
 648              i = (i + 1) & (MLX5E_CACHE_SIZE - 1)) {
 649                 struct mlx5e_dma_info *dma_info = &rq->page_cache.page_cache[i];
 650
 651                 /* With AF_XDP, page_cache is not used, so this loop is not
 652                  * entered, and it's safe to call mlx5e_page_release_dynamic
 653                  * directly.
 654                  */
 655                 mlx5e_page_release_dynamic(rq, dma_info, false);
 656         }
 657
 658         xdp_rxq_info_unreg(&rq->xdp_rxq);
 659         page_pool_destroy(rq->page_pool);
 660         mlx5_wq_destroy(&rq->wq_ctrl);
 661 }
 662
 663 static int mlx5e_create_rq(struct mlx5e_rq *rq,
 664                            struct mlx5e_rq_param *param)
 665 {
 666         struct mlx5_core_dev *mdev = rq->mdev;
 667
 668         void *in;
 669         void *rqc;
 670         void *wq;
 671         int inlen;
 672         int err;
 673
 674         inlen = MLX5_ST_SZ_BYTES(create_rq_in) +
 675                 sizeof(u64) * rq->wq_ctrl.buf.npages;
 676         in = kvzalloc(inlen, GFP_KERNEL);
 677         if (!in)
 678                 return -ENOMEM;
 679
 680         rqc = MLX5_ADDR_OF(create_rq_in, in, ctx);
 681         wq  = MLX5_ADDR_OF(rqc, rqc, wq);
 682
 683         memcpy(rqc, param->rqc, sizeof(param->rqc));
 684
 685         MLX5_SET(rqc,  rqc, cqn,                rq->cq.mcq.cqn);
 686         MLX5_SET(rqc,  rqc, state,              MLX5_RQC_STATE_RST);
 687         MLX5_SET(wq,   wq,  log_wq_pg_sz,       rq->wq_ctrl.buf.page_shift -
 688                                                 MLX5_ADAPTER_PAGE_SHIFT);
 689         MLX5_SET64(wq, wq,  dbr_addr,           rq->wq_ctrl.db.dma);
 690
 691         mlx5_fill_page_frag_array(&rq->wq_ctrl.buf,
 692                                   (__be64 *)MLX5_ADDR_OF(wq, wq, pas));
 693
 694         err = mlx5_core_create_rq(mdev, in, inlen, &rq->rqn);
 695
 696         kvfree(in);
 697
 698         return err;
 699 }
 700
 701 int mlx5e_modify_rq_state(struct mlx5e_rq *rq, int curr_state, int next_state)
 702 {
 703         struct mlx5_core_dev *mdev = rq->mdev;
 704
 705         void *in;
 706         void *rqc;
 707         int inlen;
 708         int err;
 709
 710         inlen = MLX5_ST_SZ_BYTES(modify_rq_in);
 711         in = kvzalloc(inlen, GFP_KERNEL);
 712         if (!in)
 713                 return -ENOMEM;
 714
 715         rqc = MLX5_ADDR_OF(modify_rq_in, in, ctx);
 716
 717         MLX5_SET(modify_rq_in, in, rq_state, curr_state);
 718         MLX5_SET(rqc, rqc, state, next_state);
 719
 720         err = mlx5_core_modify_rq(mdev, rq->rqn, in, inlen);
 721
 722         kvfree(in);
 723
 724         return err;
 725 }
 726
 727 static int mlx5e_modify_rq_scatter_fcs(struct mlx5e_rq *rq, bool enable)
 728 {
 729         struct mlx5e_channel *c = rq->channel;
 730         struct mlx5e_priv *priv = c->priv;
 731         struct mlx5_core_dev *mdev = priv->mdev;
 732
 733         void *in;
 734         void *rqc;
 735         int inlen;
 736         int err;
 737
 738         inlen = MLX5_ST_SZ_BYTES(modify_rq_in);
 739         in = kvzalloc(inlen, GFP_KERNEL);
 740         if (!in)
 741                 return -ENOMEM;
 742
 743         rqc = MLX5_ADDR_OF(modify_rq_in, in, ctx);
 744
 745         MLX5_SET(modify_rq_in, in, rq_state, MLX5_RQC_STATE_RDY);
 746         MLX5_SET64(modify_rq_in, in, modify_bitmask,
 747                    MLX5_MODIFY_RQ_IN_MODIFY_BITMASK_SCATTER_FCS);
 748         MLX5_SET(rqc, rqc, scatter_fcs, enable);
 749         MLX5_SET(rqc, rqc, state, MLX5_RQC_STATE_RDY);
 750
 751         err = mlx5_core_modify_rq(mdev, rq->rqn, in, inlen);
 752
 753         kvfree(in);
 754
 755         return err;
 756 }
 757
 758 static int mlx5e_modify_rq_vsd(struct mlx5e_rq *rq, bool vsd)
 759 {
 760         struct mlx5e_channel *c = rq->channel;
 761         struct mlx5_core_dev *mdev = c->mdev;
 762         void *in;
 763         void *rqc;
 764         int inlen;
 765         int err;
 766
 767         inlen = MLX5_ST_SZ_BYTES(modify_rq_in);
 768         in = kvzalloc(inlen, GFP_KERNEL);
 769         if (!in)
 770                 return -ENOMEM;
 771
 772         rqc = MLX5_ADDR_OF(modify_rq_in, in, ctx);
 773
 774         MLX5_SET(modify_rq_in, in, rq_state, MLX5_RQC_STATE_RDY);
 775         MLX5_SET64(modify_rq_in, in, modify_bitmask,
 776                    MLX5_MODIFY_RQ_IN_MODIFY_BITMASK_VSD);
 777         MLX5_SET(rqc, rqc, vsd, vsd);
 778         MLX5_SET(rqc, rqc, state, MLX5_RQC_STATE_RDY);
 779
 780         err = mlx5_core_modify_rq(mdev, rq->rqn, in, inlen);
 781
 782         kvfree(in);
 783
 784         return err;
 785 }
 786
 787 static void mlx5e_destroy_rq(struct mlx5e_rq *rq)
 788 {
 789         mlx5_core_destroy_rq(rq->mdev, rq->rqn);
 790 }
 791
 792 int mlx5e_wait_for_min_rx_wqes(struct mlx5e_rq *rq, int wait_time)
 793 {
 794         unsigned long exp_time = jiffies + msecs_to_jiffies(wait_time);
 795         struct mlx5e_channel *c = rq->channel;
 796
 797         u16 min_wqes = mlx5_min_rx_wqes(rq->wq_type, mlx5e_rqwq_get_size(rq));
 798
 799         do {
 800                 if (mlx5e_rqwq_get_cur_sz(rq) >= min_wqes)
 801                         return 0;
 802
 803                 msleep(20);
 804         } while (time_before(jiffies, exp_time));
 805
 806         netdev_warn(c->netdev, "Failed to get min RX wqes on Channel[%d] RQN[0x%x] wq cur_sz(%d) min_rx_wqes(%d)\n",
 807                     c->ix, rq->rqn, mlx5e_rqwq_get_cur_sz(rq), min_wqes);
 808
 809         mlx5e_reporter_rx_timeout(rq);
 810         return -ETIMEDOUT;
 811 }
 812
 813 void mlx5e_free_rx_descs(struct mlx5e_rq *rq)
 814 {
 815         __be16 wqe_ix_be;
 816         u16 wqe_ix;
 817
 818         if (rq->wq_type == MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ) {
 819                 struct mlx5_wq_ll *wq = &rq->mpwqe.wq;
 820                 u16 head = wq->head;
 821                 int i;
 822
 823                 /* Outstanding UMR WQEs (in progress) start at wq->head */
 824                 for (i = 0; i < rq->mpwqe.umr_in_progress; i++) {
 825                         rq->dealloc_wqe(rq, head);
 826                         head = mlx5_wq_ll_get_wqe_next_ix(wq, head);
 827                 }
 828
 829                 while (!mlx5_wq_ll_is_empty(wq)) {
 830                         struct mlx5e_rx_wqe_ll *wqe;
 831
 832                         wqe_ix_be = *wq->tail_next;
 833                         wqe_ix    = be16_to_cpu(wqe_ix_be);
 834                         wqe       = mlx5_wq_ll_get_wqe(wq, wqe_ix);
 835                         rq->dealloc_wqe(rq, wqe_ix);
 836                         mlx5_wq_ll_pop(wq, wqe_ix_be,
 837                                        &wqe->next.next_wqe_index);
 838                 }
 839         } else {
 840                 struct mlx5_wq_cyc *wq = &rq->wqe.wq;
 841
 842                 while (!mlx5_wq_cyc_is_empty(wq)) {
 843                         wqe_ix = mlx5_wq_cyc_get_tail(wq);
 844                         rq->dealloc_wqe(rq, wqe_ix);
 845                         mlx5_wq_cyc_pop(wq);
 846                 }
 847         }
 848
 849 }
 850
 851 int mlx5e_open_rq(struct mlx5e_channel *c, struct mlx5e_params *params,
 852                   struct mlx5e_rq_param *param, struct mlx5e_xsk_param *xsk,
 853                   struct xdp_umem *umem, struct mlx5e_rq *rq)
 854 {
 855         int err;
 856
 857         err = mlx5e_alloc_rq(c, params, xsk, umem, param, rq);
 858         if (err)
 859                 return err;
 860
 861         err = mlx5e_create_rq(rq, param);
 862         if (err)
 863                 goto err_free_rq;
 864
 865         err = mlx5e_modify_rq_state(rq, MLX5_RQC_STATE_RST, MLX5_RQC_STATE_RDY);
 866         if (err)
 867                 goto err_destroy_rq;
 868
 869         if (MLX5_CAP_ETH(c->mdev, cqe_checksum_full))
 870                 __set_bit(MLX5E_RQ_STATE_CSUM_FULL, &c->rq.state);
 871
 872         if (params->rx_dim_enabled)
 873                 __set_bit(MLX5E_RQ_STATE_AM, &c->rq.state);
 874
 875         /* We disable csum_complete when XDP is enabled since
 876          * XDP programs might manipulate packets which will render
 877          * skb->checksum incorrect.
 878          */
 879         if (MLX5E_GET_PFLAG(params, MLX5E_PFLAG_RX_NO_CSUM_COMPLETE) || c->xdp)
 880                 __set_bit(MLX5E_RQ_STATE_NO_CSUM_COMPLETE, &c->rq.state);
 881
 882         return 0;
 883
 884 err_destroy_rq:
 885         mlx5e_destroy_rq(rq);
 886 err_free_rq:
 887         mlx5e_free_rq(rq);
 888
 889         return err;
 890 }
 891
 892 void mlx5e_activate_rq(struct mlx5e_rq *rq)
 893 {
 894         set_bit(MLX5E_RQ_STATE_ENABLED, &rq->state);
 895         mlx5e_trigger_irq(&rq->channel->icosq);
 896 }
 897
 898 void mlx5e_deactivate_rq(struct mlx5e_rq *rq)
 899 {
 900         clear_bit(MLX5E_RQ_STATE_ENABLED, &rq->state);
 901         napi_synchronize(&rq->channel->napi); /* prevent mlx5e_post_rx_wqes */
 902 }
 903
 904 void mlx5e_close_rq(struct mlx5e_rq *rq)
 905 {
 906         cancel_work_sync(&rq->dim.work);
 907         cancel_work_sync(&rq->channel->icosq.recover_work);
 908         cancel_work_sync(&rq->recover_work);
 909         mlx5e_destroy_rq(rq);
 910         mlx5e_free_rx_descs(rq);
 911         mlx5e_free_rq(rq);
 912 }
 913
 914 static void mlx5e_free_xdpsq_db(struct mlx5e_xdpsq *sq)
 915 {
 916         kvfree(sq->db.xdpi_fifo.xi);
 917         kvfree(sq->db.wqe_info);
 918 }
 919
 920 static int mlx5e_alloc_xdpsq_fifo(struct mlx5e_xdpsq *sq, int numa)
 921 {
 922         struct mlx5e_xdp_info_fifo *xdpi_fifo = &sq->db.xdpi_fifo;
 923         int wq_sz        = mlx5_wq_cyc_get_size(&sq->wq);
 924         int dsegs_per_wq = wq_sz * MLX5_SEND_WQEBB_NUM_DS;
 925
 926         xdpi_fifo->xi = kvzalloc_node(sizeof(*xdpi_fifo->xi) * dsegs_per_wq,
 927                                       GFP_KERNEL, numa);
 928         if (!xdpi_fifo->xi)
 929                 return -ENOMEM;
 930
 931         xdpi_fifo->pc   = &sq->xdpi_fifo_pc;
 932         xdpi_fifo->cc   = &sq->xdpi_fifo_cc;
 933         xdpi_fifo->mask = dsegs_per_wq - 1;
 934
 935         return 0;
 936 }
 937
 938 static int mlx5e_alloc_xdpsq_db(struct mlx5e_xdpsq *sq, int numa)
 939 {
 940         int wq_sz = mlx5_wq_cyc_get_size(&sq->wq);
 941         int err;
 942
 943         sq->db.wqe_info = kvzalloc_node(sizeof(*sq->db.wqe_info) * wq_sz,
 944                                         GFP_KERNEL, numa);
 945         if (!sq->db.wqe_info)
 946                 return -ENOMEM;
 947
 948         err = mlx5e_alloc_xdpsq_fifo(sq, numa);
 949         if (err) {
 950                 mlx5e_free_xdpsq_db(sq);
 951                 return err;
 952         }
 953
 954         return 0;
 955 }
 956
 957 static int mlx5e_alloc_xdpsq(struct mlx5e_channel *c,
 958                              struct mlx5e_params *params,
 959                              struct xdp_umem *umem,
 960                              struct mlx5e_sq_param *param,
 961                              struct mlx5e_xdpsq *sq,
 962                              bool is_redirect)
 963 {
 964         void *sqc_wq               = MLX5_ADDR_OF(sqc, param->sqc, wq);
 965         struct mlx5_core_dev *mdev = c->mdev;
 966         struct mlx5_wq_cyc *wq = &sq->wq;
 967         int err;
 968
 969         sq->pdev      = c->pdev;
 970         sq->mkey_be   = c->mkey_be;
 971         sq->channel   = c;
 972         sq->uar_map   = mdev->mlx5e_res.bfreg.map;
 973         sq->min_inline_mode = params->tx_min_inline_mode;
 974         sq->hw_mtu    = MLX5E_SW2HW_MTU(params, params->sw_mtu);
 975         sq->umem      = umem;
 976
 977         sq->stats = sq->umem ?
 978                 &c->priv->channel_stats[c->ix].xsksq :
 979                 is_redirect ?
 980                         &c->priv->channel_stats[c->ix].xdpsq :
 981                         &c->priv->channel_stats[c->ix].rq_xdpsq;
 982
 983         param->wq.db_numa_node = cpu_to_node(c->cpu);
 984         err = mlx5_wq_cyc_create(mdev, &param->wq, sqc_wq, wq, &sq->wq_ctrl);
 985         if (err)
 986                 return err;
 987         wq->db = &wq->db[MLX5_SND_DBR];
 988
 989         err = mlx5e_alloc_xdpsq_db(sq, cpu_to_node(c->cpu));
 990         if (err)
 991                 goto err_sq_wq_destroy;
 992
 993         return 0;
 994
 995 err_sq_wq_destroy:
 996         mlx5_wq_destroy(&sq->wq_ctrl);
 997
 998         return err;
 999 }
1000
1001 static void mlx5e_free_xdpsq(struct mlx5e_xdpsq *sq)
1002 {
1003         mlx5e_free_xdpsq_db(sq);
1004         mlx5_wq_destroy(&sq->wq_ctrl);
1005 }
1006
1007 static void mlx5e_free_icosq_db(struct mlx5e_icosq *sq)
1008 {
1009         kvfree(sq->db.ico_wqe);
1010 }
1011
1012 static int mlx5e_alloc_icosq_db(struct mlx5e_icosq *sq, int numa)
1013 {
1014         int wq_sz = mlx5_wq_cyc_get_size(&sq->wq);
1015
1016         sq->db.ico_wqe = kvzalloc_node(array_size(wq_sz,
1017                                                   sizeof(*sq->db.ico_wqe)),
1018                                        GFP_KERNEL, numa);
1019         if (!sq->db.ico_wqe)
1020                 return -ENOMEM;
1021
1022         return 0;
1023 }
1024
1025 static void mlx5e_icosq_err_cqe_work(struct work_struct *recover_work)
1026 {
1027         struct mlx5e_icosq *sq = container_of(recover_work, struct mlx5e_icosq,
1028                                               recover_work);
1029
1030         mlx5e_reporter_icosq_cqe_err(sq);
1031 }
1032
1033 static int mlx5e_alloc_icosq(struct mlx5e_channel *c,
1034                              struct mlx5e_sq_param *param,
1035                              struct mlx5e_icosq *sq)
1036 {
1037         void *sqc_wq               = MLX5_ADDR_OF(sqc, param->sqc, wq);
1038         struct mlx5_core_dev *mdev = c->mdev;
1039         struct mlx5_wq_cyc *wq = &sq->wq;
1040         int err;
1041
1042         sq->channel   = c;
1043         sq->uar_map   = mdev->mlx5e_res.bfreg.map;
1044
1045         param->wq.db_numa_node = cpu_to_node(c->cpu);
1046         err = mlx5_wq_cyc_create(mdev, &param->wq, sqc_wq, wq, &sq->wq_ctrl);
1047         if (err)
1048                 return err;
1049         wq->db = &wq->db[MLX5_SND_DBR];
1050
1051         err = mlx5e_alloc_icosq_db(sq, cpu_to_node(c->cpu));
1052         if (err)
1053                 goto err_sq_wq_destroy;
1054
1055         INIT_WORK(&sq->recover_work, mlx5e_icosq_err_cqe_work);
1056
1057         return 0;
1058
1059 err_sq_wq_destroy:
1060         mlx5_wq_destroy(&sq->wq_ctrl);
1061
1062         return err;
1063 }
1064
1065 static void mlx5e_free_icosq(struct mlx5e_icosq *sq)
1066 {
1067         mlx5e_free_icosq_db(sq);
1068         mlx5_wq_destroy(&sq->wq_ctrl);
1069 }
1070
1071 static void mlx5e_free_txqsq_db(struct mlx5e_txqsq *sq)
1072 {
1073         kvfree(sq->db.wqe_info);
1074         kvfree(sq->db.dma_fifo);
1075 }
1076
1077 static int mlx5e_alloc_txqsq_db(struct mlx5e_txqsq *sq, int numa)
1078 {
1079         int wq_sz = mlx5_wq_cyc_get_size(&sq->wq);
1080         int df_sz = wq_sz * MLX5_SEND_WQEBB_NUM_DS;
1081
1082         sq->db.dma_fifo = kvzalloc_node(array_size(df_sz,
1083                                                    sizeof(*sq->db.dma_fifo)),
1084                                         GFP_KERNEL, numa);
1085         sq->db.wqe_info = kvzalloc_node(array_size(wq_sz,
1086                                                    sizeof(*sq->db.wqe_info)),
1087                                         GFP_KERNEL, numa);
1088         if (!sq->db.dma_fifo || !sq->db.wqe_info) {
1089                 mlx5e_free_txqsq_db(sq);
1090                 return -ENOMEM;
1091         }
1092
1093         sq->dma_fifo_mask = df_sz - 1;
1094
1095         return 0;
1096 }
1097
1098 static void mlx5e_tx_err_cqe_work(struct work_struct *recover_work);
1099 static int mlx5e_alloc_txqsq(struct mlx5e_channel *c,
1100                              int txq_ix,
1101                              struct mlx5e_params *params,
1102                              struct mlx5e_sq_param *param,
1103                              struct mlx5e_txqsq *sq,
1104                              int tc)
1105 {
1106         void *sqc_wq               = MLX5_ADDR_OF(sqc, param->sqc, wq);
1107         struct mlx5_core_dev *mdev = c->mdev;
1108         struct mlx5_wq_cyc *wq = &sq->wq;
1109         int err;
1110
1111         sq->pdev      = c->pdev;
1112         sq->tstamp    = c->tstamp;
1113         sq->clock     = &mdev->clock;
1114         sq->mkey_be   = c->mkey_be;
1115         sq->channel   = c;
1116         sq->ch_ix     = c->ix;
1117         sq->txq_ix    = txq_ix;
1118         sq->uar_map   = mdev->mlx5e_res.bfreg.map;
1119         sq->min_inline_mode = params->tx_min_inline_mode;
1120         sq->hw_mtu    = MLX5E_SW2HW_MTU(params, params->sw_mtu);
1121         sq->stats     = &c->priv->channel_stats[c->ix].sq[tc];
1122         sq->stop_room = MLX5E_SQ_STOP_ROOM;
1123         INIT_WORK(&sq->recover_work, mlx5e_tx_err_cqe_work);
1124         if (!MLX5_CAP_ETH(mdev, wqe_vlan_insert))
1125                 set_bit(MLX5E_SQ_STATE_VLAN_NEED_L2_INLINE, &sq->state);
1126         if (MLX5_IPSEC_DEV(c->priv->mdev))
1127                 set_bit(MLX5E_SQ_STATE_IPSEC, &sq->state);
1128 #ifdef CONFIG_MLX5_EN_TLS
1129         if (mlx5_accel_is_tls_device(c->priv->mdev)) {
1130                 set_bit(MLX5E_SQ_STATE_TLS, &sq->state);
1131                 sq->stop_room += MLX5E_SQ_TLS_ROOM +
1132                         mlx5e_ktls_dumps_num_wqebbs(sq, MAX_SKB_FRAGS,
1133                                                     TLS_MAX_PAYLOAD_SIZE);
1134         }
1135 #endif
1136
1137         param->wq.db_numa_node = cpu_to_node(c->cpu);
1138         err = mlx5_wq_cyc_create(mdev, &param->wq, sqc_wq, wq, &sq->wq_ctrl);
1139         if (err)
1140                 return err;
1141         wq->db    = &wq->db[MLX5_SND_DBR];
1142
1143         err = mlx5e_alloc_txqsq_db(sq, cpu_to_node(c->cpu));
1144         if (err)
1145                 goto err_sq_wq_destroy;
1146
1147         INIT_WORK(&sq->dim.work, mlx5e_tx_dim_work);
1148         sq->dim.mode = params->tx_cq_moderation.cq_period_mode;
1149
1150         return 0;
1151
1152 err_sq_wq_destroy:
1153         mlx5_wq_destroy(&sq->wq_ctrl);
1154
1155         return err;
1156 }
1157
1158 static void mlx5e_free_txqsq(struct mlx5e_txqsq *sq)
1159 {
1160         mlx5e_free_txqsq_db(sq);
1161         mlx5_wq_destroy(&sq->wq_ctrl);
1162 }
1163
1164 struct mlx5e_create_sq_param {
1165         struct mlx5_wq_ctrl        *wq_ctrl;
1166         u32                         cqn;
1167         u32                         tisn;
1168         u8                          tis_lst_sz;
1169         u8                          min_inline_mode;
1170 };
1171
1172 static int mlx5e_create_sq(struct mlx5_core_dev *mdev,
1173                            struct mlx5e_sq_param *param,
1174                            struct mlx5e_create_sq_param *csp,
1175                            u32 *sqn)
1176 {
1177         void *in;
1178         void *sqc;
1179         void *wq;
1180         int inlen;
1181         int err;
1182
1183         inlen = MLX5_ST_SZ_BYTES(create_sq_in) +
1184                 sizeof(u64) * csp->wq_ctrl->buf.npages;
1185         in = kvzalloc(inlen, GFP_KERNEL);
1186         if (!in)
1187                 return -ENOMEM;
1188
1189         sqc = MLX5_ADDR_OF(create_sq_in, in, ctx);
1190         wq = MLX5_ADDR_OF(sqc, sqc, wq);
1191
1192         memcpy(sqc, param->sqc, sizeof(param->sqc));
1193         MLX5_SET(sqc,  sqc, tis_lst_sz, csp->tis_lst_sz);
1194         MLX5_SET(sqc,  sqc, tis_num_0, csp->tisn);
1195         MLX5_SET(sqc,  sqc, cqn, csp->cqn);
1196
1197         if (MLX5_CAP_ETH(mdev, wqe_inline_mode) == MLX5_CAP_INLINE_MODE_VPORT_CONTEXT)
1198                 MLX5_SET(sqc,  sqc, min_wqe_inline_mode, csp->min_inline_mode);
1199
1200         MLX5_SET(sqc,  sqc, state, MLX5_SQC_STATE_RST);
1201         MLX5_SET(sqc,  sqc, flush_in_error_en, 1);
1202
1203         MLX5_SET(wq,   wq, wq_type,       MLX5_WQ_TYPE_CYCLIC);
1204         MLX5_SET(wq,   wq, uar_page,      mdev->mlx5e_res.bfreg.index);
1205         MLX5_SET(wq,   wq, log_wq_pg_sz,  csp->wq_ctrl->buf.page_shift -
1206                                           MLX5_ADAPTER_PAGE_SHIFT);
1207         MLX5_SET64(wq, wq, dbr_addr,      csp->wq_ctrl->db.dma);
1208
1209         mlx5_fill_page_frag_array(&csp->wq_ctrl->buf,
1210                                   (__be64 *)MLX5_ADDR_OF(wq, wq, pas));
1211
1212         err = mlx5_core_create_sq(mdev, in, inlen, sqn);
1213
1214         kvfree(in);
1215
1216         return err;
1217 }
1218
1219 int mlx5e_modify_sq(struct mlx5_core_dev *mdev, u32 sqn,
1220                     struct mlx5e_modify_sq_param *p)
1221 {
1222         void *in;
1223         void *sqc;
1224         int inlen;
1225         int err;
1226
1227         inlen = MLX5_ST_SZ_BYTES(modify_sq_in);
1228         in = kvzalloc(inlen, GFP_KERNEL);
1229         if (!in)
1230                 return -ENOMEM;
1231
1232         sqc = MLX5_ADDR_OF(modify_sq_in, in, ctx);
1233
1234         MLX5_SET(modify_sq_in, in, sq_state, p->curr_state);
1235         MLX5_SET(sqc, sqc, state, p->next_state);
1236         if (p->rl_update && p->next_state == MLX5_SQC_STATE_RDY) {
1237                 MLX5_SET64(modify_sq_in, in, modify_bitmask, 1);
1238                 MLX5_SET(sqc,  sqc, packet_pacing_rate_limit_index, p->rl_index);
1239         }
1240
1241         err = mlx5_core_modify_sq(mdev, sqn, in, inlen);
1242
1243         kvfree(in);
1244
1245         return err;
1246 }
1247
1248 static void mlx5e_destroy_sq(struct mlx5_core_dev *mdev, u32 sqn)
1249 {
1250         mlx5_core_destroy_sq(mdev, sqn);
1251 }
1252
1253 static int mlx5e_create_sq_rdy(struct mlx5_core_dev *mdev,
1254                                struct mlx5e_sq_param *param,
1255                                struct mlx5e_create_sq_param *csp,
1256                                u32 *sqn)
1257 {
1258         struct mlx5e_modify_sq_param msp = {0};
1259         int err;
1260
1261         err = mlx5e_create_sq(mdev, param, csp, sqn);
1262         if (err)
1263                 return err;
1264
1265         msp.curr_state = MLX5_SQC_STATE_RST;
1266         msp.next_state = MLX5_SQC_STATE_RDY;
1267         err = mlx5e_modify_sq(mdev, *sqn, &msp);
1268         if (err)
1269                 mlx5e_destroy_sq(mdev, *sqn);
1270
1271         return err;
1272 }
1273
1274 static int mlx5e_set_sq_maxrate(struct net_device *dev,
1275                                 struct mlx5e_txqsq *sq, u32 rate);
1276
1277 static int mlx5e_open_txqsq(struct mlx5e_channel *c,
1278                             u32 tisn,
1279                             int txq_ix,
1280                             struct mlx5e_params *params,
1281                             struct mlx5e_sq_param *param,
1282                             struct mlx5e_txqsq *sq,
1283                             int tc)
1284 {
1285         struct mlx5e_create_sq_param csp = {};
1286         u32 tx_rate;
1287         int err;
1288
1289         err = mlx5e_alloc_txqsq(c, txq_ix, params, param, sq, tc);
1290         if (err)
1291                 return err;
1292
1293         csp.tisn            = tisn;
1294         csp.tis_lst_sz      = 1;
1295         csp.cqn             = sq->cq.mcq.cqn;
1296         csp.wq_ctrl         = &sq->wq_ctrl;
1297         csp.min_inline_mode = sq->min_inline_mode;
1298         err = mlx5e_create_sq_rdy(c->mdev, param, &csp, &sq->sqn);
1299         if (err)
1300                 goto err_free_txqsq;
1301
1302         tx_rate = c->priv->tx_rates[sq->txq_ix];
1303         if (tx_rate)
1304                 mlx5e_set_sq_maxrate(c->netdev, sq, tx_rate);
1305
1306         if (params->tx_dim_enabled)
1307                 sq->state |= BIT(MLX5E_SQ_STATE_AM);
1308
1309         return 0;
1310
1311 err_free_txqsq:
1312         mlx5e_free_txqsq(sq);
1313
1314         return err;
1315 }
1316
1317 void mlx5e_activate_txqsq(struct mlx5e_txqsq *sq)
1318 {
1319         sq->txq = netdev_get_tx_queue(sq->channel->netdev, sq->txq_ix);
1320         set_bit(MLX5E_SQ_STATE_ENABLED, &sq->state);
1321         netdev_tx_reset_queue(sq->txq);
1322         netif_tx_start_queue(sq->txq);
1323 }
1324
1325 void mlx5e_tx_disable_queue(struct netdev_queue *txq)
1326 {
1327         __netif_tx_lock_bh(txq);
1328         netif_tx_stop_queue(txq);
1329         __netif_tx_unlock_bh(txq);
1330 }
1331
1332 static void mlx5e_deactivate_txqsq(struct mlx5e_txqsq *sq)
1333 {
1334         struct mlx5e_channel *c = sq->channel;
1335         struct mlx5_wq_cyc *wq = &sq->wq;
1336
1337         clear_bit(MLX5E_SQ_STATE_ENABLED, &sq->state);
1338         /* prevent netif_tx_wake_queue */
1339         napi_synchronize(&c->napi);
1340
1341         mlx5e_tx_disable_queue(sq->txq);
1342
1343         /* last doorbell out, godspeed .. */
1344         if (mlx5e_wqc_has_room_for(wq, sq->cc, sq->pc, 1)) {
1345                 u16 pi = mlx5_wq_cyc_ctr2ix(wq, sq->pc);
1346                 struct mlx5e_tx_wqe_info *wi;
1347                 struct mlx5e_tx_wqe *nop;
1348
1349                 wi = &sq->db.wqe_info[pi];
1350
1351                 memset(wi, 0, sizeof(*wi));
1352                 wi->num_wqebbs = 1;
1353                 nop = mlx5e_post_nop(wq, sq->sqn, &sq->pc);
1354                 mlx5e_notify_hw(wq, sq->pc, sq->uar_map, &nop->ctrl);
1355         }
1356 }
1357
1358 static void mlx5e_close_txqsq(struct mlx5e_txqsq *sq)
1359 {
1360         struct mlx5e_channel *c = sq->channel;
1361         struct mlx5_core_dev *mdev = c->mdev;
1362         struct mlx5_rate_limit rl = {0};
1363
1364         cancel_work_sync(&sq->dim.work);
1365         cancel_work_sync(&sq->recover_work);
1366         mlx5e_destroy_sq(mdev, sq->sqn);
1367         if (sq->rate_limit) {
1368                 rl.rate = sq->rate_limit;
1369                 mlx5_rl_remove_rate(mdev, &rl);
1370         }
1371         mlx5e_free_txqsq_descs(sq);
1372         mlx5e_free_txqsq(sq);
1373 }
1374
1375 static void mlx5e_tx_err_cqe_work(struct work_struct *recover_work)
1376 {
1377         struct mlx5e_txqsq *sq = container_of(recover_work, struct mlx5e_txqsq,
1378                                               recover_work);
1379
1380         mlx5e_reporter_tx_err_cqe(sq);
1381 }
1382
1383 int mlx5e_open_icosq(struct mlx5e_channel *c, struct mlx5e_params *params,
1384                      struct mlx5e_sq_param *param, struct mlx5e_icosq *sq)
1385 {
1386         struct mlx5e_create_sq_param csp = {};
1387         int err;
1388
1389         err = mlx5e_alloc_icosq(c, param, sq);
1390         if (err)
1391                 return err;
1392
1393         csp.cqn             = sq->cq.mcq.cqn;
1394         csp.wq_ctrl         = &sq->wq_ctrl;
1395         csp.min_inline_mode = params->tx_min_inline_mode;
1396         err = mlx5e_create_sq_rdy(c->mdev, param, &csp, &sq->sqn);
1397         if (err)
1398                 goto err_free_icosq;
1399
1400         return 0;
1401
1402 err_free_icosq:
1403         mlx5e_free_icosq(sq);
1404
1405         return err;
1406 }
1407
1408 void mlx5e_activate_icosq(struct mlx5e_icosq *icosq)
1409 {
1410         set_bit(MLX5E_SQ_STATE_ENABLED, &icosq->state);
1411 }
1412
1413 void mlx5e_deactivate_icosq(struct mlx5e_icosq *icosq)
1414 {
1415         struct mlx5e_channel *c = icosq->channel;
1416
1417         clear_bit(MLX5E_SQ_STATE_ENABLED, &icosq->state);
1418         napi_synchronize(&c->napi);
1419 }
1420
1421 void mlx5e_close_icosq(struct mlx5e_icosq *sq)
1422 {
1423         struct mlx5e_channel *c = sq->channel;
1424
1425         mlx5e_destroy_sq(c->mdev, sq->sqn);
1426         mlx5e_free_icosq(sq);
1427 }
1428
1429 int mlx5e_open_xdpsq(struct mlx5e_channel *c, struct mlx5e_params *params,
1430                      struct mlx5e_sq_param *param, struct xdp_umem *umem,
1431                      struct mlx5e_xdpsq *sq, bool is_redirect)
1432 {
1433         struct mlx5e_create_sq_param csp = {};
1434         int err;
1435
1436         err = mlx5e_alloc_xdpsq(c, params, umem, param, sq, is_redirect);
1437         if (err)
1438                 return err;
1439
1440         csp.tis_lst_sz      = 1;
1441         csp.tisn            = c->priv->tisn[c->lag_port][0]; /* tc = 0 */
1442         csp.cqn             = sq->cq.mcq.cqn;
1443         csp.wq_ctrl         = &sq->wq_ctrl;
1444         csp.min_inline_mode = sq->min_inline_mode;
1445         set_bit(MLX5E_SQ_STATE_ENABLED, &sq->state);
1446         err = mlx5e_create_sq_rdy(c->mdev, param, &csp, &sq->sqn);
1447         if (err)
1448                 goto err_free_xdpsq;
1449
1450         mlx5e_set_xmit_fp(sq, param->is_mpw);
1451
1452         if (!param->is_mpw) {
1453                 unsigned int ds_cnt = MLX5E_XDP_TX_DS_COUNT;
1454                 unsigned int inline_hdr_sz = 0;
1455                 int i;
1456
1457                 if (sq->min_inline_mode != MLX5_INLINE_MODE_NONE) {
1458                         inline_hdr_sz = MLX5E_XDP_MIN_INLINE;
1459                         ds_cnt++;
1460                 }
1461
1462                 /* Pre initialize fixed WQE fields */
1463                 for (i = 0; i < mlx5_wq_cyc_get_size(&sq->wq); i++) {
1464                         struct mlx5e_xdp_wqe_info *wi  = &sq->db.wqe_info[i];
1465                         struct mlx5e_tx_wqe      *wqe  = mlx5_wq_cyc_get_wqe(&sq->wq, i);
1466                         struct mlx5_wqe_ctrl_seg *cseg = &wqe->ctrl;
1467                         struct mlx5_wqe_eth_seg  *eseg = &wqe->eth;
1468                         struct mlx5_wqe_data_seg *dseg;
1469
1470                         cseg->qpn_ds = cpu_to_be32((sq->sqn << 8) | ds_cnt);
1471                         eseg->inline_hdr.sz = cpu_to_be16(inline_hdr_sz);
1472
1473                         dseg = (struct mlx5_wqe_data_seg *)cseg + (ds_cnt - 1);
1474                         dseg->lkey = sq->mkey_be;
1475
1476                         wi->num_wqebbs = 1;
1477                         wi->num_pkts   = 1;
1478                 }
1479         }
1480
1481         return 0;
1482
1483 err_free_xdpsq:
1484         clear_bit(MLX5E_SQ_STATE_ENABLED, &sq->state);
1485         mlx5e_free_xdpsq(sq);
1486
1487         return err;
1488 }
1489
1490 void mlx5e_close_xdpsq(struct mlx5e_xdpsq *sq)
1491 {
1492         struct mlx5e_channel *c = sq->channel;
1493
1494         clear_bit(MLX5E_SQ_STATE_ENABLED, &sq->state);
1495         napi_synchronize(&c->napi);
1496
1497         mlx5e_destroy_sq(c->mdev, sq->sqn);
1498         mlx5e_free_xdpsq_descs(sq);
1499         mlx5e_free_xdpsq(sq);
1500 }
1501
1502 static int mlx5e_alloc_cq_common(struct mlx5_core_dev *mdev,
1503                                  struct mlx5e_cq_param *param,
1504                                  struct mlx5e_cq *cq)
1505 {
1506         struct mlx5_core_cq *mcq = &cq->mcq;
1507         int eqn_not_used;
1508         unsigned int irqn;
1509         int err;
1510         u32 i;
1511
1512         err = mlx5_vector2eqn(mdev, param->eq_ix, &eqn_not_used, &irqn);
1513         if (err)
1514                 return err;
1515
1516         err = mlx5_cqwq_create(mdev, &param->wq, param->cqc, &cq->wq,
1517                                &cq->wq_ctrl);
1518         if (err)
1519                 return err;
1520
1521         mcq->cqe_sz     = 64;
1522         mcq->set_ci_db  = cq->wq_ctrl.db.db;
1523         mcq->arm_db     = cq->wq_ctrl.db.db + 1;
1524         *mcq->set_ci_db = 0;
1525         *mcq->arm_db    = 0;
1526         mcq->vector     = param->eq_ix;
1527         mcq->comp       = mlx5e_completion_event;
1528         mcq->event      = mlx5e_cq_error_event;
1529         mcq->irqn       = irqn;
1530
1531         for (i = 0; i < mlx5_cqwq_get_size(&cq->wq); i++) {
1532                 struct mlx5_cqe64 *cqe = mlx5_cqwq_get_wqe(&cq->wq, i);
1533
1534                 cqe->op_own = 0xf1;
1535         }
1536
1537         cq->mdev = mdev;
1538
1539         return 0;
1540 }
1541
1542 static int mlx5e_alloc_cq(struct mlx5e_channel *c,
1543                           struct mlx5e_cq_param *param,
1544                           struct mlx5e_cq *cq)
1545 {
1546         struct mlx5_core_dev *mdev = c->priv->mdev;
1547         int err;
1548
1549         param->wq.buf_numa_node = cpu_to_node(c->cpu);
1550         param->wq.db_numa_node  = cpu_to_node(c->cpu);
1551         param->eq_ix   = c->ix;
1552
1553         err = mlx5e_alloc_cq_common(mdev, param, cq);
1554
1555         cq->napi    = &c->napi;
1556         cq->channel = c;
1557
1558         return err;
1559 }
1560
1561 static void mlx5e_free_cq(struct mlx5e_cq *cq)
1562 {
1563         mlx5_wq_destroy(&cq->wq_ctrl);
1564 }
1565
1566 static int mlx5e_create_cq(struct mlx5e_cq *cq, struct mlx5e_cq_param *param)
1567 {
1568         u32 out[MLX5_ST_SZ_DW(create_cq_out)];
1569         struct mlx5_core_dev *mdev = cq->mdev;
1570         struct mlx5_core_cq *mcq = &cq->mcq;
1571
1572         void *in;
1573         void *cqc;
1574         int inlen;
1575         unsigned int irqn_not_used;
1576         int eqn;
1577         int err;
1578
1579         err = mlx5_vector2eqn(mdev, param->eq_ix, &eqn, &irqn_not_used);
1580         if (err)
1581                 return err;
1582
1583         inlen = MLX5_ST_SZ_BYTES(create_cq_in) +
1584                 sizeof(u64) * cq->wq_ctrl.buf.npages;
1585         in = kvzalloc(inlen, GFP_KERNEL);
1586         if (!in)
1587                 return -ENOMEM;
1588
1589         cqc = MLX5_ADDR_OF(create_cq_in, in, cq_context);
1590
1591         memcpy(cqc, param->cqc, sizeof(param->cqc));
1592
1593         mlx5_fill_page_frag_array(&cq->wq_ctrl.buf,
1594                                   (__be64 *)MLX5_ADDR_OF(create_cq_in, in, pas));
1595
1596         MLX5_SET(cqc,   cqc, cq_period_mode, param->cq_period_mode);
1597         MLX5_SET(cqc,   cqc, c_eqn,         eqn);
1598         MLX5_SET(cqc,   cqc, uar_page,      mdev->priv.uar->index);
1599         MLX5_SET(cqc,   cqc, log_page_size, cq->wq_ctrl.buf.page_shift -
1600                                             MLX5_ADAPTER_PAGE_SHIFT);
1601         MLX5_SET64(cqc, cqc, dbr_addr,      cq->wq_ctrl.db.dma);
1602
1603         err = mlx5_core_create_cq(mdev, mcq, in, inlen, out, sizeof(out));
1604
1605         kvfree(in);
1606
1607         if (err)
1608                 return err;
1609
1610         mlx5e_cq_arm(cq);
1611
1612         return 0;
1613 }
1614
1615 static void mlx5e_destroy_cq(struct mlx5e_cq *cq)
1616 {
1617         mlx5_core_destroy_cq(cq->mdev, &cq->mcq);
1618 }
1619
1620 int mlx5e_open_cq(struct mlx5e_channel *c, struct dim_cq_moder moder,
1621                   struct mlx5e_cq_param *param, struct mlx5e_cq *cq)
1622 {
1623         struct mlx5_core_dev *mdev = c->mdev;
1624         int err;
1625
1626         err = mlx5e_alloc_cq(c, param, cq);
1627         if (err)
1628                 return err;
1629
1630         err = mlx5e_create_cq(cq, param);
1631         if (err)
1632                 goto err_free_cq;
1633
1634         if (MLX5_CAP_GEN(mdev, cq_moderation))
1635                 mlx5_core_modify_cq_moderation(mdev, &cq->mcq, moder.usec, moder.pkts);
1636         return 0;
1637
1638 err_free_cq:
1639         mlx5e_free_cq(cq);
1640
1641         return err;
1642 }
1643
1644 void mlx5e_close_cq(struct mlx5e_cq *cq)
1645 {
1646         mlx5e_destroy_cq(cq);
1647         mlx5e_free_cq(cq);
1648 }
1649
1650 static int mlx5e_open_tx_cqs(struct mlx5e_channel *c,
1651                              struct mlx5e_params *params,
1652                              struct mlx5e_channel_param *cparam)
1653 {
1654         int err;
1655         int tc;
1656
1657         for (tc = 0; tc < c->num_tc; tc++) {
1658                 err = mlx5e_open_cq(c, params->tx_cq_moderation,
1659                                     &cparam->tx_cq, &c->sq[tc].cq);
1660                 if (err)
1661                         goto err_close_tx_cqs;
1662         }
1663
1664         return 0;
1665
1666 err_close_tx_cqs:
1667         for (tc--; tc >= 0; tc--)
1668                 mlx5e_close_cq(&c->sq[tc].cq);
1669
1670         return err;
1671 }
1672
1673 static void mlx5e_close_tx_cqs(struct mlx5e_channel *c)
1674 {
1675         int tc;
1676
1677         for (tc = 0; tc < c->num_tc; tc++)
1678                 mlx5e_close_cq(&c->sq[tc].cq);
1679 }
1680
1681 static int mlx5e_open_sqs(struct mlx5e_channel *c,
1682                           struct mlx5e_params *params,
1683                           struct mlx5e_channel_param *cparam)
1684 {
1685         int err, tc;
1686
1687         for (tc = 0; tc < params->num_tc; tc++) {
1688                 int txq_ix = c->ix + tc * params->num_channels;
1689
1690                 err = mlx5e_open_txqsq(c, c->priv->tisn[c->lag_port][tc], txq_ix,
1691                                        params, &cparam->sq, &c->sq[tc], tc);
1692                 if (err)
1693                         goto err_close_sqs;
1694         }
1695
1696         return 0;
1697
1698 err_close_sqs:
1699         for (tc--; tc >= 0; tc--)
1700                 mlx5e_close_txqsq(&c->sq[tc]);
1701
1702         return err;
1703 }
1704
1705 static void mlx5e_close_sqs(struct mlx5e_channel *c)
1706 {
1707         int tc;
1708
1709         for (tc = 0; tc < c->num_tc; tc++)
1710                 mlx5e_close_txqsq(&c->sq[tc]);
1711 }
1712
1713 static int mlx5e_set_sq_maxrate(struct net_device *dev,
1714                                 struct mlx5e_txqsq *sq, u32 rate)
1715 {
1716         struct mlx5e_priv *priv = netdev_priv(dev);
1717         struct mlx5_core_dev *mdev = priv->mdev;
1718         struct mlx5e_modify_sq_param msp = {0};
1719         struct mlx5_rate_limit rl = {0};
1720         u16 rl_index = 0;
1721         int err;
1722
1723         if (rate == sq->rate_limit)
1724                 /* nothing to do */
1725                 return 0;
1726
1727         if (sq->rate_limit) {
1728                 rl.rate = sq->rate_limit;
1729                 /* remove current rl index to free space to next ones */
1730                 mlx5_rl_remove_rate(mdev, &rl);
1731         }
1732
1733         sq->rate_limit = 0;
1734
1735         if (rate) {
1736                 rl.rate = rate;
1737                 err = mlx5_rl_add_rate(mdev, &rl_index, &rl);
1738                 if (err) {
1739                         netdev_err(dev, "Failed configuring rate %u: %d\n",
1740                                    rate, err);
1741                         return err;
1742                 }
1743         }
1744
1745         msp.curr_state = MLX5_SQC_STATE_RDY;
1746         msp.next_state = MLX5_SQC_STATE_RDY;
1747         msp.rl_index   = rl_index;
1748         msp.rl_update  = true;
1749         err = mlx5e_modify_sq(mdev, sq->sqn, &msp);
1750         if (err) {
1751                 netdev_err(dev, "Failed configuring rate %u: %d\n",
1752                            rate, err);
1753                 /* remove the rate from the table */
1754                 if (rate)
1755                         mlx5_rl_remove_rate(mdev, &rl);
1756                 return err;
1757         }
1758
1759         sq->rate_limit = rate;
1760         return 0;
1761 }
1762
1763 static int mlx5e_set_tx_maxrate(struct net_device *dev, int index, u32 rate)
1764 {
1765         struct mlx5e_priv *priv = netdev_priv(dev);
1766         struct mlx5_core_dev *mdev = priv->mdev;
1767         struct mlx5e_txqsq *sq = priv->txq2sq[index];
1768         int err = 0;
1769
1770         if (!mlx5_rl_is_supported(mdev)) {
1771                 netdev_err(dev, "Rate limiting is not supported on this device\n");
1772                 return -EINVAL;
1773         }
1774
1775         /* rate is given in Mb/sec, HW config is in Kb/sec */
1776         rate = rate << 10;
1777
1778         /* Check whether rate in valid range, 0 is always valid */
1779         if (rate && !mlx5_rl_is_in_range(mdev, rate)) {
1780                 netdev_err(dev, "TX rate %u, is not in range\n", rate);
1781                 return -ERANGE;
1782         }
1783
1784         mutex_lock(&priv->state_lock);
1785         if (test_bit(MLX5E_STATE_OPENED, &priv->state))
1786                 err = mlx5e_set_sq_maxrate(dev, sq, rate);
1787         if (!err)
1788                 priv->tx_rates[index] = rate;
1789         mutex_unlock(&priv->state_lock);
1790
1791         return err;
1792 }
1793
1794 static int mlx5e_alloc_xps_cpumask(struct mlx5e_channel *c,
1795                                    struct mlx5e_params *params)
1796 {
1797         int num_comp_vectors = mlx5_comp_vectors_count(c->mdev);
1798         int irq;
1799
1800         if (!zalloc_cpumask_var(&c->xps_cpumask, GFP_KERNEL))
1801                 return -ENOMEM;
1802
1803         for (irq = c->ix; irq < num_comp_vectors; irq += params->num_channels) {
1804                 int cpu = cpumask_first(mlx5_comp_irq_get_affinity_mask(c->mdev, irq));
1805
1806                 cpumask_set_cpu(cpu, c->xps_cpumask);
1807         }
1808
1809         return 0;
1810 }
1811
1812 static void mlx5e_free_xps_cpumask(struct mlx5e_channel *c)
1813 {
1814         free_cpumask_var(c->xps_cpumask);
1815 }
1816
1817 static int mlx5e_open_queues(struct mlx5e_channel *c,
1818                              struct mlx5e_params *params,
1819                              struct mlx5e_channel_param *cparam)
1820 {
1821         struct dim_cq_moder icocq_moder = {0, 0};
1822         int err;
1823
1824         err = mlx5e_open_cq(c, icocq_moder, &cparam->icosq_cq, &c->icosq.cq);
1825         if (err)
1826                 return err;
1827
1828         err = mlx5e_open_tx_cqs(c, params, cparam);
1829         if (err)
1830                 goto err_close_icosq_cq;
1831
1832         err = mlx5e_open_cq(c, params->tx_cq_moderation, &cparam->tx_cq, &c->xdpsq.cq);
1833         if (err)
1834                 goto err_close_tx_cqs;
1835
1836         err = mlx5e_open_cq(c, params->rx_cq_moderation, &cparam->rx_cq, &c->rq.cq);
1837         if (err)
1838                 goto err_close_xdp_tx_cqs;
1839
1840         /* XDP SQ CQ params are same as normal TXQ sq CQ params */
1841         err = c->xdp ? mlx5e_open_cq(c, params->tx_cq_moderation,
1842                                      &cparam->tx_cq, &c->rq_xdpsq.cq) : 0;
1843         if (err)
1844                 goto err_close_rx_cq;
1845
1846         napi_enable(&c->napi);
1847
1848         err = mlx5e_open_icosq(c, params, &cparam->icosq, &c->icosq);
1849         if (err)
1850                 goto err_disable_napi;
1851
1852         err = mlx5e_open_sqs(c, params, cparam);
1853         if (err)
1854                 goto err_close_icosq;
1855
1856         if (c->xdp) {
1857                 err = mlx5e_open_xdpsq(c, params, &cparam->xdp_sq, NULL,
1858                                        &c->rq_xdpsq, false);
1859                 if (err)
1860                         goto err_close_sqs;
1861         }
1862
1863         err = mlx5e_open_rq(c, params, &cparam->rq, NULL, NULL, &c->rq);
1864         if (err)
1865                 goto err_close_xdp_sq;
1866
1867         err = mlx5e_open_xdpsq(c, params, &cparam->xdp_sq, NULL, &c->xdpsq, true);
1868         if (err)
1869                 goto err_close_rq;
1870
1871         return 0;
1872
1873 err_close_rq:
1874         mlx5e_close_rq(&c->rq);
1875
1876 err_close_xdp_sq:
1877         if (c->xdp)
1878                 mlx5e_close_xdpsq(&c->rq_xdpsq);
1879
1880 err_close_sqs:
1881         mlx5e_close_sqs(c);
1882
1883 err_close_icosq:
1884         mlx5e_close_icosq(&c->icosq);
1885
1886 err_disable_napi:
1887         napi_disable(&c->napi);
1888
1889         if (c->xdp)
1890                 mlx5e_close_cq(&c->rq_xdpsq.cq);
1891
1892 err_close_rx_cq:
1893         mlx5e_close_cq(&c->rq.cq);
1894
1895 err_close_xdp_tx_cqs:
1896         mlx5e_close_cq(&c->xdpsq.cq);
1897
1898 err_close_tx_cqs:
1899         mlx5e_close_tx_cqs(c);
1900
1901 err_close_icosq_cq:
1902         mlx5e_close_cq(&c->icosq.cq);
1903
1904         return err;
1905 }
1906
1907 static void mlx5e_close_queues(struct mlx5e_channel *c)
1908 {
1909         mlx5e_close_xdpsq(&c->xdpsq);
1910         mlx5e_close_rq(&c->rq);
1911         if (c->xdp)
1912                 mlx5e_close_xdpsq(&c->rq_xdpsq);
1913         mlx5e_close_sqs(c);
1914         mlx5e_close_icosq(&c->icosq);
1915         napi_disable(&c->napi);
1916         if (c->xdp)
1917                 mlx5e_close_cq(&c->rq_xdpsq.cq);
1918         mlx5e_close_cq(&c->rq.cq);
1919         mlx5e_close_cq(&c->xdpsq.cq);
1920         mlx5e_close_tx_cqs(c);
1921         mlx5e_close_cq(&c->icosq.cq);
1922 }
1923
1924 static u8 mlx5e_enumerate_lag_port(struct mlx5_core_dev *mdev, int ix)
1925 {
1926         u16 port_aff_bias = mlx5_core_is_pf(mdev) ? 0 : MLX5_CAP_GEN(mdev, vhca_id);
1927
1928         return (ix + port_aff_bias) % mlx5e_get_num_lag_ports(mdev);
1929 }
1930
1931 static int mlx5e_open_channel(struct mlx5e_priv *priv, int ix,
1932                               struct mlx5e_params *params,
1933                               struct mlx5e_channel_param *cparam,
1934                               struct xdp_umem *umem,
1935                               struct mlx5e_channel **cp)
1936 {
1937         int cpu = cpumask_first(mlx5_comp_irq_get_affinity_mask(priv->mdev, ix));
1938         struct net_device *netdev = priv->netdev;
1939         struct mlx5e_xsk_param xsk;
1940         struct mlx5e_channel *c;
1941         unsigned int irq;
1942         int err;
1943         int eqn;
1944
1945         err = mlx5_vector2eqn(priv->mdev, ix, &eqn, &irq);
1946         if (err)
1947                 return err;
1948
1949         c = kvzalloc_node(sizeof(*c), GFP_KERNEL, cpu_to_node(cpu));
1950         if (!c)
1951                 return -ENOMEM;
1952
1953         c->priv     = priv;
1954         c->mdev     = priv->mdev;
1955         c->tstamp   = &priv->tstamp;
1956         c->ix       = ix;
1957         c->cpu      = cpu;
1958         c->pdev     = priv->mdev->device;
1959         c->netdev   = priv->netdev;
1960         c->mkey_be  = cpu_to_be32(priv->mdev->mlx5e_res.mkey.key);
1961         c->num_tc   = params->num_tc;
1962         c->xdp      = !!params->xdp_prog;
1963         c->stats    = &priv->channel_stats[ix].ch;
1964         c->irq_desc = irq_to_desc(irq);
1965         c->lag_port = mlx5e_enumerate_lag_port(priv->mdev, ix);
1966
1967         err = mlx5e_alloc_xps_cpumask(c, params);
1968         if (err)
1969                 goto err_free_channel;
1970
1971         netif_napi_add(netdev, &c->napi, mlx5e_napi_poll, 64);
1972
1973         err = mlx5e_open_queues(c, params, cparam);
1974         if (unlikely(err))
1975                 goto err_napi_del;
1976
1977         if (umem) {
1978                 mlx5e_build_xsk_param(umem, &xsk);
1979                 err = mlx5e_open_xsk(priv, params, &xsk, umem, c);
1980                 if (unlikely(err))
1981                         goto err_close_queues;
1982         }
1983
1984         *cp = c;
1985
1986         return 0;
1987
1988 err_close_queues:
1989         mlx5e_close_queues(c);
1990
1991 err_napi_del:
1992         netif_napi_del(&c->napi);
1993         mlx5e_free_xps_cpumask(c);
1994
1995 err_free_channel:
1996         kvfree(c);
1997
1998         return err;
1999 }
2000
2001 static void mlx5e_activate_channel(struct mlx5e_channel *c)
2002 {
2003         int tc;
2004
2005         for (tc = 0; tc < c->num_tc; tc++)
2006                 mlx5e_activate_txqsq(&c->sq[tc]);
2007         mlx5e_activate_icosq(&c->icosq);
2008         mlx5e_activate_rq(&c->rq);
2009         netif_set_xps_queue(c->netdev, c->xps_cpumask, c->ix);
2010
2011         if (test_bit(MLX5E_CHANNEL_STATE_XSK, c->state))
2012                 mlx5e_activate_xsk(c);
2013 }
2014
2015 static void mlx5e_deactivate_channel(struct mlx5e_channel *c)
2016 {
2017         int tc;
2018
2019         if (test_bit(MLX5E_CHANNEL_STATE_XSK, c->state))
2020                 mlx5e_deactivate_xsk(c);
2021
2022         mlx5e_deactivate_rq(&c->rq);
2023         mlx5e_deactivate_icosq(&c->icosq);
2024         for (tc = 0; tc < c->num_tc; tc++)
2025                 mlx5e_deactivate_txqsq(&c->sq[tc]);
2026 }
2027
2028 static void mlx5e_close_channel(struct mlx5e_channel *c)
2029 {
2030         if (test_bit(MLX5E_CHANNEL_STATE_XSK, c->state))
2031                 mlx5e_close_xsk(c);
2032         mlx5e_close_queues(c);
2033         netif_napi_del(&c->napi);
2034         mlx5e_free_xps_cpumask(c);
2035
2036         kvfree(c);
2037 }
2038
2039 #define DEFAULT_FRAG_SIZE (2048)
2040
2041 static void mlx5e_build_rq_frags_info(struct mlx5_core_dev *mdev,
2042                                       struct mlx5e_params *params,
2043                                       struct mlx5e_xsk_param *xsk,
2044                                       struct mlx5e_rq_frags_info *info)
2045 {
2046         u32 byte_count = MLX5E_SW2HW_MTU(params, params->sw_mtu);
2047         int frag_size_max = DEFAULT_FRAG_SIZE;
2048         u32 buf_size = 0;
2049         int i;
2050
2051 #ifdef CONFIG_MLX5_EN_IPSEC
2052         if (MLX5_IPSEC_DEV(mdev))
2053                 byte_count += MLX5E_METADATA_ETHER_LEN;
2054 #endif
2055
2056         if (mlx5e_rx_is_linear_skb(params, xsk)) {
2057                 int frag_stride;
2058
2059                 frag_stride = mlx5e_rx_get_linear_frag_sz(params, xsk);
2060                 frag_stride = roundup_pow_of_two(frag_stride);
2061
2062                 info->arr[0].frag_size = byte_count;
2063                 info->arr[0].frag_stride = frag_stride;
2064                 info->num_frags = 1;
2065                 info->wqe_bulk = PAGE_SIZE / frag_stride;
2066                 goto out;
2067         }
2068
2069         if (byte_count > PAGE_SIZE +
2070             (MLX5E_MAX_RX_FRAGS - 1) * frag_size_max)
2071                 frag_size_max = PAGE_SIZE;
2072
2073         i = 0;
2074         while (buf_size < byte_count) {
2075                 int frag_size = byte_count - buf_size;
2076
2077                 if (i < MLX5E_MAX_RX_FRAGS - 1)
2078                         frag_size = min(frag_size, frag_size_max);
2079
2080                 info->arr[i].frag_size = frag_size;
2081                 info->arr[i].frag_stride = roundup_pow_of_two(frag_size);
2082
2083                 buf_size += frag_size;
2084                 i++;
2085         }
2086         info->num_frags = i;
2087         /* number of different wqes sharing a page */
2088         info->wqe_bulk = 1 + (info->num_frags % 2);
2089
2090 out:
2091         info->wqe_bulk = max_t(u8, info->wqe_bulk, 8);
2092         info->log_num_frags = order_base_2(info->num_frags);
2093 }
2094
2095 static inline u8 mlx5e_get_rqwq_log_stride(u8 wq_type, int ndsegs)
2096 {
2097         int sz = sizeof(struct mlx5_wqe_data_seg) * ndsegs;
2098
2099         switch (wq_type) {
2100         case MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ:
2101                 sz += sizeof(struct mlx5e_rx_wqe_ll);
2102                 break;
2103         default: /* MLX5_WQ_TYPE_CYCLIC */
2104                 sz += sizeof(struct mlx5e_rx_wqe_cyc);
2105         }
2106
2107         return order_base_2(sz);
2108 }
2109
2110 static u8 mlx5e_get_rq_log_wq_sz(void *rqc)
2111 {
2112         void *wq = MLX5_ADDR_OF(rqc, rqc, wq);
2113
2114         return MLX5_GET(wq, wq, log_wq_sz);
2115 }
2116
2117 void mlx5e_build_rq_param(struct mlx5e_priv *priv,
2118                           struct mlx5e_params *params,
2119                           struct mlx5e_xsk_param *xsk,
2120                           struct mlx5e_rq_param *param)
2121 {
2122         struct mlx5_core_dev *mdev = priv->mdev;
2123         void *rqc = param->rqc;
2124         void *wq = MLX5_ADDR_OF(rqc, rqc, wq);
2125         int ndsegs = 1;
2126
2127         switch (params->rq_wq_type) {
2128         case MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ:
2129                 MLX5_SET(wq, wq, log_wqe_num_of_strides,
2130                          mlx5e_mpwqe_get_log_num_strides(mdev, params, xsk) -
2131                          MLX5_MPWQE_LOG_NUM_STRIDES_BASE);
2132                 MLX5_SET(wq, wq, log_wqe_stride_size,
2133                          mlx5e_mpwqe_get_log_stride_size(mdev, params, xsk) -
2134                          MLX5_MPWQE_LOG_STRIDE_SZ_BASE);
2135                 MLX5_SET(wq, wq, log_wq_sz, mlx5e_mpwqe_get_log_rq_size(params, xsk));
2136                 break;
2137         default: /* MLX5_WQ_TYPE_CYCLIC */
2138                 MLX5_SET(wq, wq, log_wq_sz, params->log_rq_mtu_frames);
2139                 mlx5e_build_rq_frags_info(mdev, params, xsk, &param->frags_info);
2140                 ndsegs = param->frags_info.num_frags;
2141         }
2142
2143         MLX5_SET(wq, wq, wq_type,          params->rq_wq_type);
2144         MLX5_SET(wq, wq, end_padding_mode, MLX5_WQ_END_PAD_MODE_ALIGN);
2145         MLX5_SET(wq, wq, log_wq_stride,
2146                  mlx5e_get_rqwq_log_stride(params->rq_wq_type, ndsegs));
2147         MLX5_SET(wq, wq, pd,               mdev->mlx5e_res.pdn);
2148         MLX5_SET(rqc, rqc, counter_set_id, priv->q_counter);
2149         MLX5_SET(rqc, rqc, vsd,            params->vlan_strip_disable);
2150         MLX5_SET(rqc, rqc, scatter_fcs,    params->scatter_fcs_en);
2151
2152         param->wq.buf_numa_node = dev_to_node(mdev->device);
2153 }
2154
2155 static void mlx5e_build_drop_rq_param(struct mlx5e_priv *priv,
2156                                       struct mlx5e_rq_param *param)
2157 {
2158         struct mlx5_core_dev *mdev = priv->mdev;
2159         void *rqc = param->rqc;
2160         void *wq = MLX5_ADDR_OF(rqc, rqc, wq);
2161
2162         MLX5_SET(wq, wq, wq_type, MLX5_WQ_TYPE_CYCLIC);
2163         MLX5_SET(wq, wq, log_wq_stride,
2164                  mlx5e_get_rqwq_log_stride(MLX5_WQ_TYPE_CYCLIC, 1));
2165         MLX5_SET(rqc, rqc, counter_set_id, priv->drop_rq_q_counter);
2166
2167         param->wq.buf_numa_node = dev_to_node(mdev->device);
2168 }
2169
2170 void mlx5e_build_sq_param_common(struct mlx5e_priv *priv,
2171                                  struct mlx5e_sq_param *param)
2172 {
2173         void *sqc = param->sqc;
2174         void *wq = MLX5_ADDR_OF(sqc, sqc, wq);
2175
2176         MLX5_SET(wq, wq, log_wq_stride, ilog2(MLX5_SEND_WQE_BB));
2177         MLX5_SET(wq, wq, pd,            priv->mdev->mlx5e_res.pdn);
2178
2179         param->wq.buf_numa_node = dev_to_node(priv->mdev->device);
2180 }
2181
2182 static void mlx5e_build_sq_param(struct mlx5e_priv *priv,
2183                                  struct mlx5e_params *params,
2184                                  struct mlx5e_sq_param *param)
2185 {
2186         void *sqc = param->sqc;
2187         void *wq = MLX5_ADDR_OF(sqc, sqc, wq);
2188         bool allow_swp;
2189
2190         allow_swp = mlx5_geneve_tx_allowed(priv->mdev) ||
2191                     !!MLX5_IPSEC_DEV(priv->mdev);
2192         mlx5e_build_sq_param_common(priv, param);
2193         MLX5_SET(wq, wq, log_wq_sz, params->log_sq_size);
2194         MLX5_SET(sqc, sqc, allow_swp, allow_swp);
2195 }
2196
2197 static void mlx5e_build_common_cq_param(struct mlx5e_priv *priv,
2198                                         struct mlx5e_cq_param *param)
2199 {
2200         void *cqc = param->cqc;
2201
2202         MLX5_SET(cqc, cqc, uar_page, priv->mdev->priv.uar->index);
2203         if (MLX5_CAP_GEN(priv->mdev, cqe_128_always) && cache_line_size() >= 128)
2204                 MLX5_SET(cqc, cqc, cqe_sz, CQE_STRIDE_128_PAD);
2205 }
2206
2207 void mlx5e_build_rx_cq_param(struct mlx5e_priv *priv,
2208                              struct mlx5e_params *params,
2209                              struct mlx5e_xsk_param *xsk,
2210                              struct mlx5e_cq_param *param)
2211 {
2212         struct mlx5_core_dev *mdev = priv->mdev;
2213         void *cqc = param->cqc;
2214         u8 log_cq_size;
2215
2216         switch (params->rq_wq_type) {
2217         case MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ:
2218                 log_cq_size = mlx5e_mpwqe_get_log_rq_size(params, xsk) +
2219                         mlx5e_mpwqe_get_log_num_strides(mdev, params, xsk);
2220                 break;
2221         default: /* MLX5_WQ_TYPE_CYCLIC */
2222                 log_cq_size = params->log_rq_mtu_frames;
2223         }
2224
2225         MLX5_SET(cqc, cqc, log_cq_size, log_cq_size);
2226         if (MLX5E_GET_PFLAG(params, MLX5E_PFLAG_RX_CQE_COMPRESS)) {
2227                 MLX5_SET(cqc, cqc, mini_cqe_res_format, MLX5_CQE_FORMAT_CSUM);
2228                 MLX5_SET(cqc, cqc, cqe_comp_en, 1);
2229         }
2230
2231         mlx5e_build_common_cq_param(priv, param);
2232         param->cq_period_mode = params->rx_cq_moderation.cq_period_mode;
2233 }
2234
2235 void mlx5e_build_tx_cq_param(struct mlx5e_priv *priv,
2236                              struct mlx5e_params *params,
2237                              struct mlx5e_cq_param *param)
2238 {
2239         void *cqc = param->cqc;
2240
2241         MLX5_SET(cqc, cqc, log_cq_size, params->log_sq_size);
2242
2243         mlx5e_build_common_cq_param(priv, param);
2244         param->cq_period_mode = params->tx_cq_moderation.cq_period_mode;
2245 }
2246
2247 void mlx5e_build_ico_cq_param(struct mlx5e_priv *priv,
2248                               u8 log_wq_size,
2249                               struct mlx5e_cq_param *param)
2250 {
2251         void *cqc = param->cqc;
2252
2253         MLX5_SET(cqc, cqc, log_cq_size, log_wq_size);
2254
2255         mlx5e_build_common_cq_param(priv, param);
2256
2257         param->cq_period_mode = DIM_CQ_PERIOD_MODE_START_FROM_EQE;
2258 }
2259
2260 void mlx5e_build_icosq_param(struct mlx5e_priv *priv,
2261                              u8 log_wq_size,
2262                              struct mlx5e_sq_param *param)
2263 {
2264         void *sqc = param->sqc;
2265         void *wq = MLX5_ADDR_OF(sqc, sqc, wq);
2266
2267         mlx5e_build_sq_param_common(priv, param);
2268
2269         MLX5_SET(wq, wq, log_wq_sz, log_wq_size);
2270         MLX5_SET(sqc, sqc, reg_umr, MLX5_CAP_ETH(priv->mdev, reg_umr_sq));
2271 }
2272
2273 void mlx5e_build_xdpsq_param(struct mlx5e_priv *priv,
2274                              struct mlx5e_params *params,
2275                              struct mlx5e_sq_param *param)
2276 {
2277         void *sqc = param->sqc;
2278         void *wq = MLX5_ADDR_OF(sqc, sqc, wq);
2279
2280         mlx5e_build_sq_param_common(priv, param);
2281         MLX5_SET(wq, wq, log_wq_sz, params->log_sq_size);
2282         param->is_mpw = MLX5E_GET_PFLAG(params, MLX5E_PFLAG_XDP_TX_MPWQE);
2283 }
2284
2285 static u8 mlx5e_build_icosq_log_wq_sz(struct mlx5e_params *params,
2286                                       struct mlx5e_rq_param *rqp)
2287 {
2288         switch (params->rq_wq_type) {
2289         case MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ:
2290                 return order_base_2(MLX5E_UMR_WQEBBS) +
2291                         mlx5e_get_rq_log_wq_sz(rqp->rqc);
2292         default: /* MLX5_WQ_TYPE_CYCLIC */
2293                 return MLX5E_PARAMS_MINIMUM_LOG_SQ_SIZE;
2294         }
2295 }
2296
2297 static void mlx5e_build_channel_param(struct mlx5e_priv *priv,
2298                                       struct mlx5e_params *params,
2299                                       struct mlx5e_channel_param *cparam)
2300 {
2301         u8 icosq_log_wq_sz;
2302
2303         mlx5e_build_rq_param(priv, params, NULL, &cparam->rq);
2304
2305         icosq_log_wq_sz = mlx5e_build_icosq_log_wq_sz(params, &cparam->rq);
2306
2307         mlx5e_build_sq_param(priv, params, &cparam->sq);
2308         mlx5e_build_xdpsq_param(priv, params, &cparam->xdp_sq);
2309         mlx5e_build_icosq_param(priv, icosq_log_wq_sz, &cparam->icosq);
2310         mlx5e_build_rx_cq_param(priv, params, NULL, &cparam->rx_cq);
2311         mlx5e_build_tx_cq_param(priv, params, &cparam->tx_cq);
2312         mlx5e_build_ico_cq_param(priv, icosq_log_wq_sz, &cparam->icosq_cq);
2313 }
2314
2315 int mlx5e_open_channels(struct mlx5e_priv *priv,
2316                         struct mlx5e_channels *chs)
2317 {
2318         struct mlx5e_channel_param *cparam;
2319         int err = -ENOMEM;
2320         int i;
2321
2322         chs->num = chs->params.num_channels;
2323
2324         chs->c = kcalloc(chs->num, sizeof(struct mlx5e_channel *), GFP_KERNEL);
2325         cparam = kvzalloc(sizeof(struct mlx5e_channel_param), GFP_KERNEL);
2326         if (!chs->c || !cparam)
2327                 goto err_free;
2328
2329         mlx5e_build_channel_param(priv, &chs->params, cparam);
2330         for (i = 0; i < chs->num; i++) {
2331                 struct xdp_umem *umem = NULL;
2332
2333                 if (chs->params.xdp_prog)
2334                         umem = mlx5e_xsk_get_umem(&chs->params, chs->params.xsk, i);
2335
2336                 err = mlx5e_open_channel(priv, i, &chs->params, cparam, umem, &chs->c[i]);
2337                 if (err)
2338                         goto err_close_channels;
2339         }
2340
2341         mlx5e_health_channels_update(priv);
2342         kvfree(cparam);
2343         return 0;
2344
2345 err_close_channels:
2346         for (i--; i >= 0; i--)
2347                 mlx5e_close_channel(chs->c[i]);
2348
2349 err_free:
2350         kfree(chs->c);
2351         kvfree(cparam);
2352         chs->num = 0;
2353         return err;
2354 }
2355
2356 static void mlx5e_activate_channels(struct mlx5e_channels *chs)
2357 {
2358         int i;
2359
2360         for (i = 0; i < chs->num; i++)
2361                 mlx5e_activate_channel(chs->c[i]);
2362 }
2363
2364 #define MLX5E_RQ_WQES_TIMEOUT 20000 /* msecs */
2365
2366 static int mlx5e_wait_channels_min_rx_wqes(struct mlx5e_channels *chs)
2367 {
2368         int err = 0;
2369         int i;
2370
2371         for (i = 0; i < chs->num; i++) {
2372                 int timeout = err ? 0 : MLX5E_RQ_WQES_TIMEOUT;
2373
2374                 err |= mlx5e_wait_for_min_rx_wqes(&chs->c[i]->rq, timeout);
2375
2376                 /* Don't wait on the XSK RQ, because the newer xdpsock sample
2377                  * doesn't provide any Fill Ring entries at the setup stage.
2378                  */
2379         }
2380
2381         return err ? -ETIMEDOUT : 0;
2382 }
2383
2384 static void mlx5e_deactivate_channels(struct mlx5e_channels *chs)
2385 {
2386         int i;
2387
2388         for (i = 0; i < chs->num; i++)
2389                 mlx5e_deactivate_channel(chs->c[i]);
2390 }
2391
2392 void mlx5e_close_channels(struct mlx5e_channels *chs)
2393 {
2394         int i;
2395
2396         for (i = 0; i < chs->num; i++)
2397                 mlx5e_close_channel(chs->c[i]);
2398
2399         kfree(chs->c);
2400         chs->num = 0;
2401 }
2402
2403 static int
2404 mlx5e_create_rqt(struct mlx5e_priv *priv, int sz, struct mlx5e_rqt *rqt)
2405 {
2406         struct mlx5_core_dev *mdev = priv->mdev;
2407         void *rqtc;
2408         int inlen;
2409         int err;
2410         u32 *in;
2411         int i;
2412
2413         inlen = MLX5_ST_SZ_BYTES(create_rqt_in) + sizeof(u32) * sz;
2414         in = kvzalloc(inlen, GFP_KERNEL);
2415         if (!in)
2416                 return -ENOMEM;
2417
2418         rqtc = MLX5_ADDR_OF(create_rqt_in, in, rqt_context);
2419
2420         MLX5_SET(rqtc, rqtc, rqt_actual_size, sz);
2421         MLX5_SET(rqtc, rqtc, rqt_max_size, sz);
2422
2423         for (i = 0; i < sz; i++)
2424                 MLX5_SET(rqtc, rqtc, rq_num[i], priv->drop_rq.rqn);
2425
2426         err = mlx5_core_create_rqt(mdev, in, inlen, &rqt->rqtn);
2427         if (!err)
2428                 rqt->enabled = true;
2429
2430         kvfree(in);
2431         return err;
2432 }
2433
2434 void mlx5e_destroy_rqt(struct mlx5e_priv *priv, struct mlx5e_rqt *rqt)
2435 {
2436         rqt->enabled = false;
2437         mlx5_core_destroy_rqt(priv->mdev, rqt->rqtn);
2438 }
2439
2440 int mlx5e_create_indirect_rqt(struct mlx5e_priv *priv)
2441 {
2442         struct mlx5e_rqt *rqt = &priv->indir_rqt;
2443         int err;
2444
2445         err = mlx5e_create_rqt(priv, MLX5E_INDIR_RQT_SIZE, rqt);
2446         if (err)
2447                 mlx5_core_warn(priv->mdev, "create indirect rqts failed, %d\n", err);
2448         return err;
2449 }
2450
2451 int mlx5e_create_direct_rqts(struct mlx5e_priv *priv, struct mlx5e_tir *tirs)
2452 {
2453         int err;
2454         int ix;
2455
2456         for (ix = 0; ix < priv->max_nch; ix++) {
2457                 err = mlx5e_create_rqt(priv, 1 /*size */, &tirs[ix].rqt);
2458                 if (unlikely(err))
2459                         goto err_destroy_rqts;
2460         }
2461
2462         return 0;
2463
2464 err_destroy_rqts:
2465         mlx5_core_warn(priv->mdev, "create rqts failed, %d\n", err);
2466         for (ix--; ix >= 0; ix--)
2467                 mlx5e_destroy_rqt(priv, &tirs[ix].rqt);
2468
2469         return err;
2470 }
2471
2472 void mlx5e_destroy_direct_rqts(struct mlx5e_priv *priv, struct mlx5e_tir *tirs)
2473 {
2474         int i;
2475
2476         for (i = 0; i < priv->max_nch; i++)
2477                 mlx5e_destroy_rqt(priv, &tirs[i].rqt);
2478 }
2479
2480 static int mlx5e_rx_hash_fn(int hfunc)
2481 {
2482         return (hfunc == ETH_RSS_HASH_TOP) ?
2483                MLX5_RX_HASH_FN_TOEPLITZ :
2484                MLX5_RX_HASH_FN_INVERTED_XOR8;
2485 }
2486
2487 int mlx5e_bits_invert(unsigned long a, int size)
2488 {
2489         int inv = 0;
2490         int i;
2491
2492         for (i = 0; i < size; i++)
2493                 inv |= (test_bit(size - i - 1, &a) ? 1 : 0) << i;
2494
2495         return inv;
2496 }
2497
2498 static void mlx5e_fill_rqt_rqns(struct mlx5e_priv *priv, int sz,
2499                                 struct mlx5e_redirect_rqt_param rrp, void *rqtc)
2500 {
2501         int i;
2502
2503         for (i = 0; i < sz; i++) {
2504                 u32 rqn;
2505
2506                 if (rrp.is_rss) {
2507                         int ix = i;
2508
2509                         if (rrp.rss.hfunc == ETH_RSS_HASH_XOR)
2510                                 ix = mlx5e_bits_invert(i, ilog2(sz));
2511
2512                         ix = priv->rss_params.indirection_rqt[ix];
2513                         rqn = rrp.rss.channels->c[ix]->rq.rqn;
2514                 } else {
2515                         rqn = rrp.rqn;
2516                 }
2517                 MLX5_SET(rqtc, rqtc, rq_num[i], rqn);
2518         }
2519 }
2520
2521 int mlx5e_redirect_rqt(struct mlx5e_priv *priv, u32 rqtn, int sz,
2522                        struct mlx5e_redirect_rqt_param rrp)
2523 {
2524         struct mlx5_core_dev *mdev = priv->mdev;
2525         void *rqtc;
2526         int inlen;
2527         u32 *in;
2528         int err;
2529
2530         inlen = MLX5_ST_SZ_BYTES(modify_rqt_in) + sizeof(u32) * sz;
2531         in = kvzalloc(inlen, GFP_KERNEL);
2532         if (!in)
2533                 return -ENOMEM;
2534
2535         rqtc = MLX5_ADDR_OF(modify_rqt_in, in, ctx);
2536
2537         MLX5_SET(rqtc, rqtc, rqt_actual_size, sz);
2538         MLX5_SET(modify_rqt_in, in, bitmask.rqn_list, 1);
2539         mlx5e_fill_rqt_rqns(priv, sz, rrp, rqtc);
2540         err = mlx5_core_modify_rqt(mdev, rqtn, in, inlen);
2541
2542         kvfree(in);
2543         return err;
2544 }
2545
2546 static u32 mlx5e_get_direct_rqn(struct mlx5e_priv *priv, int ix,
2547                                 struct mlx5e_redirect_rqt_param rrp)
2548 {
2549         if (!rrp.is_rss)
2550                 return rrp.rqn;
2551
2552         if (ix >= rrp.rss.channels->num)
2553                 return priv->drop_rq.rqn;
2554
2555         return rrp.rss.channels->c[ix]->rq.rqn;
2556 }
2557
2558 static void mlx5e_redirect_rqts(struct mlx5e_priv *priv,
2559                                 struct mlx5e_redirect_rqt_param rrp)
2560 {
2561         u32 rqtn;
2562         int ix;
2563
2564         if (priv->indir_rqt.enabled) {
2565                 /* RSS RQ table */
2566                 rqtn = priv->indir_rqt.rqtn;
2567                 mlx5e_redirect_rqt(priv, rqtn, MLX5E_INDIR_RQT_SIZE, rrp);
2568         }
2569
2570         for (ix = 0; ix < priv->max_nch; ix++) {
2571                 struct mlx5e_redirect_rqt_param direct_rrp = {
2572                         .is_rss = false,
2573                         {
2574                                 .rqn    = mlx5e_get_direct_rqn(priv, ix, rrp)
2575                         },
2576                 };
2577
2578                 /* Direct RQ Tables */
2579                 if (!priv->direct_tir[ix].rqt.enabled)
2580                         continue;
2581
2582                 rqtn = priv->direct_tir[ix].rqt.rqtn;
2583                 mlx5e_redirect_rqt(priv, rqtn, 1, direct_rrp);
2584         }
2585 }
2586
2587 static void mlx5e_redirect_rqts_to_channels(struct mlx5e_priv *priv,
2588                                             struct mlx5e_channels *chs)
2589 {
2590         struct mlx5e_redirect_rqt_param rrp = {
2591                 .is_rss        = true,
2592                 {
2593                         .rss = {
2594                                 .channels  = chs,
2595                                 .hfunc     = priv->rss_params.hfunc,
2596                         }
2597                 },
2598         };
2599
2600         mlx5e_redirect_rqts(priv, rrp);
2601 }
2602
2603 static void mlx5e_redirect_rqts_to_drop(struct mlx5e_priv *priv)
2604 {
2605         struct mlx5e_redirect_rqt_param drop_rrp = {
2606                 .is_rss = false,
2607                 {
2608                         .rqn = priv->drop_rq.rqn,
2609                 },
2610         };
2611
2612         mlx5e_redirect_rqts(priv, drop_rrp);
2613 }
2614
2615 static const struct mlx5e_tirc_config tirc_default_config[MLX5E_NUM_INDIR_TIRS] = {
2616         [MLX5E_TT_IPV4_TCP] = { .l3_prot_type = MLX5_L3_PROT_TYPE_IPV4,
2617                                 .l4_prot_type = MLX5_L4_PROT_TYPE_TCP,
2618                                 .rx_hash_fields = MLX5_HASH_IP_L4PORTS,
2619         },
2620         [MLX5E_TT_IPV6_TCP] = { .l3_prot_type = MLX5_L3_PROT_TYPE_IPV6,
2621                                 .l4_prot_type = MLX5_L4_PROT_TYPE_TCP,
2622                                 .rx_hash_fields = MLX5_HASH_IP_L4PORTS,
2623         },
2624         [MLX5E_TT_IPV4_UDP] = { .l3_prot_type = MLX5_L3_PROT_TYPE_IPV4,
2625                                 .l4_prot_type = MLX5_L4_PROT_TYPE_UDP,
2626                                 .rx_hash_fields = MLX5_HASH_IP_L4PORTS,
2627         },
2628         [MLX5E_TT_IPV6_UDP] = { .l3_prot_type = MLX5_L3_PROT_TYPE_IPV6,
2629                                 .l4_prot_type = MLX5_L4_PROT_TYPE_UDP,
2630                                 .rx_hash_fields = MLX5_HASH_IP_L4PORTS,
2631         },
2632         [MLX5E_TT_IPV4_IPSEC_AH] = { .l3_prot_type = MLX5_L3_PROT_TYPE_IPV4,
2633                                      .l4_prot_type = 0,
2634                                      .rx_hash_fields = MLX5_HASH_IP_IPSEC_SPI,
2635         },
2636         [MLX5E_TT_IPV6_IPSEC_AH] = { .l3_prot_type = MLX5_L3_PROT_TYPE_IPV6,
2637                                      .l4_prot_type = 0,
2638                                      .rx_hash_fields = MLX5_HASH_IP_IPSEC_SPI,
2639         },
2640         [MLX5E_TT_IPV4_IPSEC_ESP] = { .l3_prot_type = MLX5_L3_PROT_TYPE_IPV4,
2641                                       .l4_prot_type = 0,
2642                                       .rx_hash_fields = MLX5_HASH_IP_IPSEC_SPI,
2643         },
2644         [MLX5E_TT_IPV6_IPSEC_ESP] = { .l3_prot_type = MLX5_L3_PROT_TYPE_IPV6,
2645                                       .l4_prot_type = 0,
2646                                       .rx_hash_fields = MLX5_HASH_IP_IPSEC_SPI,
2647         },
2648         [MLX5E_TT_IPV4] = { .l3_prot_type = MLX5_L3_PROT_TYPE_IPV4,
2649                             .l4_prot_type = 0,
2650                             .rx_hash_fields = MLX5_HASH_IP,
2651         },
2652         [MLX5E_TT_IPV6] = { .l3_prot_type = MLX5_L3_PROT_TYPE_IPV6,
2653                             .l4_prot_type = 0,
2654                             .rx_hash_fields = MLX5_HASH_IP,
2655         },
2656 };
2657
2658 struct mlx5e_tirc_config mlx5e_tirc_get_default_config(enum mlx5e_traffic_types tt)
2659 {
2660         return tirc_default_config[tt];
2661 }
2662
2663 static void mlx5e_build_tir_ctx_lro(struct mlx5e_params *params, void *tirc)
2664 {
2665         if (!params->lro_en)
2666                 return;
2667
2668 #define ROUGH_MAX_L2_L3_HDR_SZ 256
2669
2670         MLX5_SET(tirc, tirc, lro_enable_mask,
2671                  MLX5_TIRC_LRO_ENABLE_MASK_IPV4_LRO |
2672                  MLX5_TIRC_LRO_ENABLE_MASK_IPV6_LRO);
2673         MLX5_SET(tirc, tirc, lro_max_ip_payload_size,
2674                  (MLX5E_PARAMS_DEFAULT_LRO_WQE_SZ - ROUGH_MAX_L2_L3_HDR_SZ) >> 8);
2675         MLX5_SET(tirc, tirc, lro_timeout_period_usecs, params->lro_timeout);
2676 }
2677
2678 void mlx5e_build_indir_tir_ctx_hash(struct mlx5e_rss_params *rss_params,
2679                                     const struct mlx5e_tirc_config *ttconfig,
2680                                     void *tirc, bool inner)
2681 {
2682         void *hfso = inner ? MLX5_ADDR_OF(tirc, tirc, rx_hash_field_selector_inner) :
2683                              MLX5_ADDR_OF(tirc, tirc, rx_hash_field_selector_outer);
2684
2685         MLX5_SET(tirc, tirc, rx_hash_fn, mlx5e_rx_hash_fn(rss_params->hfunc));
2686         if (rss_params->hfunc == ETH_RSS_HASH_TOP) {
2687                 void *rss_key = MLX5_ADDR_OF(tirc, tirc,
2688                                              rx_hash_toeplitz_key);
2689                 size_t len = MLX5_FLD_SZ_BYTES(tirc,
2690                                                rx_hash_toeplitz_key);
2691
2692                 MLX5_SET(tirc, tirc, rx_hash_symmetric, 1);
2693                 memcpy(rss_key, rss_params->toeplitz_hash_key, len);
2694         }
2695         MLX5_SET(rx_hash_field_select, hfso, l3_prot_type,
2696                  ttconfig->l3_prot_type);
2697         MLX5_SET(rx_hash_field_select, hfso, l4_prot_type,
2698                  ttconfig->l4_prot_type);
2699         MLX5_SET(rx_hash_field_select, hfso, selected_fields,
2700                  ttconfig->rx_hash_fields);
2701 }
2702
2703 static void mlx5e_update_rx_hash_fields(struct mlx5e_tirc_config *ttconfig,
2704                                         enum mlx5e_traffic_types tt,
2705                                         u32 rx_hash_fields)
2706 {
2707         *ttconfig                = tirc_default_config[tt];
2708         ttconfig->rx_hash_fields = rx_hash_fields;
2709 }
2710
2711 void mlx5e_modify_tirs_hash(struct mlx5e_priv *priv, void *in, int inlen)
2712 {
2713         void *tirc = MLX5_ADDR_OF(modify_tir_in, in, ctx);
2714         struct mlx5e_rss_params *rss = &priv->rss_params;
2715         struct mlx5_core_dev *mdev = priv->mdev;
2716         int ctxlen = MLX5_ST_SZ_BYTES(tirc);
2717         struct mlx5e_tirc_config ttconfig;
2718         int tt;
2719
2720         MLX5_SET(modify_tir_in, in, bitmask.hash, 1);
2721
2722         for (tt = 0; tt < MLX5E_NUM_INDIR_TIRS; tt++) {
2723                 memset(tirc, 0, ctxlen);
2724                 mlx5e_update_rx_hash_fields(&ttconfig, tt,
2725                                             rss->rx_hash_fields[tt]);
2726                 mlx5e_build_indir_tir_ctx_hash(rss, &ttconfig, tirc, false);
2727                 mlx5_core_modify_tir(mdev, priv->indir_tir[tt].tirn, in, inlen);
2728         }
2729
2730         if (!mlx5e_tunnel_inner_ft_supported(priv->mdev))
2731                 return;
2732
2733         for (tt = 0; tt < MLX5E_NUM_INDIR_TIRS; tt++) {
2734                 memset(tirc, 0, ctxlen);
2735                 mlx5e_update_rx_hash_fields(&ttconfig, tt,
2736                                             rss->rx_hash_fields[tt]);
2737                 mlx5e_build_indir_tir_ctx_hash(rss, &ttconfig, tirc, true);
2738                 mlx5_core_modify_tir(mdev, priv->inner_indir_tir[tt].tirn, in,
2739                                      inlen);
2740         }
2741 }
2742
2743 static int mlx5e_modify_tirs_lro(struct mlx5e_priv *priv)
2744 {
2745         struct mlx5_core_dev *mdev = priv->mdev;
2746
2747         void *in;
2748         void *tirc;
2749         int inlen;
2750         int err;
2751         int tt;
2752         int ix;
2753
2754         inlen = MLX5_ST_SZ_BYTES(modify_tir_in);
2755         in = kvzalloc(inlen, GFP_KERNEL);
2756         if (!in)
2757                 return -ENOMEM;
2758
2759         MLX5_SET(modify_tir_in, in, bitmask.lro, 1);
2760         tirc = MLX5_ADDR_OF(modify_tir_in, in, ctx);
2761
2762         mlx5e_build_tir_ctx_lro(&priv->channels.params, tirc);
2763
2764         for (tt = 0; tt < MLX5E_NUM_INDIR_TIRS; tt++) {
2765                 err = mlx5_core_modify_tir(mdev, priv->indir_tir[tt].tirn, in,
2766                                            inlen);
2767                 if (err)
2768                         goto free_in;
2769         }
2770
2771         for (ix = 0; ix < priv->max_nch; ix++) {
2772                 err = mlx5_core_modify_tir(mdev, priv->direct_tir[ix].tirn,
2773                                            in, inlen);
2774                 if (err)
2775                         goto free_in;
2776         }
2777
2778 free_in:
2779         kvfree(in);
2780
2781         return err;
2782 }
2783
2784 static int mlx5e_set_mtu(struct mlx5_core_dev *mdev,
2785                          struct mlx5e_params *params, u16 mtu)
2786 {
2787         u16 hw_mtu = MLX5E_SW2HW_MTU(params, mtu);
2788         int err;
2789
2790         err = mlx5_set_port_mtu(mdev, hw_mtu, 1);
2791         if (err)
2792                 return err;
2793
2794         /* Update vport context MTU */
2795         mlx5_modify_nic_vport_mtu(mdev, hw_mtu);
2796         return 0;
2797 }
2798
2799 static void mlx5e_query_mtu(struct mlx5_core_dev *mdev,
2800                             struct mlx5e_params *params, u16 *mtu)
2801 {
2802         u16 hw_mtu = 0;
2803         int err;
2804
2805         err = mlx5_query_nic_vport_mtu(mdev, &hw_mtu);
2806         if (err || !hw_mtu) /* fallback to port oper mtu */
2807                 mlx5_query_port_oper_mtu(mdev, &hw_mtu, 1);
2808
2809         *mtu = MLX5E_HW2SW_MTU(params, hw_mtu);
2810 }
2811
2812 int mlx5e_set_dev_port_mtu(struct mlx5e_priv *priv)
2813 {
2814         struct mlx5e_params *params = &priv->channels.params;
2815         struct net_device *netdev = priv->netdev;
2816         struct mlx5_core_dev *mdev = priv->mdev;
2817         u16 mtu;
2818         int err;
2819
2820         err = mlx5e_set_mtu(mdev, params, params->sw_mtu);
2821         if (err)
2822                 return err;
2823
2824         mlx5e_query_mtu(mdev, params, &mtu);
2825         if (mtu != params->sw_mtu)
2826                 netdev_warn(netdev, "%s: VPort MTU %d is different than netdev mtu %d\n",
2827                             __func__, mtu, params->sw_mtu);
2828
2829         params->sw_mtu = mtu;
2830         return 0;
2831 }
2832
2833 void mlx5e_set_netdev_mtu_boundaries(struct mlx5e_priv *priv)
2834 {
2835         struct mlx5e_params *params = &priv->channels.params;
2836         struct net_device *netdev   = priv->netdev;
2837         struct mlx5_core_dev *mdev  = priv->mdev;
2838         u16 max_mtu;
2839
2840         /* MTU range: 68 - hw-specific max */
2841         netdev->min_mtu = ETH_MIN_MTU;
2842
2843         mlx5_query_port_max_mtu(mdev, &max_mtu, 1);
2844         netdev->max_mtu = min_t(unsigned int, MLX5E_HW2SW_MTU(params, max_mtu),
2845                                 ETH_MAX_MTU);
2846 }
2847
2848 static void mlx5e_netdev_set_tcs(struct net_device *netdev)
2849 {
2850         struct mlx5e_priv *priv = netdev_priv(netdev);
2851         int nch = priv->channels.params.num_channels;
2852         int ntc = priv->channels.params.num_tc;
2853         int tc;
2854
2855         netdev_reset_tc(netdev);
2856
2857         if (ntc == 1)
2858                 return;
2859
2860         netdev_set_num_tc(netdev, ntc);
2861
2862         /* Map netdev TCs to offset 0
2863          * We have our own UP to TXQ mapping for QoS
2864          */
2865         for (tc = 0; tc < ntc; tc++)
2866                 netdev_set_tc_queue(netdev, tc, nch, 0);
2867 }
2868
2869 static void mlx5e_build_txq_maps(struct mlx5e_priv *priv)
2870 {
2871         int i, ch;
2872
2873         ch = priv->channels.num;
2874
2875         for (i = 0; i < ch; i++) {
2876                 int tc;
2877
2878                 for (tc = 0; tc < priv->channels.params.num_tc; tc++) {
2879                         struct mlx5e_channel *c = priv->channels.c[i];
2880                         struct mlx5e_txqsq *sq = &c->sq[tc];
2881
2882                         priv->txq2sq[sq->txq_ix] = sq;
2883                         priv->channel_tc2realtxq[i][tc] = i + tc * ch;
2884                 }
2885         }
2886 }
2887
2888 void mlx5e_activate_priv_channels(struct mlx5e_priv *priv)
2889 {
2890         int num_txqs = priv->channels.num * priv->channels.params.num_tc;
2891         int num_rxqs = priv->channels.num * priv->profile->rq_groups;
2892         struct net_device *netdev = priv->netdev;
2893
2894         mlx5e_netdev_set_tcs(netdev);
2895         netif_set_real_num_tx_queues(netdev, num_txqs);
2896         netif_set_real_num_rx_queues(netdev, num_rxqs);
2897
2898         mlx5e_build_txq_maps(priv);
2899         mlx5e_activate_channels(&priv->channels);
2900         mlx5e_xdp_tx_enable(priv);
2901         netif_tx_start_all_queues(priv->netdev);
2902
2903         if (mlx5e_is_vport_rep(priv))
2904                 mlx5e_add_sqs_fwd_rules(priv);
2905
2906         mlx5e_wait_channels_min_rx_wqes(&priv->channels);
2907         mlx5e_redirect_rqts_to_channels(priv, &priv->channels);
2908
2909         mlx5e_xsk_redirect_rqts_to_channels(priv, &priv->channels);
2910 }
2911
2912 void mlx5e_deactivate_priv_channels(struct mlx5e_priv *priv)
2913 {
2914         mlx5e_xsk_redirect_rqts_to_drop(priv, &priv->channels);
2915
2916         mlx5e_redirect_rqts_to_drop(priv);
2917
2918         if (mlx5e_is_vport_rep(priv))
2919                 mlx5e_remove_sqs_fwd_rules(priv);
2920
2921         /* FIXME: This is a W/A only for tx timeout watch dog false alarm when
2922          * polling for inactive tx queues.
2923          */
2924         netif_tx_stop_all_queues(priv->netdev);
2925         netif_tx_disable(priv->netdev);
2926         mlx5e_xdp_tx_disable(priv);
2927         mlx5e_deactivate_channels(&priv->channels);
2928 }
2929
2930 static void mlx5e_switch_priv_channels(struct mlx5e_priv *priv,
2931                                        struct mlx5e_channels *new_chs,
2932                                        mlx5e_fp_hw_modify hw_modify)
2933 {
2934         struct net_device *netdev = priv->netdev;
2935         int new_num_txqs;
2936         int carrier_ok;
2937
2938         new_num_txqs = new_chs->num * new_chs->params.num_tc;
2939
2940         carrier_ok = netif_carrier_ok(netdev);
2941         netif_carrier_off(netdev);
2942
2943         if (new_num_txqs < netdev->real_num_tx_queues)
2944                 netif_set_real_num_tx_queues(netdev, new_num_txqs);
2945
2946         mlx5e_deactivate_priv_channels(priv);
2947         mlx5e_close_channels(&priv->channels);
2948
2949         priv->channels = *new_chs;
2950
2951         /* New channels are ready to roll, modify HW settings if needed */
2952         if (hw_modify)
2953                 hw_modify(priv);
2954
2955         priv->profile->update_rx(priv);
2956         mlx5e_activate_priv_channels(priv);
2957
2958         /* return carrier back if needed */
2959         if (carrier_ok)
2960                 netif_carrier_on(netdev);
2961 }
2962
2963 int mlx5e_safe_switch_channels(struct mlx5e_priv *priv,
2964                                struct mlx5e_channels *new_chs,
2965                                mlx5e_fp_hw_modify hw_modify)
2966 {
2967         int err;
2968
2969         err = mlx5e_open_channels(priv, new_chs);
2970         if (err)
2971                 return err;
2972
2973         mlx5e_switch_priv_channels(priv, new_chs, hw_modify);
2974         return 0;
2975 }
2976
2977 int mlx5e_safe_reopen_channels(struct mlx5e_priv *priv)
2978 {
2979         struct mlx5e_channels new_channels = {};
2980
2981         new_channels.params = priv->channels.params;
2982         return mlx5e_safe_switch_channels(priv, &new_channels, NULL);
2983 }
2984
2985 void mlx5e_timestamp_init(struct mlx5e_priv *priv)
2986 {
2987         priv->tstamp.tx_type   = HWTSTAMP_TX_OFF;
2988         priv->tstamp.rx_filter = HWTSTAMP_FILTER_NONE;
2989 }
2990
2991 int mlx5e_open_locked(struct net_device *netdev)
2992 {
2993         struct mlx5e_priv *priv = netdev_priv(netdev);
2994         int err;
2995
2996         set_bit(MLX5E_STATE_OPENED, &priv->state);
2997
2998         err = mlx5e_open_channels(priv, &priv->channels);
2999         if (err)
3000                 goto err_clear_state_opened_flag;
3001
3002         priv->profile->update_rx(priv);
3003         mlx5e_activate_priv_channels(priv);
3004         if (priv->profile->update_carrier)
3005                 priv->profile->update_carrier(priv);
3006
3007         mlx5e_queue_update_stats(priv);
3008         return 0;
3009
3010 err_clear_state_opened_flag:
3011         clear_bit(MLX5E_STATE_OPENED, &priv->state);
3012         return err;
3013 }
3014
3015 int mlx5e_open(struct net_device *netdev)
3016 {
3017         struct mlx5e_priv *priv = netdev_priv(netdev);
3018         int err;
3019
3020         mutex_lock(&priv->state_lock);
3021         err = mlx5e_open_locked(netdev);
3022         if (!err)
3023                 mlx5_set_port_admin_status(priv->mdev, MLX5_PORT_UP);
3024         mutex_unlock(&priv->state_lock);
3025
3026         if (mlx5_vxlan_allowed(priv->mdev->vxlan))
3027                 udp_tunnel_get_rx_info(netdev);
3028
3029         return err;
3030 }
3031
3032 int mlx5e_close_locked(struct net_device *netdev)
3033 {
3034         struct mlx5e_priv *priv = netdev_priv(netdev);
3035
3036         /* May already be CLOSED in case a previous configuration operation
3037          * (e.g RX/TX queue size change) that involves close&open failed.
3038          */
3039         if (!test_bit(MLX5E_STATE_OPENED, &priv->state))
3040                 return 0;
3041
3042         clear_bit(MLX5E_STATE_OPENED, &priv->state);
3043
3044         netif_carrier_off(priv->netdev);
3045         mlx5e_deactivate_priv_channels(priv);
3046         mlx5e_close_channels(&priv->channels);
3047
3048         return 0;
3049 }
3050
3051 int mlx5e_close(struct net_device *netdev)
3052 {
3053         struct mlx5e_priv *priv = netdev_priv(netdev);
3054         int err;
3055
3056         if (!netif_device_present(netdev))
3057                 return -ENODEV;
3058
3059         mutex_lock(&priv->state_lock);
3060         mlx5_set_port_admin_status(priv->mdev, MLX5_PORT_DOWN);
3061         err = mlx5e_close_locked(netdev);
3062         mutex_unlock(&priv->state_lock);
3063
3064         return err;
3065 }
3066
3067 static int mlx5e_alloc_drop_rq(struct mlx5_core_dev *mdev,
3068                                struct mlx5e_rq *rq,
3069                                struct mlx5e_rq_param *param)
3070 {
3071         void *rqc = param->rqc;
3072         void *rqc_wq = MLX5_ADDR_OF(rqc, rqc, wq);
3073         int err;
3074
3075         param->wq.db_numa_node = param->wq.buf_numa_node;
3076
3077         err = mlx5_wq_cyc_create(mdev, &param->wq, rqc_wq, &rq->wqe.wq,
3078                                  &rq->wq_ctrl);
3079         if (err)
3080                 return err;
3081
3082         /* Mark as unused given "Drop-RQ" packets never reach XDP */
3083         xdp_rxq_info_unused(&rq->xdp_rxq);
3084
3085         rq->mdev = mdev;
3086
3087         return 0;
3088 }
3089
3090 static int mlx5e_alloc_drop_cq(struct mlx5_core_dev *mdev,
3091                                struct mlx5e_cq *cq,
3092                                struct mlx5e_cq_param *param)
3093 {
3094         param->wq.buf_numa_node = dev_to_node(mdev->device);
3095         param->wq.db_numa_node  = dev_to_node(mdev->device);
3096
3097         return mlx5e_alloc_cq_common(mdev, param, cq);
3098 }
3099
3100 int mlx5e_open_drop_rq(struct mlx5e_priv *priv,
3101                        struct mlx5e_rq *drop_rq)
3102 {
3103         struct mlx5_core_dev *mdev = priv->mdev;
3104         struct mlx5e_cq_param cq_param = {};
3105         struct mlx5e_rq_param rq_param = {};
3106         struct mlx5e_cq *cq = &drop_rq->cq;
3107         int err;
3108
3109         mlx5e_build_drop_rq_param(priv, &rq_param);
3110
3111         err = mlx5e_alloc_drop_cq(mdev, cq, &cq_param);
3112         if (err)
3113                 return err;
3114
3115         err = mlx5e_create_cq(cq, &cq_param);
3116         if (err)
3117                 goto err_free_cq;
3118
3119         err = mlx5e_alloc_drop_rq(mdev, drop_rq, &rq_param);
3120         if (err)
3121                 goto err_destroy_cq;
3122
3123         err = mlx5e_create_rq(drop_rq, &rq_param);
3124         if (err)
3125                 goto err_free_rq;
3126
3127         err = mlx5e_modify_rq_state(drop_rq, MLX5_RQC_STATE_RST, MLX5_RQC_STATE_RDY);
3128         if (err)
3129                 mlx5_core_warn(priv->mdev, "modify_rq_state failed, rx_if_down_packets won't be counted %d\n", err);
3130
3131         return 0;
3132
3133 err_free_rq:
3134         mlx5e_free_rq(drop_rq);
3135
3136 err_destroy_cq:
3137         mlx5e_destroy_cq(cq);
3138
3139 err_free_cq:
3140         mlx5e_free_cq(cq);
3141
3142         return err;
3143 }
3144
3145 void mlx5e_close_drop_rq(struct mlx5e_rq *drop_rq)
3146 {
3147         mlx5e_destroy_rq(drop_rq);
3148         mlx5e_free_rq(drop_rq);
3149         mlx5e_destroy_cq(&drop_rq->cq);
3150         mlx5e_free_cq(&drop_rq->cq);
3151 }
3152
3153 int mlx5e_create_tis(struct mlx5_core_dev *mdev, void *in, u32 *tisn)
3154 {
3155         void *tisc = MLX5_ADDR_OF(create_tis_in, in, ctx);
3156
3157         MLX5_SET(tisc, tisc, transport_domain, mdev->mlx5e_res.td.tdn);
3158
3159         if (MLX5_GET(tisc, tisc, tls_en))
3160                 MLX5_SET(tisc, tisc, pd, mdev->mlx5e_res.pdn);
3161
3162         if (mlx5_lag_is_lacp_owner(mdev))
3163                 MLX5_SET(tisc, tisc, strict_lag_tx_port_affinity, 1);
3164
3165         return mlx5_core_create_tis(mdev, in, MLX5_ST_SZ_BYTES(create_tis_in), tisn);
3166 }
3167
3168 void mlx5e_destroy_tis(struct mlx5_core_dev *mdev, u32 tisn)
3169 {
3170         mlx5_core_destroy_tis(mdev, tisn);
3171 }
3172
3173 void mlx5e_destroy_tises(struct mlx5e_priv *priv)
3174 {
3175         int tc, i;
3176
3177         for (i = 0; i < mlx5e_get_num_lag_ports(priv->mdev); i++)
3178                 for (tc = 0; tc < priv->profile->max_tc; tc++)
3179                         mlx5e_destroy_tis(priv->mdev, priv->tisn[i][tc]);
3180 }
3181
3182 static bool mlx5e_lag_should_assign_affinity(struct mlx5_core_dev *mdev)
3183 {
3184         return MLX5_CAP_GEN(mdev, lag_tx_port_affinity) && mlx5e_get_num_lag_ports(mdev) > 1;
3185 }
3186
3187 int mlx5e_create_tises(struct mlx5e_priv *priv)
3188 {
3189         int tc, i;
3190         int err;
3191
3192         for (i = 0; i < mlx5e_get_num_lag_ports(priv->mdev); i++) {
3193                 for (tc = 0; tc < priv->profile->max_tc; tc++) {
3194                         u32 in[MLX5_ST_SZ_DW(create_tis_in)] = {};
3195                         void *tisc;
3196
3197                         tisc = MLX5_ADDR_OF(create_tis_in, in, ctx);
3198
3199                         MLX5_SET(tisc, tisc, prio, tc << 1);
3200
3201                         if (mlx5e_lag_should_assign_affinity(priv->mdev))
3202                                 MLX5_SET(tisc, tisc, lag_tx_port_affinity, i + 1);
3203
3204                         err = mlx5e_create_tis(priv->mdev, in, &priv->tisn[i][tc]);
3205                         if (err)
3206                                 goto err_close_tises;
3207                 }
3208         }
3209
3210         return 0;
3211
3212 err_close_tises:
3213         for (; i >= 0; i--) {
3214                 for (tc--; tc >= 0; tc--)
3215                         mlx5e_destroy_tis(priv->mdev, priv->tisn[i][tc]);
3216                 tc = priv->profile->max_tc;
3217         }
3218
3219         return err;
3220 }
3221
3222 static void mlx5e_cleanup_nic_tx(struct mlx5e_priv *priv)
3223 {
3224         mlx5e_destroy_tises(priv);
3225 }
3226
3227 static void mlx5e_build_indir_tir_ctx_common(struct mlx5e_priv *priv,
3228                                              u32 rqtn, u32 *tirc)
3229 {
3230         MLX5_SET(tirc, tirc, transport_domain, priv->mdev->mlx5e_res.td.tdn);
3231         MLX5_SET(tirc, tirc, disp_type, MLX5_TIRC_DISP_TYPE_INDIRECT);
3232         MLX5_SET(tirc, tirc, indirect_table, rqtn);
3233         MLX5_SET(tirc, tirc, tunneled_offload_en,
3234                  priv->channels.params.tunneled_offload_en);
3235
3236         mlx5e_build_tir_ctx_lro(&priv->channels.params, tirc);
3237 }
3238
3239 static void mlx5e_build_indir_tir_ctx(struct mlx5e_priv *priv,
3240                                       enum mlx5e_traffic_types tt,
3241                                       u32 *tirc)
3242 {
3243         mlx5e_build_indir_tir_ctx_common(priv, priv->indir_rqt.rqtn, tirc);
3244         mlx5e_build_indir_tir_ctx_hash(&priv->rss_params,
3245                                        &tirc_default_config[tt], tirc, false);
3246 }
3247
3248 static void mlx5e_build_direct_tir_ctx(struct mlx5e_priv *priv, u32 rqtn, u32 *tirc)
3249 {
3250         mlx5e_build_indir_tir_ctx_common(priv, rqtn, tirc);
3251         MLX5_SET(tirc, tirc, rx_hash_fn, MLX5_RX_HASH_FN_INVERTED_XOR8);
3252 }
3253
3254 static void mlx5e_build_inner_indir_tir_ctx(struct mlx5e_priv *priv,
3255                                             enum mlx5e_traffic_types tt,
3256                                             u32 *tirc)
3257 {
3258         mlx5e_build_indir_tir_ctx_common(priv, priv->indir_rqt.rqtn, tirc);
3259         mlx5e_build_indir_tir_ctx_hash(&priv->rss_params,
3260                                        &tirc_default_config[tt], tirc, true);
3261 }
3262
3263 int mlx5e_create_indirect_tirs(struct mlx5e_priv *priv, bool inner_ttc)
3264 {
3265         struct mlx5e_tir *tir;
3266         void *tirc;
3267         int inlen;
3268         int i = 0;
3269         int err;
3270         u32 *in;
3271         int tt;
3272
3273         inlen = MLX5_ST_SZ_BYTES(create_tir_in);
3274         in = kvzalloc(inlen, GFP_KERNEL);
3275         if (!in)
3276                 return -ENOMEM;
3277
3278         for (tt = 0; tt < MLX5E_NUM_INDIR_TIRS; tt++) {
3279                 memset(in, 0, inlen);
3280                 tir = &priv->indir_tir[tt];
3281                 tirc = MLX5_ADDR_OF(create_tir_in, in, ctx);
3282                 mlx5e_build_indir_tir_ctx(priv, tt, tirc);
3283                 err = mlx5e_create_tir(priv->mdev, tir, in, inlen);
3284                 if (err) {
3285                         mlx5_core_warn(priv->mdev, "create indirect tirs failed, %d\n", err);
3286                         goto err_destroy_inner_tirs;
3287                 }
3288         }
3289
3290         if (!inner_ttc || !mlx5e_tunnel_inner_ft_supported(priv->mdev))
3291                 goto out;
3292
3293         for (i = 0; i < MLX5E_NUM_INDIR_TIRS; i++) {
3294                 memset(in, 0, inlen);
3295                 tir = &priv->inner_indir_tir[i];
3296                 tirc = MLX5_ADDR_OF(create_tir_in, in, ctx);
3297                 mlx5e_build_inner_indir_tir_ctx(priv, i, tirc);
3298                 err = mlx5e_create_tir(priv->mdev, tir, in, inlen);
3299                 if (err) {
3300                         mlx5_core_warn(priv->mdev, "create inner indirect tirs failed, %d\n", err);
3301                         goto err_destroy_inner_tirs;
3302                 }
3303         }
3304
3305 out:
3306         kvfree(in);
3307
3308         return 0;
3309
3310 err_destroy_inner_tirs:
3311         for (i--; i >= 0; i--)
3312                 mlx5e_destroy_tir(priv->mdev, &priv->inner_indir_tir[i]);
3313
3314         for (tt--; tt >= 0; tt--)
3315                 mlx5e_destroy_tir(priv->mdev, &priv->indir_tir[tt]);
3316
3317         kvfree(in);
3318
3319         return err;
3320 }
3321
3322 int mlx5e_create_direct_tirs(struct mlx5e_priv *priv, struct mlx5e_tir *tirs)
3323 {
3324         struct mlx5e_tir *tir;
3325         void *tirc;
3326         int inlen;
3327         int err = 0;
3328         u32 *in;
3329         int ix;
3330
3331         inlen = MLX5_ST_SZ_BYTES(create_tir_in);
3332         in = kvzalloc(inlen, GFP_KERNEL);
3333         if (!in)
3334                 return -ENOMEM;
3335
3336         for (ix = 0; ix < priv->max_nch; ix++) {
3337                 memset(in, 0, inlen);
3338                 tir = &tirs[ix];
3339                 tirc = MLX5_ADDR_OF(create_tir_in, in, ctx);
3340                 mlx5e_build_direct_tir_ctx(priv, tir->rqt.rqtn, tirc);
3341                 err = mlx5e_create_tir(priv->mdev, tir, in, inlen);
3342                 if (unlikely(err))
3343                         goto err_destroy_ch_tirs;
3344         }
3345
3346         goto out;
3347
3348 err_destroy_ch_tirs:
3349         mlx5_core_warn(priv->mdev, "create tirs failed, %d\n", err);
3350         for (ix--; ix >= 0; ix--)
3351                 mlx5e_destroy_tir(priv->mdev, &tirs[ix]);
3352
3353 out:
3354         kvfree(in);
3355
3356         return err;
3357 }
3358
3359 void mlx5e_destroy_indirect_tirs(struct mlx5e_priv *priv, bool inner_ttc)
3360 {
3361         int i;
3362
3363         for (i = 0; i < MLX5E_NUM_INDIR_TIRS; i++)
3364                 mlx5e_destroy_tir(priv->mdev, &priv->indir_tir[i]);
3365
3366         if (!inner_ttc || !mlx5e_tunnel_inner_ft_supported(priv->mdev))
3367                 return;
3368
3369         for (i = 0; i < MLX5E_NUM_INDIR_TIRS; i++)
3370                 mlx5e_destroy_tir(priv->mdev, &priv->inner_indir_tir[i]);
3371 }
3372
3373 void mlx5e_destroy_direct_tirs(struct mlx5e_priv *priv, struct mlx5e_tir *tirs)
3374 {
3375         int i;
3376
3377         for (i = 0; i < priv->max_nch; i++)
3378                 mlx5e_destroy_tir(priv->mdev, &tirs[i]);
3379 }
3380
3381 static int mlx5e_modify_channels_scatter_fcs(struct mlx5e_channels *chs, bool enable)
3382 {
3383         int err = 0;
3384         int i;
3385
3386         for (i = 0; i < chs->num; i++) {
3387                 err = mlx5e_modify_rq_scatter_fcs(&chs->c[i]->rq, enable);
3388                 if (err)
3389                         return err;
3390         }
3391
3392         return 0;
3393 }
3394
3395 static int mlx5e_modify_channels_vsd(struct mlx5e_channels *chs, bool vsd)
3396 {
3397         int err = 0;
3398         int i;
3399
3400         for (i = 0; i < chs->num; i++) {
3401                 err = mlx5e_modify_rq_vsd(&chs->c[i]->rq, vsd);
3402                 if (err)
3403                         return err;
3404         }
3405
3406         return 0;
3407 }
3408
3409 static int mlx5e_setup_tc_mqprio(struct mlx5e_priv *priv,
3410                                  struct tc_mqprio_qopt *mqprio)
3411 {
3412         struct mlx5e_channels new_channels = {};
3413         u8 tc = mqprio->num_tc;
3414         int err = 0;
3415
3416         mqprio->hw = TC_MQPRIO_HW_OFFLOAD_TCS;
3417
3418         if (tc && tc != MLX5E_MAX_NUM_TC)
3419                 return -EINVAL;
3420
3421         mutex_lock(&priv->state_lock);
3422
3423         new_channels.params = priv->channels.params;
3424         new_channels.params.num_tc = tc ? tc : 1;
3425
3426         if (!test_bit(MLX5E_STATE_OPENED, &priv->state)) {
3427                 priv->channels.params = new_channels.params;
3428                 goto out;
3429         }
3430
3431         err = mlx5e_safe_switch_channels(priv, &new_channels, NULL);
3432         if (err)
3433                 goto out;
3434
3435         priv->max_opened_tc = max_t(u8, priv->max_opened_tc,
3436                                     new_channels.params.num_tc);
3437 out:
3438         mutex_unlock(&priv->state_lock);
3439         return err;
3440 }
3441
3442 #ifdef CONFIG_MLX5_ESWITCH
3443 static int mlx5e_setup_tc_cls_flower(struct mlx5e_priv *priv,
3444                                      struct flow_cls_offload *cls_flower,
3445                                      unsigned long flags)
3446 {
3447         switch (cls_flower->command) {
3448         case FLOW_CLS_REPLACE:
3449                 return mlx5e_configure_flower(priv->netdev, priv, cls_flower,
3450                                               flags);
3451         case FLOW_CLS_DESTROY:
3452                 return mlx5e_delete_flower(priv->netdev, priv, cls_flower,
3453                                            flags);
3454         case FLOW_CLS_STATS:
3455                 return mlx5e_stats_flower(priv->netdev, priv, cls_flower,
3456                                           flags);
3457         default:
3458                 return -EOPNOTSUPP;
3459         }
3460 }
3461
3462 static int mlx5e_setup_tc_block_cb(enum tc_setup_type type, void *type_data,
3463                                    void *cb_priv)
3464 {
3465         unsigned long flags = MLX5_TC_FLAG(INGRESS) | MLX5_TC_FLAG(NIC_OFFLOAD);
3466         struct mlx5e_priv *priv = cb_priv;
3467
3468         switch (type) {
3469         case TC_SETUP_CLSFLOWER:
3470                 return mlx5e_setup_tc_cls_flower(priv, type_data, flags);
3471         default:
3472                 return -EOPNOTSUPP;
3473         }
3474 }
3475 #endif
3476
3477 static LIST_HEAD(mlx5e_block_cb_list);
3478
3479 static int mlx5e_setup_tc(struct net_device *dev, enum tc_setup_type type,
3480                           void *type_data)
3481 {
3482         struct mlx5e_priv *priv = netdev_priv(dev);
3483
3484         switch (type) {
3485 #ifdef CONFIG_MLX5_ESWITCH
3486         case TC_SETUP_BLOCK: {
3487                 struct flow_block_offload *f = type_data;
3488
3489                 f->unlocked_driver_cb = true;
3490                 return flow_block_cb_setup_simple(type_data,
3491                                                   &mlx5e_block_cb_list,
3492                                                   mlx5e_setup_tc_block_cb,
3493                                                   priv, priv, true);
3494         }
3495 #endif
3496         case TC_SETUP_QDISC_MQPRIO:
3497                 return mlx5e_setup_tc_mqprio(priv, type_data);
3498         default:
3499                 return -EOPNOTSUPP;
3500         }
3501 }
3502
3503 void mlx5e_fold_sw_stats64(struct mlx5e_priv *priv, struct rtnl_link_stats64 *s)
3504 {
3505         int i;
3506
3507         for (i = 0; i < priv->max_nch; i++) {
3508                 struct mlx5e_channel_stats *channel_stats = &priv->channel_stats[i];
3509                 struct mlx5e_rq_stats *xskrq_stats = &channel_stats->xskrq;
3510                 struct mlx5e_rq_stats *rq_stats = &channel_stats->rq;
3511                 int j;
3512
3513                 s->rx_packets   += rq_stats->packets + xskrq_stats->packets;
3514                 s->rx_bytes     += rq_stats->bytes + xskrq_stats->bytes;
3515
3516                 for (j = 0; j < priv->max_opened_tc; j++) {
3517                         struct mlx5e_sq_stats *sq_stats = &channel_stats->sq[j];
3518
3519                         s->tx_packets    += sq_stats->packets;
3520                         s->tx_bytes      += sq_stats->bytes;
3521                         s->tx_dropped    += sq_stats->dropped;
3522                 }
3523         }
3524 }
3525
3526 void
3527 mlx5e_get_stats(struct net_device *dev, struct rtnl_link_stats64 *stats)
3528 {
3529         struct mlx5e_priv *priv = netdev_priv(dev);
3530         struct mlx5e_vport_stats *vstats = &priv->stats.vport;
3531         struct mlx5e_pport_stats *pstats = &priv->stats.pport;
3532
3533         if (!mlx5e_monitor_counter_supported(priv)) {
3534                 /* update HW stats in background for next time */
3535                 mlx5e_queue_update_stats(priv);
3536         }
3537
3538         if (mlx5e_is_uplink_rep(priv)) {
3539                 stats->rx_packets = PPORT_802_3_GET(pstats, a_frames_received_ok);
3540                 stats->rx_bytes   = PPORT_802_3_GET(pstats, a_octets_received_ok);
3541                 stats->tx_packets = PPORT_802_3_GET(pstats, a_frames_transmitted_ok);
3542                 stats->tx_bytes   = PPORT_802_3_GET(pstats, a_octets_transmitted_ok);
3543         } else {
3544                 mlx5e_fold_sw_stats64(priv, stats);
3545         }
3546
3547         stats->rx_dropped = priv->stats.qcnt.rx_out_of_buffer;
3548
3549         stats->rx_length_errors =
3550                 PPORT_802_3_GET(pstats, a_in_range_length_errors) +
3551                 PPORT_802_3_GET(pstats, a_out_of_range_length_field) +
3552                 PPORT_802_3_GET(pstats, a_frame_too_long_errors);
3553         stats->rx_crc_errors =
3554                 PPORT_802_3_GET(pstats, a_frame_check_sequence_errors);
3555         stats->rx_frame_errors = PPORT_802_3_GET(pstats, a_alignment_errors);
3556         stats->tx_aborted_errors = PPORT_2863_GET(pstats, if_out_discards);
3557         stats->rx_errors = stats->rx_length_errors + stats->rx_crc_errors +
3558                            stats->rx_frame_errors;
3559         stats->tx_errors = stats->tx_aborted_errors + stats->tx_carrier_errors;
3560
3561         /* vport multicast also counts packets that are dropped due to steering
3562          * or rx out of buffer
3563          */
3564         stats->multicast =
3565                 VPORT_COUNTER_GET(vstats, received_eth_multicast.packets);
3566 }
3567
3568 static void mlx5e_set_rx_mode(struct net_device *dev)
3569 {
3570         struct mlx5e_priv *priv = netdev_priv(dev);
3571
3572         queue_work(priv->wq, &priv->set_rx_mode_work);
3573 }
3574
3575 static int mlx5e_set_mac(struct net_device *netdev, void *addr)
3576 {
3577         struct mlx5e_priv *priv = netdev_priv(netdev);
3578         struct sockaddr *saddr = addr;
3579
3580         if (!is_valid_ether_addr(saddr->sa_data))
3581                 return -EADDRNOTAVAIL;
3582
3583         netif_addr_lock_bh(netdev);
3584         ether_addr_copy(netdev->dev_addr, saddr->sa_data);
3585         netif_addr_unlock_bh(netdev);
3586
3587         queue_work(priv->wq, &priv->set_rx_mode_work);
3588
3589         return 0;
3590 }
3591
3592 #define MLX5E_SET_FEATURE(features, feature, enable)    \
3593         do {                                            \
3594                 if (enable)                             \
3595                         *features |= feature;           \
3596                 else                                    \
3597                         *features &= ~feature;          \
3598         } while (0)
3599
3600 typedef int (*mlx5e_feature_handler)(struct net_device *netdev, bool enable);
3601
3602 static int set_feature_lro(struct net_device *netdev, bool enable)
3603 {
3604         struct mlx5e_priv *priv = netdev_priv(netdev);
3605         struct mlx5_core_dev *mdev = priv->mdev;
3606         struct mlx5e_channels new_channels = {};
3607         struct mlx5e_params *old_params;
3608         int err = 0;
3609         bool reset;
3610
3611         mutex_lock(&priv->state_lock);
3612
3613         if (enable && priv->xsk.refcnt) {
3614                 netdev_warn(netdev, "LRO is incompatible with AF_XDP (%hu XSKs are active)\n",
3615                             priv->xsk.refcnt);
3616                 err = -EINVAL;
3617                 goto out;
3618         }
3619
3620         old_params = &priv->channels.params;
3621         if (enable && !MLX5E_GET_PFLAG(old_params, MLX5E_PFLAG_RX_STRIDING_RQ)) {
3622                 netdev_warn(netdev, "can't set LRO with legacy RQ\n");
3623                 err = -EINVAL;
3624                 goto out;
3625         }
3626
3627         reset = test_bit(MLX5E_STATE_OPENED, &priv->state);
3628
3629         new_channels.params = *old_params;
3630         new_channels.params.lro_en = enable;
3631
3632         if (old_params->rq_wq_type != MLX5_WQ_TYPE_CYCLIC) {
3633                 if (mlx5e_rx_mpwqe_is_linear_skb(mdev, old_params, NULL) ==
3634                     mlx5e_rx_mpwqe_is_linear_skb(mdev, &new_channels.params, NULL))
3635                         reset = false;
3636         }
3637
3638         if (!reset) {
3639                 *old_params = new_channels.params;
3640                 err = mlx5e_modify_tirs_lro(priv);
3641                 goto out;
3642         }
3643
3644         err = mlx5e_safe_switch_channels(priv, &new_channels, mlx5e_modify_tirs_lro);
3645 out:
3646         mutex_unlock(&priv->state_lock);
3647         return err;
3648 }
3649
3650 static int set_feature_cvlan_filter(struct net_device *netdev, bool enable)
3651 {
3652         struct mlx5e_priv *priv = netdev_priv(netdev);
3653
3654         if (enable)
3655                 mlx5e_enable_cvlan_filter(priv);
3656         else
3657                 mlx5e_disable_cvlan_filter(priv);
3658
3659         return 0;
3660 }
3661
3662 #ifdef CONFIG_MLX5_ESWITCH
3663 static int set_feature_tc_num_filters(struct net_device *netdev, bool enable)
3664 {
3665         struct mlx5e_priv *priv = netdev_priv(netdev);
3666
3667         if (!enable && mlx5e_tc_num_filters(priv, MLX5_TC_FLAG(NIC_OFFLOAD))) {
3668                 netdev_err(netdev,
3669                            "Active offloaded tc filters, can't turn hw_tc_offload off\n");
3670                 return -EINVAL;
3671         }
3672
3673         return 0;
3674 }
3675 #endif
3676
3677 static int set_feature_rx_all(struct net_device *netdev, bool enable)
3678 {
3679         struct mlx5e_priv *priv = netdev_priv(netdev);
3680         struct mlx5_core_dev *mdev = priv->mdev;
3681
3682         return mlx5_set_port_fcs(mdev, !enable);
3683 }
3684
3685 static int set_feature_rx_fcs(struct net_device *netdev, bool enable)
3686 {
3687         struct mlx5e_priv *priv = netdev_priv(netdev);
3688         int err;
3689
3690         mutex_lock(&priv->state_lock);
3691
3692         priv->channels.params.scatter_fcs_en = enable;
3693         err = mlx5e_modify_channels_scatter_fcs(&priv->channels, enable);
3694         if (err)
3695                 priv->channels.params.scatter_fcs_en = !enable;
3696
3697         mutex_unlock(&priv->state_lock);
3698
3699         return err;
3700 }
3701
3702 static int set_feature_rx_vlan(struct net_device *netdev, bool enable)
3703 {
3704         struct mlx5e_priv *priv = netdev_priv(netdev);
3705         int err = 0;
3706
3707         mutex_lock(&priv->state_lock);
3708
3709         priv->channels.params.vlan_strip_disable = !enable;
3710         if (!test_bit(MLX5E_STATE_OPENED, &priv->state))
3711                 goto unlock;
3712
3713         err = mlx5e_modify_channels_vsd(&priv->channels, !enable);
3714         if (err)
3715                 priv->channels.params.vlan_strip_disable = enable;
3716
3717 unlock:
3718         mutex_unlock(&priv->state_lock);
3719
3720         return err;
3721 }
3722
3723 #ifdef CONFIG_MLX5_EN_ARFS
3724 static int set_feature_arfs(struct net_device *netdev, bool enable)
3725 {
3726         struct mlx5e_priv *priv = netdev_priv(netdev);
3727         int err;
3728
3729         if (enable)
3730                 err = mlx5e_arfs_enable(priv);
3731         else
3732                 err = mlx5e_arfs_disable(priv);
3733
3734         return err;
3735 }
3736 #endif
3737
3738 static int mlx5e_handle_feature(struct net_device *netdev,
3739                                 netdev_features_t *features,
3740                                 netdev_features_t wanted_features,
3741                                 netdev_features_t feature,
3742                                 mlx5e_feature_handler feature_handler)
3743 {
3744         netdev_features_t changes = wanted_features ^ netdev->features;
3745         bool enable = !!(wanted_features & feature);
3746         int err;
3747
3748         if (!(changes & feature))
3749                 return 0;
3750
3751         err = feature_handler(netdev, enable);
3752         if (err) {
3753                 netdev_err(netdev, "%s feature %pNF failed, err %d\n",
3754                            enable ? "Enable" : "Disable", &feature, err);
3755                 return err;
3756         }
3757
3758         MLX5E_SET_FEATURE(features, feature, enable);
3759         return 0;
3760 }
3761
3762 int mlx5e_set_features(struct net_device *netdev, netdev_features_t features)
3763 {
3764         netdev_features_t oper_features = netdev->features;
3765         int err = 0;
3766
3767 #define MLX5E_HANDLE_FEATURE(feature, handler) \
3768         mlx5e_handle_feature(netdev, &oper_features, features, feature, handler)
3769
3770         err |= MLX5E_HANDLE_FEATURE(NETIF_F_LRO, set_feature_lro);
3771         err |= MLX5E_HANDLE_FEATURE(NETIF_F_HW_VLAN_CTAG_FILTER,
3772                                     set_feature_cvlan_filter);
3773 #ifdef CONFIG_MLX5_ESWITCH
3774         err |= MLX5E_HANDLE_FEATURE(NETIF_F_HW_TC, set_feature_tc_num_filters);
3775 #endif
3776         err |= MLX5E_HANDLE_FEATURE(NETIF_F_RXALL, set_feature_rx_all);
3777         err |= MLX5E_HANDLE_FEATURE(NETIF_F_RXFCS, set_feature_rx_fcs);
3778         err |= MLX5E_HANDLE_FEATURE(NETIF_F_HW_VLAN_CTAG_RX, set_feature_rx_vlan);
3779 #ifdef CONFIG_MLX5_EN_ARFS
3780         err |= MLX5E_HANDLE_FEATURE(NETIF_F_NTUPLE, set_feature_arfs);
3781 #endif
3782
3783         if (err) {
3784                 netdev->features = oper_features;
3785                 return -EINVAL;
3786         }
3787
3788         return 0;
3789 }
3790
3791 static netdev_features_t mlx5e_fix_features(struct net_device *netdev,
3792                                             netdev_features_t features)
3793 {
3794         struct mlx5e_priv *priv = netdev_priv(netdev);
3795         struct mlx5e_params *params;
3796
3797         mutex_lock(&priv->state_lock);
3798         params = &priv->channels.params;
3799         if (!bitmap_empty(priv->fs.vlan.active_svlans, VLAN_N_VID)) {
3800                 /* HW strips the outer C-tag header, this is a problem
3801                  * for S-tag traffic.
3802                  */
3803                 features &= ~NETIF_F_HW_VLAN_CTAG_RX;
3804                 if (!params->vlan_strip_disable)
3805                         netdev_warn(netdev, "Dropping C-tag vlan stripping offload due to S-tag vlan\n");
3806         }
3807         if (!MLX5E_GET_PFLAG(params, MLX5E_PFLAG_RX_STRIDING_RQ)) {
3808                 if (features & NETIF_F_LRO) {
3809                         netdev_warn(netdev, "Disabling LRO, not supported in legacy RQ\n");
3810                         features &= ~NETIF_F_LRO;
3811                 }
3812         }
3813
3814         if (MLX5E_GET_PFLAG(params, MLX5E_PFLAG_RX_CQE_COMPRESS)) {
3815                 features &= ~NETIF_F_RXHASH;
3816                 if (netdev->features & NETIF_F_RXHASH)
3817                         netdev_warn(netdev, "Disabling rxhash, not supported when CQE compress is active\n");
3818         }
3819
3820         mutex_unlock(&priv->state_lock);
3821
3822         return features;
3823 }
3824
3825 static bool mlx5e_xsk_validate_mtu(struct net_device *netdev,
3826                                    struct mlx5e_channels *chs,
3827                                    struct mlx5e_params *new_params,
3828                                    struct mlx5_core_dev *mdev)
3829 {
3830         u16 ix;
3831
3832         for (ix = 0; ix < chs->params.num_channels; ix++) {
3833                 struct xdp_umem *umem = mlx5e_xsk_get_umem(&chs->params, chs->params.xsk, ix);
3834                 struct mlx5e_xsk_param xsk;
3835
3836                 if (!umem)
3837                         continue;
3838
3839                 mlx5e_build_xsk_param(umem, &xsk);
3840
3841                 if (!mlx5e_validate_xsk_param(new_params, &xsk, mdev)) {
3842                         u32 hr = mlx5e_get_linear_rq_headroom(new_params, &xsk);
3843                         int max_mtu_frame, max_mtu_page, max_mtu;
3844
3845                         /* Two criteria must be met:
3846                          * 1. HW MTU + all headrooms <= XSK frame size.
3847                          * 2. Size of SKBs allocated on XDP_PASS <= PAGE_SIZE.
3848                          */
3849                         max_mtu_frame = MLX5E_HW2SW_MTU(new_params, xsk.chunk_size - hr);
3850                         max_mtu_page = mlx5e_xdp_max_mtu(new_params, &xsk);
3851                         max_mtu = min(max_mtu_frame, max_mtu_page);
3852
3853                         netdev_err(netdev, "MTU %d is too big for an XSK running on channel %hu. Try MTU <= %d\n",
3854                                    new_params->sw_mtu, ix, max_mtu);
3855                         return false;
3856                 }
3857         }
3858
3859         return true;
3860 }
3861
3862 int mlx5e_change_mtu(struct net_device *netdev, int new_mtu,
3863                      change_hw_mtu_cb set_mtu_cb)
3864 {
3865         struct mlx5e_priv *priv = netdev_priv(netdev);
3866         struct mlx5e_channels new_channels = {};
3867         struct mlx5e_params *params;
3868         int err = 0;
3869         bool reset;
3870
3871         mutex_lock(&priv->state_lock);
3872
3873         params = &priv->channels.params;
3874
3875         reset = !params->lro_en;
3876         reset = reset && test_bit(MLX5E_STATE_OPENED, &priv->state);
3877
3878         new_channels.params = *params;
3879         new_channels.params.sw_mtu = new_mtu;
3880
3881         if (params->xdp_prog &&
3882             !mlx5e_rx_is_linear_skb(&new_channels.params, NULL)) {
3883                 netdev_err(netdev, "MTU(%d) > %d is not allowed while XDP enabled\n",
3884                            new_mtu, mlx5e_xdp_max_mtu(params, NULL));
3885                 err = -EINVAL;
3886                 goto out;
3887         }
3888
3889         if (priv->xsk.refcnt &&
3890             !mlx5e_xsk_validate_mtu(netdev, &priv->channels,
3891                                     &new_channels.params, priv->mdev)) {
3892                 err = -EINVAL;
3893                 goto out;
3894         }
3895
3896         if (params->rq_wq_type == MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ) {
3897                 bool is_linear = mlx5e_rx_mpwqe_is_linear_skb(priv->mdev,
3898                                                               &new_channels.params,
3899                                                               NULL);
3900                 u8 ppw_old = mlx5e_mpwqe_log_pkts_per_wqe(params, NULL);
3901                 u8 ppw_new = mlx5e_mpwqe_log_pkts_per_wqe(&new_channels.params, NULL);
3902
3903                 /* If XSK is active, XSK RQs are linear. */
3904                 is_linear |= priv->xsk.refcnt;
3905
3906                 /* Always reset in linear mode - hw_mtu is used in data path. */
3907                 reset = reset && (is_linear || (ppw_old != ppw_new));
3908         }
3909
3910         if (!reset) {
3911                 params->sw_mtu = new_mtu;
3912                 if (set_mtu_cb)
3913                         set_mtu_cb(priv);
3914                 netdev->mtu = params->sw_mtu;
3915                 goto out;
3916         }
3917
3918         err = mlx5e_safe_switch_channels(priv, &new_channels, set_mtu_cb);
3919         if (err)
3920                 goto out;
3921
3922         netdev->mtu = new_channels.params.sw_mtu;
3923
3924 out:
3925         mutex_unlock(&priv->state_lock);
3926         return err;
3927 }
3928
3929 static int mlx5e_change_nic_mtu(struct net_device *netdev, int new_mtu)
3930 {
3931         return mlx5e_change_mtu(netdev, new_mtu, mlx5e_set_dev_port_mtu);
3932 }
3933
3934 int mlx5e_hwstamp_set(struct mlx5e_priv *priv, struct ifreq *ifr)
3935 {
3936         struct hwtstamp_config config;
3937         int err;
3938
3939         if (!MLX5_CAP_GEN(priv->mdev, device_frequency_khz) ||
3940             (mlx5_clock_get_ptp_index(priv->mdev) == -1))
3941                 return -EOPNOTSUPP;
3942
3943         if (copy_from_user(&config, ifr->ifr_data, sizeof(config)))
3944                 return -EFAULT;
3945
3946         /* TX HW timestamp */
3947         switch (config.tx_type) {
3948         case HWTSTAMP_TX_OFF:
3949         case HWTSTAMP_TX_ON:
3950                 break;
3951         default:
3952                 return -ERANGE;
3953         }
3954
3955         mutex_lock(&priv->state_lock);
3956         /* RX HW timestamp */
3957         switch (config.rx_filter) {
3958         case HWTSTAMP_FILTER_NONE:
3959                 /* Reset CQE compression to Admin default */
3960                 mlx5e_modify_rx_cqe_compression_locked(priv, priv->channels.params.rx_cqe_compress_def);
3961                 break;
3962         case HWTSTAMP_FILTER_ALL:
3963         case HWTSTAMP_FILTER_SOME:
3964         case HWTSTAMP_FILTER_PTP_V1_L4_EVENT:
3965         case HWTSTAMP_FILTER_PTP_V1_L4_SYNC:
3966         case HWTSTAMP_FILTER_PTP_V1_L4_DELAY_REQ:
3967         case HWTSTAMP_FILTER_PTP_V2_L4_EVENT:
3968         case HWTSTAMP_FILTER_PTP_V2_L4_SYNC:
3969         case HWTSTAMP_FILTER_PTP_V2_L4_DELAY_REQ:
3970         case HWTSTAMP_FILTER_PTP_V2_L2_EVENT:
3971         case HWTSTAMP_FILTER_PTP_V2_L2_SYNC:
3972         case HWTSTAMP_FILTER_PTP_V2_L2_DELAY_REQ:
3973         case HWTSTAMP_FILTER_PTP_V2_EVENT:
3974         case HWTSTAMP_FILTER_PTP_V2_SYNC:
3975         case HWTSTAMP_FILTER_PTP_V2_DELAY_REQ:
3976         case HWTSTAMP_FILTER_NTP_ALL:
3977                 /* Disable CQE compression */
3978                 if (MLX5E_GET_PFLAG(&priv->channels.params, MLX5E_PFLAG_RX_CQE_COMPRESS))
3979                         netdev_warn(priv->netdev, "Disabling RX cqe compression\n");
3980                 err = mlx5e_modify_rx_cqe_compression_locked(priv, false);
3981                 if (err) {
3982                         netdev_err(priv->netdev, "Failed disabling cqe compression err=%d\n", err);
3983                         mutex_unlock(&priv->state_lock);
3984                         return err;
3985                 }
3986                 config.rx_filter = HWTSTAMP_FILTER_ALL;
3987                 break;
3988         default:
3989                 mutex_unlock(&priv->state_lock);
3990                 return -ERANGE;
3991         }
3992
3993         memcpy(&priv->tstamp, &config, sizeof(config));
3994         mutex_unlock(&priv->state_lock);
3995
3996         /* might need to fix some features */
3997         netdev_update_features(priv->netdev);
3998
3999         return copy_to_user(ifr->ifr_data, &config,
4000                             sizeof(config)) ? -EFAULT : 0;
4001 }
4002
4003 int mlx5e_hwstamp_get(struct mlx5e_priv *priv, struct ifreq *ifr)
4004 {
4005         struct hwtstamp_config *cfg = &priv->tstamp;
4006
4007         if (!MLX5_CAP_GEN(priv->mdev, device_frequency_khz))
4008                 return -EOPNOTSUPP;
4009
4010         return copy_to_user(ifr->ifr_data, cfg, sizeof(*cfg)) ? -EFAULT : 0;
4011 }
4012
4013 static int mlx5e_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
4014 {
4015         struct mlx5e_priv *priv = netdev_priv(dev);
4016
4017         switch (cmd) {
4018         case SIOCSHWTSTAMP:
4019                 return mlx5e_hwstamp_set(priv, ifr);
4020         case SIOCGHWTSTAMP:
4021                 return mlx5e_hwstamp_get(priv, ifr);
4022         default:
4023                 return -EOPNOTSUPP;
4024         }
4025 }
4026
4027 #ifdef CONFIG_MLX5_ESWITCH
4028 int mlx5e_set_vf_mac(struct net_device *dev, int vf, u8 *mac)
4029 {
4030         struct mlx5e_priv *priv = netdev_priv(dev);
4031         struct mlx5_core_dev *mdev = priv->mdev;
4032
4033         return mlx5_eswitch_set_vport_mac(mdev->priv.eswitch, vf + 1, mac);
4034 }
4035
4036 static int mlx5e_set_vf_vlan(struct net_device *dev, int vf, u16 vlan, u8 qos,
4037                              __be16 vlan_proto)
4038 {
4039         struct mlx5e_priv *priv = netdev_priv(dev);
4040         struct mlx5_core_dev *mdev = priv->mdev;
4041
4042         if (vlan_proto != htons(ETH_P_8021Q))
4043                 return -EPROTONOSUPPORT;
4044
4045         return mlx5_eswitch_set_vport_vlan(mdev->priv.eswitch, vf + 1,
4046                                            vlan, qos);
4047 }
4048
4049 static int mlx5e_set_vf_spoofchk(struct net_device *dev, int vf, bool setting)
4050 {
4051         struct mlx5e_priv *priv = netdev_priv(dev);
4052         struct mlx5_core_dev *mdev = priv->mdev;
4053
4054         return mlx5_eswitch_set_vport_spoofchk(mdev->priv.eswitch, vf + 1, setting);
4055 }
4056
4057 static int mlx5e_set_vf_trust(struct net_device *dev, int vf, bool setting)
4058 {
4059         struct mlx5e_priv *priv = netdev_priv(dev);
4060         struct mlx5_core_dev *mdev = priv->mdev;
4061
4062         return mlx5_eswitch_set_vport_trust(mdev->priv.eswitch, vf + 1, setting);
4063 }
4064
4065 int mlx5e_set_vf_rate(struct net_device *dev, int vf, int min_tx_rate,
4066                       int max_tx_rate)
4067 {
4068         struct mlx5e_priv *priv = netdev_priv(dev);
4069         struct mlx5_core_dev *mdev = priv->mdev;
4070
4071         return mlx5_eswitch_set_vport_rate(mdev->priv.eswitch, vf + 1,
4072                                            max_tx_rate, min_tx_rate);
4073 }
4074
4075 static int mlx5_vport_link2ifla(u8 esw_link)
4076 {
4077         switch (esw_link) {
4078         case MLX5_VPORT_ADMIN_STATE_DOWN:
4079                 return IFLA_VF_LINK_STATE_DISABLE;
4080         case MLX5_VPORT_ADMIN_STATE_UP:
4081                 return IFLA_VF_LINK_STATE_ENABLE;
4082         }
4083         return IFLA_VF_LINK_STATE_AUTO;
4084 }
4085
4086 static int mlx5_ifla_link2vport(u8 ifla_link)
4087 {
4088         switch (ifla_link) {
4089         case IFLA_VF_LINK_STATE_DISABLE:
4090                 return MLX5_VPORT_ADMIN_STATE_DOWN;
4091         case IFLA_VF_LINK_STATE_ENABLE:
4092                 return MLX5_VPORT_ADMIN_STATE_UP;
4093         }
4094         return MLX5_VPORT_ADMIN_STATE_AUTO;
4095 }
4096
4097 static int mlx5e_set_vf_link_state(struct net_device *dev, int vf,
4098                                    int link_state)
4099 {
4100         struct mlx5e_priv *priv = netdev_priv(dev);
4101         struct mlx5_core_dev *mdev = priv->mdev;
4102
4103         return mlx5_eswitch_set_vport_state(mdev->priv.eswitch, vf + 1,
4104                                             mlx5_ifla_link2vport(link_state));
4105 }
4106
4107 int mlx5e_get_vf_config(struct net_device *dev,
4108                         int vf, struct ifla_vf_info *ivi)
4109 {
4110         struct mlx5e_priv *priv = netdev_priv(dev);
4111         struct mlx5_core_dev *mdev = priv->mdev;
4112         int err;
4113
4114         err = mlx5_eswitch_get_vport_config(mdev->priv.eswitch, vf + 1, ivi);
4115         if (err)
4116                 return err;
4117         ivi->linkstate = mlx5_vport_link2ifla(ivi->linkstate);
4118         return 0;
4119 }
4120
4121 int mlx5e_get_vf_stats(struct net_device *dev,
4122                        int vf, struct ifla_vf_stats *vf_stats)
4123 {
4124         struct mlx5e_priv *priv = netdev_priv(dev);
4125         struct mlx5_core_dev *mdev = priv->mdev;
4126
4127         return mlx5_eswitch_get_vport_stats(mdev->priv.eswitch, vf + 1,
4128                                             vf_stats);
4129 }
4130 #endif
4131
4132 struct mlx5e_vxlan_work {
4133         struct work_struct      work;
4134         struct mlx5e_priv       *priv;
4135         u16                     port;
4136 };
4137
4138 static void mlx5e_vxlan_add_work(struct work_struct *work)
4139 {
4140         struct mlx5e_vxlan_work *vxlan_work =
4141                 container_of(work, struct mlx5e_vxlan_work, work);
4142         struct mlx5e_priv *priv = vxlan_work->priv;
4143         u16 port = vxlan_work->port;
4144
4145         mutex_lock(&priv->state_lock);
4146         mlx5_vxlan_add_port(priv->mdev->vxlan, port);
4147         mutex_unlock(&priv->state_lock);
4148
4149         kfree(vxlan_work);
4150 }
4151
4152 static void mlx5e_vxlan_del_work(struct work_struct *work)
4153 {
4154         struct mlx5e_vxlan_work *vxlan_work =
4155                 container_of(work, struct mlx5e_vxlan_work, work);
4156         struct mlx5e_priv *priv         = vxlan_work->priv;
4157         u16 port = vxlan_work->port;
4158
4159         mutex_lock(&priv->state_lock);
4160         mlx5_vxlan_del_port(priv->mdev->vxlan, port);
4161         mutex_unlock(&priv->state_lock);
4162         kfree(vxlan_work);
4163 }
4164
4165 static void mlx5e_vxlan_queue_work(struct mlx5e_priv *priv, u16 port, int add)
4166 {
4167         struct mlx5e_vxlan_work *vxlan_work;
4168
4169         vxlan_work = kmalloc(sizeof(*vxlan_work), GFP_ATOMIC);
4170         if (!vxlan_work)
4171                 return;
4172
4173         if (add)
4174                 INIT_WORK(&vxlan_work->work, mlx5e_vxlan_add_work);
4175         else
4176                 INIT_WORK(&vxlan_work->work, mlx5e_vxlan_del_work);
4177
4178         vxlan_work->priv = priv;
4179         vxlan_work->port = port;
4180         queue_work(priv->wq, &vxlan_work->work);
4181 }
4182
4183 void mlx5e_add_vxlan_port(struct net_device *netdev, struct udp_tunnel_info *ti)
4184 {
4185         struct mlx5e_priv *priv = netdev_priv(netdev);
4186
4187         if (ti->type != UDP_TUNNEL_TYPE_VXLAN)
4188                 return;
4189
4190         if (!mlx5_vxlan_allowed(priv->mdev->vxlan))
4191                 return;
4192
4193         mlx5e_vxlan_queue_work(priv, be16_to_cpu(ti->port), 1);
4194 }
4195
4196 void mlx5e_del_vxlan_port(struct net_device *netdev, struct udp_tunnel_info *ti)
4197 {
4198         struct mlx5e_priv *priv = netdev_priv(netdev);
4199
4200         if (ti->type != UDP_TUNNEL_TYPE_VXLAN)
4201                 return;
4202
4203         if (!mlx5_vxlan_allowed(priv->mdev->vxlan))
4204                 return;
4205
4206         mlx5e_vxlan_queue_work(priv, be16_to_cpu(ti->port), 0);
4207 }
4208
4209 static netdev_features_t mlx5e_tunnel_features_check(struct mlx5e_priv *priv,
4210                                                      struct sk_buff *skb,
4211                                                      netdev_features_t features)
4212 {
4213         unsigned int offset = 0;
4214         struct udphdr *udph;
4215         u8 proto;
4216         u16 port;
4217
4218         switch (vlan_get_protocol(skb)) {
4219         case htons(ETH_P_IP):
4220                 proto = ip_hdr(skb)->protocol;
4221                 break;
4222         case htons(ETH_P_IPV6):
4223                 proto = ipv6_find_hdr(skb, &offset, -1, NULL, NULL);
4224                 break;
4225         default:
4226                 goto out;
4227         }
4228
4229         switch (proto) {
4230         case IPPROTO_GRE:
4231                 return features;
4232         case IPPROTO_IPIP:
4233         case IPPROTO_IPV6:
4234                 if (mlx5e_tunnel_proto_supported(priv->mdev, IPPROTO_IPIP))
4235                         return features;
4236                 break;
4237         case IPPROTO_UDP:
4238                 udph = udp_hdr(skb);
4239                 port = be16_to_cpu(udph->dest);
4240
4241                 /* Verify if UDP port is being offloaded by HW */
4242                 if (mlx5_vxlan_lookup_port(priv->mdev->vxlan, port))
4243                         return features;
4244
4245 #if IS_ENABLED(CONFIG_GENEVE)
4246                 /* Support Geneve offload for default UDP port */
4247                 if (port == GENEVE_UDP_PORT && mlx5_geneve_tx_allowed(priv->mdev))
4248                         return features;
4249 #endif
4250         }
4251
4252 out:
4253         /* Disable CSUM and GSO if the udp dport is not offloaded by HW */
4254         return features & ~(NETIF_F_CSUM_MASK | NETIF_F_GSO_MASK);
4255 }
4256
4257 netdev_features_t mlx5e_features_check(struct sk_buff *skb,
4258                                        struct net_device *netdev,
4259                                        netdev_features_t features)
4260 {
4261         struct mlx5e_priv *priv = netdev_priv(netdev);
4262
4263         features = vlan_features_check(skb, features);
4264         features = vxlan_features_check(skb, features);
4265
4266 #ifdef CONFIG_MLX5_EN_IPSEC
4267         if (mlx5e_ipsec_feature_check(skb, netdev, features))
4268                 return features;
4269 #endif
4270
4271         /* Validate if the tunneled packet is being offloaded by HW */
4272         if (skb->encapsulation &&
4273             (features & NETIF_F_CSUM_MASK || features & NETIF_F_GSO_MASK))
4274                 return mlx5e_tunnel_features_check(priv, skb, features);
4275
4276         return features;
4277 }
4278
4279 static void mlx5e_tx_timeout_work(struct work_struct *work)
4280 {
4281         struct mlx5e_priv *priv = container_of(work, struct mlx5e_priv,
4282                                                tx_timeout_work);
4283         bool report_failed = false;
4284         int err;
4285         int i;
4286
4287         rtnl_lock();
4288         mutex_lock(&priv->state_lock);
4289
4290         if (!test_bit(MLX5E_STATE_OPENED, &priv->state))
4291                 goto unlock;
4292
4293         for (i = 0; i < priv->channels.num * priv->channels.params.num_tc; i++) {
4294                 struct netdev_queue *dev_queue =
4295                         netdev_get_tx_queue(priv->netdev, i);
4296                 struct mlx5e_txqsq *sq = priv->txq2sq[i];
4297
4298                 if (!netif_xmit_stopped(dev_queue))
4299                         continue;
4300
4301                 if (mlx5e_reporter_tx_timeout(sq))
4302                         report_failed = true;
4303         }
4304
4305         if (!report_failed)
4306                 goto unlock;
4307
4308         err = mlx5e_safe_reopen_channels(priv);
4309         if (err)
4310                 netdev_err(priv->netdev,
4311                            "mlx5e_safe_reopen_channels failed recovering from a tx_timeout, err(%d).\n",
4312                            err);
4313
4314 unlock:
4315         mutex_unlock(&priv->state_lock);
4316         rtnl_unlock();
4317 }
4318
4319 static void mlx5e_tx_timeout(struct net_device *dev, unsigned int txqueue)
4320 {
4321         struct mlx5e_priv *priv = netdev_priv(dev);
4322
4323         netdev_err(dev, "TX timeout detected\n");
4324         queue_work(priv->wq, &priv->tx_timeout_work);
4325 }
4326
4327 static int mlx5e_xdp_allowed(struct mlx5e_priv *priv, struct bpf_prog *prog)
4328 {
4329         struct net_device *netdev = priv->netdev;
4330         struct mlx5e_channels new_channels = {};
4331
4332         if (priv->channels.params.lro_en) {
4333                 netdev_warn(netdev, "can't set XDP while LRO is on, disable LRO first\n");
4334                 return -EINVAL;
4335         }
4336
4337         if (MLX5_IPSEC_DEV(priv->mdev)) {
4338                 netdev_warn(netdev, "can't set XDP with IPSec offload\n");
4339                 return -EINVAL;
4340         }
4341
4342         new_channels.params = priv->channels.params;
4343         new_channels.params.xdp_prog = prog;
4344
4345         /* No XSK params: AF_XDP can't be enabled yet at the point of setting
4346          * the XDP program.
4347          */
4348         if (!mlx5e_rx_is_linear_skb(&new_channels.params, NULL)) {
4349                 netdev_warn(netdev, "XDP is not allowed with MTU(%d) > %d\n",
4350                             new_channels.params.sw_mtu,
4351                             mlx5e_xdp_max_mtu(&new_channels.params, NULL));
4352                 return -EINVAL;
4353         }
4354
4355         return 0;
4356 }
4357
4358 static int mlx5e_xdp_set(struct net_device *netdev, struct bpf_prog *prog)
4359 {
4360         struct mlx5e_priv *priv = netdev_priv(netdev);
4361         struct bpf_prog *old_prog;
4362         bool reset, was_opened;
4363         int err = 0;
4364         int i;
4365
4366         mutex_lock(&priv->state_lock);
4367
4368         if (prog) {
4369                 err = mlx5e_xdp_allowed(priv, prog);
4370                 if (err)
4371                         goto unlock;
4372         }
4373
4374         was_opened = test_bit(MLX5E_STATE_OPENED, &priv->state);
4375         /* no need for full reset when exchanging programs */
4376         reset = (!priv->channels.params.xdp_prog || !prog);
4377
4378         if (was_opened && !reset)
4379                 /* num_channels is invariant here, so we can take the
4380                  * batched reference right upfront.
4381                  */
4382                 bpf_prog_add(prog, priv->channels.num);
4383
4384         if (was_opened && reset) {
4385                 struct mlx5e_channels new_channels = {};
4386
4387                 new_channels.params = priv->channels.params;
4388                 new_channels.params.xdp_prog = prog;
4389                 mlx5e_set_rq_type(priv->mdev, &new_channels.params);
4390                 old_prog = priv->channels.params.xdp_prog;
4391
4392                 err = mlx5e_safe_switch_channels(priv, &new_channels, NULL);
4393                 if (err)
4394                         goto unlock;
4395         } else {
4396                 /* exchange programs, extra prog reference we got from caller
4397                  * as long as we don't fail from this point onwards.
4398                  */
4399                 old_prog = xchg(&priv->channels.params.xdp_prog, prog);
4400         }
4401
4402         if (old_prog)
4403                 bpf_prog_put(old_prog);
4404
4405         if (!was_opened && reset) /* change RQ type according to priv->xdp_prog */
4406                 mlx5e_set_rq_type(priv->mdev, &priv->channels.params);
4407
4408         if (!was_opened || reset)
4409                 goto unlock;
4410
4411         /* exchanging programs w/o reset, we update ref counts on behalf
4412          * of the channels RQs here.
4413          */
4414         for (i = 0; i < priv->channels.num; i++) {
4415                 struct mlx5e_channel *c = priv->channels.c[i];
4416                 bool xsk_open = test_bit(MLX5E_CHANNEL_STATE_XSK, c->state);
4417
4418                 clear_bit(MLX5E_RQ_STATE_ENABLED, &c->rq.state);
4419                 if (xsk_open)
4420                         clear_bit(MLX5E_RQ_STATE_ENABLED, &c->xskrq.state);
4421                 napi_synchronize(&c->napi);
4422                 /* prevent mlx5e_poll_rx_cq from accessing rq->xdp_prog */
4423
4424                 old_prog = xchg(&c->rq.xdp_prog, prog);
4425                 if (old_prog)
4426                         bpf_prog_put(old_prog);
4427
4428                 if (xsk_open) {
4429                         old_prog = xchg(&c->xskrq.xdp_prog, prog);
4430                         if (old_prog)
4431                                 bpf_prog_put(old_prog);
4432                 }
4433
4434                 set_bit(MLX5E_RQ_STATE_ENABLED, &c->rq.state);
4435                 if (xsk_open)
4436                         set_bit(MLX5E_RQ_STATE_ENABLED, &c->xskrq.state);
4437                 /* napi_schedule in case we have missed anything */
4438                 napi_schedule(&c->napi);
4439         }
4440
4441 unlock:
4442         mutex_unlock(&priv->state_lock);
4443         return err;
4444 }
4445
4446 static u32 mlx5e_xdp_query(struct net_device *dev)
4447 {
4448         struct mlx5e_priv *priv = netdev_priv(dev);
4449         const struct bpf_prog *xdp_prog;
4450         u32 prog_id = 0;
4451
4452         mutex_lock(&priv->state_lock);
4453         xdp_prog = priv->channels.params.xdp_prog;
4454         if (xdp_prog)
4455                 prog_id = xdp_prog->aux->id;
4456         mutex_unlock(&priv->state_lock);
4457
4458         return prog_id;
4459 }
4460
4461 static int mlx5e_xdp(struct net_device *dev, struct netdev_bpf *xdp)
4462 {
4463         switch (xdp->command) {
4464         case XDP_SETUP_PROG:
4465                 return mlx5e_xdp_set(dev, xdp->prog);
4466         case XDP_QUERY_PROG:
4467                 xdp->prog_id = mlx5e_xdp_query(dev);
4468                 return 0;
4469         case XDP_SETUP_XSK_UMEM:
4470                 return mlx5e_xsk_setup_umem(dev, xdp->xsk.umem,
4471                                             xdp->xsk.queue_id);
4472         default:
4473                 return -EINVAL;
4474         }
4475 }
4476
4477 #ifdef CONFIG_MLX5_ESWITCH
4478 static int mlx5e_bridge_getlink(struct sk_buff *skb, u32 pid, u32 seq,
4479                                 struct net_device *dev, u32 filter_mask,
4480                                 int nlflags)
4481 {
4482         struct mlx5e_priv *priv = netdev_priv(dev);
4483         struct mlx5_core_dev *mdev = priv->mdev;
4484         u8 mode, setting;
4485         int err;
4486
4487         err = mlx5_eswitch_get_vepa(mdev->priv.eswitch, &setting);
4488         if (err)
4489                 return err;
4490         mode = setting ? BRIDGE_MODE_VEPA : BRIDGE_MODE_VEB;
4491         return ndo_dflt_bridge_getlink(skb, pid, seq, dev,
4492                                        mode,
4493                                        0, 0, nlflags, filter_mask, NULL);
4494 }
4495
4496 static int mlx5e_bridge_setlink(struct net_device *dev, struct nlmsghdr *nlh,
4497                                 u16 flags, struct netlink_ext_ack *extack)
4498 {
4499         struct mlx5e_priv *priv = netdev_priv(dev);
4500         struct mlx5_core_dev *mdev = priv->mdev;
4501         struct nlattr *attr, *br_spec;
4502         u16 mode = BRIDGE_MODE_UNDEF;
4503         u8 setting;
4504         int rem;
4505
4506         br_spec = nlmsg_find_attr(nlh, sizeof(struct ifinfomsg), IFLA_AF_SPEC);
4507         if (!br_spec)
4508                 return -EINVAL;
4509
4510         nla_for_each_nested(attr, br_spec, rem) {
4511                 if (nla_type(attr) != IFLA_BRIDGE_MODE)
4512                         continue;
4513
4514                 if (nla_len(attr) < sizeof(mode))
4515                         return -EINVAL;
4516
4517                 mode = nla_get_u16(attr);
4518                 if (mode > BRIDGE_MODE_VEPA)
4519                         return -EINVAL;
4520
4521                 break;
4522         }
4523
4524         if (mode == BRIDGE_MODE_UNDEF)
4525                 return -EINVAL;
4526
4527         setting = (mode == BRIDGE_MODE_VEPA) ?  1 : 0;
4528         return mlx5_eswitch_set_vepa(mdev->priv.eswitch, setting);
4529 }
4530 #endif
4531
4532 const struct net_device_ops mlx5e_netdev_ops = {
4533         .ndo_open                = mlx5e_open,
4534         .ndo_stop                = mlx5e_close,
4535         .ndo_start_xmit          = mlx5e_xmit,
4536         .ndo_setup_tc            = mlx5e_setup_tc,
4537         .ndo_select_queue        = mlx5e_select_queue,
4538         .ndo_get_stats64         = mlx5e_get_stats,
4539         .ndo_set_rx_mode         = mlx5e_set_rx_mode,
4540         .ndo_set_mac_address     = mlx5e_set_mac,
4541         .ndo_vlan_rx_add_vid     = mlx5e_vlan_rx_add_vid,
4542         .ndo_vlan_rx_kill_vid    = mlx5e_vlan_rx_kill_vid,
4543         .ndo_set_features        = mlx5e_set_features,
4544         .ndo_fix_features        = mlx5e_fix_features,
4545         .ndo_change_mtu          = mlx5e_change_nic_mtu,
4546         .ndo_do_ioctl            = mlx5e_ioctl,
4547         .ndo_set_tx_maxrate      = mlx5e_set_tx_maxrate,
4548         .ndo_udp_tunnel_add      = mlx5e_add_vxlan_port,
4549         .ndo_udp_tunnel_del      = mlx5e_del_vxlan_port,
4550         .ndo_features_check      = mlx5e_features_check,
4551         .ndo_tx_timeout          = mlx5e_tx_timeout,
4552         .ndo_bpf                 = mlx5e_xdp,
4553         .ndo_xdp_xmit            = mlx5e_xdp_xmit,
4554         .ndo_xsk_wakeup          = mlx5e_xsk_wakeup,
4555 #ifdef CONFIG_MLX5_EN_ARFS
4556         .ndo_rx_flow_steer       = mlx5e_rx_flow_steer,
4557 #endif
4558 #ifdef CONFIG_MLX5_ESWITCH
4559         .ndo_bridge_setlink      = mlx5e_bridge_setlink,
4560         .ndo_bridge_getlink      = mlx5e_bridge_getlink,
4561
4562         /* SRIOV E-Switch NDOs */
4563         .ndo_set_vf_mac          = mlx5e_set_vf_mac,
4564         .ndo_set_vf_vlan         = mlx5e_set_vf_vlan,
4565         .ndo_set_vf_spoofchk     = mlx5e_set_vf_spoofchk,
4566         .ndo_set_vf_trust        = mlx5e_set_vf_trust,
4567         .ndo_set_vf_rate         = mlx5e_set_vf_rate,
4568         .ndo_get_vf_config       = mlx5e_get_vf_config,
4569         .ndo_set_vf_link_state   = mlx5e_set_vf_link_state,
4570         .ndo_get_vf_stats        = mlx5e_get_vf_stats,
4571 #endif
4572 };
4573
4574 static int mlx5e_check_required_hca_cap(struct mlx5_core_dev *mdev)
4575 {
4576         if (MLX5_CAP_GEN(mdev, port_type) != MLX5_CAP_PORT_TYPE_ETH)
4577                 return -EOPNOTSUPP;
4578         if (!MLX5_CAP_GEN(mdev, eth_net_offloads) ||
4579             !MLX5_CAP_GEN(mdev, nic_flow_table) ||
4580             !MLX5_CAP_ETH(mdev, csum_cap) ||
4581             !MLX5_CAP_ETH(mdev, max_lso_cap) ||
4582             !MLX5_CAP_ETH(mdev, vlan_cap) ||
4583             !MLX5_CAP_ETH(mdev, rss_ind_tbl_cap) ||
4584             MLX5_CAP_FLOWTABLE(mdev,
4585                                flow_table_properties_nic_receive.max_ft_level)
4586                                < 3) {
4587                 mlx5_core_warn(mdev,
4588                                "Not creating net device, some required device capabilities are missing\n");
4589                 return -EOPNOTSUPP;
4590         }
4591         if (!MLX5_CAP_ETH(mdev, self_lb_en_modifiable))
4592                 mlx5_core_warn(mdev, "Self loop back prevention is not supported\n");
4593         if (!MLX5_CAP_GEN(mdev, cq_moderation))
4594                 mlx5_core_warn(mdev, "CQ moderation is not supported\n");
4595
4596         return 0;
4597 }
4598
4599 void mlx5e_build_default_indir_rqt(u32 *indirection_rqt, int len,
4600                                    int num_channels)
4601 {
4602         int i;
4603
4604         for (i = 0; i < len; i++)
4605                 indirection_rqt[i] = i % num_channels;
4606 }
4607
4608 static bool slow_pci_heuristic(struct mlx5_core_dev *mdev)
4609 {
4610         u32 link_speed = 0;
4611         u32 pci_bw = 0;
4612
4613         mlx5e_port_max_linkspeed(mdev, &link_speed);
4614         pci_bw = pcie_bandwidth_available(mdev->pdev, NULL, NULL, NULL);
4615         mlx5_core_dbg_once(mdev, "Max link speed = %d, PCI BW = %d\n",
4616                            link_speed, pci_bw);
4617
4618 #define MLX5E_SLOW_PCI_RATIO (2)
4619
4620         return link_speed && pci_bw &&
4621                 link_speed > MLX5E_SLOW_PCI_RATIO * pci_bw;
4622 }
4623
4624 static struct dim_cq_moder mlx5e_get_def_tx_moderation(u8 cq_period_mode)
4625 {
4626         struct dim_cq_moder moder;
4627
4628         moder.cq_period_mode = cq_period_mode;
4629         moder.pkts = MLX5E_PARAMS_DEFAULT_TX_CQ_MODERATION_PKTS;
4630         moder.usec = MLX5E_PARAMS_DEFAULT_TX_CQ_MODERATION_USEC;
4631         if (cq_period_mode == MLX5_CQ_PERIOD_MODE_START_FROM_CQE)
4632                 moder.usec = MLX5E_PARAMS_DEFAULT_TX_CQ_MODERATION_USEC_FROM_CQE;
4633
4634         return moder;
4635 }
4636
4637 static struct dim_cq_moder mlx5e_get_def_rx_moderation(u8 cq_period_mode)
4638 {
4639         struct dim_cq_moder moder;
4640
4641         moder.cq_period_mode = cq_period_mode;
4642         moder.pkts = MLX5E_PARAMS_DEFAULT_RX_CQ_MODERATION_PKTS;
4643         moder.usec = MLX5E_PARAMS_DEFAULT_RX_CQ_MODERATION_USEC;
4644         if (cq_period_mode == MLX5_CQ_PERIOD_MODE_START_FROM_CQE)
4645                 moder.usec = MLX5E_PARAMS_DEFAULT_RX_CQ_MODERATION_USEC_FROM_CQE;
4646
4647         return moder;
4648 }
4649
4650 static u8 mlx5_to_net_dim_cq_period_mode(u8 cq_period_mode)
4651 {
4652         return cq_period_mode == MLX5_CQ_PERIOD_MODE_START_FROM_CQE ?
4653                 DIM_CQ_PERIOD_MODE_START_FROM_CQE :
4654                 DIM_CQ_PERIOD_MODE_START_FROM_EQE;
4655 }
4656
4657 void mlx5e_set_tx_cq_mode_params(struct mlx5e_params *params, u8 cq_period_mode)
4658 {
4659         if (params->tx_dim_enabled) {
4660                 u8 dim_period_mode = mlx5_to_net_dim_cq_period_mode(cq_period_mode);
4661
4662                 params->tx_cq_moderation = net_dim_get_def_tx_moderation(dim_period_mode);
4663         } else {
4664                 params->tx_cq_moderation = mlx5e_get_def_tx_moderation(cq_period_mode);
4665         }
4666
4667         MLX5E_SET_PFLAG(params, MLX5E_PFLAG_TX_CQE_BASED_MODER,
4668                         params->tx_cq_moderation.cq_period_mode ==
4669                                 MLX5_CQ_PERIOD_MODE_START_FROM_CQE);
4670 }
4671
4672 void mlx5e_set_rx_cq_mode_params(struct mlx5e_params *params, u8 cq_period_mode)
4673 {
4674         if (params->rx_dim_enabled) {
4675                 u8 dim_period_mode = mlx5_to_net_dim_cq_period_mode(cq_period_mode);
4676
4677                 params->rx_cq_moderation = net_dim_get_def_rx_moderation(dim_period_mode);
4678         } else {
4679                 params->rx_cq_moderation = mlx5e_get_def_rx_moderation(cq_period_mode);
4680         }
4681
4682         MLX5E_SET_PFLAG(params, MLX5E_PFLAG_RX_CQE_BASED_MODER,
4683                         params->rx_cq_moderation.cq_period_mode ==
4684                                 MLX5_CQ_PERIOD_MODE_START_FROM_CQE);
4685 }
4686
4687 static u32 mlx5e_choose_lro_timeout(struct mlx5_core_dev *mdev, u32 wanted_timeout)
4688 {
4689         int i;
4690
4691         /* The supported periods are organized in ascending order */
4692         for (i = 0; i < MLX5E_LRO_TIMEOUT_ARR_SIZE - 1; i++)
4693                 if (MLX5_CAP_ETH(mdev, lro_timer_supported_periods[i]) >= wanted_timeout)
4694                         break;
4695
4696         return MLX5_CAP_ETH(mdev, lro_timer_supported_periods[i]);
4697 }
4698
4699 void mlx5e_build_rq_params(struct mlx5_core_dev *mdev,
4700                            struct mlx5e_params *params)
4701 {
4702         /* Prefer Striding RQ, unless any of the following holds:
4703          * - Striding RQ configuration is not possible/supported.
4704          * - Slow PCI heuristic.
4705          * - Legacy RQ would use linear SKB while Striding RQ would use non-linear.
4706          *
4707          * No XSK params: checking the availability of striding RQ in general.
4708          */
4709         if (!slow_pci_heuristic(mdev) &&
4710             mlx5e_striding_rq_possible(mdev, params) &&
4711             (mlx5e_rx_mpwqe_is_linear_skb(mdev, params, NULL) ||
4712              !mlx5e_rx_is_linear_skb(params, NULL)))
4713                 MLX5E_SET_PFLAG(params, MLX5E_PFLAG_RX_STRIDING_RQ, true);
4714         mlx5e_set_rq_type(mdev, params);
4715         mlx5e_init_rq_type_params(mdev, params);
4716 }
4717
4718 void mlx5e_build_rss_params(struct mlx5e_rss_params *rss_params,
4719                             u16 num_channels)
4720 {
4721         enum mlx5e_traffic_types tt;
4722
4723         rss_params->hfunc = ETH_RSS_HASH_TOP;
4724         netdev_rss_key_fill(rss_params->toeplitz_hash_key,
4725                             sizeof(rss_params->toeplitz_hash_key));
4726         mlx5e_build_default_indir_rqt(rss_params->indirection_rqt,
4727                                       MLX5E_INDIR_RQT_SIZE, num_channels);
4728         for (tt = 0; tt < MLX5E_NUM_INDIR_TIRS; tt++)
4729                 rss_params->rx_hash_fields[tt] =
4730                         tirc_default_config[tt].rx_hash_fields;
4731 }
4732
4733 void mlx5e_build_nic_params(struct mlx5e_priv *priv,
4734                             struct mlx5e_xsk *xsk,
4735                             struct mlx5e_rss_params *rss_params,
4736                             struct mlx5e_params *params,
4737                             u16 mtu)
4738 {
4739         struct mlx5_core_dev *mdev = priv->mdev;
4740         u8 rx_cq_period_mode;
4741
4742         params->sw_mtu = mtu;
4743         params->hard_mtu = MLX5E_ETH_HARD_MTU;
4744         params->num_channels = min_t(unsigned int, MLX5E_MAX_NUM_CHANNELS / 2,
4745                                      priv->max_nch);
4746         params->num_tc       = 1;
4747
4748         /* SQ */
4749         params->log_sq_size = is_kdump_kernel() ?
4750                 MLX5E_PARAMS_MINIMUM_LOG_SQ_SIZE :
4751                 MLX5E_PARAMS_DEFAULT_LOG_SQ_SIZE;
4752
4753         /* XDP SQ */
4754         MLX5E_SET_PFLAG(params, MLX5E_PFLAG_XDP_TX_MPWQE,
4755                         MLX5_CAP_ETH(mdev, enhanced_multi_pkt_send_wqe));
4756
4757         /* set CQE compression */
4758         params->rx_cqe_compress_def = false;
4759         if (MLX5_CAP_GEN(mdev, cqe_compression) &&
4760             MLX5_CAP_GEN(mdev, vport_group_manager))
4761                 params->rx_cqe_compress_def = slow_pci_heuristic(mdev);
4762
4763         MLX5E_SET_PFLAG(params, MLX5E_PFLAG_RX_CQE_COMPRESS, params->rx_cqe_compress_def);
4764         MLX5E_SET_PFLAG(params, MLX5E_PFLAG_RX_NO_CSUM_COMPLETE, false);
4765
4766         /* RQ */
4767         mlx5e_build_rq_params(mdev, params);
4768
4769         /* HW LRO */
4770
4771         /* TODO: && MLX5_CAP_ETH(mdev, lro_cap) */
4772         if (params->rq_wq_type == MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ) {
4773                 /* No XSK params: checking the availability of striding RQ in general. */
4774                 if (!mlx5e_rx_mpwqe_is_linear_skb(mdev, params, NULL))
4775                         params->lro_en = !slow_pci_heuristic(mdev);
4776         }
4777         params->lro_timeout = mlx5e_choose_lro_timeout(mdev, MLX5E_DEFAULT_LRO_TIMEOUT);
4778
4779         /* CQ moderation params */
4780         rx_cq_period_mode = MLX5_CAP_GEN(mdev, cq_period_start_from_cqe) ?
4781                         MLX5_CQ_PERIOD_MODE_START_FROM_CQE :
4782                         MLX5_CQ_PERIOD_MODE_START_FROM_EQE;
4783         params->rx_dim_enabled = MLX5_CAP_GEN(mdev, cq_moderation);
4784         params->tx_dim_enabled = MLX5_CAP_GEN(mdev, cq_moderation);
4785         mlx5e_set_rx_cq_mode_params(params, rx_cq_period_mode);
4786         mlx5e_set_tx_cq_mode_params(params, MLX5_CQ_PERIOD_MODE_START_FROM_EQE);
4787
4788         /* TX inline */
4789         mlx5_query_min_inline(mdev, &params->tx_min_inline_mode);
4790
4791         /* RSS */
4792         mlx5e_build_rss_params(rss_params, params->num_channels);
4793         params->tunneled_offload_en =
4794                 mlx5e_tunnel_inner_ft_supported(mdev);
4795
4796         /* AF_XDP */
4797         params->xsk = xsk;
4798 }
4799
4800 static void mlx5e_set_netdev_dev_addr(struct net_device *netdev)
4801 {
4802         struct mlx5e_priv *priv = netdev_priv(netdev);
4803
4804         mlx5_query_mac_address(priv->mdev, netdev->dev_addr);
4805         if (is_zero_ether_addr(netdev->dev_addr) &&
4806             !MLX5_CAP_GEN(priv->mdev, vport_group_manager)) {
4807                 eth_hw_addr_random(netdev);
4808                 mlx5_core_info(priv->mdev, "Assigned random MAC address %pM\n", netdev->dev_addr);
4809         }
4810 }
4811
4812 static void mlx5e_build_nic_netdev(struct net_device *netdev)
4813 {
4814         struct mlx5e_priv *priv = netdev_priv(netdev);
4815         struct mlx5_core_dev *mdev = priv->mdev;
4816         bool fcs_supported;
4817         bool fcs_enabled;
4818
4819         SET_NETDEV_DEV(netdev, mdev->device);
4820
4821         netdev->netdev_ops = &mlx5e_netdev_ops;
4822
4823 #ifdef CONFIG_MLX5_CORE_EN_DCB
4824         if (MLX5_CAP_GEN(mdev, vport_group_manager) && MLX5_CAP_GEN(mdev, qos))
4825                 netdev->dcbnl_ops = &mlx5e_dcbnl_ops;
4826 #endif
4827
4828         netdev->watchdog_timeo    = 15 * HZ;
4829
4830         netdev->ethtool_ops       = &mlx5e_ethtool_ops;
4831
4832         netdev->vlan_features    |= NETIF_F_SG;
4833         netdev->vlan_features    |= NETIF_F_HW_CSUM;
4834         netdev->vlan_features    |= NETIF_F_GRO;
4835         netdev->vlan_features    |= NETIF_F_TSO;
4836         netdev->vlan_features    |= NETIF_F_TSO6;
4837         netdev->vlan_features    |= NETIF_F_RXCSUM;
4838         netdev->vlan_features    |= NETIF_F_RXHASH;
4839
4840         netdev->mpls_features    |= NETIF_F_SG;
4841         netdev->mpls_features    |= NETIF_F_HW_CSUM;
4842         netdev->mpls_features    |= NETIF_F_TSO;
4843         netdev->mpls_features    |= NETIF_F_TSO6;
4844
4845         netdev->hw_enc_features  |= NETIF_F_HW_VLAN_CTAG_TX;
4846         netdev->hw_enc_features  |= NETIF_F_HW_VLAN_CTAG_RX;
4847
4848         if (!!MLX5_CAP_ETH(mdev, lro_cap) &&
4849             mlx5e_check_fragmented_striding_rq_cap(mdev))
4850                 netdev->vlan_features    |= NETIF_F_LRO;
4851
4852         netdev->hw_features       = netdev->vlan_features;
4853         netdev->hw_features      |= NETIF_F_HW_VLAN_CTAG_TX;
4854         netdev->hw_features      |= NETIF_F_HW_VLAN_CTAG_RX;
4855         netdev->hw_features      |= NETIF_F_HW_VLAN_CTAG_FILTER;
4856         netdev->hw_features      |= NETIF_F_HW_VLAN_STAG_TX;
4857
4858         if (mlx5_vxlan_allowed(mdev->vxlan) || mlx5_geneve_tx_allowed(mdev) ||
4859             mlx5e_any_tunnel_proto_supported(mdev)) {
4860                 netdev->hw_enc_features |= NETIF_F_HW_CSUM;
4861                 netdev->hw_enc_features |= NETIF_F_TSO;
4862                 netdev->hw_enc_features |= NETIF_F_TSO6;
4863                 netdev->hw_enc_features |= NETIF_F_GSO_PARTIAL;
4864         }
4865
4866         if (mlx5_vxlan_allowed(mdev->vxlan) || mlx5_geneve_tx_allowed(mdev)) {
4867                 netdev->hw_features     |= NETIF_F_GSO_UDP_TUNNEL |
4868                                            NETIF_F_GSO_UDP_TUNNEL_CSUM;
4869                 netdev->hw_enc_features |= NETIF_F_GSO_UDP_TUNNEL |
4870                                            NETIF_F_GSO_UDP_TUNNEL_CSUM;
4871                 netdev->gso_partial_features = NETIF_F_GSO_UDP_TUNNEL_CSUM;
4872                 netdev->vlan_features |= NETIF_F_GSO_UDP_TUNNEL |
4873                                          NETIF_F_GSO_UDP_TUNNEL_CSUM;
4874         }
4875
4876         if (mlx5e_tunnel_proto_supported(mdev, IPPROTO_GRE)) {
4877                 netdev->hw_features     |= NETIF_F_GSO_GRE |
4878                                            NETIF_F_GSO_GRE_CSUM;
4879                 netdev->hw_enc_features |= NETIF_F_GSO_GRE |
4880                                            NETIF_F_GSO_GRE_CSUM;
4881                 netdev->gso_partial_features |= NETIF_F_GSO_GRE |
4882                                                 NETIF_F_GSO_GRE_CSUM;
4883         }
4884
4885         if (mlx5e_tunnel_proto_supported(mdev, IPPROTO_IPIP)) {
4886                 netdev->hw_features |= NETIF_F_GSO_IPXIP4 |
4887                                        NETIF_F_GSO_IPXIP6;
4888                 netdev->hw_enc_features |= NETIF_F_GSO_IPXIP4 |
4889                                            NETIF_F_GSO_IPXIP6;
4890                 netdev->gso_partial_features |= NETIF_F_GSO_IPXIP4 |
4891                                                 NETIF_F_GSO_IPXIP6;
4892         }
4893
4894         netdev->hw_features                      |= NETIF_F_GSO_PARTIAL;
4895         netdev->gso_partial_features             |= NETIF_F_GSO_UDP_L4;
4896         netdev->hw_features                      |= NETIF_F_GSO_UDP_L4;
4897         netdev->features                         |= NETIF_F_GSO_UDP_L4;
4898
4899         mlx5_query_port_fcs(mdev, &fcs_supported, &fcs_enabled);
4900
4901         if (fcs_supported)
4902                 netdev->hw_features |= NETIF_F_RXALL;
4903
4904         if (MLX5_CAP_ETH(mdev, scatter_fcs))
4905                 netdev->hw_features |= NETIF_F_RXFCS;
4906
4907         netdev->features          = netdev->hw_features;
4908         if (!priv->channels.params.lro_en)
4909                 netdev->features  &= ~NETIF_F_LRO;
4910
4911         if (fcs_enabled)
4912                 netdev->features  &= ~NETIF_F_RXALL;
4913
4914         if (!priv->channels.params.scatter_fcs_en)
4915                 netdev->features  &= ~NETIF_F_RXFCS;
4916
4917         /* prefere CQE compression over rxhash */
4918         if (MLX5E_GET_PFLAG(&priv->channels.params, MLX5E_PFLAG_RX_CQE_COMPRESS))
4919                 netdev->features &= ~NETIF_F_RXHASH;
4920
4921 #define FT_CAP(f) MLX5_CAP_FLOWTABLE(mdev, flow_table_properties_nic_receive.f)
4922         if (FT_CAP(flow_modify_en) &&
4923             FT_CAP(modify_root) &&
4924             FT_CAP(identified_miss_table_mode) &&
4925             FT_CAP(flow_table_modify)) {
4926 #ifdef CONFIG_MLX5_ESWITCH
4927                 netdev->hw_features      |= NETIF_F_HW_TC;
4928 #endif
4929 #ifdef CONFIG_MLX5_EN_ARFS
4930                 netdev->hw_features      |= NETIF_F_NTUPLE;
4931 #endif
4932         }
4933
4934         netdev->features         |= NETIF_F_HIGHDMA;
4935         netdev->features         |= NETIF_F_HW_VLAN_STAG_FILTER;
4936
4937         netdev->priv_flags       |= IFF_UNICAST_FLT;
4938
4939         mlx5e_set_netdev_dev_addr(netdev);
4940         mlx5e_ipsec_build_netdev(priv);
4941         mlx5e_tls_build_netdev(priv);
4942 }
4943
4944 void mlx5e_create_q_counters(struct mlx5e_priv *priv)
4945 {
4946         struct mlx5_core_dev *mdev = priv->mdev;
4947         int err;
4948
4949         err = mlx5_core_alloc_q_counter(mdev, &priv->q_counter);
4950         if (err) {
4951                 mlx5_core_warn(mdev, "alloc queue counter failed, %d\n", err);
4952                 priv->q_counter = 0;
4953         }
4954
4955         err = mlx5_core_alloc_q_counter(mdev, &priv->drop_rq_q_counter);
4956         if (err) {
4957                 mlx5_core_warn(mdev, "alloc drop RQ counter failed, %d\n", err);
4958                 priv->drop_rq_q_counter = 0;
4959         }
4960 }
4961
4962 void mlx5e_destroy_q_counters(struct mlx5e_priv *priv)
4963 {
4964         if (priv->q_counter)
4965                 mlx5_core_dealloc_q_counter(priv->mdev, priv->q_counter);
4966
4967         if (priv->drop_rq_q_counter)
4968                 mlx5_core_dealloc_q_counter(priv->mdev, priv->drop_rq_q_counter);
4969 }
4970
4971 static int mlx5e_nic_init(struct mlx5_core_dev *mdev,
4972                           struct net_device *netdev,
4973                           const struct mlx5e_profile *profile,
4974                           void *ppriv)
4975 {
4976         struct mlx5e_priv *priv = netdev_priv(netdev);
4977         struct mlx5e_rss_params *rss = &priv->rss_params;
4978         int err;
4979
4980         err = mlx5e_netdev_init(netdev, priv, mdev, profile, ppriv);
4981         if (err)
4982                 return err;
4983
4984         mlx5e_build_nic_params(priv, &priv->xsk, rss, &priv->channels.params,
4985                                netdev->mtu);
4986
4987         mlx5e_timestamp_init(priv);
4988
4989         err = mlx5e_ipsec_init(priv);
4990         if (err)
4991                 mlx5_core_err(mdev, "IPSec initialization failed, %d\n", err);
4992         err = mlx5e_tls_init(priv);
4993         if (err)
4994                 mlx5_core_err(mdev, "TLS initialization failed, %d\n", err);
4995         mlx5e_build_nic_netdev(netdev);
4996         mlx5e_health_create_reporters(priv);
4997
4998         return 0;
4999 }
5000
5001 static void mlx5e_nic_cleanup(struct mlx5e_priv *priv)
5002 {
5003         mlx5e_health_destroy_reporters(priv);
5004         mlx5e_tls_cleanup(priv);
5005         mlx5e_ipsec_cleanup(priv);
5006         mlx5e_netdev_cleanup(priv->netdev, priv);
5007 }
5008
5009 static int mlx5e_init_nic_rx(struct mlx5e_priv *priv)
5010 {
5011         struct mlx5_core_dev *mdev = priv->mdev;
5012         int err;
5013
5014         mlx5e_create_q_counters(priv);
5015
5016         err = mlx5e_open_drop_rq(priv, &priv->drop_rq);
5017         if (err) {
5018                 mlx5_core_err(mdev, "open drop rq failed, %d\n", err);
5019                 goto err_destroy_q_counters;
5020         }
5021
5022         err = mlx5e_create_indirect_rqt(priv);
5023         if (err)
5024                 goto err_close_drop_rq;
5025
5026         err = mlx5e_create_direct_rqts(priv, priv->direct_tir);
5027         if (err)
5028                 goto err_destroy_indirect_rqts;
5029
5030         err = mlx5e_create_indirect_tirs(priv, true);
5031         if (err)
5032                 goto err_destroy_direct_rqts;
5033
5034         err = mlx5e_create_direct_tirs(priv, priv->direct_tir);
5035         if (err)
5036                 goto err_destroy_indirect_tirs;
5037
5038         err = mlx5e_create_direct_rqts(priv, priv->xsk_tir);
5039         if (unlikely(err))
5040                 goto err_destroy_direct_tirs;
5041
5042         err = mlx5e_create_direct_tirs(priv, priv->xsk_tir);
5043         if (unlikely(err))
5044                 goto err_destroy_xsk_rqts;
5045
5046         err = mlx5e_create_flow_steering(priv);
5047         if (err) {
5048                 mlx5_core_warn(mdev, "create flow steering failed, %d\n", err);
5049                 goto err_destroy_xsk_tirs;
5050         }
5051
5052         err = mlx5e_tc_nic_init(priv);
5053         if (err)
5054                 goto err_destroy_flow_steering;
5055
5056         return 0;
5057
5058 err_destroy_flow_steering:
5059         mlx5e_destroy_flow_steering(priv);
5060 err_destroy_xsk_tirs:
5061         mlx5e_destroy_direct_tirs(priv, priv->xsk_tir);
5062 err_destroy_xsk_rqts:
5063         mlx5e_destroy_direct_rqts(priv, priv->xsk_tir);
5064 err_destroy_direct_tirs:
5065         mlx5e_destroy_direct_tirs(priv, priv->direct_tir);
5066 err_destroy_indirect_tirs:
5067         mlx5e_destroy_indirect_tirs(priv, true);
5068 err_destroy_direct_rqts:
5069         mlx5e_destroy_direct_rqts(priv, priv->direct_tir);
5070 err_destroy_indirect_rqts:
5071         mlx5e_destroy_rqt(priv, &priv->indir_rqt);
5072 err_close_drop_rq:
5073         mlx5e_close_drop_rq(&priv->drop_rq);
5074 err_destroy_q_counters:
5075         mlx5e_destroy_q_counters(priv);
5076         return err;
5077 }
5078
5079 static void mlx5e_cleanup_nic_rx(struct mlx5e_priv *priv)
5080 {
5081         mlx5e_tc_nic_cleanup(priv);
5082         mlx5e_destroy_flow_steering(priv);
5083         mlx5e_destroy_direct_tirs(priv, priv->xsk_tir);
5084         mlx5e_destroy_direct_rqts(priv, priv->xsk_tir);
5085         mlx5e_destroy_direct_tirs(priv, priv->direct_tir);
5086         mlx5e_destroy_indirect_tirs(priv, true);
5087         mlx5e_destroy_direct_rqts(priv, priv->direct_tir);
5088         mlx5e_destroy_rqt(priv, &priv->indir_rqt);
5089         mlx5e_close_drop_rq(&priv->drop_rq);
5090         mlx5e_destroy_q_counters(priv);
5091 }
5092
5093 static int mlx5e_init_nic_tx(struct mlx5e_priv *priv)
5094 {
5095         int err;
5096
5097         err = mlx5e_create_tises(priv);
5098         if (err) {
5099                 mlx5_core_warn(priv->mdev, "create tises failed, %d\n", err);
5100                 return err;
5101         }
5102
5103 #ifdef CONFIG_MLX5_CORE_EN_DCB
5104         mlx5e_dcbnl_initialize(priv);
5105 #endif
5106         return 0;
5107 }
5108
5109 static void mlx5e_nic_enable(struct mlx5e_priv *priv)
5110 {
5111         struct net_device *netdev = priv->netdev;
5112         struct mlx5_core_dev *mdev = priv->mdev;
5113
5114         mlx5e_init_l2_addr(priv);
5115
5116         /* Marking the link as currently not needed by the Driver */
5117         if (!netif_running(netdev))
5118                 mlx5_set_port_admin_status(mdev, MLX5_PORT_DOWN);
5119
5120         mlx5e_set_netdev_mtu_boundaries(priv);
5121         mlx5e_set_dev_port_mtu(priv);
5122
5123         mlx5_lag_add(mdev, netdev);
5124
5125         mlx5e_enable_async_events(priv);
5126         if (mlx5e_monitor_counter_supported(priv))
5127                 mlx5e_monitor_counter_init(priv);
5128
5129         mlx5e_hv_vhca_stats_create(priv);
5130         if (netdev->reg_state != NETREG_REGISTERED)
5131                 return;
5132 #ifdef CONFIG_MLX5_CORE_EN_DCB
5133         mlx5e_dcbnl_init_app(priv);
5134 #endif
5135
5136         queue_work(priv->wq, &priv->set_rx_mode_work);
5137
5138         rtnl_lock();
5139         if (netif_running(netdev))
5140                 mlx5e_open(netdev);
5141         netif_device_attach(netdev);
5142         rtnl_unlock();
5143 }
5144
5145 static void mlx5e_nic_disable(struct mlx5e_priv *priv)
5146 {
5147         struct net_device *netdev = priv->netdev;
5148         struct mlx5_core_dev *mdev = priv->mdev;
5149
5150 #ifdef CONFIG_MLX5_CORE_EN_DCB
5151         if (priv->netdev->reg_state == NETREG_REGISTERED)
5152                 mlx5e_dcbnl_delete_app(priv);
5153 #endif
5154
5155         rtnl_lock();
5156         if (netif_running(priv->netdev))
5157                 mlx5e_close(priv->netdev);
5158         netif_device_detach(priv->netdev);
5159         rtnl_unlock();
5160
5161         queue_work(priv->wq, &priv->set_rx_mode_work);
5162
5163         mlx5e_hv_vhca_stats_destroy(priv);
5164         if (mlx5e_monitor_counter_supported(priv))
5165                 mlx5e_monitor_counter_cleanup(priv);
5166
5167         mlx5e_disable_async_events(priv);
5168         mlx5_lag_remove(mdev, netdev);
5169 }
5170
5171 int mlx5e_update_nic_rx(struct mlx5e_priv *priv)
5172 {
5173         return mlx5e_refresh_tirs(priv, false);
5174 }
5175
5176 static const struct mlx5e_profile mlx5e_nic_profile = {
5177         .init              = mlx5e_nic_init,
5178         .cleanup           = mlx5e_nic_cleanup,
5179         .init_rx           = mlx5e_init_nic_rx,
5180         .cleanup_rx        = mlx5e_cleanup_nic_rx,
5181         .init_tx           = mlx5e_init_nic_tx,
5182         .cleanup_tx        = mlx5e_cleanup_nic_tx,
5183         .enable            = mlx5e_nic_enable,
5184         .disable           = mlx5e_nic_disable,
5185         .update_rx         = mlx5e_update_nic_rx,
5186         .update_stats      = mlx5e_update_ndo_stats,
5187         .update_carrier    = mlx5e_update_carrier,
5188         .rx_handlers.handle_rx_cqe       = mlx5e_handle_rx_cqe,
5189         .rx_handlers.handle_rx_cqe_mpwqe = mlx5e_handle_rx_cqe_mpwrq,
5190         .max_tc            = MLX5E_MAX_NUM_TC,
5191         .rq_groups         = MLX5E_NUM_RQ_GROUPS(XSK),
5192         .stats_grps        = mlx5e_nic_stats_grps,
5193         .stats_grps_num    = mlx5e_nic_stats_grps_num,
5194 };
5195
5196 /* mlx5e generic netdev management API (move to en_common.c) */
5197
5198 /* mlx5e_netdev_init/cleanup must be called from profile->init/cleanup callbacks */
5199 int mlx5e_netdev_init(struct net_device *netdev,
5200                       struct mlx5e_priv *priv,
5201                       struct mlx5_core_dev *mdev,
5202                       const struct mlx5e_profile *profile,
5203                       void *ppriv)
5204 {
5205         /* priv init */
5206         priv->mdev        = mdev;
5207         priv->netdev      = netdev;
5208         priv->profile     = profile;
5209         priv->ppriv       = ppriv;
5210         priv->msglevel    = MLX5E_MSG_LEVEL;
5211         priv->max_nch     = netdev->num_rx_queues / max_t(u8, profile->rq_groups, 1);
5212         priv->max_opened_tc = 1;
5213
5214         mutex_init(&priv->state_lock);
5215         INIT_WORK(&priv->update_carrier_work, mlx5e_update_carrier_work);
5216         INIT_WORK(&priv->set_rx_mode_work, mlx5e_set_rx_mode_work);
5217         INIT_WORK(&priv->tx_timeout_work, mlx5e_tx_timeout_work);
5218         INIT_WORK(&priv->update_stats_work, mlx5e_update_stats_work);
5219
5220         priv->wq = create_singlethread_workqueue("mlx5e");
5221         if (!priv->wq)
5222                 return -ENOMEM;
5223
5224         /* netdev init */
5225         netif_carrier_off(netdev);
5226
5227 #ifdef CONFIG_MLX5_EN_ARFS
5228         netdev->rx_cpu_rmap =  mlx5_eq_table_get_rmap(mdev);
5229 #endif
5230
5231         return 0;
5232 }
5233
5234 void mlx5e_netdev_cleanup(struct net_device *netdev, struct mlx5e_priv *priv)
5235 {
5236         destroy_workqueue(priv->wq);
5237 }
5238
5239 struct net_device *mlx5e_create_netdev(struct mlx5_core_dev *mdev,
5240                                        const struct mlx5e_profile *profile,
5241                                        int nch,
5242                                        void *ppriv)
5243 {
5244         struct net_device *netdev;
5245         int err;
5246
5247         netdev = alloc_etherdev_mqs(sizeof(struct mlx5e_priv),
5248                                     nch * profile->max_tc,
5249                                     nch * profile->rq_groups);
5250         if (!netdev) {
5251                 mlx5_core_err(mdev, "alloc_etherdev_mqs() failed\n");
5252                 return NULL;
5253         }
5254
5255         err = profile->init(mdev, netdev, profile, ppriv);
5256         if (err) {
5257                 mlx5_core_err(mdev, "failed to init mlx5e profile %d\n", err);
5258                 goto err_free_netdev;
5259         }
5260
5261         return netdev;
5262
5263 err_free_netdev:
5264         free_netdev(netdev);
5265
5266         return NULL;
5267 }
5268
5269 int mlx5e_attach_netdev(struct mlx5e_priv *priv)
5270 {
5271         const struct mlx5e_profile *profile;
5272         int max_nch;
5273         int err;
5274
5275         profile = priv->profile;
5276         clear_bit(MLX5E_STATE_DESTROYING, &priv->state);
5277
5278         /* max number of channels may have changed */
5279         max_nch = mlx5e_get_max_num_channels(priv->mdev);
5280         if (priv->channels.params.num_channels > max_nch) {
5281                 mlx5_core_warn(priv->mdev, "MLX5E: Reducing number of channels to %d\n", max_nch);
5282                 priv->channels.params.num_channels = max_nch;
5283                 mlx5e_build_default_indir_rqt(priv->rss_params.indirection_rqt,
5284                                               MLX5E_INDIR_RQT_SIZE, max_nch);
5285         }
5286
5287         err = profile->init_tx(priv);
5288         if (err)
5289                 goto out;
5290
5291         err = profile->init_rx(priv);
5292         if (err)
5293                 goto err_cleanup_tx;
5294
5295         if (profile->enable)
5296                 profile->enable(priv);
5297
5298         return 0;
5299
5300 err_cleanup_tx:
5301         profile->cleanup_tx(priv);
5302
5303 out:
5304         return err;
5305 }
5306
5307 void mlx5e_detach_netdev(struct mlx5e_priv *priv)
5308 {
5309         const struct mlx5e_profile *profile = priv->profile;
5310
5311         set_bit(MLX5E_STATE_DESTROYING, &priv->state);
5312
5313         if (profile->disable)
5314                 profile->disable(priv);
5315         flush_workqueue(priv->wq);
5316
5317         profile->cleanup_rx(priv);
5318         profile->cleanup_tx(priv);
5319         cancel_work_sync(&priv->update_stats_work);
5320 }
5321
5322 void mlx5e_destroy_netdev(struct mlx5e_priv *priv)
5323 {
5324         const struct mlx5e_profile *profile = priv->profile;
5325         struct net_device *netdev = priv->netdev;
5326
5327         if (profile->cleanup)
5328                 profile->cleanup(priv);
5329         free_netdev(netdev);
5330 }
5331
5332 /* mlx5e_attach and mlx5e_detach scope should be only creating/destroying
5333  * hardware contexts and to connect it to the current netdev.
5334  */
5335 static int mlx5e_attach(struct mlx5_core_dev *mdev, void *vpriv)
5336 {
5337         struct mlx5e_priv *priv = vpriv;
5338         struct net_device *netdev = priv->netdev;
5339         int err;
5340
5341         if (netif_device_present(netdev))
5342                 return 0;
5343
5344         err = mlx5e_create_mdev_resources(mdev);
5345         if (err)
5346                 return err;
5347
5348         err = mlx5e_attach_netdev(priv);
5349         if (err) {
5350                 mlx5e_destroy_mdev_resources(mdev);
5351                 return err;
5352         }
5353
5354         return 0;
5355 }
5356
5357 static void mlx5e_detach(struct mlx5_core_dev *mdev, void *vpriv)
5358 {
5359         struct mlx5e_priv *priv = vpriv;
5360         struct net_device *netdev = priv->netdev;
5361
5362 #ifdef CONFIG_MLX5_ESWITCH
5363         if (MLX5_ESWITCH_MANAGER(mdev) && vpriv == mdev)
5364                 return;
5365 #endif
5366
5367         if (!netif_device_present(netdev))
5368                 return;
5369
5370         mlx5e_detach_netdev(priv);
5371         mlx5e_destroy_mdev_resources(mdev);
5372 }
5373
5374 static void *mlx5e_add(struct mlx5_core_dev *mdev)
5375 {
5376         struct net_device *netdev;
5377         void *priv;
5378         int err;
5379         int nch;
5380
5381         err = mlx5e_check_required_hca_cap(mdev);
5382         if (err)
5383                 return NULL;
5384
5385 #ifdef CONFIG_MLX5_ESWITCH
5386         if (MLX5_ESWITCH_MANAGER(mdev) &&
5387             mlx5_eswitch_mode(mdev->priv.eswitch) == MLX5_ESWITCH_OFFLOADS) {
5388                 mlx5e_rep_register_vport_reps(mdev);
5389                 return mdev;
5390         }
5391 #endif
5392
5393         nch = mlx5e_get_max_num_channels(mdev);
5394         netdev = mlx5e_create_netdev(mdev, &mlx5e_nic_profile, nch, NULL);
5395         if (!netdev) {
5396                 mlx5_core_err(mdev, "mlx5e_create_netdev failed\n");
5397                 return NULL;
5398         }
5399
5400         dev_net_set(netdev, mlx5_core_net(mdev));
5401         priv = netdev_priv(netdev);
5402
5403         err = mlx5e_attach(mdev, priv);
5404         if (err) {
5405                 mlx5_core_err(mdev, "mlx5e_attach failed, %d\n", err);
5406                 goto err_destroy_netdev;
5407         }
5408
5409         err = register_netdev(netdev);
5410         if (err) {
5411                 mlx5_core_err(mdev, "register_netdev failed, %d\n", err);
5412                 goto err_detach;
5413         }
5414
5415 #ifdef CONFIG_MLX5_CORE_EN_DCB
5416         mlx5e_dcbnl_init_app(priv);
5417 #endif
5418         return priv;
5419
5420 err_detach:
5421         mlx5e_detach(mdev, priv);
5422 err_destroy_netdev:
5423         mlx5e_destroy_netdev(priv);
5424         return NULL;
5425 }
5426
5427 static void mlx5e_remove(struct mlx5_core_dev *mdev, void *vpriv)
5428 {
5429         struct mlx5e_priv *priv;
5430
5431 #ifdef CONFIG_MLX5_ESWITCH
5432         if (MLX5_ESWITCH_MANAGER(mdev) && vpriv == mdev) {
5433                 mlx5e_rep_unregister_vport_reps(mdev);
5434                 return;
5435         }
5436 #endif
5437         priv = vpriv;
5438 #ifdef CONFIG_MLX5_CORE_EN_DCB
5439         mlx5e_dcbnl_delete_app(priv);
5440 #endif
5441         unregister_netdev(priv->netdev);
5442         mlx5e_detach(mdev, vpriv);
5443         mlx5e_destroy_netdev(priv);
5444 }
5445
5446 static struct mlx5_interface mlx5e_interface = {
5447         .add       = mlx5e_add,
5448         .remove    = mlx5e_remove,
5449         .attach    = mlx5e_attach,
5450         .detach    = mlx5e_detach,
5451         .protocol  = MLX5_INTERFACE_PROTOCOL_ETH,
5452 };
5453
5454 void mlx5e_init(void)
5455 {
5456         mlx5e_ipsec_build_inverse_table();
5457         mlx5e_build_ptys2ethtool_map();
5458         mlx5_register_interface(&mlx5e_interface);
5459 }
5460
5461 void mlx5e_cleanup(void)
5462 {
5463         mlx5_unregister_interface(&mlx5e_interface);
5464 }