2 * Copyright (c) 2015-2016, Mellanox Technologies. All rights reserved.
4 * This software is available to you under a choice of one of two
5 * licenses. You may choose to be licensed under the terms of the GNU
6 * General Public License (GPL) Version 2, available from the file
7 * COPYING in the main directory of this source tree, or the
8 * OpenIB.org BSD license below:
10 * Redistribution and use in source and binary forms, with or
11 * without modification, are permitted provided that the following
14 * - Redistributions of source code must retain the above
15 * copyright notice, this list of conditions and the following
18 * - Redistributions in binary form must reproduce the above
19 * copyright notice, this list of conditions and the following
20 * disclaimer in the documentation and/or other materials
21 * provided with the distribution.
23 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
24 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
25 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
26 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
27 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
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29 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
33 #include <net/tc_act/tc_gact.h>
34 #include <net/pkt_cls.h>
35 #include <linux/mlx5/fs.h>
36 #include <net/vxlan.h>
37 #include <linux/bpf.h>
38 #include <net/page_pool.h>
43 #include "en_accel/ipsec.h"
44 #include "en_accel/ipsec_rxtx.h"
45 #include "en_accel/tls.h"
46 #include "accel/ipsec.h"
47 #include "accel/tls.h"
51 struct mlx5e_rq_param {
52 u32 rqc[MLX5_ST_SZ_DW(rqc)];
53 struct mlx5_wq_param wq;
54 struct mlx5e_rq_frags_info frags_info;
57 struct mlx5e_sq_param {
58 u32 sqc[MLX5_ST_SZ_DW(sqc)];
59 struct mlx5_wq_param wq;
62 struct mlx5e_cq_param {
63 u32 cqc[MLX5_ST_SZ_DW(cqc)];
64 struct mlx5_wq_param wq;
69 struct mlx5e_channel_param {
70 struct mlx5e_rq_param rq;
71 struct mlx5e_sq_param sq;
72 struct mlx5e_sq_param xdp_sq;
73 struct mlx5e_sq_param icosq;
74 struct mlx5e_cq_param rx_cq;
75 struct mlx5e_cq_param tx_cq;
76 struct mlx5e_cq_param icosq_cq;
79 bool mlx5e_check_fragmented_striding_rq_cap(struct mlx5_core_dev *mdev)
81 bool striding_rq_umr = MLX5_CAP_GEN(mdev, striding_rq) &&
82 MLX5_CAP_GEN(mdev, umr_ptr_rlky) &&
83 MLX5_CAP_ETH(mdev, reg_umr_sq);
84 u16 max_wqe_sz_cap = MLX5_CAP_GEN(mdev, max_wqe_sz_sq);
85 bool inline_umr = MLX5E_UMR_WQE_INLINE_SZ <= max_wqe_sz_cap;
90 mlx5_core_warn(mdev, "Cannot support Striding RQ: UMR WQE size (%d) exceeds maximum supported (%d).\n",
91 (int)MLX5E_UMR_WQE_INLINE_SZ, max_wqe_sz_cap);
97 static u32 mlx5e_rx_get_linear_frag_sz(struct mlx5e_params *params)
99 if (!params->xdp_prog) {
100 u16 hw_mtu = MLX5E_SW2HW_MTU(params, params->sw_mtu);
101 u16 rq_headroom = MLX5_RX_HEADROOM + NET_IP_ALIGN;
103 return MLX5_SKB_FRAG_SZ(rq_headroom + hw_mtu);
109 static u8 mlx5e_mpwqe_log_pkts_per_wqe(struct mlx5e_params *params)
111 u32 linear_frag_sz = mlx5e_rx_get_linear_frag_sz(params);
113 return MLX5_MPWRQ_LOG_WQE_SZ - order_base_2(linear_frag_sz);
116 static bool mlx5e_rx_is_linear_skb(struct mlx5_core_dev *mdev,
117 struct mlx5e_params *params)
119 u32 frag_sz = mlx5e_rx_get_linear_frag_sz(params);
121 return !params->lro_en && frag_sz <= PAGE_SIZE;
124 static bool mlx5e_rx_mpwqe_is_linear_skb(struct mlx5_core_dev *mdev,
125 struct mlx5e_params *params)
127 u32 frag_sz = mlx5e_rx_get_linear_frag_sz(params);
128 s8 signed_log_num_strides_param;
131 if (!mlx5e_rx_is_linear_skb(mdev, params))
134 if (MLX5_CAP_GEN(mdev, ext_stride_num_range))
137 log_num_strides = MLX5_MPWRQ_LOG_WQE_SZ - order_base_2(frag_sz);
138 signed_log_num_strides_param =
139 (s8)log_num_strides - MLX5_MPWQE_LOG_NUM_STRIDES_BASE;
141 return signed_log_num_strides_param >= 0;
144 static u8 mlx5e_mpwqe_get_log_rq_size(struct mlx5e_params *params)
146 if (params->log_rq_mtu_frames <
147 mlx5e_mpwqe_log_pkts_per_wqe(params) + MLX5E_PARAMS_MINIMUM_LOG_RQ_SIZE_MPW)
148 return MLX5E_PARAMS_MINIMUM_LOG_RQ_SIZE_MPW;
150 return params->log_rq_mtu_frames - mlx5e_mpwqe_log_pkts_per_wqe(params);
153 static u8 mlx5e_mpwqe_get_log_stride_size(struct mlx5_core_dev *mdev,
154 struct mlx5e_params *params)
156 if (mlx5e_rx_mpwqe_is_linear_skb(mdev, params))
157 return order_base_2(mlx5e_rx_get_linear_frag_sz(params));
159 return MLX5E_MPWQE_STRIDE_SZ(mdev,
160 MLX5E_GET_PFLAG(params, MLX5E_PFLAG_RX_CQE_COMPRESS));
163 static u8 mlx5e_mpwqe_get_log_num_strides(struct mlx5_core_dev *mdev,
164 struct mlx5e_params *params)
166 return MLX5_MPWRQ_LOG_WQE_SZ -
167 mlx5e_mpwqe_get_log_stride_size(mdev, params);
170 static u16 mlx5e_get_rq_headroom(struct mlx5_core_dev *mdev,
171 struct mlx5e_params *params)
173 u16 linear_rq_headroom = params->xdp_prog ?
174 XDP_PACKET_HEADROOM : MLX5_RX_HEADROOM;
177 linear_rq_headroom += NET_IP_ALIGN;
179 is_linear_skb = (params->rq_wq_type == MLX5_WQ_TYPE_CYCLIC) ?
180 mlx5e_rx_is_linear_skb(mdev, params) :
181 mlx5e_rx_mpwqe_is_linear_skb(mdev, params);
183 return is_linear_skb ? linear_rq_headroom : 0;
186 void mlx5e_init_rq_type_params(struct mlx5_core_dev *mdev,
187 struct mlx5e_params *params)
189 params->lro_wqe_sz = MLX5E_PARAMS_DEFAULT_LRO_WQE_SZ;
190 params->log_rq_mtu_frames = is_kdump_kernel() ?
191 MLX5E_PARAMS_MINIMUM_LOG_RQ_SIZE :
192 MLX5E_PARAMS_DEFAULT_LOG_RQ_SIZE;
194 mlx5_core_info(mdev, "MLX5E: StrdRq(%d) RqSz(%ld) StrdSz(%ld) RxCqeCmprss(%d)\n",
195 params->rq_wq_type == MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ,
196 params->rq_wq_type == MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ ?
197 BIT(mlx5e_mpwqe_get_log_rq_size(params)) :
198 BIT(params->log_rq_mtu_frames),
199 BIT(mlx5e_mpwqe_get_log_stride_size(mdev, params)),
200 MLX5E_GET_PFLAG(params, MLX5E_PFLAG_RX_CQE_COMPRESS));
203 bool mlx5e_striding_rq_possible(struct mlx5_core_dev *mdev,
204 struct mlx5e_params *params)
206 return mlx5e_check_fragmented_striding_rq_cap(mdev) &&
207 !MLX5_IPSEC_DEV(mdev) &&
208 !(params->xdp_prog && !mlx5e_rx_mpwqe_is_linear_skb(mdev, params));
211 void mlx5e_set_rq_type(struct mlx5_core_dev *mdev, struct mlx5e_params *params)
213 params->rq_wq_type = mlx5e_striding_rq_possible(mdev, params) &&
214 MLX5E_GET_PFLAG(params, MLX5E_PFLAG_RX_STRIDING_RQ) ?
215 MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ :
219 static void mlx5e_update_carrier(struct mlx5e_priv *priv)
221 struct mlx5_core_dev *mdev = priv->mdev;
224 port_state = mlx5_query_vport_state(mdev,
225 MLX5_QUERY_VPORT_STATE_IN_OP_MOD_VNIC_VPORT,
228 if (port_state == VPORT_STATE_UP) {
229 netdev_info(priv->netdev, "Link up\n");
230 netif_carrier_on(priv->netdev);
232 netdev_info(priv->netdev, "Link down\n");
233 netif_carrier_off(priv->netdev);
237 static void mlx5e_update_carrier_work(struct work_struct *work)
239 struct mlx5e_priv *priv = container_of(work, struct mlx5e_priv,
240 update_carrier_work);
242 mutex_lock(&priv->state_lock);
243 if (test_bit(MLX5E_STATE_OPENED, &priv->state))
244 if (priv->profile->update_carrier)
245 priv->profile->update_carrier(priv);
246 mutex_unlock(&priv->state_lock);
249 void mlx5e_update_stats(struct mlx5e_priv *priv)
253 for (i = mlx5e_num_stats_grps - 1; i >= 0; i--)
254 if (mlx5e_stats_grps[i].update_stats)
255 mlx5e_stats_grps[i].update_stats(priv);
258 static void mlx5e_update_ndo_stats(struct mlx5e_priv *priv)
262 for (i = mlx5e_num_stats_grps - 1; i >= 0; i--)
263 if (mlx5e_stats_grps[i].update_stats_mask &
264 MLX5E_NDO_UPDATE_STATS)
265 mlx5e_stats_grps[i].update_stats(priv);
268 void mlx5e_update_stats_work(struct work_struct *work)
270 struct delayed_work *dwork = to_delayed_work(work);
271 struct mlx5e_priv *priv = container_of(dwork, struct mlx5e_priv,
273 mutex_lock(&priv->state_lock);
274 if (test_bit(MLX5E_STATE_OPENED, &priv->state)) {
275 priv->profile->update_stats(priv);
276 queue_delayed_work(priv->wq, dwork,
277 msecs_to_jiffies(MLX5E_UPDATE_STATS_INTERVAL));
279 mutex_unlock(&priv->state_lock);
282 static void mlx5e_async_event(struct mlx5_core_dev *mdev, void *vpriv,
283 enum mlx5_dev_event event, unsigned long param)
285 struct mlx5e_priv *priv = vpriv;
287 if (!test_bit(MLX5E_STATE_ASYNC_EVENTS_ENABLED, &priv->state))
291 case MLX5_DEV_EVENT_PORT_UP:
292 case MLX5_DEV_EVENT_PORT_DOWN:
293 queue_work(priv->wq, &priv->update_carrier_work);
300 static void mlx5e_enable_async_events(struct mlx5e_priv *priv)
302 set_bit(MLX5E_STATE_ASYNC_EVENTS_ENABLED, &priv->state);
305 static void mlx5e_disable_async_events(struct mlx5e_priv *priv)
307 clear_bit(MLX5E_STATE_ASYNC_EVENTS_ENABLED, &priv->state);
308 synchronize_irq(pci_irq_vector(priv->mdev->pdev, MLX5_EQ_VEC_ASYNC));
311 static inline void mlx5e_build_umr_wqe(struct mlx5e_rq *rq,
312 struct mlx5e_icosq *sq,
313 struct mlx5e_umr_wqe *wqe)
315 struct mlx5_wqe_ctrl_seg *cseg = &wqe->ctrl;
316 struct mlx5_wqe_umr_ctrl_seg *ucseg = &wqe->uctrl;
317 u8 ds_cnt = DIV_ROUND_UP(MLX5E_UMR_WQE_INLINE_SZ, MLX5_SEND_WQE_DS);
319 cseg->qpn_ds = cpu_to_be32((sq->sqn << MLX5_WQE_CTRL_QPN_SHIFT) |
321 cseg->fm_ce_se = MLX5_WQE_CTRL_CQ_UPDATE;
322 cseg->imm = rq->mkey_be;
324 ucseg->flags = MLX5_UMR_TRANSLATION_OFFSET_EN | MLX5_UMR_INLINE;
325 ucseg->xlt_octowords =
326 cpu_to_be16(MLX5_MTT_OCTW(MLX5_MPWRQ_PAGES_PER_WQE));
327 ucseg->mkey_mask = cpu_to_be64(MLX5_MKEY_MASK_FREE);
330 static u32 mlx5e_rqwq_get_size(struct mlx5e_rq *rq)
332 switch (rq->wq_type) {
333 case MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ:
334 return mlx5_wq_ll_get_size(&rq->mpwqe.wq);
336 return mlx5_wq_cyc_get_size(&rq->wqe.wq);
340 static u32 mlx5e_rqwq_get_cur_sz(struct mlx5e_rq *rq)
342 switch (rq->wq_type) {
343 case MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ:
344 return rq->mpwqe.wq.cur_sz;
346 return rq->wqe.wq.cur_sz;
350 static int mlx5e_rq_alloc_mpwqe_info(struct mlx5e_rq *rq,
351 struct mlx5e_channel *c)
353 int wq_sz = mlx5_wq_ll_get_size(&rq->mpwqe.wq);
355 rq->mpwqe.info = kvzalloc_node(wq_sz * sizeof(*rq->mpwqe.info),
356 GFP_KERNEL, cpu_to_node(c->cpu));
360 mlx5e_build_umr_wqe(rq, &c->icosq, &rq->mpwqe.umr_wqe);
365 static int mlx5e_create_umr_mkey(struct mlx5_core_dev *mdev,
366 u64 npages, u8 page_shift,
367 struct mlx5_core_mkey *umr_mkey)
369 int inlen = MLX5_ST_SZ_BYTES(create_mkey_in);
374 in = kvzalloc(inlen, GFP_KERNEL);
378 mkc = MLX5_ADDR_OF(create_mkey_in, in, memory_key_mkey_entry);
380 MLX5_SET(mkc, mkc, free, 1);
381 MLX5_SET(mkc, mkc, umr_en, 1);
382 MLX5_SET(mkc, mkc, lw, 1);
383 MLX5_SET(mkc, mkc, lr, 1);
384 MLX5_SET(mkc, mkc, access_mode_1_0, MLX5_MKC_ACCESS_MODE_MTT);
386 MLX5_SET(mkc, mkc, qpn, 0xffffff);
387 MLX5_SET(mkc, mkc, pd, mdev->mlx5e_res.pdn);
388 MLX5_SET64(mkc, mkc, len, npages << page_shift);
389 MLX5_SET(mkc, mkc, translations_octword_size,
390 MLX5_MTT_OCTW(npages));
391 MLX5_SET(mkc, mkc, log_page_size, page_shift);
393 err = mlx5_core_create_mkey(mdev, umr_mkey, in, inlen);
399 static int mlx5e_create_rq_umr_mkey(struct mlx5_core_dev *mdev, struct mlx5e_rq *rq)
401 u64 num_mtts = MLX5E_REQUIRED_MTTS(mlx5_wq_ll_get_size(&rq->mpwqe.wq));
403 return mlx5e_create_umr_mkey(mdev, num_mtts, PAGE_SHIFT, &rq->umr_mkey);
406 static inline u64 mlx5e_get_mpwqe_offset(struct mlx5e_rq *rq, u16 wqe_ix)
408 return (wqe_ix << MLX5E_LOG_ALIGNED_MPWQE_PPW) << PAGE_SHIFT;
411 static void mlx5e_init_frags_partition(struct mlx5e_rq *rq)
413 struct mlx5e_wqe_frag_info next_frag, *prev;
416 next_frag.di = &rq->wqe.di[0];
417 next_frag.offset = 0;
420 for (i = 0; i < mlx5_wq_cyc_get_size(&rq->wqe.wq); i++) {
421 struct mlx5e_rq_frag_info *frag_info = &rq->wqe.info.arr[0];
422 struct mlx5e_wqe_frag_info *frag =
423 &rq->wqe.frags[i << rq->wqe.info.log_num_frags];
426 for (f = 0; f < rq->wqe.info.num_frags; f++, frag++) {
427 if (next_frag.offset + frag_info[f].frag_stride > PAGE_SIZE) {
429 next_frag.offset = 0;
431 prev->last_in_page = true;
436 next_frag.offset += frag_info[f].frag_stride;
442 prev->last_in_page = true;
445 static int mlx5e_init_di_list(struct mlx5e_rq *rq,
446 struct mlx5e_params *params,
449 int len = wq_sz << rq->wqe.info.log_num_frags;
451 rq->wqe.di = kvzalloc_node(array_size(len, sizeof(*rq->wqe.di)),
452 GFP_KERNEL, cpu_to_node(cpu));
456 mlx5e_init_frags_partition(rq);
461 static void mlx5e_free_di_list(struct mlx5e_rq *rq)
466 static int mlx5e_alloc_rq(struct mlx5e_channel *c,
467 struct mlx5e_params *params,
468 struct mlx5e_rq_param *rqp,
471 struct page_pool_params pp_params = { 0 };
472 struct mlx5_core_dev *mdev = c->mdev;
473 void *rqc = rqp->rqc;
474 void *rqc_wq = MLX5_ADDR_OF(rqc, rqc, wq);
480 rqp->wq.db_numa_node = cpu_to_node(c->cpu);
482 rq->wq_type = params->rq_wq_type;
484 rq->netdev = c->netdev;
485 rq->tstamp = c->tstamp;
486 rq->clock = &mdev->clock;
490 rq->hw_mtu = MLX5E_SW2HW_MTU(params, params->sw_mtu);
491 rq->stats = &c->priv->channel_stats[c->ix].rq;
493 rq->xdp_prog = params->xdp_prog ? bpf_prog_inc(params->xdp_prog) : NULL;
494 if (IS_ERR(rq->xdp_prog)) {
495 err = PTR_ERR(rq->xdp_prog);
497 goto err_rq_wq_destroy;
500 err = xdp_rxq_info_reg(&rq->xdp_rxq, rq->netdev, rq->ix);
502 goto err_rq_wq_destroy;
504 rq->buff.map_dir = rq->xdp_prog ? DMA_BIDIRECTIONAL : DMA_FROM_DEVICE;
505 rq->buff.headroom = mlx5e_get_rq_headroom(mdev, params);
506 pool_size = 1 << params->log_rq_mtu_frames;
508 switch (rq->wq_type) {
509 case MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ:
510 err = mlx5_wq_ll_create(mdev, &rqp->wq, rqc_wq, &rq->mpwqe.wq,
515 rq->mpwqe.wq.db = &rq->mpwqe.wq.db[MLX5_RCV_DBR];
517 wq_sz = mlx5_wq_ll_get_size(&rq->mpwqe.wq);
519 pool_size = MLX5_MPWRQ_PAGES_PER_WQE << mlx5e_mpwqe_get_log_rq_size(params);
521 rq->post_wqes = mlx5e_post_rx_mpwqes;
522 rq->dealloc_wqe = mlx5e_dealloc_rx_mpwqe;
524 rq->handle_rx_cqe = c->priv->profile->rx_handlers.handle_rx_cqe_mpwqe;
525 #ifdef CONFIG_MLX5_EN_IPSEC
526 if (MLX5_IPSEC_DEV(mdev)) {
528 netdev_err(c->netdev, "MPWQE RQ with IPSec offload not supported\n");
529 goto err_rq_wq_destroy;
532 if (!rq->handle_rx_cqe) {
534 netdev_err(c->netdev, "RX handler of MPWQE RQ is not set, err %d\n", err);
535 goto err_rq_wq_destroy;
538 rq->mpwqe.skb_from_cqe_mpwrq =
539 mlx5e_rx_mpwqe_is_linear_skb(mdev, params) ?
540 mlx5e_skb_from_cqe_mpwrq_linear :
541 mlx5e_skb_from_cqe_mpwrq_nonlinear;
542 rq->mpwqe.log_stride_sz = mlx5e_mpwqe_get_log_stride_size(mdev, params);
543 rq->mpwqe.num_strides = BIT(mlx5e_mpwqe_get_log_num_strides(mdev, params));
545 err = mlx5e_create_rq_umr_mkey(mdev, rq);
547 goto err_rq_wq_destroy;
548 rq->mkey_be = cpu_to_be32(rq->umr_mkey.key);
550 err = mlx5e_rq_alloc_mpwqe_info(rq, c);
554 default: /* MLX5_WQ_TYPE_CYCLIC */
555 err = mlx5_wq_cyc_create(mdev, &rqp->wq, rqc_wq, &rq->wqe.wq,
560 rq->wqe.wq.db = &rq->wqe.wq.db[MLX5_RCV_DBR];
562 wq_sz = mlx5_wq_cyc_get_size(&rq->wqe.wq);
564 rq->wqe.info = rqp->frags_info;
566 kvzalloc_node(array_size(sizeof(*rq->wqe.frags),
567 (wq_sz << rq->wqe.info.log_num_frags)),
568 GFP_KERNEL, cpu_to_node(c->cpu));
569 if (!rq->wqe.frags) {
574 err = mlx5e_init_di_list(rq, params, wq_sz, c->cpu);
577 rq->post_wqes = mlx5e_post_rx_wqes;
578 rq->dealloc_wqe = mlx5e_dealloc_rx_wqe;
580 #ifdef CONFIG_MLX5_EN_IPSEC
582 rq->handle_rx_cqe = mlx5e_ipsec_handle_rx_cqe;
585 rq->handle_rx_cqe = c->priv->profile->rx_handlers.handle_rx_cqe;
586 if (!rq->handle_rx_cqe) {
588 netdev_err(c->netdev, "RX handler of RQ is not set, err %d\n", err);
592 rq->wqe.skb_from_cqe = mlx5e_rx_is_linear_skb(mdev, params) ?
593 mlx5e_skb_from_cqe_linear :
594 mlx5e_skb_from_cqe_nonlinear;
595 rq->mkey_be = c->mkey_be;
598 /* Create a page_pool and register it with rxq */
600 pp_params.flags = 0; /* No-internal DMA mapping in page_pool */
601 pp_params.pool_size = pool_size;
602 pp_params.nid = cpu_to_node(c->cpu);
603 pp_params.dev = c->pdev;
604 pp_params.dma_dir = rq->buff.map_dir;
606 /* page_pool can be used even when there is no rq->xdp_prog,
607 * given page_pool does not handle DMA mapping there is no
608 * required state to clear. And page_pool gracefully handle
611 rq->page_pool = page_pool_create(&pp_params);
612 if (IS_ERR(rq->page_pool)) {
613 err = PTR_ERR(rq->page_pool);
614 rq->page_pool = NULL;
617 err = xdp_rxq_info_reg_mem_model(&rq->xdp_rxq,
618 MEM_TYPE_PAGE_POOL, rq->page_pool);
622 for (i = 0; i < wq_sz; i++) {
623 if (rq->wq_type == MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ) {
624 struct mlx5e_rx_wqe_ll *wqe =
625 mlx5_wq_ll_get_wqe(&rq->mpwqe.wq, i);
627 rq->mpwqe.num_strides << rq->mpwqe.log_stride_sz;
628 u64 dma_offset = mlx5e_get_mpwqe_offset(rq, i);
630 wqe->data[0].addr = cpu_to_be64(dma_offset + rq->buff.headroom);
631 wqe->data[0].byte_count = cpu_to_be32(byte_count);
632 wqe->data[0].lkey = rq->mkey_be;
634 struct mlx5e_rx_wqe_cyc *wqe =
635 mlx5_wq_cyc_get_wqe(&rq->wqe.wq, i);
638 for (f = 0; f < rq->wqe.info.num_frags; f++) {
639 u32 frag_size = rq->wqe.info.arr[f].frag_size |
640 MLX5_HW_START_PADDING;
642 wqe->data[f].byte_count = cpu_to_be32(frag_size);
643 wqe->data[f].lkey = rq->mkey_be;
645 /* check if num_frags is not a pow of two */
646 if (rq->wqe.info.num_frags < (1 << rq->wqe.info.log_num_frags)) {
647 wqe->data[f].byte_count = 0;
648 wqe->data[f].lkey = cpu_to_be32(MLX5_INVALID_LKEY);
649 wqe->data[f].addr = 0;
654 INIT_WORK(&rq->dim.work, mlx5e_rx_dim_work);
656 switch (params->rx_cq_moderation.cq_period_mode) {
657 case MLX5_CQ_PERIOD_MODE_START_FROM_CQE:
658 rq->dim.mode = NET_DIM_CQ_PERIOD_MODE_START_FROM_CQE;
660 case MLX5_CQ_PERIOD_MODE_START_FROM_EQE:
662 rq->dim.mode = NET_DIM_CQ_PERIOD_MODE_START_FROM_EQE;
665 rq->page_cache.head = 0;
666 rq->page_cache.tail = 0;
671 switch (rq->wq_type) {
672 case MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ:
673 kvfree(rq->mpwqe.info);
674 mlx5_core_destroy_mkey(mdev, &rq->umr_mkey);
676 default: /* MLX5_WQ_TYPE_CYCLIC */
677 kvfree(rq->wqe.frags);
678 mlx5e_free_di_list(rq);
683 bpf_prog_put(rq->xdp_prog);
684 xdp_rxq_info_unreg(&rq->xdp_rxq);
686 page_pool_destroy(rq->page_pool);
687 mlx5_wq_destroy(&rq->wq_ctrl);
692 static void mlx5e_free_rq(struct mlx5e_rq *rq)
697 bpf_prog_put(rq->xdp_prog);
699 xdp_rxq_info_unreg(&rq->xdp_rxq);
701 page_pool_destroy(rq->page_pool);
703 switch (rq->wq_type) {
704 case MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ:
705 kvfree(rq->mpwqe.info);
706 mlx5_core_destroy_mkey(rq->mdev, &rq->umr_mkey);
708 default: /* MLX5_WQ_TYPE_CYCLIC */
709 kvfree(rq->wqe.frags);
710 mlx5e_free_di_list(rq);
713 for (i = rq->page_cache.head; i != rq->page_cache.tail;
714 i = (i + 1) & (MLX5E_CACHE_SIZE - 1)) {
715 struct mlx5e_dma_info *dma_info = &rq->page_cache.page_cache[i];
717 mlx5e_page_release(rq, dma_info, false);
719 mlx5_wq_destroy(&rq->wq_ctrl);
722 static int mlx5e_create_rq(struct mlx5e_rq *rq,
723 struct mlx5e_rq_param *param)
725 struct mlx5_core_dev *mdev = rq->mdev;
733 inlen = MLX5_ST_SZ_BYTES(create_rq_in) +
734 sizeof(u64) * rq->wq_ctrl.buf.npages;
735 in = kvzalloc(inlen, GFP_KERNEL);
739 rqc = MLX5_ADDR_OF(create_rq_in, in, ctx);
740 wq = MLX5_ADDR_OF(rqc, rqc, wq);
742 memcpy(rqc, param->rqc, sizeof(param->rqc));
744 MLX5_SET(rqc, rqc, cqn, rq->cq.mcq.cqn);
745 MLX5_SET(rqc, rqc, state, MLX5_RQC_STATE_RST);
746 MLX5_SET(wq, wq, log_wq_pg_sz, rq->wq_ctrl.buf.page_shift -
747 MLX5_ADAPTER_PAGE_SHIFT);
748 MLX5_SET64(wq, wq, dbr_addr, rq->wq_ctrl.db.dma);
750 mlx5_fill_page_frag_array(&rq->wq_ctrl.buf,
751 (__be64 *)MLX5_ADDR_OF(wq, wq, pas));
753 err = mlx5_core_create_rq(mdev, in, inlen, &rq->rqn);
760 static int mlx5e_modify_rq_state(struct mlx5e_rq *rq, int curr_state,
763 struct mlx5_core_dev *mdev = rq->mdev;
770 inlen = MLX5_ST_SZ_BYTES(modify_rq_in);
771 in = kvzalloc(inlen, GFP_KERNEL);
775 rqc = MLX5_ADDR_OF(modify_rq_in, in, ctx);
777 MLX5_SET(modify_rq_in, in, rq_state, curr_state);
778 MLX5_SET(rqc, rqc, state, next_state);
780 err = mlx5_core_modify_rq(mdev, rq->rqn, in, inlen);
787 static int mlx5e_modify_rq_scatter_fcs(struct mlx5e_rq *rq, bool enable)
789 struct mlx5e_channel *c = rq->channel;
790 struct mlx5e_priv *priv = c->priv;
791 struct mlx5_core_dev *mdev = priv->mdev;
798 inlen = MLX5_ST_SZ_BYTES(modify_rq_in);
799 in = kvzalloc(inlen, GFP_KERNEL);
803 rqc = MLX5_ADDR_OF(modify_rq_in, in, ctx);
805 MLX5_SET(modify_rq_in, in, rq_state, MLX5_RQC_STATE_RDY);
806 MLX5_SET64(modify_rq_in, in, modify_bitmask,
807 MLX5_MODIFY_RQ_IN_MODIFY_BITMASK_SCATTER_FCS);
808 MLX5_SET(rqc, rqc, scatter_fcs, enable);
809 MLX5_SET(rqc, rqc, state, MLX5_RQC_STATE_RDY);
811 err = mlx5_core_modify_rq(mdev, rq->rqn, in, inlen);
818 static int mlx5e_modify_rq_vsd(struct mlx5e_rq *rq, bool vsd)
820 struct mlx5e_channel *c = rq->channel;
821 struct mlx5_core_dev *mdev = c->mdev;
827 inlen = MLX5_ST_SZ_BYTES(modify_rq_in);
828 in = kvzalloc(inlen, GFP_KERNEL);
832 rqc = MLX5_ADDR_OF(modify_rq_in, in, ctx);
834 MLX5_SET(modify_rq_in, in, rq_state, MLX5_RQC_STATE_RDY);
835 MLX5_SET64(modify_rq_in, in, modify_bitmask,
836 MLX5_MODIFY_RQ_IN_MODIFY_BITMASK_VSD);
837 MLX5_SET(rqc, rqc, vsd, vsd);
838 MLX5_SET(rqc, rqc, state, MLX5_RQC_STATE_RDY);
840 err = mlx5_core_modify_rq(mdev, rq->rqn, in, inlen);
847 static void mlx5e_destroy_rq(struct mlx5e_rq *rq)
849 mlx5_core_destroy_rq(rq->mdev, rq->rqn);
852 static int mlx5e_wait_for_min_rx_wqes(struct mlx5e_rq *rq, int wait_time)
854 unsigned long exp_time = jiffies + msecs_to_jiffies(wait_time);
855 struct mlx5e_channel *c = rq->channel;
857 u16 min_wqes = mlx5_min_rx_wqes(rq->wq_type, mlx5e_rqwq_get_size(rq));
860 if (mlx5e_rqwq_get_cur_sz(rq) >= min_wqes)
864 } while (time_before(jiffies, exp_time));
866 netdev_warn(c->netdev, "Failed to get min RX wqes on Channel[%d] RQN[0x%x] wq cur_sz(%d) min_rx_wqes(%d)\n",
867 c->ix, rq->rqn, mlx5e_rqwq_get_cur_sz(rq), min_wqes);
872 static void mlx5e_free_rx_descs(struct mlx5e_rq *rq)
877 if (rq->wq_type == MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ) {
878 struct mlx5_wq_ll *wq = &rq->mpwqe.wq;
880 /* UMR WQE (if in progress) is always at wq->head */
881 if (rq->mpwqe.umr_in_progress)
882 mlx5e_free_rx_mpwqe(rq, &rq->mpwqe.info[wq->head]);
884 while (!mlx5_wq_ll_is_empty(wq)) {
885 struct mlx5e_rx_wqe_ll *wqe;
887 wqe_ix_be = *wq->tail_next;
888 wqe_ix = be16_to_cpu(wqe_ix_be);
889 wqe = mlx5_wq_ll_get_wqe(wq, wqe_ix);
890 rq->dealloc_wqe(rq, wqe_ix);
891 mlx5_wq_ll_pop(wq, wqe_ix_be,
892 &wqe->next.next_wqe_index);
895 struct mlx5_wq_cyc *wq = &rq->wqe.wq;
897 while (!mlx5_wq_cyc_is_empty(wq)) {
898 wqe_ix = mlx5_wq_cyc_get_tail(wq);
899 rq->dealloc_wqe(rq, wqe_ix);
906 static int mlx5e_open_rq(struct mlx5e_channel *c,
907 struct mlx5e_params *params,
908 struct mlx5e_rq_param *param,
913 err = mlx5e_alloc_rq(c, params, param, rq);
917 err = mlx5e_create_rq(rq, param);
921 err = mlx5e_modify_rq_state(rq, MLX5_RQC_STATE_RST, MLX5_RQC_STATE_RDY);
925 if (params->rx_dim_enabled)
926 __set_bit(MLX5E_RQ_STATE_AM, &c->rq.state);
931 mlx5e_destroy_rq(rq);
938 static void mlx5e_activate_rq(struct mlx5e_rq *rq)
940 struct mlx5e_icosq *sq = &rq->channel->icosq;
941 struct mlx5_wq_cyc *wq = &sq->wq;
942 struct mlx5e_tx_wqe *nopwqe;
944 u16 pi = mlx5_wq_cyc_ctr2ix(wq, sq->pc);
946 set_bit(MLX5E_RQ_STATE_ENABLED, &rq->state);
947 sq->db.ico_wqe[pi].opcode = MLX5_OPCODE_NOP;
948 nopwqe = mlx5e_post_nop(wq, sq->sqn, &sq->pc);
949 mlx5e_notify_hw(wq, sq->pc, sq->uar_map, &nopwqe->ctrl);
952 static void mlx5e_deactivate_rq(struct mlx5e_rq *rq)
954 clear_bit(MLX5E_RQ_STATE_ENABLED, &rq->state);
955 napi_synchronize(&rq->channel->napi); /* prevent mlx5e_post_rx_wqes */
958 static void mlx5e_close_rq(struct mlx5e_rq *rq)
960 cancel_work_sync(&rq->dim.work);
961 mlx5e_destroy_rq(rq);
962 mlx5e_free_rx_descs(rq);
966 static void mlx5e_free_xdpsq_db(struct mlx5e_xdpsq *sq)
971 static int mlx5e_alloc_xdpsq_db(struct mlx5e_xdpsq *sq, int numa)
973 int wq_sz = mlx5_wq_cyc_get_size(&sq->wq);
975 sq->db.di = kvzalloc_node(sizeof(*sq->db.di) * wq_sz,
978 mlx5e_free_xdpsq_db(sq);
985 static int mlx5e_alloc_xdpsq(struct mlx5e_channel *c,
986 struct mlx5e_params *params,
987 struct mlx5e_sq_param *param,
988 struct mlx5e_xdpsq *sq)
990 void *sqc_wq = MLX5_ADDR_OF(sqc, param->sqc, wq);
991 struct mlx5_core_dev *mdev = c->mdev;
992 struct mlx5_wq_cyc *wq = &sq->wq;
996 sq->mkey_be = c->mkey_be;
998 sq->uar_map = mdev->mlx5e_res.bfreg.map;
999 sq->min_inline_mode = params->tx_min_inline_mode;
1001 param->wq.db_numa_node = cpu_to_node(c->cpu);
1002 err = mlx5_wq_cyc_create(mdev, ¶m->wq, sqc_wq, wq, &sq->wq_ctrl);
1005 wq->db = &wq->db[MLX5_SND_DBR];
1007 err = mlx5e_alloc_xdpsq_db(sq, cpu_to_node(c->cpu));
1009 goto err_sq_wq_destroy;
1014 mlx5_wq_destroy(&sq->wq_ctrl);
1019 static void mlx5e_free_xdpsq(struct mlx5e_xdpsq *sq)
1021 mlx5e_free_xdpsq_db(sq);
1022 mlx5_wq_destroy(&sq->wq_ctrl);
1025 static void mlx5e_free_icosq_db(struct mlx5e_icosq *sq)
1027 kvfree(sq->db.ico_wqe);
1030 static int mlx5e_alloc_icosq_db(struct mlx5e_icosq *sq, int numa)
1032 u8 wq_sz = mlx5_wq_cyc_get_size(&sq->wq);
1034 sq->db.ico_wqe = kvzalloc_node(sizeof(*sq->db.ico_wqe) * wq_sz,
1036 if (!sq->db.ico_wqe)
1042 static int mlx5e_alloc_icosq(struct mlx5e_channel *c,
1043 struct mlx5e_sq_param *param,
1044 struct mlx5e_icosq *sq)
1046 void *sqc_wq = MLX5_ADDR_OF(sqc, param->sqc, wq);
1047 struct mlx5_core_dev *mdev = c->mdev;
1048 struct mlx5_wq_cyc *wq = &sq->wq;
1052 sq->uar_map = mdev->mlx5e_res.bfreg.map;
1054 param->wq.db_numa_node = cpu_to_node(c->cpu);
1055 err = mlx5_wq_cyc_create(mdev, ¶m->wq, sqc_wq, wq, &sq->wq_ctrl);
1058 wq->db = &wq->db[MLX5_SND_DBR];
1060 err = mlx5e_alloc_icosq_db(sq, cpu_to_node(c->cpu));
1062 goto err_sq_wq_destroy;
1067 mlx5_wq_destroy(&sq->wq_ctrl);
1072 static void mlx5e_free_icosq(struct mlx5e_icosq *sq)
1074 mlx5e_free_icosq_db(sq);
1075 mlx5_wq_destroy(&sq->wq_ctrl);
1078 static void mlx5e_free_txqsq_db(struct mlx5e_txqsq *sq)
1080 kvfree(sq->db.wqe_info);
1081 kvfree(sq->db.dma_fifo);
1084 static int mlx5e_alloc_txqsq_db(struct mlx5e_txqsq *sq, int numa)
1086 int wq_sz = mlx5_wq_cyc_get_size(&sq->wq);
1087 int df_sz = wq_sz * MLX5_SEND_WQEBB_NUM_DS;
1089 sq->db.dma_fifo = kvzalloc_node(df_sz * sizeof(*sq->db.dma_fifo),
1091 sq->db.wqe_info = kvzalloc_node(wq_sz * sizeof(*sq->db.wqe_info),
1093 if (!sq->db.dma_fifo || !sq->db.wqe_info) {
1094 mlx5e_free_txqsq_db(sq);
1098 sq->dma_fifo_mask = df_sz - 1;
1103 static void mlx5e_sq_recover(struct work_struct *work);
1104 static int mlx5e_alloc_txqsq(struct mlx5e_channel *c,
1106 struct mlx5e_params *params,
1107 struct mlx5e_sq_param *param,
1108 struct mlx5e_txqsq *sq,
1111 void *sqc_wq = MLX5_ADDR_OF(sqc, param->sqc, wq);
1112 struct mlx5_core_dev *mdev = c->mdev;
1113 struct mlx5_wq_cyc *wq = &sq->wq;
1117 sq->tstamp = c->tstamp;
1118 sq->clock = &mdev->clock;
1119 sq->mkey_be = c->mkey_be;
1121 sq->txq_ix = txq_ix;
1122 sq->uar_map = mdev->mlx5e_res.bfreg.map;
1123 sq->min_inline_mode = params->tx_min_inline_mode;
1124 sq->stats = &c->priv->channel_stats[c->ix].sq[tc];
1125 INIT_WORK(&sq->recover.recover_work, mlx5e_sq_recover);
1126 if (MLX5_IPSEC_DEV(c->priv->mdev))
1127 set_bit(MLX5E_SQ_STATE_IPSEC, &sq->state);
1128 if (mlx5_accel_is_tls_device(c->priv->mdev))
1129 set_bit(MLX5E_SQ_STATE_TLS, &sq->state);
1131 param->wq.db_numa_node = cpu_to_node(c->cpu);
1132 err = mlx5_wq_cyc_create(mdev, ¶m->wq, sqc_wq, wq, &sq->wq_ctrl);
1135 wq->db = &wq->db[MLX5_SND_DBR];
1137 err = mlx5e_alloc_txqsq_db(sq, cpu_to_node(c->cpu));
1139 goto err_sq_wq_destroy;
1141 INIT_WORK(&sq->dim.work, mlx5e_tx_dim_work);
1142 sq->dim.mode = params->tx_cq_moderation.cq_period_mode;
1147 mlx5_wq_destroy(&sq->wq_ctrl);
1152 static void mlx5e_free_txqsq(struct mlx5e_txqsq *sq)
1154 mlx5e_free_txqsq_db(sq);
1155 mlx5_wq_destroy(&sq->wq_ctrl);
1158 struct mlx5e_create_sq_param {
1159 struct mlx5_wq_ctrl *wq_ctrl;
1166 static int mlx5e_create_sq(struct mlx5_core_dev *mdev,
1167 struct mlx5e_sq_param *param,
1168 struct mlx5e_create_sq_param *csp,
1177 inlen = MLX5_ST_SZ_BYTES(create_sq_in) +
1178 sizeof(u64) * csp->wq_ctrl->buf.npages;
1179 in = kvzalloc(inlen, GFP_KERNEL);
1183 sqc = MLX5_ADDR_OF(create_sq_in, in, ctx);
1184 wq = MLX5_ADDR_OF(sqc, sqc, wq);
1186 memcpy(sqc, param->sqc, sizeof(param->sqc));
1187 MLX5_SET(sqc, sqc, tis_lst_sz, csp->tis_lst_sz);
1188 MLX5_SET(sqc, sqc, tis_num_0, csp->tisn);
1189 MLX5_SET(sqc, sqc, cqn, csp->cqn);
1191 if (MLX5_CAP_ETH(mdev, wqe_inline_mode) == MLX5_CAP_INLINE_MODE_VPORT_CONTEXT)
1192 MLX5_SET(sqc, sqc, min_wqe_inline_mode, csp->min_inline_mode);
1194 MLX5_SET(sqc, sqc, state, MLX5_SQC_STATE_RST);
1195 MLX5_SET(sqc, sqc, flush_in_error_en, 1);
1197 MLX5_SET(wq, wq, wq_type, MLX5_WQ_TYPE_CYCLIC);
1198 MLX5_SET(wq, wq, uar_page, mdev->mlx5e_res.bfreg.index);
1199 MLX5_SET(wq, wq, log_wq_pg_sz, csp->wq_ctrl->buf.page_shift -
1200 MLX5_ADAPTER_PAGE_SHIFT);
1201 MLX5_SET64(wq, wq, dbr_addr, csp->wq_ctrl->db.dma);
1203 mlx5_fill_page_frag_array(&csp->wq_ctrl->buf,
1204 (__be64 *)MLX5_ADDR_OF(wq, wq, pas));
1206 err = mlx5_core_create_sq(mdev, in, inlen, sqn);
1213 struct mlx5e_modify_sq_param {
1220 static int mlx5e_modify_sq(struct mlx5_core_dev *mdev, u32 sqn,
1221 struct mlx5e_modify_sq_param *p)
1228 inlen = MLX5_ST_SZ_BYTES(modify_sq_in);
1229 in = kvzalloc(inlen, GFP_KERNEL);
1233 sqc = MLX5_ADDR_OF(modify_sq_in, in, ctx);
1235 MLX5_SET(modify_sq_in, in, sq_state, p->curr_state);
1236 MLX5_SET(sqc, sqc, state, p->next_state);
1237 if (p->rl_update && p->next_state == MLX5_SQC_STATE_RDY) {
1238 MLX5_SET64(modify_sq_in, in, modify_bitmask, 1);
1239 MLX5_SET(sqc, sqc, packet_pacing_rate_limit_index, p->rl_index);
1242 err = mlx5_core_modify_sq(mdev, sqn, in, inlen);
1249 static void mlx5e_destroy_sq(struct mlx5_core_dev *mdev, u32 sqn)
1251 mlx5_core_destroy_sq(mdev, sqn);
1254 static int mlx5e_create_sq_rdy(struct mlx5_core_dev *mdev,
1255 struct mlx5e_sq_param *param,
1256 struct mlx5e_create_sq_param *csp,
1259 struct mlx5e_modify_sq_param msp = {0};
1262 err = mlx5e_create_sq(mdev, param, csp, sqn);
1266 msp.curr_state = MLX5_SQC_STATE_RST;
1267 msp.next_state = MLX5_SQC_STATE_RDY;
1268 err = mlx5e_modify_sq(mdev, *sqn, &msp);
1270 mlx5e_destroy_sq(mdev, *sqn);
1275 static int mlx5e_set_sq_maxrate(struct net_device *dev,
1276 struct mlx5e_txqsq *sq, u32 rate);
1278 static int mlx5e_open_txqsq(struct mlx5e_channel *c,
1281 struct mlx5e_params *params,
1282 struct mlx5e_sq_param *param,
1283 struct mlx5e_txqsq *sq,
1286 struct mlx5e_create_sq_param csp = {};
1290 err = mlx5e_alloc_txqsq(c, txq_ix, params, param, sq, tc);
1296 csp.cqn = sq->cq.mcq.cqn;
1297 csp.wq_ctrl = &sq->wq_ctrl;
1298 csp.min_inline_mode = sq->min_inline_mode;
1299 err = mlx5e_create_sq_rdy(c->mdev, param, &csp, &sq->sqn);
1301 goto err_free_txqsq;
1303 tx_rate = c->priv->tx_rates[sq->txq_ix];
1305 mlx5e_set_sq_maxrate(c->netdev, sq, tx_rate);
1307 if (params->tx_dim_enabled)
1308 sq->state |= BIT(MLX5E_SQ_STATE_AM);
1313 clear_bit(MLX5E_SQ_STATE_ENABLED, &sq->state);
1314 mlx5e_free_txqsq(sq);
1319 static void mlx5e_reset_txqsq_cc_pc(struct mlx5e_txqsq *sq)
1321 WARN_ONCE(sq->cc != sq->pc,
1322 "SQ 0x%x: cc (0x%x) != pc (0x%x)\n",
1323 sq->sqn, sq->cc, sq->pc);
1325 sq->dma_fifo_cc = 0;
1329 static void mlx5e_activate_txqsq(struct mlx5e_txqsq *sq)
1331 sq->txq = netdev_get_tx_queue(sq->channel->netdev, sq->txq_ix);
1332 clear_bit(MLX5E_SQ_STATE_RECOVERING, &sq->state);
1333 set_bit(MLX5E_SQ_STATE_ENABLED, &sq->state);
1334 netdev_tx_reset_queue(sq->txq);
1335 netif_tx_start_queue(sq->txq);
1338 static inline void netif_tx_disable_queue(struct netdev_queue *txq)
1340 __netif_tx_lock_bh(txq);
1341 netif_tx_stop_queue(txq);
1342 __netif_tx_unlock_bh(txq);
1345 static void mlx5e_deactivate_txqsq(struct mlx5e_txqsq *sq)
1347 struct mlx5e_channel *c = sq->channel;
1348 struct mlx5_wq_cyc *wq = &sq->wq;
1350 clear_bit(MLX5E_SQ_STATE_ENABLED, &sq->state);
1351 /* prevent netif_tx_wake_queue */
1352 napi_synchronize(&c->napi);
1354 netif_tx_disable_queue(sq->txq);
1356 /* last doorbell out, godspeed .. */
1357 if (mlx5e_wqc_has_room_for(wq, sq->cc, sq->pc, 1)) {
1358 u16 pi = mlx5_wq_cyc_ctr2ix(wq, sq->pc);
1359 struct mlx5e_tx_wqe *nop;
1361 sq->db.wqe_info[pi].skb = NULL;
1362 nop = mlx5e_post_nop(wq, sq->sqn, &sq->pc);
1363 mlx5e_notify_hw(wq, sq->pc, sq->uar_map, &nop->ctrl);
1367 static void mlx5e_close_txqsq(struct mlx5e_txqsq *sq)
1369 struct mlx5e_channel *c = sq->channel;
1370 struct mlx5_core_dev *mdev = c->mdev;
1371 struct mlx5_rate_limit rl = {0};
1373 mlx5e_destroy_sq(mdev, sq->sqn);
1374 if (sq->rate_limit) {
1375 rl.rate = sq->rate_limit;
1376 mlx5_rl_remove_rate(mdev, &rl);
1378 mlx5e_free_txqsq_descs(sq);
1379 mlx5e_free_txqsq(sq);
1382 static int mlx5e_wait_for_sq_flush(struct mlx5e_txqsq *sq)
1384 unsigned long exp_time = jiffies + msecs_to_jiffies(2000);
1386 while (time_before(jiffies, exp_time)) {
1387 if (sq->cc == sq->pc)
1393 netdev_err(sq->channel->netdev,
1394 "Wait for SQ 0x%x flush timeout (sq cc = 0x%x, sq pc = 0x%x)\n",
1395 sq->sqn, sq->cc, sq->pc);
1400 static int mlx5e_sq_to_ready(struct mlx5e_txqsq *sq, int curr_state)
1402 struct mlx5_core_dev *mdev = sq->channel->mdev;
1403 struct net_device *dev = sq->channel->netdev;
1404 struct mlx5e_modify_sq_param msp = {0};
1407 msp.curr_state = curr_state;
1408 msp.next_state = MLX5_SQC_STATE_RST;
1410 err = mlx5e_modify_sq(mdev, sq->sqn, &msp);
1412 netdev_err(dev, "Failed to move sq 0x%x to reset\n", sq->sqn);
1416 memset(&msp, 0, sizeof(msp));
1417 msp.curr_state = MLX5_SQC_STATE_RST;
1418 msp.next_state = MLX5_SQC_STATE_RDY;
1420 err = mlx5e_modify_sq(mdev, sq->sqn, &msp);
1422 netdev_err(dev, "Failed to move sq 0x%x to ready\n", sq->sqn);
1429 static void mlx5e_sq_recover(struct work_struct *work)
1431 struct mlx5e_txqsq_recover *recover =
1432 container_of(work, struct mlx5e_txqsq_recover,
1434 struct mlx5e_txqsq *sq = container_of(recover, struct mlx5e_txqsq,
1436 struct mlx5_core_dev *mdev = sq->channel->mdev;
1437 struct net_device *dev = sq->channel->netdev;
1441 err = mlx5_core_query_sq_state(mdev, sq->sqn, &state);
1443 netdev_err(dev, "Failed to query SQ 0x%x state. err = %d\n",
1448 if (state != MLX5_RQC_STATE_ERR) {
1449 netdev_err(dev, "SQ 0x%x not in ERROR state\n", sq->sqn);
1453 netif_tx_disable_queue(sq->txq);
1455 if (mlx5e_wait_for_sq_flush(sq))
1458 /* If the interval between two consecutive recovers per SQ is too
1459 * short, don't recover to avoid infinite loop of ERR_CQE -> recover.
1460 * If we reached this state, there is probably a bug that needs to be
1461 * fixed. let's keep the queue close and let tx timeout cleanup.
1463 if (jiffies_to_msecs(jiffies - recover->last_recover) <
1464 MLX5E_SQ_RECOVER_MIN_INTERVAL) {
1465 netdev_err(dev, "Recover SQ 0x%x canceled, too many error CQEs\n",
1470 /* At this point, no new packets will arrive from the stack as TXQ is
1471 * marked with QUEUE_STATE_DRV_XOFF. In addition, NAPI cleared all
1472 * pending WQEs. SQ can safely reset the SQ.
1474 if (mlx5e_sq_to_ready(sq, state))
1477 mlx5e_reset_txqsq_cc_pc(sq);
1478 sq->stats->recover++;
1479 recover->last_recover = jiffies;
1480 mlx5e_activate_txqsq(sq);
1483 static int mlx5e_open_icosq(struct mlx5e_channel *c,
1484 struct mlx5e_params *params,
1485 struct mlx5e_sq_param *param,
1486 struct mlx5e_icosq *sq)
1488 struct mlx5e_create_sq_param csp = {};
1491 err = mlx5e_alloc_icosq(c, param, sq);
1495 csp.cqn = sq->cq.mcq.cqn;
1496 csp.wq_ctrl = &sq->wq_ctrl;
1497 csp.min_inline_mode = params->tx_min_inline_mode;
1498 set_bit(MLX5E_SQ_STATE_ENABLED, &sq->state);
1499 err = mlx5e_create_sq_rdy(c->mdev, param, &csp, &sq->sqn);
1501 goto err_free_icosq;
1506 clear_bit(MLX5E_SQ_STATE_ENABLED, &sq->state);
1507 mlx5e_free_icosq(sq);
1512 static void mlx5e_close_icosq(struct mlx5e_icosq *sq)
1514 struct mlx5e_channel *c = sq->channel;
1516 clear_bit(MLX5E_SQ_STATE_ENABLED, &sq->state);
1517 napi_synchronize(&c->napi);
1519 mlx5e_destroy_sq(c->mdev, sq->sqn);
1520 mlx5e_free_icosq(sq);
1523 static int mlx5e_open_xdpsq(struct mlx5e_channel *c,
1524 struct mlx5e_params *params,
1525 struct mlx5e_sq_param *param,
1526 struct mlx5e_xdpsq *sq)
1528 unsigned int ds_cnt = MLX5E_XDP_TX_DS_COUNT;
1529 struct mlx5e_create_sq_param csp = {};
1530 unsigned int inline_hdr_sz = 0;
1534 err = mlx5e_alloc_xdpsq(c, params, param, sq);
1539 csp.tisn = c->priv->tisn[0]; /* tc = 0 */
1540 csp.cqn = sq->cq.mcq.cqn;
1541 csp.wq_ctrl = &sq->wq_ctrl;
1542 csp.min_inline_mode = sq->min_inline_mode;
1543 set_bit(MLX5E_SQ_STATE_ENABLED, &sq->state);
1544 err = mlx5e_create_sq_rdy(c->mdev, param, &csp, &sq->sqn);
1546 goto err_free_xdpsq;
1548 if (sq->min_inline_mode != MLX5_INLINE_MODE_NONE) {
1549 inline_hdr_sz = MLX5E_XDP_MIN_INLINE;
1553 /* Pre initialize fixed WQE fields */
1554 for (i = 0; i < mlx5_wq_cyc_get_size(&sq->wq); i++) {
1555 struct mlx5e_tx_wqe *wqe = mlx5_wq_cyc_get_wqe(&sq->wq, i);
1556 struct mlx5_wqe_ctrl_seg *cseg = &wqe->ctrl;
1557 struct mlx5_wqe_eth_seg *eseg = &wqe->eth;
1558 struct mlx5_wqe_data_seg *dseg;
1560 cseg->qpn_ds = cpu_to_be32((sq->sqn << 8) | ds_cnt);
1561 eseg->inline_hdr.sz = cpu_to_be16(inline_hdr_sz);
1563 dseg = (struct mlx5_wqe_data_seg *)cseg + (ds_cnt - 1);
1564 dseg->lkey = sq->mkey_be;
1570 clear_bit(MLX5E_SQ_STATE_ENABLED, &sq->state);
1571 mlx5e_free_xdpsq(sq);
1576 static void mlx5e_close_xdpsq(struct mlx5e_xdpsq *sq)
1578 struct mlx5e_channel *c = sq->channel;
1580 clear_bit(MLX5E_SQ_STATE_ENABLED, &sq->state);
1581 napi_synchronize(&c->napi);
1583 mlx5e_destroy_sq(c->mdev, sq->sqn);
1584 mlx5e_free_xdpsq_descs(sq);
1585 mlx5e_free_xdpsq(sq);
1588 static int mlx5e_alloc_cq_common(struct mlx5_core_dev *mdev,
1589 struct mlx5e_cq_param *param,
1590 struct mlx5e_cq *cq)
1592 struct mlx5_core_cq *mcq = &cq->mcq;
1598 err = mlx5_cqwq_create(mdev, ¶m->wq, param->cqc, &cq->wq,
1603 mlx5_vector2eqn(mdev, param->eq_ix, &eqn_not_used, &irqn);
1606 mcq->set_ci_db = cq->wq_ctrl.db.db;
1607 mcq->arm_db = cq->wq_ctrl.db.db + 1;
1608 *mcq->set_ci_db = 0;
1610 mcq->vector = param->eq_ix;
1611 mcq->comp = mlx5e_completion_event;
1612 mcq->event = mlx5e_cq_error_event;
1615 for (i = 0; i < mlx5_cqwq_get_size(&cq->wq); i++) {
1616 struct mlx5_cqe64 *cqe = mlx5_cqwq_get_wqe(&cq->wq, i);
1626 static int mlx5e_alloc_cq(struct mlx5e_channel *c,
1627 struct mlx5e_cq_param *param,
1628 struct mlx5e_cq *cq)
1630 struct mlx5_core_dev *mdev = c->priv->mdev;
1633 param->wq.buf_numa_node = cpu_to_node(c->cpu);
1634 param->wq.db_numa_node = cpu_to_node(c->cpu);
1635 param->eq_ix = c->ix;
1637 err = mlx5e_alloc_cq_common(mdev, param, cq);
1639 cq->napi = &c->napi;
1645 static void mlx5e_free_cq(struct mlx5e_cq *cq)
1647 mlx5_wq_destroy(&cq->wq_ctrl);
1650 static int mlx5e_create_cq(struct mlx5e_cq *cq, struct mlx5e_cq_param *param)
1652 struct mlx5_core_dev *mdev = cq->mdev;
1653 struct mlx5_core_cq *mcq = &cq->mcq;
1658 unsigned int irqn_not_used;
1662 inlen = MLX5_ST_SZ_BYTES(create_cq_in) +
1663 sizeof(u64) * cq->wq_ctrl.buf.npages;
1664 in = kvzalloc(inlen, GFP_KERNEL);
1668 cqc = MLX5_ADDR_OF(create_cq_in, in, cq_context);
1670 memcpy(cqc, param->cqc, sizeof(param->cqc));
1672 mlx5_fill_page_frag_array(&cq->wq_ctrl.buf,
1673 (__be64 *)MLX5_ADDR_OF(create_cq_in, in, pas));
1675 mlx5_vector2eqn(mdev, param->eq_ix, &eqn, &irqn_not_used);
1677 MLX5_SET(cqc, cqc, cq_period_mode, param->cq_period_mode);
1678 MLX5_SET(cqc, cqc, c_eqn, eqn);
1679 MLX5_SET(cqc, cqc, uar_page, mdev->priv.uar->index);
1680 MLX5_SET(cqc, cqc, log_page_size, cq->wq_ctrl.buf.page_shift -
1681 MLX5_ADAPTER_PAGE_SHIFT);
1682 MLX5_SET64(cqc, cqc, dbr_addr, cq->wq_ctrl.db.dma);
1684 err = mlx5_core_create_cq(mdev, mcq, in, inlen);
1696 static void mlx5e_destroy_cq(struct mlx5e_cq *cq)
1698 mlx5_core_destroy_cq(cq->mdev, &cq->mcq);
1701 static int mlx5e_open_cq(struct mlx5e_channel *c,
1702 struct net_dim_cq_moder moder,
1703 struct mlx5e_cq_param *param,
1704 struct mlx5e_cq *cq)
1706 struct mlx5_core_dev *mdev = c->mdev;
1709 err = mlx5e_alloc_cq(c, param, cq);
1713 err = mlx5e_create_cq(cq, param);
1717 if (MLX5_CAP_GEN(mdev, cq_moderation))
1718 mlx5_core_modify_cq_moderation(mdev, &cq->mcq, moder.usec, moder.pkts);
1727 static void mlx5e_close_cq(struct mlx5e_cq *cq)
1729 mlx5e_destroy_cq(cq);
1733 static int mlx5e_get_cpu(struct mlx5e_priv *priv, int ix)
1735 return cpumask_first(priv->mdev->priv.irq_info[ix].mask);
1738 static int mlx5e_open_tx_cqs(struct mlx5e_channel *c,
1739 struct mlx5e_params *params,
1740 struct mlx5e_channel_param *cparam)
1745 for (tc = 0; tc < c->num_tc; tc++) {
1746 err = mlx5e_open_cq(c, params->tx_cq_moderation,
1747 &cparam->tx_cq, &c->sq[tc].cq);
1749 goto err_close_tx_cqs;
1755 for (tc--; tc >= 0; tc--)
1756 mlx5e_close_cq(&c->sq[tc].cq);
1761 static void mlx5e_close_tx_cqs(struct mlx5e_channel *c)
1765 for (tc = 0; tc < c->num_tc; tc++)
1766 mlx5e_close_cq(&c->sq[tc].cq);
1769 static int mlx5e_open_sqs(struct mlx5e_channel *c,
1770 struct mlx5e_params *params,
1771 struct mlx5e_channel_param *cparam)
1773 struct mlx5e_priv *priv = c->priv;
1774 int err, tc, max_nch = priv->profile->max_nch(priv->mdev);
1776 for (tc = 0; tc < params->num_tc; tc++) {
1777 int txq_ix = c->ix + tc * max_nch;
1779 err = mlx5e_open_txqsq(c, c->priv->tisn[tc], txq_ix,
1780 params, &cparam->sq, &c->sq[tc], tc);
1788 for (tc--; tc >= 0; tc--)
1789 mlx5e_close_txqsq(&c->sq[tc]);
1794 static void mlx5e_close_sqs(struct mlx5e_channel *c)
1798 for (tc = 0; tc < c->num_tc; tc++)
1799 mlx5e_close_txqsq(&c->sq[tc]);
1802 static int mlx5e_set_sq_maxrate(struct net_device *dev,
1803 struct mlx5e_txqsq *sq, u32 rate)
1805 struct mlx5e_priv *priv = netdev_priv(dev);
1806 struct mlx5_core_dev *mdev = priv->mdev;
1807 struct mlx5e_modify_sq_param msp = {0};
1808 struct mlx5_rate_limit rl = {0};
1812 if (rate == sq->rate_limit)
1816 if (sq->rate_limit) {
1817 rl.rate = sq->rate_limit;
1818 /* remove current rl index to free space to next ones */
1819 mlx5_rl_remove_rate(mdev, &rl);
1826 err = mlx5_rl_add_rate(mdev, &rl_index, &rl);
1828 netdev_err(dev, "Failed configuring rate %u: %d\n",
1834 msp.curr_state = MLX5_SQC_STATE_RDY;
1835 msp.next_state = MLX5_SQC_STATE_RDY;
1836 msp.rl_index = rl_index;
1837 msp.rl_update = true;
1838 err = mlx5e_modify_sq(mdev, sq->sqn, &msp);
1840 netdev_err(dev, "Failed configuring rate %u: %d\n",
1842 /* remove the rate from the table */
1844 mlx5_rl_remove_rate(mdev, &rl);
1848 sq->rate_limit = rate;
1852 static int mlx5e_set_tx_maxrate(struct net_device *dev, int index, u32 rate)
1854 struct mlx5e_priv *priv = netdev_priv(dev);
1855 struct mlx5_core_dev *mdev = priv->mdev;
1856 struct mlx5e_txqsq *sq = priv->txq2sq[index];
1859 if (!mlx5_rl_is_supported(mdev)) {
1860 netdev_err(dev, "Rate limiting is not supported on this device\n");
1864 /* rate is given in Mb/sec, HW config is in Kb/sec */
1867 /* Check whether rate in valid range, 0 is always valid */
1868 if (rate && !mlx5_rl_is_in_range(mdev, rate)) {
1869 netdev_err(dev, "TX rate %u, is not in range\n", rate);
1873 mutex_lock(&priv->state_lock);
1874 if (test_bit(MLX5E_STATE_OPENED, &priv->state))
1875 err = mlx5e_set_sq_maxrate(dev, sq, rate);
1877 priv->tx_rates[index] = rate;
1878 mutex_unlock(&priv->state_lock);
1883 static int mlx5e_open_channel(struct mlx5e_priv *priv, int ix,
1884 struct mlx5e_params *params,
1885 struct mlx5e_channel_param *cparam,
1886 struct mlx5e_channel **cp)
1888 struct net_dim_cq_moder icocq_moder = {0, 0};
1889 struct net_device *netdev = priv->netdev;
1890 int cpu = mlx5e_get_cpu(priv, ix);
1891 struct mlx5e_channel *c;
1896 c = kvzalloc_node(sizeof(*c), GFP_KERNEL, cpu_to_node(cpu));
1901 c->mdev = priv->mdev;
1902 c->tstamp = &priv->tstamp;
1905 c->pdev = &priv->mdev->pdev->dev;
1906 c->netdev = priv->netdev;
1907 c->mkey_be = cpu_to_be32(priv->mdev->mlx5e_res.mkey.key);
1908 c->num_tc = params->num_tc;
1909 c->xdp = !!params->xdp_prog;
1910 c->stats = &priv->channel_stats[ix].ch;
1912 mlx5_vector2eqn(priv->mdev, ix, &eqn, &irq);
1913 c->irq_desc = irq_to_desc(irq);
1915 netif_napi_add(netdev, &c->napi, mlx5e_napi_poll, 64);
1917 err = mlx5e_open_cq(c, icocq_moder, &cparam->icosq_cq, &c->icosq.cq);
1921 err = mlx5e_open_tx_cqs(c, params, cparam);
1923 goto err_close_icosq_cq;
1925 err = mlx5e_open_cq(c, params->rx_cq_moderation, &cparam->rx_cq, &c->rq.cq);
1927 goto err_close_tx_cqs;
1929 /* XDP SQ CQ params are same as normal TXQ sq CQ params */
1930 err = c->xdp ? mlx5e_open_cq(c, params->tx_cq_moderation,
1931 &cparam->tx_cq, &c->rq.xdpsq.cq) : 0;
1933 goto err_close_rx_cq;
1935 napi_enable(&c->napi);
1937 err = mlx5e_open_icosq(c, params, &cparam->icosq, &c->icosq);
1939 goto err_disable_napi;
1941 err = mlx5e_open_sqs(c, params, cparam);
1943 goto err_close_icosq;
1945 err = c->xdp ? mlx5e_open_xdpsq(c, params, &cparam->xdp_sq, &c->rq.xdpsq) : 0;
1949 err = mlx5e_open_rq(c, params, &cparam->rq, &c->rq);
1951 goto err_close_xdp_sq;
1958 mlx5e_close_xdpsq(&c->rq.xdpsq);
1964 mlx5e_close_icosq(&c->icosq);
1967 napi_disable(&c->napi);
1969 mlx5e_close_cq(&c->rq.xdpsq.cq);
1972 mlx5e_close_cq(&c->rq.cq);
1975 mlx5e_close_tx_cqs(c);
1978 mlx5e_close_cq(&c->icosq.cq);
1981 netif_napi_del(&c->napi);
1987 static void mlx5e_activate_channel(struct mlx5e_channel *c)
1991 for (tc = 0; tc < c->num_tc; tc++)
1992 mlx5e_activate_txqsq(&c->sq[tc]);
1993 mlx5e_activate_rq(&c->rq);
1994 netif_set_xps_queue(c->netdev, get_cpu_mask(c->cpu), c->ix);
1997 static void mlx5e_deactivate_channel(struct mlx5e_channel *c)
2001 mlx5e_deactivate_rq(&c->rq);
2002 for (tc = 0; tc < c->num_tc; tc++)
2003 mlx5e_deactivate_txqsq(&c->sq[tc]);
2006 static void mlx5e_close_channel(struct mlx5e_channel *c)
2008 mlx5e_close_rq(&c->rq);
2010 mlx5e_close_xdpsq(&c->rq.xdpsq);
2012 mlx5e_close_icosq(&c->icosq);
2013 napi_disable(&c->napi);
2015 mlx5e_close_cq(&c->rq.xdpsq.cq);
2016 mlx5e_close_cq(&c->rq.cq);
2017 mlx5e_close_tx_cqs(c);
2018 mlx5e_close_cq(&c->icosq.cq);
2019 netif_napi_del(&c->napi);
2024 #define DEFAULT_FRAG_SIZE (2048)
2026 static void mlx5e_build_rq_frags_info(struct mlx5_core_dev *mdev,
2027 struct mlx5e_params *params,
2028 struct mlx5e_rq_frags_info *info)
2030 u32 byte_count = MLX5E_SW2HW_MTU(params, params->sw_mtu);
2031 int frag_size_max = DEFAULT_FRAG_SIZE;
2035 #ifdef CONFIG_MLX5_EN_IPSEC
2036 if (MLX5_IPSEC_DEV(mdev))
2037 byte_count += MLX5E_METADATA_ETHER_LEN;
2040 if (mlx5e_rx_is_linear_skb(mdev, params)) {
2043 frag_stride = mlx5e_rx_get_linear_frag_sz(params);
2044 frag_stride = roundup_pow_of_two(frag_stride);
2046 info->arr[0].frag_size = byte_count;
2047 info->arr[0].frag_stride = frag_stride;
2048 info->num_frags = 1;
2049 info->wqe_bulk = PAGE_SIZE / frag_stride;
2053 if (byte_count > PAGE_SIZE +
2054 (MLX5E_MAX_RX_FRAGS - 1) * frag_size_max)
2055 frag_size_max = PAGE_SIZE;
2058 while (buf_size < byte_count) {
2059 int frag_size = byte_count - buf_size;
2061 if (i < MLX5E_MAX_RX_FRAGS - 1)
2062 frag_size = min(frag_size, frag_size_max);
2064 info->arr[i].frag_size = frag_size;
2065 info->arr[i].frag_stride = roundup_pow_of_two(frag_size);
2067 buf_size += frag_size;
2070 info->num_frags = i;
2071 /* number of different wqes sharing a page */
2072 info->wqe_bulk = 1 + (info->num_frags % 2);
2075 info->wqe_bulk = max_t(u8, info->wqe_bulk, 8);
2076 info->log_num_frags = order_base_2(info->num_frags);
2079 static inline u8 mlx5e_get_rqwq_log_stride(u8 wq_type, int ndsegs)
2081 int sz = sizeof(struct mlx5_wqe_data_seg) * ndsegs;
2084 case MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ:
2085 sz += sizeof(struct mlx5e_rx_wqe_ll);
2087 default: /* MLX5_WQ_TYPE_CYCLIC */
2088 sz += sizeof(struct mlx5e_rx_wqe_cyc);
2091 return order_base_2(sz);
2094 static void mlx5e_build_rq_param(struct mlx5e_priv *priv,
2095 struct mlx5e_params *params,
2096 struct mlx5e_rq_param *param)
2098 struct mlx5_core_dev *mdev = priv->mdev;
2099 void *rqc = param->rqc;
2100 void *wq = MLX5_ADDR_OF(rqc, rqc, wq);
2103 switch (params->rq_wq_type) {
2104 case MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ:
2105 MLX5_SET(wq, wq, log_wqe_num_of_strides,
2106 mlx5e_mpwqe_get_log_num_strides(mdev, params) -
2107 MLX5_MPWQE_LOG_NUM_STRIDES_BASE);
2108 MLX5_SET(wq, wq, log_wqe_stride_size,
2109 mlx5e_mpwqe_get_log_stride_size(mdev, params) -
2110 MLX5_MPWQE_LOG_STRIDE_SZ_BASE);
2111 MLX5_SET(wq, wq, log_wq_sz, mlx5e_mpwqe_get_log_rq_size(params));
2113 default: /* MLX5_WQ_TYPE_CYCLIC */
2114 MLX5_SET(wq, wq, log_wq_sz, params->log_rq_mtu_frames);
2115 mlx5e_build_rq_frags_info(mdev, params, ¶m->frags_info);
2116 ndsegs = param->frags_info.num_frags;
2119 MLX5_SET(wq, wq, wq_type, params->rq_wq_type);
2120 MLX5_SET(wq, wq, end_padding_mode, MLX5_WQ_END_PAD_MODE_ALIGN);
2121 MLX5_SET(wq, wq, log_wq_stride,
2122 mlx5e_get_rqwq_log_stride(params->rq_wq_type, ndsegs));
2123 MLX5_SET(wq, wq, pd, mdev->mlx5e_res.pdn);
2124 MLX5_SET(rqc, rqc, counter_set_id, priv->q_counter);
2125 MLX5_SET(rqc, rqc, vsd, params->vlan_strip_disable);
2126 MLX5_SET(rqc, rqc, scatter_fcs, params->scatter_fcs_en);
2128 param->wq.buf_numa_node = dev_to_node(&mdev->pdev->dev);
2131 static void mlx5e_build_drop_rq_param(struct mlx5e_priv *priv,
2132 struct mlx5e_rq_param *param)
2134 struct mlx5_core_dev *mdev = priv->mdev;
2135 void *rqc = param->rqc;
2136 void *wq = MLX5_ADDR_OF(rqc, rqc, wq);
2138 MLX5_SET(wq, wq, wq_type, MLX5_WQ_TYPE_CYCLIC);
2139 MLX5_SET(wq, wq, log_wq_stride,
2140 mlx5e_get_rqwq_log_stride(MLX5_WQ_TYPE_CYCLIC, 1));
2141 MLX5_SET(rqc, rqc, counter_set_id, priv->drop_rq_q_counter);
2143 param->wq.buf_numa_node = dev_to_node(&mdev->pdev->dev);
2146 static void mlx5e_build_sq_param_common(struct mlx5e_priv *priv,
2147 struct mlx5e_sq_param *param)
2149 void *sqc = param->sqc;
2150 void *wq = MLX5_ADDR_OF(sqc, sqc, wq);
2152 MLX5_SET(wq, wq, log_wq_stride, ilog2(MLX5_SEND_WQE_BB));
2153 MLX5_SET(wq, wq, pd, priv->mdev->mlx5e_res.pdn);
2155 param->wq.buf_numa_node = dev_to_node(&priv->mdev->pdev->dev);
2158 static void mlx5e_build_sq_param(struct mlx5e_priv *priv,
2159 struct mlx5e_params *params,
2160 struct mlx5e_sq_param *param)
2162 void *sqc = param->sqc;
2163 void *wq = MLX5_ADDR_OF(sqc, sqc, wq);
2165 mlx5e_build_sq_param_common(priv, param);
2166 MLX5_SET(wq, wq, log_wq_sz, params->log_sq_size);
2167 MLX5_SET(sqc, sqc, allow_swp, !!MLX5_IPSEC_DEV(priv->mdev));
2170 static void mlx5e_build_common_cq_param(struct mlx5e_priv *priv,
2171 struct mlx5e_cq_param *param)
2173 void *cqc = param->cqc;
2175 MLX5_SET(cqc, cqc, uar_page, priv->mdev->priv.uar->index);
2178 static void mlx5e_build_rx_cq_param(struct mlx5e_priv *priv,
2179 struct mlx5e_params *params,
2180 struct mlx5e_cq_param *param)
2182 struct mlx5_core_dev *mdev = priv->mdev;
2183 void *cqc = param->cqc;
2186 switch (params->rq_wq_type) {
2187 case MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ:
2188 log_cq_size = mlx5e_mpwqe_get_log_rq_size(params) +
2189 mlx5e_mpwqe_get_log_num_strides(mdev, params);
2191 default: /* MLX5_WQ_TYPE_CYCLIC */
2192 log_cq_size = params->log_rq_mtu_frames;
2195 MLX5_SET(cqc, cqc, log_cq_size, log_cq_size);
2196 if (MLX5E_GET_PFLAG(params, MLX5E_PFLAG_RX_CQE_COMPRESS)) {
2197 MLX5_SET(cqc, cqc, mini_cqe_res_format, MLX5_CQE_FORMAT_CSUM);
2198 MLX5_SET(cqc, cqc, cqe_comp_en, 1);
2201 mlx5e_build_common_cq_param(priv, param);
2202 param->cq_period_mode = params->rx_cq_moderation.cq_period_mode;
2205 static void mlx5e_build_tx_cq_param(struct mlx5e_priv *priv,
2206 struct mlx5e_params *params,
2207 struct mlx5e_cq_param *param)
2209 void *cqc = param->cqc;
2211 MLX5_SET(cqc, cqc, log_cq_size, params->log_sq_size);
2213 mlx5e_build_common_cq_param(priv, param);
2214 param->cq_period_mode = params->tx_cq_moderation.cq_period_mode;
2217 static void mlx5e_build_ico_cq_param(struct mlx5e_priv *priv,
2219 struct mlx5e_cq_param *param)
2221 void *cqc = param->cqc;
2223 MLX5_SET(cqc, cqc, log_cq_size, log_wq_size);
2225 mlx5e_build_common_cq_param(priv, param);
2227 param->cq_period_mode = NET_DIM_CQ_PERIOD_MODE_START_FROM_EQE;
2230 static void mlx5e_build_icosq_param(struct mlx5e_priv *priv,
2232 struct mlx5e_sq_param *param)
2234 void *sqc = param->sqc;
2235 void *wq = MLX5_ADDR_OF(sqc, sqc, wq);
2237 mlx5e_build_sq_param_common(priv, param);
2239 MLX5_SET(wq, wq, log_wq_sz, log_wq_size);
2240 MLX5_SET(sqc, sqc, reg_umr, MLX5_CAP_ETH(priv->mdev, reg_umr_sq));
2243 static void mlx5e_build_xdpsq_param(struct mlx5e_priv *priv,
2244 struct mlx5e_params *params,
2245 struct mlx5e_sq_param *param)
2247 void *sqc = param->sqc;
2248 void *wq = MLX5_ADDR_OF(sqc, sqc, wq);
2250 mlx5e_build_sq_param_common(priv, param);
2251 MLX5_SET(wq, wq, log_wq_sz, params->log_sq_size);
2254 static void mlx5e_build_channel_param(struct mlx5e_priv *priv,
2255 struct mlx5e_params *params,
2256 struct mlx5e_channel_param *cparam)
2258 u8 icosq_log_wq_sz = MLX5E_PARAMS_MINIMUM_LOG_SQ_SIZE;
2260 mlx5e_build_rq_param(priv, params, &cparam->rq);
2261 mlx5e_build_sq_param(priv, params, &cparam->sq);
2262 mlx5e_build_xdpsq_param(priv, params, &cparam->xdp_sq);
2263 mlx5e_build_icosq_param(priv, icosq_log_wq_sz, &cparam->icosq);
2264 mlx5e_build_rx_cq_param(priv, params, &cparam->rx_cq);
2265 mlx5e_build_tx_cq_param(priv, params, &cparam->tx_cq);
2266 mlx5e_build_ico_cq_param(priv, icosq_log_wq_sz, &cparam->icosq_cq);
2269 int mlx5e_open_channels(struct mlx5e_priv *priv,
2270 struct mlx5e_channels *chs)
2272 struct mlx5e_channel_param *cparam;
2276 chs->num = chs->params.num_channels;
2278 chs->c = kcalloc(chs->num, sizeof(struct mlx5e_channel *), GFP_KERNEL);
2279 cparam = kvzalloc(sizeof(struct mlx5e_channel_param), GFP_KERNEL);
2280 if (!chs->c || !cparam)
2283 mlx5e_build_channel_param(priv, &chs->params, cparam);
2284 for (i = 0; i < chs->num; i++) {
2285 err = mlx5e_open_channel(priv, i, &chs->params, cparam, &chs->c[i]);
2287 goto err_close_channels;
2294 for (i--; i >= 0; i--)
2295 mlx5e_close_channel(chs->c[i]);
2304 static void mlx5e_activate_channels(struct mlx5e_channels *chs)
2308 for (i = 0; i < chs->num; i++)
2309 mlx5e_activate_channel(chs->c[i]);
2312 static int mlx5e_wait_channels_min_rx_wqes(struct mlx5e_channels *chs)
2317 for (i = 0; i < chs->num; i++)
2318 err |= mlx5e_wait_for_min_rx_wqes(&chs->c[i]->rq,
2321 return err ? -ETIMEDOUT : 0;
2324 static void mlx5e_deactivate_channels(struct mlx5e_channels *chs)
2328 for (i = 0; i < chs->num; i++)
2329 mlx5e_deactivate_channel(chs->c[i]);
2332 void mlx5e_close_channels(struct mlx5e_channels *chs)
2336 for (i = 0; i < chs->num; i++)
2337 mlx5e_close_channel(chs->c[i]);
2344 mlx5e_create_rqt(struct mlx5e_priv *priv, int sz, struct mlx5e_rqt *rqt)
2346 struct mlx5_core_dev *mdev = priv->mdev;
2353 inlen = MLX5_ST_SZ_BYTES(create_rqt_in) + sizeof(u32) * sz;
2354 in = kvzalloc(inlen, GFP_KERNEL);
2358 rqtc = MLX5_ADDR_OF(create_rqt_in, in, rqt_context);
2360 MLX5_SET(rqtc, rqtc, rqt_actual_size, sz);
2361 MLX5_SET(rqtc, rqtc, rqt_max_size, sz);
2363 for (i = 0; i < sz; i++)
2364 MLX5_SET(rqtc, rqtc, rq_num[i], priv->drop_rq.rqn);
2366 err = mlx5_core_create_rqt(mdev, in, inlen, &rqt->rqtn);
2368 rqt->enabled = true;
2374 void mlx5e_destroy_rqt(struct mlx5e_priv *priv, struct mlx5e_rqt *rqt)
2376 rqt->enabled = false;
2377 mlx5_core_destroy_rqt(priv->mdev, rqt->rqtn);
2380 int mlx5e_create_indirect_rqt(struct mlx5e_priv *priv)
2382 struct mlx5e_rqt *rqt = &priv->indir_rqt;
2385 err = mlx5e_create_rqt(priv, MLX5E_INDIR_RQT_SIZE, rqt);
2387 mlx5_core_warn(priv->mdev, "create indirect rqts failed, %d\n", err);
2391 int mlx5e_create_direct_rqts(struct mlx5e_priv *priv)
2393 struct mlx5e_rqt *rqt;
2397 for (ix = 0; ix < priv->profile->max_nch(priv->mdev); ix++) {
2398 rqt = &priv->direct_tir[ix].rqt;
2399 err = mlx5e_create_rqt(priv, 1 /*size */, rqt);
2401 goto err_destroy_rqts;
2407 mlx5_core_warn(priv->mdev, "create direct rqts failed, %d\n", err);
2408 for (ix--; ix >= 0; ix--)
2409 mlx5e_destroy_rqt(priv, &priv->direct_tir[ix].rqt);
2414 void mlx5e_destroy_direct_rqts(struct mlx5e_priv *priv)
2418 for (i = 0; i < priv->profile->max_nch(priv->mdev); i++)
2419 mlx5e_destroy_rqt(priv, &priv->direct_tir[i].rqt);
2422 static int mlx5e_rx_hash_fn(int hfunc)
2424 return (hfunc == ETH_RSS_HASH_TOP) ?
2425 MLX5_RX_HASH_FN_TOEPLITZ :
2426 MLX5_RX_HASH_FN_INVERTED_XOR8;
2429 int mlx5e_bits_invert(unsigned long a, int size)
2434 for (i = 0; i < size; i++)
2435 inv |= (test_bit(size - i - 1, &a) ? 1 : 0) << i;
2440 static void mlx5e_fill_rqt_rqns(struct mlx5e_priv *priv, int sz,
2441 struct mlx5e_redirect_rqt_param rrp, void *rqtc)
2445 for (i = 0; i < sz; i++) {
2451 if (rrp.rss.hfunc == ETH_RSS_HASH_XOR)
2452 ix = mlx5e_bits_invert(i, ilog2(sz));
2454 ix = priv->channels.params.indirection_rqt[ix];
2455 rqn = rrp.rss.channels->c[ix]->rq.rqn;
2459 MLX5_SET(rqtc, rqtc, rq_num[i], rqn);
2463 int mlx5e_redirect_rqt(struct mlx5e_priv *priv, u32 rqtn, int sz,
2464 struct mlx5e_redirect_rqt_param rrp)
2466 struct mlx5_core_dev *mdev = priv->mdev;
2472 inlen = MLX5_ST_SZ_BYTES(modify_rqt_in) + sizeof(u32) * sz;
2473 in = kvzalloc(inlen, GFP_KERNEL);
2477 rqtc = MLX5_ADDR_OF(modify_rqt_in, in, ctx);
2479 MLX5_SET(rqtc, rqtc, rqt_actual_size, sz);
2480 MLX5_SET(modify_rqt_in, in, bitmask.rqn_list, 1);
2481 mlx5e_fill_rqt_rqns(priv, sz, rrp, rqtc);
2482 err = mlx5_core_modify_rqt(mdev, rqtn, in, inlen);
2488 static u32 mlx5e_get_direct_rqn(struct mlx5e_priv *priv, int ix,
2489 struct mlx5e_redirect_rqt_param rrp)
2494 if (ix >= rrp.rss.channels->num)
2495 return priv->drop_rq.rqn;
2497 return rrp.rss.channels->c[ix]->rq.rqn;
2500 static void mlx5e_redirect_rqts(struct mlx5e_priv *priv,
2501 struct mlx5e_redirect_rqt_param rrp)
2506 if (priv->indir_rqt.enabled) {
2508 rqtn = priv->indir_rqt.rqtn;
2509 mlx5e_redirect_rqt(priv, rqtn, MLX5E_INDIR_RQT_SIZE, rrp);
2512 for (ix = 0; ix < priv->profile->max_nch(priv->mdev); ix++) {
2513 struct mlx5e_redirect_rqt_param direct_rrp = {
2516 .rqn = mlx5e_get_direct_rqn(priv, ix, rrp)
2520 /* Direct RQ Tables */
2521 if (!priv->direct_tir[ix].rqt.enabled)
2524 rqtn = priv->direct_tir[ix].rqt.rqtn;
2525 mlx5e_redirect_rqt(priv, rqtn, 1, direct_rrp);
2529 static void mlx5e_redirect_rqts_to_channels(struct mlx5e_priv *priv,
2530 struct mlx5e_channels *chs)
2532 struct mlx5e_redirect_rqt_param rrp = {
2537 .hfunc = chs->params.rss_hfunc,
2542 mlx5e_redirect_rqts(priv, rrp);
2545 static void mlx5e_redirect_rqts_to_drop(struct mlx5e_priv *priv)
2547 struct mlx5e_redirect_rqt_param drop_rrp = {
2550 .rqn = priv->drop_rq.rqn,
2554 mlx5e_redirect_rqts(priv, drop_rrp);
2557 static void mlx5e_build_tir_ctx_lro(struct mlx5e_params *params, void *tirc)
2559 if (!params->lro_en)
2562 #define ROUGH_MAX_L2_L3_HDR_SZ 256
2564 MLX5_SET(tirc, tirc, lro_enable_mask,
2565 MLX5_TIRC_LRO_ENABLE_MASK_IPV4_LRO |
2566 MLX5_TIRC_LRO_ENABLE_MASK_IPV6_LRO);
2567 MLX5_SET(tirc, tirc, lro_max_ip_payload_size,
2568 (params->lro_wqe_sz - ROUGH_MAX_L2_L3_HDR_SZ) >> 8);
2569 MLX5_SET(tirc, tirc, lro_timeout_period_usecs, params->lro_timeout);
2572 void mlx5e_build_indir_tir_ctx_hash(struct mlx5e_params *params,
2573 enum mlx5e_traffic_types tt,
2574 void *tirc, bool inner)
2576 void *hfso = inner ? MLX5_ADDR_OF(tirc, tirc, rx_hash_field_selector_inner) :
2577 MLX5_ADDR_OF(tirc, tirc, rx_hash_field_selector_outer);
2579 #define MLX5_HASH_IP (MLX5_HASH_FIELD_SEL_SRC_IP |\
2580 MLX5_HASH_FIELD_SEL_DST_IP)
2582 #define MLX5_HASH_IP_L4PORTS (MLX5_HASH_FIELD_SEL_SRC_IP |\
2583 MLX5_HASH_FIELD_SEL_DST_IP |\
2584 MLX5_HASH_FIELD_SEL_L4_SPORT |\
2585 MLX5_HASH_FIELD_SEL_L4_DPORT)
2587 #define MLX5_HASH_IP_IPSEC_SPI (MLX5_HASH_FIELD_SEL_SRC_IP |\
2588 MLX5_HASH_FIELD_SEL_DST_IP |\
2589 MLX5_HASH_FIELD_SEL_IPSEC_SPI)
2591 MLX5_SET(tirc, tirc, rx_hash_fn, mlx5e_rx_hash_fn(params->rss_hfunc));
2592 if (params->rss_hfunc == ETH_RSS_HASH_TOP) {
2593 void *rss_key = MLX5_ADDR_OF(tirc, tirc,
2594 rx_hash_toeplitz_key);
2595 size_t len = MLX5_FLD_SZ_BYTES(tirc,
2596 rx_hash_toeplitz_key);
2598 MLX5_SET(tirc, tirc, rx_hash_symmetric, 1);
2599 memcpy(rss_key, params->toeplitz_hash_key, len);
2603 case MLX5E_TT_IPV4_TCP:
2604 MLX5_SET(rx_hash_field_select, hfso, l3_prot_type,
2605 MLX5_L3_PROT_TYPE_IPV4);
2606 MLX5_SET(rx_hash_field_select, hfso, l4_prot_type,
2607 MLX5_L4_PROT_TYPE_TCP);
2608 MLX5_SET(rx_hash_field_select, hfso, selected_fields,
2609 MLX5_HASH_IP_L4PORTS);
2612 case MLX5E_TT_IPV6_TCP:
2613 MLX5_SET(rx_hash_field_select, hfso, l3_prot_type,
2614 MLX5_L3_PROT_TYPE_IPV6);
2615 MLX5_SET(rx_hash_field_select, hfso, l4_prot_type,
2616 MLX5_L4_PROT_TYPE_TCP);
2617 MLX5_SET(rx_hash_field_select, hfso, selected_fields,
2618 MLX5_HASH_IP_L4PORTS);
2621 case MLX5E_TT_IPV4_UDP:
2622 MLX5_SET(rx_hash_field_select, hfso, l3_prot_type,
2623 MLX5_L3_PROT_TYPE_IPV4);
2624 MLX5_SET(rx_hash_field_select, hfso, l4_prot_type,
2625 MLX5_L4_PROT_TYPE_UDP);
2626 MLX5_SET(rx_hash_field_select, hfso, selected_fields,
2627 MLX5_HASH_IP_L4PORTS);
2630 case MLX5E_TT_IPV6_UDP:
2631 MLX5_SET(rx_hash_field_select, hfso, l3_prot_type,
2632 MLX5_L3_PROT_TYPE_IPV6);
2633 MLX5_SET(rx_hash_field_select, hfso, l4_prot_type,
2634 MLX5_L4_PROT_TYPE_UDP);
2635 MLX5_SET(rx_hash_field_select, hfso, selected_fields,
2636 MLX5_HASH_IP_L4PORTS);
2639 case MLX5E_TT_IPV4_IPSEC_AH:
2640 MLX5_SET(rx_hash_field_select, hfso, l3_prot_type,
2641 MLX5_L3_PROT_TYPE_IPV4);
2642 MLX5_SET(rx_hash_field_select, hfso, selected_fields,
2643 MLX5_HASH_IP_IPSEC_SPI);
2646 case MLX5E_TT_IPV6_IPSEC_AH:
2647 MLX5_SET(rx_hash_field_select, hfso, l3_prot_type,
2648 MLX5_L3_PROT_TYPE_IPV6);
2649 MLX5_SET(rx_hash_field_select, hfso, selected_fields,
2650 MLX5_HASH_IP_IPSEC_SPI);
2653 case MLX5E_TT_IPV4_IPSEC_ESP:
2654 MLX5_SET(rx_hash_field_select, hfso, l3_prot_type,
2655 MLX5_L3_PROT_TYPE_IPV4);
2656 MLX5_SET(rx_hash_field_select, hfso, selected_fields,
2657 MLX5_HASH_IP_IPSEC_SPI);
2660 case MLX5E_TT_IPV6_IPSEC_ESP:
2661 MLX5_SET(rx_hash_field_select, hfso, l3_prot_type,
2662 MLX5_L3_PROT_TYPE_IPV6);
2663 MLX5_SET(rx_hash_field_select, hfso, selected_fields,
2664 MLX5_HASH_IP_IPSEC_SPI);
2668 MLX5_SET(rx_hash_field_select, hfso, l3_prot_type,
2669 MLX5_L3_PROT_TYPE_IPV4);
2670 MLX5_SET(rx_hash_field_select, hfso, selected_fields,
2675 MLX5_SET(rx_hash_field_select, hfso, l3_prot_type,
2676 MLX5_L3_PROT_TYPE_IPV6);
2677 MLX5_SET(rx_hash_field_select, hfso, selected_fields,
2681 WARN_ONCE(true, "%s: bad traffic type!\n", __func__);
2685 static int mlx5e_modify_tirs_lro(struct mlx5e_priv *priv)
2687 struct mlx5_core_dev *mdev = priv->mdev;
2696 inlen = MLX5_ST_SZ_BYTES(modify_tir_in);
2697 in = kvzalloc(inlen, GFP_KERNEL);
2701 MLX5_SET(modify_tir_in, in, bitmask.lro, 1);
2702 tirc = MLX5_ADDR_OF(modify_tir_in, in, ctx);
2704 mlx5e_build_tir_ctx_lro(&priv->channels.params, tirc);
2706 for (tt = 0; tt < MLX5E_NUM_INDIR_TIRS; tt++) {
2707 err = mlx5_core_modify_tir(mdev, priv->indir_tir[tt].tirn, in,
2713 for (ix = 0; ix < priv->profile->max_nch(priv->mdev); ix++) {
2714 err = mlx5_core_modify_tir(mdev, priv->direct_tir[ix].tirn,
2726 static void mlx5e_build_inner_indir_tir_ctx(struct mlx5e_priv *priv,
2727 enum mlx5e_traffic_types tt,
2730 MLX5_SET(tirc, tirc, transport_domain, priv->mdev->mlx5e_res.td.tdn);
2732 mlx5e_build_tir_ctx_lro(&priv->channels.params, tirc);
2734 MLX5_SET(tirc, tirc, disp_type, MLX5_TIRC_DISP_TYPE_INDIRECT);
2735 MLX5_SET(tirc, tirc, indirect_table, priv->indir_rqt.rqtn);
2736 MLX5_SET(tirc, tirc, tunneled_offload_en, 0x1);
2738 mlx5e_build_indir_tir_ctx_hash(&priv->channels.params, tt, tirc, true);
2741 static int mlx5e_set_mtu(struct mlx5_core_dev *mdev,
2742 struct mlx5e_params *params, u16 mtu)
2744 u16 hw_mtu = MLX5E_SW2HW_MTU(params, mtu);
2747 err = mlx5_set_port_mtu(mdev, hw_mtu, 1);
2751 /* Update vport context MTU */
2752 mlx5_modify_nic_vport_mtu(mdev, hw_mtu);
2756 static void mlx5e_query_mtu(struct mlx5_core_dev *mdev,
2757 struct mlx5e_params *params, u16 *mtu)
2762 err = mlx5_query_nic_vport_mtu(mdev, &hw_mtu);
2763 if (err || !hw_mtu) /* fallback to port oper mtu */
2764 mlx5_query_port_oper_mtu(mdev, &hw_mtu, 1);
2766 *mtu = MLX5E_HW2SW_MTU(params, hw_mtu);
2769 static int mlx5e_set_dev_port_mtu(struct mlx5e_priv *priv)
2771 struct mlx5e_params *params = &priv->channels.params;
2772 struct net_device *netdev = priv->netdev;
2773 struct mlx5_core_dev *mdev = priv->mdev;
2777 err = mlx5e_set_mtu(mdev, params, params->sw_mtu);
2781 mlx5e_query_mtu(mdev, params, &mtu);
2782 if (mtu != params->sw_mtu)
2783 netdev_warn(netdev, "%s: VPort MTU %d is different than netdev mtu %d\n",
2784 __func__, mtu, params->sw_mtu);
2786 params->sw_mtu = mtu;
2790 static void mlx5e_netdev_set_tcs(struct net_device *netdev)
2792 struct mlx5e_priv *priv = netdev_priv(netdev);
2793 int nch = priv->channels.params.num_channels;
2794 int ntc = priv->channels.params.num_tc;
2797 netdev_reset_tc(netdev);
2802 netdev_set_num_tc(netdev, ntc);
2804 /* Map netdev TCs to offset 0
2805 * We have our own UP to TXQ mapping for QoS
2807 for (tc = 0; tc < ntc; tc++)
2808 netdev_set_tc_queue(netdev, tc, nch, 0);
2811 static void mlx5e_build_tc2txq_maps(struct mlx5e_priv *priv)
2813 int max_nch = priv->profile->max_nch(priv->mdev);
2816 for (i = 0; i < max_nch; i++)
2817 for (tc = 0; tc < priv->profile->max_tc; tc++)
2818 priv->channel_tc2txq[i][tc] = i + tc * max_nch;
2821 static void mlx5e_build_tx2sq_maps(struct mlx5e_priv *priv)
2823 struct mlx5e_channel *c;
2824 struct mlx5e_txqsq *sq;
2827 for (i = 0; i < priv->channels.num; i++) {
2828 c = priv->channels.c[i];
2829 for (tc = 0; tc < c->num_tc; tc++) {
2831 priv->txq2sq[sq->txq_ix] = sq;
2836 void mlx5e_activate_priv_channels(struct mlx5e_priv *priv)
2838 int num_txqs = priv->channels.num * priv->channels.params.num_tc;
2839 struct net_device *netdev = priv->netdev;
2841 mlx5e_netdev_set_tcs(netdev);
2842 netif_set_real_num_tx_queues(netdev, num_txqs);
2843 netif_set_real_num_rx_queues(netdev, priv->channels.num);
2845 mlx5e_build_tx2sq_maps(priv);
2846 mlx5e_activate_channels(&priv->channels);
2847 netif_tx_start_all_queues(priv->netdev);
2849 if (MLX5_VPORT_MANAGER(priv->mdev))
2850 mlx5e_add_sqs_fwd_rules(priv);
2852 mlx5e_wait_channels_min_rx_wqes(&priv->channels);
2853 mlx5e_redirect_rqts_to_channels(priv, &priv->channels);
2856 void mlx5e_deactivate_priv_channels(struct mlx5e_priv *priv)
2858 mlx5e_redirect_rqts_to_drop(priv);
2860 if (MLX5_VPORT_MANAGER(priv->mdev))
2861 mlx5e_remove_sqs_fwd_rules(priv);
2863 /* FIXME: This is a W/A only for tx timeout watch dog false alarm when
2864 * polling for inactive tx queues.
2866 netif_tx_stop_all_queues(priv->netdev);
2867 netif_tx_disable(priv->netdev);
2868 mlx5e_deactivate_channels(&priv->channels);
2871 void mlx5e_switch_priv_channels(struct mlx5e_priv *priv,
2872 struct mlx5e_channels *new_chs,
2873 mlx5e_fp_hw_modify hw_modify)
2875 struct net_device *netdev = priv->netdev;
2878 new_num_txqs = new_chs->num * new_chs->params.num_tc;
2880 carrier_ok = netif_carrier_ok(netdev);
2881 netif_carrier_off(netdev);
2883 if (new_num_txqs < netdev->real_num_tx_queues)
2884 netif_set_real_num_tx_queues(netdev, new_num_txqs);
2886 mlx5e_deactivate_priv_channels(priv);
2887 mlx5e_close_channels(&priv->channels);
2889 priv->channels = *new_chs;
2891 /* New channels are ready to roll, modify HW settings if needed */
2895 mlx5e_refresh_tirs(priv, false);
2896 mlx5e_activate_priv_channels(priv);
2898 /* return carrier back if needed */
2900 netif_carrier_on(netdev);
2903 void mlx5e_timestamp_init(struct mlx5e_priv *priv)
2905 priv->tstamp.tx_type = HWTSTAMP_TX_OFF;
2906 priv->tstamp.rx_filter = HWTSTAMP_FILTER_NONE;
2909 int mlx5e_open_locked(struct net_device *netdev)
2911 struct mlx5e_priv *priv = netdev_priv(netdev);
2914 set_bit(MLX5E_STATE_OPENED, &priv->state);
2916 err = mlx5e_open_channels(priv, &priv->channels);
2918 goto err_clear_state_opened_flag;
2920 mlx5e_refresh_tirs(priv, false);
2921 mlx5e_activate_priv_channels(priv);
2922 if (priv->profile->update_carrier)
2923 priv->profile->update_carrier(priv);
2925 if (priv->profile->update_stats)
2926 queue_delayed_work(priv->wq, &priv->update_stats_work, 0);
2930 err_clear_state_opened_flag:
2931 clear_bit(MLX5E_STATE_OPENED, &priv->state);
2935 int mlx5e_open(struct net_device *netdev)
2937 struct mlx5e_priv *priv = netdev_priv(netdev);
2940 mutex_lock(&priv->state_lock);
2941 err = mlx5e_open_locked(netdev);
2943 mlx5_set_port_admin_status(priv->mdev, MLX5_PORT_UP);
2944 mutex_unlock(&priv->state_lock);
2946 if (mlx5e_vxlan_allowed(priv->mdev))
2947 udp_tunnel_get_rx_info(netdev);
2952 int mlx5e_close_locked(struct net_device *netdev)
2954 struct mlx5e_priv *priv = netdev_priv(netdev);
2956 /* May already be CLOSED in case a previous configuration operation
2957 * (e.g RX/TX queue size change) that involves close&open failed.
2959 if (!test_bit(MLX5E_STATE_OPENED, &priv->state))
2962 clear_bit(MLX5E_STATE_OPENED, &priv->state);
2964 netif_carrier_off(priv->netdev);
2965 mlx5e_deactivate_priv_channels(priv);
2966 mlx5e_close_channels(&priv->channels);
2971 int mlx5e_close(struct net_device *netdev)
2973 struct mlx5e_priv *priv = netdev_priv(netdev);
2976 if (!netif_device_present(netdev))
2979 mutex_lock(&priv->state_lock);
2980 mlx5_set_port_admin_status(priv->mdev, MLX5_PORT_DOWN);
2981 err = mlx5e_close_locked(netdev);
2982 mutex_unlock(&priv->state_lock);
2987 static int mlx5e_alloc_drop_rq(struct mlx5_core_dev *mdev,
2988 struct mlx5e_rq *rq,
2989 struct mlx5e_rq_param *param)
2991 void *rqc = param->rqc;
2992 void *rqc_wq = MLX5_ADDR_OF(rqc, rqc, wq);
2995 param->wq.db_numa_node = param->wq.buf_numa_node;
2997 err = mlx5_wq_cyc_create(mdev, ¶m->wq, rqc_wq, &rq->wqe.wq,
3002 /* Mark as unused given "Drop-RQ" packets never reach XDP */
3003 xdp_rxq_info_unused(&rq->xdp_rxq);
3010 static int mlx5e_alloc_drop_cq(struct mlx5_core_dev *mdev,
3011 struct mlx5e_cq *cq,
3012 struct mlx5e_cq_param *param)
3014 param->wq.buf_numa_node = dev_to_node(&mdev->pdev->dev);
3015 param->wq.db_numa_node = dev_to_node(&mdev->pdev->dev);
3017 return mlx5e_alloc_cq_common(mdev, param, cq);
3020 static int mlx5e_open_drop_rq(struct mlx5e_priv *priv,
3021 struct mlx5e_rq *drop_rq)
3023 struct mlx5_core_dev *mdev = priv->mdev;
3024 struct mlx5e_cq_param cq_param = {};
3025 struct mlx5e_rq_param rq_param = {};
3026 struct mlx5e_cq *cq = &drop_rq->cq;
3029 mlx5e_build_drop_rq_param(priv, &rq_param);
3031 err = mlx5e_alloc_drop_cq(mdev, cq, &cq_param);
3035 err = mlx5e_create_cq(cq, &cq_param);
3039 err = mlx5e_alloc_drop_rq(mdev, drop_rq, &rq_param);
3041 goto err_destroy_cq;
3043 err = mlx5e_create_rq(drop_rq, &rq_param);
3047 err = mlx5e_modify_rq_state(drop_rq, MLX5_RQC_STATE_RST, MLX5_RQC_STATE_RDY);
3049 mlx5_core_warn(priv->mdev, "modify_rq_state failed, rx_if_down_packets won't be counted %d\n", err);
3054 mlx5e_free_rq(drop_rq);
3057 mlx5e_destroy_cq(cq);
3065 static void mlx5e_close_drop_rq(struct mlx5e_rq *drop_rq)
3067 mlx5e_destroy_rq(drop_rq);
3068 mlx5e_free_rq(drop_rq);
3069 mlx5e_destroy_cq(&drop_rq->cq);
3070 mlx5e_free_cq(&drop_rq->cq);
3073 int mlx5e_create_tis(struct mlx5_core_dev *mdev, int tc,
3074 u32 underlay_qpn, u32 *tisn)
3076 u32 in[MLX5_ST_SZ_DW(create_tis_in)] = {0};
3077 void *tisc = MLX5_ADDR_OF(create_tis_in, in, ctx);
3079 MLX5_SET(tisc, tisc, prio, tc << 1);
3080 MLX5_SET(tisc, tisc, underlay_qpn, underlay_qpn);
3081 MLX5_SET(tisc, tisc, transport_domain, mdev->mlx5e_res.td.tdn);
3083 if (mlx5_lag_is_lacp_owner(mdev))
3084 MLX5_SET(tisc, tisc, strict_lag_tx_port_affinity, 1);
3086 return mlx5_core_create_tis(mdev, in, sizeof(in), tisn);
3089 void mlx5e_destroy_tis(struct mlx5_core_dev *mdev, u32 tisn)
3091 mlx5_core_destroy_tis(mdev, tisn);
3094 int mlx5e_create_tises(struct mlx5e_priv *priv)
3099 for (tc = 0; tc < priv->profile->max_tc; tc++) {
3100 err = mlx5e_create_tis(priv->mdev, tc, 0, &priv->tisn[tc]);
3102 goto err_close_tises;
3108 for (tc--; tc >= 0; tc--)
3109 mlx5e_destroy_tis(priv->mdev, priv->tisn[tc]);
3114 void mlx5e_cleanup_nic_tx(struct mlx5e_priv *priv)
3118 for (tc = 0; tc < priv->profile->max_tc; tc++)
3119 mlx5e_destroy_tis(priv->mdev, priv->tisn[tc]);
3122 static void mlx5e_build_indir_tir_ctx(struct mlx5e_priv *priv,
3123 enum mlx5e_traffic_types tt,
3126 MLX5_SET(tirc, tirc, transport_domain, priv->mdev->mlx5e_res.td.tdn);
3128 mlx5e_build_tir_ctx_lro(&priv->channels.params, tirc);
3130 MLX5_SET(tirc, tirc, disp_type, MLX5_TIRC_DISP_TYPE_INDIRECT);
3131 MLX5_SET(tirc, tirc, indirect_table, priv->indir_rqt.rqtn);
3132 mlx5e_build_indir_tir_ctx_hash(&priv->channels.params, tt, tirc, false);
3135 static void mlx5e_build_direct_tir_ctx(struct mlx5e_priv *priv, u32 rqtn, u32 *tirc)
3137 MLX5_SET(tirc, tirc, transport_domain, priv->mdev->mlx5e_res.td.tdn);
3139 mlx5e_build_tir_ctx_lro(&priv->channels.params, tirc);
3141 MLX5_SET(tirc, tirc, disp_type, MLX5_TIRC_DISP_TYPE_INDIRECT);
3142 MLX5_SET(tirc, tirc, indirect_table, rqtn);
3143 MLX5_SET(tirc, tirc, rx_hash_fn, MLX5_RX_HASH_FN_INVERTED_XOR8);
3146 int mlx5e_create_indirect_tirs(struct mlx5e_priv *priv)
3148 struct mlx5e_tir *tir;
3156 inlen = MLX5_ST_SZ_BYTES(create_tir_in);
3157 in = kvzalloc(inlen, GFP_KERNEL);
3161 for (tt = 0; tt < MLX5E_NUM_INDIR_TIRS; tt++) {
3162 memset(in, 0, inlen);
3163 tir = &priv->indir_tir[tt];
3164 tirc = MLX5_ADDR_OF(create_tir_in, in, ctx);
3165 mlx5e_build_indir_tir_ctx(priv, tt, tirc);
3166 err = mlx5e_create_tir(priv->mdev, tir, in, inlen);
3168 mlx5_core_warn(priv->mdev, "create indirect tirs failed, %d\n", err);
3169 goto err_destroy_inner_tirs;
3173 if (!mlx5e_tunnel_inner_ft_supported(priv->mdev))
3176 for (i = 0; i < MLX5E_NUM_INDIR_TIRS; i++) {
3177 memset(in, 0, inlen);
3178 tir = &priv->inner_indir_tir[i];
3179 tirc = MLX5_ADDR_OF(create_tir_in, in, ctx);
3180 mlx5e_build_inner_indir_tir_ctx(priv, i, tirc);
3181 err = mlx5e_create_tir(priv->mdev, tir, in, inlen);
3183 mlx5_core_warn(priv->mdev, "create inner indirect tirs failed, %d\n", err);
3184 goto err_destroy_inner_tirs;
3193 err_destroy_inner_tirs:
3194 for (i--; i >= 0; i--)
3195 mlx5e_destroy_tir(priv->mdev, &priv->inner_indir_tir[i]);
3197 for (tt--; tt >= 0; tt--)
3198 mlx5e_destroy_tir(priv->mdev, &priv->indir_tir[tt]);
3205 int mlx5e_create_direct_tirs(struct mlx5e_priv *priv)
3207 int nch = priv->profile->max_nch(priv->mdev);
3208 struct mlx5e_tir *tir;
3215 inlen = MLX5_ST_SZ_BYTES(create_tir_in);
3216 in = kvzalloc(inlen, GFP_KERNEL);
3220 for (ix = 0; ix < nch; ix++) {
3221 memset(in, 0, inlen);
3222 tir = &priv->direct_tir[ix];
3223 tirc = MLX5_ADDR_OF(create_tir_in, in, ctx);
3224 mlx5e_build_direct_tir_ctx(priv, priv->direct_tir[ix].rqt.rqtn, tirc);
3225 err = mlx5e_create_tir(priv->mdev, tir, in, inlen);
3227 goto err_destroy_ch_tirs;
3234 err_destroy_ch_tirs:
3235 mlx5_core_warn(priv->mdev, "create direct tirs failed, %d\n", err);
3236 for (ix--; ix >= 0; ix--)
3237 mlx5e_destroy_tir(priv->mdev, &priv->direct_tir[ix]);
3244 void mlx5e_destroy_indirect_tirs(struct mlx5e_priv *priv)
3248 for (i = 0; i < MLX5E_NUM_INDIR_TIRS; i++)
3249 mlx5e_destroy_tir(priv->mdev, &priv->indir_tir[i]);
3251 if (!mlx5e_tunnel_inner_ft_supported(priv->mdev))
3254 for (i = 0; i < MLX5E_NUM_INDIR_TIRS; i++)
3255 mlx5e_destroy_tir(priv->mdev, &priv->inner_indir_tir[i]);
3258 void mlx5e_destroy_direct_tirs(struct mlx5e_priv *priv)
3260 int nch = priv->profile->max_nch(priv->mdev);
3263 for (i = 0; i < nch; i++)
3264 mlx5e_destroy_tir(priv->mdev, &priv->direct_tir[i]);
3267 static int mlx5e_modify_channels_scatter_fcs(struct mlx5e_channels *chs, bool enable)
3272 for (i = 0; i < chs->num; i++) {
3273 err = mlx5e_modify_rq_scatter_fcs(&chs->c[i]->rq, enable);
3281 static int mlx5e_modify_channels_vsd(struct mlx5e_channels *chs, bool vsd)
3286 for (i = 0; i < chs->num; i++) {
3287 err = mlx5e_modify_rq_vsd(&chs->c[i]->rq, vsd);
3295 static int mlx5e_setup_tc_mqprio(struct net_device *netdev,
3296 struct tc_mqprio_qopt *mqprio)
3298 struct mlx5e_priv *priv = netdev_priv(netdev);
3299 struct mlx5e_channels new_channels = {};
3300 u8 tc = mqprio->num_tc;
3303 mqprio->hw = TC_MQPRIO_HW_OFFLOAD_TCS;
3305 if (tc && tc != MLX5E_MAX_NUM_TC)
3308 mutex_lock(&priv->state_lock);
3310 new_channels.params = priv->channels.params;
3311 new_channels.params.num_tc = tc ? tc : 1;
3313 if (!test_bit(MLX5E_STATE_OPENED, &priv->state)) {
3314 priv->channels.params = new_channels.params;
3318 err = mlx5e_open_channels(priv, &new_channels);
3322 priv->max_opened_tc = max_t(u8, priv->max_opened_tc,
3323 new_channels.params.num_tc);
3324 mlx5e_switch_priv_channels(priv, &new_channels, NULL);
3326 mutex_unlock(&priv->state_lock);
3330 #ifdef CONFIG_MLX5_ESWITCH
3331 static int mlx5e_setup_tc_cls_flower(struct mlx5e_priv *priv,
3332 struct tc_cls_flower_offload *cls_flower,
3335 switch (cls_flower->command) {
3336 case TC_CLSFLOWER_REPLACE:
3337 return mlx5e_configure_flower(priv, cls_flower, flags);
3338 case TC_CLSFLOWER_DESTROY:
3339 return mlx5e_delete_flower(priv, cls_flower, flags);
3340 case TC_CLSFLOWER_STATS:
3341 return mlx5e_stats_flower(priv, cls_flower, flags);
3347 static int mlx5e_setup_tc_block_cb(enum tc_setup_type type, void *type_data,
3350 struct mlx5e_priv *priv = cb_priv;
3352 if (!tc_cls_can_offload_and_chain0(priv->netdev, type_data))
3356 case TC_SETUP_CLSFLOWER:
3357 return mlx5e_setup_tc_cls_flower(priv, type_data, MLX5E_TC_INGRESS);
3363 static int mlx5e_setup_tc_block(struct net_device *dev,
3364 struct tc_block_offload *f)
3366 struct mlx5e_priv *priv = netdev_priv(dev);
3368 if (f->binder_type != TCF_BLOCK_BINDER_TYPE_CLSACT_INGRESS)
3371 switch (f->command) {
3373 return tcf_block_cb_register(f->block, mlx5e_setup_tc_block_cb,
3374 priv, priv, f->extack);
3375 case TC_BLOCK_UNBIND:
3376 tcf_block_cb_unregister(f->block, mlx5e_setup_tc_block_cb,
3385 static int mlx5e_setup_tc(struct net_device *dev, enum tc_setup_type type,
3389 #ifdef CONFIG_MLX5_ESWITCH
3390 case TC_SETUP_BLOCK:
3391 return mlx5e_setup_tc_block(dev, type_data);
3393 case TC_SETUP_QDISC_MQPRIO:
3394 return mlx5e_setup_tc_mqprio(dev, type_data);
3401 mlx5e_get_stats(struct net_device *dev, struct rtnl_link_stats64 *stats)
3403 struct mlx5e_priv *priv = netdev_priv(dev);
3404 struct mlx5e_sw_stats *sstats = &priv->stats.sw;
3405 struct mlx5e_vport_stats *vstats = &priv->stats.vport;
3406 struct mlx5e_pport_stats *pstats = &priv->stats.pport;
3408 if (mlx5e_is_uplink_rep(priv)) {
3409 stats->rx_packets = PPORT_802_3_GET(pstats, a_frames_received_ok);
3410 stats->rx_bytes = PPORT_802_3_GET(pstats, a_octets_received_ok);
3411 stats->tx_packets = PPORT_802_3_GET(pstats, a_frames_transmitted_ok);
3412 stats->tx_bytes = PPORT_802_3_GET(pstats, a_octets_transmitted_ok);
3414 mlx5e_grp_sw_update_stats(priv);
3415 stats->rx_packets = sstats->rx_packets;
3416 stats->rx_bytes = sstats->rx_bytes;
3417 stats->tx_packets = sstats->tx_packets;
3418 stats->tx_bytes = sstats->tx_bytes;
3419 stats->tx_dropped = sstats->tx_queue_dropped;
3422 stats->rx_dropped = priv->stats.qcnt.rx_out_of_buffer;
3424 stats->rx_length_errors =
3425 PPORT_802_3_GET(pstats, a_in_range_length_errors) +
3426 PPORT_802_3_GET(pstats, a_out_of_range_length_field) +
3427 PPORT_802_3_GET(pstats, a_frame_too_long_errors);
3428 stats->rx_crc_errors =
3429 PPORT_802_3_GET(pstats, a_frame_check_sequence_errors);
3430 stats->rx_frame_errors = PPORT_802_3_GET(pstats, a_alignment_errors);
3431 stats->tx_aborted_errors = PPORT_2863_GET(pstats, if_out_discards);
3432 stats->rx_errors = stats->rx_length_errors + stats->rx_crc_errors +
3433 stats->rx_frame_errors;
3434 stats->tx_errors = stats->tx_aborted_errors + stats->tx_carrier_errors;
3436 /* vport multicast also counts packets that are dropped due to steering
3437 * or rx out of buffer
3440 VPORT_COUNTER_GET(vstats, received_eth_multicast.packets);
3443 static void mlx5e_set_rx_mode(struct net_device *dev)
3445 struct mlx5e_priv *priv = netdev_priv(dev);
3447 queue_work(priv->wq, &priv->set_rx_mode_work);
3450 static int mlx5e_set_mac(struct net_device *netdev, void *addr)
3452 struct mlx5e_priv *priv = netdev_priv(netdev);
3453 struct sockaddr *saddr = addr;
3455 if (!is_valid_ether_addr(saddr->sa_data))
3456 return -EADDRNOTAVAIL;
3458 netif_addr_lock_bh(netdev);
3459 ether_addr_copy(netdev->dev_addr, saddr->sa_data);
3460 netif_addr_unlock_bh(netdev);
3462 queue_work(priv->wq, &priv->set_rx_mode_work);
3467 #define MLX5E_SET_FEATURE(features, feature, enable) \
3470 *features |= feature; \
3472 *features &= ~feature; \
3475 typedef int (*mlx5e_feature_handler)(struct net_device *netdev, bool enable);
3477 static int set_feature_lro(struct net_device *netdev, bool enable)
3479 struct mlx5e_priv *priv = netdev_priv(netdev);
3480 struct mlx5_core_dev *mdev = priv->mdev;
3481 struct mlx5e_channels new_channels = {};
3482 struct mlx5e_params *old_params;
3486 mutex_lock(&priv->state_lock);
3488 old_params = &priv->channels.params;
3489 if (enable && !MLX5E_GET_PFLAG(old_params, MLX5E_PFLAG_RX_STRIDING_RQ)) {
3490 netdev_warn(netdev, "can't set LRO with legacy RQ\n");
3495 reset = test_bit(MLX5E_STATE_OPENED, &priv->state);
3497 new_channels.params = *old_params;
3498 new_channels.params.lro_en = enable;
3500 if (old_params->rq_wq_type != MLX5_WQ_TYPE_CYCLIC) {
3501 if (mlx5e_rx_mpwqe_is_linear_skb(mdev, old_params) ==
3502 mlx5e_rx_mpwqe_is_linear_skb(mdev, &new_channels.params))
3507 *old_params = new_channels.params;
3508 err = mlx5e_modify_tirs_lro(priv);
3512 err = mlx5e_open_channels(priv, &new_channels);
3516 mlx5e_switch_priv_channels(priv, &new_channels, mlx5e_modify_tirs_lro);
3518 mutex_unlock(&priv->state_lock);
3522 static int set_feature_cvlan_filter(struct net_device *netdev, bool enable)
3524 struct mlx5e_priv *priv = netdev_priv(netdev);
3527 mlx5e_enable_cvlan_filter(priv);
3529 mlx5e_disable_cvlan_filter(priv);
3534 static int set_feature_tc_num_filters(struct net_device *netdev, bool enable)
3536 struct mlx5e_priv *priv = netdev_priv(netdev);
3538 if (!enable && mlx5e_tc_num_filters(priv)) {
3540 "Active offloaded tc filters, can't turn hw_tc_offload off\n");
3547 static int set_feature_rx_all(struct net_device *netdev, bool enable)
3549 struct mlx5e_priv *priv = netdev_priv(netdev);
3550 struct mlx5_core_dev *mdev = priv->mdev;
3552 return mlx5_set_port_fcs(mdev, !enable);
3555 static int set_feature_rx_fcs(struct net_device *netdev, bool enable)
3557 struct mlx5e_priv *priv = netdev_priv(netdev);
3560 mutex_lock(&priv->state_lock);
3562 priv->channels.params.scatter_fcs_en = enable;
3563 err = mlx5e_modify_channels_scatter_fcs(&priv->channels, enable);
3565 priv->channels.params.scatter_fcs_en = !enable;
3567 mutex_unlock(&priv->state_lock);
3572 static int set_feature_rx_vlan(struct net_device *netdev, bool enable)
3574 struct mlx5e_priv *priv = netdev_priv(netdev);
3577 mutex_lock(&priv->state_lock);
3579 priv->channels.params.vlan_strip_disable = !enable;
3580 if (!test_bit(MLX5E_STATE_OPENED, &priv->state))
3583 err = mlx5e_modify_channels_vsd(&priv->channels, !enable);
3585 priv->channels.params.vlan_strip_disable = enable;
3588 mutex_unlock(&priv->state_lock);
3593 #ifdef CONFIG_RFS_ACCEL
3594 static int set_feature_arfs(struct net_device *netdev, bool enable)
3596 struct mlx5e_priv *priv = netdev_priv(netdev);
3600 err = mlx5e_arfs_enable(priv);
3602 err = mlx5e_arfs_disable(priv);
3608 static int mlx5e_handle_feature(struct net_device *netdev,
3609 netdev_features_t *features,
3610 netdev_features_t wanted_features,
3611 netdev_features_t feature,
3612 mlx5e_feature_handler feature_handler)
3614 netdev_features_t changes = wanted_features ^ netdev->features;
3615 bool enable = !!(wanted_features & feature);
3618 if (!(changes & feature))
3621 err = feature_handler(netdev, enable);
3623 netdev_err(netdev, "%s feature %pNF failed, err %d\n",
3624 enable ? "Enable" : "Disable", &feature, err);
3628 MLX5E_SET_FEATURE(features, feature, enable);
3632 static int mlx5e_set_features(struct net_device *netdev,
3633 netdev_features_t features)
3635 netdev_features_t oper_features = netdev->features;
3638 #define MLX5E_HANDLE_FEATURE(feature, handler) \
3639 mlx5e_handle_feature(netdev, &oper_features, features, feature, handler)
3641 err |= MLX5E_HANDLE_FEATURE(NETIF_F_LRO, set_feature_lro);
3642 err |= MLX5E_HANDLE_FEATURE(NETIF_F_HW_VLAN_CTAG_FILTER,
3643 set_feature_cvlan_filter);
3644 err |= MLX5E_HANDLE_FEATURE(NETIF_F_HW_TC, set_feature_tc_num_filters);
3645 err |= MLX5E_HANDLE_FEATURE(NETIF_F_RXALL, set_feature_rx_all);
3646 err |= MLX5E_HANDLE_FEATURE(NETIF_F_RXFCS, set_feature_rx_fcs);
3647 err |= MLX5E_HANDLE_FEATURE(NETIF_F_HW_VLAN_CTAG_RX, set_feature_rx_vlan);
3648 #ifdef CONFIG_RFS_ACCEL
3649 err |= MLX5E_HANDLE_FEATURE(NETIF_F_NTUPLE, set_feature_arfs);
3653 netdev->features = oper_features;
3660 static netdev_features_t mlx5e_fix_features(struct net_device *netdev,
3661 netdev_features_t features)
3663 struct mlx5e_priv *priv = netdev_priv(netdev);
3664 struct mlx5e_params *params;
3666 mutex_lock(&priv->state_lock);
3667 params = &priv->channels.params;
3668 if (!bitmap_empty(priv->fs.vlan.active_svlans, VLAN_N_VID)) {
3669 /* HW strips the outer C-tag header, this is a problem
3670 * for S-tag traffic.
3672 features &= ~NETIF_F_HW_VLAN_CTAG_RX;
3673 if (!params->vlan_strip_disable)
3674 netdev_warn(netdev, "Dropping C-tag vlan stripping offload due to S-tag vlan\n");
3676 if (!MLX5E_GET_PFLAG(params, MLX5E_PFLAG_RX_STRIDING_RQ)) {
3677 features &= ~NETIF_F_LRO;
3679 netdev_warn(netdev, "Disabling LRO, not supported in legacy RQ\n");
3682 mutex_unlock(&priv->state_lock);
3687 int mlx5e_change_mtu(struct net_device *netdev, int new_mtu,
3688 change_hw_mtu_cb set_mtu_cb)
3690 struct mlx5e_priv *priv = netdev_priv(netdev);
3691 struct mlx5e_channels new_channels = {};
3692 struct mlx5e_params *params;
3696 mutex_lock(&priv->state_lock);
3698 params = &priv->channels.params;
3700 reset = !params->lro_en;
3701 reset = reset && test_bit(MLX5E_STATE_OPENED, &priv->state);
3703 new_channels.params = *params;
3704 new_channels.params.sw_mtu = new_mtu;
3706 if (params->rq_wq_type == MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ) {
3707 u8 ppw_old = mlx5e_mpwqe_log_pkts_per_wqe(params);
3708 u8 ppw_new = mlx5e_mpwqe_log_pkts_per_wqe(&new_channels.params);
3710 reset = reset && (ppw_old != ppw_new);
3714 params->sw_mtu = new_mtu;
3716 netdev->mtu = params->sw_mtu;
3720 err = mlx5e_open_channels(priv, &new_channels);
3724 mlx5e_switch_priv_channels(priv, &new_channels, set_mtu_cb);
3725 netdev->mtu = new_channels.params.sw_mtu;
3728 mutex_unlock(&priv->state_lock);
3732 static int mlx5e_change_nic_mtu(struct net_device *netdev, int new_mtu)
3734 return mlx5e_change_mtu(netdev, new_mtu, mlx5e_set_dev_port_mtu);
3737 int mlx5e_hwstamp_set(struct mlx5e_priv *priv, struct ifreq *ifr)
3739 struct hwtstamp_config config;
3742 if (!MLX5_CAP_GEN(priv->mdev, device_frequency_khz))
3745 if (copy_from_user(&config, ifr->ifr_data, sizeof(config)))
3748 /* TX HW timestamp */
3749 switch (config.tx_type) {
3750 case HWTSTAMP_TX_OFF:
3751 case HWTSTAMP_TX_ON:
3757 mutex_lock(&priv->state_lock);
3758 /* RX HW timestamp */
3759 switch (config.rx_filter) {
3760 case HWTSTAMP_FILTER_NONE:
3761 /* Reset CQE compression to Admin default */
3762 mlx5e_modify_rx_cqe_compression_locked(priv, priv->channels.params.rx_cqe_compress_def);
3764 case HWTSTAMP_FILTER_ALL:
3765 case HWTSTAMP_FILTER_SOME:
3766 case HWTSTAMP_FILTER_PTP_V1_L4_EVENT:
3767 case HWTSTAMP_FILTER_PTP_V1_L4_SYNC:
3768 case HWTSTAMP_FILTER_PTP_V1_L4_DELAY_REQ:
3769 case HWTSTAMP_FILTER_PTP_V2_L4_EVENT:
3770 case HWTSTAMP_FILTER_PTP_V2_L4_SYNC:
3771 case HWTSTAMP_FILTER_PTP_V2_L4_DELAY_REQ:
3772 case HWTSTAMP_FILTER_PTP_V2_L2_EVENT:
3773 case HWTSTAMP_FILTER_PTP_V2_L2_SYNC:
3774 case HWTSTAMP_FILTER_PTP_V2_L2_DELAY_REQ:
3775 case HWTSTAMP_FILTER_PTP_V2_EVENT:
3776 case HWTSTAMP_FILTER_PTP_V2_SYNC:
3777 case HWTSTAMP_FILTER_PTP_V2_DELAY_REQ:
3778 case HWTSTAMP_FILTER_NTP_ALL:
3779 /* Disable CQE compression */
3780 netdev_warn(priv->netdev, "Disabling cqe compression");
3781 err = mlx5e_modify_rx_cqe_compression_locked(priv, false);
3783 netdev_err(priv->netdev, "Failed disabling cqe compression err=%d\n", err);
3784 mutex_unlock(&priv->state_lock);
3787 config.rx_filter = HWTSTAMP_FILTER_ALL;
3790 mutex_unlock(&priv->state_lock);
3794 memcpy(&priv->tstamp, &config, sizeof(config));
3795 mutex_unlock(&priv->state_lock);
3797 return copy_to_user(ifr->ifr_data, &config,
3798 sizeof(config)) ? -EFAULT : 0;
3801 int mlx5e_hwstamp_get(struct mlx5e_priv *priv, struct ifreq *ifr)
3803 struct hwtstamp_config *cfg = &priv->tstamp;
3805 if (!MLX5_CAP_GEN(priv->mdev, device_frequency_khz))
3808 return copy_to_user(ifr->ifr_data, cfg, sizeof(*cfg)) ? -EFAULT : 0;
3811 static int mlx5e_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
3813 struct mlx5e_priv *priv = netdev_priv(dev);
3817 return mlx5e_hwstamp_set(priv, ifr);
3819 return mlx5e_hwstamp_get(priv, ifr);
3825 #ifdef CONFIG_MLX5_ESWITCH
3826 static int mlx5e_set_vf_mac(struct net_device *dev, int vf, u8 *mac)
3828 struct mlx5e_priv *priv = netdev_priv(dev);
3829 struct mlx5_core_dev *mdev = priv->mdev;
3831 return mlx5_eswitch_set_vport_mac(mdev->priv.eswitch, vf + 1, mac);
3834 static int mlx5e_set_vf_vlan(struct net_device *dev, int vf, u16 vlan, u8 qos,
3837 struct mlx5e_priv *priv = netdev_priv(dev);
3838 struct mlx5_core_dev *mdev = priv->mdev;
3840 if (vlan_proto != htons(ETH_P_8021Q))
3841 return -EPROTONOSUPPORT;
3843 return mlx5_eswitch_set_vport_vlan(mdev->priv.eswitch, vf + 1,
3847 static int mlx5e_set_vf_spoofchk(struct net_device *dev, int vf, bool setting)
3849 struct mlx5e_priv *priv = netdev_priv(dev);
3850 struct mlx5_core_dev *mdev = priv->mdev;
3852 return mlx5_eswitch_set_vport_spoofchk(mdev->priv.eswitch, vf + 1, setting);
3855 static int mlx5e_set_vf_trust(struct net_device *dev, int vf, bool setting)
3857 struct mlx5e_priv *priv = netdev_priv(dev);
3858 struct mlx5_core_dev *mdev = priv->mdev;
3860 return mlx5_eswitch_set_vport_trust(mdev->priv.eswitch, vf + 1, setting);
3863 static int mlx5e_set_vf_rate(struct net_device *dev, int vf, int min_tx_rate,
3866 struct mlx5e_priv *priv = netdev_priv(dev);
3867 struct mlx5_core_dev *mdev = priv->mdev;
3869 return mlx5_eswitch_set_vport_rate(mdev->priv.eswitch, vf + 1,
3870 max_tx_rate, min_tx_rate);
3873 static int mlx5_vport_link2ifla(u8 esw_link)
3876 case MLX5_ESW_VPORT_ADMIN_STATE_DOWN:
3877 return IFLA_VF_LINK_STATE_DISABLE;
3878 case MLX5_ESW_VPORT_ADMIN_STATE_UP:
3879 return IFLA_VF_LINK_STATE_ENABLE;
3881 return IFLA_VF_LINK_STATE_AUTO;
3884 static int mlx5_ifla_link2vport(u8 ifla_link)
3886 switch (ifla_link) {
3887 case IFLA_VF_LINK_STATE_DISABLE:
3888 return MLX5_ESW_VPORT_ADMIN_STATE_DOWN;
3889 case IFLA_VF_LINK_STATE_ENABLE:
3890 return MLX5_ESW_VPORT_ADMIN_STATE_UP;
3892 return MLX5_ESW_VPORT_ADMIN_STATE_AUTO;
3895 static int mlx5e_set_vf_link_state(struct net_device *dev, int vf,
3898 struct mlx5e_priv *priv = netdev_priv(dev);
3899 struct mlx5_core_dev *mdev = priv->mdev;
3901 return mlx5_eswitch_set_vport_state(mdev->priv.eswitch, vf + 1,
3902 mlx5_ifla_link2vport(link_state));
3905 static int mlx5e_get_vf_config(struct net_device *dev,
3906 int vf, struct ifla_vf_info *ivi)
3908 struct mlx5e_priv *priv = netdev_priv(dev);
3909 struct mlx5_core_dev *mdev = priv->mdev;
3912 err = mlx5_eswitch_get_vport_config(mdev->priv.eswitch, vf + 1, ivi);
3915 ivi->linkstate = mlx5_vport_link2ifla(ivi->linkstate);
3919 static int mlx5e_get_vf_stats(struct net_device *dev,
3920 int vf, struct ifla_vf_stats *vf_stats)
3922 struct mlx5e_priv *priv = netdev_priv(dev);
3923 struct mlx5_core_dev *mdev = priv->mdev;
3925 return mlx5_eswitch_get_vport_stats(mdev->priv.eswitch, vf + 1,
3930 static void mlx5e_add_vxlan_port(struct net_device *netdev,
3931 struct udp_tunnel_info *ti)
3933 struct mlx5e_priv *priv = netdev_priv(netdev);
3935 if (ti->type != UDP_TUNNEL_TYPE_VXLAN)
3938 if (!mlx5e_vxlan_allowed(priv->mdev))
3941 mlx5e_vxlan_queue_work(priv, ti->sa_family, be16_to_cpu(ti->port), 1);
3944 static void mlx5e_del_vxlan_port(struct net_device *netdev,
3945 struct udp_tunnel_info *ti)
3947 struct mlx5e_priv *priv = netdev_priv(netdev);
3949 if (ti->type != UDP_TUNNEL_TYPE_VXLAN)
3952 if (!mlx5e_vxlan_allowed(priv->mdev))
3955 mlx5e_vxlan_queue_work(priv, ti->sa_family, be16_to_cpu(ti->port), 0);
3958 static netdev_features_t mlx5e_tunnel_features_check(struct mlx5e_priv *priv,
3959 struct sk_buff *skb,
3960 netdev_features_t features)
3962 unsigned int offset = 0;
3963 struct udphdr *udph;
3967 switch (vlan_get_protocol(skb)) {
3968 case htons(ETH_P_IP):
3969 proto = ip_hdr(skb)->protocol;
3971 case htons(ETH_P_IPV6):
3972 proto = ipv6_find_hdr(skb, &offset, -1, NULL, NULL);
3982 udph = udp_hdr(skb);
3983 port = be16_to_cpu(udph->dest);
3985 /* Verify if UDP port is being offloaded by HW */
3986 if (mlx5e_vxlan_lookup_port(priv, port))
3991 /* Disable CSUM and GSO if the udp dport is not offloaded by HW */
3992 return features & ~(NETIF_F_CSUM_MASK | NETIF_F_GSO_MASK);
3995 static netdev_features_t mlx5e_features_check(struct sk_buff *skb,
3996 struct net_device *netdev,
3997 netdev_features_t features)
3999 struct mlx5e_priv *priv = netdev_priv(netdev);
4001 features = vlan_features_check(skb, features);
4002 features = vxlan_features_check(skb, features);
4004 #ifdef CONFIG_MLX5_EN_IPSEC
4005 if (mlx5e_ipsec_feature_check(skb, netdev, features))
4009 /* Validate if the tunneled packet is being offloaded by HW */
4010 if (skb->encapsulation &&
4011 (features & NETIF_F_CSUM_MASK || features & NETIF_F_GSO_MASK))
4012 return mlx5e_tunnel_features_check(priv, skb, features);
4017 static bool mlx5e_tx_timeout_eq_recover(struct net_device *dev,
4018 struct mlx5e_txqsq *sq)
4020 struct mlx5_eq *eq = sq->cq.mcq.eq;
4023 netdev_err(dev, "EQ 0x%x: Cons = 0x%x, irqn = 0x%x\n",
4024 eq->eqn, eq->cons_index, eq->irqn);
4026 eqe_count = mlx5_eq_poll_irq_disabled(eq);
4030 netdev_err(dev, "Recover %d eqes on EQ 0x%x\n", eqe_count, eq->eqn);
4031 sq->channel->stats->eq_rearm++;
4035 static void mlx5e_tx_timeout_work(struct work_struct *work)
4037 struct mlx5e_priv *priv = container_of(work, struct mlx5e_priv,
4039 struct net_device *dev = priv->netdev;
4040 bool reopen_channels = false;
4044 mutex_lock(&priv->state_lock);
4046 if (!test_bit(MLX5E_STATE_OPENED, &priv->state))
4049 for (i = 0; i < priv->channels.num * priv->channels.params.num_tc; i++) {
4050 struct netdev_queue *dev_queue = netdev_get_tx_queue(dev, i);
4051 struct mlx5e_txqsq *sq = priv->txq2sq[i];
4053 if (!netif_xmit_stopped(dev_queue))
4057 "TX timeout on queue: %d, SQ: 0x%x, CQ: 0x%x, SQ Cons: 0x%x SQ Prod: 0x%x, usecs since last trans: %u\n",
4058 i, sq->sqn, sq->cq.mcq.cqn, sq->cc, sq->pc,
4059 jiffies_to_usecs(jiffies - dev_queue->trans_start));
4061 /* If we recover a lost interrupt, most likely TX timeout will
4062 * be resolved, skip reopening channels
4064 if (!mlx5e_tx_timeout_eq_recover(dev, sq)) {
4065 clear_bit(MLX5E_SQ_STATE_ENABLED, &sq->state);
4066 reopen_channels = true;
4070 if (!reopen_channels)
4073 mlx5e_close_locked(dev);
4074 err = mlx5e_open_locked(dev);
4076 netdev_err(priv->netdev,
4077 "mlx5e_open_locked failed recovering from a tx_timeout, err(%d).\n",
4081 mutex_unlock(&priv->state_lock);
4085 static void mlx5e_tx_timeout(struct net_device *dev)
4087 struct mlx5e_priv *priv = netdev_priv(dev);
4089 netdev_err(dev, "TX timeout detected\n");
4090 queue_work(priv->wq, &priv->tx_timeout_work);
4093 static int mlx5e_xdp_set(struct net_device *netdev, struct bpf_prog *prog)
4095 struct mlx5e_priv *priv = netdev_priv(netdev);
4096 struct bpf_prog *old_prog;
4098 bool reset, was_opened;
4101 mutex_lock(&priv->state_lock);
4103 if ((netdev->features & NETIF_F_LRO) && prog) {
4104 netdev_warn(netdev, "can't set XDP while LRO is on, disable LRO first\n");
4109 if ((netdev->features & NETIF_F_HW_ESP) && prog) {
4110 netdev_warn(netdev, "can't set XDP with IPSec offload\n");
4115 was_opened = test_bit(MLX5E_STATE_OPENED, &priv->state);
4116 /* no need for full reset when exchanging programs */
4117 reset = (!priv->channels.params.xdp_prog || !prog);
4119 if (was_opened && reset)
4120 mlx5e_close_locked(netdev);
4121 if (was_opened && !reset) {
4122 /* num_channels is invariant here, so we can take the
4123 * batched reference right upfront.
4125 prog = bpf_prog_add(prog, priv->channels.num);
4127 err = PTR_ERR(prog);
4132 /* exchange programs, extra prog reference we got from caller
4133 * as long as we don't fail from this point onwards.
4135 old_prog = xchg(&priv->channels.params.xdp_prog, prog);
4137 bpf_prog_put(old_prog);
4139 if (reset) /* change RQ type according to priv->xdp_prog */
4140 mlx5e_set_rq_type(priv->mdev, &priv->channels.params);
4142 if (was_opened && reset)
4143 mlx5e_open_locked(netdev);
4145 if (!test_bit(MLX5E_STATE_OPENED, &priv->state) || reset)
4148 /* exchanging programs w/o reset, we update ref counts on behalf
4149 * of the channels RQs here.
4151 for (i = 0; i < priv->channels.num; i++) {
4152 struct mlx5e_channel *c = priv->channels.c[i];
4154 clear_bit(MLX5E_RQ_STATE_ENABLED, &c->rq.state);
4155 napi_synchronize(&c->napi);
4156 /* prevent mlx5e_poll_rx_cq from accessing rq->xdp_prog */
4158 old_prog = xchg(&c->rq.xdp_prog, prog);
4160 set_bit(MLX5E_RQ_STATE_ENABLED, &c->rq.state);
4161 /* napi_schedule in case we have missed anything */
4162 napi_schedule(&c->napi);
4165 bpf_prog_put(old_prog);
4169 mutex_unlock(&priv->state_lock);
4173 static u32 mlx5e_xdp_query(struct net_device *dev)
4175 struct mlx5e_priv *priv = netdev_priv(dev);
4176 const struct bpf_prog *xdp_prog;
4179 mutex_lock(&priv->state_lock);
4180 xdp_prog = priv->channels.params.xdp_prog;
4182 prog_id = xdp_prog->aux->id;
4183 mutex_unlock(&priv->state_lock);
4188 static int mlx5e_xdp(struct net_device *dev, struct netdev_bpf *xdp)
4190 switch (xdp->command) {
4191 case XDP_SETUP_PROG:
4192 return mlx5e_xdp_set(dev, xdp->prog);
4193 case XDP_QUERY_PROG:
4194 xdp->prog_id = mlx5e_xdp_query(dev);
4195 xdp->prog_attached = !!xdp->prog_id;
4202 #ifdef CONFIG_NET_POLL_CONTROLLER
4203 /* Fake "interrupt" called by netpoll (eg netconsole) to send skbs without
4204 * reenabling interrupts.
4206 static void mlx5e_netpoll(struct net_device *dev)
4208 struct mlx5e_priv *priv = netdev_priv(dev);
4209 struct mlx5e_channels *chs = &priv->channels;
4213 for (i = 0; i < chs->num; i++)
4214 napi_schedule(&chs->c[i]->napi);
4218 static const struct net_device_ops mlx5e_netdev_ops = {
4219 .ndo_open = mlx5e_open,
4220 .ndo_stop = mlx5e_close,
4221 .ndo_start_xmit = mlx5e_xmit,
4222 .ndo_setup_tc = mlx5e_setup_tc,
4223 .ndo_select_queue = mlx5e_select_queue,
4224 .ndo_get_stats64 = mlx5e_get_stats,
4225 .ndo_set_rx_mode = mlx5e_set_rx_mode,
4226 .ndo_set_mac_address = mlx5e_set_mac,
4227 .ndo_vlan_rx_add_vid = mlx5e_vlan_rx_add_vid,
4228 .ndo_vlan_rx_kill_vid = mlx5e_vlan_rx_kill_vid,
4229 .ndo_set_features = mlx5e_set_features,
4230 .ndo_fix_features = mlx5e_fix_features,
4231 .ndo_change_mtu = mlx5e_change_nic_mtu,
4232 .ndo_do_ioctl = mlx5e_ioctl,
4233 .ndo_set_tx_maxrate = mlx5e_set_tx_maxrate,
4234 .ndo_udp_tunnel_add = mlx5e_add_vxlan_port,
4235 .ndo_udp_tunnel_del = mlx5e_del_vxlan_port,
4236 .ndo_features_check = mlx5e_features_check,
4237 #ifdef CONFIG_RFS_ACCEL
4238 .ndo_rx_flow_steer = mlx5e_rx_flow_steer,
4240 .ndo_tx_timeout = mlx5e_tx_timeout,
4241 .ndo_bpf = mlx5e_xdp,
4242 #ifdef CONFIG_NET_POLL_CONTROLLER
4243 .ndo_poll_controller = mlx5e_netpoll,
4245 #ifdef CONFIG_MLX5_ESWITCH
4246 /* SRIOV E-Switch NDOs */
4247 .ndo_set_vf_mac = mlx5e_set_vf_mac,
4248 .ndo_set_vf_vlan = mlx5e_set_vf_vlan,
4249 .ndo_set_vf_spoofchk = mlx5e_set_vf_spoofchk,
4250 .ndo_set_vf_trust = mlx5e_set_vf_trust,
4251 .ndo_set_vf_rate = mlx5e_set_vf_rate,
4252 .ndo_get_vf_config = mlx5e_get_vf_config,
4253 .ndo_set_vf_link_state = mlx5e_set_vf_link_state,
4254 .ndo_get_vf_stats = mlx5e_get_vf_stats,
4255 .ndo_has_offload_stats = mlx5e_has_offload_stats,
4256 .ndo_get_offload_stats = mlx5e_get_offload_stats,
4260 static int mlx5e_check_required_hca_cap(struct mlx5_core_dev *mdev)
4262 if (MLX5_CAP_GEN(mdev, port_type) != MLX5_CAP_PORT_TYPE_ETH)
4264 if (!MLX5_CAP_GEN(mdev, eth_net_offloads) ||
4265 !MLX5_CAP_GEN(mdev, nic_flow_table) ||
4266 !MLX5_CAP_ETH(mdev, csum_cap) ||
4267 !MLX5_CAP_ETH(mdev, max_lso_cap) ||
4268 !MLX5_CAP_ETH(mdev, vlan_cap) ||
4269 !MLX5_CAP_ETH(mdev, rss_ind_tbl_cap) ||
4270 MLX5_CAP_FLOWTABLE(mdev,
4271 flow_table_properties_nic_receive.max_ft_level)
4273 mlx5_core_warn(mdev,
4274 "Not creating net device, some required device capabilities are missing\n");
4277 if (!MLX5_CAP_ETH(mdev, self_lb_en_modifiable))
4278 mlx5_core_warn(mdev, "Self loop back prevention is not supported\n");
4279 if (!MLX5_CAP_GEN(mdev, cq_moderation))
4280 mlx5_core_warn(mdev, "CQ moderation is not supported\n");
4285 void mlx5e_build_default_indir_rqt(u32 *indirection_rqt, int len,
4290 for (i = 0; i < len; i++)
4291 indirection_rqt[i] = i % num_channels;
4294 static bool slow_pci_heuristic(struct mlx5_core_dev *mdev)
4299 mlx5e_port_max_linkspeed(mdev, &link_speed);
4300 pci_bw = pcie_bandwidth_available(mdev->pdev, NULL, NULL, NULL);
4301 mlx5_core_dbg_once(mdev, "Max link speed = %d, PCI BW = %d\n",
4302 link_speed, pci_bw);
4304 #define MLX5E_SLOW_PCI_RATIO (2)
4306 return link_speed && pci_bw &&
4307 link_speed > MLX5E_SLOW_PCI_RATIO * pci_bw;
4310 static struct net_dim_cq_moder mlx5e_get_def_tx_moderation(u8 cq_period_mode)
4312 struct net_dim_cq_moder moder;
4314 moder.cq_period_mode = cq_period_mode;
4315 moder.pkts = MLX5E_PARAMS_DEFAULT_TX_CQ_MODERATION_PKTS;
4316 moder.usec = MLX5E_PARAMS_DEFAULT_TX_CQ_MODERATION_USEC;
4317 if (cq_period_mode == MLX5_CQ_PERIOD_MODE_START_FROM_CQE)
4318 moder.usec = MLX5E_PARAMS_DEFAULT_TX_CQ_MODERATION_USEC_FROM_CQE;
4323 static struct net_dim_cq_moder mlx5e_get_def_rx_moderation(u8 cq_period_mode)
4325 struct net_dim_cq_moder moder;
4327 moder.cq_period_mode = cq_period_mode;
4328 moder.pkts = MLX5E_PARAMS_DEFAULT_RX_CQ_MODERATION_PKTS;
4329 moder.usec = MLX5E_PARAMS_DEFAULT_RX_CQ_MODERATION_USEC;
4330 if (cq_period_mode == MLX5_CQ_PERIOD_MODE_START_FROM_CQE)
4331 moder.usec = MLX5E_PARAMS_DEFAULT_RX_CQ_MODERATION_USEC_FROM_CQE;
4336 static u8 mlx5_to_net_dim_cq_period_mode(u8 cq_period_mode)
4338 return cq_period_mode == MLX5_CQ_PERIOD_MODE_START_FROM_CQE ?
4339 NET_DIM_CQ_PERIOD_MODE_START_FROM_CQE :
4340 NET_DIM_CQ_PERIOD_MODE_START_FROM_EQE;
4343 void mlx5e_set_tx_cq_mode_params(struct mlx5e_params *params, u8 cq_period_mode)
4345 if (params->tx_dim_enabled) {
4346 u8 dim_period_mode = mlx5_to_net_dim_cq_period_mode(cq_period_mode);
4348 params->tx_cq_moderation = net_dim_get_def_tx_moderation(dim_period_mode);
4350 params->tx_cq_moderation = mlx5e_get_def_tx_moderation(cq_period_mode);
4353 MLX5E_SET_PFLAG(params, MLX5E_PFLAG_TX_CQE_BASED_MODER,
4354 params->tx_cq_moderation.cq_period_mode ==
4355 MLX5_CQ_PERIOD_MODE_START_FROM_CQE);
4358 void mlx5e_set_rx_cq_mode_params(struct mlx5e_params *params, u8 cq_period_mode)
4360 if (params->rx_dim_enabled) {
4361 u8 dim_period_mode = mlx5_to_net_dim_cq_period_mode(cq_period_mode);
4363 params->rx_cq_moderation = net_dim_get_def_rx_moderation(dim_period_mode);
4365 params->rx_cq_moderation = mlx5e_get_def_rx_moderation(cq_period_mode);
4368 MLX5E_SET_PFLAG(params, MLX5E_PFLAG_RX_CQE_BASED_MODER,
4369 params->rx_cq_moderation.cq_period_mode ==
4370 MLX5_CQ_PERIOD_MODE_START_FROM_CQE);
4373 static u32 mlx5e_choose_lro_timeout(struct mlx5_core_dev *mdev, u32 wanted_timeout)
4377 /* The supported periods are organized in ascending order */
4378 for (i = 0; i < MLX5E_LRO_TIMEOUT_ARR_SIZE - 1; i++)
4379 if (MLX5_CAP_ETH(mdev, lro_timer_supported_periods[i]) >= wanted_timeout)
4382 return MLX5_CAP_ETH(mdev, lro_timer_supported_periods[i]);
4385 void mlx5e_build_nic_params(struct mlx5_core_dev *mdev,
4386 struct mlx5e_params *params,
4387 u16 max_channels, u16 mtu)
4389 u8 rx_cq_period_mode;
4391 params->sw_mtu = mtu;
4392 params->hard_mtu = MLX5E_ETH_HARD_MTU;
4393 params->num_channels = max_channels;
4397 params->log_sq_size = is_kdump_kernel() ?
4398 MLX5E_PARAMS_MINIMUM_LOG_SQ_SIZE :
4399 MLX5E_PARAMS_DEFAULT_LOG_SQ_SIZE;
4401 /* set CQE compression */
4402 params->rx_cqe_compress_def = false;
4403 if (MLX5_CAP_GEN(mdev, cqe_compression) &&
4404 MLX5_CAP_GEN(mdev, vport_group_manager))
4405 params->rx_cqe_compress_def = slow_pci_heuristic(mdev);
4407 MLX5E_SET_PFLAG(params, MLX5E_PFLAG_RX_CQE_COMPRESS, params->rx_cqe_compress_def);
4410 /* Prefer Striding RQ, unless any of the following holds:
4411 * - Striding RQ configuration is not possible/supported.
4412 * - Slow PCI heuristic.
4413 * - Legacy RQ would use linear SKB while Striding RQ would use non-linear.
4415 if (!slow_pci_heuristic(mdev) &&
4416 mlx5e_striding_rq_possible(mdev, params) &&
4417 (mlx5e_rx_mpwqe_is_linear_skb(mdev, params) ||
4418 !mlx5e_rx_is_linear_skb(mdev, params)))
4419 MLX5E_SET_PFLAG(params, MLX5E_PFLAG_RX_STRIDING_RQ, true);
4420 mlx5e_set_rq_type(mdev, params);
4421 mlx5e_init_rq_type_params(mdev, params);
4425 /* TODO: && MLX5_CAP_ETH(mdev, lro_cap) */
4426 if (params->rq_wq_type == MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ)
4427 if (!mlx5e_rx_mpwqe_is_linear_skb(mdev, params))
4428 params->lro_en = !slow_pci_heuristic(mdev);
4429 params->lro_timeout = mlx5e_choose_lro_timeout(mdev, MLX5E_DEFAULT_LRO_TIMEOUT);
4431 /* CQ moderation params */
4432 rx_cq_period_mode = MLX5_CAP_GEN(mdev, cq_period_start_from_cqe) ?
4433 MLX5_CQ_PERIOD_MODE_START_FROM_CQE :
4434 MLX5_CQ_PERIOD_MODE_START_FROM_EQE;
4435 params->rx_dim_enabled = MLX5_CAP_GEN(mdev, cq_moderation);
4436 params->tx_dim_enabled = MLX5_CAP_GEN(mdev, cq_moderation);
4437 mlx5e_set_rx_cq_mode_params(params, rx_cq_period_mode);
4438 mlx5e_set_tx_cq_mode_params(params, MLX5_CQ_PERIOD_MODE_START_FROM_EQE);
4441 params->tx_min_inline_mode = mlx5e_params_calculate_tx_min_inline(mdev);
4444 params->rss_hfunc = ETH_RSS_HASH_XOR;
4445 netdev_rss_key_fill(params->toeplitz_hash_key, sizeof(params->toeplitz_hash_key));
4446 mlx5e_build_default_indir_rqt(params->indirection_rqt,
4447 MLX5E_INDIR_RQT_SIZE, max_channels);
4450 static void mlx5e_build_nic_netdev_priv(struct mlx5_core_dev *mdev,
4451 struct net_device *netdev,
4452 const struct mlx5e_profile *profile,
4455 struct mlx5e_priv *priv = netdev_priv(netdev);
4458 priv->netdev = netdev;
4459 priv->profile = profile;
4460 priv->ppriv = ppriv;
4461 priv->msglevel = MLX5E_MSG_LEVEL;
4462 priv->max_opened_tc = 1;
4464 mlx5e_build_nic_params(mdev, &priv->channels.params,
4465 profile->max_nch(mdev), netdev->mtu);
4467 mutex_init(&priv->state_lock);
4469 INIT_WORK(&priv->update_carrier_work, mlx5e_update_carrier_work);
4470 INIT_WORK(&priv->set_rx_mode_work, mlx5e_set_rx_mode_work);
4471 INIT_WORK(&priv->tx_timeout_work, mlx5e_tx_timeout_work);
4472 INIT_DELAYED_WORK(&priv->update_stats_work, mlx5e_update_stats_work);
4474 mlx5e_timestamp_init(priv);
4477 static void mlx5e_set_netdev_dev_addr(struct net_device *netdev)
4479 struct mlx5e_priv *priv = netdev_priv(netdev);
4481 mlx5_query_nic_vport_mac_address(priv->mdev, 0, netdev->dev_addr);
4482 if (is_zero_ether_addr(netdev->dev_addr) &&
4483 !MLX5_CAP_GEN(priv->mdev, vport_group_manager)) {
4484 eth_hw_addr_random(netdev);
4485 mlx5_core_info(priv->mdev, "Assigned random MAC address %pM\n", netdev->dev_addr);
4489 #if IS_ENABLED(CONFIG_MLX5_ESWITCH)
4490 static const struct switchdev_ops mlx5e_switchdev_ops = {
4491 .switchdev_port_attr_get = mlx5e_attr_get,
4495 static void mlx5e_build_nic_netdev(struct net_device *netdev)
4497 struct mlx5e_priv *priv = netdev_priv(netdev);
4498 struct mlx5_core_dev *mdev = priv->mdev;
4502 SET_NETDEV_DEV(netdev, &mdev->pdev->dev);
4504 netdev->netdev_ops = &mlx5e_netdev_ops;
4506 #ifdef CONFIG_MLX5_CORE_EN_DCB
4507 if (MLX5_CAP_GEN(mdev, vport_group_manager) && MLX5_CAP_GEN(mdev, qos))
4508 netdev->dcbnl_ops = &mlx5e_dcbnl_ops;
4511 netdev->watchdog_timeo = 15 * HZ;
4513 netdev->ethtool_ops = &mlx5e_ethtool_ops;
4515 netdev->vlan_features |= NETIF_F_SG;
4516 netdev->vlan_features |= NETIF_F_IP_CSUM;
4517 netdev->vlan_features |= NETIF_F_IPV6_CSUM;
4518 netdev->vlan_features |= NETIF_F_GRO;
4519 netdev->vlan_features |= NETIF_F_TSO;
4520 netdev->vlan_features |= NETIF_F_TSO6;
4521 netdev->vlan_features |= NETIF_F_RXCSUM;
4522 netdev->vlan_features |= NETIF_F_RXHASH;
4524 netdev->hw_enc_features |= NETIF_F_HW_VLAN_CTAG_TX;
4525 netdev->hw_enc_features |= NETIF_F_HW_VLAN_CTAG_RX;
4527 if (!!MLX5_CAP_ETH(mdev, lro_cap) &&
4528 mlx5e_check_fragmented_striding_rq_cap(mdev))
4529 netdev->vlan_features |= NETIF_F_LRO;
4531 netdev->hw_features = netdev->vlan_features;
4532 netdev->hw_features |= NETIF_F_HW_VLAN_CTAG_TX;
4533 netdev->hw_features |= NETIF_F_HW_VLAN_CTAG_RX;
4534 netdev->hw_features |= NETIF_F_HW_VLAN_CTAG_FILTER;
4535 netdev->hw_features |= NETIF_F_HW_VLAN_STAG_TX;
4537 if (mlx5e_vxlan_allowed(mdev) || MLX5_CAP_ETH(mdev, tunnel_stateless_gre)) {
4538 netdev->hw_features |= NETIF_F_GSO_PARTIAL;
4539 netdev->hw_enc_features |= NETIF_F_IP_CSUM;
4540 netdev->hw_enc_features |= NETIF_F_IPV6_CSUM;
4541 netdev->hw_enc_features |= NETIF_F_TSO;
4542 netdev->hw_enc_features |= NETIF_F_TSO6;
4543 netdev->hw_enc_features |= NETIF_F_GSO_PARTIAL;
4546 if (mlx5e_vxlan_allowed(mdev)) {
4547 netdev->hw_features |= NETIF_F_GSO_UDP_TUNNEL |
4548 NETIF_F_GSO_UDP_TUNNEL_CSUM;
4549 netdev->hw_enc_features |= NETIF_F_GSO_UDP_TUNNEL |
4550 NETIF_F_GSO_UDP_TUNNEL_CSUM;
4551 netdev->gso_partial_features = NETIF_F_GSO_UDP_TUNNEL_CSUM;
4554 if (MLX5_CAP_ETH(mdev, tunnel_stateless_gre)) {
4555 netdev->hw_features |= NETIF_F_GSO_GRE |
4556 NETIF_F_GSO_GRE_CSUM;
4557 netdev->hw_enc_features |= NETIF_F_GSO_GRE |
4558 NETIF_F_GSO_GRE_CSUM;
4559 netdev->gso_partial_features |= NETIF_F_GSO_GRE |
4560 NETIF_F_GSO_GRE_CSUM;
4563 mlx5_query_port_fcs(mdev, &fcs_supported, &fcs_enabled);
4566 netdev->hw_features |= NETIF_F_RXALL;
4568 if (MLX5_CAP_ETH(mdev, scatter_fcs))
4569 netdev->hw_features |= NETIF_F_RXFCS;
4571 netdev->features = netdev->hw_features;
4572 if (!priv->channels.params.lro_en)
4573 netdev->features &= ~NETIF_F_LRO;
4576 netdev->features &= ~NETIF_F_RXALL;
4578 if (!priv->channels.params.scatter_fcs_en)
4579 netdev->features &= ~NETIF_F_RXFCS;
4581 #define FT_CAP(f) MLX5_CAP_FLOWTABLE(mdev, flow_table_properties_nic_receive.f)
4582 if (FT_CAP(flow_modify_en) &&
4583 FT_CAP(modify_root) &&
4584 FT_CAP(identified_miss_table_mode) &&
4585 FT_CAP(flow_table_modify)) {
4586 netdev->hw_features |= NETIF_F_HW_TC;
4587 #ifdef CONFIG_RFS_ACCEL
4588 netdev->hw_features |= NETIF_F_NTUPLE;
4592 netdev->features |= NETIF_F_HIGHDMA;
4593 netdev->features |= NETIF_F_HW_VLAN_STAG_FILTER;
4595 netdev->features |= NETIF_F_GSO_UDP_L4;
4596 netdev->hw_features |= NETIF_F_GSO_UDP_L4;
4598 netdev->priv_flags |= IFF_UNICAST_FLT;
4600 mlx5e_set_netdev_dev_addr(netdev);
4602 #if IS_ENABLED(CONFIG_MLX5_ESWITCH)
4603 if (MLX5_VPORT_MANAGER(mdev))
4604 netdev->switchdev_ops = &mlx5e_switchdev_ops;
4607 mlx5e_ipsec_build_netdev(priv);
4608 mlx5e_tls_build_netdev(priv);
4611 static void mlx5e_create_q_counters(struct mlx5e_priv *priv)
4613 struct mlx5_core_dev *mdev = priv->mdev;
4616 err = mlx5_core_alloc_q_counter(mdev, &priv->q_counter);
4618 mlx5_core_warn(mdev, "alloc queue counter failed, %d\n", err);
4619 priv->q_counter = 0;
4622 err = mlx5_core_alloc_q_counter(mdev, &priv->drop_rq_q_counter);
4624 mlx5_core_warn(mdev, "alloc drop RQ counter failed, %d\n", err);
4625 priv->drop_rq_q_counter = 0;
4629 static void mlx5e_destroy_q_counters(struct mlx5e_priv *priv)
4631 if (priv->q_counter)
4632 mlx5_core_dealloc_q_counter(priv->mdev, priv->q_counter);
4634 if (priv->drop_rq_q_counter)
4635 mlx5_core_dealloc_q_counter(priv->mdev, priv->drop_rq_q_counter);
4638 static void mlx5e_nic_init(struct mlx5_core_dev *mdev,
4639 struct net_device *netdev,
4640 const struct mlx5e_profile *profile,
4643 struct mlx5e_priv *priv = netdev_priv(netdev);
4646 mlx5e_build_nic_netdev_priv(mdev, netdev, profile, ppriv);
4647 err = mlx5e_ipsec_init(priv);
4649 mlx5_core_err(mdev, "IPSec initialization failed, %d\n", err);
4650 err = mlx5e_tls_init(priv);
4652 mlx5_core_err(mdev, "TLS initialization failed, %d\n", err);
4653 mlx5e_build_nic_netdev(netdev);
4654 mlx5e_build_tc2txq_maps(priv);
4655 mlx5e_vxlan_init(priv);
4658 static void mlx5e_nic_cleanup(struct mlx5e_priv *priv)
4660 mlx5e_tls_cleanup(priv);
4661 mlx5e_ipsec_cleanup(priv);
4662 mlx5e_vxlan_cleanup(priv);
4665 static int mlx5e_init_nic_rx(struct mlx5e_priv *priv)
4667 struct mlx5_core_dev *mdev = priv->mdev;
4670 err = mlx5e_create_indirect_rqt(priv);
4674 err = mlx5e_create_direct_rqts(priv);
4676 goto err_destroy_indirect_rqts;
4678 err = mlx5e_create_indirect_tirs(priv);
4680 goto err_destroy_direct_rqts;
4682 err = mlx5e_create_direct_tirs(priv);
4684 goto err_destroy_indirect_tirs;
4686 err = mlx5e_create_flow_steering(priv);
4688 mlx5_core_warn(mdev, "create flow steering failed, %d\n", err);
4689 goto err_destroy_direct_tirs;
4692 err = mlx5e_tc_nic_init(priv);
4694 goto err_destroy_flow_steering;
4698 err_destroy_flow_steering:
4699 mlx5e_destroy_flow_steering(priv);
4700 err_destroy_direct_tirs:
4701 mlx5e_destroy_direct_tirs(priv);
4702 err_destroy_indirect_tirs:
4703 mlx5e_destroy_indirect_tirs(priv);
4704 err_destroy_direct_rqts:
4705 mlx5e_destroy_direct_rqts(priv);
4706 err_destroy_indirect_rqts:
4707 mlx5e_destroy_rqt(priv, &priv->indir_rqt);
4711 static void mlx5e_cleanup_nic_rx(struct mlx5e_priv *priv)
4713 mlx5e_tc_nic_cleanup(priv);
4714 mlx5e_destroy_flow_steering(priv);
4715 mlx5e_destroy_direct_tirs(priv);
4716 mlx5e_destroy_indirect_tirs(priv);
4717 mlx5e_destroy_direct_rqts(priv);
4718 mlx5e_destroy_rqt(priv, &priv->indir_rqt);
4721 static int mlx5e_init_nic_tx(struct mlx5e_priv *priv)
4725 err = mlx5e_create_tises(priv);
4727 mlx5_core_warn(priv->mdev, "create tises failed, %d\n", err);
4731 #ifdef CONFIG_MLX5_CORE_EN_DCB
4732 mlx5e_dcbnl_initialize(priv);
4737 static void mlx5e_nic_enable(struct mlx5e_priv *priv)
4739 struct net_device *netdev = priv->netdev;
4740 struct mlx5_core_dev *mdev = priv->mdev;
4743 mlx5e_init_l2_addr(priv);
4745 /* Marking the link as currently not needed by the Driver */
4746 if (!netif_running(netdev))
4747 mlx5_set_port_admin_status(mdev, MLX5_PORT_DOWN);
4749 /* MTU range: 68 - hw-specific max */
4750 netdev->min_mtu = ETH_MIN_MTU;
4751 mlx5_query_port_max_mtu(priv->mdev, &max_mtu, 1);
4752 netdev->max_mtu = MLX5E_HW2SW_MTU(&priv->channels.params, max_mtu);
4753 mlx5e_set_dev_port_mtu(priv);
4755 mlx5_lag_add(mdev, netdev);
4757 mlx5e_enable_async_events(priv);
4759 if (MLX5_VPORT_MANAGER(priv->mdev))
4760 mlx5e_register_vport_reps(priv);
4762 if (netdev->reg_state != NETREG_REGISTERED)
4764 #ifdef CONFIG_MLX5_CORE_EN_DCB
4765 mlx5e_dcbnl_init_app(priv);
4768 queue_work(priv->wq, &priv->set_rx_mode_work);
4771 if (netif_running(netdev))
4773 netif_device_attach(netdev);
4777 static void mlx5e_nic_disable(struct mlx5e_priv *priv)
4779 struct mlx5_core_dev *mdev = priv->mdev;
4781 #ifdef CONFIG_MLX5_CORE_EN_DCB
4782 if (priv->netdev->reg_state == NETREG_REGISTERED)
4783 mlx5e_dcbnl_delete_app(priv);
4787 if (netif_running(priv->netdev))
4788 mlx5e_close(priv->netdev);
4789 netif_device_detach(priv->netdev);
4792 queue_work(priv->wq, &priv->set_rx_mode_work);
4794 if (MLX5_VPORT_MANAGER(priv->mdev))
4795 mlx5e_unregister_vport_reps(priv);
4797 mlx5e_disable_async_events(priv);
4798 mlx5_lag_remove(mdev);
4801 static const struct mlx5e_profile mlx5e_nic_profile = {
4802 .init = mlx5e_nic_init,
4803 .cleanup = mlx5e_nic_cleanup,
4804 .init_rx = mlx5e_init_nic_rx,
4805 .cleanup_rx = mlx5e_cleanup_nic_rx,
4806 .init_tx = mlx5e_init_nic_tx,
4807 .cleanup_tx = mlx5e_cleanup_nic_tx,
4808 .enable = mlx5e_nic_enable,
4809 .disable = mlx5e_nic_disable,
4810 .update_stats = mlx5e_update_ndo_stats,
4811 .max_nch = mlx5e_get_max_num_channels,
4812 .update_carrier = mlx5e_update_carrier,
4813 .rx_handlers.handle_rx_cqe = mlx5e_handle_rx_cqe,
4814 .rx_handlers.handle_rx_cqe_mpwqe = mlx5e_handle_rx_cqe_mpwrq,
4815 .max_tc = MLX5E_MAX_NUM_TC,
4818 /* mlx5e generic netdev management API (move to en_common.c) */
4820 struct net_device *mlx5e_create_netdev(struct mlx5_core_dev *mdev,
4821 const struct mlx5e_profile *profile,
4824 int nch = profile->max_nch(mdev);
4825 struct net_device *netdev;
4826 struct mlx5e_priv *priv;
4828 netdev = alloc_etherdev_mqs(sizeof(struct mlx5e_priv),
4829 nch * profile->max_tc,
4832 mlx5_core_err(mdev, "alloc_etherdev_mqs() failed\n");
4836 #ifdef CONFIG_RFS_ACCEL
4837 netdev->rx_cpu_rmap = mdev->rmap;
4840 profile->init(mdev, netdev, profile, ppriv);
4842 netif_carrier_off(netdev);
4844 priv = netdev_priv(netdev);
4846 priv->wq = create_singlethread_workqueue("mlx5e");
4848 goto err_cleanup_nic;
4853 if (profile->cleanup)
4854 profile->cleanup(priv);
4855 free_netdev(netdev);
4860 int mlx5e_attach_netdev(struct mlx5e_priv *priv)
4862 struct mlx5_core_dev *mdev = priv->mdev;
4863 const struct mlx5e_profile *profile;
4866 profile = priv->profile;
4867 clear_bit(MLX5E_STATE_DESTROYING, &priv->state);
4869 err = profile->init_tx(priv);
4873 mlx5e_create_q_counters(priv);
4875 err = mlx5e_open_drop_rq(priv, &priv->drop_rq);
4877 mlx5_core_err(mdev, "open drop rq failed, %d\n", err);
4878 goto err_destroy_q_counters;
4881 err = profile->init_rx(priv);
4883 goto err_close_drop_rq;
4885 if (profile->enable)
4886 profile->enable(priv);
4891 mlx5e_close_drop_rq(&priv->drop_rq);
4893 err_destroy_q_counters:
4894 mlx5e_destroy_q_counters(priv);
4895 profile->cleanup_tx(priv);
4901 void mlx5e_detach_netdev(struct mlx5e_priv *priv)
4903 const struct mlx5e_profile *profile = priv->profile;
4905 set_bit(MLX5E_STATE_DESTROYING, &priv->state);
4907 if (profile->disable)
4908 profile->disable(priv);
4909 flush_workqueue(priv->wq);
4911 profile->cleanup_rx(priv);
4912 mlx5e_close_drop_rq(&priv->drop_rq);
4913 mlx5e_destroy_q_counters(priv);
4914 profile->cleanup_tx(priv);
4915 cancel_delayed_work_sync(&priv->update_stats_work);
4918 void mlx5e_destroy_netdev(struct mlx5e_priv *priv)
4920 const struct mlx5e_profile *profile = priv->profile;
4921 struct net_device *netdev = priv->netdev;
4923 destroy_workqueue(priv->wq);
4924 if (profile->cleanup)
4925 profile->cleanup(priv);
4926 free_netdev(netdev);
4929 /* mlx5e_attach and mlx5e_detach scope should be only creating/destroying
4930 * hardware contexts and to connect it to the current netdev.
4932 static int mlx5e_attach(struct mlx5_core_dev *mdev, void *vpriv)
4934 struct mlx5e_priv *priv = vpriv;
4935 struct net_device *netdev = priv->netdev;
4938 if (netif_device_present(netdev))
4941 err = mlx5e_create_mdev_resources(mdev);
4945 err = mlx5e_attach_netdev(priv);
4947 mlx5e_destroy_mdev_resources(mdev);
4954 static void mlx5e_detach(struct mlx5_core_dev *mdev, void *vpriv)
4956 struct mlx5e_priv *priv = vpriv;
4957 struct net_device *netdev = priv->netdev;
4959 if (!netif_device_present(netdev))
4962 mlx5e_detach_netdev(priv);
4963 mlx5e_destroy_mdev_resources(mdev);
4966 static void *mlx5e_add(struct mlx5_core_dev *mdev)
4968 struct net_device *netdev;
4973 err = mlx5e_check_required_hca_cap(mdev);
4977 #ifdef CONFIG_MLX5_ESWITCH
4978 if (MLX5_VPORT_MANAGER(mdev)) {
4979 rpriv = mlx5e_alloc_nic_rep_priv(mdev);
4981 mlx5_core_warn(mdev, "Failed to alloc NIC rep priv data\n");
4987 netdev = mlx5e_create_netdev(mdev, &mlx5e_nic_profile, rpriv);
4989 mlx5_core_err(mdev, "mlx5e_create_netdev failed\n");
4990 goto err_free_rpriv;
4993 priv = netdev_priv(netdev);
4995 err = mlx5e_attach(mdev, priv);
4997 mlx5_core_err(mdev, "mlx5e_attach failed, %d\n", err);
4998 goto err_destroy_netdev;
5001 err = register_netdev(netdev);
5003 mlx5_core_err(mdev, "register_netdev failed, %d\n", err);
5007 #ifdef CONFIG_MLX5_CORE_EN_DCB
5008 mlx5e_dcbnl_init_app(priv);
5013 mlx5e_detach(mdev, priv);
5015 mlx5e_destroy_netdev(priv);
5021 static void mlx5e_remove(struct mlx5_core_dev *mdev, void *vpriv)
5023 struct mlx5e_priv *priv = vpriv;
5024 void *ppriv = priv->ppriv;
5026 #ifdef CONFIG_MLX5_CORE_EN_DCB
5027 mlx5e_dcbnl_delete_app(priv);
5029 unregister_netdev(priv->netdev);
5030 mlx5e_detach(mdev, vpriv);
5031 mlx5e_destroy_netdev(priv);
5035 static void *mlx5e_get_netdev(void *vpriv)
5037 struct mlx5e_priv *priv = vpriv;
5039 return priv->netdev;
5042 static struct mlx5_interface mlx5e_interface = {
5044 .remove = mlx5e_remove,
5045 .attach = mlx5e_attach,
5046 .detach = mlx5e_detach,
5047 .event = mlx5e_async_event,
5048 .protocol = MLX5_INTERFACE_PROTOCOL_ETH,
5049 .get_dev = mlx5e_get_netdev,
5052 void mlx5e_init(void)
5054 mlx5e_ipsec_build_inverse_table();
5055 mlx5e_build_ptys2ethtool_map();
5056 mlx5_register_interface(&mlx5e_interface);
5059 void mlx5e_cleanup(void)
5061 mlx5_unregister_interface(&mlx5e_interface);