2 * Copyright (c) 2015-2016, Mellanox Technologies. All rights reserved.
4 * This software is available to you under a choice of one of two
5 * licenses. You may choose to be licensed under the terms of the GNU
6 * General Public License (GPL) Version 2, available from the file
7 * COPYING in the main directory of this source tree, or the
8 * OpenIB.org BSD license below:
10 * Redistribution and use in source and binary forms, with or
11 * without modification, are permitted provided that the following
14 * - Redistributions of source code must retain the above
15 * copyright notice, this list of conditions and the following
18 * - Redistributions in binary form must reproduce the above
19 * copyright notice, this list of conditions and the following
20 * disclaimer in the documentation and/or other materials
21 * provided with the distribution.
23 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
24 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
25 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
26 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
27 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
28 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
29 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
33 #include <net/tc_act/tc_gact.h>
34 #include <net/pkt_cls.h>
35 #include <linux/mlx5/fs.h>
36 #include <net/vxlan.h>
37 #include <net/geneve.h>
38 #include <linux/bpf.h>
39 #include <linux/if_bridge.h>
40 #include <net/page_pool.h>
41 #include <net/xdp_sock_drv.h>
47 #include "en_accel/ipsec.h"
48 #include "en_accel/en_accel.h"
49 #include "en_accel/tls.h"
50 #include "accel/ipsec.h"
51 #include "accel/tls.h"
52 #include "lib/vxlan.h"
53 #include "lib/clock.h"
57 #include "en/monitor_stats.h"
58 #include "en/health.h"
59 #include "en/params.h"
60 #include "en/xsk/pool.h"
61 #include "en/xsk/setup.h"
62 #include "en/xsk/rx.h"
63 #include "en/xsk/tx.h"
64 #include "en/hv_vhca_stats.h"
65 #include "en/devlink.h"
70 #include "fpga/ipsec.h"
72 bool mlx5e_check_fragmented_striding_rq_cap(struct mlx5_core_dev *mdev)
74 bool striding_rq_umr = MLX5_CAP_GEN(mdev, striding_rq) &&
75 MLX5_CAP_GEN(mdev, umr_ptr_rlky) &&
76 MLX5_CAP_ETH(mdev, reg_umr_sq);
77 u16 max_wqe_sz_cap = MLX5_CAP_GEN(mdev, max_wqe_sz_sq);
78 bool inline_umr = MLX5E_UMR_WQE_INLINE_SZ <= max_wqe_sz_cap;
83 mlx5_core_warn(mdev, "Cannot support Striding RQ: UMR WQE size (%d) exceeds maximum supported (%d).\n",
84 (int)MLX5E_UMR_WQE_INLINE_SZ, max_wqe_sz_cap);
90 void mlx5e_update_carrier(struct mlx5e_priv *priv)
92 struct mlx5_core_dev *mdev = priv->mdev;
96 port_state = mlx5_query_vport_state(mdev,
97 MLX5_VPORT_STATE_OP_MOD_VNIC_VPORT,
100 up = port_state == VPORT_STATE_UP;
101 if (up == netif_carrier_ok(priv->netdev))
102 netif_carrier_event(priv->netdev);
104 netdev_info(priv->netdev, "Link up\n");
105 netif_carrier_on(priv->netdev);
107 netdev_info(priv->netdev, "Link down\n");
108 netif_carrier_off(priv->netdev);
112 static void mlx5e_update_carrier_work(struct work_struct *work)
114 struct mlx5e_priv *priv = container_of(work, struct mlx5e_priv,
115 update_carrier_work);
117 mutex_lock(&priv->state_lock);
118 if (test_bit(MLX5E_STATE_OPENED, &priv->state))
119 if (priv->profile->update_carrier)
120 priv->profile->update_carrier(priv);
121 mutex_unlock(&priv->state_lock);
124 static void mlx5e_update_stats_work(struct work_struct *work)
126 struct mlx5e_priv *priv = container_of(work, struct mlx5e_priv,
129 mutex_lock(&priv->state_lock);
130 priv->profile->update_stats(priv);
131 mutex_unlock(&priv->state_lock);
134 void mlx5e_queue_update_stats(struct mlx5e_priv *priv)
136 if (!priv->profile->update_stats)
139 if (unlikely(test_bit(MLX5E_STATE_DESTROYING, &priv->state)))
142 queue_work(priv->wq, &priv->update_stats_work);
145 static int async_event(struct notifier_block *nb, unsigned long event, void *data)
147 struct mlx5e_priv *priv = container_of(nb, struct mlx5e_priv, events_nb);
148 struct mlx5_eqe *eqe = data;
150 if (event != MLX5_EVENT_TYPE_PORT_CHANGE)
153 switch (eqe->sub_type) {
154 case MLX5_PORT_CHANGE_SUBTYPE_DOWN:
155 case MLX5_PORT_CHANGE_SUBTYPE_ACTIVE:
156 queue_work(priv->wq, &priv->update_carrier_work);
165 static void mlx5e_enable_async_events(struct mlx5e_priv *priv)
167 priv->events_nb.notifier_call = async_event;
168 mlx5_notifier_register(priv->mdev, &priv->events_nb);
171 static void mlx5e_disable_async_events(struct mlx5e_priv *priv)
173 mlx5_notifier_unregister(priv->mdev, &priv->events_nb);
176 static int blocking_event(struct notifier_block *nb, unsigned long event, void *data)
178 struct mlx5e_priv *priv = container_of(nb, struct mlx5e_priv, blocking_events_nb);
182 case MLX5_DRIVER_EVENT_TYPE_TRAP:
183 err = mlx5e_handle_trap_event(priv, data);
186 netdev_warn(priv->netdev, "Sync event: Unknown event %ld\n", event);
192 static void mlx5e_enable_blocking_events(struct mlx5e_priv *priv)
194 priv->blocking_events_nb.notifier_call = blocking_event;
195 mlx5_blocking_notifier_register(priv->mdev, &priv->blocking_events_nb);
198 static void mlx5e_disable_blocking_events(struct mlx5e_priv *priv)
200 mlx5_blocking_notifier_unregister(priv->mdev, &priv->blocking_events_nb);
203 static inline void mlx5e_build_umr_wqe(struct mlx5e_rq *rq,
204 struct mlx5e_icosq *sq,
205 struct mlx5e_umr_wqe *wqe)
207 struct mlx5_wqe_ctrl_seg *cseg = &wqe->ctrl;
208 struct mlx5_wqe_umr_ctrl_seg *ucseg = &wqe->uctrl;
209 u8 ds_cnt = DIV_ROUND_UP(MLX5E_UMR_WQE_INLINE_SZ, MLX5_SEND_WQE_DS);
211 cseg->qpn_ds = cpu_to_be32((sq->sqn << MLX5_WQE_CTRL_QPN_SHIFT) |
213 cseg->umr_mkey = rq->mkey_be;
215 ucseg->flags = MLX5_UMR_TRANSLATION_OFFSET_EN | MLX5_UMR_INLINE;
216 ucseg->xlt_octowords =
217 cpu_to_be16(MLX5_MTT_OCTW(MLX5_MPWRQ_PAGES_PER_WQE));
218 ucseg->mkey_mask = cpu_to_be64(MLX5_MKEY_MASK_FREE);
221 static int mlx5e_rq_shampo_hd_alloc(struct mlx5e_rq *rq, int node)
223 rq->mpwqe.shampo = kvzalloc_node(sizeof(*rq->mpwqe.shampo),
225 if (!rq->mpwqe.shampo)
230 static void mlx5e_rq_shampo_hd_free(struct mlx5e_rq *rq)
232 kvfree(rq->mpwqe.shampo);
235 static int mlx5e_rq_shampo_hd_info_alloc(struct mlx5e_rq *rq, int node)
237 struct mlx5e_shampo_hd *shampo = rq->mpwqe.shampo;
239 shampo->bitmap = bitmap_zalloc_node(shampo->hd_per_wq, GFP_KERNEL,
244 shampo->info = kvzalloc_node(array_size(shampo->hd_per_wq,
245 sizeof(*shampo->info)),
248 kvfree(shampo->bitmap);
254 static void mlx5e_rq_shampo_hd_info_free(struct mlx5e_rq *rq)
256 kvfree(rq->mpwqe.shampo->bitmap);
257 kvfree(rq->mpwqe.shampo->info);
260 static int mlx5e_rq_alloc_mpwqe_info(struct mlx5e_rq *rq, int node)
262 int wq_sz = mlx5_wq_ll_get_size(&rq->mpwqe.wq);
264 rq->mpwqe.info = kvzalloc_node(array_size(wq_sz,
265 sizeof(*rq->mpwqe.info)),
270 mlx5e_build_umr_wqe(rq, rq->icosq, &rq->mpwqe.umr_wqe);
275 static int mlx5e_create_umr_mtt_mkey(struct mlx5_core_dev *mdev,
276 u64 npages, u8 page_shift, u32 *umr_mkey,
277 dma_addr_t filler_addr)
279 struct mlx5_mtt *mtt;
286 inlen = MLX5_ST_SZ_BYTES(create_mkey_in) + sizeof(*mtt) * npages;
288 in = kvzalloc(inlen, GFP_KERNEL);
292 mkc = MLX5_ADDR_OF(create_mkey_in, in, memory_key_mkey_entry);
294 MLX5_SET(mkc, mkc, free, 1);
295 MLX5_SET(mkc, mkc, umr_en, 1);
296 MLX5_SET(mkc, mkc, lw, 1);
297 MLX5_SET(mkc, mkc, lr, 1);
298 MLX5_SET(mkc, mkc, access_mode_1_0, MLX5_MKC_ACCESS_MODE_MTT);
299 mlx5e_mkey_set_relaxed_ordering(mdev, mkc);
300 MLX5_SET(mkc, mkc, qpn, 0xffffff);
301 MLX5_SET(mkc, mkc, pd, mdev->mlx5e_res.hw_objs.pdn);
302 MLX5_SET64(mkc, mkc, len, npages << page_shift);
303 MLX5_SET(mkc, mkc, translations_octword_size,
304 MLX5_MTT_OCTW(npages));
305 MLX5_SET(mkc, mkc, log_page_size, page_shift);
306 MLX5_SET(create_mkey_in, in, translations_octword_actual_size,
307 MLX5_MTT_OCTW(npages));
309 /* Initialize the mkey with all MTTs pointing to a default
310 * page (filler_addr). When the channels are activated, UMR
311 * WQEs will redirect the RX WQEs to the actual memory from
312 * the RQ's pool, while the gaps (wqe_overflow) remain mapped
313 * to the default page.
315 mtt = MLX5_ADDR_OF(create_mkey_in, in, klm_pas_mtt);
316 for (i = 0 ; i < npages ; i++)
317 mtt[i].ptag = cpu_to_be64(filler_addr);
319 err = mlx5_core_create_mkey(mdev, umr_mkey, in, inlen);
325 static int mlx5e_create_umr_klm_mkey(struct mlx5_core_dev *mdev,
334 inlen = MLX5_ST_SZ_BYTES(create_mkey_in);
336 in = kvzalloc(inlen, GFP_KERNEL);
340 mkc = MLX5_ADDR_OF(create_mkey_in, in, memory_key_mkey_entry);
342 MLX5_SET(mkc, mkc, free, 1);
343 MLX5_SET(mkc, mkc, umr_en, 1);
344 MLX5_SET(mkc, mkc, lw, 1);
345 MLX5_SET(mkc, mkc, lr, 1);
346 MLX5_SET(mkc, mkc, access_mode_1_0, MLX5_MKC_ACCESS_MODE_KLMS);
347 mlx5e_mkey_set_relaxed_ordering(mdev, mkc);
348 MLX5_SET(mkc, mkc, qpn, 0xffffff);
349 MLX5_SET(mkc, mkc, pd, mdev->mlx5e_res.hw_objs.pdn);
350 MLX5_SET(mkc, mkc, translations_octword_size, nentries);
351 MLX5_SET(mkc, mkc, length64, 1);
352 err = mlx5_core_create_mkey(mdev, umr_mkey, in, inlen);
358 static int mlx5e_create_rq_umr_mkey(struct mlx5_core_dev *mdev, struct mlx5e_rq *rq)
360 u64 num_mtts = MLX5E_REQUIRED_MTTS(mlx5_wq_ll_get_size(&rq->mpwqe.wq));
362 return mlx5e_create_umr_mtt_mkey(mdev, num_mtts, PAGE_SHIFT,
363 &rq->umr_mkey, rq->wqe_overflow.addr);
366 static int mlx5e_create_rq_hd_umr_mkey(struct mlx5_core_dev *mdev,
369 u32 max_klm_size = BIT(MLX5_CAP_GEN(mdev, log_max_klm_list_size));
371 if (max_klm_size < rq->mpwqe.shampo->hd_per_wq) {
372 mlx5_core_err(mdev, "max klm list size 0x%x is smaller than shampo header buffer list size 0x%x\n",
373 max_klm_size, rq->mpwqe.shampo->hd_per_wq);
376 return mlx5e_create_umr_klm_mkey(mdev, rq->mpwqe.shampo->hd_per_wq,
377 &rq->mpwqe.shampo->mkey);
380 static u64 mlx5e_get_mpwqe_offset(u16 wqe_ix)
382 return MLX5E_REQUIRED_MTTS(wqe_ix) << PAGE_SHIFT;
385 static void mlx5e_init_frags_partition(struct mlx5e_rq *rq)
387 struct mlx5e_wqe_frag_info next_frag = {};
388 struct mlx5e_wqe_frag_info *prev = NULL;
391 next_frag.di = &rq->wqe.di[0];
393 for (i = 0; i < mlx5_wq_cyc_get_size(&rq->wqe.wq); i++) {
394 struct mlx5e_rq_frag_info *frag_info = &rq->wqe.info.arr[0];
395 struct mlx5e_wqe_frag_info *frag =
396 &rq->wqe.frags[i << rq->wqe.info.log_num_frags];
399 for (f = 0; f < rq->wqe.info.num_frags; f++, frag++) {
400 if (next_frag.offset + frag_info[f].frag_stride > PAGE_SIZE) {
402 next_frag.offset = 0;
404 prev->last_in_page = true;
409 next_frag.offset += frag_info[f].frag_stride;
415 prev->last_in_page = true;
418 int mlx5e_init_di_list(struct mlx5e_rq *rq, int wq_sz, int node)
420 int len = wq_sz << rq->wqe.info.log_num_frags;
422 rq->wqe.di = kvzalloc_node(array_size(len, sizeof(*rq->wqe.di)), GFP_KERNEL, node);
426 mlx5e_init_frags_partition(rq);
431 void mlx5e_free_di_list(struct mlx5e_rq *rq)
436 static void mlx5e_rq_err_cqe_work(struct work_struct *recover_work)
438 struct mlx5e_rq *rq = container_of(recover_work, struct mlx5e_rq, recover_work);
440 mlx5e_reporter_rq_cqe_err(rq);
443 static int mlx5e_alloc_mpwqe_rq_drop_page(struct mlx5e_rq *rq)
445 rq->wqe_overflow.page = alloc_page(GFP_KERNEL);
446 if (!rq->wqe_overflow.page)
449 rq->wqe_overflow.addr = dma_map_page(rq->pdev, rq->wqe_overflow.page, 0,
450 PAGE_SIZE, rq->buff.map_dir);
451 if (dma_mapping_error(rq->pdev, rq->wqe_overflow.addr)) {
452 __free_page(rq->wqe_overflow.page);
458 static void mlx5e_free_mpwqe_rq_drop_page(struct mlx5e_rq *rq)
460 dma_unmap_page(rq->pdev, rq->wqe_overflow.addr, PAGE_SIZE,
462 __free_page(rq->wqe_overflow.page);
465 static int mlx5e_init_rxq_rq(struct mlx5e_channel *c, struct mlx5e_params *params,
468 struct mlx5_core_dev *mdev = c->mdev;
471 rq->wq_type = params->rq_wq_type;
473 rq->netdev = c->netdev;
475 rq->tstamp = c->tstamp;
476 rq->clock = &mdev->clock;
477 rq->icosq = &c->icosq;
480 rq->hw_mtu = MLX5E_SW2HW_MTU(params, params->sw_mtu);
481 rq->xdpsq = &c->rq_xdpsq;
482 rq->stats = &c->priv->channel_stats[c->ix].rq;
483 rq->ptp_cyc2time = mlx5_rq_ts_translator(mdev);
484 err = mlx5e_rq_set_handlers(rq, params, NULL);
488 return xdp_rxq_info_reg(&rq->xdp_rxq, rq->netdev, rq->ix, 0);
491 static int mlx5_rq_shampo_alloc(struct mlx5_core_dev *mdev,
492 struct mlx5e_params *params,
493 struct mlx5e_rq_param *rqp,
498 void *wqc = MLX5_ADDR_OF(rqc, rqp->rqc, wq);
502 if (!test_bit(MLX5E_RQ_STATE_SHAMPO, &rq->state))
504 err = mlx5e_rq_shampo_hd_alloc(rq, node);
507 rq->mpwqe.shampo->hd_per_wq =
508 mlx5e_shampo_hd_per_wq(mdev, params, rqp);
509 err = mlx5e_create_rq_hd_umr_mkey(mdev, rq);
512 err = mlx5e_rq_shampo_hd_info_alloc(rq, node);
514 goto err_shampo_info;
515 rq->hw_gro_data = kvzalloc_node(sizeof(*rq->hw_gro_data), GFP_KERNEL, node);
516 if (!rq->hw_gro_data) {
518 goto err_hw_gro_data;
520 rq->mpwqe.shampo->key =
521 cpu_to_be32(rq->mpwqe.shampo->mkey);
522 rq->mpwqe.shampo->hd_per_wqe =
523 mlx5e_shampo_hd_per_wqe(mdev, params, rqp);
524 wq_size = BIT(MLX5_GET(wq, wqc, log_wq_sz));
525 *pool_size += (rq->mpwqe.shampo->hd_per_wqe * wq_size) /
526 MLX5E_SHAMPO_WQ_HEADER_PER_PAGE;
530 mlx5e_rq_shampo_hd_info_free(rq);
532 mlx5_core_destroy_mkey(mdev, rq->mpwqe.shampo->mkey);
534 mlx5e_rq_shampo_hd_free(rq);
539 static void mlx5e_rq_free_shampo(struct mlx5e_rq *rq)
541 if (!test_bit(MLX5E_RQ_STATE_SHAMPO, &rq->state))
544 kvfree(rq->hw_gro_data);
545 mlx5e_rq_shampo_hd_info_free(rq);
546 mlx5_core_destroy_mkey(rq->mdev, rq->mpwqe.shampo->mkey);
547 mlx5e_rq_shampo_hd_free(rq);
550 static int mlx5e_alloc_rq(struct mlx5e_params *params,
551 struct mlx5e_xsk_param *xsk,
552 struct mlx5e_rq_param *rqp,
553 int node, struct mlx5e_rq *rq)
555 struct page_pool_params pp_params = { 0 };
556 struct mlx5_core_dev *mdev = rq->mdev;
557 void *rqc = rqp->rqc;
558 void *rqc_wq = MLX5_ADDR_OF(rqc, rqc, wq);
564 rqp->wq.db_numa_node = node;
565 INIT_WORK(&rq->recover_work, mlx5e_rq_err_cqe_work);
567 if (params->xdp_prog)
568 bpf_prog_inc(params->xdp_prog);
569 RCU_INIT_POINTER(rq->xdp_prog, params->xdp_prog);
571 rq->buff.map_dir = params->xdp_prog ? DMA_BIDIRECTIONAL : DMA_FROM_DEVICE;
572 rq->buff.headroom = mlx5e_get_rq_headroom(mdev, params, xsk);
573 pool_size = 1 << params->log_rq_mtu_frames;
575 switch (rq->wq_type) {
576 case MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ:
577 err = mlx5_wq_ll_create(mdev, &rqp->wq, rqc_wq, &rq->mpwqe.wq,
580 goto err_rq_xdp_prog;
582 err = mlx5e_alloc_mpwqe_rq_drop_page(rq);
584 goto err_rq_wq_destroy;
586 rq->mpwqe.wq.db = &rq->mpwqe.wq.db[MLX5_RCV_DBR];
588 wq_sz = mlx5_wq_ll_get_size(&rq->mpwqe.wq);
590 pool_size = MLX5_MPWRQ_PAGES_PER_WQE <<
591 mlx5e_mpwqe_get_log_rq_size(params, xsk);
593 rq->mpwqe.log_stride_sz = mlx5e_mpwqe_get_log_stride_size(mdev, params, xsk);
594 rq->mpwqe.num_strides =
595 BIT(mlx5e_mpwqe_get_log_num_strides(mdev, params, xsk));
597 rq->buff.frame0_sz = (1 << rq->mpwqe.log_stride_sz);
599 err = mlx5e_create_rq_umr_mkey(mdev, rq);
601 goto err_rq_drop_page;
602 rq->mkey_be = cpu_to_be32(rq->umr_mkey);
604 err = mlx5e_rq_alloc_mpwqe_info(rq, node);
608 err = mlx5_rq_shampo_alloc(mdev, params, rqp, rq, &pool_size, node);
610 goto err_free_by_rq_type;
613 default: /* MLX5_WQ_TYPE_CYCLIC */
614 err = mlx5_wq_cyc_create(mdev, &rqp->wq, rqc_wq, &rq->wqe.wq,
617 goto err_rq_xdp_prog;
619 rq->wqe.wq.db = &rq->wqe.wq.db[MLX5_RCV_DBR];
621 wq_sz = mlx5_wq_cyc_get_size(&rq->wqe.wq);
623 rq->wqe.info = rqp->frags_info;
624 rq->buff.frame0_sz = rq->wqe.info.arr[0].frag_stride;
627 kvzalloc_node(array_size(sizeof(*rq->wqe.frags),
628 (wq_sz << rq->wqe.info.log_num_frags)),
630 if (!rq->wqe.frags) {
632 goto err_rq_wq_destroy;
635 err = mlx5e_init_di_list(rq, wq_sz, node);
639 rq->mkey_be = cpu_to_be32(mdev->mlx5e_res.hw_objs.mkey);
643 err = xdp_rxq_info_reg_mem_model(&rq->xdp_rxq,
644 MEM_TYPE_XSK_BUFF_POOL, NULL);
645 xsk_pool_set_rxq_info(rq->xsk_pool, &rq->xdp_rxq);
647 /* Create a page_pool and register it with rxq */
649 pp_params.flags = 0; /* No-internal DMA mapping in page_pool */
650 pp_params.pool_size = pool_size;
651 pp_params.nid = node;
652 pp_params.dev = rq->pdev;
653 pp_params.dma_dir = rq->buff.map_dir;
655 /* page_pool can be used even when there is no rq->xdp_prog,
656 * given page_pool does not handle DMA mapping there is no
657 * required state to clear. And page_pool gracefully handle
660 rq->page_pool = page_pool_create(&pp_params);
661 if (IS_ERR(rq->page_pool)) {
662 err = PTR_ERR(rq->page_pool);
663 rq->page_pool = NULL;
664 goto err_free_shampo;
666 if (xdp_rxq_info_is_reg(&rq->xdp_rxq))
667 err = xdp_rxq_info_reg_mem_model(&rq->xdp_rxq,
668 MEM_TYPE_PAGE_POOL, rq->page_pool);
671 goto err_free_shampo;
673 for (i = 0; i < wq_sz; i++) {
674 if (rq->wq_type == MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ) {
675 struct mlx5e_rx_wqe_ll *wqe =
676 mlx5_wq_ll_get_wqe(&rq->mpwqe.wq, i);
678 rq->mpwqe.num_strides << rq->mpwqe.log_stride_sz;
679 u64 dma_offset = mlx5e_get_mpwqe_offset(i);
680 u16 headroom = test_bit(MLX5E_RQ_STATE_SHAMPO, &rq->state) ?
681 0 : rq->buff.headroom;
683 wqe->data[0].addr = cpu_to_be64(dma_offset + headroom);
684 wqe->data[0].byte_count = cpu_to_be32(byte_count);
685 wqe->data[0].lkey = rq->mkey_be;
687 struct mlx5e_rx_wqe_cyc *wqe =
688 mlx5_wq_cyc_get_wqe(&rq->wqe.wq, i);
691 for (f = 0; f < rq->wqe.info.num_frags; f++) {
692 u32 frag_size = rq->wqe.info.arr[f].frag_size |
693 MLX5_HW_START_PADDING;
695 wqe->data[f].byte_count = cpu_to_be32(frag_size);
696 wqe->data[f].lkey = rq->mkey_be;
698 /* check if num_frags is not a pow of two */
699 if (rq->wqe.info.num_frags < (1 << rq->wqe.info.log_num_frags)) {
700 wqe->data[f].byte_count = 0;
701 wqe->data[f].lkey = cpu_to_be32(MLX5_INVALID_LKEY);
702 wqe->data[f].addr = 0;
707 INIT_WORK(&rq->dim.work, mlx5e_rx_dim_work);
709 switch (params->rx_cq_moderation.cq_period_mode) {
710 case MLX5_CQ_PERIOD_MODE_START_FROM_CQE:
711 rq->dim.mode = DIM_CQ_PERIOD_MODE_START_FROM_CQE;
713 case MLX5_CQ_PERIOD_MODE_START_FROM_EQE:
715 rq->dim.mode = DIM_CQ_PERIOD_MODE_START_FROM_EQE;
718 rq->page_cache.head = 0;
719 rq->page_cache.tail = 0;
724 mlx5e_rq_free_shampo(rq);
726 switch (rq->wq_type) {
727 case MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ:
728 kvfree(rq->mpwqe.info);
730 mlx5_core_destroy_mkey(mdev, rq->umr_mkey);
732 mlx5e_free_mpwqe_rq_drop_page(rq);
734 default: /* MLX5_WQ_TYPE_CYCLIC */
735 mlx5e_free_di_list(rq);
737 kvfree(rq->wqe.frags);
740 mlx5_wq_destroy(&rq->wq_ctrl);
742 if (params->xdp_prog)
743 bpf_prog_put(params->xdp_prog);
748 static void mlx5e_free_rq(struct mlx5e_rq *rq)
750 struct bpf_prog *old_prog;
753 if (xdp_rxq_info_is_reg(&rq->xdp_rxq)) {
754 old_prog = rcu_dereference_protected(rq->xdp_prog,
755 lockdep_is_held(&rq->priv->state_lock));
757 bpf_prog_put(old_prog);
760 switch (rq->wq_type) {
761 case MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ:
762 kvfree(rq->mpwqe.info);
763 mlx5_core_destroy_mkey(rq->mdev, rq->umr_mkey);
764 mlx5e_free_mpwqe_rq_drop_page(rq);
765 mlx5e_rq_free_shampo(rq);
767 default: /* MLX5_WQ_TYPE_CYCLIC */
768 kvfree(rq->wqe.frags);
769 mlx5e_free_di_list(rq);
772 for (i = rq->page_cache.head; i != rq->page_cache.tail;
773 i = (i + 1) & (MLX5E_CACHE_SIZE - 1)) {
774 struct mlx5e_dma_info *dma_info = &rq->page_cache.page_cache[i];
776 /* With AF_XDP, page_cache is not used, so this loop is not
777 * entered, and it's safe to call mlx5e_page_release_dynamic
780 mlx5e_page_release_dynamic(rq, dma_info, false);
783 xdp_rxq_info_unreg(&rq->xdp_rxq);
784 page_pool_destroy(rq->page_pool);
785 mlx5_wq_destroy(&rq->wq_ctrl);
788 int mlx5e_create_rq(struct mlx5e_rq *rq, struct mlx5e_rq_param *param)
790 struct mlx5_core_dev *mdev = rq->mdev;
798 inlen = MLX5_ST_SZ_BYTES(create_rq_in) +
799 sizeof(u64) * rq->wq_ctrl.buf.npages;
800 in = kvzalloc(inlen, GFP_KERNEL);
804 ts_format = mlx5_is_real_time_rq(mdev) ?
805 MLX5_TIMESTAMP_FORMAT_REAL_TIME :
806 MLX5_TIMESTAMP_FORMAT_FREE_RUNNING;
807 rqc = MLX5_ADDR_OF(create_rq_in, in, ctx);
808 wq = MLX5_ADDR_OF(rqc, rqc, wq);
810 memcpy(rqc, param->rqc, sizeof(param->rqc));
812 MLX5_SET(rqc, rqc, cqn, rq->cq.mcq.cqn);
813 MLX5_SET(rqc, rqc, state, MLX5_RQC_STATE_RST);
814 MLX5_SET(rqc, rqc, ts_format, ts_format);
815 MLX5_SET(wq, wq, log_wq_pg_sz, rq->wq_ctrl.buf.page_shift -
816 MLX5_ADAPTER_PAGE_SHIFT);
817 MLX5_SET64(wq, wq, dbr_addr, rq->wq_ctrl.db.dma);
819 if (test_bit(MLX5E_RQ_STATE_SHAMPO, &rq->state)) {
820 MLX5_SET(wq, wq, log_headers_buffer_entry_num,
821 order_base_2(rq->mpwqe.shampo->hd_per_wq));
822 MLX5_SET(wq, wq, headers_mkey, rq->mpwqe.shampo->mkey);
825 mlx5_fill_page_frag_array(&rq->wq_ctrl.buf,
826 (__be64 *)MLX5_ADDR_OF(wq, wq, pas));
828 err = mlx5_core_create_rq(mdev, in, inlen, &rq->rqn);
835 int mlx5e_modify_rq_state(struct mlx5e_rq *rq, int curr_state, int next_state)
837 struct mlx5_core_dev *mdev = rq->mdev;
844 inlen = MLX5_ST_SZ_BYTES(modify_rq_in);
845 in = kvzalloc(inlen, GFP_KERNEL);
849 if (curr_state == MLX5_RQC_STATE_RST && next_state == MLX5_RQC_STATE_RDY)
850 mlx5e_rqwq_reset(rq);
852 rqc = MLX5_ADDR_OF(modify_rq_in, in, ctx);
854 MLX5_SET(modify_rq_in, in, rq_state, curr_state);
855 MLX5_SET(rqc, rqc, state, next_state);
857 err = mlx5_core_modify_rq(mdev, rq->rqn, in);
864 static int mlx5e_modify_rq_scatter_fcs(struct mlx5e_rq *rq, bool enable)
866 struct mlx5_core_dev *mdev = rq->mdev;
873 inlen = MLX5_ST_SZ_BYTES(modify_rq_in);
874 in = kvzalloc(inlen, GFP_KERNEL);
878 rqc = MLX5_ADDR_OF(modify_rq_in, in, ctx);
880 MLX5_SET(modify_rq_in, in, rq_state, MLX5_RQC_STATE_RDY);
881 MLX5_SET64(modify_rq_in, in, modify_bitmask,
882 MLX5_MODIFY_RQ_IN_MODIFY_BITMASK_SCATTER_FCS);
883 MLX5_SET(rqc, rqc, scatter_fcs, enable);
884 MLX5_SET(rqc, rqc, state, MLX5_RQC_STATE_RDY);
886 err = mlx5_core_modify_rq(mdev, rq->rqn, in);
893 static int mlx5e_modify_rq_vsd(struct mlx5e_rq *rq, bool vsd)
895 struct mlx5_core_dev *mdev = rq->mdev;
901 inlen = MLX5_ST_SZ_BYTES(modify_rq_in);
902 in = kvzalloc(inlen, GFP_KERNEL);
906 rqc = MLX5_ADDR_OF(modify_rq_in, in, ctx);
908 MLX5_SET(modify_rq_in, in, rq_state, MLX5_RQC_STATE_RDY);
909 MLX5_SET64(modify_rq_in, in, modify_bitmask,
910 MLX5_MODIFY_RQ_IN_MODIFY_BITMASK_VSD);
911 MLX5_SET(rqc, rqc, vsd, vsd);
912 MLX5_SET(rqc, rqc, state, MLX5_RQC_STATE_RDY);
914 err = mlx5_core_modify_rq(mdev, rq->rqn, in);
921 void mlx5e_destroy_rq(struct mlx5e_rq *rq)
923 mlx5_core_destroy_rq(rq->mdev, rq->rqn);
926 int mlx5e_wait_for_min_rx_wqes(struct mlx5e_rq *rq, int wait_time)
928 unsigned long exp_time = jiffies + msecs_to_jiffies(wait_time);
930 u16 min_wqes = mlx5_min_rx_wqes(rq->wq_type, mlx5e_rqwq_get_size(rq));
933 if (mlx5e_rqwq_get_cur_sz(rq) >= min_wqes)
937 } while (time_before(jiffies, exp_time));
939 netdev_warn(rq->netdev, "Failed to get min RX wqes on Channel[%d] RQN[0x%x] wq cur_sz(%d) min_rx_wqes(%d)\n",
940 rq->ix, rq->rqn, mlx5e_rqwq_get_cur_sz(rq), min_wqes);
942 mlx5e_reporter_rx_timeout(rq);
946 void mlx5e_free_rx_in_progress_descs(struct mlx5e_rq *rq)
948 struct mlx5_wq_ll *wq;
952 if (rq->wq_type != MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ)
958 /* Outstanding UMR WQEs (in progress) start at wq->head */
959 for (i = 0; i < rq->mpwqe.umr_in_progress; i++) {
960 rq->dealloc_wqe(rq, head);
961 head = mlx5_wq_ll_get_wqe_next_ix(wq, head);
964 if (test_bit(MLX5E_RQ_STATE_SHAMPO, &rq->state)) {
967 len = (rq->mpwqe.shampo->pi - rq->mpwqe.shampo->ci) &
968 (rq->mpwqe.shampo->hd_per_wq - 1);
969 mlx5e_shampo_dealloc_hd(rq, len, rq->mpwqe.shampo->ci, false);
970 rq->mpwqe.shampo->pi = rq->mpwqe.shampo->ci;
973 rq->mpwqe.actual_wq_head = wq->head;
974 rq->mpwqe.umr_in_progress = 0;
975 rq->mpwqe.umr_completed = 0;
978 void mlx5e_free_rx_descs(struct mlx5e_rq *rq)
983 if (rq->wq_type == MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ) {
984 struct mlx5_wq_ll *wq = &rq->mpwqe.wq;
986 mlx5e_free_rx_in_progress_descs(rq);
988 while (!mlx5_wq_ll_is_empty(wq)) {
989 struct mlx5e_rx_wqe_ll *wqe;
991 wqe_ix_be = *wq->tail_next;
992 wqe_ix = be16_to_cpu(wqe_ix_be);
993 wqe = mlx5_wq_ll_get_wqe(wq, wqe_ix);
994 rq->dealloc_wqe(rq, wqe_ix);
995 mlx5_wq_ll_pop(wq, wqe_ix_be,
996 &wqe->next.next_wqe_index);
999 if (test_bit(MLX5E_RQ_STATE_SHAMPO, &rq->state))
1000 mlx5e_shampo_dealloc_hd(rq, rq->mpwqe.shampo->hd_per_wq,
1003 struct mlx5_wq_cyc *wq = &rq->wqe.wq;
1005 while (!mlx5_wq_cyc_is_empty(wq)) {
1006 wqe_ix = mlx5_wq_cyc_get_tail(wq);
1007 rq->dealloc_wqe(rq, wqe_ix);
1008 mlx5_wq_cyc_pop(wq);
1014 int mlx5e_open_rq(struct mlx5e_params *params, struct mlx5e_rq_param *param,
1015 struct mlx5e_xsk_param *xsk, int node,
1016 struct mlx5e_rq *rq)
1018 struct mlx5_core_dev *mdev = rq->mdev;
1021 if (params->packet_merge.type == MLX5E_PACKET_MERGE_SHAMPO)
1022 __set_bit(MLX5E_RQ_STATE_SHAMPO, &rq->state);
1024 err = mlx5e_alloc_rq(params, xsk, param, node, rq);
1028 err = mlx5e_create_rq(rq, param);
1032 err = mlx5e_modify_rq_state(rq, MLX5_RQC_STATE_RST, MLX5_RQC_STATE_RDY);
1034 goto err_destroy_rq;
1036 if (mlx5e_is_tls_on(rq->priv) && !mlx5e_accel_is_ktls_device(mdev))
1037 __set_bit(MLX5E_RQ_STATE_FPGA_TLS, &rq->state); /* must be FPGA */
1039 if (MLX5_CAP_ETH(mdev, cqe_checksum_full))
1040 __set_bit(MLX5E_RQ_STATE_CSUM_FULL, &rq->state);
1042 if (params->rx_dim_enabled)
1043 __set_bit(MLX5E_RQ_STATE_AM, &rq->state);
1045 /* We disable csum_complete when XDP is enabled since
1046 * XDP programs might manipulate packets which will render
1047 * skb->checksum incorrect.
1049 if (MLX5E_GET_PFLAG(params, MLX5E_PFLAG_RX_NO_CSUM_COMPLETE) || params->xdp_prog)
1050 __set_bit(MLX5E_RQ_STATE_NO_CSUM_COMPLETE, &rq->state);
1052 /* For CQE compression on striding RQ, use stride index provided by
1053 * HW if capability is supported.
1055 if (MLX5E_GET_PFLAG(params, MLX5E_PFLAG_RX_STRIDING_RQ) &&
1056 MLX5_CAP_GEN(mdev, mini_cqe_resp_stride_index))
1057 __set_bit(MLX5E_RQ_STATE_MINI_CQE_HW_STRIDX, &rq->state);
1062 mlx5e_destroy_rq(rq);
1069 void mlx5e_activate_rq(struct mlx5e_rq *rq)
1071 set_bit(MLX5E_RQ_STATE_ENABLED, &rq->state);
1073 mlx5e_trigger_irq(rq->icosq);
1076 napi_schedule(rq->cq.napi);
1081 void mlx5e_deactivate_rq(struct mlx5e_rq *rq)
1083 clear_bit(MLX5E_RQ_STATE_ENABLED, &rq->state);
1084 synchronize_net(); /* Sync with NAPI to prevent mlx5e_post_rx_wqes. */
1087 void mlx5e_close_rq(struct mlx5e_rq *rq)
1089 cancel_work_sync(&rq->dim.work);
1090 cancel_work_sync(&rq->recover_work);
1091 mlx5e_destroy_rq(rq);
1092 mlx5e_free_rx_descs(rq);
1096 static void mlx5e_free_xdpsq_db(struct mlx5e_xdpsq *sq)
1098 kvfree(sq->db.xdpi_fifo.xi);
1099 kvfree(sq->db.wqe_info);
1102 static int mlx5e_alloc_xdpsq_fifo(struct mlx5e_xdpsq *sq, int numa)
1104 struct mlx5e_xdp_info_fifo *xdpi_fifo = &sq->db.xdpi_fifo;
1105 int wq_sz = mlx5_wq_cyc_get_size(&sq->wq);
1106 int dsegs_per_wq = wq_sz * MLX5_SEND_WQEBB_NUM_DS;
1109 size = array_size(sizeof(*xdpi_fifo->xi), dsegs_per_wq);
1110 xdpi_fifo->xi = kvzalloc_node(size, GFP_KERNEL, numa);
1114 xdpi_fifo->pc = &sq->xdpi_fifo_pc;
1115 xdpi_fifo->cc = &sq->xdpi_fifo_cc;
1116 xdpi_fifo->mask = dsegs_per_wq - 1;
1121 static int mlx5e_alloc_xdpsq_db(struct mlx5e_xdpsq *sq, int numa)
1123 int wq_sz = mlx5_wq_cyc_get_size(&sq->wq);
1127 size = array_size(sizeof(*sq->db.wqe_info), wq_sz);
1128 sq->db.wqe_info = kvzalloc_node(size, GFP_KERNEL, numa);
1129 if (!sq->db.wqe_info)
1132 err = mlx5e_alloc_xdpsq_fifo(sq, numa);
1134 mlx5e_free_xdpsq_db(sq);
1141 static int mlx5e_alloc_xdpsq(struct mlx5e_channel *c,
1142 struct mlx5e_params *params,
1143 struct xsk_buff_pool *xsk_pool,
1144 struct mlx5e_sq_param *param,
1145 struct mlx5e_xdpsq *sq,
1148 void *sqc_wq = MLX5_ADDR_OF(sqc, param->sqc, wq);
1149 struct mlx5_core_dev *mdev = c->mdev;
1150 struct mlx5_wq_cyc *wq = &sq->wq;
1154 sq->mkey_be = c->mkey_be;
1156 sq->uar_map = mdev->mlx5e_res.hw_objs.bfreg.map;
1157 sq->min_inline_mode = params->tx_min_inline_mode;
1158 sq->hw_mtu = MLX5E_SW2HW_MTU(params, params->sw_mtu);
1159 sq->xsk_pool = xsk_pool;
1161 sq->stats = sq->xsk_pool ?
1162 &c->priv->channel_stats[c->ix].xsksq :
1164 &c->priv->channel_stats[c->ix].xdpsq :
1165 &c->priv->channel_stats[c->ix].rq_xdpsq;
1167 param->wq.db_numa_node = cpu_to_node(c->cpu);
1168 err = mlx5_wq_cyc_create(mdev, ¶m->wq, sqc_wq, wq, &sq->wq_ctrl);
1171 wq->db = &wq->db[MLX5_SND_DBR];
1173 err = mlx5e_alloc_xdpsq_db(sq, cpu_to_node(c->cpu));
1175 goto err_sq_wq_destroy;
1180 mlx5_wq_destroy(&sq->wq_ctrl);
1185 static void mlx5e_free_xdpsq(struct mlx5e_xdpsq *sq)
1187 mlx5e_free_xdpsq_db(sq);
1188 mlx5_wq_destroy(&sq->wq_ctrl);
1191 static void mlx5e_free_icosq_db(struct mlx5e_icosq *sq)
1193 kvfree(sq->db.wqe_info);
1196 static int mlx5e_alloc_icosq_db(struct mlx5e_icosq *sq, int numa)
1198 int wq_sz = mlx5_wq_cyc_get_size(&sq->wq);
1201 size = array_size(wq_sz, sizeof(*sq->db.wqe_info));
1202 sq->db.wqe_info = kvzalloc_node(size, GFP_KERNEL, numa);
1203 if (!sq->db.wqe_info)
1209 static void mlx5e_icosq_err_cqe_work(struct work_struct *recover_work)
1211 struct mlx5e_icosq *sq = container_of(recover_work, struct mlx5e_icosq,
1214 mlx5e_reporter_icosq_cqe_err(sq);
1217 static void mlx5e_async_icosq_err_cqe_work(struct work_struct *recover_work)
1219 struct mlx5e_icosq *sq = container_of(recover_work, struct mlx5e_icosq,
1222 /* Not implemented yet. */
1224 netdev_warn(sq->channel->netdev, "async_icosq recovery is not implemented\n");
1227 static int mlx5e_alloc_icosq(struct mlx5e_channel *c,
1228 struct mlx5e_sq_param *param,
1229 struct mlx5e_icosq *sq,
1230 work_func_t recover_work_func)
1232 void *sqc_wq = MLX5_ADDR_OF(sqc, param->sqc, wq);
1233 struct mlx5_core_dev *mdev = c->mdev;
1234 struct mlx5_wq_cyc *wq = &sq->wq;
1238 sq->uar_map = mdev->mlx5e_res.hw_objs.bfreg.map;
1239 sq->reserved_room = param->stop_room;
1241 param->wq.db_numa_node = cpu_to_node(c->cpu);
1242 err = mlx5_wq_cyc_create(mdev, ¶m->wq, sqc_wq, wq, &sq->wq_ctrl);
1245 wq->db = &wq->db[MLX5_SND_DBR];
1247 err = mlx5e_alloc_icosq_db(sq, cpu_to_node(c->cpu));
1249 goto err_sq_wq_destroy;
1251 INIT_WORK(&sq->recover_work, recover_work_func);
1256 mlx5_wq_destroy(&sq->wq_ctrl);
1261 static void mlx5e_free_icosq(struct mlx5e_icosq *sq)
1263 mlx5e_free_icosq_db(sq);
1264 mlx5_wq_destroy(&sq->wq_ctrl);
1267 void mlx5e_free_txqsq_db(struct mlx5e_txqsq *sq)
1269 kvfree(sq->db.wqe_info);
1270 kvfree(sq->db.skb_fifo.fifo);
1271 kvfree(sq->db.dma_fifo);
1274 int mlx5e_alloc_txqsq_db(struct mlx5e_txqsq *sq, int numa)
1276 int wq_sz = mlx5_wq_cyc_get_size(&sq->wq);
1277 int df_sz = wq_sz * MLX5_SEND_WQEBB_NUM_DS;
1279 sq->db.dma_fifo = kvzalloc_node(array_size(df_sz,
1280 sizeof(*sq->db.dma_fifo)),
1282 sq->db.skb_fifo.fifo = kvzalloc_node(array_size(df_sz,
1283 sizeof(*sq->db.skb_fifo.fifo)),
1285 sq->db.wqe_info = kvzalloc_node(array_size(wq_sz,
1286 sizeof(*sq->db.wqe_info)),
1288 if (!sq->db.dma_fifo || !sq->db.skb_fifo.fifo || !sq->db.wqe_info) {
1289 mlx5e_free_txqsq_db(sq);
1293 sq->dma_fifo_mask = df_sz - 1;
1295 sq->db.skb_fifo.pc = &sq->skb_fifo_pc;
1296 sq->db.skb_fifo.cc = &sq->skb_fifo_cc;
1297 sq->db.skb_fifo.mask = df_sz - 1;
1302 static int mlx5e_alloc_txqsq(struct mlx5e_channel *c,
1304 struct mlx5e_params *params,
1305 struct mlx5e_sq_param *param,
1306 struct mlx5e_txqsq *sq,
1309 void *sqc_wq = MLX5_ADDR_OF(sqc, param->sqc, wq);
1310 struct mlx5_core_dev *mdev = c->mdev;
1311 struct mlx5_wq_cyc *wq = &sq->wq;
1315 sq->tstamp = c->tstamp;
1316 sq->clock = &mdev->clock;
1317 sq->mkey_be = c->mkey_be;
1318 sq->netdev = c->netdev;
1322 sq->txq_ix = txq_ix;
1323 sq->uar_map = mdev->mlx5e_res.hw_objs.bfreg.map;
1324 sq->min_inline_mode = params->tx_min_inline_mode;
1325 sq->hw_mtu = MLX5E_SW2HW_MTU(params, params->sw_mtu);
1326 INIT_WORK(&sq->recover_work, mlx5e_tx_err_cqe_work);
1327 if (!MLX5_CAP_ETH(mdev, wqe_vlan_insert))
1328 set_bit(MLX5E_SQ_STATE_VLAN_NEED_L2_INLINE, &sq->state);
1329 if (MLX5_IPSEC_DEV(c->priv->mdev))
1330 set_bit(MLX5E_SQ_STATE_IPSEC, &sq->state);
1332 set_bit(MLX5E_SQ_STATE_MPWQE, &sq->state);
1333 sq->stop_room = param->stop_room;
1334 sq->ptp_cyc2time = mlx5_sq_ts_translator(mdev);
1336 param->wq.db_numa_node = cpu_to_node(c->cpu);
1337 err = mlx5_wq_cyc_create(mdev, ¶m->wq, sqc_wq, wq, &sq->wq_ctrl);
1340 wq->db = &wq->db[MLX5_SND_DBR];
1342 err = mlx5e_alloc_txqsq_db(sq, cpu_to_node(c->cpu));
1344 goto err_sq_wq_destroy;
1346 INIT_WORK(&sq->dim.work, mlx5e_tx_dim_work);
1347 sq->dim.mode = params->tx_cq_moderation.cq_period_mode;
1352 mlx5_wq_destroy(&sq->wq_ctrl);
1357 void mlx5e_free_txqsq(struct mlx5e_txqsq *sq)
1359 mlx5e_free_txqsq_db(sq);
1360 mlx5_wq_destroy(&sq->wq_ctrl);
1363 static int mlx5e_create_sq(struct mlx5_core_dev *mdev,
1364 struct mlx5e_sq_param *param,
1365 struct mlx5e_create_sq_param *csp,
1375 inlen = MLX5_ST_SZ_BYTES(create_sq_in) +
1376 sizeof(u64) * csp->wq_ctrl->buf.npages;
1377 in = kvzalloc(inlen, GFP_KERNEL);
1381 ts_format = mlx5_is_real_time_sq(mdev) ?
1382 MLX5_TIMESTAMP_FORMAT_REAL_TIME :
1383 MLX5_TIMESTAMP_FORMAT_FREE_RUNNING;
1384 sqc = MLX5_ADDR_OF(create_sq_in, in, ctx);
1385 wq = MLX5_ADDR_OF(sqc, sqc, wq);
1387 memcpy(sqc, param->sqc, sizeof(param->sqc));
1388 MLX5_SET(sqc, sqc, tis_lst_sz, csp->tis_lst_sz);
1389 MLX5_SET(sqc, sqc, tis_num_0, csp->tisn);
1390 MLX5_SET(sqc, sqc, cqn, csp->cqn);
1391 MLX5_SET(sqc, sqc, ts_cqe_to_dest_cqn, csp->ts_cqe_to_dest_cqn);
1392 MLX5_SET(sqc, sqc, ts_format, ts_format);
1395 if (MLX5_CAP_ETH(mdev, wqe_inline_mode) == MLX5_CAP_INLINE_MODE_VPORT_CONTEXT)
1396 MLX5_SET(sqc, sqc, min_wqe_inline_mode, csp->min_inline_mode);
1398 MLX5_SET(sqc, sqc, state, MLX5_SQC_STATE_RST);
1399 MLX5_SET(sqc, sqc, flush_in_error_en, 1);
1401 MLX5_SET(wq, wq, wq_type, MLX5_WQ_TYPE_CYCLIC);
1402 MLX5_SET(wq, wq, uar_page, mdev->mlx5e_res.hw_objs.bfreg.index);
1403 MLX5_SET(wq, wq, log_wq_pg_sz, csp->wq_ctrl->buf.page_shift -
1404 MLX5_ADAPTER_PAGE_SHIFT);
1405 MLX5_SET64(wq, wq, dbr_addr, csp->wq_ctrl->db.dma);
1407 mlx5_fill_page_frag_array(&csp->wq_ctrl->buf,
1408 (__be64 *)MLX5_ADDR_OF(wq, wq, pas));
1410 err = mlx5_core_create_sq(mdev, in, inlen, sqn);
1417 int mlx5e_modify_sq(struct mlx5_core_dev *mdev, u32 sqn,
1418 struct mlx5e_modify_sq_param *p)
1426 inlen = MLX5_ST_SZ_BYTES(modify_sq_in);
1427 in = kvzalloc(inlen, GFP_KERNEL);
1431 sqc = MLX5_ADDR_OF(modify_sq_in, in, ctx);
1433 MLX5_SET(modify_sq_in, in, sq_state, p->curr_state);
1434 MLX5_SET(sqc, sqc, state, p->next_state);
1435 if (p->rl_update && p->next_state == MLX5_SQC_STATE_RDY) {
1437 MLX5_SET(sqc, sqc, packet_pacing_rate_limit_index, p->rl_index);
1439 if (p->qos_update && p->next_state == MLX5_SQC_STATE_RDY) {
1441 MLX5_SET(sqc, sqc, qos_queue_group_id, p->qos_queue_group_id);
1443 MLX5_SET64(modify_sq_in, in, modify_bitmask, bitmask);
1445 err = mlx5_core_modify_sq(mdev, sqn, in);
1452 static void mlx5e_destroy_sq(struct mlx5_core_dev *mdev, u32 sqn)
1454 mlx5_core_destroy_sq(mdev, sqn);
1457 int mlx5e_create_sq_rdy(struct mlx5_core_dev *mdev,
1458 struct mlx5e_sq_param *param,
1459 struct mlx5e_create_sq_param *csp,
1460 u16 qos_queue_group_id,
1463 struct mlx5e_modify_sq_param msp = {0};
1466 err = mlx5e_create_sq(mdev, param, csp, sqn);
1470 msp.curr_state = MLX5_SQC_STATE_RST;
1471 msp.next_state = MLX5_SQC_STATE_RDY;
1472 if (qos_queue_group_id) {
1473 msp.qos_update = true;
1474 msp.qos_queue_group_id = qos_queue_group_id;
1476 err = mlx5e_modify_sq(mdev, *sqn, &msp);
1478 mlx5e_destroy_sq(mdev, *sqn);
1483 static int mlx5e_set_sq_maxrate(struct net_device *dev,
1484 struct mlx5e_txqsq *sq, u32 rate);
1486 int mlx5e_open_txqsq(struct mlx5e_channel *c, u32 tisn, int txq_ix,
1487 struct mlx5e_params *params, struct mlx5e_sq_param *param,
1488 struct mlx5e_txqsq *sq, int tc, u16 qos_queue_group_id,
1489 struct mlx5e_sq_stats *sq_stats)
1491 struct mlx5e_create_sq_param csp = {};
1495 err = mlx5e_alloc_txqsq(c, txq_ix, params, param, sq, tc);
1499 sq->stats = sq_stats;
1503 csp.cqn = sq->cq.mcq.cqn;
1504 csp.wq_ctrl = &sq->wq_ctrl;
1505 csp.min_inline_mode = sq->min_inline_mode;
1506 err = mlx5e_create_sq_rdy(c->mdev, param, &csp, qos_queue_group_id, &sq->sqn);
1508 goto err_free_txqsq;
1510 tx_rate = c->priv->tx_rates[sq->txq_ix];
1512 mlx5e_set_sq_maxrate(c->netdev, sq, tx_rate);
1514 if (params->tx_dim_enabled)
1515 sq->state |= BIT(MLX5E_SQ_STATE_AM);
1520 mlx5e_free_txqsq(sq);
1525 void mlx5e_activate_txqsq(struct mlx5e_txqsq *sq)
1527 sq->txq = netdev_get_tx_queue(sq->netdev, sq->txq_ix);
1528 set_bit(MLX5E_SQ_STATE_ENABLED, &sq->state);
1529 netdev_tx_reset_queue(sq->txq);
1530 netif_tx_start_queue(sq->txq);
1533 void mlx5e_tx_disable_queue(struct netdev_queue *txq)
1535 __netif_tx_lock_bh(txq);
1536 netif_tx_stop_queue(txq);
1537 __netif_tx_unlock_bh(txq);
1540 void mlx5e_deactivate_txqsq(struct mlx5e_txqsq *sq)
1542 struct mlx5_wq_cyc *wq = &sq->wq;
1544 clear_bit(MLX5E_SQ_STATE_ENABLED, &sq->state);
1545 synchronize_net(); /* Sync with NAPI to prevent netif_tx_wake_queue. */
1547 mlx5e_tx_disable_queue(sq->txq);
1549 /* last doorbell out, godspeed .. */
1550 if (mlx5e_wqc_has_room_for(wq, sq->cc, sq->pc, 1)) {
1551 u16 pi = mlx5_wq_cyc_ctr2ix(wq, sq->pc);
1552 struct mlx5e_tx_wqe *nop;
1554 sq->db.wqe_info[pi] = (struct mlx5e_tx_wqe_info) {
1558 nop = mlx5e_post_nop(wq, sq->sqn, &sq->pc);
1559 mlx5e_notify_hw(wq, sq->pc, sq->uar_map, &nop->ctrl);
1563 void mlx5e_close_txqsq(struct mlx5e_txqsq *sq)
1565 struct mlx5_core_dev *mdev = sq->mdev;
1566 struct mlx5_rate_limit rl = {0};
1568 cancel_work_sync(&sq->dim.work);
1569 cancel_work_sync(&sq->recover_work);
1570 mlx5e_destroy_sq(mdev, sq->sqn);
1571 if (sq->rate_limit) {
1572 rl.rate = sq->rate_limit;
1573 mlx5_rl_remove_rate(mdev, &rl);
1575 mlx5e_free_txqsq_descs(sq);
1576 mlx5e_free_txqsq(sq);
1579 void mlx5e_tx_err_cqe_work(struct work_struct *recover_work)
1581 struct mlx5e_txqsq *sq = container_of(recover_work, struct mlx5e_txqsq,
1584 mlx5e_reporter_tx_err_cqe(sq);
1587 static int mlx5e_open_icosq(struct mlx5e_channel *c, struct mlx5e_params *params,
1588 struct mlx5e_sq_param *param, struct mlx5e_icosq *sq,
1589 work_func_t recover_work_func)
1591 struct mlx5e_create_sq_param csp = {};
1594 err = mlx5e_alloc_icosq(c, param, sq, recover_work_func);
1598 csp.cqn = sq->cq.mcq.cqn;
1599 csp.wq_ctrl = &sq->wq_ctrl;
1600 csp.min_inline_mode = params->tx_min_inline_mode;
1601 err = mlx5e_create_sq_rdy(c->mdev, param, &csp, 0, &sq->sqn);
1603 goto err_free_icosq;
1605 if (param->is_tls) {
1606 sq->ktls_resync = mlx5e_ktls_rx_resync_create_resp_list();
1607 if (IS_ERR(sq->ktls_resync)) {
1608 err = PTR_ERR(sq->ktls_resync);
1609 goto err_destroy_icosq;
1615 mlx5e_destroy_sq(c->mdev, sq->sqn);
1617 mlx5e_free_icosq(sq);
1622 void mlx5e_activate_icosq(struct mlx5e_icosq *icosq)
1624 set_bit(MLX5E_SQ_STATE_ENABLED, &icosq->state);
1627 void mlx5e_deactivate_icosq(struct mlx5e_icosq *icosq)
1629 clear_bit(MLX5E_SQ_STATE_ENABLED, &icosq->state);
1630 synchronize_net(); /* Sync with NAPI. */
1633 static void mlx5e_close_icosq(struct mlx5e_icosq *sq)
1635 struct mlx5e_channel *c = sq->channel;
1637 if (sq->ktls_resync)
1638 mlx5e_ktls_rx_resync_destroy_resp_list(sq->ktls_resync);
1639 mlx5e_destroy_sq(c->mdev, sq->sqn);
1640 mlx5e_free_icosq_descs(sq);
1641 mlx5e_free_icosq(sq);
1644 int mlx5e_open_xdpsq(struct mlx5e_channel *c, struct mlx5e_params *params,
1645 struct mlx5e_sq_param *param, struct xsk_buff_pool *xsk_pool,
1646 struct mlx5e_xdpsq *sq, bool is_redirect)
1648 struct mlx5e_create_sq_param csp = {};
1651 err = mlx5e_alloc_xdpsq(c, params, xsk_pool, param, sq, is_redirect);
1656 csp.tisn = c->priv->tisn[c->lag_port][0]; /* tc = 0 */
1657 csp.cqn = sq->cq.mcq.cqn;
1658 csp.wq_ctrl = &sq->wq_ctrl;
1659 csp.min_inline_mode = sq->min_inline_mode;
1660 set_bit(MLX5E_SQ_STATE_ENABLED, &sq->state);
1661 err = mlx5e_create_sq_rdy(c->mdev, param, &csp, 0, &sq->sqn);
1663 goto err_free_xdpsq;
1665 mlx5e_set_xmit_fp(sq, param->is_mpw);
1667 if (!param->is_mpw) {
1668 unsigned int ds_cnt = MLX5E_XDP_TX_DS_COUNT;
1669 unsigned int inline_hdr_sz = 0;
1672 if (sq->min_inline_mode != MLX5_INLINE_MODE_NONE) {
1673 inline_hdr_sz = MLX5E_XDP_MIN_INLINE;
1677 /* Pre initialize fixed WQE fields */
1678 for (i = 0; i < mlx5_wq_cyc_get_size(&sq->wq); i++) {
1679 struct mlx5e_tx_wqe *wqe = mlx5_wq_cyc_get_wqe(&sq->wq, i);
1680 struct mlx5_wqe_ctrl_seg *cseg = &wqe->ctrl;
1681 struct mlx5_wqe_eth_seg *eseg = &wqe->eth;
1682 struct mlx5_wqe_data_seg *dseg;
1684 sq->db.wqe_info[i] = (struct mlx5e_xdp_wqe_info) {
1689 cseg->qpn_ds = cpu_to_be32((sq->sqn << 8) | ds_cnt);
1690 eseg->inline_hdr.sz = cpu_to_be16(inline_hdr_sz);
1692 dseg = (struct mlx5_wqe_data_seg *)cseg + (ds_cnt - 1);
1693 dseg->lkey = sq->mkey_be;
1700 clear_bit(MLX5E_SQ_STATE_ENABLED, &sq->state);
1701 mlx5e_free_xdpsq(sq);
1706 void mlx5e_close_xdpsq(struct mlx5e_xdpsq *sq)
1708 struct mlx5e_channel *c = sq->channel;
1710 clear_bit(MLX5E_SQ_STATE_ENABLED, &sq->state);
1711 synchronize_net(); /* Sync with NAPI. */
1713 mlx5e_destroy_sq(c->mdev, sq->sqn);
1714 mlx5e_free_xdpsq_descs(sq);
1715 mlx5e_free_xdpsq(sq);
1718 static int mlx5e_alloc_cq_common(struct mlx5e_priv *priv,
1719 struct mlx5e_cq_param *param,
1720 struct mlx5e_cq *cq)
1722 struct mlx5_core_dev *mdev = priv->mdev;
1723 struct mlx5_core_cq *mcq = &cq->mcq;
1727 err = mlx5_cqwq_create(mdev, ¶m->wq, param->cqc, &cq->wq,
1733 mcq->set_ci_db = cq->wq_ctrl.db.db;
1734 mcq->arm_db = cq->wq_ctrl.db.db + 1;
1735 *mcq->set_ci_db = 0;
1737 mcq->vector = param->eq_ix;
1738 mcq->comp = mlx5e_completion_event;
1739 mcq->event = mlx5e_cq_error_event;
1741 for (i = 0; i < mlx5_cqwq_get_size(&cq->wq); i++) {
1742 struct mlx5_cqe64 *cqe = mlx5_cqwq_get_wqe(&cq->wq, i);
1748 cq->netdev = priv->netdev;
1754 static int mlx5e_alloc_cq(struct mlx5e_priv *priv,
1755 struct mlx5e_cq_param *param,
1756 struct mlx5e_create_cq_param *ccp,
1757 struct mlx5e_cq *cq)
1761 param->wq.buf_numa_node = ccp->node;
1762 param->wq.db_numa_node = ccp->node;
1763 param->eq_ix = ccp->ix;
1765 err = mlx5e_alloc_cq_common(priv, param, cq);
1767 cq->napi = ccp->napi;
1768 cq->ch_stats = ccp->ch_stats;
1773 static void mlx5e_free_cq(struct mlx5e_cq *cq)
1775 mlx5_wq_destroy(&cq->wq_ctrl);
1778 static int mlx5e_create_cq(struct mlx5e_cq *cq, struct mlx5e_cq_param *param)
1780 u32 out[MLX5_ST_SZ_DW(create_cq_out)];
1781 struct mlx5_core_dev *mdev = cq->mdev;
1782 struct mlx5_core_cq *mcq = &cq->mcq;
1790 err = mlx5_vector2eqn(mdev, param->eq_ix, &eqn);
1794 inlen = MLX5_ST_SZ_BYTES(create_cq_in) +
1795 sizeof(u64) * cq->wq_ctrl.buf.npages;
1796 in = kvzalloc(inlen, GFP_KERNEL);
1800 cqc = MLX5_ADDR_OF(create_cq_in, in, cq_context);
1802 memcpy(cqc, param->cqc, sizeof(param->cqc));
1804 mlx5_fill_page_frag_array(&cq->wq_ctrl.buf,
1805 (__be64 *)MLX5_ADDR_OF(create_cq_in, in, pas));
1807 MLX5_SET(cqc, cqc, cq_period_mode, param->cq_period_mode);
1808 MLX5_SET(cqc, cqc, c_eqn_or_apu_element, eqn);
1809 MLX5_SET(cqc, cqc, uar_page, mdev->priv.uar->index);
1810 MLX5_SET(cqc, cqc, log_page_size, cq->wq_ctrl.buf.page_shift -
1811 MLX5_ADAPTER_PAGE_SHIFT);
1812 MLX5_SET64(cqc, cqc, dbr_addr, cq->wq_ctrl.db.dma);
1814 err = mlx5_core_create_cq(mdev, mcq, in, inlen, out, sizeof(out));
1826 static void mlx5e_destroy_cq(struct mlx5e_cq *cq)
1828 mlx5_core_destroy_cq(cq->mdev, &cq->mcq);
1831 int mlx5e_open_cq(struct mlx5e_priv *priv, struct dim_cq_moder moder,
1832 struct mlx5e_cq_param *param, struct mlx5e_create_cq_param *ccp,
1833 struct mlx5e_cq *cq)
1835 struct mlx5_core_dev *mdev = priv->mdev;
1838 err = mlx5e_alloc_cq(priv, param, ccp, cq);
1842 err = mlx5e_create_cq(cq, param);
1846 if (MLX5_CAP_GEN(mdev, cq_moderation))
1847 mlx5_core_modify_cq_moderation(mdev, &cq->mcq, moder.usec, moder.pkts);
1856 void mlx5e_close_cq(struct mlx5e_cq *cq)
1858 mlx5e_destroy_cq(cq);
1862 static int mlx5e_open_tx_cqs(struct mlx5e_channel *c,
1863 struct mlx5e_params *params,
1864 struct mlx5e_create_cq_param *ccp,
1865 struct mlx5e_channel_param *cparam)
1870 for (tc = 0; tc < c->num_tc; tc++) {
1871 err = mlx5e_open_cq(c->priv, params->tx_cq_moderation, &cparam->txq_sq.cqp,
1872 ccp, &c->sq[tc].cq);
1874 goto err_close_tx_cqs;
1880 for (tc--; tc >= 0; tc--)
1881 mlx5e_close_cq(&c->sq[tc].cq);
1886 static void mlx5e_close_tx_cqs(struct mlx5e_channel *c)
1890 for (tc = 0; tc < c->num_tc; tc++)
1891 mlx5e_close_cq(&c->sq[tc].cq);
1894 static int mlx5e_mqprio_txq_to_tc(struct netdev_tc_txq *tc_to_txq, unsigned int txq)
1898 for (tc = 0; tc < TC_MAX_QUEUE; tc++)
1899 if (txq - tc_to_txq[tc].offset < tc_to_txq[tc].count)
1902 WARN(1, "Unexpected TCs configuration. No match found for txq %u", txq);
1906 static int mlx5e_txq_get_qos_node_hw_id(struct mlx5e_params *params, int txq_ix,
1911 if (params->mqprio.mode != TC_MQPRIO_MODE_CHANNEL ||
1912 !params->mqprio.channel.rl) {
1917 tc = mlx5e_mqprio_txq_to_tc(params->mqprio.tc_to_txq, txq_ix);
1921 return mlx5e_mqprio_rl_get_node_hw_id(params->mqprio.channel.rl, tc, hw_id);
1924 static int mlx5e_open_sqs(struct mlx5e_channel *c,
1925 struct mlx5e_params *params,
1926 struct mlx5e_channel_param *cparam)
1930 for (tc = 0; tc < mlx5e_get_dcb_num_tc(params); tc++) {
1931 int txq_ix = c->ix + tc * params->num_channels;
1932 u32 qos_queue_group_id;
1934 err = mlx5e_txq_get_qos_node_hw_id(params, txq_ix, &qos_queue_group_id);
1938 err = mlx5e_open_txqsq(c, c->priv->tisn[c->lag_port][tc], txq_ix,
1939 params, &cparam->txq_sq, &c->sq[tc], tc,
1941 &c->priv->channel_stats[c->ix].sq[tc]);
1949 for (tc--; tc >= 0; tc--)
1950 mlx5e_close_txqsq(&c->sq[tc]);
1955 static void mlx5e_close_sqs(struct mlx5e_channel *c)
1959 for (tc = 0; tc < c->num_tc; tc++)
1960 mlx5e_close_txqsq(&c->sq[tc]);
1963 static int mlx5e_set_sq_maxrate(struct net_device *dev,
1964 struct mlx5e_txqsq *sq, u32 rate)
1966 struct mlx5e_priv *priv = netdev_priv(dev);
1967 struct mlx5_core_dev *mdev = priv->mdev;
1968 struct mlx5e_modify_sq_param msp = {0};
1969 struct mlx5_rate_limit rl = {0};
1973 if (rate == sq->rate_limit)
1977 if (sq->rate_limit) {
1978 rl.rate = sq->rate_limit;
1979 /* remove current rl index to free space to next ones */
1980 mlx5_rl_remove_rate(mdev, &rl);
1987 err = mlx5_rl_add_rate(mdev, &rl_index, &rl);
1989 netdev_err(dev, "Failed configuring rate %u: %d\n",
1995 msp.curr_state = MLX5_SQC_STATE_RDY;
1996 msp.next_state = MLX5_SQC_STATE_RDY;
1997 msp.rl_index = rl_index;
1998 msp.rl_update = true;
1999 err = mlx5e_modify_sq(mdev, sq->sqn, &msp);
2001 netdev_err(dev, "Failed configuring rate %u: %d\n",
2003 /* remove the rate from the table */
2005 mlx5_rl_remove_rate(mdev, &rl);
2009 sq->rate_limit = rate;
2013 static int mlx5e_set_tx_maxrate(struct net_device *dev, int index, u32 rate)
2015 struct mlx5e_priv *priv = netdev_priv(dev);
2016 struct mlx5_core_dev *mdev = priv->mdev;
2017 struct mlx5e_txqsq *sq = priv->txq2sq[index];
2020 if (!mlx5_rl_is_supported(mdev)) {
2021 netdev_err(dev, "Rate limiting is not supported on this device\n");
2025 /* rate is given in Mb/sec, HW config is in Kb/sec */
2028 /* Check whether rate in valid range, 0 is always valid */
2029 if (rate && !mlx5_rl_is_in_range(mdev, rate)) {
2030 netdev_err(dev, "TX rate %u, is not in range\n", rate);
2034 mutex_lock(&priv->state_lock);
2035 if (test_bit(MLX5E_STATE_OPENED, &priv->state))
2036 err = mlx5e_set_sq_maxrate(dev, sq, rate);
2038 priv->tx_rates[index] = rate;
2039 mutex_unlock(&priv->state_lock);
2044 static int mlx5e_open_rxq_rq(struct mlx5e_channel *c, struct mlx5e_params *params,
2045 struct mlx5e_rq_param *rq_params)
2049 err = mlx5e_init_rxq_rq(c, params, &c->rq);
2053 return mlx5e_open_rq(params, rq_params, NULL, cpu_to_node(c->cpu), &c->rq);
2056 static int mlx5e_open_queues(struct mlx5e_channel *c,
2057 struct mlx5e_params *params,
2058 struct mlx5e_channel_param *cparam)
2060 struct dim_cq_moder icocq_moder = {0, 0};
2061 struct mlx5e_create_cq_param ccp;
2064 mlx5e_build_create_cq_param(&ccp, c);
2066 err = mlx5e_open_cq(c->priv, icocq_moder, &cparam->async_icosq.cqp, &ccp,
2067 &c->async_icosq.cq);
2071 err = mlx5e_open_cq(c->priv, icocq_moder, &cparam->icosq.cqp, &ccp,
2074 goto err_close_async_icosq_cq;
2076 err = mlx5e_open_tx_cqs(c, params, &ccp, cparam);
2078 goto err_close_icosq_cq;
2080 err = mlx5e_open_cq(c->priv, params->tx_cq_moderation, &cparam->xdp_sq.cqp, &ccp,
2083 goto err_close_tx_cqs;
2085 err = mlx5e_open_cq(c->priv, params->rx_cq_moderation, &cparam->rq.cqp, &ccp,
2088 goto err_close_xdp_tx_cqs;
2090 err = c->xdp ? mlx5e_open_cq(c->priv, params->tx_cq_moderation, &cparam->xdp_sq.cqp,
2091 &ccp, &c->rq_xdpsq.cq) : 0;
2093 goto err_close_rx_cq;
2095 spin_lock_init(&c->async_icosq_lock);
2097 err = mlx5e_open_icosq(c, params, &cparam->async_icosq, &c->async_icosq,
2098 mlx5e_async_icosq_err_cqe_work);
2100 goto err_close_xdpsq_cq;
2102 mutex_init(&c->icosq_recovery_lock);
2104 err = mlx5e_open_icosq(c, params, &cparam->icosq, &c->icosq,
2105 mlx5e_icosq_err_cqe_work);
2107 goto err_close_async_icosq;
2109 err = mlx5e_open_sqs(c, params, cparam);
2111 goto err_close_icosq;
2113 err = mlx5e_open_rxq_rq(c, params, &cparam->rq);
2118 err = mlx5e_open_xdpsq(c, params, &cparam->xdp_sq, NULL,
2119 &c->rq_xdpsq, false);
2124 err = mlx5e_open_xdpsq(c, params, &cparam->xdp_sq, NULL, &c->xdpsq, true);
2126 goto err_close_xdp_sq;
2132 mlx5e_close_xdpsq(&c->rq_xdpsq);
2135 mlx5e_close_rq(&c->rq);
2141 mlx5e_close_icosq(&c->icosq);
2143 err_close_async_icosq:
2144 mlx5e_close_icosq(&c->async_icosq);
2148 mlx5e_close_cq(&c->rq_xdpsq.cq);
2151 mlx5e_close_cq(&c->rq.cq);
2153 err_close_xdp_tx_cqs:
2154 mlx5e_close_cq(&c->xdpsq.cq);
2157 mlx5e_close_tx_cqs(c);
2160 mlx5e_close_cq(&c->icosq.cq);
2162 err_close_async_icosq_cq:
2163 mlx5e_close_cq(&c->async_icosq.cq);
2168 static void mlx5e_close_queues(struct mlx5e_channel *c)
2170 mlx5e_close_xdpsq(&c->xdpsq);
2172 mlx5e_close_xdpsq(&c->rq_xdpsq);
2173 /* The same ICOSQ is used for UMRs for both RQ and XSKRQ. */
2174 cancel_work_sync(&c->icosq.recover_work);
2175 mlx5e_close_rq(&c->rq);
2177 mlx5e_close_icosq(&c->icosq);
2178 mutex_destroy(&c->icosq_recovery_lock);
2179 mlx5e_close_icosq(&c->async_icosq);
2181 mlx5e_close_cq(&c->rq_xdpsq.cq);
2182 mlx5e_close_cq(&c->rq.cq);
2183 mlx5e_close_cq(&c->xdpsq.cq);
2184 mlx5e_close_tx_cqs(c);
2185 mlx5e_close_cq(&c->icosq.cq);
2186 mlx5e_close_cq(&c->async_icosq.cq);
2189 static u8 mlx5e_enumerate_lag_port(struct mlx5_core_dev *mdev, int ix)
2191 u16 port_aff_bias = mlx5_core_is_pf(mdev) ? 0 : MLX5_CAP_GEN(mdev, vhca_id);
2193 return (ix + port_aff_bias) % mlx5e_get_num_lag_ports(mdev);
2196 static int mlx5e_open_channel(struct mlx5e_priv *priv, int ix,
2197 struct mlx5e_params *params,
2198 struct mlx5e_channel_param *cparam,
2199 struct xsk_buff_pool *xsk_pool,
2200 struct mlx5e_channel **cp)
2202 int cpu = cpumask_first(mlx5_comp_irq_get_affinity_mask(priv->mdev, ix));
2203 struct net_device *netdev = priv->netdev;
2204 struct mlx5e_xsk_param xsk;
2205 struct mlx5e_channel *c;
2209 err = mlx5_vector2irqn(priv->mdev, ix, &irq);
2213 c = kvzalloc_node(sizeof(*c), GFP_KERNEL, cpu_to_node(cpu));
2218 c->mdev = priv->mdev;
2219 c->tstamp = &priv->tstamp;
2222 c->pdev = mlx5_core_dma_dev(priv->mdev);
2223 c->netdev = priv->netdev;
2224 c->mkey_be = cpu_to_be32(priv->mdev->mlx5e_res.hw_objs.mkey);
2225 c->num_tc = mlx5e_get_dcb_num_tc(params);
2226 c->xdp = !!params->xdp_prog;
2227 c->stats = &priv->channel_stats[ix].ch;
2228 c->aff_mask = irq_get_effective_affinity_mask(irq);
2229 c->lag_port = mlx5e_enumerate_lag_port(priv->mdev, ix);
2231 netif_napi_add(netdev, &c->napi, mlx5e_napi_poll, 64);
2233 err = mlx5e_open_queues(c, params, cparam);
2238 mlx5e_build_xsk_param(xsk_pool, &xsk);
2239 err = mlx5e_open_xsk(priv, params, &xsk, xsk_pool, c);
2241 goto err_close_queues;
2249 mlx5e_close_queues(c);
2252 netif_napi_del(&c->napi);
2259 static void mlx5e_activate_channel(struct mlx5e_channel *c)
2263 napi_enable(&c->napi);
2265 for (tc = 0; tc < c->num_tc; tc++)
2266 mlx5e_activate_txqsq(&c->sq[tc]);
2267 mlx5e_activate_icosq(&c->icosq);
2268 mlx5e_activate_icosq(&c->async_icosq);
2269 mlx5e_activate_rq(&c->rq);
2271 if (test_bit(MLX5E_CHANNEL_STATE_XSK, c->state))
2272 mlx5e_activate_xsk(c);
2275 static void mlx5e_deactivate_channel(struct mlx5e_channel *c)
2279 if (test_bit(MLX5E_CHANNEL_STATE_XSK, c->state))
2280 mlx5e_deactivate_xsk(c);
2282 mlx5e_deactivate_rq(&c->rq);
2283 mlx5e_deactivate_icosq(&c->async_icosq);
2284 mlx5e_deactivate_icosq(&c->icosq);
2285 for (tc = 0; tc < c->num_tc; tc++)
2286 mlx5e_deactivate_txqsq(&c->sq[tc]);
2287 mlx5e_qos_deactivate_queues(c);
2289 napi_disable(&c->napi);
2292 static void mlx5e_close_channel(struct mlx5e_channel *c)
2294 if (test_bit(MLX5E_CHANNEL_STATE_XSK, c->state))
2296 mlx5e_close_queues(c);
2297 mlx5e_qos_close_queues(c);
2298 netif_napi_del(&c->napi);
2303 int mlx5e_open_channels(struct mlx5e_priv *priv,
2304 struct mlx5e_channels *chs)
2306 struct mlx5e_channel_param *cparam;
2310 chs->num = chs->params.num_channels;
2312 chs->c = kcalloc(chs->num, sizeof(struct mlx5e_channel *), GFP_KERNEL);
2313 cparam = kvzalloc(sizeof(struct mlx5e_channel_param), GFP_KERNEL);
2314 if (!chs->c || !cparam)
2317 err = mlx5e_build_channel_param(priv->mdev, &chs->params, priv->q_counter, cparam);
2321 for (i = 0; i < chs->num; i++) {
2322 struct xsk_buff_pool *xsk_pool = NULL;
2324 if (chs->params.xdp_prog)
2325 xsk_pool = mlx5e_xsk_get_pool(&chs->params, chs->params.xsk, i);
2327 err = mlx5e_open_channel(priv, i, &chs->params, cparam, xsk_pool, &chs->c[i]);
2329 goto err_close_channels;
2332 if (MLX5E_GET_PFLAG(&chs->params, MLX5E_PFLAG_TX_PORT_TS) || chs->params.ptp_rx) {
2333 err = mlx5e_ptp_open(priv, &chs->params, chs->c[0]->lag_port, &chs->ptp);
2335 goto err_close_channels;
2338 err = mlx5e_qos_open_queues(priv, chs);
2342 mlx5e_health_channels_update(priv);
2348 mlx5e_ptp_close(chs->ptp);
2351 for (i--; i >= 0; i--)
2352 mlx5e_close_channel(chs->c[i]);
2361 static void mlx5e_activate_channels(struct mlx5e_channels *chs)
2365 for (i = 0; i < chs->num; i++)
2366 mlx5e_activate_channel(chs->c[i]);
2369 mlx5e_ptp_activate_channel(chs->ptp);
2372 #define MLX5E_RQ_WQES_TIMEOUT 20000 /* msecs */
2374 static int mlx5e_wait_channels_min_rx_wqes(struct mlx5e_channels *chs)
2379 for (i = 0; i < chs->num; i++) {
2380 int timeout = err ? 0 : MLX5E_RQ_WQES_TIMEOUT;
2382 err |= mlx5e_wait_for_min_rx_wqes(&chs->c[i]->rq, timeout);
2384 /* Don't wait on the XSK RQ, because the newer xdpsock sample
2385 * doesn't provide any Fill Ring entries at the setup stage.
2389 return err ? -ETIMEDOUT : 0;
2392 static void mlx5e_deactivate_channels(struct mlx5e_channels *chs)
2397 mlx5e_ptp_deactivate_channel(chs->ptp);
2399 for (i = 0; i < chs->num; i++)
2400 mlx5e_deactivate_channel(chs->c[i]);
2403 void mlx5e_close_channels(struct mlx5e_channels *chs)
2408 mlx5e_ptp_close(chs->ptp);
2411 for (i = 0; i < chs->num; i++)
2412 mlx5e_close_channel(chs->c[i]);
2418 static int mlx5e_modify_tirs_packet_merge(struct mlx5e_priv *priv)
2420 struct mlx5e_rx_res *res = priv->rx_res;
2422 return mlx5e_rx_res_packet_merge_set_param(res, &priv->channels.params.packet_merge);
2425 static MLX5E_DEFINE_PREACTIVATE_WRAPPER_CTX(mlx5e_modify_tirs_packet_merge);
2427 static int mlx5e_set_mtu(struct mlx5_core_dev *mdev,
2428 struct mlx5e_params *params, u16 mtu)
2430 u16 hw_mtu = MLX5E_SW2HW_MTU(params, mtu);
2433 err = mlx5_set_port_mtu(mdev, hw_mtu, 1);
2437 /* Update vport context MTU */
2438 mlx5_modify_nic_vport_mtu(mdev, hw_mtu);
2442 static void mlx5e_query_mtu(struct mlx5_core_dev *mdev,
2443 struct mlx5e_params *params, u16 *mtu)
2448 err = mlx5_query_nic_vport_mtu(mdev, &hw_mtu);
2449 if (err || !hw_mtu) /* fallback to port oper mtu */
2450 mlx5_query_port_oper_mtu(mdev, &hw_mtu, 1);
2452 *mtu = MLX5E_HW2SW_MTU(params, hw_mtu);
2455 int mlx5e_set_dev_port_mtu(struct mlx5e_priv *priv)
2457 struct mlx5e_params *params = &priv->channels.params;
2458 struct net_device *netdev = priv->netdev;
2459 struct mlx5_core_dev *mdev = priv->mdev;
2463 err = mlx5e_set_mtu(mdev, params, params->sw_mtu);
2467 mlx5e_query_mtu(mdev, params, &mtu);
2468 if (mtu != params->sw_mtu)
2469 netdev_warn(netdev, "%s: VPort MTU %d is different than netdev mtu %d\n",
2470 __func__, mtu, params->sw_mtu);
2472 params->sw_mtu = mtu;
2476 MLX5E_DEFINE_PREACTIVATE_WRAPPER_CTX(mlx5e_set_dev_port_mtu);
2478 void mlx5e_set_netdev_mtu_boundaries(struct mlx5e_priv *priv)
2480 struct mlx5e_params *params = &priv->channels.params;
2481 struct net_device *netdev = priv->netdev;
2482 struct mlx5_core_dev *mdev = priv->mdev;
2485 /* MTU range: 68 - hw-specific max */
2486 netdev->min_mtu = ETH_MIN_MTU;
2488 mlx5_query_port_max_mtu(mdev, &max_mtu, 1);
2489 netdev->max_mtu = min_t(unsigned int, MLX5E_HW2SW_MTU(params, max_mtu),
2493 static int mlx5e_netdev_set_tcs(struct net_device *netdev, u16 nch, u8 ntc,
2494 struct netdev_tc_txq *tc_to_txq)
2498 netdev_reset_tc(netdev);
2503 err = netdev_set_num_tc(netdev, ntc);
2505 netdev_WARN(netdev, "netdev_set_num_tc failed (%d), ntc = %d\n", err, ntc);
2509 for (tc = 0; tc < ntc; tc++) {
2512 count = tc_to_txq[tc].count;
2513 offset = tc_to_txq[tc].offset;
2514 netdev_set_tc_queue(netdev, tc, count, offset);
2520 int mlx5e_update_tx_netdev_queues(struct mlx5e_priv *priv)
2522 int qos_queues, nch, ntc, num_txqs, err;
2524 qos_queues = mlx5e_qos_cur_leaf_nodes(priv);
2526 nch = priv->channels.params.num_channels;
2527 ntc = mlx5e_get_dcb_num_tc(&priv->channels.params);
2528 num_txqs = nch * ntc + qos_queues;
2529 if (MLX5E_GET_PFLAG(&priv->channels.params, MLX5E_PFLAG_TX_PORT_TS))
2532 mlx5e_dbg(DRV, priv, "Setting num_txqs %d\n", num_txqs);
2533 err = netif_set_real_num_tx_queues(priv->netdev, num_txqs);
2535 netdev_warn(priv->netdev, "netif_set_real_num_tx_queues failed, %d\n", err);
2540 static int mlx5e_update_netdev_queues(struct mlx5e_priv *priv)
2542 struct netdev_tc_txq old_tc_to_txq[TC_MAX_QUEUE], *tc_to_txq;
2543 struct net_device *netdev = priv->netdev;
2544 int old_num_txqs, old_ntc;
2545 int num_rxqs, nch, ntc;
2549 old_num_txqs = netdev->real_num_tx_queues;
2550 old_ntc = netdev->num_tc ? : 1;
2551 for (i = 0; i < ARRAY_SIZE(old_tc_to_txq); i++)
2552 old_tc_to_txq[i] = netdev->tc_to_txq[i];
2554 nch = priv->channels.params.num_channels;
2555 ntc = priv->channels.params.mqprio.num_tc;
2556 num_rxqs = nch * priv->profile->rq_groups;
2557 tc_to_txq = priv->channels.params.mqprio.tc_to_txq;
2559 err = mlx5e_netdev_set_tcs(netdev, nch, ntc, tc_to_txq);
2562 err = mlx5e_update_tx_netdev_queues(priv);
2565 err = netif_set_real_num_rx_queues(netdev, num_rxqs);
2567 netdev_warn(netdev, "netif_set_real_num_rx_queues failed, %d\n", err);
2570 if (priv->mqprio_rl != priv->channels.params.mqprio.channel.rl) {
2571 if (priv->mqprio_rl) {
2572 mlx5e_mqprio_rl_cleanup(priv->mqprio_rl);
2573 mlx5e_mqprio_rl_free(priv->mqprio_rl);
2575 priv->mqprio_rl = priv->channels.params.mqprio.channel.rl;
2581 /* netif_set_real_num_rx_queues could fail only when nch increased. Only
2582 * one of nch and ntc is changed in this function. That means, the call
2583 * to netif_set_real_num_tx_queues below should not fail, because it
2584 * decreases the number of TX queues.
2586 WARN_ON_ONCE(netif_set_real_num_tx_queues(netdev, old_num_txqs));
2589 WARN_ON_ONCE(mlx5e_netdev_set_tcs(netdev, old_num_txqs / old_ntc, old_ntc,
2595 static MLX5E_DEFINE_PREACTIVATE_WRAPPER_CTX(mlx5e_update_netdev_queues);
2597 static void mlx5e_set_default_xps_cpumasks(struct mlx5e_priv *priv,
2598 struct mlx5e_params *params)
2600 struct mlx5_core_dev *mdev = priv->mdev;
2601 int num_comp_vectors, ix, irq;
2603 num_comp_vectors = mlx5_comp_vectors_count(mdev);
2605 for (ix = 0; ix < params->num_channels; ix++) {
2606 cpumask_clear(priv->scratchpad.cpumask);
2608 for (irq = ix; irq < num_comp_vectors; irq += params->num_channels) {
2609 int cpu = cpumask_first(mlx5_comp_irq_get_affinity_mask(mdev, irq));
2611 cpumask_set_cpu(cpu, priv->scratchpad.cpumask);
2614 netif_set_xps_queue(priv->netdev, priv->scratchpad.cpumask, ix);
2618 int mlx5e_num_channels_changed(struct mlx5e_priv *priv)
2620 u16 count = priv->channels.params.num_channels;
2623 err = mlx5e_update_netdev_queues(priv);
2627 mlx5e_set_default_xps_cpumasks(priv, &priv->channels.params);
2629 /* This function may be called on attach, before priv->rx_res is created. */
2630 if (!netif_is_rxfh_configured(priv->netdev) && priv->rx_res)
2631 mlx5e_rx_res_rss_set_indir_uniform(priv->rx_res, count);
2636 MLX5E_DEFINE_PREACTIVATE_WRAPPER_CTX(mlx5e_num_channels_changed);
2638 static void mlx5e_build_txq_maps(struct mlx5e_priv *priv)
2640 int i, ch, tc, num_tc;
2642 ch = priv->channels.num;
2643 num_tc = mlx5e_get_dcb_num_tc(&priv->channels.params);
2645 for (i = 0; i < ch; i++) {
2646 for (tc = 0; tc < num_tc; tc++) {
2647 struct mlx5e_channel *c = priv->channels.c[i];
2648 struct mlx5e_txqsq *sq = &c->sq[tc];
2650 priv->txq2sq[sq->txq_ix] = sq;
2651 priv->channel_tc2realtxq[i][tc] = i + tc * ch;
2655 if (!priv->channels.ptp)
2658 if (!test_bit(MLX5E_PTP_STATE_TX, priv->channels.ptp->state))
2661 for (tc = 0; tc < num_tc; tc++) {
2662 struct mlx5e_ptp *c = priv->channels.ptp;
2663 struct mlx5e_txqsq *sq = &c->ptpsq[tc].txqsq;
2665 priv->txq2sq[sq->txq_ix] = sq;
2666 priv->port_ptp_tc2realtxq[tc] = priv->num_tc_x_num_ch + tc;
2670 static void mlx5e_update_num_tc_x_num_ch(struct mlx5e_priv *priv)
2672 /* Sync with mlx5e_select_queue. */
2673 WRITE_ONCE(priv->num_tc_x_num_ch,
2674 mlx5e_get_dcb_num_tc(&priv->channels.params) * priv->channels.num);
2677 void mlx5e_activate_priv_channels(struct mlx5e_priv *priv)
2679 mlx5e_update_num_tc_x_num_ch(priv);
2680 mlx5e_build_txq_maps(priv);
2681 mlx5e_activate_channels(&priv->channels);
2682 mlx5e_qos_activate_queues(priv);
2683 mlx5e_xdp_tx_enable(priv);
2684 netif_tx_start_all_queues(priv->netdev);
2686 if (mlx5e_is_vport_rep(priv))
2687 mlx5e_add_sqs_fwd_rules(priv);
2689 mlx5e_wait_channels_min_rx_wqes(&priv->channels);
2692 mlx5e_rx_res_channels_activate(priv->rx_res, &priv->channels);
2695 void mlx5e_deactivate_priv_channels(struct mlx5e_priv *priv)
2698 mlx5e_rx_res_channels_deactivate(priv->rx_res);
2700 if (mlx5e_is_vport_rep(priv))
2701 mlx5e_remove_sqs_fwd_rules(priv);
2703 /* FIXME: This is a W/A only for tx timeout watch dog false alarm when
2704 * polling for inactive tx queues.
2706 netif_tx_stop_all_queues(priv->netdev);
2707 netif_tx_disable(priv->netdev);
2708 mlx5e_xdp_tx_disable(priv);
2709 mlx5e_deactivate_channels(&priv->channels);
2712 static int mlx5e_switch_priv_params(struct mlx5e_priv *priv,
2713 struct mlx5e_params *new_params,
2714 mlx5e_fp_preactivate preactivate,
2717 struct mlx5e_params old_params;
2719 old_params = priv->channels.params;
2720 priv->channels.params = *new_params;
2725 err = preactivate(priv, context);
2727 priv->channels.params = old_params;
2735 static int mlx5e_switch_priv_channels(struct mlx5e_priv *priv,
2736 struct mlx5e_channels *new_chs,
2737 mlx5e_fp_preactivate preactivate,
2740 struct net_device *netdev = priv->netdev;
2741 struct mlx5e_channels old_chs;
2745 carrier_ok = netif_carrier_ok(netdev);
2746 netif_carrier_off(netdev);
2748 mlx5e_deactivate_priv_channels(priv);
2750 old_chs = priv->channels;
2751 priv->channels = *new_chs;
2753 /* New channels are ready to roll, call the preactivate hook if needed
2754 * to modify HW settings or update kernel parameters.
2757 err = preactivate(priv, context);
2759 priv->channels = old_chs;
2764 mlx5e_close_channels(&old_chs);
2765 priv->profile->update_rx(priv);
2768 mlx5e_activate_priv_channels(priv);
2770 /* return carrier back if needed */
2772 netif_carrier_on(netdev);
2777 int mlx5e_safe_switch_params(struct mlx5e_priv *priv,
2778 struct mlx5e_params *params,
2779 mlx5e_fp_preactivate preactivate,
2780 void *context, bool reset)
2782 struct mlx5e_channels new_chs = {};
2785 reset &= test_bit(MLX5E_STATE_OPENED, &priv->state);
2787 return mlx5e_switch_priv_params(priv, params, preactivate, context);
2789 new_chs.params = *params;
2790 err = mlx5e_open_channels(priv, &new_chs);
2793 err = mlx5e_switch_priv_channels(priv, &new_chs, preactivate, context);
2795 mlx5e_close_channels(&new_chs);
2800 int mlx5e_safe_reopen_channels(struct mlx5e_priv *priv)
2802 return mlx5e_safe_switch_params(priv, &priv->channels.params, NULL, NULL, true);
2805 void mlx5e_timestamp_init(struct mlx5e_priv *priv)
2807 priv->tstamp.tx_type = HWTSTAMP_TX_OFF;
2808 priv->tstamp.rx_filter = HWTSTAMP_FILTER_NONE;
2811 static void mlx5e_modify_admin_state(struct mlx5_core_dev *mdev,
2812 enum mlx5_port_status state)
2814 struct mlx5_eswitch *esw = mdev->priv.eswitch;
2815 int vport_admin_state;
2817 mlx5_set_port_admin_status(mdev, state);
2819 if (mlx5_eswitch_mode(mdev) == MLX5_ESWITCH_OFFLOADS ||
2820 !MLX5_CAP_GEN(mdev, uplink_follow))
2823 if (state == MLX5_PORT_UP)
2824 vport_admin_state = MLX5_VPORT_ADMIN_STATE_AUTO;
2826 vport_admin_state = MLX5_VPORT_ADMIN_STATE_DOWN;
2828 mlx5_eswitch_set_vport_state(esw, MLX5_VPORT_UPLINK, vport_admin_state);
2831 int mlx5e_open_locked(struct net_device *netdev)
2833 struct mlx5e_priv *priv = netdev_priv(netdev);
2836 set_bit(MLX5E_STATE_OPENED, &priv->state);
2838 err = mlx5e_open_channels(priv, &priv->channels);
2840 goto err_clear_state_opened_flag;
2842 priv->profile->update_rx(priv);
2843 mlx5e_activate_priv_channels(priv);
2844 mlx5e_apply_traps(priv, true);
2845 if (priv->profile->update_carrier)
2846 priv->profile->update_carrier(priv);
2848 mlx5e_queue_update_stats(priv);
2851 err_clear_state_opened_flag:
2852 clear_bit(MLX5E_STATE_OPENED, &priv->state);
2856 int mlx5e_open(struct net_device *netdev)
2858 struct mlx5e_priv *priv = netdev_priv(netdev);
2861 mutex_lock(&priv->state_lock);
2862 err = mlx5e_open_locked(netdev);
2864 mlx5e_modify_admin_state(priv->mdev, MLX5_PORT_UP);
2865 mutex_unlock(&priv->state_lock);
2870 int mlx5e_close_locked(struct net_device *netdev)
2872 struct mlx5e_priv *priv = netdev_priv(netdev);
2874 /* May already be CLOSED in case a previous configuration operation
2875 * (e.g RX/TX queue size change) that involves close&open failed.
2877 if (!test_bit(MLX5E_STATE_OPENED, &priv->state))
2880 mlx5e_apply_traps(priv, false);
2881 clear_bit(MLX5E_STATE_OPENED, &priv->state);
2883 netif_carrier_off(priv->netdev);
2884 mlx5e_deactivate_priv_channels(priv);
2885 mlx5e_close_channels(&priv->channels);
2890 int mlx5e_close(struct net_device *netdev)
2892 struct mlx5e_priv *priv = netdev_priv(netdev);
2895 if (!netif_device_present(netdev))
2898 mutex_lock(&priv->state_lock);
2899 mlx5e_modify_admin_state(priv->mdev, MLX5_PORT_DOWN);
2900 err = mlx5e_close_locked(netdev);
2901 mutex_unlock(&priv->state_lock);
2906 static void mlx5e_free_drop_rq(struct mlx5e_rq *rq)
2908 mlx5_wq_destroy(&rq->wq_ctrl);
2911 static int mlx5e_alloc_drop_rq(struct mlx5_core_dev *mdev,
2912 struct mlx5e_rq *rq,
2913 struct mlx5e_rq_param *param)
2915 void *rqc = param->rqc;
2916 void *rqc_wq = MLX5_ADDR_OF(rqc, rqc, wq);
2919 param->wq.db_numa_node = param->wq.buf_numa_node;
2921 err = mlx5_wq_cyc_create(mdev, ¶m->wq, rqc_wq, &rq->wqe.wq,
2926 /* Mark as unused given "Drop-RQ" packets never reach XDP */
2927 xdp_rxq_info_unused(&rq->xdp_rxq);
2934 static int mlx5e_alloc_drop_cq(struct mlx5e_priv *priv,
2935 struct mlx5e_cq *cq,
2936 struct mlx5e_cq_param *param)
2938 struct mlx5_core_dev *mdev = priv->mdev;
2940 param->wq.buf_numa_node = dev_to_node(mlx5_core_dma_dev(mdev));
2941 param->wq.db_numa_node = dev_to_node(mlx5_core_dma_dev(mdev));
2943 return mlx5e_alloc_cq_common(priv, param, cq);
2946 int mlx5e_open_drop_rq(struct mlx5e_priv *priv,
2947 struct mlx5e_rq *drop_rq)
2949 struct mlx5_core_dev *mdev = priv->mdev;
2950 struct mlx5e_cq_param cq_param = {};
2951 struct mlx5e_rq_param rq_param = {};
2952 struct mlx5e_cq *cq = &drop_rq->cq;
2955 mlx5e_build_drop_rq_param(mdev, priv->drop_rq_q_counter, &rq_param);
2957 err = mlx5e_alloc_drop_cq(priv, cq, &cq_param);
2961 err = mlx5e_create_cq(cq, &cq_param);
2965 err = mlx5e_alloc_drop_rq(mdev, drop_rq, &rq_param);
2967 goto err_destroy_cq;
2969 err = mlx5e_create_rq(drop_rq, &rq_param);
2973 err = mlx5e_modify_rq_state(drop_rq, MLX5_RQC_STATE_RST, MLX5_RQC_STATE_RDY);
2975 mlx5_core_warn(priv->mdev, "modify_rq_state failed, rx_if_down_packets won't be counted %d\n", err);
2980 mlx5e_free_drop_rq(drop_rq);
2983 mlx5e_destroy_cq(cq);
2991 void mlx5e_close_drop_rq(struct mlx5e_rq *drop_rq)
2993 mlx5e_destroy_rq(drop_rq);
2994 mlx5e_free_drop_rq(drop_rq);
2995 mlx5e_destroy_cq(&drop_rq->cq);
2996 mlx5e_free_cq(&drop_rq->cq);
2999 int mlx5e_create_tis(struct mlx5_core_dev *mdev, void *in, u32 *tisn)
3001 void *tisc = MLX5_ADDR_OF(create_tis_in, in, ctx);
3003 MLX5_SET(tisc, tisc, transport_domain, mdev->mlx5e_res.hw_objs.td.tdn);
3005 if (MLX5_GET(tisc, tisc, tls_en))
3006 MLX5_SET(tisc, tisc, pd, mdev->mlx5e_res.hw_objs.pdn);
3008 if (mlx5_lag_is_lacp_owner(mdev))
3009 MLX5_SET(tisc, tisc, strict_lag_tx_port_affinity, 1);
3011 return mlx5_core_create_tis(mdev, in, tisn);
3014 void mlx5e_destroy_tis(struct mlx5_core_dev *mdev, u32 tisn)
3016 mlx5_core_destroy_tis(mdev, tisn);
3019 void mlx5e_destroy_tises(struct mlx5e_priv *priv)
3023 for (i = 0; i < mlx5e_get_num_lag_ports(priv->mdev); i++)
3024 for (tc = 0; tc < priv->profile->max_tc; tc++)
3025 mlx5e_destroy_tis(priv->mdev, priv->tisn[i][tc]);
3028 static bool mlx5e_lag_should_assign_affinity(struct mlx5_core_dev *mdev)
3030 return MLX5_CAP_GEN(mdev, lag_tx_port_affinity) && mlx5e_get_num_lag_ports(mdev) > 1;
3033 int mlx5e_create_tises(struct mlx5e_priv *priv)
3038 for (i = 0; i < mlx5e_get_num_lag_ports(priv->mdev); i++) {
3039 for (tc = 0; tc < priv->profile->max_tc; tc++) {
3040 u32 in[MLX5_ST_SZ_DW(create_tis_in)] = {};
3043 tisc = MLX5_ADDR_OF(create_tis_in, in, ctx);
3045 MLX5_SET(tisc, tisc, prio, tc << 1);
3047 if (mlx5e_lag_should_assign_affinity(priv->mdev))
3048 MLX5_SET(tisc, tisc, lag_tx_port_affinity, i + 1);
3050 err = mlx5e_create_tis(priv->mdev, in, &priv->tisn[i][tc]);
3052 goto err_close_tises;
3059 for (; i >= 0; i--) {
3060 for (tc--; tc >= 0; tc--)
3061 mlx5e_destroy_tis(priv->mdev, priv->tisn[i][tc]);
3062 tc = priv->profile->max_tc;
3068 static void mlx5e_cleanup_nic_tx(struct mlx5e_priv *priv)
3070 mlx5e_destroy_tises(priv);
3073 static int mlx5e_modify_channels_scatter_fcs(struct mlx5e_channels *chs, bool enable)
3078 for (i = 0; i < chs->num; i++) {
3079 err = mlx5e_modify_rq_scatter_fcs(&chs->c[i]->rq, enable);
3087 static int mlx5e_modify_channels_vsd(struct mlx5e_channels *chs, bool vsd)
3092 for (i = 0; i < chs->num; i++) {
3093 err = mlx5e_modify_rq_vsd(&chs->c[i]->rq, vsd);
3097 if (chs->ptp && test_bit(MLX5E_PTP_STATE_RX, chs->ptp->state))
3098 return mlx5e_modify_rq_vsd(&chs->ptp->rq, vsd);
3103 static void mlx5e_mqprio_build_default_tc_to_txq(struct netdev_tc_txq *tc_to_txq,
3108 memset(tc_to_txq, 0, sizeof(*tc_to_txq) * TC_MAX_QUEUE);
3110 /* Map netdev TCs to offset 0.
3111 * We have our own UP to TXQ mapping for DCB mode of QoS
3113 for (tc = 0; tc < ntc; tc++) {
3114 tc_to_txq[tc] = (struct netdev_tc_txq) {
3121 static void mlx5e_mqprio_build_tc_to_txq(struct netdev_tc_txq *tc_to_txq,
3122 struct tc_mqprio_qopt *qopt)
3126 for (tc = 0; tc < TC_MAX_QUEUE; tc++) {
3127 tc_to_txq[tc] = (struct netdev_tc_txq) {
3128 .count = qopt->count[tc],
3129 .offset = qopt->offset[tc],
3134 static void mlx5e_params_mqprio_dcb_set(struct mlx5e_params *params, u8 num_tc)
3136 params->mqprio.mode = TC_MQPRIO_MODE_DCB;
3137 params->mqprio.num_tc = num_tc;
3138 params->mqprio.channel.rl = NULL;
3139 mlx5e_mqprio_build_default_tc_to_txq(params->mqprio.tc_to_txq, num_tc,
3140 params->num_channels);
3143 static void mlx5e_params_mqprio_channel_set(struct mlx5e_params *params,
3144 struct tc_mqprio_qopt *qopt,
3145 struct mlx5e_mqprio_rl *rl)
3147 params->mqprio.mode = TC_MQPRIO_MODE_CHANNEL;
3148 params->mqprio.num_tc = qopt->num_tc;
3149 params->mqprio.channel.rl = rl;
3150 mlx5e_mqprio_build_tc_to_txq(params->mqprio.tc_to_txq, qopt);
3153 static void mlx5e_params_mqprio_reset(struct mlx5e_params *params)
3155 mlx5e_params_mqprio_dcb_set(params, 1);
3158 static int mlx5e_setup_tc_mqprio_dcb(struct mlx5e_priv *priv,
3159 struct tc_mqprio_qopt *mqprio)
3161 struct mlx5e_params new_params;
3162 u8 tc = mqprio->num_tc;
3165 mqprio->hw = TC_MQPRIO_HW_OFFLOAD_TCS;
3167 if (tc && tc != MLX5E_MAX_NUM_TC)
3170 new_params = priv->channels.params;
3171 mlx5e_params_mqprio_dcb_set(&new_params, tc ? tc : 1);
3173 err = mlx5e_safe_switch_params(priv, &new_params,
3174 mlx5e_num_channels_changed_ctx, NULL, true);
3176 priv->max_opened_tc = max_t(u8, priv->max_opened_tc,
3177 mlx5e_get_dcb_num_tc(&priv->channels.params));
3181 static int mlx5e_mqprio_channel_validate(struct mlx5e_priv *priv,
3182 struct tc_mqprio_qopt_offload *mqprio)
3184 struct net_device *netdev = priv->netdev;
3185 struct mlx5e_ptp *ptp_channel;
3189 ptp_channel = priv->channels.ptp;
3190 if (ptp_channel && test_bit(MLX5E_PTP_STATE_TX, ptp_channel->state)) {
3192 "Cannot activate MQPRIO mode channel since it conflicts with TX port TS\n");
3196 if (mqprio->qopt.offset[0] != 0 || mqprio->qopt.num_tc < 1 ||
3197 mqprio->qopt.num_tc > MLX5E_MAX_NUM_MQPRIO_CH_TC)
3200 for (i = 0; i < mqprio->qopt.num_tc; i++) {
3201 if (!mqprio->qopt.count[i]) {
3202 netdev_err(netdev, "Zero size for queue-group (%d) is not supported\n", i);
3205 if (mqprio->min_rate[i]) {
3206 netdev_err(netdev, "Min tx rate is not supported\n");
3210 if (mqprio->max_rate[i]) {
3213 err = mlx5e_qos_bytes_rate_check(priv->mdev, mqprio->max_rate[i]);
3218 if (mqprio->qopt.offset[i] != agg_count) {
3219 netdev_err(netdev, "Discontinuous queues config is not supported\n");
3222 agg_count += mqprio->qopt.count[i];
3225 if (priv->channels.params.num_channels != agg_count) {
3226 netdev_err(netdev, "Num of queues (%d) does not match available (%d)\n",
3227 agg_count, priv->channels.params.num_channels);
3234 static bool mlx5e_mqprio_rate_limit(struct tc_mqprio_qopt_offload *mqprio)
3238 for (tc = 0; tc < mqprio->qopt.num_tc; tc++)
3239 if (mqprio->max_rate[tc])
3244 static int mlx5e_setup_tc_mqprio_channel(struct mlx5e_priv *priv,
3245 struct tc_mqprio_qopt_offload *mqprio)
3247 mlx5e_fp_preactivate preactivate;
3248 struct mlx5e_params new_params;
3249 struct mlx5e_mqprio_rl *rl;
3253 err = mlx5e_mqprio_channel_validate(priv, mqprio);
3258 if (mlx5e_mqprio_rate_limit(mqprio)) {
3259 rl = mlx5e_mqprio_rl_alloc();
3262 err = mlx5e_mqprio_rl_init(rl, priv->mdev, mqprio->qopt.num_tc,
3265 mlx5e_mqprio_rl_free(rl);
3270 new_params = priv->channels.params;
3271 mlx5e_params_mqprio_channel_set(&new_params, &mqprio->qopt, rl);
3273 nch_changed = mlx5e_get_dcb_num_tc(&priv->channels.params) > 1;
3274 preactivate = nch_changed ? mlx5e_num_channels_changed_ctx :
3275 mlx5e_update_netdev_queues_ctx;
3276 err = mlx5e_safe_switch_params(priv, &new_params, preactivate, NULL, true);
3278 mlx5e_mqprio_rl_cleanup(rl);
3279 mlx5e_mqprio_rl_free(rl);
3285 static int mlx5e_setup_tc_mqprio(struct mlx5e_priv *priv,
3286 struct tc_mqprio_qopt_offload *mqprio)
3288 /* MQPRIO is another toplevel qdisc that can't be attached
3289 * simultaneously with the offloaded HTB.
3291 if (WARN_ON(priv->htb.maj_id))
3294 switch (mqprio->mode) {
3295 case TC_MQPRIO_MODE_DCB:
3296 return mlx5e_setup_tc_mqprio_dcb(priv, &mqprio->qopt);
3297 case TC_MQPRIO_MODE_CHANNEL:
3298 return mlx5e_setup_tc_mqprio_channel(priv, mqprio);
3304 static int mlx5e_setup_tc_htb(struct mlx5e_priv *priv, struct tc_htb_qopt_offload *htb)
3308 switch (htb->command) {
3310 return mlx5e_htb_root_add(priv, htb->parent_classid, htb->classid,
3312 case TC_HTB_DESTROY:
3313 return mlx5e_htb_root_del(priv);
3314 case TC_HTB_LEAF_ALLOC_QUEUE:
3315 res = mlx5e_htb_leaf_alloc_queue(priv, htb->classid, htb->parent_classid,
3316 htb->rate, htb->ceil, htb->extack);
3321 case TC_HTB_LEAF_TO_INNER:
3322 return mlx5e_htb_leaf_to_inner(priv, htb->parent_classid, htb->classid,
3323 htb->rate, htb->ceil, htb->extack);
3324 case TC_HTB_LEAF_DEL:
3325 return mlx5e_htb_leaf_del(priv, &htb->classid, htb->extack);
3326 case TC_HTB_LEAF_DEL_LAST:
3327 case TC_HTB_LEAF_DEL_LAST_FORCE:
3328 return mlx5e_htb_leaf_del_last(priv, htb->classid,
3329 htb->command == TC_HTB_LEAF_DEL_LAST_FORCE,
3331 case TC_HTB_NODE_MODIFY:
3332 return mlx5e_htb_node_modify(priv, htb->classid, htb->rate, htb->ceil,
3334 case TC_HTB_LEAF_QUERY_QUEUE:
3335 res = mlx5e_get_txq_by_classid(priv, htb->classid);
3345 static LIST_HEAD(mlx5e_block_cb_list);
3347 static int mlx5e_setup_tc(struct net_device *dev, enum tc_setup_type type,
3350 struct mlx5e_priv *priv = netdev_priv(dev);
3351 bool tc_unbind = false;
3354 if (type == TC_SETUP_BLOCK &&
3355 ((struct flow_block_offload *)type_data)->command == FLOW_BLOCK_UNBIND)
3358 if (!netif_device_present(dev) && !tc_unbind)
3362 case TC_SETUP_BLOCK: {
3363 struct flow_block_offload *f = type_data;
3365 f->unlocked_driver_cb = true;
3366 return flow_block_cb_setup_simple(type_data,
3367 &mlx5e_block_cb_list,
3368 mlx5e_setup_tc_block_cb,
3371 case TC_SETUP_QDISC_MQPRIO:
3372 mutex_lock(&priv->state_lock);
3373 err = mlx5e_setup_tc_mqprio(priv, type_data);
3374 mutex_unlock(&priv->state_lock);
3376 case TC_SETUP_QDISC_HTB:
3377 mutex_lock(&priv->state_lock);
3378 err = mlx5e_setup_tc_htb(priv, type_data);
3379 mutex_unlock(&priv->state_lock);
3386 void mlx5e_fold_sw_stats64(struct mlx5e_priv *priv, struct rtnl_link_stats64 *s)
3390 for (i = 0; i < priv->stats_nch; i++) {
3391 struct mlx5e_channel_stats *channel_stats = &priv->channel_stats[i];
3392 struct mlx5e_rq_stats *xskrq_stats = &channel_stats->xskrq;
3393 struct mlx5e_rq_stats *rq_stats = &channel_stats->rq;
3396 s->rx_packets += rq_stats->packets + xskrq_stats->packets;
3397 s->rx_bytes += rq_stats->bytes + xskrq_stats->bytes;
3398 s->multicast += rq_stats->mcast_packets + xskrq_stats->mcast_packets;
3400 for (j = 0; j < priv->max_opened_tc; j++) {
3401 struct mlx5e_sq_stats *sq_stats = &channel_stats->sq[j];
3403 s->tx_packets += sq_stats->packets;
3404 s->tx_bytes += sq_stats->bytes;
3405 s->tx_dropped += sq_stats->dropped;
3408 if (priv->tx_ptp_opened) {
3409 for (i = 0; i < priv->max_opened_tc; i++) {
3410 struct mlx5e_sq_stats *sq_stats = &priv->ptp_stats.sq[i];
3412 s->tx_packets += sq_stats->packets;
3413 s->tx_bytes += sq_stats->bytes;
3414 s->tx_dropped += sq_stats->dropped;
3417 if (priv->rx_ptp_opened) {
3418 struct mlx5e_rq_stats *rq_stats = &priv->ptp_stats.rq;
3420 s->rx_packets += rq_stats->packets;
3421 s->rx_bytes += rq_stats->bytes;
3422 s->multicast += rq_stats->mcast_packets;
3427 mlx5e_get_stats(struct net_device *dev, struct rtnl_link_stats64 *stats)
3429 struct mlx5e_priv *priv = netdev_priv(dev);
3430 struct mlx5e_pport_stats *pstats = &priv->stats.pport;
3432 if (!netif_device_present(dev))
3435 /* In switchdev mode, monitor counters doesn't monitor
3436 * rx/tx stats of 802_3. The update stats mechanism
3437 * should keep the 802_3 layout counters updated
3439 if (!mlx5e_monitor_counter_supported(priv) ||
3440 mlx5e_is_uplink_rep(priv)) {
3441 /* update HW stats in background for next time */
3442 mlx5e_queue_update_stats(priv);
3445 if (mlx5e_is_uplink_rep(priv)) {
3446 struct mlx5e_vport_stats *vstats = &priv->stats.vport;
3448 stats->rx_packets = PPORT_802_3_GET(pstats, a_frames_received_ok);
3449 stats->rx_bytes = PPORT_802_3_GET(pstats, a_octets_received_ok);
3450 stats->tx_packets = PPORT_802_3_GET(pstats, a_frames_transmitted_ok);
3451 stats->tx_bytes = PPORT_802_3_GET(pstats, a_octets_transmitted_ok);
3453 /* vport multicast also counts packets that are dropped due to steering
3454 * or rx out of buffer
3456 stats->multicast = VPORT_COUNTER_GET(vstats, received_eth_multicast.packets);
3458 mlx5e_fold_sw_stats64(priv, stats);
3461 stats->rx_dropped = priv->stats.qcnt.rx_out_of_buffer;
3463 stats->rx_length_errors =
3464 PPORT_802_3_GET(pstats, a_in_range_length_errors) +
3465 PPORT_802_3_GET(pstats, a_out_of_range_length_field) +
3466 PPORT_802_3_GET(pstats, a_frame_too_long_errors);
3467 stats->rx_crc_errors =
3468 PPORT_802_3_GET(pstats, a_frame_check_sequence_errors);
3469 stats->rx_frame_errors = PPORT_802_3_GET(pstats, a_alignment_errors);
3470 stats->tx_aborted_errors = PPORT_2863_GET(pstats, if_out_discards);
3471 stats->rx_errors = stats->rx_length_errors + stats->rx_crc_errors +
3472 stats->rx_frame_errors;
3473 stats->tx_errors = stats->tx_aborted_errors + stats->tx_carrier_errors;
3476 static void mlx5e_nic_set_rx_mode(struct mlx5e_priv *priv)
3478 if (mlx5e_is_uplink_rep(priv))
3479 return; /* no rx mode for uplink rep */
3481 queue_work(priv->wq, &priv->set_rx_mode_work);
3484 static void mlx5e_set_rx_mode(struct net_device *dev)
3486 struct mlx5e_priv *priv = netdev_priv(dev);
3488 mlx5e_nic_set_rx_mode(priv);
3491 static int mlx5e_set_mac(struct net_device *netdev, void *addr)
3493 struct mlx5e_priv *priv = netdev_priv(netdev);
3494 struct sockaddr *saddr = addr;
3496 if (!is_valid_ether_addr(saddr->sa_data))
3497 return -EADDRNOTAVAIL;
3499 netif_addr_lock_bh(netdev);
3500 eth_hw_addr_set(netdev, saddr->sa_data);
3501 netif_addr_unlock_bh(netdev);
3503 mlx5e_nic_set_rx_mode(priv);
3508 #define MLX5E_SET_FEATURE(features, feature, enable) \
3511 *features |= feature; \
3513 *features &= ~feature; \
3516 typedef int (*mlx5e_feature_handler)(struct net_device *netdev, bool enable);
3518 static int set_feature_lro(struct net_device *netdev, bool enable)
3520 struct mlx5e_priv *priv = netdev_priv(netdev);
3521 struct mlx5_core_dev *mdev = priv->mdev;
3522 struct mlx5e_params *cur_params;
3523 struct mlx5e_params new_params;
3527 mutex_lock(&priv->state_lock);
3529 if (enable && priv->xsk.refcnt) {
3530 netdev_warn(netdev, "LRO is incompatible with AF_XDP (%u XSKs are active)\n",
3536 cur_params = &priv->channels.params;
3537 if (enable && !MLX5E_GET_PFLAG(cur_params, MLX5E_PFLAG_RX_STRIDING_RQ)) {
3538 netdev_warn(netdev, "can't set LRO with legacy RQ\n");
3543 new_params = *cur_params;
3546 new_params.packet_merge.type = MLX5E_PACKET_MERGE_LRO;
3547 else if (new_params.packet_merge.type == MLX5E_PACKET_MERGE_LRO)
3548 new_params.packet_merge.type = MLX5E_PACKET_MERGE_NONE;
3552 if (!(cur_params->packet_merge.type == MLX5E_PACKET_MERGE_SHAMPO &&
3553 new_params.packet_merge.type == MLX5E_PACKET_MERGE_LRO)) {
3554 if (cur_params->rq_wq_type == MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ) {
3555 if (mlx5e_rx_mpwqe_is_linear_skb(mdev, cur_params, NULL) ==
3556 mlx5e_rx_mpwqe_is_linear_skb(mdev, &new_params, NULL))
3561 err = mlx5e_safe_switch_params(priv, &new_params,
3562 mlx5e_modify_tirs_packet_merge_ctx, NULL, reset);
3564 mutex_unlock(&priv->state_lock);
3568 static int set_feature_hw_gro(struct net_device *netdev, bool enable)
3570 struct mlx5e_priv *priv = netdev_priv(netdev);
3571 struct mlx5e_params new_params;
3575 mutex_lock(&priv->state_lock);
3576 new_params = priv->channels.params;
3579 if (MLX5E_GET_PFLAG(&new_params, MLX5E_PFLAG_RX_CQE_COMPRESS)) {
3580 netdev_warn(netdev, "Can't set HW-GRO when CQE compress is active\n");
3584 new_params.packet_merge.type = MLX5E_PACKET_MERGE_SHAMPO;
3585 new_params.packet_merge.shampo.match_criteria_type =
3586 MLX5_RQC_SHAMPO_MATCH_CRITERIA_TYPE_EXTENDED;
3587 new_params.packet_merge.shampo.alignment_granularity =
3588 MLX5_RQC_SHAMPO_NO_MATCH_ALIGNMENT_GRANULARITY_STRIDE;
3589 } else if (new_params.packet_merge.type == MLX5E_PACKET_MERGE_SHAMPO) {
3590 new_params.packet_merge.type = MLX5E_PACKET_MERGE_NONE;
3595 err = mlx5e_safe_switch_params(priv, &new_params,
3596 mlx5e_modify_tirs_packet_merge_ctx, NULL, reset);
3598 mutex_unlock(&priv->state_lock);
3602 static int set_feature_cvlan_filter(struct net_device *netdev, bool enable)
3604 struct mlx5e_priv *priv = netdev_priv(netdev);
3607 mlx5e_enable_cvlan_filter(priv);
3609 mlx5e_disable_cvlan_filter(priv);
3614 static int set_feature_hw_tc(struct net_device *netdev, bool enable)
3616 struct mlx5e_priv *priv = netdev_priv(netdev);
3618 #if IS_ENABLED(CONFIG_MLX5_CLS_ACT)
3619 if (!enable && mlx5e_tc_num_filters(priv, MLX5_TC_FLAG(NIC_OFFLOAD))) {
3621 "Active offloaded tc filters, can't turn hw_tc_offload off\n");
3626 if (!enable && priv->htb.maj_id) {
3627 netdev_err(netdev, "Active HTB offload, can't turn hw_tc_offload off\n");
3634 static int set_feature_rx_all(struct net_device *netdev, bool enable)
3636 struct mlx5e_priv *priv = netdev_priv(netdev);
3637 struct mlx5_core_dev *mdev = priv->mdev;
3639 return mlx5_set_port_fcs(mdev, !enable);
3642 static int mlx5e_set_rx_port_ts(struct mlx5_core_dev *mdev, bool enable)
3644 u32 in[MLX5_ST_SZ_DW(pcmr_reg)] = {};
3645 bool supported, curr_state;
3648 if (!MLX5_CAP_GEN(mdev, ports_check))
3651 err = mlx5_query_ports_check(mdev, in, sizeof(in));
3655 supported = MLX5_GET(pcmr_reg, in, rx_ts_over_crc_cap);
3656 curr_state = MLX5_GET(pcmr_reg, in, rx_ts_over_crc);
3658 if (!supported || enable == curr_state)
3661 MLX5_SET(pcmr_reg, in, local_port, 1);
3662 MLX5_SET(pcmr_reg, in, rx_ts_over_crc, enable);
3664 return mlx5_set_ports_check(mdev, in, sizeof(in));
3667 static int set_feature_rx_fcs(struct net_device *netdev, bool enable)
3669 struct mlx5e_priv *priv = netdev_priv(netdev);
3670 struct mlx5e_channels *chs = &priv->channels;
3671 struct mlx5_core_dev *mdev = priv->mdev;
3674 mutex_lock(&priv->state_lock);
3677 err = mlx5e_set_rx_port_ts(mdev, false);
3681 chs->params.scatter_fcs_en = true;
3682 err = mlx5e_modify_channels_scatter_fcs(chs, true);
3684 chs->params.scatter_fcs_en = false;
3685 mlx5e_set_rx_port_ts(mdev, true);
3688 chs->params.scatter_fcs_en = false;
3689 err = mlx5e_modify_channels_scatter_fcs(chs, false);
3691 chs->params.scatter_fcs_en = true;
3694 err = mlx5e_set_rx_port_ts(mdev, true);
3696 mlx5_core_warn(mdev, "Failed to set RX port timestamp %d\n", err);
3702 mutex_unlock(&priv->state_lock);
3706 static int set_feature_rx_vlan(struct net_device *netdev, bool enable)
3708 struct mlx5e_priv *priv = netdev_priv(netdev);
3711 mutex_lock(&priv->state_lock);
3713 priv->channels.params.vlan_strip_disable = !enable;
3714 if (!test_bit(MLX5E_STATE_OPENED, &priv->state))
3717 err = mlx5e_modify_channels_vsd(&priv->channels, !enable);
3719 priv->channels.params.vlan_strip_disable = enable;
3722 mutex_unlock(&priv->state_lock);
3727 #ifdef CONFIG_MLX5_EN_ARFS
3728 static int set_feature_arfs(struct net_device *netdev, bool enable)
3730 struct mlx5e_priv *priv = netdev_priv(netdev);
3734 err = mlx5e_arfs_enable(priv);
3736 err = mlx5e_arfs_disable(priv);
3742 static int mlx5e_handle_feature(struct net_device *netdev,
3743 netdev_features_t *features,
3744 netdev_features_t wanted_features,
3745 netdev_features_t feature,
3746 mlx5e_feature_handler feature_handler)
3748 netdev_features_t changes = wanted_features ^ netdev->features;
3749 bool enable = !!(wanted_features & feature);
3752 if (!(changes & feature))
3755 err = feature_handler(netdev, enable);
3757 netdev_err(netdev, "%s feature %pNF failed, err %d\n",
3758 enable ? "Enable" : "Disable", &feature, err);
3762 MLX5E_SET_FEATURE(features, feature, enable);
3766 int mlx5e_set_features(struct net_device *netdev, netdev_features_t features)
3768 netdev_features_t oper_features = netdev->features;
3771 #define MLX5E_HANDLE_FEATURE(feature, handler) \
3772 mlx5e_handle_feature(netdev, &oper_features, features, feature, handler)
3774 err |= MLX5E_HANDLE_FEATURE(NETIF_F_LRO, set_feature_lro);
3775 err |= MLX5E_HANDLE_FEATURE(NETIF_F_GRO_HW, set_feature_hw_gro);
3776 err |= MLX5E_HANDLE_FEATURE(NETIF_F_HW_VLAN_CTAG_FILTER,
3777 set_feature_cvlan_filter);
3778 err |= MLX5E_HANDLE_FEATURE(NETIF_F_HW_TC, set_feature_hw_tc);
3779 err |= MLX5E_HANDLE_FEATURE(NETIF_F_RXALL, set_feature_rx_all);
3780 err |= MLX5E_HANDLE_FEATURE(NETIF_F_RXFCS, set_feature_rx_fcs);
3781 err |= MLX5E_HANDLE_FEATURE(NETIF_F_HW_VLAN_CTAG_RX, set_feature_rx_vlan);
3782 #ifdef CONFIG_MLX5_EN_ARFS
3783 err |= MLX5E_HANDLE_FEATURE(NETIF_F_NTUPLE, set_feature_arfs);
3785 err |= MLX5E_HANDLE_FEATURE(NETIF_F_HW_TLS_RX, mlx5e_ktls_set_feature_rx);
3788 netdev->features = oper_features;
3795 static netdev_features_t mlx5e_fix_uplink_rep_features(struct net_device *netdev,
3796 netdev_features_t features)
3798 features &= ~NETIF_F_HW_TLS_RX;
3799 if (netdev->features & NETIF_F_HW_TLS_RX)
3800 netdev_warn(netdev, "Disabling hw_tls_rx, not supported in switchdev mode\n");
3802 features &= ~NETIF_F_HW_TLS_TX;
3803 if (netdev->features & NETIF_F_HW_TLS_TX)
3804 netdev_warn(netdev, "Disabling hw_tls_tx, not supported in switchdev mode\n");
3806 features &= ~NETIF_F_NTUPLE;
3807 if (netdev->features & NETIF_F_NTUPLE)
3808 netdev_warn(netdev, "Disabling ntuple, not supported in switchdev mode\n");
3813 static netdev_features_t mlx5e_fix_features(struct net_device *netdev,
3814 netdev_features_t features)
3816 struct mlx5e_priv *priv = netdev_priv(netdev);
3817 struct mlx5e_params *params;
3819 mutex_lock(&priv->state_lock);
3820 params = &priv->channels.params;
3821 if (!priv->fs.vlan ||
3822 !bitmap_empty(mlx5e_vlan_get_active_svlans(priv->fs.vlan), VLAN_N_VID)) {
3823 /* HW strips the outer C-tag header, this is a problem
3824 * for S-tag traffic.
3826 features &= ~NETIF_F_HW_VLAN_CTAG_RX;
3827 if (!params->vlan_strip_disable)
3828 netdev_warn(netdev, "Dropping C-tag vlan stripping offload due to S-tag vlan\n");
3831 if (!MLX5E_GET_PFLAG(params, MLX5E_PFLAG_RX_STRIDING_RQ)) {
3832 if (features & NETIF_F_LRO) {
3833 netdev_warn(netdev, "Disabling LRO, not supported in legacy RQ\n");
3834 features &= ~NETIF_F_LRO;
3836 if (features & NETIF_F_GRO_HW) {
3837 netdev_warn(netdev, "Disabling HW-GRO, not supported in legacy RQ\n");
3838 features &= ~NETIF_F_GRO_HW;
3842 if (MLX5E_GET_PFLAG(params, MLX5E_PFLAG_RX_CQE_COMPRESS)) {
3843 features &= ~NETIF_F_RXHASH;
3844 if (netdev->features & NETIF_F_RXHASH)
3845 netdev_warn(netdev, "Disabling rxhash, not supported when CQE compress is active\n");
3848 if (mlx5e_is_uplink_rep(priv))
3849 features = mlx5e_fix_uplink_rep_features(netdev, features);
3851 mutex_unlock(&priv->state_lock);
3856 static bool mlx5e_xsk_validate_mtu(struct net_device *netdev,
3857 struct mlx5e_channels *chs,
3858 struct mlx5e_params *new_params,
3859 struct mlx5_core_dev *mdev)
3863 for (ix = 0; ix < chs->params.num_channels; ix++) {
3864 struct xsk_buff_pool *xsk_pool =
3865 mlx5e_xsk_get_pool(&chs->params, chs->params.xsk, ix);
3866 struct mlx5e_xsk_param xsk;
3871 mlx5e_build_xsk_param(xsk_pool, &xsk);
3873 if (!mlx5e_validate_xsk_param(new_params, &xsk, mdev)) {
3874 u32 hr = mlx5e_get_linear_rq_headroom(new_params, &xsk);
3875 int max_mtu_frame, max_mtu_page, max_mtu;
3877 /* Two criteria must be met:
3878 * 1. HW MTU + all headrooms <= XSK frame size.
3879 * 2. Size of SKBs allocated on XDP_PASS <= PAGE_SIZE.
3881 max_mtu_frame = MLX5E_HW2SW_MTU(new_params, xsk.chunk_size - hr);
3882 max_mtu_page = mlx5e_xdp_max_mtu(new_params, &xsk);
3883 max_mtu = min(max_mtu_frame, max_mtu_page);
3885 netdev_err(netdev, "MTU %d is too big for an XSK running on channel %u. Try MTU <= %d\n",
3886 new_params->sw_mtu, ix, max_mtu);
3894 int mlx5e_change_mtu(struct net_device *netdev, int new_mtu,
3895 mlx5e_fp_preactivate preactivate)
3897 struct mlx5e_priv *priv = netdev_priv(netdev);
3898 struct mlx5e_params new_params;
3899 struct mlx5e_params *params;
3903 mutex_lock(&priv->state_lock);
3905 params = &priv->channels.params;
3907 new_params = *params;
3908 new_params.sw_mtu = new_mtu;
3909 err = mlx5e_validate_params(priv->mdev, &new_params);
3913 if (params->xdp_prog &&
3914 !mlx5e_rx_is_linear_skb(&new_params, NULL)) {
3915 netdev_err(netdev, "MTU(%d) > %d is not allowed while XDP enabled\n",
3916 new_mtu, mlx5e_xdp_max_mtu(params, NULL));
3921 if (priv->xsk.refcnt &&
3922 !mlx5e_xsk_validate_mtu(netdev, &priv->channels,
3923 &new_params, priv->mdev)) {
3928 if (params->packet_merge.type == MLX5E_PACKET_MERGE_LRO)
3931 if (params->rq_wq_type == MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ) {
3932 bool is_linear_old = mlx5e_rx_mpwqe_is_linear_skb(priv->mdev, params, NULL);
3933 bool is_linear_new = mlx5e_rx_mpwqe_is_linear_skb(priv->mdev,
3935 u8 ppw_old = mlx5e_mpwqe_log_pkts_per_wqe(params, NULL);
3936 u8 ppw_new = mlx5e_mpwqe_log_pkts_per_wqe(&new_params, NULL);
3938 /* Always reset in linear mode - hw_mtu is used in data path.
3939 * Check that the mode was non-linear and didn't change.
3940 * If XSK is active, XSK RQs are linear.
3942 if (!is_linear_old && !is_linear_new && !priv->xsk.refcnt &&
3947 err = mlx5e_safe_switch_params(priv, &new_params, preactivate, NULL, reset);
3950 netdev->mtu = params->sw_mtu;
3951 mutex_unlock(&priv->state_lock);
3955 static int mlx5e_change_nic_mtu(struct net_device *netdev, int new_mtu)
3957 return mlx5e_change_mtu(netdev, new_mtu, mlx5e_set_dev_port_mtu_ctx);
3960 int mlx5e_ptp_rx_manage_fs_ctx(struct mlx5e_priv *priv, void *ctx)
3962 bool set = *(bool *)ctx;
3964 return mlx5e_ptp_rx_manage_fs(priv, set);
3967 static int mlx5e_hwstamp_config_no_ptp_rx(struct mlx5e_priv *priv, bool rx_filter)
3969 bool rx_cqe_compress_def = priv->channels.params.rx_cqe_compress_def;
3973 /* Reset CQE compression to Admin default */
3974 return mlx5e_modify_rx_cqe_compression_locked(priv, rx_cqe_compress_def, false);
3976 if (!MLX5E_GET_PFLAG(&priv->channels.params, MLX5E_PFLAG_RX_CQE_COMPRESS))
3979 /* Disable CQE compression */
3980 netdev_warn(priv->netdev, "Disabling RX cqe compression\n");
3981 err = mlx5e_modify_rx_cqe_compression_locked(priv, false, true);
3983 netdev_err(priv->netdev, "Failed disabling cqe compression err=%d\n", err);
3988 static int mlx5e_hwstamp_config_ptp_rx(struct mlx5e_priv *priv, bool ptp_rx)
3990 struct mlx5e_params new_params;
3992 if (ptp_rx == priv->channels.params.ptp_rx)
3995 new_params = priv->channels.params;
3996 new_params.ptp_rx = ptp_rx;
3997 return mlx5e_safe_switch_params(priv, &new_params, mlx5e_ptp_rx_manage_fs_ctx,
3998 &new_params.ptp_rx, true);
4001 int mlx5e_hwstamp_set(struct mlx5e_priv *priv, struct ifreq *ifr)
4003 struct hwtstamp_config config;
4004 bool rx_cqe_compress_def;
4008 if (!MLX5_CAP_GEN(priv->mdev, device_frequency_khz) ||
4009 (mlx5_clock_get_ptp_index(priv->mdev) == -1))
4012 if (copy_from_user(&config, ifr->ifr_data, sizeof(config)))
4015 /* TX HW timestamp */
4016 switch (config.tx_type) {
4017 case HWTSTAMP_TX_OFF:
4018 case HWTSTAMP_TX_ON:
4024 mutex_lock(&priv->state_lock);
4025 rx_cqe_compress_def = priv->channels.params.rx_cqe_compress_def;
4027 /* RX HW timestamp */
4028 switch (config.rx_filter) {
4029 case HWTSTAMP_FILTER_NONE:
4032 case HWTSTAMP_FILTER_ALL:
4033 case HWTSTAMP_FILTER_SOME:
4034 case HWTSTAMP_FILTER_PTP_V1_L4_EVENT:
4035 case HWTSTAMP_FILTER_PTP_V1_L4_SYNC:
4036 case HWTSTAMP_FILTER_PTP_V1_L4_DELAY_REQ:
4037 case HWTSTAMP_FILTER_PTP_V2_L4_EVENT:
4038 case HWTSTAMP_FILTER_PTP_V2_L4_SYNC:
4039 case HWTSTAMP_FILTER_PTP_V2_L4_DELAY_REQ:
4040 case HWTSTAMP_FILTER_PTP_V2_L2_EVENT:
4041 case HWTSTAMP_FILTER_PTP_V2_L2_SYNC:
4042 case HWTSTAMP_FILTER_PTP_V2_L2_DELAY_REQ:
4043 case HWTSTAMP_FILTER_PTP_V2_EVENT:
4044 case HWTSTAMP_FILTER_PTP_V2_SYNC:
4045 case HWTSTAMP_FILTER_PTP_V2_DELAY_REQ:
4046 case HWTSTAMP_FILTER_NTP_ALL:
4047 config.rx_filter = HWTSTAMP_FILTER_ALL;
4048 /* ptp_rx is set if both HW TS is set and CQE
4049 * compression is set
4051 ptp_rx = rx_cqe_compress_def;
4058 if (!priv->profile->rx_ptp_support)
4059 err = mlx5e_hwstamp_config_no_ptp_rx(priv,
4060 config.rx_filter != HWTSTAMP_FILTER_NONE);
4062 err = mlx5e_hwstamp_config_ptp_rx(priv, ptp_rx);
4066 memcpy(&priv->tstamp, &config, sizeof(config));
4067 mutex_unlock(&priv->state_lock);
4069 /* might need to fix some features */
4070 netdev_update_features(priv->netdev);
4072 return copy_to_user(ifr->ifr_data, &config,
4073 sizeof(config)) ? -EFAULT : 0;
4075 mutex_unlock(&priv->state_lock);
4079 int mlx5e_hwstamp_get(struct mlx5e_priv *priv, struct ifreq *ifr)
4081 struct hwtstamp_config *cfg = &priv->tstamp;
4083 if (!MLX5_CAP_GEN(priv->mdev, device_frequency_khz))
4086 return copy_to_user(ifr->ifr_data, cfg, sizeof(*cfg)) ? -EFAULT : 0;
4089 static int mlx5e_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
4091 struct mlx5e_priv *priv = netdev_priv(dev);
4095 return mlx5e_hwstamp_set(priv, ifr);
4097 return mlx5e_hwstamp_get(priv, ifr);
4103 #ifdef CONFIG_MLX5_ESWITCH
4104 int mlx5e_set_vf_mac(struct net_device *dev, int vf, u8 *mac)
4106 struct mlx5e_priv *priv = netdev_priv(dev);
4107 struct mlx5_core_dev *mdev = priv->mdev;
4109 return mlx5_eswitch_set_vport_mac(mdev->priv.eswitch, vf + 1, mac);
4112 static int mlx5e_set_vf_vlan(struct net_device *dev, int vf, u16 vlan, u8 qos,
4115 struct mlx5e_priv *priv = netdev_priv(dev);
4116 struct mlx5_core_dev *mdev = priv->mdev;
4118 if (vlan_proto != htons(ETH_P_8021Q))
4119 return -EPROTONOSUPPORT;
4121 return mlx5_eswitch_set_vport_vlan(mdev->priv.eswitch, vf + 1,
4125 static int mlx5e_set_vf_spoofchk(struct net_device *dev, int vf, bool setting)
4127 struct mlx5e_priv *priv = netdev_priv(dev);
4128 struct mlx5_core_dev *mdev = priv->mdev;
4130 return mlx5_eswitch_set_vport_spoofchk(mdev->priv.eswitch, vf + 1, setting);
4133 static int mlx5e_set_vf_trust(struct net_device *dev, int vf, bool setting)
4135 struct mlx5e_priv *priv = netdev_priv(dev);
4136 struct mlx5_core_dev *mdev = priv->mdev;
4138 return mlx5_eswitch_set_vport_trust(mdev->priv.eswitch, vf + 1, setting);
4141 int mlx5e_set_vf_rate(struct net_device *dev, int vf, int min_tx_rate,
4144 struct mlx5e_priv *priv = netdev_priv(dev);
4145 struct mlx5_core_dev *mdev = priv->mdev;
4147 return mlx5_eswitch_set_vport_rate(mdev->priv.eswitch, vf + 1,
4148 max_tx_rate, min_tx_rate);
4151 static int mlx5_vport_link2ifla(u8 esw_link)
4154 case MLX5_VPORT_ADMIN_STATE_DOWN:
4155 return IFLA_VF_LINK_STATE_DISABLE;
4156 case MLX5_VPORT_ADMIN_STATE_UP:
4157 return IFLA_VF_LINK_STATE_ENABLE;
4159 return IFLA_VF_LINK_STATE_AUTO;
4162 static int mlx5_ifla_link2vport(u8 ifla_link)
4164 switch (ifla_link) {
4165 case IFLA_VF_LINK_STATE_DISABLE:
4166 return MLX5_VPORT_ADMIN_STATE_DOWN;
4167 case IFLA_VF_LINK_STATE_ENABLE:
4168 return MLX5_VPORT_ADMIN_STATE_UP;
4170 return MLX5_VPORT_ADMIN_STATE_AUTO;
4173 static int mlx5e_set_vf_link_state(struct net_device *dev, int vf,
4176 struct mlx5e_priv *priv = netdev_priv(dev);
4177 struct mlx5_core_dev *mdev = priv->mdev;
4179 if (mlx5e_is_uplink_rep(priv))
4182 return mlx5_eswitch_set_vport_state(mdev->priv.eswitch, vf + 1,
4183 mlx5_ifla_link2vport(link_state));
4186 int mlx5e_get_vf_config(struct net_device *dev,
4187 int vf, struct ifla_vf_info *ivi)
4189 struct mlx5e_priv *priv = netdev_priv(dev);
4190 struct mlx5_core_dev *mdev = priv->mdev;
4193 if (!netif_device_present(dev))
4196 err = mlx5_eswitch_get_vport_config(mdev->priv.eswitch, vf + 1, ivi);
4199 ivi->linkstate = mlx5_vport_link2ifla(ivi->linkstate);
4203 int mlx5e_get_vf_stats(struct net_device *dev,
4204 int vf, struct ifla_vf_stats *vf_stats)
4206 struct mlx5e_priv *priv = netdev_priv(dev);
4207 struct mlx5_core_dev *mdev = priv->mdev;
4209 return mlx5_eswitch_get_vport_stats(mdev->priv.eswitch, vf + 1,
4214 mlx5e_has_offload_stats(const struct net_device *dev, int attr_id)
4216 struct mlx5e_priv *priv = netdev_priv(dev);
4218 if (!netif_device_present(dev))
4221 if (!mlx5e_is_uplink_rep(priv))
4224 return mlx5e_rep_has_offload_stats(dev, attr_id);
4228 mlx5e_get_offload_stats(int attr_id, const struct net_device *dev,
4231 struct mlx5e_priv *priv = netdev_priv(dev);
4233 if (!mlx5e_is_uplink_rep(priv))
4236 return mlx5e_rep_get_offload_stats(attr_id, dev, sp);
4240 static bool mlx5e_tunnel_proto_supported_tx(struct mlx5_core_dev *mdev, u8 proto_type)
4242 switch (proto_type) {
4244 return MLX5_CAP_ETH(mdev, tunnel_stateless_gre);
4247 return (MLX5_CAP_ETH(mdev, tunnel_stateless_ip_over_ip) ||
4248 MLX5_CAP_ETH(mdev, tunnel_stateless_ip_over_ip_tx));
4254 static bool mlx5e_gre_tunnel_inner_proto_offload_supported(struct mlx5_core_dev *mdev,
4255 struct sk_buff *skb)
4257 switch (skb->inner_protocol) {
4258 case htons(ETH_P_IP):
4259 case htons(ETH_P_IPV6):
4260 case htons(ETH_P_TEB):
4262 case htons(ETH_P_MPLS_UC):
4263 case htons(ETH_P_MPLS_MC):
4264 return MLX5_CAP_ETH(mdev, tunnel_stateless_mpls_over_gre);
4269 static netdev_features_t mlx5e_tunnel_features_check(struct mlx5e_priv *priv,
4270 struct sk_buff *skb,
4271 netdev_features_t features)
4273 unsigned int offset = 0;
4274 struct udphdr *udph;
4278 switch (vlan_get_protocol(skb)) {
4279 case htons(ETH_P_IP):
4280 proto = ip_hdr(skb)->protocol;
4282 case htons(ETH_P_IPV6):
4283 proto = ipv6_find_hdr(skb, &offset, -1, NULL, NULL);
4291 if (mlx5e_gre_tunnel_inner_proto_offload_supported(priv->mdev, skb))
4296 if (mlx5e_tunnel_proto_supported_tx(priv->mdev, IPPROTO_IPIP))
4300 udph = udp_hdr(skb);
4301 port = be16_to_cpu(udph->dest);
4303 /* Verify if UDP port is being offloaded by HW */
4304 if (mlx5_vxlan_lookup_port(priv->mdev->vxlan, port))
4307 #if IS_ENABLED(CONFIG_GENEVE)
4308 /* Support Geneve offload for default UDP port */
4309 if (port == GENEVE_UDP_PORT && mlx5_geneve_tx_allowed(priv->mdev))
4313 #ifdef CONFIG_MLX5_EN_IPSEC
4315 return mlx5e_ipsec_feature_check(skb, features);
4320 /* Disable CSUM and GSO if the udp dport is not offloaded by HW */
4321 return features & ~(NETIF_F_CSUM_MASK | NETIF_F_GSO_MASK);
4324 netdev_features_t mlx5e_features_check(struct sk_buff *skb,
4325 struct net_device *netdev,
4326 netdev_features_t features)
4328 struct mlx5e_priv *priv = netdev_priv(netdev);
4330 features = vlan_features_check(skb, features);
4331 features = vxlan_features_check(skb, features);
4333 /* Validate if the tunneled packet is being offloaded by HW */
4334 if (skb->encapsulation &&
4335 (features & NETIF_F_CSUM_MASK || features & NETIF_F_GSO_MASK))
4336 return mlx5e_tunnel_features_check(priv, skb, features);
4341 static void mlx5e_tx_timeout_work(struct work_struct *work)
4343 struct mlx5e_priv *priv = container_of(work, struct mlx5e_priv,
4345 struct net_device *netdev = priv->netdev;
4349 mutex_lock(&priv->state_lock);
4351 if (!test_bit(MLX5E_STATE_OPENED, &priv->state))
4354 for (i = 0; i < netdev->real_num_tx_queues; i++) {
4355 struct netdev_queue *dev_queue =
4356 netdev_get_tx_queue(netdev, i);
4357 struct mlx5e_txqsq *sq = priv->txq2sq[i];
4359 if (!netif_xmit_stopped(dev_queue))
4362 if (mlx5e_reporter_tx_timeout(sq))
4363 /* break if tried to reopened channels */
4368 mutex_unlock(&priv->state_lock);
4372 static void mlx5e_tx_timeout(struct net_device *dev, unsigned int txqueue)
4374 struct mlx5e_priv *priv = netdev_priv(dev);
4376 netdev_err(dev, "TX timeout detected\n");
4377 queue_work(priv->wq, &priv->tx_timeout_work);
4380 static int mlx5e_xdp_allowed(struct mlx5e_priv *priv, struct bpf_prog *prog)
4382 struct net_device *netdev = priv->netdev;
4383 struct mlx5e_params new_params;
4385 if (priv->channels.params.packet_merge.type != MLX5E_PACKET_MERGE_NONE) {
4386 netdev_warn(netdev, "can't set XDP while HW-GRO/LRO is on, disable them first\n");
4390 if (mlx5_fpga_is_ipsec_device(priv->mdev)) {
4392 "XDP is not available on Innova cards with IPsec support\n");
4396 new_params = priv->channels.params;
4397 new_params.xdp_prog = prog;
4399 /* No XSK params: AF_XDP can't be enabled yet at the point of setting
4402 if (!mlx5e_rx_is_linear_skb(&new_params, NULL)) {
4403 netdev_warn(netdev, "XDP is not allowed with MTU(%d) > %d\n",
4405 mlx5e_xdp_max_mtu(&new_params, NULL));
4412 static void mlx5e_rq_replace_xdp_prog(struct mlx5e_rq *rq, struct bpf_prog *prog)
4414 struct bpf_prog *old_prog;
4416 old_prog = rcu_replace_pointer(rq->xdp_prog, prog,
4417 lockdep_is_held(&rq->priv->state_lock));
4419 bpf_prog_put(old_prog);
4422 static int mlx5e_xdp_set(struct net_device *netdev, struct bpf_prog *prog)
4424 struct mlx5e_priv *priv = netdev_priv(netdev);
4425 struct mlx5e_params new_params;
4426 struct bpf_prog *old_prog;
4431 mutex_lock(&priv->state_lock);
4434 err = mlx5e_xdp_allowed(priv, prog);
4439 /* no need for full reset when exchanging programs */
4440 reset = (!priv->channels.params.xdp_prog || !prog);
4442 new_params = priv->channels.params;
4443 new_params.xdp_prog = prog;
4445 mlx5e_set_rq_type(priv->mdev, &new_params);
4446 old_prog = priv->channels.params.xdp_prog;
4448 err = mlx5e_safe_switch_params(priv, &new_params, NULL, NULL, reset);
4453 bpf_prog_put(old_prog);
4455 if (!test_bit(MLX5E_STATE_OPENED, &priv->state) || reset)
4458 /* exchanging programs w/o reset, we update ref counts on behalf
4459 * of the channels RQs here.
4461 bpf_prog_add(prog, priv->channels.num);
4462 for (i = 0; i < priv->channels.num; i++) {
4463 struct mlx5e_channel *c = priv->channels.c[i];
4465 mlx5e_rq_replace_xdp_prog(&c->rq, prog);
4466 if (test_bit(MLX5E_CHANNEL_STATE_XSK, c->state)) {
4468 mlx5e_rq_replace_xdp_prog(&c->xskrq, prog);
4473 mutex_unlock(&priv->state_lock);
4477 static int mlx5e_xdp(struct net_device *dev, struct netdev_bpf *xdp)
4479 switch (xdp->command) {
4480 case XDP_SETUP_PROG:
4481 return mlx5e_xdp_set(dev, xdp->prog);
4482 case XDP_SETUP_XSK_POOL:
4483 return mlx5e_xsk_setup_pool(dev, xdp->xsk.pool,
4490 #ifdef CONFIG_MLX5_ESWITCH
4491 static int mlx5e_bridge_getlink(struct sk_buff *skb, u32 pid, u32 seq,
4492 struct net_device *dev, u32 filter_mask,
4495 struct mlx5e_priv *priv = netdev_priv(dev);
4496 struct mlx5_core_dev *mdev = priv->mdev;
4500 err = mlx5_eswitch_get_vepa(mdev->priv.eswitch, &setting);
4503 mode = setting ? BRIDGE_MODE_VEPA : BRIDGE_MODE_VEB;
4504 return ndo_dflt_bridge_getlink(skb, pid, seq, dev,
4506 0, 0, nlflags, filter_mask, NULL);
4509 static int mlx5e_bridge_setlink(struct net_device *dev, struct nlmsghdr *nlh,
4510 u16 flags, struct netlink_ext_ack *extack)
4512 struct mlx5e_priv *priv = netdev_priv(dev);
4513 struct mlx5_core_dev *mdev = priv->mdev;
4514 struct nlattr *attr, *br_spec;
4515 u16 mode = BRIDGE_MODE_UNDEF;
4519 br_spec = nlmsg_find_attr(nlh, sizeof(struct ifinfomsg), IFLA_AF_SPEC);
4523 nla_for_each_nested(attr, br_spec, rem) {
4524 if (nla_type(attr) != IFLA_BRIDGE_MODE)
4527 if (nla_len(attr) < sizeof(mode))
4530 mode = nla_get_u16(attr);
4531 if (mode > BRIDGE_MODE_VEPA)
4537 if (mode == BRIDGE_MODE_UNDEF)
4540 setting = (mode == BRIDGE_MODE_VEPA) ? 1 : 0;
4541 return mlx5_eswitch_set_vepa(mdev->priv.eswitch, setting);
4545 const struct net_device_ops mlx5e_netdev_ops = {
4546 .ndo_open = mlx5e_open,
4547 .ndo_stop = mlx5e_close,
4548 .ndo_start_xmit = mlx5e_xmit,
4549 .ndo_setup_tc = mlx5e_setup_tc,
4550 .ndo_select_queue = mlx5e_select_queue,
4551 .ndo_get_stats64 = mlx5e_get_stats,
4552 .ndo_set_rx_mode = mlx5e_set_rx_mode,
4553 .ndo_set_mac_address = mlx5e_set_mac,
4554 .ndo_vlan_rx_add_vid = mlx5e_vlan_rx_add_vid,
4555 .ndo_vlan_rx_kill_vid = mlx5e_vlan_rx_kill_vid,
4556 .ndo_set_features = mlx5e_set_features,
4557 .ndo_fix_features = mlx5e_fix_features,
4558 .ndo_change_mtu = mlx5e_change_nic_mtu,
4559 .ndo_eth_ioctl = mlx5e_ioctl,
4560 .ndo_set_tx_maxrate = mlx5e_set_tx_maxrate,
4561 .ndo_features_check = mlx5e_features_check,
4562 .ndo_tx_timeout = mlx5e_tx_timeout,
4563 .ndo_bpf = mlx5e_xdp,
4564 .ndo_xdp_xmit = mlx5e_xdp_xmit,
4565 .ndo_xsk_wakeup = mlx5e_xsk_wakeup,
4566 #ifdef CONFIG_MLX5_EN_ARFS
4567 .ndo_rx_flow_steer = mlx5e_rx_flow_steer,
4569 #ifdef CONFIG_MLX5_ESWITCH
4570 .ndo_bridge_setlink = mlx5e_bridge_setlink,
4571 .ndo_bridge_getlink = mlx5e_bridge_getlink,
4573 /* SRIOV E-Switch NDOs */
4574 .ndo_set_vf_mac = mlx5e_set_vf_mac,
4575 .ndo_set_vf_vlan = mlx5e_set_vf_vlan,
4576 .ndo_set_vf_spoofchk = mlx5e_set_vf_spoofchk,
4577 .ndo_set_vf_trust = mlx5e_set_vf_trust,
4578 .ndo_set_vf_rate = mlx5e_set_vf_rate,
4579 .ndo_get_vf_config = mlx5e_get_vf_config,
4580 .ndo_set_vf_link_state = mlx5e_set_vf_link_state,
4581 .ndo_get_vf_stats = mlx5e_get_vf_stats,
4582 .ndo_has_offload_stats = mlx5e_has_offload_stats,
4583 .ndo_get_offload_stats = mlx5e_get_offload_stats,
4585 .ndo_get_devlink_port = mlx5e_get_devlink_port,
4588 static u32 mlx5e_choose_lro_timeout(struct mlx5_core_dev *mdev, u32 wanted_timeout)
4592 /* The supported periods are organized in ascending order */
4593 for (i = 0; i < MLX5E_LRO_TIMEOUT_ARR_SIZE - 1; i++)
4594 if (MLX5_CAP_ETH(mdev, lro_timer_supported_periods[i]) >= wanted_timeout)
4597 return MLX5_CAP_ETH(mdev, lro_timer_supported_periods[i]);
4600 void mlx5e_build_nic_params(struct mlx5e_priv *priv, struct mlx5e_xsk *xsk, u16 mtu)
4602 struct mlx5e_params *params = &priv->channels.params;
4603 struct mlx5_core_dev *mdev = priv->mdev;
4604 u8 rx_cq_period_mode;
4606 params->sw_mtu = mtu;
4607 params->hard_mtu = MLX5E_ETH_HARD_MTU;
4608 params->num_channels = min_t(unsigned int, MLX5E_MAX_NUM_CHANNELS / 2,
4610 mlx5e_params_mqprio_reset(params);
4612 /* Set an initial non-zero value, so that mlx5e_select_queue won't
4613 * divide by zero if called before first activating channels.
4615 priv->num_tc_x_num_ch = params->num_channels * params->mqprio.num_tc;
4618 params->log_sq_size = is_kdump_kernel() ?
4619 MLX5E_PARAMS_MINIMUM_LOG_SQ_SIZE :
4620 MLX5E_PARAMS_DEFAULT_LOG_SQ_SIZE;
4621 MLX5E_SET_PFLAG(params, MLX5E_PFLAG_SKB_TX_MPWQE, mlx5e_tx_mpwqe_supported(mdev));
4624 MLX5E_SET_PFLAG(params, MLX5E_PFLAG_XDP_TX_MPWQE, mlx5e_tx_mpwqe_supported(mdev));
4626 /* set CQE compression */
4627 params->rx_cqe_compress_def = false;
4628 if (MLX5_CAP_GEN(mdev, cqe_compression) &&
4629 MLX5_CAP_GEN(mdev, vport_group_manager))
4630 params->rx_cqe_compress_def = slow_pci_heuristic(mdev);
4632 MLX5E_SET_PFLAG(params, MLX5E_PFLAG_RX_CQE_COMPRESS, params->rx_cqe_compress_def);
4633 MLX5E_SET_PFLAG(params, MLX5E_PFLAG_RX_NO_CSUM_COMPLETE, false);
4636 mlx5e_build_rq_params(mdev, params);
4639 if (MLX5_CAP_ETH(mdev, lro_cap) &&
4640 params->rq_wq_type == MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ) {
4641 /* No XSK params: checking the availability of striding RQ in general. */
4642 if (!mlx5e_rx_mpwqe_is_linear_skb(mdev, params, NULL))
4643 params->packet_merge.type = slow_pci_heuristic(mdev) ?
4644 MLX5E_PACKET_MERGE_NONE : MLX5E_PACKET_MERGE_LRO;
4646 params->packet_merge.timeout = mlx5e_choose_lro_timeout(mdev, MLX5E_DEFAULT_LRO_TIMEOUT);
4648 /* CQ moderation params */
4649 rx_cq_period_mode = MLX5_CAP_GEN(mdev, cq_period_start_from_cqe) ?
4650 MLX5_CQ_PERIOD_MODE_START_FROM_CQE :
4651 MLX5_CQ_PERIOD_MODE_START_FROM_EQE;
4652 params->rx_dim_enabled = MLX5_CAP_GEN(mdev, cq_moderation);
4653 params->tx_dim_enabled = MLX5_CAP_GEN(mdev, cq_moderation);
4654 mlx5e_set_rx_cq_mode_params(params, rx_cq_period_mode);
4655 mlx5e_set_tx_cq_mode_params(params, MLX5_CQ_PERIOD_MODE_START_FROM_EQE);
4658 mlx5_query_min_inline(mdev, ¶ms->tx_min_inline_mode);
4660 params->tunneled_offload_en = mlx5_tunnel_inner_ft_supported(mdev);
4665 /* Do not update netdev->features directly in here
4666 * on mlx5e_attach_netdev() we will call mlx5e_update_features()
4667 * To update netdev->features please modify mlx5e_fix_features()
4671 static void mlx5e_set_netdev_dev_addr(struct net_device *netdev)
4673 struct mlx5e_priv *priv = netdev_priv(netdev);
4676 mlx5_query_mac_address(priv->mdev, addr);
4677 if (is_zero_ether_addr(addr) &&
4678 !MLX5_CAP_GEN(priv->mdev, vport_group_manager)) {
4679 eth_hw_addr_random(netdev);
4680 mlx5_core_info(priv->mdev, "Assigned random MAC address %pM\n", netdev->dev_addr);
4684 eth_hw_addr_set(netdev, addr);
4687 static int mlx5e_vxlan_set_port(struct net_device *netdev, unsigned int table,
4688 unsigned int entry, struct udp_tunnel_info *ti)
4690 struct mlx5e_priv *priv = netdev_priv(netdev);
4692 return mlx5_vxlan_add_port(priv->mdev->vxlan, ntohs(ti->port));
4695 static int mlx5e_vxlan_unset_port(struct net_device *netdev, unsigned int table,
4696 unsigned int entry, struct udp_tunnel_info *ti)
4698 struct mlx5e_priv *priv = netdev_priv(netdev);
4700 return mlx5_vxlan_del_port(priv->mdev->vxlan, ntohs(ti->port));
4703 void mlx5e_vxlan_set_netdev_info(struct mlx5e_priv *priv)
4705 if (!mlx5_vxlan_allowed(priv->mdev->vxlan))
4708 priv->nic_info.set_port = mlx5e_vxlan_set_port;
4709 priv->nic_info.unset_port = mlx5e_vxlan_unset_port;
4710 priv->nic_info.flags = UDP_TUNNEL_NIC_INFO_MAY_SLEEP |
4711 UDP_TUNNEL_NIC_INFO_STATIC_IANA_VXLAN;
4712 priv->nic_info.tables[0].tunnel_types = UDP_TUNNEL_TYPE_VXLAN;
4713 /* Don't count the space hard-coded to the IANA port */
4714 priv->nic_info.tables[0].n_entries =
4715 mlx5_vxlan_max_udp_ports(priv->mdev) - 1;
4717 priv->netdev->udp_tunnel_nic_info = &priv->nic_info;
4720 static bool mlx5e_tunnel_any_tx_proto_supported(struct mlx5_core_dev *mdev)
4724 for (tt = 0; tt < MLX5_NUM_TUNNEL_TT; tt++) {
4725 if (mlx5e_tunnel_proto_supported_tx(mdev, mlx5_get_proto_by_tunnel_type(tt)))
4728 return (mlx5_vxlan_allowed(mdev->vxlan) || mlx5_geneve_tx_allowed(mdev));
4731 static void mlx5e_build_nic_netdev(struct net_device *netdev)
4733 struct mlx5e_priv *priv = netdev_priv(netdev);
4734 struct mlx5_core_dev *mdev = priv->mdev;
4738 SET_NETDEV_DEV(netdev, mdev->device);
4740 netdev->netdev_ops = &mlx5e_netdev_ops;
4742 mlx5e_dcbnl_build_netdev(netdev);
4744 netdev->watchdog_timeo = 15 * HZ;
4746 netdev->ethtool_ops = &mlx5e_ethtool_ops;
4748 netdev->vlan_features |= NETIF_F_SG;
4749 netdev->vlan_features |= NETIF_F_HW_CSUM;
4750 netdev->vlan_features |= NETIF_F_GRO;
4751 netdev->vlan_features |= NETIF_F_TSO;
4752 netdev->vlan_features |= NETIF_F_TSO6;
4753 netdev->vlan_features |= NETIF_F_RXCSUM;
4754 netdev->vlan_features |= NETIF_F_RXHASH;
4756 netdev->mpls_features |= NETIF_F_SG;
4757 netdev->mpls_features |= NETIF_F_HW_CSUM;
4758 netdev->mpls_features |= NETIF_F_TSO;
4759 netdev->mpls_features |= NETIF_F_TSO6;
4761 netdev->hw_enc_features |= NETIF_F_HW_VLAN_CTAG_TX;
4762 netdev->hw_enc_features |= NETIF_F_HW_VLAN_CTAG_RX;
4764 /* Tunneled LRO is not supported in the driver, and the same RQs are
4765 * shared between inner and outer TIRs, so the driver can't disable LRO
4766 * for inner TIRs while having it enabled for outer TIRs. Due to this,
4767 * block LRO altogether if the firmware declares tunneled LRO support.
4769 if (!!MLX5_CAP_ETH(mdev, lro_cap) &&
4770 !MLX5_CAP_ETH(mdev, tunnel_lro_vxlan) &&
4771 !MLX5_CAP_ETH(mdev, tunnel_lro_gre) &&
4772 mlx5e_check_fragmented_striding_rq_cap(mdev))
4773 netdev->vlan_features |= NETIF_F_LRO;
4775 netdev->hw_features = netdev->vlan_features;
4776 netdev->hw_features |= NETIF_F_HW_VLAN_CTAG_TX;
4777 netdev->hw_features |= NETIF_F_HW_VLAN_CTAG_RX;
4778 netdev->hw_features |= NETIF_F_HW_VLAN_CTAG_FILTER;
4779 netdev->hw_features |= NETIF_F_HW_VLAN_STAG_TX;
4781 if (!!MLX5_CAP_GEN(mdev, shampo) &&
4782 mlx5e_check_fragmented_striding_rq_cap(mdev))
4783 netdev->hw_features |= NETIF_F_GRO_HW;
4785 if (mlx5e_tunnel_any_tx_proto_supported(mdev)) {
4786 netdev->hw_enc_features |= NETIF_F_HW_CSUM;
4787 netdev->hw_enc_features |= NETIF_F_TSO;
4788 netdev->hw_enc_features |= NETIF_F_TSO6;
4789 netdev->hw_enc_features |= NETIF_F_GSO_PARTIAL;
4792 if (mlx5_vxlan_allowed(mdev->vxlan) || mlx5_geneve_tx_allowed(mdev)) {
4793 netdev->hw_features |= NETIF_F_GSO_UDP_TUNNEL;
4794 netdev->hw_enc_features |= NETIF_F_GSO_UDP_TUNNEL;
4795 netdev->vlan_features |= NETIF_F_GSO_UDP_TUNNEL;
4798 if (mlx5e_tunnel_proto_supported_tx(mdev, IPPROTO_GRE)) {
4799 netdev->hw_features |= NETIF_F_GSO_GRE;
4800 netdev->hw_enc_features |= NETIF_F_GSO_GRE;
4801 netdev->gso_partial_features |= NETIF_F_GSO_GRE;
4804 if (mlx5e_tunnel_proto_supported_tx(mdev, IPPROTO_IPIP)) {
4805 netdev->hw_features |= NETIF_F_GSO_IPXIP4 |
4807 netdev->hw_enc_features |= NETIF_F_GSO_IPXIP4 |
4809 netdev->gso_partial_features |= NETIF_F_GSO_IPXIP4 |
4813 netdev->hw_features |= NETIF_F_GSO_PARTIAL;
4814 netdev->gso_partial_features |= NETIF_F_GSO_UDP_L4;
4815 netdev->hw_features |= NETIF_F_GSO_UDP_L4;
4816 netdev->features |= NETIF_F_GSO_UDP_L4;
4818 mlx5_query_port_fcs(mdev, &fcs_supported, &fcs_enabled);
4821 netdev->hw_features |= NETIF_F_RXALL;
4823 if (MLX5_CAP_ETH(mdev, scatter_fcs))
4824 netdev->hw_features |= NETIF_F_RXFCS;
4826 if (mlx5_qos_is_supported(mdev))
4827 netdev->hw_features |= NETIF_F_HW_TC;
4829 netdev->features = netdev->hw_features;
4833 netdev->features &= ~NETIF_F_RXALL;
4834 netdev->features &= ~NETIF_F_LRO;
4835 netdev->features &= ~NETIF_F_GRO_HW;
4836 netdev->features &= ~NETIF_F_RXFCS;
4838 #define FT_CAP(f) MLX5_CAP_FLOWTABLE(mdev, flow_table_properties_nic_receive.f)
4839 if (FT_CAP(flow_modify_en) &&
4840 FT_CAP(modify_root) &&
4841 FT_CAP(identified_miss_table_mode) &&
4842 FT_CAP(flow_table_modify)) {
4843 #if IS_ENABLED(CONFIG_MLX5_CLS_ACT)
4844 netdev->hw_features |= NETIF_F_HW_TC;
4846 #ifdef CONFIG_MLX5_EN_ARFS
4847 netdev->hw_features |= NETIF_F_NTUPLE;
4851 netdev->features |= NETIF_F_HIGHDMA;
4852 netdev->features |= NETIF_F_HW_VLAN_STAG_FILTER;
4854 netdev->priv_flags |= IFF_UNICAST_FLT;
4856 mlx5e_set_netdev_dev_addr(netdev);
4857 mlx5e_ipsec_build_netdev(priv);
4858 mlx5e_tls_build_netdev(priv);
4861 void mlx5e_create_q_counters(struct mlx5e_priv *priv)
4863 u32 out[MLX5_ST_SZ_DW(alloc_q_counter_out)] = {};
4864 u32 in[MLX5_ST_SZ_DW(alloc_q_counter_in)] = {};
4865 struct mlx5_core_dev *mdev = priv->mdev;
4868 MLX5_SET(alloc_q_counter_in, in, opcode, MLX5_CMD_OP_ALLOC_Q_COUNTER);
4869 err = mlx5_cmd_exec_inout(mdev, alloc_q_counter, in, out);
4872 MLX5_GET(alloc_q_counter_out, out, counter_set_id);
4874 err = mlx5_cmd_exec_inout(mdev, alloc_q_counter, in, out);
4876 priv->drop_rq_q_counter =
4877 MLX5_GET(alloc_q_counter_out, out, counter_set_id);
4880 void mlx5e_destroy_q_counters(struct mlx5e_priv *priv)
4882 u32 in[MLX5_ST_SZ_DW(dealloc_q_counter_in)] = {};
4884 MLX5_SET(dealloc_q_counter_in, in, opcode,
4885 MLX5_CMD_OP_DEALLOC_Q_COUNTER);
4886 if (priv->q_counter) {
4887 MLX5_SET(dealloc_q_counter_in, in, counter_set_id,
4889 mlx5_cmd_exec_in(priv->mdev, dealloc_q_counter, in);
4892 if (priv->drop_rq_q_counter) {
4893 MLX5_SET(dealloc_q_counter_in, in, counter_set_id,
4894 priv->drop_rq_q_counter);
4895 mlx5_cmd_exec_in(priv->mdev, dealloc_q_counter, in);
4899 static int mlx5e_nic_init(struct mlx5_core_dev *mdev,
4900 struct net_device *netdev)
4902 struct mlx5e_priv *priv = netdev_priv(netdev);
4905 mlx5e_build_nic_params(priv, &priv->xsk, netdev->mtu);
4906 mlx5e_vxlan_set_netdev_info(priv);
4908 mlx5e_timestamp_init(priv);
4910 err = mlx5e_fs_init(priv);
4912 mlx5_core_err(mdev, "FS initialization failed, %d\n", err);
4916 err = mlx5e_ipsec_init(priv);
4918 mlx5_core_err(mdev, "IPSec initialization failed, %d\n", err);
4920 err = mlx5e_tls_init(priv);
4922 mlx5_core_err(mdev, "TLS initialization failed, %d\n", err);
4924 mlx5e_health_create_reporters(priv);
4928 static void mlx5e_nic_cleanup(struct mlx5e_priv *priv)
4930 mlx5e_health_destroy_reporters(priv);
4931 mlx5e_tls_cleanup(priv);
4932 mlx5e_ipsec_cleanup(priv);
4933 mlx5e_fs_cleanup(priv);
4936 static int mlx5e_init_nic_rx(struct mlx5e_priv *priv)
4938 struct mlx5_core_dev *mdev = priv->mdev;
4939 enum mlx5e_rx_res_features features;
4942 priv->rx_res = mlx5e_rx_res_alloc();
4946 mlx5e_create_q_counters(priv);
4948 err = mlx5e_open_drop_rq(priv, &priv->drop_rq);
4950 mlx5_core_err(mdev, "open drop rq failed, %d\n", err);
4951 goto err_destroy_q_counters;
4954 features = MLX5E_RX_RES_FEATURE_XSK | MLX5E_RX_RES_FEATURE_PTP;
4955 if (priv->channels.params.tunneled_offload_en)
4956 features |= MLX5E_RX_RES_FEATURE_INNER_FT;
4957 err = mlx5e_rx_res_init(priv->rx_res, priv->mdev, features,
4958 priv->max_nch, priv->drop_rq.rqn,
4959 &priv->channels.params.packet_merge,
4960 priv->channels.params.num_channels);
4962 goto err_close_drop_rq;
4964 err = mlx5e_create_flow_steering(priv);
4966 mlx5_core_warn(mdev, "create flow steering failed, %d\n", err);
4967 goto err_destroy_rx_res;
4970 err = mlx5e_tc_nic_init(priv);
4972 goto err_destroy_flow_steering;
4974 err = mlx5e_accel_init_rx(priv);
4976 goto err_tc_nic_cleanup;
4978 #ifdef CONFIG_MLX5_EN_ARFS
4979 priv->netdev->rx_cpu_rmap = mlx5_eq_table_get_rmap(priv->mdev);
4985 mlx5e_tc_nic_cleanup(priv);
4986 err_destroy_flow_steering:
4987 mlx5e_destroy_flow_steering(priv);
4989 mlx5e_rx_res_destroy(priv->rx_res);
4991 mlx5e_close_drop_rq(&priv->drop_rq);
4992 err_destroy_q_counters:
4993 mlx5e_destroy_q_counters(priv);
4994 mlx5e_rx_res_free(priv->rx_res);
4995 priv->rx_res = NULL;
4999 static void mlx5e_cleanup_nic_rx(struct mlx5e_priv *priv)
5001 mlx5e_accel_cleanup_rx(priv);
5002 mlx5e_tc_nic_cleanup(priv);
5003 mlx5e_destroy_flow_steering(priv);
5004 mlx5e_rx_res_destroy(priv->rx_res);
5005 mlx5e_close_drop_rq(&priv->drop_rq);
5006 mlx5e_destroy_q_counters(priv);
5007 mlx5e_rx_res_free(priv->rx_res);
5008 priv->rx_res = NULL;
5011 static int mlx5e_init_nic_tx(struct mlx5e_priv *priv)
5015 err = mlx5e_create_tises(priv);
5017 mlx5_core_warn(priv->mdev, "create tises failed, %d\n", err);
5021 mlx5e_dcbnl_initialize(priv);
5025 static void mlx5e_nic_enable(struct mlx5e_priv *priv)
5027 struct net_device *netdev = priv->netdev;
5028 struct mlx5_core_dev *mdev = priv->mdev;
5030 mlx5e_init_l2_addr(priv);
5032 /* Marking the link as currently not needed by the Driver */
5033 if (!netif_running(netdev))
5034 mlx5e_modify_admin_state(mdev, MLX5_PORT_DOWN);
5036 mlx5e_set_netdev_mtu_boundaries(priv);
5037 mlx5e_set_dev_port_mtu(priv);
5039 mlx5_lag_add_netdev(mdev, netdev);
5041 mlx5e_enable_async_events(priv);
5042 mlx5e_enable_blocking_events(priv);
5043 if (mlx5e_monitor_counter_supported(priv))
5044 mlx5e_monitor_counter_init(priv);
5046 mlx5e_hv_vhca_stats_create(priv);
5047 if (netdev->reg_state != NETREG_REGISTERED)
5049 mlx5e_dcbnl_init_app(priv);
5051 mlx5e_nic_set_rx_mode(priv);
5054 if (netif_running(netdev))
5056 udp_tunnel_nic_reset_ntf(priv->netdev);
5057 netif_device_attach(netdev);
5061 static void mlx5e_nic_disable(struct mlx5e_priv *priv)
5063 struct mlx5_core_dev *mdev = priv->mdev;
5065 if (priv->netdev->reg_state == NETREG_REGISTERED)
5066 mlx5e_dcbnl_delete_app(priv);
5069 if (netif_running(priv->netdev))
5070 mlx5e_close(priv->netdev);
5071 netif_device_detach(priv->netdev);
5074 mlx5e_nic_set_rx_mode(priv);
5076 mlx5e_hv_vhca_stats_destroy(priv);
5077 if (mlx5e_monitor_counter_supported(priv))
5078 mlx5e_monitor_counter_cleanup(priv);
5080 mlx5e_disable_blocking_events(priv);
5081 if (priv->en_trap) {
5082 mlx5e_deactivate_trap(priv);
5083 mlx5e_close_trap(priv->en_trap);
5084 priv->en_trap = NULL;
5086 mlx5e_disable_async_events(priv);
5087 mlx5_lag_remove_netdev(mdev, priv->netdev);
5088 mlx5_vxlan_reset_to_default(mdev->vxlan);
5091 int mlx5e_update_nic_rx(struct mlx5e_priv *priv)
5093 return mlx5e_refresh_tirs(priv, false, false);
5096 static const struct mlx5e_profile mlx5e_nic_profile = {
5097 .init = mlx5e_nic_init,
5098 .cleanup = mlx5e_nic_cleanup,
5099 .init_rx = mlx5e_init_nic_rx,
5100 .cleanup_rx = mlx5e_cleanup_nic_rx,
5101 .init_tx = mlx5e_init_nic_tx,
5102 .cleanup_tx = mlx5e_cleanup_nic_tx,
5103 .enable = mlx5e_nic_enable,
5104 .disable = mlx5e_nic_disable,
5105 .update_rx = mlx5e_update_nic_rx,
5106 .update_stats = mlx5e_stats_update_ndo_stats,
5107 .update_carrier = mlx5e_update_carrier,
5108 .rx_handlers = &mlx5e_rx_handlers_nic,
5109 .max_tc = MLX5E_MAX_NUM_TC,
5110 .rq_groups = MLX5E_NUM_RQ_GROUPS(XSK),
5111 .stats_grps = mlx5e_nic_stats_grps,
5112 .stats_grps_num = mlx5e_nic_stats_grps_num,
5113 .rx_ptp_support = true,
5117 mlx5e_calc_max_nch(struct mlx5_core_dev *mdev, struct net_device *netdev,
5118 const struct mlx5e_profile *profile)
5121 unsigned int max_nch, tmp;
5123 /* core resources */
5124 max_nch = mlx5e_get_max_num_channels(mdev);
5126 /* netdev rx queues */
5127 tmp = netdev->num_rx_queues / max_t(u8, profile->rq_groups, 1);
5128 max_nch = min_t(unsigned int, max_nch, tmp);
5130 /* netdev tx queues */
5131 tmp = netdev->num_tx_queues;
5132 if (mlx5_qos_is_supported(mdev))
5133 tmp -= mlx5e_qos_max_leaf_nodes(mdev);
5134 if (MLX5_CAP_GEN(mdev, ts_cqe_to_dest_cqn))
5135 tmp -= profile->max_tc;
5136 tmp = tmp / profile->max_tc;
5137 max_nch = min_t(unsigned int, max_nch, tmp);
5142 /* mlx5e generic netdev management API (move to en_common.c) */
5143 int mlx5e_priv_init(struct mlx5e_priv *priv,
5144 const struct mlx5e_profile *profile,
5145 struct net_device *netdev,
5146 struct mlx5_core_dev *mdev)
5150 priv->netdev = netdev;
5151 priv->msglevel = MLX5E_MSG_LEVEL;
5152 priv->max_nch = mlx5e_calc_max_nch(mdev, netdev, profile);
5153 priv->stats_nch = priv->max_nch;
5154 priv->max_opened_tc = 1;
5156 if (!alloc_cpumask_var(&priv->scratchpad.cpumask, GFP_KERNEL))
5159 mutex_init(&priv->state_lock);
5160 hash_init(priv->htb.qos_tc2node);
5161 INIT_WORK(&priv->update_carrier_work, mlx5e_update_carrier_work);
5162 INIT_WORK(&priv->set_rx_mode_work, mlx5e_set_rx_mode_work);
5163 INIT_WORK(&priv->tx_timeout_work, mlx5e_tx_timeout_work);
5164 INIT_WORK(&priv->update_stats_work, mlx5e_update_stats_work);
5166 priv->wq = create_singlethread_workqueue("mlx5e");
5168 goto err_free_cpumask;
5173 free_cpumask_var(priv->scratchpad.cpumask);
5178 void mlx5e_priv_cleanup(struct mlx5e_priv *priv)
5182 /* bail if change profile failed and also rollback failed */
5186 destroy_workqueue(priv->wq);
5187 free_cpumask_var(priv->scratchpad.cpumask);
5189 for (i = 0; i < priv->htb.max_qos_sqs; i++)
5190 kfree(priv->htb.qos_sq_stats[i]);
5191 kvfree(priv->htb.qos_sq_stats);
5193 if (priv->mqprio_rl) {
5194 mlx5e_mqprio_rl_cleanup(priv->mqprio_rl);
5195 mlx5e_mqprio_rl_free(priv->mqprio_rl);
5198 memset(priv, 0, sizeof(*priv));
5202 mlx5e_create_netdev(struct mlx5_core_dev *mdev, const struct mlx5e_profile *profile,
5203 unsigned int txqs, unsigned int rxqs)
5205 struct net_device *netdev;
5208 netdev = alloc_etherdev_mqs(sizeof(struct mlx5e_priv), txqs, rxqs);
5210 mlx5_core_err(mdev, "alloc_etherdev_mqs() failed\n");
5214 err = mlx5e_priv_init(netdev_priv(netdev), profile, netdev, mdev);
5216 mlx5_core_err(mdev, "mlx5e_priv_init failed, err=%d\n", err);
5217 goto err_free_netdev;
5220 netif_carrier_off(netdev);
5221 dev_net_set(netdev, mlx5_core_net(mdev));
5226 free_netdev(netdev);
5231 static void mlx5e_update_features(struct net_device *netdev)
5233 if (netdev->reg_state != NETREG_REGISTERED)
5234 return; /* features will be updated on netdev registration */
5237 netdev_update_features(netdev);
5241 static void mlx5e_reset_channels(struct net_device *netdev)
5243 netdev_reset_tc(netdev);
5246 int mlx5e_attach_netdev(struct mlx5e_priv *priv)
5248 const bool take_rtnl = priv->netdev->reg_state == NETREG_REGISTERED;
5249 const struct mlx5e_profile *profile = priv->profile;
5253 clear_bit(MLX5E_STATE_DESTROYING, &priv->state);
5255 /* max number of channels may have changed */
5256 max_nch = mlx5e_calc_max_nch(priv->mdev, priv->netdev, profile);
5257 if (priv->channels.params.num_channels > max_nch) {
5258 mlx5_core_warn(priv->mdev, "MLX5E: Reducing number of channels to %d\n", max_nch);
5259 /* Reducing the number of channels - RXFH has to be reset, and
5260 * mlx5e_num_channels_changed below will build the RQT.
5262 priv->netdev->priv_flags &= ~IFF_RXFH_CONFIGURED;
5263 priv->channels.params.num_channels = max_nch;
5264 if (priv->channels.params.mqprio.mode == TC_MQPRIO_MODE_CHANNEL) {
5265 mlx5_core_warn(priv->mdev, "MLX5E: Disabling MQPRIO channel mode\n");
5266 mlx5e_params_mqprio_reset(&priv->channels.params);
5269 if (max_nch != priv->max_nch) {
5270 mlx5_core_warn(priv->mdev,
5271 "MLX5E: Updating max number of channels from %u to %u\n",
5272 priv->max_nch, max_nch);
5273 priv->max_nch = max_nch;
5276 /* 1. Set the real number of queues in the kernel the first time.
5277 * 2. Set our default XPS cpumask.
5280 * rtnl_lock is required by netif_set_real_num_*_queues in case the
5281 * netdev has been registered by this point (if this function was called
5282 * in the reload or resume flow).
5286 err = mlx5e_num_channels_changed(priv);
5292 err = profile->init_tx(priv);
5296 err = profile->init_rx(priv);
5298 goto err_cleanup_tx;
5300 if (profile->enable)
5301 profile->enable(priv);
5303 mlx5e_update_features(priv->netdev);
5308 profile->cleanup_tx(priv);
5311 mlx5e_reset_channels(priv->netdev);
5312 set_bit(MLX5E_STATE_DESTROYING, &priv->state);
5313 cancel_work_sync(&priv->update_stats_work);
5317 void mlx5e_detach_netdev(struct mlx5e_priv *priv)
5319 const struct mlx5e_profile *profile = priv->profile;
5321 set_bit(MLX5E_STATE_DESTROYING, &priv->state);
5323 if (profile->disable)
5324 profile->disable(priv);
5325 flush_workqueue(priv->wq);
5327 profile->cleanup_rx(priv);
5328 profile->cleanup_tx(priv);
5329 mlx5e_reset_channels(priv->netdev);
5330 cancel_work_sync(&priv->update_stats_work);
5334 mlx5e_netdev_attach_profile(struct net_device *netdev, struct mlx5_core_dev *mdev,
5335 const struct mlx5e_profile *new_profile, void *new_ppriv)
5337 struct mlx5e_priv *priv = netdev_priv(netdev);
5340 err = mlx5e_priv_init(priv, new_profile, netdev, mdev);
5342 mlx5_core_err(mdev, "mlx5e_priv_init failed, err=%d\n", err);
5345 netif_carrier_off(netdev);
5346 priv->profile = new_profile;
5347 priv->ppriv = new_ppriv;
5348 err = new_profile->init(priv->mdev, priv->netdev);
5351 err = mlx5e_attach_netdev(priv);
5353 goto profile_cleanup;
5357 new_profile->cleanup(priv);
5359 mlx5e_priv_cleanup(priv);
5363 int mlx5e_netdev_change_profile(struct mlx5e_priv *priv,
5364 const struct mlx5e_profile *new_profile, void *new_ppriv)
5366 const struct mlx5e_profile *orig_profile = priv->profile;
5367 struct net_device *netdev = priv->netdev;
5368 struct mlx5_core_dev *mdev = priv->mdev;
5369 void *orig_ppriv = priv->ppriv;
5370 int err, rollback_err;
5372 /* cleanup old profile */
5373 mlx5e_detach_netdev(priv);
5374 priv->profile->cleanup(priv);
5375 mlx5e_priv_cleanup(priv);
5377 err = mlx5e_netdev_attach_profile(netdev, mdev, new_profile, new_ppriv);
5378 if (err) { /* roll back to original profile */
5379 netdev_warn(netdev, "%s: new profile init failed, %d\n", __func__, err);
5386 rollback_err = mlx5e_netdev_attach_profile(netdev, mdev, orig_profile, orig_ppriv);
5388 netdev_err(netdev, "%s: failed to rollback to orig profile, %d\n",
5389 __func__, rollback_err);
5393 void mlx5e_netdev_attach_nic_profile(struct mlx5e_priv *priv)
5395 mlx5e_netdev_change_profile(priv, &mlx5e_nic_profile, NULL);
5398 void mlx5e_destroy_netdev(struct mlx5e_priv *priv)
5400 struct net_device *netdev = priv->netdev;
5402 mlx5e_priv_cleanup(priv);
5403 free_netdev(netdev);
5406 static int mlx5e_resume(struct auxiliary_device *adev)
5408 struct mlx5_adev *edev = container_of(adev, struct mlx5_adev, adev);
5409 struct mlx5e_priv *priv = dev_get_drvdata(&adev->dev);
5410 struct net_device *netdev = priv->netdev;
5411 struct mlx5_core_dev *mdev = edev->mdev;
5414 if (netif_device_present(netdev))
5417 err = mlx5e_create_mdev_resources(mdev);
5421 err = mlx5e_attach_netdev(priv);
5423 mlx5e_destroy_mdev_resources(mdev);
5430 static int mlx5e_suspend(struct auxiliary_device *adev, pm_message_t state)
5432 struct mlx5e_priv *priv = dev_get_drvdata(&adev->dev);
5433 struct net_device *netdev = priv->netdev;
5434 struct mlx5_core_dev *mdev = priv->mdev;
5436 if (!netif_device_present(netdev))
5439 mlx5e_detach_netdev(priv);
5440 mlx5e_destroy_mdev_resources(mdev);
5444 static int mlx5e_probe(struct auxiliary_device *adev,
5445 const struct auxiliary_device_id *id)
5447 struct mlx5_adev *edev = container_of(adev, struct mlx5_adev, adev);
5448 const struct mlx5e_profile *profile = &mlx5e_nic_profile;
5449 struct mlx5_core_dev *mdev = edev->mdev;
5450 struct net_device *netdev;
5451 pm_message_t state = {};
5452 unsigned int txqs, rxqs, ptp_txqs = 0;
5453 struct mlx5e_priv *priv;
5458 if (MLX5_CAP_GEN(mdev, ts_cqe_to_dest_cqn))
5459 ptp_txqs = profile->max_tc;
5461 if (mlx5_qos_is_supported(mdev))
5462 qos_sqs = mlx5e_qos_max_leaf_nodes(mdev);
5464 nch = mlx5e_get_max_num_channels(mdev);
5465 txqs = nch * profile->max_tc + ptp_txqs + qos_sqs;
5466 rxqs = nch * profile->rq_groups;
5467 netdev = mlx5e_create_netdev(mdev, profile, txqs, rxqs);
5469 mlx5_core_err(mdev, "mlx5e_create_netdev failed\n");
5473 mlx5e_build_nic_netdev(netdev);
5475 priv = netdev_priv(netdev);
5476 dev_set_drvdata(&adev->dev, priv);
5478 priv->profile = profile;
5481 err = mlx5e_devlink_port_register(priv);
5483 mlx5_core_err(mdev, "mlx5e_devlink_port_register failed, %d\n", err);
5484 goto err_destroy_netdev;
5487 err = profile->init(mdev, netdev);
5489 mlx5_core_err(mdev, "mlx5e_nic_profile init failed, %d\n", err);
5490 goto err_devlink_cleanup;
5493 err = mlx5e_resume(adev);
5495 mlx5_core_err(mdev, "mlx5e_resume failed, %d\n", err);
5496 goto err_profile_cleanup;
5499 err = register_netdev(netdev);
5501 mlx5_core_err(mdev, "register_netdev failed, %d\n", err);
5505 mlx5e_devlink_port_type_eth_set(priv);
5507 mlx5e_dcbnl_init_app(priv);
5508 mlx5_uplink_netdev_set(mdev, netdev);
5512 mlx5e_suspend(adev, state);
5513 err_profile_cleanup:
5514 profile->cleanup(priv);
5515 err_devlink_cleanup:
5516 mlx5e_devlink_port_unregister(priv);
5518 mlx5e_destroy_netdev(priv);
5522 static void mlx5e_remove(struct auxiliary_device *adev)
5524 struct mlx5e_priv *priv = dev_get_drvdata(&adev->dev);
5525 pm_message_t state = {};
5527 mlx5e_dcbnl_delete_app(priv);
5528 unregister_netdev(priv->netdev);
5529 mlx5e_suspend(adev, state);
5530 priv->profile->cleanup(priv);
5531 mlx5e_devlink_port_unregister(priv);
5532 mlx5e_destroy_netdev(priv);
5535 static const struct auxiliary_device_id mlx5e_id_table[] = {
5536 { .name = MLX5_ADEV_NAME ".eth", },
5540 MODULE_DEVICE_TABLE(auxiliary, mlx5e_id_table);
5542 static struct auxiliary_driver mlx5e_driver = {
5544 .probe = mlx5e_probe,
5545 .remove = mlx5e_remove,
5546 .suspend = mlx5e_suspend,
5547 .resume = mlx5e_resume,
5548 .id_table = mlx5e_id_table,
5551 int mlx5e_init(void)
5555 mlx5e_ipsec_build_inverse_table();
5556 mlx5e_build_ptys2ethtool_map();
5557 ret = auxiliary_driver_register(&mlx5e_driver);
5561 ret = mlx5e_rep_init();
5563 auxiliary_driver_unregister(&mlx5e_driver);
5567 void mlx5e_cleanup(void)
5569 mlx5e_rep_cleanup();
5570 auxiliary_driver_unregister(&mlx5e_driver);