drivers/net/ethernet/mellanox/mlx5/core/en_main.c

   1 /*
   2  * Copyright (c) 2015-2016, Mellanox Technologies. All rights reserved.
   3  *
   4  * This software is available to you under a choice of one of two
   5  * licenses.  You may choose to be licensed under the terms of the GNU
   6  * General Public License (GPL) Version 2, available from the file
   7  * COPYING in the main directory of this source tree, or the
   8  * OpenIB.org BSD license below:
   9  *
  10  *     Redistribution and use in source and binary forms, with or
  11  *     without modification, are permitted provided that the following
  12  *     conditions are met:
  13  *
  14  *      - Redistributions of source code must retain the above
  15  *        copyright notice, this list of conditions and the following
  16  *        disclaimer.
  17  *
  18  *      - Redistributions in binary form must reproduce the above
  19  *        copyright notice, this list of conditions and the following
  20  *        disclaimer in the documentation and/or other materials
  21  *        provided with the distribution.
  22  *
  23  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  24  * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  25  * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
  26  * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
  27  * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
  28  * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
  29  * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
  30  * SOFTWARE.
  31  */
  32
  33 #include <net/tc_act/tc_gact.h>
  34 #include <net/pkt_cls.h>
  35 #include <linux/mlx5/fs.h>
  36 #include <net/vxlan.h>
  37 #include <linux/bpf.h>
  38 #include <net/page_pool.h>
  39 #include "eswitch.h"
  40 #include "en.h"
  41 #include "en_tc.h"
  42 #include "en_rep.h"
  43 #include "en_accel/ipsec.h"
  44 #include "en_accel/ipsec_rxtx.h"
  45 #include "en_accel/tls.h"
  46 #include "accel/ipsec.h"
  47 #include "accel/tls.h"
  48 #include "vxlan.h"
  49 #include "en/port.h"
  50
  51 struct mlx5e_rq_param {
  52         u32                     rqc[MLX5_ST_SZ_DW(rqc)];
  53         struct mlx5_wq_param    wq;
  54         struct mlx5e_rq_frags_info frags_info;
  55 };
  56
  57 struct mlx5e_sq_param {
  58         u32                        sqc[MLX5_ST_SZ_DW(sqc)];
  59         struct mlx5_wq_param       wq;
  60 };
  61
  62 struct mlx5e_cq_param {
  63         u32                        cqc[MLX5_ST_SZ_DW(cqc)];
  64         struct mlx5_wq_param       wq;
  65         u16                        eq_ix;
  66         u8                         cq_period_mode;
  67 };
  68
  69 struct mlx5e_channel_param {
  70         struct mlx5e_rq_param      rq;
  71         struct mlx5e_sq_param      sq;
  72         struct mlx5e_sq_param      xdp_sq;
  73         struct mlx5e_sq_param      icosq;
  74         struct mlx5e_cq_param      rx_cq;
  75         struct mlx5e_cq_param      tx_cq;
  76         struct mlx5e_cq_param      icosq_cq;
  77 };
  78
  79 bool mlx5e_check_fragmented_striding_rq_cap(struct mlx5_core_dev *mdev)
  80 {
  81         bool striding_rq_umr = MLX5_CAP_GEN(mdev, striding_rq) &&
  82                 MLX5_CAP_GEN(mdev, umr_ptr_rlky) &&
  83                 MLX5_CAP_ETH(mdev, reg_umr_sq);
  84         u16 max_wqe_sz_cap = MLX5_CAP_GEN(mdev, max_wqe_sz_sq);
  85         bool inline_umr = MLX5E_UMR_WQE_INLINE_SZ <= max_wqe_sz_cap;
  86
  87         if (!striding_rq_umr)
  88                 return false;
  89         if (!inline_umr) {
  90                 mlx5_core_warn(mdev, "Cannot support Striding RQ: UMR WQE size (%d) exceeds maximum supported (%d).\n",
  91                                (int)MLX5E_UMR_WQE_INLINE_SZ, max_wqe_sz_cap);
  92                 return false;
  93         }
  94         return true;
  95 }
  96
  97 static u32 mlx5e_rx_get_linear_frag_sz(struct mlx5e_params *params)
  98 {
  99         if (!params->xdp_prog) {
 100                 u16 hw_mtu = MLX5E_SW2HW_MTU(params, params->sw_mtu);
 101                 u16 rq_headroom = MLX5_RX_HEADROOM + NET_IP_ALIGN;
 102
 103                 return MLX5_SKB_FRAG_SZ(rq_headroom + hw_mtu);
 104         }
 105
 106         return PAGE_SIZE;
 107 }
 108
 109 static u8 mlx5e_mpwqe_log_pkts_per_wqe(struct mlx5e_params *params)
 110 {
 111         u32 linear_frag_sz = mlx5e_rx_get_linear_frag_sz(params);
 112
 113         return MLX5_MPWRQ_LOG_WQE_SZ - order_base_2(linear_frag_sz);
 114 }
 115
 116 static bool mlx5e_rx_is_linear_skb(struct mlx5_core_dev *mdev,
 117                                    struct mlx5e_params *params)
 118 {
 119         u32 frag_sz = mlx5e_rx_get_linear_frag_sz(params);
 120
 121         return !params->lro_en && frag_sz <= PAGE_SIZE;
 122 }
 123
 124 static bool mlx5e_rx_mpwqe_is_linear_skb(struct mlx5_core_dev *mdev,
 125                                          struct mlx5e_params *params)
 126 {
 127         u32 frag_sz = mlx5e_rx_get_linear_frag_sz(params);
 128         s8 signed_log_num_strides_param;
 129         u8 log_num_strides;
 130
 131         if (!mlx5e_rx_is_linear_skb(mdev, params))
 132                 return false;
 133
 134         if (MLX5_CAP_GEN(mdev, ext_stride_num_range))
 135                 return true;
 136
 137         log_num_strides = MLX5_MPWRQ_LOG_WQE_SZ - order_base_2(frag_sz);
 138         signed_log_num_strides_param =
 139                 (s8)log_num_strides - MLX5_MPWQE_LOG_NUM_STRIDES_BASE;
 140
 141         return signed_log_num_strides_param >= 0;
 142 }
 143
 144 static u8 mlx5e_mpwqe_get_log_rq_size(struct mlx5e_params *params)
 145 {
 146         if (params->log_rq_mtu_frames <
 147             mlx5e_mpwqe_log_pkts_per_wqe(params) + MLX5E_PARAMS_MINIMUM_LOG_RQ_SIZE_MPW)
 148                 return MLX5E_PARAMS_MINIMUM_LOG_RQ_SIZE_MPW;
 149
 150         return params->log_rq_mtu_frames - mlx5e_mpwqe_log_pkts_per_wqe(params);
 151 }
 152
 153 static u8 mlx5e_mpwqe_get_log_stride_size(struct mlx5_core_dev *mdev,
 154                                           struct mlx5e_params *params)
 155 {
 156         if (mlx5e_rx_mpwqe_is_linear_skb(mdev, params))
 157                 return order_base_2(mlx5e_rx_get_linear_frag_sz(params));
 158
 159         return MLX5E_MPWQE_STRIDE_SZ(mdev,
 160                 MLX5E_GET_PFLAG(params, MLX5E_PFLAG_RX_CQE_COMPRESS));
 161 }
 162
 163 static u8 mlx5e_mpwqe_get_log_num_strides(struct mlx5_core_dev *mdev,
 164                                           struct mlx5e_params *params)
 165 {
 166         return MLX5_MPWRQ_LOG_WQE_SZ -
 167                 mlx5e_mpwqe_get_log_stride_size(mdev, params);
 168 }
 169
 170 static u16 mlx5e_get_rq_headroom(struct mlx5_core_dev *mdev,
 171                                  struct mlx5e_params *params)
 172 {
 173         u16 linear_rq_headroom = params->xdp_prog ?
 174                 XDP_PACKET_HEADROOM : MLX5_RX_HEADROOM;
 175         bool is_linear_skb;
 176
 177         linear_rq_headroom += NET_IP_ALIGN;
 178
 179         is_linear_skb = (params->rq_wq_type == MLX5_WQ_TYPE_CYCLIC) ?
 180                 mlx5e_rx_is_linear_skb(mdev, params) :
 181                 mlx5e_rx_mpwqe_is_linear_skb(mdev, params);
 182
 183         return is_linear_skb ? linear_rq_headroom : 0;
 184 }
 185
 186 void mlx5e_init_rq_type_params(struct mlx5_core_dev *mdev,
 187                                struct mlx5e_params *params)
 188 {
 189         params->lro_wqe_sz = MLX5E_PARAMS_DEFAULT_LRO_WQE_SZ;
 190         params->log_rq_mtu_frames = is_kdump_kernel() ?
 191                 MLX5E_PARAMS_MINIMUM_LOG_RQ_SIZE :
 192                 MLX5E_PARAMS_DEFAULT_LOG_RQ_SIZE;
 193
 194         mlx5_core_info(mdev, "MLX5E: StrdRq(%d) RqSz(%ld) StrdSz(%ld) RxCqeCmprss(%d)\n",
 195                        params->rq_wq_type == MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ,
 196                        params->rq_wq_type == MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ ?
 197                        BIT(mlx5e_mpwqe_get_log_rq_size(params)) :
 198                        BIT(params->log_rq_mtu_frames),
 199                        BIT(mlx5e_mpwqe_get_log_stride_size(mdev, params)),
 200                        MLX5E_GET_PFLAG(params, MLX5E_PFLAG_RX_CQE_COMPRESS));
 201 }
 202
 203 bool mlx5e_striding_rq_possible(struct mlx5_core_dev *mdev,
 204                                 struct mlx5e_params *params)
 205 {
 206         return mlx5e_check_fragmented_striding_rq_cap(mdev) &&
 207                 !MLX5_IPSEC_DEV(mdev) &&
 208                 !(params->xdp_prog && !mlx5e_rx_mpwqe_is_linear_skb(mdev, params));
 209 }
 210
 211 void mlx5e_set_rq_type(struct mlx5_core_dev *mdev, struct mlx5e_params *params)
 212 {
 213         params->rq_wq_type = mlx5e_striding_rq_possible(mdev, params) &&
 214                 MLX5E_GET_PFLAG(params, MLX5E_PFLAG_RX_STRIDING_RQ) ?
 215                 MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ :
 216                 MLX5_WQ_TYPE_CYCLIC;
 217 }
 218
 219 static void mlx5e_update_carrier(struct mlx5e_priv *priv)
 220 {
 221         struct mlx5_core_dev *mdev = priv->mdev;
 222         u8 port_state;
 223
 224         port_state = mlx5_query_vport_state(mdev,
 225                                             MLX5_QUERY_VPORT_STATE_IN_OP_MOD_VNIC_VPORT,
 226                                             0);
 227
 228         if (port_state == VPORT_STATE_UP) {
 229                 netdev_info(priv->netdev, "Link up\n");
 230                 netif_carrier_on(priv->netdev);
 231         } else {
 232                 netdev_info(priv->netdev, "Link down\n");
 233                 netif_carrier_off(priv->netdev);
 234         }
 235 }
 236
 237 static void mlx5e_update_carrier_work(struct work_struct *work)
 238 {
 239         struct mlx5e_priv *priv = container_of(work, struct mlx5e_priv,
 240                                                update_carrier_work);
 241
 242         mutex_lock(&priv->state_lock);
 243         if (test_bit(MLX5E_STATE_OPENED, &priv->state))
 244                 if (priv->profile->update_carrier)
 245                         priv->profile->update_carrier(priv);
 246         mutex_unlock(&priv->state_lock);
 247 }
 248
 249 void mlx5e_update_stats(struct mlx5e_priv *priv)
 250 {
 251         int i;
 252
 253         for (i = mlx5e_num_stats_grps - 1; i >= 0; i--)
 254                 if (mlx5e_stats_grps[i].update_stats)
 255                         mlx5e_stats_grps[i].update_stats(priv);
 256 }
 257
 258 static void mlx5e_update_ndo_stats(struct mlx5e_priv *priv)
 259 {
 260         int i;
 261
 262         for (i = mlx5e_num_stats_grps - 1; i >= 0; i--)
 263                 if (mlx5e_stats_grps[i].update_stats_mask &
 264                     MLX5E_NDO_UPDATE_STATS)
 265                         mlx5e_stats_grps[i].update_stats(priv);
 266 }
 267
 268 void mlx5e_update_stats_work(struct work_struct *work)
 269 {
 270         struct delayed_work *dwork = to_delayed_work(work);
 271         struct mlx5e_priv *priv = container_of(dwork, struct mlx5e_priv,
 272                                                update_stats_work);
 273         mutex_lock(&priv->state_lock);
 274         if (test_bit(MLX5E_STATE_OPENED, &priv->state)) {
 275                 priv->profile->update_stats(priv);
 276                 queue_delayed_work(priv->wq, dwork,
 277                                    msecs_to_jiffies(MLX5E_UPDATE_STATS_INTERVAL));
 278         }
 279         mutex_unlock(&priv->state_lock);
 280 }
 281
 282 static void mlx5e_async_event(struct mlx5_core_dev *mdev, void *vpriv,
 283                               enum mlx5_dev_event event, unsigned long param)
 284 {
 285         struct mlx5e_priv *priv = vpriv;
 286
 287         if (!test_bit(MLX5E_STATE_ASYNC_EVENTS_ENABLED, &priv->state))
 288                 return;
 289
 290         switch (event) {
 291         case MLX5_DEV_EVENT_PORT_UP:
 292         case MLX5_DEV_EVENT_PORT_DOWN:
 293                 queue_work(priv->wq, &priv->update_carrier_work);
 294                 break;
 295         default:
 296                 break;
 297         }
 298 }
 299
 300 static void mlx5e_enable_async_events(struct mlx5e_priv *priv)
 301 {
 302         set_bit(MLX5E_STATE_ASYNC_EVENTS_ENABLED, &priv->state);
 303 }
 304
 305 static void mlx5e_disable_async_events(struct mlx5e_priv *priv)
 306 {
 307         clear_bit(MLX5E_STATE_ASYNC_EVENTS_ENABLED, &priv->state);
 308         synchronize_irq(pci_irq_vector(priv->mdev->pdev, MLX5_EQ_VEC_ASYNC));
 309 }
 310
 311 static inline void mlx5e_build_umr_wqe(struct mlx5e_rq *rq,
 312                                        struct mlx5e_icosq *sq,
 313                                        struct mlx5e_umr_wqe *wqe)
 314 {
 315         struct mlx5_wqe_ctrl_seg      *cseg = &wqe->ctrl;
 316         struct mlx5_wqe_umr_ctrl_seg *ucseg = &wqe->uctrl;
 317         u8 ds_cnt = DIV_ROUND_UP(MLX5E_UMR_WQE_INLINE_SZ, MLX5_SEND_WQE_DS);
 318
 319         cseg->qpn_ds    = cpu_to_be32((sq->sqn << MLX5_WQE_CTRL_QPN_SHIFT) |
 320                                       ds_cnt);
 321         cseg->fm_ce_se  = MLX5_WQE_CTRL_CQ_UPDATE;
 322         cseg->imm       = rq->mkey_be;
 323
 324         ucseg->flags = MLX5_UMR_TRANSLATION_OFFSET_EN | MLX5_UMR_INLINE;
 325         ucseg->xlt_octowords =
 326                 cpu_to_be16(MLX5_MTT_OCTW(MLX5_MPWRQ_PAGES_PER_WQE));
 327         ucseg->mkey_mask     = cpu_to_be64(MLX5_MKEY_MASK_FREE);
 328 }
 329
 330 static u32 mlx5e_rqwq_get_size(struct mlx5e_rq *rq)
 331 {
 332         switch (rq->wq_type) {
 333         case MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ:
 334                 return mlx5_wq_ll_get_size(&rq->mpwqe.wq);
 335         default:
 336                 return mlx5_wq_cyc_get_size(&rq->wqe.wq);
 337         }
 338 }
 339
 340 static u32 mlx5e_rqwq_get_cur_sz(struct mlx5e_rq *rq)
 341 {
 342         switch (rq->wq_type) {
 343         case MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ:
 344                 return rq->mpwqe.wq.cur_sz;
 345         default:
 346                 return rq->wqe.wq.cur_sz;
 347         }
 348 }
 349
 350 static int mlx5e_rq_alloc_mpwqe_info(struct mlx5e_rq *rq,
 351                                      struct mlx5e_channel *c)
 352 {
 353         int wq_sz = mlx5_wq_ll_get_size(&rq->mpwqe.wq);
 354
 355         rq->mpwqe.info = kzalloc_node(wq_sz * sizeof(*rq->mpwqe.info),
 356                                       GFP_KERNEL, cpu_to_node(c->cpu));
 357         if (!rq->mpwqe.info)
 358                 return -ENOMEM;
 359
 360         mlx5e_build_umr_wqe(rq, &c->icosq, &rq->mpwqe.umr_wqe);
 361
 362         return 0;
 363 }
 364
 365 static int mlx5e_create_umr_mkey(struct mlx5_core_dev *mdev,
 366                                  u64 npages, u8 page_shift,
 367                                  struct mlx5_core_mkey *umr_mkey)
 368 {
 369         int inlen = MLX5_ST_SZ_BYTES(create_mkey_in);
 370         void *mkc;
 371         u32 *in;
 372         int err;
 373
 374         in = kvzalloc(inlen, GFP_KERNEL);
 375         if (!in)
 376                 return -ENOMEM;
 377
 378         mkc = MLX5_ADDR_OF(create_mkey_in, in, memory_key_mkey_entry);
 379
 380         MLX5_SET(mkc, mkc, free, 1);
 381         MLX5_SET(mkc, mkc, umr_en, 1);
 382         MLX5_SET(mkc, mkc, lw, 1);
 383         MLX5_SET(mkc, mkc, lr, 1);
 384         MLX5_SET(mkc, mkc, access_mode_1_0, MLX5_MKC_ACCESS_MODE_MTT);
 385
 386         MLX5_SET(mkc, mkc, qpn, 0xffffff);
 387         MLX5_SET(mkc, mkc, pd, mdev->mlx5e_res.pdn);
 388         MLX5_SET64(mkc, mkc, len, npages << page_shift);
 389         MLX5_SET(mkc, mkc, translations_octword_size,
 390                  MLX5_MTT_OCTW(npages));
 391         MLX5_SET(mkc, mkc, log_page_size, page_shift);
 392
 393         err = mlx5_core_create_mkey(mdev, umr_mkey, in, inlen);
 394
 395         kvfree(in);
 396         return err;
 397 }
 398
 399 static int mlx5e_create_rq_umr_mkey(struct mlx5_core_dev *mdev, struct mlx5e_rq *rq)
 400 {
 401         u64 num_mtts = MLX5E_REQUIRED_MTTS(mlx5_wq_ll_get_size(&rq->mpwqe.wq));
 402
 403         return mlx5e_create_umr_mkey(mdev, num_mtts, PAGE_SHIFT, &rq->umr_mkey);
 404 }
 405
 406 static inline u64 mlx5e_get_mpwqe_offset(struct mlx5e_rq *rq, u16 wqe_ix)
 407 {
 408         return (wqe_ix << MLX5E_LOG_ALIGNED_MPWQE_PPW) << PAGE_SHIFT;
 409 }
 410
 411 static void mlx5e_init_frags_partition(struct mlx5e_rq *rq)
 412 {
 413         struct mlx5e_wqe_frag_info next_frag, *prev;
 414         int i;
 415
 416         next_frag.di = &rq->wqe.di[0];
 417         next_frag.offset = 0;
 418         prev = NULL;
 419
 420         for (i = 0; i < mlx5_wq_cyc_get_size(&rq->wqe.wq); i++) {
 421                 struct mlx5e_rq_frag_info *frag_info = &rq->wqe.info.arr[0];
 422                 struct mlx5e_wqe_frag_info *frag =
 423                         &rq->wqe.frags[i << rq->wqe.info.log_num_frags];
 424                 int f;
 425
 426                 for (f = 0; f < rq->wqe.info.num_frags; f++, frag++) {
 427                         if (next_frag.offset + frag_info[f].frag_stride > PAGE_SIZE) {
 428                                 next_frag.di++;
 429                                 next_frag.offset = 0;
 430                                 if (prev)
 431                                         prev->last_in_page = true;
 432                         }
 433                         *frag = next_frag;
 434
 435                         /* prepare next */
 436                         next_frag.offset += frag_info[f].frag_stride;
 437                         prev = frag;
 438                 }
 439         }
 440
 441         if (prev)
 442                 prev->last_in_page = true;
 443 }
 444
 445 static int mlx5e_init_di_list(struct mlx5e_rq *rq,
 446                               struct mlx5e_params *params,
 447                               int wq_sz, int cpu)
 448 {
 449         int len = wq_sz << rq->wqe.info.log_num_frags;
 450
 451         rq->wqe.di = kvzalloc_node(len * sizeof(*rq->wqe.di),
 452                                    GFP_KERNEL, cpu_to_node(cpu));
 453         if (!rq->wqe.di)
 454                 return -ENOMEM;
 455
 456         mlx5e_init_frags_partition(rq);
 457
 458         return 0;
 459 }
 460
 461 static void mlx5e_free_di_list(struct mlx5e_rq *rq)
 462 {
 463         kvfree(rq->wqe.di);
 464 }
 465
 466 static int mlx5e_alloc_rq(struct mlx5e_channel *c,
 467                           struct mlx5e_params *params,
 468                           struct mlx5e_rq_param *rqp,
 469                           struct mlx5e_rq *rq)
 470 {
 471         struct page_pool_params pp_params = { 0 };
 472         struct mlx5_core_dev *mdev = c->mdev;
 473         void *rqc = rqp->rqc;
 474         void *rqc_wq = MLX5_ADDR_OF(rqc, rqc, wq);
 475         u32 pool_size;
 476         int wq_sz;
 477         int err;
 478         int i;
 479
 480         rqp->wq.db_numa_node = cpu_to_node(c->cpu);
 481
 482         rq->wq_type = params->rq_wq_type;
 483         rq->pdev    = c->pdev;
 484         rq->netdev  = c->netdev;
 485         rq->tstamp  = c->tstamp;
 486         rq->clock   = &mdev->clock;
 487         rq->channel = c;
 488         rq->ix      = c->ix;
 489         rq->mdev    = mdev;
 490         rq->hw_mtu  = MLX5E_SW2HW_MTU(params, params->sw_mtu);
 491         rq->stats   = &c->priv->channel_stats[c->ix].rq;
 492
 493         rq->xdp_prog = params->xdp_prog ? bpf_prog_inc(params->xdp_prog) : NULL;
 494         if (IS_ERR(rq->xdp_prog)) {
 495                 err = PTR_ERR(rq->xdp_prog);
 496                 rq->xdp_prog = NULL;
 497                 goto err_rq_wq_destroy;
 498         }
 499
 500         err = xdp_rxq_info_reg(&rq->xdp_rxq, rq->netdev, rq->ix);
 501         if (err < 0)
 502                 goto err_rq_wq_destroy;
 503
 504         rq->buff.map_dir = rq->xdp_prog ? DMA_BIDIRECTIONAL : DMA_FROM_DEVICE;
 505         rq->buff.headroom = mlx5e_get_rq_headroom(mdev, params);
 506         pool_size = 1 << params->log_rq_mtu_frames;
 507
 508         switch (rq->wq_type) {
 509         case MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ:
 510                 err = mlx5_wq_ll_create(mdev, &rqp->wq, rqc_wq, &rq->mpwqe.wq,
 511                                         &rq->wq_ctrl);
 512                 if (err)
 513                         return err;
 514
 515                 rq->mpwqe.wq.db = &rq->mpwqe.wq.db[MLX5_RCV_DBR];
 516
 517                 wq_sz = mlx5_wq_ll_get_size(&rq->mpwqe.wq);
 518
 519                 pool_size = MLX5_MPWRQ_PAGES_PER_WQE << mlx5e_mpwqe_get_log_rq_size(params);
 520
 521                 rq->post_wqes = mlx5e_post_rx_mpwqes;
 522                 rq->dealloc_wqe = mlx5e_dealloc_rx_mpwqe;
 523
 524                 rq->handle_rx_cqe = c->priv->profile->rx_handlers.handle_rx_cqe_mpwqe;
 525 #ifdef CONFIG_MLX5_EN_IPSEC
 526                 if (MLX5_IPSEC_DEV(mdev)) {
 527                         err = -EINVAL;
 528                         netdev_err(c->netdev, "MPWQE RQ with IPSec offload not supported\n");
 529                         goto err_rq_wq_destroy;
 530                 }
 531 #endif
 532                 if (!rq->handle_rx_cqe) {
 533                         err = -EINVAL;
 534                         netdev_err(c->netdev, "RX handler of MPWQE RQ is not set, err %d\n", err);
 535                         goto err_rq_wq_destroy;
 536                 }
 537
 538                 rq->mpwqe.skb_from_cqe_mpwrq =
 539                         mlx5e_rx_mpwqe_is_linear_skb(mdev, params) ?
 540                         mlx5e_skb_from_cqe_mpwrq_linear :
 541                         mlx5e_skb_from_cqe_mpwrq_nonlinear;
 542                 rq->mpwqe.log_stride_sz = mlx5e_mpwqe_get_log_stride_size(mdev, params);
 543                 rq->mpwqe.num_strides = BIT(mlx5e_mpwqe_get_log_num_strides(mdev, params));
 544
 545                 err = mlx5e_create_rq_umr_mkey(mdev, rq);
 546                 if (err)
 547                         goto err_rq_wq_destroy;
 548                 rq->mkey_be = cpu_to_be32(rq->umr_mkey.key);
 549
 550                 err = mlx5e_rq_alloc_mpwqe_info(rq, c);
 551                 if (err)
 552                         goto err_free;
 553                 break;
 554         default: /* MLX5_WQ_TYPE_CYCLIC */
 555                 err = mlx5_wq_cyc_create(mdev, &rqp->wq, rqc_wq, &rq->wqe.wq,
 556                                          &rq->wq_ctrl);
 557                 if (err)
 558                         return err;
 559
 560                 rq->wqe.wq.db = &rq->wqe.wq.db[MLX5_RCV_DBR];
 561
 562                 wq_sz = mlx5_wq_cyc_get_size(&rq->wqe.wq);
 563
 564                 rq->wqe.info = rqp->frags_info;
 565                 rq->wqe.frags =
 566                         kvzalloc_node((wq_sz << rq->wqe.info.log_num_frags) *
 567                                       sizeof(*rq->wqe.frags),
 568                                       GFP_KERNEL, cpu_to_node(c->cpu));
 569                 if (!rq->wqe.frags)
 570                         goto err_free;
 571
 572                 err = mlx5e_init_di_list(rq, params, wq_sz, c->cpu);
 573                 if (err)
 574                         goto err_free;
 575                 rq->post_wqes = mlx5e_post_rx_wqes;
 576                 rq->dealloc_wqe = mlx5e_dealloc_rx_wqe;
 577
 578 #ifdef CONFIG_MLX5_EN_IPSEC
 579                 if (c->priv->ipsec)
 580                         rq->handle_rx_cqe = mlx5e_ipsec_handle_rx_cqe;
 581                 else
 582 #endif
 583                         rq->handle_rx_cqe = c->priv->profile->rx_handlers.handle_rx_cqe;
 584                 if (!rq->handle_rx_cqe) {
 585                         err = -EINVAL;
 586                         netdev_err(c->netdev, "RX handler of RQ is not set, err %d\n", err);
 587                         goto err_free;
 588                 }
 589
 590                 rq->wqe.skb_from_cqe = mlx5e_rx_is_linear_skb(mdev, params) ?
 591                         mlx5e_skb_from_cqe_linear :
 592                         mlx5e_skb_from_cqe_nonlinear;
 593                 rq->mkey_be = c->mkey_be;
 594         }
 595
 596         /* Create a page_pool and register it with rxq */
 597         pp_params.order     = 0;
 598         pp_params.flags     = 0; /* No-internal DMA mapping in page_pool */
 599         pp_params.pool_size = pool_size;
 600         pp_params.nid       = cpu_to_node(c->cpu);
 601         pp_params.dev       = c->pdev;
 602         pp_params.dma_dir   = rq->buff.map_dir;
 603
 604         /* page_pool can be used even when there is no rq->xdp_prog,
 605          * given page_pool does not handle DMA mapping there is no
 606          * required state to clear. And page_pool gracefully handle
 607          * elevated refcnt.
 608          */
 609         rq->page_pool = page_pool_create(&pp_params);
 610         if (IS_ERR(rq->page_pool)) {
 611                 err = PTR_ERR(rq->page_pool);
 612                 rq->page_pool = NULL;
 613                 goto err_free;
 614         }
 615         err = xdp_rxq_info_reg_mem_model(&rq->xdp_rxq,
 616                                          MEM_TYPE_PAGE_POOL, rq->page_pool);
 617         if (err)
 618                 goto err_free;
 619
 620         for (i = 0; i < wq_sz; i++) {
 621                 if (rq->wq_type == MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ) {
 622                         struct mlx5e_rx_wqe_ll *wqe =
 623                                 mlx5_wq_ll_get_wqe(&rq->mpwqe.wq, i);
 624                         u32 byte_count =
 625                                 rq->mpwqe.num_strides << rq->mpwqe.log_stride_sz;
 626                         u64 dma_offset = mlx5e_get_mpwqe_offset(rq, i);
 627
 628                         wqe->data[0].addr = cpu_to_be64(dma_offset + rq->buff.headroom);
 629                         wqe->data[0].byte_count = cpu_to_be32(byte_count);
 630                         wqe->data[0].lkey = rq->mkey_be;
 631                 } else {
 632                         struct mlx5e_rx_wqe_cyc *wqe =
 633                                 mlx5_wq_cyc_get_wqe(&rq->wqe.wq, i);
 634                         int f;
 635
 636                         for (f = 0; f < rq->wqe.info.num_frags; f++) {
 637                                 u32 frag_size = rq->wqe.info.arr[f].frag_size |
 638                                         MLX5_HW_START_PADDING;
 639
 640                                 wqe->data[f].byte_count = cpu_to_be32(frag_size);
 641                                 wqe->data[f].lkey = rq->mkey_be;
 642                         }
 643                         /* check if num_frags is not a pow of two */
 644                         if (rq->wqe.info.num_frags < (1 << rq->wqe.info.log_num_frags)) {
 645                                 wqe->data[f].byte_count = 0;
 646                                 wqe->data[f].lkey = cpu_to_be32(MLX5_INVALID_LKEY);
 647                                 wqe->data[f].addr = 0;
 648                         }
 649                 }
 650         }
 651
 652         INIT_WORK(&rq->dim.work, mlx5e_rx_dim_work);
 653
 654         switch (params->rx_cq_moderation.cq_period_mode) {
 655         case MLX5_CQ_PERIOD_MODE_START_FROM_CQE:
 656                 rq->dim.mode = NET_DIM_CQ_PERIOD_MODE_START_FROM_CQE;
 657                 break;
 658         case MLX5_CQ_PERIOD_MODE_START_FROM_EQE:
 659         default:
 660                 rq->dim.mode = NET_DIM_CQ_PERIOD_MODE_START_FROM_EQE;
 661         }
 662
 663         rq->page_cache.head = 0;
 664         rq->page_cache.tail = 0;
 665
 666         return 0;
 667
 668 err_free:
 669         switch (rq->wq_type) {
 670         case MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ:
 671                 kfree(rq->mpwqe.info);
 672                 mlx5_core_destroy_mkey(mdev, &rq->umr_mkey);
 673                 break;
 674         default: /* MLX5_WQ_TYPE_CYCLIC */
 675                 kvfree(rq->wqe.frags);
 676                 mlx5e_free_di_list(rq);
 677         }
 678
 679 err_rq_wq_destroy:
 680         if (rq->xdp_prog)
 681                 bpf_prog_put(rq->xdp_prog);
 682         xdp_rxq_info_unreg(&rq->xdp_rxq);
 683         if (rq->page_pool)
 684                 page_pool_destroy(rq->page_pool);
 685         mlx5_wq_destroy(&rq->wq_ctrl);
 686
 687         return err;
 688 }
 689
 690 static void mlx5e_free_rq(struct mlx5e_rq *rq)
 691 {
 692         int i;
 693
 694         if (rq->xdp_prog)
 695                 bpf_prog_put(rq->xdp_prog);
 696
 697         xdp_rxq_info_unreg(&rq->xdp_rxq);
 698         if (rq->page_pool)
 699                 page_pool_destroy(rq->page_pool);
 700
 701         switch (rq->wq_type) {
 702         case MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ:
 703                 kfree(rq->mpwqe.info);
 704                 mlx5_core_destroy_mkey(rq->mdev, &rq->umr_mkey);
 705                 break;
 706         default: /* MLX5_WQ_TYPE_CYCLIC */
 707                 kvfree(rq->wqe.frags);
 708                 mlx5e_free_di_list(rq);
 709         }
 710
 711         for (i = rq->page_cache.head; i != rq->page_cache.tail;
 712              i = (i + 1) & (MLX5E_CACHE_SIZE - 1)) {
 713                 struct mlx5e_dma_info *dma_info = &rq->page_cache.page_cache[i];
 714
 715                 mlx5e_page_release(rq, dma_info, false);
 716         }
 717         mlx5_wq_destroy(&rq->wq_ctrl);
 718 }
 719
 720 static int mlx5e_create_rq(struct mlx5e_rq *rq,
 721                            struct mlx5e_rq_param *param)
 722 {
 723         struct mlx5_core_dev *mdev = rq->mdev;
 724
 725         void *in;
 726         void *rqc;
 727         void *wq;
 728         int inlen;
 729         int err;
 730
 731         inlen = MLX5_ST_SZ_BYTES(create_rq_in) +
 732                 sizeof(u64) * rq->wq_ctrl.buf.npages;
 733         in = kvzalloc(inlen, GFP_KERNEL);
 734         if (!in)
 735                 return -ENOMEM;
 736
 737         rqc = MLX5_ADDR_OF(create_rq_in, in, ctx);
 738         wq  = MLX5_ADDR_OF(rqc, rqc, wq);
 739
 740         memcpy(rqc, param->rqc, sizeof(param->rqc));
 741
 742         MLX5_SET(rqc,  rqc, cqn,                rq->cq.mcq.cqn);
 743         MLX5_SET(rqc,  rqc, state,              MLX5_RQC_STATE_RST);
 744         MLX5_SET(wq,   wq,  log_wq_pg_sz,       rq->wq_ctrl.buf.page_shift -
 745                                                 MLX5_ADAPTER_PAGE_SHIFT);
 746         MLX5_SET64(wq, wq,  dbr_addr,           rq->wq_ctrl.db.dma);
 747
 748         mlx5_fill_page_frag_array(&rq->wq_ctrl.buf,
 749                                   (__be64 *)MLX5_ADDR_OF(wq, wq, pas));
 750
 751         err = mlx5_core_create_rq(mdev, in, inlen, &rq->rqn);
 752
 753         kvfree(in);
 754
 755         return err;
 756 }
 757
 758 static int mlx5e_modify_rq_state(struct mlx5e_rq *rq, int curr_state,
 759                                  int next_state)
 760 {
 761         struct mlx5_core_dev *mdev = rq->mdev;
 762
 763         void *in;
 764         void *rqc;
 765         int inlen;
 766         int err;
 767
 768         inlen = MLX5_ST_SZ_BYTES(modify_rq_in);
 769         in = kvzalloc(inlen, GFP_KERNEL);
 770         if (!in)
 771                 return -ENOMEM;
 772
 773         rqc = MLX5_ADDR_OF(modify_rq_in, in, ctx);
 774
 775         MLX5_SET(modify_rq_in, in, rq_state, curr_state);
 776         MLX5_SET(rqc, rqc, state, next_state);
 777
 778         err = mlx5_core_modify_rq(mdev, rq->rqn, in, inlen);
 779
 780         kvfree(in);
 781
 782         return err;
 783 }
 784
 785 static int mlx5e_modify_rq_scatter_fcs(struct mlx5e_rq *rq, bool enable)
 786 {
 787         struct mlx5e_channel *c = rq->channel;
 788         struct mlx5e_priv *priv = c->priv;
 789         struct mlx5_core_dev *mdev = priv->mdev;
 790
 791         void *in;
 792         void *rqc;
 793         int inlen;
 794         int err;
 795
 796         inlen = MLX5_ST_SZ_BYTES(modify_rq_in);
 797         in = kvzalloc(inlen, GFP_KERNEL);
 798         if (!in)
 799                 return -ENOMEM;
 800
 801         rqc = MLX5_ADDR_OF(modify_rq_in, in, ctx);
 802
 803         MLX5_SET(modify_rq_in, in, rq_state, MLX5_RQC_STATE_RDY);
 804         MLX5_SET64(modify_rq_in, in, modify_bitmask,
 805                    MLX5_MODIFY_RQ_IN_MODIFY_BITMASK_SCATTER_FCS);
 806         MLX5_SET(rqc, rqc, scatter_fcs, enable);
 807         MLX5_SET(rqc, rqc, state, MLX5_RQC_STATE_RDY);
 808
 809         err = mlx5_core_modify_rq(mdev, rq->rqn, in, inlen);
 810
 811         kvfree(in);
 812
 813         return err;
 814 }
 815
 816 static int mlx5e_modify_rq_vsd(struct mlx5e_rq *rq, bool vsd)
 817 {
 818         struct mlx5e_channel *c = rq->channel;
 819         struct mlx5_core_dev *mdev = c->mdev;
 820         void *in;
 821         void *rqc;
 822         int inlen;
 823         int err;
 824
 825         inlen = MLX5_ST_SZ_BYTES(modify_rq_in);
 826         in = kvzalloc(inlen, GFP_KERNEL);
 827         if (!in)
 828                 return -ENOMEM;
 829
 830         rqc = MLX5_ADDR_OF(modify_rq_in, in, ctx);
 831
 832         MLX5_SET(modify_rq_in, in, rq_state, MLX5_RQC_STATE_RDY);
 833         MLX5_SET64(modify_rq_in, in, modify_bitmask,
 834                    MLX5_MODIFY_RQ_IN_MODIFY_BITMASK_VSD);
 835         MLX5_SET(rqc, rqc, vsd, vsd);
 836         MLX5_SET(rqc, rqc, state, MLX5_RQC_STATE_RDY);
 837
 838         err = mlx5_core_modify_rq(mdev, rq->rqn, in, inlen);
 839
 840         kvfree(in);
 841
 842         return err;
 843 }
 844
 845 static void mlx5e_destroy_rq(struct mlx5e_rq *rq)
 846 {
 847         mlx5_core_destroy_rq(rq->mdev, rq->rqn);
 848 }
 849
 850 static int mlx5e_wait_for_min_rx_wqes(struct mlx5e_rq *rq, int wait_time)
 851 {
 852         unsigned long exp_time = jiffies + msecs_to_jiffies(wait_time);
 853         struct mlx5e_channel *c = rq->channel;
 854
 855         u16 min_wqes = mlx5_min_rx_wqes(rq->wq_type, mlx5e_rqwq_get_size(rq));
 856
 857         do {
 858                 if (mlx5e_rqwq_get_cur_sz(rq) >= min_wqes)
 859                         return 0;
 860
 861                 msleep(20);
 862         } while (time_before(jiffies, exp_time));
 863
 864         netdev_warn(c->netdev, "Failed to get min RX wqes on Channel[%d] RQN[0x%x] wq cur_sz(%d) min_rx_wqes(%d)\n",
 865                     c->ix, rq->rqn, mlx5e_rqwq_get_cur_sz(rq), min_wqes);
 866
 867         return -ETIMEDOUT;
 868 }
 869
 870 static void mlx5e_free_rx_descs(struct mlx5e_rq *rq)
 871 {
 872         __be16 wqe_ix_be;
 873         u16 wqe_ix;
 874
 875         if (rq->wq_type == MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ) {
 876                 struct mlx5_wq_ll *wq = &rq->mpwqe.wq;
 877
 878                 /* UMR WQE (if in progress) is always at wq->head */
 879                 if (rq->mpwqe.umr_in_progress)
 880                         mlx5e_free_rx_mpwqe(rq, &rq->mpwqe.info[wq->head]);
 881
 882                 while (!mlx5_wq_ll_is_empty(wq)) {
 883                         struct mlx5e_rx_wqe_ll *wqe;
 884
 885                         wqe_ix_be = *wq->tail_next;
 886                         wqe_ix    = be16_to_cpu(wqe_ix_be);
 887                         wqe       = mlx5_wq_ll_get_wqe(wq, wqe_ix);
 888                         rq->dealloc_wqe(rq, wqe_ix);
 889                         mlx5_wq_ll_pop(wq, wqe_ix_be,
 890                                        &wqe->next.next_wqe_index);
 891                 }
 892         } else {
 893                 struct mlx5_wq_cyc *wq = &rq->wqe.wq;
 894
 895                 while (!mlx5_wq_cyc_is_empty(wq)) {
 896                         wqe_ix = mlx5_wq_cyc_get_tail(wq);
 897                         rq->dealloc_wqe(rq, wqe_ix);
 898                         mlx5_wq_cyc_pop(wq);
 899                 }
 900         }
 901
 902 }
 903
 904 static int mlx5e_open_rq(struct mlx5e_channel *c,
 905                          struct mlx5e_params *params,
 906                          struct mlx5e_rq_param *param,
 907                          struct mlx5e_rq *rq)
 908 {
 909         int err;
 910
 911         err = mlx5e_alloc_rq(c, params, param, rq);
 912         if (err)
 913                 return err;
 914
 915         err = mlx5e_create_rq(rq, param);
 916         if (err)
 917                 goto err_free_rq;
 918
 919         err = mlx5e_modify_rq_state(rq, MLX5_RQC_STATE_RST, MLX5_RQC_STATE_RDY);
 920         if (err)
 921                 goto err_destroy_rq;
 922
 923         if (params->rx_dim_enabled)
 924                 __set_bit(MLX5E_RQ_STATE_AM, &c->rq.state);
 925
 926         return 0;
 927
 928 err_destroy_rq:
 929         mlx5e_destroy_rq(rq);
 930 err_free_rq:
 931         mlx5e_free_rq(rq);
 932
 933         return err;
 934 }
 935
 936 static void mlx5e_activate_rq(struct mlx5e_rq *rq)
 937 {
 938         struct mlx5e_icosq *sq = &rq->channel->icosq;
 939         struct mlx5_wq_cyc *wq = &sq->wq;
 940         struct mlx5e_tx_wqe *nopwqe;
 941
 942         u16 pi = mlx5_wq_cyc_ctr2ix(wq, sq->pc);
 943
 944         set_bit(MLX5E_RQ_STATE_ENABLED, &rq->state);
 945         sq->db.ico_wqe[pi].opcode     = MLX5_OPCODE_NOP;
 946         nopwqe = mlx5e_post_nop(wq, sq->sqn, &sq->pc);
 947         mlx5e_notify_hw(wq, sq->pc, sq->uar_map, &nopwqe->ctrl);
 948 }
 949
 950 static void mlx5e_deactivate_rq(struct mlx5e_rq *rq)
 951 {
 952         clear_bit(MLX5E_RQ_STATE_ENABLED, &rq->state);
 953         napi_synchronize(&rq->channel->napi); /* prevent mlx5e_post_rx_wqes */
 954 }
 955
 956 static void mlx5e_close_rq(struct mlx5e_rq *rq)
 957 {
 958         cancel_work_sync(&rq->dim.work);
 959         mlx5e_destroy_rq(rq);
 960         mlx5e_free_rx_descs(rq);
 961         mlx5e_free_rq(rq);
 962 }
 963
 964 static void mlx5e_free_xdpsq_db(struct mlx5e_xdpsq *sq)
 965 {
 966         kfree(sq->db.di);
 967 }
 968
 969 static int mlx5e_alloc_xdpsq_db(struct mlx5e_xdpsq *sq, int numa)
 970 {
 971         int wq_sz = mlx5_wq_cyc_get_size(&sq->wq);
 972
 973         sq->db.di = kzalloc_node(sizeof(*sq->db.di) * wq_sz,
 974                                      GFP_KERNEL, numa);
 975         if (!sq->db.di) {
 976                 mlx5e_free_xdpsq_db(sq);
 977                 return -ENOMEM;
 978         }
 979
 980         return 0;
 981 }
 982
 983 static int mlx5e_alloc_xdpsq(struct mlx5e_channel *c,
 984                              struct mlx5e_params *params,
 985                              struct mlx5e_sq_param *param,
 986                              struct mlx5e_xdpsq *sq)
 987 {
 988         void *sqc_wq               = MLX5_ADDR_OF(sqc, param->sqc, wq);
 989         struct mlx5_core_dev *mdev = c->mdev;
 990         struct mlx5_wq_cyc *wq = &sq->wq;
 991         int err;
 992
 993         sq->pdev      = c->pdev;
 994         sq->mkey_be   = c->mkey_be;
 995         sq->channel   = c;
 996         sq->uar_map   = mdev->mlx5e_res.bfreg.map;
 997         sq->min_inline_mode = params->tx_min_inline_mode;
 998
 999         param->wq.db_numa_node = cpu_to_node(c->cpu);
1000         err = mlx5_wq_cyc_create(mdev, &param->wq, sqc_wq, wq, &sq->wq_ctrl);
1001         if (err)
1002                 return err;
1003         wq->db = &wq->db[MLX5_SND_DBR];
1004
1005         err = mlx5e_alloc_xdpsq_db(sq, cpu_to_node(c->cpu));
1006         if (err)
1007                 goto err_sq_wq_destroy;
1008
1009         return 0;
1010
1011 err_sq_wq_destroy:
1012         mlx5_wq_destroy(&sq->wq_ctrl);
1013
1014         return err;
1015 }
1016
1017 static void mlx5e_free_xdpsq(struct mlx5e_xdpsq *sq)
1018 {
1019         mlx5e_free_xdpsq_db(sq);
1020         mlx5_wq_destroy(&sq->wq_ctrl);
1021 }
1022
1023 static void mlx5e_free_icosq_db(struct mlx5e_icosq *sq)
1024 {
1025         kfree(sq->db.ico_wqe);
1026 }
1027
1028 static int mlx5e_alloc_icosq_db(struct mlx5e_icosq *sq, int numa)
1029 {
1030         u8 wq_sz = mlx5_wq_cyc_get_size(&sq->wq);
1031
1032         sq->db.ico_wqe = kzalloc_node(sizeof(*sq->db.ico_wqe) * wq_sz,
1033                                       GFP_KERNEL, numa);
1034         if (!sq->db.ico_wqe)
1035                 return -ENOMEM;
1036
1037         return 0;
1038 }
1039
1040 static int mlx5e_alloc_icosq(struct mlx5e_channel *c,
1041                              struct mlx5e_sq_param *param,
1042                              struct mlx5e_icosq *sq)
1043 {
1044         void *sqc_wq               = MLX5_ADDR_OF(sqc, param->sqc, wq);
1045         struct mlx5_core_dev *mdev = c->mdev;
1046         struct mlx5_wq_cyc *wq = &sq->wq;
1047         int err;
1048
1049         sq->channel   = c;
1050         sq->uar_map   = mdev->mlx5e_res.bfreg.map;
1051
1052         param->wq.db_numa_node = cpu_to_node(c->cpu);
1053         err = mlx5_wq_cyc_create(mdev, &param->wq, sqc_wq, wq, &sq->wq_ctrl);
1054         if (err)
1055                 return err;
1056         wq->db = &wq->db[MLX5_SND_DBR];
1057
1058         err = mlx5e_alloc_icosq_db(sq, cpu_to_node(c->cpu));
1059         if (err)
1060                 goto err_sq_wq_destroy;
1061
1062         return 0;
1063
1064 err_sq_wq_destroy:
1065         mlx5_wq_destroy(&sq->wq_ctrl);
1066
1067         return err;
1068 }
1069
1070 static void mlx5e_free_icosq(struct mlx5e_icosq *sq)
1071 {
1072         mlx5e_free_icosq_db(sq);
1073         mlx5_wq_destroy(&sq->wq_ctrl);
1074 }
1075
1076 static void mlx5e_free_txqsq_db(struct mlx5e_txqsq *sq)
1077 {
1078         kfree(sq->db.wqe_info);
1079         kfree(sq->db.dma_fifo);
1080 }
1081
1082 static int mlx5e_alloc_txqsq_db(struct mlx5e_txqsq *sq, int numa)
1083 {
1084         int wq_sz = mlx5_wq_cyc_get_size(&sq->wq);
1085         int df_sz = wq_sz * MLX5_SEND_WQEBB_NUM_DS;
1086
1087         sq->db.dma_fifo = kzalloc_node(df_sz * sizeof(*sq->db.dma_fifo),
1088                                            GFP_KERNEL, numa);
1089         sq->db.wqe_info = kzalloc_node(wq_sz * sizeof(*sq->db.wqe_info),
1090                                            GFP_KERNEL, numa);
1091         if (!sq->db.dma_fifo || !sq->db.wqe_info) {
1092                 mlx5e_free_txqsq_db(sq);
1093                 return -ENOMEM;
1094         }
1095
1096         sq->dma_fifo_mask = df_sz - 1;
1097
1098         return 0;
1099 }
1100
1101 static void mlx5e_sq_recover(struct work_struct *work);
1102 static int mlx5e_alloc_txqsq(struct mlx5e_channel *c,
1103                              int txq_ix,
1104                              struct mlx5e_params *params,
1105                              struct mlx5e_sq_param *param,
1106                              struct mlx5e_txqsq *sq,
1107                              int tc)
1108 {
1109         void *sqc_wq               = MLX5_ADDR_OF(sqc, param->sqc, wq);
1110         struct mlx5_core_dev *mdev = c->mdev;
1111         struct mlx5_wq_cyc *wq = &sq->wq;
1112         int err;
1113
1114         sq->pdev      = c->pdev;
1115         sq->tstamp    = c->tstamp;
1116         sq->clock     = &mdev->clock;
1117         sq->mkey_be   = c->mkey_be;
1118         sq->channel   = c;
1119         sq->txq_ix    = txq_ix;
1120         sq->uar_map   = mdev->mlx5e_res.bfreg.map;
1121         sq->min_inline_mode = params->tx_min_inline_mode;
1122         sq->stats     = &c->priv->channel_stats[c->ix].sq[tc];
1123         INIT_WORK(&sq->recover.recover_work, mlx5e_sq_recover);
1124         if (MLX5_IPSEC_DEV(c->priv->mdev))
1125                 set_bit(MLX5E_SQ_STATE_IPSEC, &sq->state);
1126         if (mlx5_accel_is_tls_device(c->priv->mdev))
1127                 set_bit(MLX5E_SQ_STATE_TLS, &sq->state);
1128
1129         param->wq.db_numa_node = cpu_to_node(c->cpu);
1130         err = mlx5_wq_cyc_create(mdev, &param->wq, sqc_wq, wq, &sq->wq_ctrl);
1131         if (err)
1132                 return err;
1133         wq->db    = &wq->db[MLX5_SND_DBR];
1134
1135         err = mlx5e_alloc_txqsq_db(sq, cpu_to_node(c->cpu));
1136         if (err)
1137                 goto err_sq_wq_destroy;
1138
1139         INIT_WORK(&sq->dim.work, mlx5e_tx_dim_work);
1140         sq->dim.mode = params->tx_cq_moderation.cq_period_mode;
1141
1142         return 0;
1143
1144 err_sq_wq_destroy:
1145         mlx5_wq_destroy(&sq->wq_ctrl);
1146
1147         return err;
1148 }
1149
1150 static void mlx5e_free_txqsq(struct mlx5e_txqsq *sq)
1151 {
1152         mlx5e_free_txqsq_db(sq);
1153         mlx5_wq_destroy(&sq->wq_ctrl);
1154 }
1155
1156 struct mlx5e_create_sq_param {
1157         struct mlx5_wq_ctrl        *wq_ctrl;
1158         u32                         cqn;
1159         u32                         tisn;
1160         u8                          tis_lst_sz;
1161         u8                          min_inline_mode;
1162 };
1163
1164 static int mlx5e_create_sq(struct mlx5_core_dev *mdev,
1165                            struct mlx5e_sq_param *param,
1166                            struct mlx5e_create_sq_param *csp,
1167                            u32 *sqn)
1168 {
1169         void *in;
1170         void *sqc;
1171         void *wq;
1172         int inlen;
1173         int err;
1174
1175         inlen = MLX5_ST_SZ_BYTES(create_sq_in) +
1176                 sizeof(u64) * csp->wq_ctrl->buf.npages;
1177         in = kvzalloc(inlen, GFP_KERNEL);
1178         if (!in)
1179                 return -ENOMEM;
1180
1181         sqc = MLX5_ADDR_OF(create_sq_in, in, ctx);
1182         wq = MLX5_ADDR_OF(sqc, sqc, wq);
1183
1184         memcpy(sqc, param->sqc, sizeof(param->sqc));
1185         MLX5_SET(sqc,  sqc, tis_lst_sz, csp->tis_lst_sz);
1186         MLX5_SET(sqc,  sqc, tis_num_0, csp->tisn);
1187         MLX5_SET(sqc,  sqc, cqn, csp->cqn);
1188
1189         if (MLX5_CAP_ETH(mdev, wqe_inline_mode) == MLX5_CAP_INLINE_MODE_VPORT_CONTEXT)
1190                 MLX5_SET(sqc,  sqc, min_wqe_inline_mode, csp->min_inline_mode);
1191
1192         MLX5_SET(sqc,  sqc, state, MLX5_SQC_STATE_RST);
1193         MLX5_SET(sqc,  sqc, flush_in_error_en, 1);
1194
1195         MLX5_SET(wq,   wq, wq_type,       MLX5_WQ_TYPE_CYCLIC);
1196         MLX5_SET(wq,   wq, uar_page,      mdev->mlx5e_res.bfreg.index);
1197         MLX5_SET(wq,   wq, log_wq_pg_sz,  csp->wq_ctrl->buf.page_shift -
1198                                           MLX5_ADAPTER_PAGE_SHIFT);
1199         MLX5_SET64(wq, wq, dbr_addr,      csp->wq_ctrl->db.dma);
1200
1201         mlx5_fill_page_frag_array(&csp->wq_ctrl->buf,
1202                                   (__be64 *)MLX5_ADDR_OF(wq, wq, pas));
1203
1204         err = mlx5_core_create_sq(mdev, in, inlen, sqn);
1205
1206         kvfree(in);
1207
1208         return err;
1209 }
1210
1211 struct mlx5e_modify_sq_param {
1212         int curr_state;
1213         int next_state;
1214         bool rl_update;
1215         int rl_index;
1216 };
1217
1218 static int mlx5e_modify_sq(struct mlx5_core_dev *mdev, u32 sqn,
1219                            struct mlx5e_modify_sq_param *p)
1220 {
1221         void *in;
1222         void *sqc;
1223         int inlen;
1224         int err;
1225
1226         inlen = MLX5_ST_SZ_BYTES(modify_sq_in);
1227         in = kvzalloc(inlen, GFP_KERNEL);
1228         if (!in)
1229                 return -ENOMEM;
1230
1231         sqc = MLX5_ADDR_OF(modify_sq_in, in, ctx);
1232
1233         MLX5_SET(modify_sq_in, in, sq_state, p->curr_state);
1234         MLX5_SET(sqc, sqc, state, p->next_state);
1235         if (p->rl_update && p->next_state == MLX5_SQC_STATE_RDY) {
1236                 MLX5_SET64(modify_sq_in, in, modify_bitmask, 1);
1237                 MLX5_SET(sqc,  sqc, packet_pacing_rate_limit_index, p->rl_index);
1238         }
1239
1240         err = mlx5_core_modify_sq(mdev, sqn, in, inlen);
1241
1242         kvfree(in);
1243
1244         return err;
1245 }
1246
1247 static void mlx5e_destroy_sq(struct mlx5_core_dev *mdev, u32 sqn)
1248 {
1249         mlx5_core_destroy_sq(mdev, sqn);
1250 }
1251
1252 static int mlx5e_create_sq_rdy(struct mlx5_core_dev *mdev,
1253                                struct mlx5e_sq_param *param,
1254                                struct mlx5e_create_sq_param *csp,
1255                                u32 *sqn)
1256 {
1257         struct mlx5e_modify_sq_param msp = {0};
1258         int err;
1259
1260         err = mlx5e_create_sq(mdev, param, csp, sqn);
1261         if (err)
1262                 return err;
1263
1264         msp.curr_state = MLX5_SQC_STATE_RST;
1265         msp.next_state = MLX5_SQC_STATE_RDY;
1266         err = mlx5e_modify_sq(mdev, *sqn, &msp);
1267         if (err)
1268                 mlx5e_destroy_sq(mdev, *sqn);
1269
1270         return err;
1271 }
1272
1273 static int mlx5e_set_sq_maxrate(struct net_device *dev,
1274                                 struct mlx5e_txqsq *sq, u32 rate);
1275
1276 static int mlx5e_open_txqsq(struct mlx5e_channel *c,
1277                             u32 tisn,
1278                             int txq_ix,
1279                             struct mlx5e_params *params,
1280                             struct mlx5e_sq_param *param,
1281                             struct mlx5e_txqsq *sq,
1282                             int tc)
1283 {
1284         struct mlx5e_create_sq_param csp = {};
1285         u32 tx_rate;
1286         int err;
1287
1288         err = mlx5e_alloc_txqsq(c, txq_ix, params, param, sq, tc);
1289         if (err)
1290                 return err;
1291
1292         csp.tisn            = tisn;
1293         csp.tis_lst_sz      = 1;
1294         csp.cqn             = sq->cq.mcq.cqn;
1295         csp.wq_ctrl         = &sq->wq_ctrl;
1296         csp.min_inline_mode = sq->min_inline_mode;
1297         err = mlx5e_create_sq_rdy(c->mdev, param, &csp, &sq->sqn);
1298         if (err)
1299                 goto err_free_txqsq;
1300
1301         tx_rate = c->priv->tx_rates[sq->txq_ix];
1302         if (tx_rate)
1303                 mlx5e_set_sq_maxrate(c->netdev, sq, tx_rate);
1304
1305         if (params->tx_dim_enabled)
1306                 sq->state |= BIT(MLX5E_SQ_STATE_AM);
1307
1308         return 0;
1309
1310 err_free_txqsq:
1311         clear_bit(MLX5E_SQ_STATE_ENABLED, &sq->state);
1312         mlx5e_free_txqsq(sq);
1313
1314         return err;
1315 }
1316
1317 static void mlx5e_reset_txqsq_cc_pc(struct mlx5e_txqsq *sq)
1318 {
1319         WARN_ONCE(sq->cc != sq->pc,
1320                   "SQ 0x%x: cc (0x%x) != pc (0x%x)\n",
1321                   sq->sqn, sq->cc, sq->pc);
1322         sq->cc = 0;
1323         sq->dma_fifo_cc = 0;
1324         sq->pc = 0;
1325 }
1326
1327 static void mlx5e_activate_txqsq(struct mlx5e_txqsq *sq)
1328 {
1329         sq->txq = netdev_get_tx_queue(sq->channel->netdev, sq->txq_ix);
1330         clear_bit(MLX5E_SQ_STATE_RECOVERING, &sq->state);
1331         set_bit(MLX5E_SQ_STATE_ENABLED, &sq->state);
1332         netdev_tx_reset_queue(sq->txq);
1333         netif_tx_start_queue(sq->txq);
1334 }
1335
1336 static inline void netif_tx_disable_queue(struct netdev_queue *txq)
1337 {
1338         __netif_tx_lock_bh(txq);
1339         netif_tx_stop_queue(txq);
1340         __netif_tx_unlock_bh(txq);
1341 }
1342
1343 static void mlx5e_deactivate_txqsq(struct mlx5e_txqsq *sq)
1344 {
1345         struct mlx5e_channel *c = sq->channel;
1346         struct mlx5_wq_cyc *wq = &sq->wq;
1347
1348         clear_bit(MLX5E_SQ_STATE_ENABLED, &sq->state);
1349         /* prevent netif_tx_wake_queue */
1350         napi_synchronize(&c->napi);
1351
1352         netif_tx_disable_queue(sq->txq);
1353
1354         /* last doorbell out, godspeed .. */
1355         if (mlx5e_wqc_has_room_for(wq, sq->cc, sq->pc, 1)) {
1356                 u16 pi = mlx5_wq_cyc_ctr2ix(wq, sq->pc);
1357                 struct mlx5e_tx_wqe *nop;
1358
1359                 sq->db.wqe_info[pi].skb = NULL;
1360                 nop = mlx5e_post_nop(wq, sq->sqn, &sq->pc);
1361                 mlx5e_notify_hw(wq, sq->pc, sq->uar_map, &nop->ctrl);
1362         }
1363 }
1364
1365 static void mlx5e_close_txqsq(struct mlx5e_txqsq *sq)
1366 {
1367         struct mlx5e_channel *c = sq->channel;
1368         struct mlx5_core_dev *mdev = c->mdev;
1369         struct mlx5_rate_limit rl = {0};
1370
1371         mlx5e_destroy_sq(mdev, sq->sqn);
1372         if (sq->rate_limit) {
1373                 rl.rate = sq->rate_limit;
1374                 mlx5_rl_remove_rate(mdev, &rl);
1375         }
1376         mlx5e_free_txqsq_descs(sq);
1377         mlx5e_free_txqsq(sq);
1378 }
1379
1380 static int mlx5e_wait_for_sq_flush(struct mlx5e_txqsq *sq)
1381 {
1382         unsigned long exp_time = jiffies + msecs_to_jiffies(2000);
1383
1384         while (time_before(jiffies, exp_time)) {
1385                 if (sq->cc == sq->pc)
1386                         return 0;
1387
1388                 msleep(20);
1389         }
1390
1391         netdev_err(sq->channel->netdev,
1392                    "Wait for SQ 0x%x flush timeout (sq cc = 0x%x, sq pc = 0x%x)\n",
1393                    sq->sqn, sq->cc, sq->pc);
1394
1395         return -ETIMEDOUT;
1396 }
1397
1398 static int mlx5e_sq_to_ready(struct mlx5e_txqsq *sq, int curr_state)
1399 {
1400         struct mlx5_core_dev *mdev = sq->channel->mdev;
1401         struct net_device *dev = sq->channel->netdev;
1402         struct mlx5e_modify_sq_param msp = {0};
1403         int err;
1404
1405         msp.curr_state = curr_state;
1406         msp.next_state = MLX5_SQC_STATE_RST;
1407
1408         err = mlx5e_modify_sq(mdev, sq->sqn, &msp);
1409         if (err) {
1410                 netdev_err(dev, "Failed to move sq 0x%x to reset\n", sq->sqn);
1411                 return err;
1412         }
1413
1414         memset(&msp, 0, sizeof(msp));
1415         msp.curr_state = MLX5_SQC_STATE_RST;
1416         msp.next_state = MLX5_SQC_STATE_RDY;
1417
1418         err = mlx5e_modify_sq(mdev, sq->sqn, &msp);
1419         if (err) {
1420                 netdev_err(dev, "Failed to move sq 0x%x to ready\n", sq->sqn);
1421                 return err;
1422         }
1423
1424         return 0;
1425 }
1426
1427 static void mlx5e_sq_recover(struct work_struct *work)
1428 {
1429         struct mlx5e_txqsq_recover *recover =
1430                 container_of(work, struct mlx5e_txqsq_recover,
1431                              recover_work);
1432         struct mlx5e_txqsq *sq = container_of(recover, struct mlx5e_txqsq,
1433                                               recover);
1434         struct mlx5_core_dev *mdev = sq->channel->mdev;
1435         struct net_device *dev = sq->channel->netdev;
1436         u8 state;
1437         int err;
1438
1439         err = mlx5_core_query_sq_state(mdev, sq->sqn, &state);
1440         if (err) {
1441                 netdev_err(dev, "Failed to query SQ 0x%x state. err = %d\n",
1442                            sq->sqn, err);
1443                 return;
1444         }
1445
1446         if (state != MLX5_RQC_STATE_ERR) {
1447                 netdev_err(dev, "SQ 0x%x not in ERROR state\n", sq->sqn);
1448                 return;
1449         }
1450
1451         netif_tx_disable_queue(sq->txq);
1452
1453         if (mlx5e_wait_for_sq_flush(sq))
1454                 return;
1455
1456         /* If the interval between two consecutive recovers per SQ is too
1457          * short, don't recover to avoid infinite loop of ERR_CQE -> recover.
1458          * If we reached this state, there is probably a bug that needs to be
1459          * fixed. let's keep the queue close and let tx timeout cleanup.
1460          */
1461         if (jiffies_to_msecs(jiffies - recover->last_recover) <
1462             MLX5E_SQ_RECOVER_MIN_INTERVAL) {
1463                 netdev_err(dev, "Recover SQ 0x%x canceled, too many error CQEs\n",
1464                            sq->sqn);
1465                 return;
1466         }
1467
1468         /* At this point, no new packets will arrive from the stack as TXQ is
1469          * marked with QUEUE_STATE_DRV_XOFF. In addition, NAPI cleared all
1470          * pending WQEs.  SQ can safely reset the SQ.
1471          */
1472         if (mlx5e_sq_to_ready(sq, state))
1473                 return;
1474
1475         mlx5e_reset_txqsq_cc_pc(sq);
1476         sq->stats->recover++;
1477         recover->last_recover = jiffies;
1478         mlx5e_activate_txqsq(sq);
1479 }
1480
1481 static int mlx5e_open_icosq(struct mlx5e_channel *c,
1482                             struct mlx5e_params *params,
1483                             struct mlx5e_sq_param *param,
1484                             struct mlx5e_icosq *sq)
1485 {
1486         struct mlx5e_create_sq_param csp = {};
1487         int err;
1488
1489         err = mlx5e_alloc_icosq(c, param, sq);
1490         if (err)
1491                 return err;
1492
1493         csp.cqn             = sq->cq.mcq.cqn;
1494         csp.wq_ctrl         = &sq->wq_ctrl;
1495         csp.min_inline_mode = params->tx_min_inline_mode;
1496         set_bit(MLX5E_SQ_STATE_ENABLED, &sq->state);
1497         err = mlx5e_create_sq_rdy(c->mdev, param, &csp, &sq->sqn);
1498         if (err)
1499                 goto err_free_icosq;
1500
1501         return 0;
1502
1503 err_free_icosq:
1504         clear_bit(MLX5E_SQ_STATE_ENABLED, &sq->state);
1505         mlx5e_free_icosq(sq);
1506
1507         return err;
1508 }
1509
1510 static void mlx5e_close_icosq(struct mlx5e_icosq *sq)
1511 {
1512         struct mlx5e_channel *c = sq->channel;
1513
1514         clear_bit(MLX5E_SQ_STATE_ENABLED, &sq->state);
1515         napi_synchronize(&c->napi);
1516
1517         mlx5e_destroy_sq(c->mdev, sq->sqn);
1518         mlx5e_free_icosq(sq);
1519 }
1520
1521 static int mlx5e_open_xdpsq(struct mlx5e_channel *c,
1522                             struct mlx5e_params *params,
1523                             struct mlx5e_sq_param *param,
1524                             struct mlx5e_xdpsq *sq)
1525 {
1526         unsigned int ds_cnt = MLX5E_XDP_TX_DS_COUNT;
1527         struct mlx5e_create_sq_param csp = {};
1528         unsigned int inline_hdr_sz = 0;
1529         int err;
1530         int i;
1531
1532         err = mlx5e_alloc_xdpsq(c, params, param, sq);
1533         if (err)
1534                 return err;
1535
1536         csp.tis_lst_sz      = 1;
1537         csp.tisn            = c->priv->tisn[0]; /* tc = 0 */
1538         csp.cqn             = sq->cq.mcq.cqn;
1539         csp.wq_ctrl         = &sq->wq_ctrl;
1540         csp.min_inline_mode = sq->min_inline_mode;
1541         set_bit(MLX5E_SQ_STATE_ENABLED, &sq->state);
1542         err = mlx5e_create_sq_rdy(c->mdev, param, &csp, &sq->sqn);
1543         if (err)
1544                 goto err_free_xdpsq;
1545
1546         if (sq->min_inline_mode != MLX5_INLINE_MODE_NONE) {
1547                 inline_hdr_sz = MLX5E_XDP_MIN_INLINE;
1548                 ds_cnt++;
1549         }
1550
1551         /* Pre initialize fixed WQE fields */
1552         for (i = 0; i < mlx5_wq_cyc_get_size(&sq->wq); i++) {
1553                 struct mlx5e_tx_wqe      *wqe  = mlx5_wq_cyc_get_wqe(&sq->wq, i);
1554                 struct mlx5_wqe_ctrl_seg *cseg = &wqe->ctrl;
1555                 struct mlx5_wqe_eth_seg  *eseg = &wqe->eth;
1556                 struct mlx5_wqe_data_seg *dseg;
1557
1558                 cseg->qpn_ds = cpu_to_be32((sq->sqn << 8) | ds_cnt);
1559                 eseg->inline_hdr.sz = cpu_to_be16(inline_hdr_sz);
1560
1561                 dseg = (struct mlx5_wqe_data_seg *)cseg + (ds_cnt - 1);
1562                 dseg->lkey = sq->mkey_be;
1563         }
1564
1565         return 0;
1566
1567 err_free_xdpsq:
1568         clear_bit(MLX5E_SQ_STATE_ENABLED, &sq->state);
1569         mlx5e_free_xdpsq(sq);
1570
1571         return err;
1572 }
1573
1574 static void mlx5e_close_xdpsq(struct mlx5e_xdpsq *sq)
1575 {
1576         struct mlx5e_channel *c = sq->channel;
1577
1578         clear_bit(MLX5E_SQ_STATE_ENABLED, &sq->state);
1579         napi_synchronize(&c->napi);
1580
1581         mlx5e_destroy_sq(c->mdev, sq->sqn);
1582         mlx5e_free_xdpsq_descs(sq);
1583         mlx5e_free_xdpsq(sq);
1584 }
1585
1586 static int mlx5e_alloc_cq_common(struct mlx5_core_dev *mdev,
1587                                  struct mlx5e_cq_param *param,
1588                                  struct mlx5e_cq *cq)
1589 {
1590         struct mlx5_core_cq *mcq = &cq->mcq;
1591         int eqn_not_used;
1592         unsigned int irqn;
1593         int err;
1594         u32 i;
1595
1596         err = mlx5_cqwq_create(mdev, &param->wq, param->cqc, &cq->wq,
1597                                &cq->wq_ctrl);
1598         if (err)
1599                 return err;
1600
1601         mlx5_vector2eqn(mdev, param->eq_ix, &eqn_not_used, &irqn);
1602
1603         mcq->cqe_sz     = 64;
1604         mcq->set_ci_db  = cq->wq_ctrl.db.db;
1605         mcq->arm_db     = cq->wq_ctrl.db.db + 1;
1606         *mcq->set_ci_db = 0;
1607         *mcq->arm_db    = 0;
1608         mcq->vector     = param->eq_ix;
1609         mcq->comp       = mlx5e_completion_event;
1610         mcq->event      = mlx5e_cq_error_event;
1611         mcq->irqn       = irqn;
1612
1613         for (i = 0; i < mlx5_cqwq_get_size(&cq->wq); i++) {
1614                 struct mlx5_cqe64 *cqe = mlx5_cqwq_get_wqe(&cq->wq, i);
1615
1616                 cqe->op_own = 0xf1;
1617         }
1618
1619         cq->mdev = mdev;
1620
1621         return 0;
1622 }
1623
1624 static int mlx5e_alloc_cq(struct mlx5e_channel *c,
1625                           struct mlx5e_cq_param *param,
1626                           struct mlx5e_cq *cq)
1627 {
1628         struct mlx5_core_dev *mdev = c->priv->mdev;
1629         int err;
1630
1631         param->wq.buf_numa_node = cpu_to_node(c->cpu);
1632         param->wq.db_numa_node  = cpu_to_node(c->cpu);
1633         param->eq_ix   = c->ix;
1634
1635         err = mlx5e_alloc_cq_common(mdev, param, cq);
1636
1637         cq->napi    = &c->napi;
1638         cq->channel = c;
1639
1640         return err;
1641 }
1642
1643 static void mlx5e_free_cq(struct mlx5e_cq *cq)
1644 {
1645         mlx5_wq_destroy(&cq->wq_ctrl);
1646 }
1647
1648 static int mlx5e_create_cq(struct mlx5e_cq *cq, struct mlx5e_cq_param *param)
1649 {
1650         struct mlx5_core_dev *mdev = cq->mdev;
1651         struct mlx5_core_cq *mcq = &cq->mcq;
1652
1653         void *in;
1654         void *cqc;
1655         int inlen;
1656         unsigned int irqn_not_used;
1657         int eqn;
1658         int err;
1659
1660         inlen = MLX5_ST_SZ_BYTES(create_cq_in) +
1661                 sizeof(u64) * cq->wq_ctrl.buf.npages;
1662         in = kvzalloc(inlen, GFP_KERNEL);
1663         if (!in)
1664                 return -ENOMEM;
1665
1666         cqc = MLX5_ADDR_OF(create_cq_in, in, cq_context);
1667
1668         memcpy(cqc, param->cqc, sizeof(param->cqc));
1669
1670         mlx5_fill_page_frag_array(&cq->wq_ctrl.buf,
1671                                   (__be64 *)MLX5_ADDR_OF(create_cq_in, in, pas));
1672
1673         mlx5_vector2eqn(mdev, param->eq_ix, &eqn, &irqn_not_used);
1674
1675         MLX5_SET(cqc,   cqc, cq_period_mode, param->cq_period_mode);
1676         MLX5_SET(cqc,   cqc, c_eqn,         eqn);
1677         MLX5_SET(cqc,   cqc, uar_page,      mdev->priv.uar->index);
1678         MLX5_SET(cqc,   cqc, log_page_size, cq->wq_ctrl.buf.page_shift -
1679                                             MLX5_ADAPTER_PAGE_SHIFT);
1680         MLX5_SET64(cqc, cqc, dbr_addr,      cq->wq_ctrl.db.dma);
1681
1682         err = mlx5_core_create_cq(mdev, mcq, in, inlen);
1683
1684         kvfree(in);
1685
1686         if (err)
1687                 return err;
1688
1689         mlx5e_cq_arm(cq);
1690
1691         return 0;
1692 }
1693
1694 static void mlx5e_destroy_cq(struct mlx5e_cq *cq)
1695 {
1696         mlx5_core_destroy_cq(cq->mdev, &cq->mcq);
1697 }
1698
1699 static int mlx5e_open_cq(struct mlx5e_channel *c,
1700                          struct net_dim_cq_moder moder,
1701                          struct mlx5e_cq_param *param,
1702                          struct mlx5e_cq *cq)
1703 {
1704         struct mlx5_core_dev *mdev = c->mdev;
1705         int err;
1706
1707         err = mlx5e_alloc_cq(c, param, cq);
1708         if (err)
1709                 return err;
1710
1711         err = mlx5e_create_cq(cq, param);
1712         if (err)
1713                 goto err_free_cq;
1714
1715         if (MLX5_CAP_GEN(mdev, cq_moderation))
1716                 mlx5_core_modify_cq_moderation(mdev, &cq->mcq, moder.usec, moder.pkts);
1717         return 0;
1718
1719 err_free_cq:
1720         mlx5e_free_cq(cq);
1721
1722         return err;
1723 }
1724
1725 static void mlx5e_close_cq(struct mlx5e_cq *cq)
1726 {
1727         mlx5e_destroy_cq(cq);
1728         mlx5e_free_cq(cq);
1729 }
1730
1731 static int mlx5e_get_cpu(struct mlx5e_priv *priv, int ix)
1732 {
1733         return cpumask_first(priv->mdev->priv.irq_info[ix].mask);
1734 }
1735
1736 static int mlx5e_open_tx_cqs(struct mlx5e_channel *c,
1737                              struct mlx5e_params *params,
1738                              struct mlx5e_channel_param *cparam)
1739 {
1740         int err;
1741         int tc;
1742
1743         for (tc = 0; tc < c->num_tc; tc++) {
1744                 err = mlx5e_open_cq(c, params->tx_cq_moderation,
1745                                     &cparam->tx_cq, &c->sq[tc].cq);
1746                 if (err)
1747                         goto err_close_tx_cqs;
1748         }
1749
1750         return 0;
1751
1752 err_close_tx_cqs:
1753         for (tc--; tc >= 0; tc--)
1754                 mlx5e_close_cq(&c->sq[tc].cq);
1755
1756         return err;
1757 }
1758
1759 static void mlx5e_close_tx_cqs(struct mlx5e_channel *c)
1760 {
1761         int tc;
1762
1763         for (tc = 0; tc < c->num_tc; tc++)
1764                 mlx5e_close_cq(&c->sq[tc].cq);
1765 }
1766
1767 static int mlx5e_open_sqs(struct mlx5e_channel *c,
1768                           struct mlx5e_params *params,
1769                           struct mlx5e_channel_param *cparam)
1770 {
1771         struct mlx5e_priv *priv = c->priv;
1772         int err, tc, max_nch = priv->profile->max_nch(priv->mdev);
1773
1774         for (tc = 0; tc < params->num_tc; tc++) {
1775                 int txq_ix = c->ix + tc * max_nch;
1776
1777                 err = mlx5e_open_txqsq(c, c->priv->tisn[tc], txq_ix,
1778                                        params, &cparam->sq, &c->sq[tc], tc);
1779                 if (err)
1780                         goto err_close_sqs;
1781         }
1782
1783         return 0;
1784
1785 err_close_sqs:
1786         for (tc--; tc >= 0; tc--)
1787                 mlx5e_close_txqsq(&c->sq[tc]);
1788
1789         return err;
1790 }
1791
1792 static void mlx5e_close_sqs(struct mlx5e_channel *c)
1793 {
1794         int tc;
1795
1796         for (tc = 0; tc < c->num_tc; tc++)
1797                 mlx5e_close_txqsq(&c->sq[tc]);
1798 }
1799
1800 static int mlx5e_set_sq_maxrate(struct net_device *dev,
1801                                 struct mlx5e_txqsq *sq, u32 rate)
1802 {
1803         struct mlx5e_priv *priv = netdev_priv(dev);
1804         struct mlx5_core_dev *mdev = priv->mdev;
1805         struct mlx5e_modify_sq_param msp = {0};
1806         struct mlx5_rate_limit rl = {0};
1807         u16 rl_index = 0;
1808         int err;
1809
1810         if (rate == sq->rate_limit)
1811                 /* nothing to do */
1812                 return 0;
1813
1814         if (sq->rate_limit) {
1815                 rl.rate = sq->rate_limit;
1816                 /* remove current rl index to free space to next ones */
1817                 mlx5_rl_remove_rate(mdev, &rl);
1818         }
1819
1820         sq->rate_limit = 0;
1821
1822         if (rate) {
1823                 rl.rate = rate;
1824                 err = mlx5_rl_add_rate(mdev, &rl_index, &rl);
1825                 if (err) {
1826                         netdev_err(dev, "Failed configuring rate %u: %d\n",
1827                                    rate, err);
1828                         return err;
1829                 }
1830         }
1831
1832         msp.curr_state = MLX5_SQC_STATE_RDY;
1833         msp.next_state = MLX5_SQC_STATE_RDY;
1834         msp.rl_index   = rl_index;
1835         msp.rl_update  = true;
1836         err = mlx5e_modify_sq(mdev, sq->sqn, &msp);
1837         if (err) {
1838                 netdev_err(dev, "Failed configuring rate %u: %d\n",
1839                            rate, err);
1840                 /* remove the rate from the table */
1841                 if (rate)
1842                         mlx5_rl_remove_rate(mdev, &rl);
1843                 return err;
1844         }
1845
1846         sq->rate_limit = rate;
1847         return 0;
1848 }
1849
1850 static int mlx5e_set_tx_maxrate(struct net_device *dev, int index, u32 rate)
1851 {
1852         struct mlx5e_priv *priv = netdev_priv(dev);
1853         struct mlx5_core_dev *mdev = priv->mdev;
1854         struct mlx5e_txqsq *sq = priv->txq2sq[index];
1855         int err = 0;
1856
1857         if (!mlx5_rl_is_supported(mdev)) {
1858                 netdev_err(dev, "Rate limiting is not supported on this device\n");
1859                 return -EINVAL;
1860         }
1861
1862         /* rate is given in Mb/sec, HW config is in Kb/sec */
1863         rate = rate << 10;
1864
1865         /* Check whether rate in valid range, 0 is always valid */
1866         if (rate && !mlx5_rl_is_in_range(mdev, rate)) {
1867                 netdev_err(dev, "TX rate %u, is not in range\n", rate);
1868                 return -ERANGE;
1869         }
1870
1871         mutex_lock(&priv->state_lock);
1872         if (test_bit(MLX5E_STATE_OPENED, &priv->state))
1873                 err = mlx5e_set_sq_maxrate(dev, sq, rate);
1874         if (!err)
1875                 priv->tx_rates[index] = rate;
1876         mutex_unlock(&priv->state_lock);
1877
1878         return err;
1879 }
1880
1881 static int mlx5e_open_channel(struct mlx5e_priv *priv, int ix,
1882                               struct mlx5e_params *params,
1883                               struct mlx5e_channel_param *cparam,
1884                               struct mlx5e_channel **cp)
1885 {
1886         struct net_dim_cq_moder icocq_moder = {0, 0};
1887         struct net_device *netdev = priv->netdev;
1888         int cpu = mlx5e_get_cpu(priv, ix);
1889         struct mlx5e_channel *c;
1890         unsigned int irq;
1891         int err;
1892         int eqn;
1893
1894         c = kzalloc_node(sizeof(*c), GFP_KERNEL, cpu_to_node(cpu));
1895         if (!c)
1896                 return -ENOMEM;
1897
1898         c->priv     = priv;
1899         c->mdev     = priv->mdev;
1900         c->tstamp   = &priv->tstamp;
1901         c->ix       = ix;
1902         c->cpu      = cpu;
1903         c->pdev     = &priv->mdev->pdev->dev;
1904         c->netdev   = priv->netdev;
1905         c->mkey_be  = cpu_to_be32(priv->mdev->mlx5e_res.mkey.key);
1906         c->num_tc   = params->num_tc;
1907         c->xdp      = !!params->xdp_prog;
1908         c->stats    = &priv->channel_stats[ix].ch;
1909
1910         mlx5_vector2eqn(priv->mdev, ix, &eqn, &irq);
1911         c->irq_desc = irq_to_desc(irq);
1912
1913         netif_napi_add(netdev, &c->napi, mlx5e_napi_poll, 64);
1914
1915         err = mlx5e_open_cq(c, icocq_moder, &cparam->icosq_cq, &c->icosq.cq);
1916         if (err)
1917                 goto err_napi_del;
1918
1919         err = mlx5e_open_tx_cqs(c, params, cparam);
1920         if (err)
1921                 goto err_close_icosq_cq;
1922
1923         err = mlx5e_open_cq(c, params->rx_cq_moderation, &cparam->rx_cq, &c->rq.cq);
1924         if (err)
1925                 goto err_close_tx_cqs;
1926
1927         /* XDP SQ CQ params are same as normal TXQ sq CQ params */
1928         err = c->xdp ? mlx5e_open_cq(c, params->tx_cq_moderation,
1929                                      &cparam->tx_cq, &c->rq.xdpsq.cq) : 0;
1930         if (err)
1931                 goto err_close_rx_cq;
1932
1933         napi_enable(&c->napi);
1934
1935         err = mlx5e_open_icosq(c, params, &cparam->icosq, &c->icosq);
1936         if (err)
1937                 goto err_disable_napi;
1938
1939         err = mlx5e_open_sqs(c, params, cparam);
1940         if (err)
1941                 goto err_close_icosq;
1942
1943         err = c->xdp ? mlx5e_open_xdpsq(c, params, &cparam->xdp_sq, &c->rq.xdpsq) : 0;
1944         if (err)
1945                 goto err_close_sqs;
1946
1947         err = mlx5e_open_rq(c, params, &cparam->rq, &c->rq);
1948         if (err)
1949                 goto err_close_xdp_sq;
1950
1951         *cp = c;
1952
1953         return 0;
1954 err_close_xdp_sq:
1955         if (c->xdp)
1956                 mlx5e_close_xdpsq(&c->rq.xdpsq);
1957
1958 err_close_sqs:
1959         mlx5e_close_sqs(c);
1960
1961 err_close_icosq:
1962         mlx5e_close_icosq(&c->icosq);
1963
1964 err_disable_napi:
1965         napi_disable(&c->napi);
1966         if (c->xdp)
1967                 mlx5e_close_cq(&c->rq.xdpsq.cq);
1968
1969 err_close_rx_cq:
1970         mlx5e_close_cq(&c->rq.cq);
1971
1972 err_close_tx_cqs:
1973         mlx5e_close_tx_cqs(c);
1974
1975 err_close_icosq_cq:
1976         mlx5e_close_cq(&c->icosq.cq);
1977
1978 err_napi_del:
1979         netif_napi_del(&c->napi);
1980         kfree(c);
1981
1982         return err;
1983 }
1984
1985 static void mlx5e_activate_channel(struct mlx5e_channel *c)
1986 {
1987         int tc;
1988
1989         for (tc = 0; tc < c->num_tc; tc++)
1990                 mlx5e_activate_txqsq(&c->sq[tc]);
1991         mlx5e_activate_rq(&c->rq);
1992         netif_set_xps_queue(c->netdev, get_cpu_mask(c->cpu), c->ix);
1993 }
1994
1995 static void mlx5e_deactivate_channel(struct mlx5e_channel *c)
1996 {
1997         int tc;
1998
1999         mlx5e_deactivate_rq(&c->rq);
2000         for (tc = 0; tc < c->num_tc; tc++)
2001                 mlx5e_deactivate_txqsq(&c->sq[tc]);
2002 }
2003
2004 static void mlx5e_close_channel(struct mlx5e_channel *c)
2005 {
2006         mlx5e_close_rq(&c->rq);
2007         if (c->xdp)
2008                 mlx5e_close_xdpsq(&c->rq.xdpsq);
2009         mlx5e_close_sqs(c);
2010         mlx5e_close_icosq(&c->icosq);
2011         napi_disable(&c->napi);
2012         if (c->xdp)
2013                 mlx5e_close_cq(&c->rq.xdpsq.cq);
2014         mlx5e_close_cq(&c->rq.cq);
2015         mlx5e_close_tx_cqs(c);
2016         mlx5e_close_cq(&c->icosq.cq);
2017         netif_napi_del(&c->napi);
2018
2019         kfree(c);
2020 }
2021
2022 #define DEFAULT_FRAG_SIZE (2048)
2023
2024 static void mlx5e_build_rq_frags_info(struct mlx5_core_dev *mdev,
2025                                       struct mlx5e_params *params,
2026                                       struct mlx5e_rq_frags_info *info)
2027 {
2028         u32 byte_count = MLX5E_SW2HW_MTU(params, params->sw_mtu);
2029         int frag_size_max = DEFAULT_FRAG_SIZE;
2030         u32 buf_size = 0;
2031         int i;
2032
2033 #ifdef CONFIG_MLX5_EN_IPSEC
2034         if (MLX5_IPSEC_DEV(mdev))
2035                 byte_count += MLX5E_METADATA_ETHER_LEN;
2036 #endif
2037
2038         if (mlx5e_rx_is_linear_skb(mdev, params)) {
2039                 int frag_stride;
2040
2041                 frag_stride = mlx5e_rx_get_linear_frag_sz(params);
2042                 frag_stride = roundup_pow_of_two(frag_stride);
2043
2044                 info->arr[0].frag_size = byte_count;
2045                 info->arr[0].frag_stride = frag_stride;
2046                 info->num_frags = 1;
2047                 info->wqe_bulk = PAGE_SIZE / frag_stride;
2048                 goto out;
2049         }
2050
2051         if (byte_count > PAGE_SIZE +
2052             (MLX5E_MAX_RX_FRAGS - 1) * frag_size_max)
2053                 frag_size_max = PAGE_SIZE;
2054
2055         i = 0;
2056         while (buf_size < byte_count) {
2057                 int frag_size = byte_count - buf_size;
2058
2059                 if (i < MLX5E_MAX_RX_FRAGS - 1)
2060                         frag_size = min(frag_size, frag_size_max);
2061
2062                 info->arr[i].frag_size = frag_size;
2063                 info->arr[i].frag_stride = roundup_pow_of_two(frag_size);
2064
2065                 buf_size += frag_size;
2066                 i++;
2067         }
2068         info->num_frags = i;
2069         /* number of different wqes sharing a page */
2070         info->wqe_bulk = 1 + (info->num_frags % 2);
2071
2072 out:
2073         info->wqe_bulk = max_t(u8, info->wqe_bulk, 8);
2074         info->log_num_frags = order_base_2(info->num_frags);
2075 }
2076
2077 static inline u8 mlx5e_get_rqwq_log_stride(u8 wq_type, int ndsegs)
2078 {
2079         int sz = sizeof(struct mlx5_wqe_data_seg) * ndsegs;
2080
2081         switch (wq_type) {
2082         case MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ:
2083                 sz += sizeof(struct mlx5e_rx_wqe_ll);
2084                 break;
2085         default: /* MLX5_WQ_TYPE_CYCLIC */
2086                 sz += sizeof(struct mlx5e_rx_wqe_cyc);
2087         }
2088
2089         return order_base_2(sz);
2090 }
2091
2092 static void mlx5e_build_rq_param(struct mlx5e_priv *priv,
2093                                  struct mlx5e_params *params,
2094                                  struct mlx5e_rq_param *param)
2095 {
2096         struct mlx5_core_dev *mdev = priv->mdev;
2097         void *rqc = param->rqc;
2098         void *wq = MLX5_ADDR_OF(rqc, rqc, wq);
2099         int ndsegs = 1;
2100
2101         switch (params->rq_wq_type) {
2102         case MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ:
2103                 MLX5_SET(wq, wq, log_wqe_num_of_strides,
2104                          mlx5e_mpwqe_get_log_num_strides(mdev, params) -
2105                          MLX5_MPWQE_LOG_NUM_STRIDES_BASE);
2106                 MLX5_SET(wq, wq, log_wqe_stride_size,
2107                          mlx5e_mpwqe_get_log_stride_size(mdev, params) -
2108                          MLX5_MPWQE_LOG_STRIDE_SZ_BASE);
2109                 MLX5_SET(wq, wq, log_wq_sz, mlx5e_mpwqe_get_log_rq_size(params));
2110                 break;
2111         default: /* MLX5_WQ_TYPE_CYCLIC */
2112                 MLX5_SET(wq, wq, log_wq_sz, params->log_rq_mtu_frames);
2113                 mlx5e_build_rq_frags_info(mdev, params, &param->frags_info);
2114                 ndsegs = param->frags_info.num_frags;
2115         }
2116
2117         MLX5_SET(wq, wq, wq_type,          params->rq_wq_type);
2118         MLX5_SET(wq, wq, end_padding_mode, MLX5_WQ_END_PAD_MODE_ALIGN);
2119         MLX5_SET(wq, wq, log_wq_stride,
2120                  mlx5e_get_rqwq_log_stride(params->rq_wq_type, ndsegs));
2121         MLX5_SET(wq, wq, pd,               mdev->mlx5e_res.pdn);
2122         MLX5_SET(rqc, rqc, counter_set_id, priv->q_counter);
2123         MLX5_SET(rqc, rqc, vsd,            params->vlan_strip_disable);
2124         MLX5_SET(rqc, rqc, scatter_fcs,    params->scatter_fcs_en);
2125
2126         param->wq.buf_numa_node = dev_to_node(&mdev->pdev->dev);
2127 }
2128
2129 static void mlx5e_build_drop_rq_param(struct mlx5e_priv *priv,
2130                                       struct mlx5e_rq_param *param)
2131 {
2132         struct mlx5_core_dev *mdev = priv->mdev;
2133         void *rqc = param->rqc;
2134         void *wq = MLX5_ADDR_OF(rqc, rqc, wq);
2135
2136         MLX5_SET(wq, wq, wq_type, MLX5_WQ_TYPE_CYCLIC);
2137         MLX5_SET(wq, wq, log_wq_stride,
2138                  mlx5e_get_rqwq_log_stride(MLX5_WQ_TYPE_CYCLIC, 1));
2139         MLX5_SET(rqc, rqc, counter_set_id, priv->drop_rq_q_counter);
2140
2141         param->wq.buf_numa_node = dev_to_node(&mdev->pdev->dev);
2142 }
2143
2144 static void mlx5e_build_sq_param_common(struct mlx5e_priv *priv,
2145                                         struct mlx5e_sq_param *param)
2146 {
2147         void *sqc = param->sqc;
2148         void *wq = MLX5_ADDR_OF(sqc, sqc, wq);
2149
2150         MLX5_SET(wq, wq, log_wq_stride, ilog2(MLX5_SEND_WQE_BB));
2151         MLX5_SET(wq, wq, pd,            priv->mdev->mlx5e_res.pdn);
2152
2153         param->wq.buf_numa_node = dev_to_node(&priv->mdev->pdev->dev);
2154 }
2155
2156 static void mlx5e_build_sq_param(struct mlx5e_priv *priv,
2157                                  struct mlx5e_params *params,
2158                                  struct mlx5e_sq_param *param)
2159 {
2160         void *sqc = param->sqc;
2161         void *wq = MLX5_ADDR_OF(sqc, sqc, wq);
2162
2163         mlx5e_build_sq_param_common(priv, param);
2164         MLX5_SET(wq, wq, log_wq_sz, params->log_sq_size);
2165         MLX5_SET(sqc, sqc, allow_swp, !!MLX5_IPSEC_DEV(priv->mdev));
2166 }
2167
2168 static void mlx5e_build_common_cq_param(struct mlx5e_priv *priv,
2169                                         struct mlx5e_cq_param *param)
2170 {
2171         void *cqc = param->cqc;
2172
2173         MLX5_SET(cqc, cqc, uar_page, priv->mdev->priv.uar->index);
2174 }
2175
2176 static void mlx5e_build_rx_cq_param(struct mlx5e_priv *priv,
2177                                     struct mlx5e_params *params,
2178                                     struct mlx5e_cq_param *param)
2179 {
2180         struct mlx5_core_dev *mdev = priv->mdev;
2181         void *cqc = param->cqc;
2182         u8 log_cq_size;
2183
2184         switch (params->rq_wq_type) {
2185         case MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ:
2186                 log_cq_size = mlx5e_mpwqe_get_log_rq_size(params) +
2187                         mlx5e_mpwqe_get_log_num_strides(mdev, params);
2188                 break;
2189         default: /* MLX5_WQ_TYPE_CYCLIC */
2190                 log_cq_size = params->log_rq_mtu_frames;
2191         }
2192
2193         MLX5_SET(cqc, cqc, log_cq_size, log_cq_size);
2194         if (MLX5E_GET_PFLAG(params, MLX5E_PFLAG_RX_CQE_COMPRESS)) {
2195                 MLX5_SET(cqc, cqc, mini_cqe_res_format, MLX5_CQE_FORMAT_CSUM);
2196                 MLX5_SET(cqc, cqc, cqe_comp_en, 1);
2197         }
2198
2199         mlx5e_build_common_cq_param(priv, param);
2200         param->cq_period_mode = params->rx_cq_moderation.cq_period_mode;
2201 }
2202
2203 static void mlx5e_build_tx_cq_param(struct mlx5e_priv *priv,
2204                                     struct mlx5e_params *params,
2205                                     struct mlx5e_cq_param *param)
2206 {
2207         void *cqc = param->cqc;
2208
2209         MLX5_SET(cqc, cqc, log_cq_size, params->log_sq_size);
2210
2211         mlx5e_build_common_cq_param(priv, param);
2212         param->cq_period_mode = params->tx_cq_moderation.cq_period_mode;
2213 }
2214
2215 static void mlx5e_build_ico_cq_param(struct mlx5e_priv *priv,
2216                                      u8 log_wq_size,
2217                                      struct mlx5e_cq_param *param)
2218 {
2219         void *cqc = param->cqc;
2220
2221         MLX5_SET(cqc, cqc, log_cq_size, log_wq_size);
2222
2223         mlx5e_build_common_cq_param(priv, param);
2224
2225         param->cq_period_mode = NET_DIM_CQ_PERIOD_MODE_START_FROM_EQE;
2226 }
2227
2228 static void mlx5e_build_icosq_param(struct mlx5e_priv *priv,
2229                                     u8 log_wq_size,
2230                                     struct mlx5e_sq_param *param)
2231 {
2232         void *sqc = param->sqc;
2233         void *wq = MLX5_ADDR_OF(sqc, sqc, wq);
2234
2235         mlx5e_build_sq_param_common(priv, param);
2236
2237         MLX5_SET(wq, wq, log_wq_sz, log_wq_size);
2238         MLX5_SET(sqc, sqc, reg_umr, MLX5_CAP_ETH(priv->mdev, reg_umr_sq));
2239 }
2240
2241 static void mlx5e_build_xdpsq_param(struct mlx5e_priv *priv,
2242                                     struct mlx5e_params *params,
2243                                     struct mlx5e_sq_param *param)
2244 {
2245         void *sqc = param->sqc;
2246         void *wq = MLX5_ADDR_OF(sqc, sqc, wq);
2247
2248         mlx5e_build_sq_param_common(priv, param);
2249         MLX5_SET(wq, wq, log_wq_sz, params->log_sq_size);
2250 }
2251
2252 static void mlx5e_build_channel_param(struct mlx5e_priv *priv,
2253                                       struct mlx5e_params *params,
2254                                       struct mlx5e_channel_param *cparam)
2255 {
2256         u8 icosq_log_wq_sz = MLX5E_PARAMS_MINIMUM_LOG_SQ_SIZE;
2257
2258         mlx5e_build_rq_param(priv, params, &cparam->rq);
2259         mlx5e_build_sq_param(priv, params, &cparam->sq);
2260         mlx5e_build_xdpsq_param(priv, params, &cparam->xdp_sq);
2261         mlx5e_build_icosq_param(priv, icosq_log_wq_sz, &cparam->icosq);
2262         mlx5e_build_rx_cq_param(priv, params, &cparam->rx_cq);
2263         mlx5e_build_tx_cq_param(priv, params, &cparam->tx_cq);
2264         mlx5e_build_ico_cq_param(priv, icosq_log_wq_sz, &cparam->icosq_cq);
2265 }
2266
2267 int mlx5e_open_channels(struct mlx5e_priv *priv,
2268                         struct mlx5e_channels *chs)
2269 {
2270         struct mlx5e_channel_param *cparam;
2271         int err = -ENOMEM;
2272         int i;
2273
2274         chs->num = chs->params.num_channels;
2275
2276         chs->c = kcalloc(chs->num, sizeof(struct mlx5e_channel *), GFP_KERNEL);
2277         cparam = kzalloc(sizeof(struct mlx5e_channel_param), GFP_KERNEL);
2278         if (!chs->c || !cparam)
2279                 goto err_free;
2280
2281         mlx5e_build_channel_param(priv, &chs->params, cparam);
2282         for (i = 0; i < chs->num; i++) {
2283                 err = mlx5e_open_channel(priv, i, &chs->params, cparam, &chs->c[i]);
2284                 if (err)
2285                         goto err_close_channels;
2286         }
2287
2288         kfree(cparam);
2289         return 0;
2290
2291 err_close_channels:
2292         for (i--; i >= 0; i--)
2293                 mlx5e_close_channel(chs->c[i]);
2294
2295 err_free:
2296         kfree(chs->c);
2297         kfree(cparam);
2298         chs->num = 0;
2299         return err;
2300 }
2301
2302 static void mlx5e_activate_channels(struct mlx5e_channels *chs)
2303 {
2304         int i;
2305
2306         for (i = 0; i < chs->num; i++)
2307                 mlx5e_activate_channel(chs->c[i]);
2308 }
2309
2310 static int mlx5e_wait_channels_min_rx_wqes(struct mlx5e_channels *chs)
2311 {
2312         int err = 0;
2313         int i;
2314
2315         for (i = 0; i < chs->num; i++)
2316                 err |= mlx5e_wait_for_min_rx_wqes(&chs->c[i]->rq,
2317                                                   err ? 0 : 20000);
2318
2319         return err ? -ETIMEDOUT : 0;
2320 }
2321
2322 static void mlx5e_deactivate_channels(struct mlx5e_channels *chs)
2323 {
2324         int i;
2325
2326         for (i = 0; i < chs->num; i++)
2327                 mlx5e_deactivate_channel(chs->c[i]);
2328 }
2329
2330 void mlx5e_close_channels(struct mlx5e_channels *chs)
2331 {
2332         int i;
2333
2334         for (i = 0; i < chs->num; i++)
2335                 mlx5e_close_channel(chs->c[i]);
2336
2337         kfree(chs->c);
2338         chs->num = 0;
2339 }
2340
2341 static int
2342 mlx5e_create_rqt(struct mlx5e_priv *priv, int sz, struct mlx5e_rqt *rqt)
2343 {
2344         struct mlx5_core_dev *mdev = priv->mdev;
2345         void *rqtc;
2346         int inlen;
2347         int err;
2348         u32 *in;
2349         int i;
2350
2351         inlen = MLX5_ST_SZ_BYTES(create_rqt_in) + sizeof(u32) * sz;
2352         in = kvzalloc(inlen, GFP_KERNEL);
2353         if (!in)
2354                 return -ENOMEM;
2355
2356         rqtc = MLX5_ADDR_OF(create_rqt_in, in, rqt_context);
2357
2358         MLX5_SET(rqtc, rqtc, rqt_actual_size, sz);
2359         MLX5_SET(rqtc, rqtc, rqt_max_size, sz);
2360
2361         for (i = 0; i < sz; i++)
2362                 MLX5_SET(rqtc, rqtc, rq_num[i], priv->drop_rq.rqn);
2363
2364         err = mlx5_core_create_rqt(mdev, in, inlen, &rqt->rqtn);
2365         if (!err)
2366                 rqt->enabled = true;
2367
2368         kvfree(in);
2369         return err;
2370 }
2371
2372 void mlx5e_destroy_rqt(struct mlx5e_priv *priv, struct mlx5e_rqt *rqt)
2373 {
2374         rqt->enabled = false;
2375         mlx5_core_destroy_rqt(priv->mdev, rqt->rqtn);
2376 }
2377
2378 int mlx5e_create_indirect_rqt(struct mlx5e_priv *priv)
2379 {
2380         struct mlx5e_rqt *rqt = &priv->indir_rqt;
2381         int err;
2382
2383         err = mlx5e_create_rqt(priv, MLX5E_INDIR_RQT_SIZE, rqt);
2384         if (err)
2385                 mlx5_core_warn(priv->mdev, "create indirect rqts failed, %d\n", err);
2386         return err;
2387 }
2388
2389 int mlx5e_create_direct_rqts(struct mlx5e_priv *priv)
2390 {
2391         struct mlx5e_rqt *rqt;
2392         int err;
2393         int ix;
2394
2395         for (ix = 0; ix < priv->profile->max_nch(priv->mdev); ix++) {
2396                 rqt = &priv->direct_tir[ix].rqt;
2397                 err = mlx5e_create_rqt(priv, 1 /*size */, rqt);
2398                 if (err)
2399                         goto err_destroy_rqts;
2400         }
2401
2402         return 0;
2403
2404 err_destroy_rqts:
2405         mlx5_core_warn(priv->mdev, "create direct rqts failed, %d\n", err);
2406         for (ix--; ix >= 0; ix--)
2407                 mlx5e_destroy_rqt(priv, &priv->direct_tir[ix].rqt);
2408
2409         return err;
2410 }
2411
2412 void mlx5e_destroy_direct_rqts(struct mlx5e_priv *priv)
2413 {
2414         int i;
2415
2416         for (i = 0; i < priv->profile->max_nch(priv->mdev); i++)
2417                 mlx5e_destroy_rqt(priv, &priv->direct_tir[i].rqt);
2418 }
2419
2420 static int mlx5e_rx_hash_fn(int hfunc)
2421 {
2422         return (hfunc == ETH_RSS_HASH_TOP) ?
2423                MLX5_RX_HASH_FN_TOEPLITZ :
2424                MLX5_RX_HASH_FN_INVERTED_XOR8;
2425 }
2426
2427 int mlx5e_bits_invert(unsigned long a, int size)
2428 {
2429         int inv = 0;
2430         int i;
2431
2432         for (i = 0; i < size; i++)
2433                 inv |= (test_bit(size - i - 1, &a) ? 1 : 0) << i;
2434
2435         return inv;
2436 }
2437
2438 static void mlx5e_fill_rqt_rqns(struct mlx5e_priv *priv, int sz,
2439                                 struct mlx5e_redirect_rqt_param rrp, void *rqtc)
2440 {
2441         int i;
2442
2443         for (i = 0; i < sz; i++) {
2444                 u32 rqn;
2445
2446                 if (rrp.is_rss) {
2447                         int ix = i;
2448
2449                         if (rrp.rss.hfunc == ETH_RSS_HASH_XOR)
2450                                 ix = mlx5e_bits_invert(i, ilog2(sz));
2451
2452                         ix = priv->channels.params.indirection_rqt[ix];
2453                         rqn = rrp.rss.channels->c[ix]->rq.rqn;
2454                 } else {
2455                         rqn = rrp.rqn;
2456                 }
2457                 MLX5_SET(rqtc, rqtc, rq_num[i], rqn);
2458         }
2459 }
2460
2461 int mlx5e_redirect_rqt(struct mlx5e_priv *priv, u32 rqtn, int sz,
2462                        struct mlx5e_redirect_rqt_param rrp)
2463 {
2464         struct mlx5_core_dev *mdev = priv->mdev;
2465         void *rqtc;
2466         int inlen;
2467         u32 *in;
2468         int err;
2469
2470         inlen = MLX5_ST_SZ_BYTES(modify_rqt_in) + sizeof(u32) * sz;
2471         in = kvzalloc(inlen, GFP_KERNEL);
2472         if (!in)
2473                 return -ENOMEM;
2474
2475         rqtc = MLX5_ADDR_OF(modify_rqt_in, in, ctx);
2476
2477         MLX5_SET(rqtc, rqtc, rqt_actual_size, sz);
2478         MLX5_SET(modify_rqt_in, in, bitmask.rqn_list, 1);
2479         mlx5e_fill_rqt_rqns(priv, sz, rrp, rqtc);
2480         err = mlx5_core_modify_rqt(mdev, rqtn, in, inlen);
2481
2482         kvfree(in);
2483         return err;
2484 }
2485
2486 static u32 mlx5e_get_direct_rqn(struct mlx5e_priv *priv, int ix,
2487                                 struct mlx5e_redirect_rqt_param rrp)
2488 {
2489         if (!rrp.is_rss)
2490                 return rrp.rqn;
2491
2492         if (ix >= rrp.rss.channels->num)
2493                 return priv->drop_rq.rqn;
2494
2495         return rrp.rss.channels->c[ix]->rq.rqn;
2496 }
2497
2498 static void mlx5e_redirect_rqts(struct mlx5e_priv *priv,
2499                                 struct mlx5e_redirect_rqt_param rrp)
2500 {
2501         u32 rqtn;
2502         int ix;
2503
2504         if (priv->indir_rqt.enabled) {
2505                 /* RSS RQ table */
2506                 rqtn = priv->indir_rqt.rqtn;
2507                 mlx5e_redirect_rqt(priv, rqtn, MLX5E_INDIR_RQT_SIZE, rrp);
2508         }
2509
2510         for (ix = 0; ix < priv->profile->max_nch(priv->mdev); ix++) {
2511                 struct mlx5e_redirect_rqt_param direct_rrp = {
2512                         .is_rss = false,
2513                         {
2514                                 .rqn    = mlx5e_get_direct_rqn(priv, ix, rrp)
2515                         },
2516                 };
2517
2518                 /* Direct RQ Tables */
2519                 if (!priv->direct_tir[ix].rqt.enabled)
2520                         continue;
2521
2522                 rqtn = priv->direct_tir[ix].rqt.rqtn;
2523                 mlx5e_redirect_rqt(priv, rqtn, 1, direct_rrp);
2524         }
2525 }
2526
2527 static void mlx5e_redirect_rqts_to_channels(struct mlx5e_priv *priv,
2528                                             struct mlx5e_channels *chs)
2529 {
2530         struct mlx5e_redirect_rqt_param rrp = {
2531                 .is_rss        = true,
2532                 {
2533                         .rss = {
2534                                 .channels  = chs,
2535                                 .hfunc     = chs->params.rss_hfunc,
2536                         }
2537                 },
2538         };
2539
2540         mlx5e_redirect_rqts(priv, rrp);
2541 }
2542
2543 static void mlx5e_redirect_rqts_to_drop(struct mlx5e_priv *priv)
2544 {
2545         struct mlx5e_redirect_rqt_param drop_rrp = {
2546                 .is_rss = false,
2547                 {
2548                         .rqn = priv->drop_rq.rqn,
2549                 },
2550         };
2551
2552         mlx5e_redirect_rqts(priv, drop_rrp);
2553 }
2554
2555 static void mlx5e_build_tir_ctx_lro(struct mlx5e_params *params, void *tirc)
2556 {
2557         if (!params->lro_en)
2558                 return;
2559
2560 #define ROUGH_MAX_L2_L3_HDR_SZ 256
2561
2562         MLX5_SET(tirc, tirc, lro_enable_mask,
2563                  MLX5_TIRC_LRO_ENABLE_MASK_IPV4_LRO |
2564                  MLX5_TIRC_LRO_ENABLE_MASK_IPV6_LRO);
2565         MLX5_SET(tirc, tirc, lro_max_ip_payload_size,
2566                  (params->lro_wqe_sz - ROUGH_MAX_L2_L3_HDR_SZ) >> 8);
2567         MLX5_SET(tirc, tirc, lro_timeout_period_usecs, params->lro_timeout);
2568 }
2569
2570 void mlx5e_build_indir_tir_ctx_hash(struct mlx5e_params *params,
2571                                     enum mlx5e_traffic_types tt,
2572                                     void *tirc, bool inner)
2573 {
2574         void *hfso = inner ? MLX5_ADDR_OF(tirc, tirc, rx_hash_field_selector_inner) :
2575                              MLX5_ADDR_OF(tirc, tirc, rx_hash_field_selector_outer);
2576
2577 #define MLX5_HASH_IP            (MLX5_HASH_FIELD_SEL_SRC_IP   |\
2578                                  MLX5_HASH_FIELD_SEL_DST_IP)
2579
2580 #define MLX5_HASH_IP_L4PORTS    (MLX5_HASH_FIELD_SEL_SRC_IP   |\
2581                                  MLX5_HASH_FIELD_SEL_DST_IP   |\
2582                                  MLX5_HASH_FIELD_SEL_L4_SPORT |\
2583                                  MLX5_HASH_FIELD_SEL_L4_DPORT)
2584
2585 #define MLX5_HASH_IP_IPSEC_SPI  (MLX5_HASH_FIELD_SEL_SRC_IP   |\
2586                                  MLX5_HASH_FIELD_SEL_DST_IP   |\
2587                                  MLX5_HASH_FIELD_SEL_IPSEC_SPI)
2588
2589         MLX5_SET(tirc, tirc, rx_hash_fn, mlx5e_rx_hash_fn(params->rss_hfunc));
2590         if (params->rss_hfunc == ETH_RSS_HASH_TOP) {
2591                 void *rss_key = MLX5_ADDR_OF(tirc, tirc,
2592                                              rx_hash_toeplitz_key);
2593                 size_t len = MLX5_FLD_SZ_BYTES(tirc,
2594                                                rx_hash_toeplitz_key);
2595
2596                 MLX5_SET(tirc, tirc, rx_hash_symmetric, 1);
2597                 memcpy(rss_key, params->toeplitz_hash_key, len);
2598         }
2599
2600         switch (tt) {
2601         case MLX5E_TT_IPV4_TCP:
2602                 MLX5_SET(rx_hash_field_select, hfso, l3_prot_type,
2603                          MLX5_L3_PROT_TYPE_IPV4);
2604                 MLX5_SET(rx_hash_field_select, hfso, l4_prot_type,
2605                          MLX5_L4_PROT_TYPE_TCP);
2606                 MLX5_SET(rx_hash_field_select, hfso, selected_fields,
2607                          MLX5_HASH_IP_L4PORTS);
2608                 break;
2609
2610         case MLX5E_TT_IPV6_TCP:
2611                 MLX5_SET(rx_hash_field_select, hfso, l3_prot_type,
2612                          MLX5_L3_PROT_TYPE_IPV6);
2613                 MLX5_SET(rx_hash_field_select, hfso, l4_prot_type,
2614                          MLX5_L4_PROT_TYPE_TCP);
2615                 MLX5_SET(rx_hash_field_select, hfso, selected_fields,
2616                          MLX5_HASH_IP_L4PORTS);
2617                 break;
2618
2619         case MLX5E_TT_IPV4_UDP:
2620                 MLX5_SET(rx_hash_field_select, hfso, l3_prot_type,
2621                          MLX5_L3_PROT_TYPE_IPV4);
2622                 MLX5_SET(rx_hash_field_select, hfso, l4_prot_type,
2623                          MLX5_L4_PROT_TYPE_UDP);
2624                 MLX5_SET(rx_hash_field_select, hfso, selected_fields,
2625                          MLX5_HASH_IP_L4PORTS);
2626                 break;
2627
2628         case MLX5E_TT_IPV6_UDP:
2629                 MLX5_SET(rx_hash_field_select, hfso, l3_prot_type,
2630                          MLX5_L3_PROT_TYPE_IPV6);
2631                 MLX5_SET(rx_hash_field_select, hfso, l4_prot_type,
2632                          MLX5_L4_PROT_TYPE_UDP);
2633                 MLX5_SET(rx_hash_field_select, hfso, selected_fields,
2634                          MLX5_HASH_IP_L4PORTS);
2635                 break;
2636
2637         case MLX5E_TT_IPV4_IPSEC_AH:
2638                 MLX5_SET(rx_hash_field_select, hfso, l3_prot_type,
2639                          MLX5_L3_PROT_TYPE_IPV4);
2640                 MLX5_SET(rx_hash_field_select, hfso, selected_fields,
2641                          MLX5_HASH_IP_IPSEC_SPI);
2642                 break;
2643
2644         case MLX5E_TT_IPV6_IPSEC_AH:
2645                 MLX5_SET(rx_hash_field_select, hfso, l3_prot_type,
2646                          MLX5_L3_PROT_TYPE_IPV6);
2647                 MLX5_SET(rx_hash_field_select, hfso, selected_fields,
2648                          MLX5_HASH_IP_IPSEC_SPI);
2649                 break;
2650
2651         case MLX5E_TT_IPV4_IPSEC_ESP:
2652                 MLX5_SET(rx_hash_field_select, hfso, l3_prot_type,
2653                          MLX5_L3_PROT_TYPE_IPV4);
2654                 MLX5_SET(rx_hash_field_select, hfso, selected_fields,
2655                          MLX5_HASH_IP_IPSEC_SPI);
2656                 break;
2657
2658         case MLX5E_TT_IPV6_IPSEC_ESP:
2659                 MLX5_SET(rx_hash_field_select, hfso, l3_prot_type,
2660                          MLX5_L3_PROT_TYPE_IPV6);
2661                 MLX5_SET(rx_hash_field_select, hfso, selected_fields,
2662                          MLX5_HASH_IP_IPSEC_SPI);
2663                 break;
2664
2665         case MLX5E_TT_IPV4:
2666                 MLX5_SET(rx_hash_field_select, hfso, l3_prot_type,
2667                          MLX5_L3_PROT_TYPE_IPV4);
2668                 MLX5_SET(rx_hash_field_select, hfso, selected_fields,
2669                          MLX5_HASH_IP);
2670                 break;
2671
2672         case MLX5E_TT_IPV6:
2673                 MLX5_SET(rx_hash_field_select, hfso, l3_prot_type,
2674                          MLX5_L3_PROT_TYPE_IPV6);
2675                 MLX5_SET(rx_hash_field_select, hfso, selected_fields,
2676                          MLX5_HASH_IP);
2677                 break;
2678         default:
2679                 WARN_ONCE(true, "%s: bad traffic type!\n", __func__);
2680         }
2681 }
2682
2683 static int mlx5e_modify_tirs_lro(struct mlx5e_priv *priv)
2684 {
2685         struct mlx5_core_dev *mdev = priv->mdev;
2686
2687         void *in;
2688         void *tirc;
2689         int inlen;
2690         int err;
2691         int tt;
2692         int ix;
2693
2694         inlen = MLX5_ST_SZ_BYTES(modify_tir_in);
2695         in = kvzalloc(inlen, GFP_KERNEL);
2696         if (!in)
2697                 return -ENOMEM;
2698
2699         MLX5_SET(modify_tir_in, in, bitmask.lro, 1);
2700         tirc = MLX5_ADDR_OF(modify_tir_in, in, ctx);
2701
2702         mlx5e_build_tir_ctx_lro(&priv->channels.params, tirc);
2703
2704         for (tt = 0; tt < MLX5E_NUM_INDIR_TIRS; tt++) {
2705                 err = mlx5_core_modify_tir(mdev, priv->indir_tir[tt].tirn, in,
2706                                            inlen);
2707                 if (err)
2708                         goto free_in;
2709         }
2710
2711         for (ix = 0; ix < priv->profile->max_nch(priv->mdev); ix++) {
2712                 err = mlx5_core_modify_tir(mdev, priv->direct_tir[ix].tirn,
2713                                            in, inlen);
2714                 if (err)
2715                         goto free_in;
2716         }
2717
2718 free_in:
2719         kvfree(in);
2720
2721         return err;
2722 }
2723
2724 static void mlx5e_build_inner_indir_tir_ctx(struct mlx5e_priv *priv,
2725                                             enum mlx5e_traffic_types tt,
2726                                             u32 *tirc)
2727 {
2728         MLX5_SET(tirc, tirc, transport_domain, priv->mdev->mlx5e_res.td.tdn);
2729
2730         mlx5e_build_tir_ctx_lro(&priv->channels.params, tirc);
2731
2732         MLX5_SET(tirc, tirc, disp_type, MLX5_TIRC_DISP_TYPE_INDIRECT);
2733         MLX5_SET(tirc, tirc, indirect_table, priv->indir_rqt.rqtn);
2734         MLX5_SET(tirc, tirc, tunneled_offload_en, 0x1);
2735
2736         mlx5e_build_indir_tir_ctx_hash(&priv->channels.params, tt, tirc, true);
2737 }
2738
2739 static int mlx5e_set_mtu(struct mlx5_core_dev *mdev,
2740                          struct mlx5e_params *params, u16 mtu)
2741 {
2742         u16 hw_mtu = MLX5E_SW2HW_MTU(params, mtu);
2743         int err;
2744
2745         err = mlx5_set_port_mtu(mdev, hw_mtu, 1);
2746         if (err)
2747                 return err;
2748
2749         /* Update vport context MTU */
2750         mlx5_modify_nic_vport_mtu(mdev, hw_mtu);
2751         return 0;
2752 }
2753
2754 static void mlx5e_query_mtu(struct mlx5_core_dev *mdev,
2755                             struct mlx5e_params *params, u16 *mtu)
2756 {
2757         u16 hw_mtu = 0;
2758         int err;
2759
2760         err = mlx5_query_nic_vport_mtu(mdev, &hw_mtu);
2761         if (err || !hw_mtu) /* fallback to port oper mtu */
2762                 mlx5_query_port_oper_mtu(mdev, &hw_mtu, 1);
2763
2764         *mtu = MLX5E_HW2SW_MTU(params, hw_mtu);
2765 }
2766
2767 static int mlx5e_set_dev_port_mtu(struct mlx5e_priv *priv)
2768 {
2769         struct mlx5e_params *params = &priv->channels.params;
2770         struct net_device *netdev = priv->netdev;
2771         struct mlx5_core_dev *mdev = priv->mdev;
2772         u16 mtu;
2773         int err;
2774
2775         err = mlx5e_set_mtu(mdev, params, params->sw_mtu);
2776         if (err)
2777                 return err;
2778
2779         mlx5e_query_mtu(mdev, params, &mtu);
2780         if (mtu != params->sw_mtu)
2781                 netdev_warn(netdev, "%s: VPort MTU %d is different than netdev mtu %d\n",
2782                             __func__, mtu, params->sw_mtu);
2783
2784         params->sw_mtu = mtu;
2785         return 0;
2786 }
2787
2788 static void mlx5e_netdev_set_tcs(struct net_device *netdev)
2789 {
2790         struct mlx5e_priv *priv = netdev_priv(netdev);
2791         int nch = priv->channels.params.num_channels;
2792         int ntc = priv->channels.params.num_tc;
2793         int tc;
2794
2795         netdev_reset_tc(netdev);
2796
2797         if (ntc == 1)
2798                 return;
2799
2800         netdev_set_num_tc(netdev, ntc);
2801
2802         /* Map netdev TCs to offset 0
2803          * We have our own UP to TXQ mapping for QoS
2804          */
2805         for (tc = 0; tc < ntc; tc++)
2806                 netdev_set_tc_queue(netdev, tc, nch, 0);
2807 }
2808
2809 static void mlx5e_build_tc2txq_maps(struct mlx5e_priv *priv)
2810 {
2811         int max_nch = priv->profile->max_nch(priv->mdev);
2812         int i, tc;
2813
2814         for (i = 0; i < max_nch; i++)
2815                 for (tc = 0; tc < priv->profile->max_tc; tc++)
2816                         priv->channel_tc2txq[i][tc] = i + tc * max_nch;
2817 }
2818
2819 static void mlx5e_build_tx2sq_maps(struct mlx5e_priv *priv)
2820 {
2821         struct mlx5e_channel *c;
2822         struct mlx5e_txqsq *sq;
2823         int i, tc;
2824
2825         for (i = 0; i < priv->channels.num; i++) {
2826                 c = priv->channels.c[i];
2827                 for (tc = 0; tc < c->num_tc; tc++) {
2828                         sq = &c->sq[tc];
2829                         priv->txq2sq[sq->txq_ix] = sq;
2830                 }
2831         }
2832 }
2833
2834 void mlx5e_activate_priv_channels(struct mlx5e_priv *priv)
2835 {
2836         int num_txqs = priv->channels.num * priv->channels.params.num_tc;
2837         struct net_device *netdev = priv->netdev;
2838
2839         mlx5e_netdev_set_tcs(netdev);
2840         netif_set_real_num_tx_queues(netdev, num_txqs);
2841         netif_set_real_num_rx_queues(netdev, priv->channels.num);
2842
2843         mlx5e_build_tx2sq_maps(priv);
2844         mlx5e_activate_channels(&priv->channels);
2845         netif_tx_start_all_queues(priv->netdev);
2846
2847         if (MLX5_VPORT_MANAGER(priv->mdev))
2848                 mlx5e_add_sqs_fwd_rules(priv);
2849
2850         mlx5e_wait_channels_min_rx_wqes(&priv->channels);
2851         mlx5e_redirect_rqts_to_channels(priv, &priv->channels);
2852 }
2853
2854 void mlx5e_deactivate_priv_channels(struct mlx5e_priv *priv)
2855 {
2856         mlx5e_redirect_rqts_to_drop(priv);
2857
2858         if (MLX5_VPORT_MANAGER(priv->mdev))
2859                 mlx5e_remove_sqs_fwd_rules(priv);
2860
2861         /* FIXME: This is a W/A only for tx timeout watch dog false alarm when
2862          * polling for inactive tx queues.
2863          */
2864         netif_tx_stop_all_queues(priv->netdev);
2865         netif_tx_disable(priv->netdev);
2866         mlx5e_deactivate_channels(&priv->channels);
2867 }
2868
2869 void mlx5e_switch_priv_channels(struct mlx5e_priv *priv,
2870                                 struct mlx5e_channels *new_chs,
2871                                 mlx5e_fp_hw_modify hw_modify)
2872 {
2873         struct net_device *netdev = priv->netdev;
2874         int new_num_txqs;
2875         int carrier_ok;
2876         new_num_txqs = new_chs->num * new_chs->params.num_tc;
2877
2878         carrier_ok = netif_carrier_ok(netdev);
2879         netif_carrier_off(netdev);
2880
2881         if (new_num_txqs < netdev->real_num_tx_queues)
2882                 netif_set_real_num_tx_queues(netdev, new_num_txqs);
2883
2884         mlx5e_deactivate_priv_channels(priv);
2885         mlx5e_close_channels(&priv->channels);
2886
2887         priv->channels = *new_chs;
2888
2889         /* New channels are ready to roll, modify HW settings if needed */
2890         if (hw_modify)
2891                 hw_modify(priv);
2892
2893         mlx5e_refresh_tirs(priv, false);
2894         mlx5e_activate_priv_channels(priv);
2895
2896         /* return carrier back if needed */
2897         if (carrier_ok)
2898                 netif_carrier_on(netdev);
2899 }
2900
2901 void mlx5e_timestamp_init(struct mlx5e_priv *priv)
2902 {
2903         priv->tstamp.tx_type   = HWTSTAMP_TX_OFF;
2904         priv->tstamp.rx_filter = HWTSTAMP_FILTER_NONE;
2905 }
2906
2907 int mlx5e_open_locked(struct net_device *netdev)
2908 {
2909         struct mlx5e_priv *priv = netdev_priv(netdev);
2910         int err;
2911
2912         set_bit(MLX5E_STATE_OPENED, &priv->state);
2913
2914         err = mlx5e_open_channels(priv, &priv->channels);
2915         if (err)
2916                 goto err_clear_state_opened_flag;
2917
2918         mlx5e_refresh_tirs(priv, false);
2919         mlx5e_activate_priv_channels(priv);
2920         if (priv->profile->update_carrier)
2921                 priv->profile->update_carrier(priv);
2922
2923         if (priv->profile->update_stats)
2924                 queue_delayed_work(priv->wq, &priv->update_stats_work, 0);
2925
2926         return 0;
2927
2928 err_clear_state_opened_flag:
2929         clear_bit(MLX5E_STATE_OPENED, &priv->state);
2930         return err;
2931 }
2932
2933 int mlx5e_open(struct net_device *netdev)
2934 {
2935         struct mlx5e_priv *priv = netdev_priv(netdev);
2936         int err;
2937
2938         mutex_lock(&priv->state_lock);
2939         err = mlx5e_open_locked(netdev);
2940         if (!err)
2941                 mlx5_set_port_admin_status(priv->mdev, MLX5_PORT_UP);
2942         mutex_unlock(&priv->state_lock);
2943
2944         if (mlx5e_vxlan_allowed(priv->mdev))
2945                 udp_tunnel_get_rx_info(netdev);
2946
2947         return err;
2948 }
2949
2950 int mlx5e_close_locked(struct net_device *netdev)
2951 {
2952         struct mlx5e_priv *priv = netdev_priv(netdev);
2953
2954         /* May already be CLOSED in case a previous configuration operation
2955          * (e.g RX/TX queue size change) that involves close&open failed.
2956          */
2957         if (!test_bit(MLX5E_STATE_OPENED, &priv->state))
2958                 return 0;
2959
2960         clear_bit(MLX5E_STATE_OPENED, &priv->state);
2961
2962         netif_carrier_off(priv->netdev);
2963         mlx5e_deactivate_priv_channels(priv);
2964         mlx5e_close_channels(&priv->channels);
2965
2966         return 0;
2967 }
2968
2969 int mlx5e_close(struct net_device *netdev)
2970 {
2971         struct mlx5e_priv *priv = netdev_priv(netdev);
2972         int err;
2973
2974         if (!netif_device_present(netdev))
2975                 return -ENODEV;
2976
2977         mutex_lock(&priv->state_lock);
2978         mlx5_set_port_admin_status(priv->mdev, MLX5_PORT_DOWN);
2979         err = mlx5e_close_locked(netdev);
2980         mutex_unlock(&priv->state_lock);
2981
2982         return err;
2983 }
2984
2985 static int mlx5e_alloc_drop_rq(struct mlx5_core_dev *mdev,
2986                                struct mlx5e_rq *rq,
2987                                struct mlx5e_rq_param *param)
2988 {
2989         void *rqc = param->rqc;
2990         void *rqc_wq = MLX5_ADDR_OF(rqc, rqc, wq);
2991         int err;
2992
2993         param->wq.db_numa_node = param->wq.buf_numa_node;
2994
2995         err = mlx5_wq_cyc_create(mdev, &param->wq, rqc_wq, &rq->wqe.wq,
2996                                  &rq->wq_ctrl);
2997         if (err)
2998                 return err;
2999
3000         /* Mark as unused given "Drop-RQ" packets never reach XDP */
3001         xdp_rxq_info_unused(&rq->xdp_rxq);
3002
3003         rq->mdev = mdev;
3004
3005         return 0;
3006 }
3007
3008 static int mlx5e_alloc_drop_cq(struct mlx5_core_dev *mdev,
3009                                struct mlx5e_cq *cq,
3010                                struct mlx5e_cq_param *param)
3011 {
3012         param->wq.buf_numa_node = dev_to_node(&mdev->pdev->dev);
3013         param->wq.db_numa_node  = dev_to_node(&mdev->pdev->dev);
3014
3015         return mlx5e_alloc_cq_common(mdev, param, cq);
3016 }
3017
3018 static int mlx5e_open_drop_rq(struct mlx5e_priv *priv,
3019                               struct mlx5e_rq *drop_rq)
3020 {
3021         struct mlx5_core_dev *mdev = priv->mdev;
3022         struct mlx5e_cq_param cq_param = {};
3023         struct mlx5e_rq_param rq_param = {};
3024         struct mlx5e_cq *cq = &drop_rq->cq;
3025         int err;
3026
3027         mlx5e_build_drop_rq_param(priv, &rq_param);
3028
3029         err = mlx5e_alloc_drop_cq(mdev, cq, &cq_param);
3030         if (err)
3031                 return err;
3032
3033         err = mlx5e_create_cq(cq, &cq_param);
3034         if (err)
3035                 goto err_free_cq;
3036
3037         err = mlx5e_alloc_drop_rq(mdev, drop_rq, &rq_param);
3038         if (err)
3039                 goto err_destroy_cq;
3040
3041         err = mlx5e_create_rq(drop_rq, &rq_param);
3042         if (err)
3043                 goto err_free_rq;
3044
3045         err = mlx5e_modify_rq_state(drop_rq, MLX5_RQC_STATE_RST, MLX5_RQC_STATE_RDY);
3046         if (err)
3047                 mlx5_core_warn(priv->mdev, "modify_rq_state failed, rx_if_down_packets won't be counted %d\n", err);
3048
3049         return 0;
3050
3051 err_free_rq:
3052         mlx5e_free_rq(drop_rq);
3053
3054 err_destroy_cq:
3055         mlx5e_destroy_cq(cq);
3056
3057 err_free_cq:
3058         mlx5e_free_cq(cq);
3059
3060         return err;
3061 }
3062
3063 static void mlx5e_close_drop_rq(struct mlx5e_rq *drop_rq)
3064 {
3065         mlx5e_destroy_rq(drop_rq);
3066         mlx5e_free_rq(drop_rq);
3067         mlx5e_destroy_cq(&drop_rq->cq);
3068         mlx5e_free_cq(&drop_rq->cq);
3069 }
3070
3071 int mlx5e_create_tis(struct mlx5_core_dev *mdev, int tc,
3072                      u32 underlay_qpn, u32 *tisn)
3073 {
3074         u32 in[MLX5_ST_SZ_DW(create_tis_in)] = {0};
3075         void *tisc = MLX5_ADDR_OF(create_tis_in, in, ctx);
3076
3077         MLX5_SET(tisc, tisc, prio, tc << 1);
3078         MLX5_SET(tisc, tisc, underlay_qpn, underlay_qpn);
3079         MLX5_SET(tisc, tisc, transport_domain, mdev->mlx5e_res.td.tdn);
3080
3081         if (mlx5_lag_is_lacp_owner(mdev))
3082                 MLX5_SET(tisc, tisc, strict_lag_tx_port_affinity, 1);
3083
3084         return mlx5_core_create_tis(mdev, in, sizeof(in), tisn);
3085 }
3086
3087 void mlx5e_destroy_tis(struct mlx5_core_dev *mdev, u32 tisn)
3088 {
3089         mlx5_core_destroy_tis(mdev, tisn);
3090 }
3091
3092 int mlx5e_create_tises(struct mlx5e_priv *priv)
3093 {
3094         int err;
3095         int tc;
3096
3097         for (tc = 0; tc < priv->profile->max_tc; tc++) {
3098                 err = mlx5e_create_tis(priv->mdev, tc, 0, &priv->tisn[tc]);
3099                 if (err)
3100                         goto err_close_tises;
3101         }
3102
3103         return 0;
3104
3105 err_close_tises:
3106         for (tc--; tc >= 0; tc--)
3107                 mlx5e_destroy_tis(priv->mdev, priv->tisn[tc]);
3108
3109         return err;
3110 }
3111
3112 void mlx5e_cleanup_nic_tx(struct mlx5e_priv *priv)
3113 {
3114         int tc;
3115
3116         for (tc = 0; tc < priv->profile->max_tc; tc++)
3117                 mlx5e_destroy_tis(priv->mdev, priv->tisn[tc]);
3118 }
3119
3120 static void mlx5e_build_indir_tir_ctx(struct mlx5e_priv *priv,
3121                                       enum mlx5e_traffic_types tt,
3122                                       u32 *tirc)
3123 {
3124         MLX5_SET(tirc, tirc, transport_domain, priv->mdev->mlx5e_res.td.tdn);
3125
3126         mlx5e_build_tir_ctx_lro(&priv->channels.params, tirc);
3127
3128         MLX5_SET(tirc, tirc, disp_type, MLX5_TIRC_DISP_TYPE_INDIRECT);
3129         MLX5_SET(tirc, tirc, indirect_table, priv->indir_rqt.rqtn);
3130         mlx5e_build_indir_tir_ctx_hash(&priv->channels.params, tt, tirc, false);
3131 }
3132
3133 static void mlx5e_build_direct_tir_ctx(struct mlx5e_priv *priv, u32 rqtn, u32 *tirc)
3134 {
3135         MLX5_SET(tirc, tirc, transport_domain, priv->mdev->mlx5e_res.td.tdn);
3136
3137         mlx5e_build_tir_ctx_lro(&priv->channels.params, tirc);
3138
3139         MLX5_SET(tirc, tirc, disp_type, MLX5_TIRC_DISP_TYPE_INDIRECT);
3140         MLX5_SET(tirc, tirc, indirect_table, rqtn);
3141         MLX5_SET(tirc, tirc, rx_hash_fn, MLX5_RX_HASH_FN_INVERTED_XOR8);
3142 }
3143
3144 int mlx5e_create_indirect_tirs(struct mlx5e_priv *priv)
3145 {
3146         struct mlx5e_tir *tir;
3147         void *tirc;
3148         int inlen;
3149         int i = 0;
3150         int err;
3151         u32 *in;
3152         int tt;
3153
3154         inlen = MLX5_ST_SZ_BYTES(create_tir_in);
3155         in = kvzalloc(inlen, GFP_KERNEL);
3156         if (!in)
3157                 return -ENOMEM;
3158
3159         for (tt = 0; tt < MLX5E_NUM_INDIR_TIRS; tt++) {
3160                 memset(in, 0, inlen);
3161                 tir = &priv->indir_tir[tt];
3162                 tirc = MLX5_ADDR_OF(create_tir_in, in, ctx);
3163                 mlx5e_build_indir_tir_ctx(priv, tt, tirc);
3164                 err = mlx5e_create_tir(priv->mdev, tir, in, inlen);
3165                 if (err) {
3166                         mlx5_core_warn(priv->mdev, "create indirect tirs failed, %d\n", err);
3167                         goto err_destroy_inner_tirs;
3168                 }
3169         }
3170
3171         if (!mlx5e_tunnel_inner_ft_supported(priv->mdev))
3172                 goto out;
3173
3174         for (i = 0; i < MLX5E_NUM_INDIR_TIRS; i++) {
3175                 memset(in, 0, inlen);
3176                 tir = &priv->inner_indir_tir[i];
3177                 tirc = MLX5_ADDR_OF(create_tir_in, in, ctx);
3178                 mlx5e_build_inner_indir_tir_ctx(priv, i, tirc);
3179                 err = mlx5e_create_tir(priv->mdev, tir, in, inlen);
3180                 if (err) {
3181                         mlx5_core_warn(priv->mdev, "create inner indirect tirs failed, %d\n", err);
3182                         goto err_destroy_inner_tirs;
3183                 }
3184         }
3185
3186 out:
3187         kvfree(in);
3188
3189         return 0;
3190
3191 err_destroy_inner_tirs:
3192         for (i--; i >= 0; i--)
3193                 mlx5e_destroy_tir(priv->mdev, &priv->inner_indir_tir[i]);
3194
3195         for (tt--; tt >= 0; tt--)
3196                 mlx5e_destroy_tir(priv->mdev, &priv->indir_tir[tt]);
3197
3198         kvfree(in);
3199
3200         return err;
3201 }
3202
3203 int mlx5e_create_direct_tirs(struct mlx5e_priv *priv)
3204 {
3205         int nch = priv->profile->max_nch(priv->mdev);
3206         struct mlx5e_tir *tir;
3207         void *tirc;
3208         int inlen;
3209         int err;
3210         u32 *in;
3211         int ix;
3212
3213         inlen = MLX5_ST_SZ_BYTES(create_tir_in);
3214         in = kvzalloc(inlen, GFP_KERNEL);
3215         if (!in)
3216                 return -ENOMEM;
3217
3218         for (ix = 0; ix < nch; ix++) {
3219                 memset(in, 0, inlen);
3220                 tir = &priv->direct_tir[ix];
3221                 tirc = MLX5_ADDR_OF(create_tir_in, in, ctx);
3222                 mlx5e_build_direct_tir_ctx(priv, priv->direct_tir[ix].rqt.rqtn, tirc);
3223                 err = mlx5e_create_tir(priv->mdev, tir, in, inlen);
3224                 if (err)
3225                         goto err_destroy_ch_tirs;
3226         }
3227
3228         kvfree(in);
3229
3230         return 0;
3231
3232 err_destroy_ch_tirs:
3233         mlx5_core_warn(priv->mdev, "create direct tirs failed, %d\n", err);
3234         for (ix--; ix >= 0; ix--)
3235                 mlx5e_destroy_tir(priv->mdev, &priv->direct_tir[ix]);
3236
3237         kvfree(in);
3238
3239         return err;
3240 }
3241
3242 void mlx5e_destroy_indirect_tirs(struct mlx5e_priv *priv)
3243 {
3244         int i;
3245
3246         for (i = 0; i < MLX5E_NUM_INDIR_TIRS; i++)
3247                 mlx5e_destroy_tir(priv->mdev, &priv->indir_tir[i]);
3248
3249         if (!mlx5e_tunnel_inner_ft_supported(priv->mdev))
3250                 return;
3251
3252         for (i = 0; i < MLX5E_NUM_INDIR_TIRS; i++)
3253                 mlx5e_destroy_tir(priv->mdev, &priv->inner_indir_tir[i]);
3254 }
3255
3256 void mlx5e_destroy_direct_tirs(struct mlx5e_priv *priv)
3257 {
3258         int nch = priv->profile->max_nch(priv->mdev);
3259         int i;
3260
3261         for (i = 0; i < nch; i++)
3262                 mlx5e_destroy_tir(priv->mdev, &priv->direct_tir[i]);
3263 }
3264
3265 static int mlx5e_modify_channels_scatter_fcs(struct mlx5e_channels *chs, bool enable)
3266 {
3267         int err = 0;
3268         int i;
3269
3270         for (i = 0; i < chs->num; i++) {
3271                 err = mlx5e_modify_rq_scatter_fcs(&chs->c[i]->rq, enable);
3272                 if (err)
3273                         return err;
3274         }
3275
3276         return 0;
3277 }
3278
3279 static int mlx5e_modify_channels_vsd(struct mlx5e_channels *chs, bool vsd)
3280 {
3281         int err = 0;
3282         int i;
3283
3284         for (i = 0; i < chs->num; i++) {
3285                 err = mlx5e_modify_rq_vsd(&chs->c[i]->rq, vsd);
3286                 if (err)
3287                         return err;
3288         }
3289
3290         return 0;
3291 }
3292
3293 static int mlx5e_setup_tc_mqprio(struct net_device *netdev,
3294                                  struct tc_mqprio_qopt *mqprio)
3295 {
3296         struct mlx5e_priv *priv = netdev_priv(netdev);
3297         struct mlx5e_channels new_channels = {};
3298         u8 tc = mqprio->num_tc;
3299         int err = 0;
3300
3301         mqprio->hw = TC_MQPRIO_HW_OFFLOAD_TCS;
3302
3303         if (tc && tc != MLX5E_MAX_NUM_TC)
3304                 return -EINVAL;
3305
3306         mutex_lock(&priv->state_lock);
3307
3308         new_channels.params = priv->channels.params;
3309         new_channels.params.num_tc = tc ? tc : 1;
3310
3311         if (!test_bit(MLX5E_STATE_OPENED, &priv->state)) {
3312                 priv->channels.params = new_channels.params;
3313                 goto out;
3314         }
3315
3316         err = mlx5e_open_channels(priv, &new_channels);
3317         if (err)
3318                 goto out;
3319
3320         priv->max_opened_tc = max_t(u8, priv->max_opened_tc,
3321                                     new_channels.params.num_tc);
3322         mlx5e_switch_priv_channels(priv, &new_channels, NULL);
3323 out:
3324         mutex_unlock(&priv->state_lock);
3325         return err;
3326 }
3327
3328 #ifdef CONFIG_MLX5_ESWITCH
3329 static int mlx5e_setup_tc_cls_flower(struct mlx5e_priv *priv,
3330                                      struct tc_cls_flower_offload *cls_flower,
3331                                      int flags)
3332 {
3333         switch (cls_flower->command) {
3334         case TC_CLSFLOWER_REPLACE:
3335                 return mlx5e_configure_flower(priv, cls_flower, flags);
3336         case TC_CLSFLOWER_DESTROY:
3337                 return mlx5e_delete_flower(priv, cls_flower, flags);
3338         case TC_CLSFLOWER_STATS:
3339                 return mlx5e_stats_flower(priv, cls_flower, flags);
3340         default:
3341                 return -EOPNOTSUPP;
3342         }
3343 }
3344
3345 static int mlx5e_setup_tc_block_cb(enum tc_setup_type type, void *type_data,
3346                                    void *cb_priv)
3347 {
3348         struct mlx5e_priv *priv = cb_priv;
3349
3350         if (!tc_cls_can_offload_and_chain0(priv->netdev, type_data))
3351                 return -EOPNOTSUPP;
3352
3353         switch (type) {
3354         case TC_SETUP_CLSFLOWER:
3355                 return mlx5e_setup_tc_cls_flower(priv, type_data, MLX5E_TC_INGRESS);
3356         default:
3357                 return -EOPNOTSUPP;
3358         }
3359 }
3360
3361 static int mlx5e_setup_tc_block(struct net_device *dev,
3362                                 struct tc_block_offload *f)
3363 {
3364         struct mlx5e_priv *priv = netdev_priv(dev);
3365
3366         if (f->binder_type != TCF_BLOCK_BINDER_TYPE_CLSACT_INGRESS)
3367                 return -EOPNOTSUPP;
3368
3369         switch (f->command) {
3370         case TC_BLOCK_BIND:
3371                 return tcf_block_cb_register(f->block, mlx5e_setup_tc_block_cb,
3372                                              priv, priv);
3373         case TC_BLOCK_UNBIND:
3374                 tcf_block_cb_unregister(f->block, mlx5e_setup_tc_block_cb,
3375                                         priv);
3376                 return 0;
3377         default:
3378                 return -EOPNOTSUPP;
3379         }
3380 }
3381 #endif
3382
3383 static int mlx5e_setup_tc(struct net_device *dev, enum tc_setup_type type,
3384                           void *type_data)
3385 {
3386         switch (type) {
3387 #ifdef CONFIG_MLX5_ESWITCH
3388         case TC_SETUP_BLOCK:
3389                 return mlx5e_setup_tc_block(dev, type_data);
3390 #endif
3391         case TC_SETUP_QDISC_MQPRIO:
3392                 return mlx5e_setup_tc_mqprio(dev, type_data);
3393         default:
3394                 return -EOPNOTSUPP;
3395         }
3396 }
3397
3398 static void
3399 mlx5e_get_stats(struct net_device *dev, struct rtnl_link_stats64 *stats)
3400 {
3401         struct mlx5e_priv *priv = netdev_priv(dev);
3402         struct mlx5e_sw_stats *sstats = &priv->stats.sw;
3403         struct mlx5e_vport_stats *vstats = &priv->stats.vport;
3404         struct mlx5e_pport_stats *pstats = &priv->stats.pport;
3405
3406         if (mlx5e_is_uplink_rep(priv)) {
3407                 stats->rx_packets = PPORT_802_3_GET(pstats, a_frames_received_ok);
3408                 stats->rx_bytes   = PPORT_802_3_GET(pstats, a_octets_received_ok);
3409                 stats->tx_packets = PPORT_802_3_GET(pstats, a_frames_transmitted_ok);
3410                 stats->tx_bytes   = PPORT_802_3_GET(pstats, a_octets_transmitted_ok);
3411         } else {
3412                 mlx5e_grp_sw_update_stats(priv);
3413                 stats->rx_packets = sstats->rx_packets;
3414                 stats->rx_bytes   = sstats->rx_bytes;
3415                 stats->tx_packets = sstats->tx_packets;
3416                 stats->tx_bytes   = sstats->tx_bytes;
3417                 stats->tx_dropped = sstats->tx_queue_dropped;
3418         }
3419
3420         stats->rx_dropped = priv->stats.qcnt.rx_out_of_buffer;
3421
3422         stats->rx_length_errors =
3423                 PPORT_802_3_GET(pstats, a_in_range_length_errors) +
3424                 PPORT_802_3_GET(pstats, a_out_of_range_length_field) +
3425                 PPORT_802_3_GET(pstats, a_frame_too_long_errors);
3426         stats->rx_crc_errors =
3427                 PPORT_802_3_GET(pstats, a_frame_check_sequence_errors);
3428         stats->rx_frame_errors = PPORT_802_3_GET(pstats, a_alignment_errors);
3429         stats->tx_aborted_errors = PPORT_2863_GET(pstats, if_out_discards);
3430         stats->rx_errors = stats->rx_length_errors + stats->rx_crc_errors +
3431                            stats->rx_frame_errors;
3432         stats->tx_errors = stats->tx_aborted_errors + stats->tx_carrier_errors;
3433
3434         /* vport multicast also counts packets that are dropped due to steering
3435          * or rx out of buffer
3436          */
3437         stats->multicast =
3438                 VPORT_COUNTER_GET(vstats, received_eth_multicast.packets);
3439 }
3440
3441 static void mlx5e_set_rx_mode(struct net_device *dev)
3442 {
3443         struct mlx5e_priv *priv = netdev_priv(dev);
3444
3445         queue_work(priv->wq, &priv->set_rx_mode_work);
3446 }
3447
3448 static int mlx5e_set_mac(struct net_device *netdev, void *addr)
3449 {
3450         struct mlx5e_priv *priv = netdev_priv(netdev);
3451         struct sockaddr *saddr = addr;
3452
3453         if (!is_valid_ether_addr(saddr->sa_data))
3454                 return -EADDRNOTAVAIL;
3455
3456         netif_addr_lock_bh(netdev);
3457         ether_addr_copy(netdev->dev_addr, saddr->sa_data);
3458         netif_addr_unlock_bh(netdev);
3459
3460         queue_work(priv->wq, &priv->set_rx_mode_work);
3461
3462         return 0;
3463 }
3464
3465 #define MLX5E_SET_FEATURE(features, feature, enable)    \
3466         do {                                            \
3467                 if (enable)                             \
3468                         *features |= feature;           \
3469                 else                                    \
3470                         *features &= ~feature;          \
3471         } while (0)
3472
3473 typedef int (*mlx5e_feature_handler)(struct net_device *netdev, bool enable);
3474
3475 static int set_feature_lro(struct net_device *netdev, bool enable)
3476 {
3477         struct mlx5e_priv *priv = netdev_priv(netdev);
3478         struct mlx5_core_dev *mdev = priv->mdev;
3479         struct mlx5e_channels new_channels = {};
3480         struct mlx5e_params *old_params;
3481         int err = 0;
3482         bool reset;
3483
3484         mutex_lock(&priv->state_lock);
3485
3486         old_params = &priv->channels.params;
3487         if (enable && !MLX5E_GET_PFLAG(old_params, MLX5E_PFLAG_RX_STRIDING_RQ)) {
3488                 netdev_warn(netdev, "can't set LRO with legacy RQ\n");
3489                 err = -EINVAL;
3490                 goto out;
3491         }
3492
3493         reset = test_bit(MLX5E_STATE_OPENED, &priv->state);
3494
3495         new_channels.params = *old_params;
3496         new_channels.params.lro_en = enable;
3497
3498         if (old_params->rq_wq_type != MLX5_WQ_TYPE_CYCLIC) {
3499                 if (mlx5e_rx_mpwqe_is_linear_skb(mdev, old_params) ==
3500                     mlx5e_rx_mpwqe_is_linear_skb(mdev, &new_channels.params))
3501                         reset = false;
3502         }
3503
3504         if (!reset) {
3505                 *old_params = new_channels.params;
3506                 err = mlx5e_modify_tirs_lro(priv);
3507                 goto out;
3508         }
3509
3510         err = mlx5e_open_channels(priv, &new_channels);
3511         if (err)
3512                 goto out;
3513
3514         mlx5e_switch_priv_channels(priv, &new_channels, mlx5e_modify_tirs_lro);
3515 out:
3516         mutex_unlock(&priv->state_lock);
3517         return err;
3518 }
3519
3520 static int set_feature_cvlan_filter(struct net_device *netdev, bool enable)
3521 {
3522         struct mlx5e_priv *priv = netdev_priv(netdev);
3523
3524         if (enable)
3525                 mlx5e_enable_cvlan_filter(priv);
3526         else
3527                 mlx5e_disable_cvlan_filter(priv);
3528
3529         return 0;
3530 }
3531
3532 static int set_feature_tc_num_filters(struct net_device *netdev, bool enable)
3533 {
3534         struct mlx5e_priv *priv = netdev_priv(netdev);
3535
3536         if (!enable && mlx5e_tc_num_filters(priv)) {
3537                 netdev_err(netdev,
3538                            "Active offloaded tc filters, can't turn hw_tc_offload off\n");
3539                 return -EINVAL;
3540         }
3541
3542         return 0;
3543 }
3544
3545 static int set_feature_rx_all(struct net_device *netdev, bool enable)
3546 {
3547         struct mlx5e_priv *priv = netdev_priv(netdev);
3548         struct mlx5_core_dev *mdev = priv->mdev;
3549
3550         return mlx5_set_port_fcs(mdev, !enable);
3551 }
3552
3553 static int set_feature_rx_fcs(struct net_device *netdev, bool enable)
3554 {
3555         struct mlx5e_priv *priv = netdev_priv(netdev);
3556         int err;
3557
3558         mutex_lock(&priv->state_lock);
3559
3560         priv->channels.params.scatter_fcs_en = enable;
3561         err = mlx5e_modify_channels_scatter_fcs(&priv->channels, enable);
3562         if (err)
3563                 priv->channels.params.scatter_fcs_en = !enable;
3564
3565         mutex_unlock(&priv->state_lock);
3566
3567         return err;
3568 }
3569
3570 static int set_feature_rx_vlan(struct net_device *netdev, bool enable)
3571 {
3572         struct mlx5e_priv *priv = netdev_priv(netdev);
3573         int err = 0;
3574
3575         mutex_lock(&priv->state_lock);
3576
3577         priv->channels.params.vlan_strip_disable = !enable;
3578         if (!test_bit(MLX5E_STATE_OPENED, &priv->state))
3579                 goto unlock;
3580
3581         err = mlx5e_modify_channels_vsd(&priv->channels, !enable);
3582         if (err)
3583                 priv->channels.params.vlan_strip_disable = enable;
3584
3585 unlock:
3586         mutex_unlock(&priv->state_lock);
3587
3588         return err;
3589 }
3590
3591 #ifdef CONFIG_RFS_ACCEL
3592 static int set_feature_arfs(struct net_device *netdev, bool enable)
3593 {
3594         struct mlx5e_priv *priv = netdev_priv(netdev);
3595         int err;
3596
3597         if (enable)
3598                 err = mlx5e_arfs_enable(priv);
3599         else
3600                 err = mlx5e_arfs_disable(priv);
3601
3602         return err;
3603 }
3604 #endif
3605
3606 static int mlx5e_handle_feature(struct net_device *netdev,
3607                                 netdev_features_t *features,
3608                                 netdev_features_t wanted_features,
3609                                 netdev_features_t feature,
3610                                 mlx5e_feature_handler feature_handler)
3611 {
3612         netdev_features_t changes = wanted_features ^ netdev->features;
3613         bool enable = !!(wanted_features & feature);
3614         int err;
3615
3616         if (!(changes & feature))
3617                 return 0;
3618
3619         err = feature_handler(netdev, enable);
3620         if (err) {
3621                 netdev_err(netdev, "%s feature %pNF failed, err %d\n",
3622                            enable ? "Enable" : "Disable", &feature, err);
3623                 return err;
3624         }
3625
3626         MLX5E_SET_FEATURE(features, feature, enable);
3627         return 0;
3628 }
3629
3630 static int mlx5e_set_features(struct net_device *netdev,
3631                               netdev_features_t features)
3632 {
3633         netdev_features_t oper_features = netdev->features;
3634         int err = 0;
3635
3636 #define MLX5E_HANDLE_FEATURE(feature, handler) \
3637         mlx5e_handle_feature(netdev, &oper_features, features, feature, handler)
3638
3639         err |= MLX5E_HANDLE_FEATURE(NETIF_F_LRO, set_feature_lro);
3640         err |= MLX5E_HANDLE_FEATURE(NETIF_F_HW_VLAN_CTAG_FILTER,
3641                                     set_feature_cvlan_filter);
3642         err |= MLX5E_HANDLE_FEATURE(NETIF_F_HW_TC, set_feature_tc_num_filters);
3643         err |= MLX5E_HANDLE_FEATURE(NETIF_F_RXALL, set_feature_rx_all);
3644         err |= MLX5E_HANDLE_FEATURE(NETIF_F_RXFCS, set_feature_rx_fcs);
3645         err |= MLX5E_HANDLE_FEATURE(NETIF_F_HW_VLAN_CTAG_RX, set_feature_rx_vlan);
3646 #ifdef CONFIG_RFS_ACCEL
3647         err |= MLX5E_HANDLE_FEATURE(NETIF_F_NTUPLE, set_feature_arfs);
3648 #endif
3649
3650         if (err) {
3651                 netdev->features = oper_features;
3652                 return -EINVAL;
3653         }
3654
3655         return 0;
3656 }
3657
3658 static netdev_features_t mlx5e_fix_features(struct net_device *netdev,
3659                                             netdev_features_t features)
3660 {
3661         struct mlx5e_priv *priv = netdev_priv(netdev);
3662         struct mlx5e_params *params;
3663
3664         mutex_lock(&priv->state_lock);
3665         params = &priv->channels.params;
3666         if (!bitmap_empty(priv->fs.vlan.active_svlans, VLAN_N_VID)) {
3667                 /* HW strips the outer C-tag header, this is a problem
3668                  * for S-tag traffic.
3669                  */
3670                 features &= ~NETIF_F_HW_VLAN_CTAG_RX;
3671                 if (!params->vlan_strip_disable)
3672                         netdev_warn(netdev, "Dropping C-tag vlan stripping offload due to S-tag vlan\n");
3673         }
3674         if (!MLX5E_GET_PFLAG(params, MLX5E_PFLAG_RX_STRIDING_RQ)) {
3675                 features &= ~NETIF_F_LRO;
3676                 if (params->lro_en)
3677                         netdev_warn(netdev, "Disabling LRO, not supported in legacy RQ\n");
3678         }
3679
3680         mutex_unlock(&priv->state_lock);
3681
3682         return features;
3683 }
3684
3685 int mlx5e_change_mtu(struct net_device *netdev, int new_mtu,
3686                      change_hw_mtu_cb set_mtu_cb)
3687 {
3688         struct mlx5e_priv *priv = netdev_priv(netdev);
3689         struct mlx5e_channels new_channels = {};
3690         struct mlx5e_params *params;
3691         int err = 0;
3692         bool reset;
3693
3694         mutex_lock(&priv->state_lock);
3695
3696         params = &priv->channels.params;
3697
3698         reset = !params->lro_en;
3699         reset = reset && test_bit(MLX5E_STATE_OPENED, &priv->state);
3700
3701         new_channels.params = *params;
3702         new_channels.params.sw_mtu = new_mtu;
3703
3704         if (params->rq_wq_type == MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ) {
3705                 u8 ppw_old = mlx5e_mpwqe_log_pkts_per_wqe(params);
3706                 u8 ppw_new = mlx5e_mpwqe_log_pkts_per_wqe(&new_channels.params);
3707
3708                 reset = reset && (ppw_old != ppw_new);
3709         }
3710
3711         if (!reset) {
3712                 params->sw_mtu = new_mtu;
3713                 set_mtu_cb(priv);
3714                 netdev->mtu = params->sw_mtu;
3715                 goto out;
3716         }
3717
3718         err = mlx5e_open_channels(priv, &new_channels);
3719         if (err)
3720                 goto out;
3721
3722         mlx5e_switch_priv_channels(priv, &new_channels, set_mtu_cb);
3723         netdev->mtu = new_channels.params.sw_mtu;
3724
3725 out:
3726         mutex_unlock(&priv->state_lock);
3727         return err;
3728 }
3729
3730 static int mlx5e_change_nic_mtu(struct net_device *netdev, int new_mtu)
3731 {
3732         return mlx5e_change_mtu(netdev, new_mtu, mlx5e_set_dev_port_mtu);
3733 }
3734
3735 int mlx5e_hwstamp_set(struct mlx5e_priv *priv, struct ifreq *ifr)
3736 {
3737         struct hwtstamp_config config;
3738         int err;
3739
3740         if (!MLX5_CAP_GEN(priv->mdev, device_frequency_khz))
3741                 return -EOPNOTSUPP;
3742
3743         if (copy_from_user(&config, ifr->ifr_data, sizeof(config)))
3744                 return -EFAULT;
3745
3746         /* TX HW timestamp */
3747         switch (config.tx_type) {
3748         case HWTSTAMP_TX_OFF:
3749         case HWTSTAMP_TX_ON:
3750                 break;
3751         default:
3752                 return -ERANGE;
3753         }
3754
3755         mutex_lock(&priv->state_lock);
3756         /* RX HW timestamp */
3757         switch (config.rx_filter) {
3758         case HWTSTAMP_FILTER_NONE:
3759                 /* Reset CQE compression to Admin default */
3760                 mlx5e_modify_rx_cqe_compression_locked(priv, priv->channels.params.rx_cqe_compress_def);
3761                 break;
3762         case HWTSTAMP_FILTER_ALL:
3763         case HWTSTAMP_FILTER_SOME:
3764         case HWTSTAMP_FILTER_PTP_V1_L4_EVENT:
3765         case HWTSTAMP_FILTER_PTP_V1_L4_SYNC:
3766         case HWTSTAMP_FILTER_PTP_V1_L4_DELAY_REQ:
3767         case HWTSTAMP_FILTER_PTP_V2_L4_EVENT:
3768         case HWTSTAMP_FILTER_PTP_V2_L4_SYNC:
3769         case HWTSTAMP_FILTER_PTP_V2_L4_DELAY_REQ:
3770         case HWTSTAMP_FILTER_PTP_V2_L2_EVENT:
3771         case HWTSTAMP_FILTER_PTP_V2_L2_SYNC:
3772         case HWTSTAMP_FILTER_PTP_V2_L2_DELAY_REQ:
3773         case HWTSTAMP_FILTER_PTP_V2_EVENT:
3774         case HWTSTAMP_FILTER_PTP_V2_SYNC:
3775         case HWTSTAMP_FILTER_PTP_V2_DELAY_REQ:
3776         case HWTSTAMP_FILTER_NTP_ALL:
3777                 /* Disable CQE compression */
3778                 netdev_warn(priv->netdev, "Disabling cqe compression");
3779                 err = mlx5e_modify_rx_cqe_compression_locked(priv, false);
3780                 if (err) {
3781                         netdev_err(priv->netdev, "Failed disabling cqe compression err=%d\n", err);
3782                         mutex_unlock(&priv->state_lock);
3783                         return err;
3784                 }
3785                 config.rx_filter = HWTSTAMP_FILTER_ALL;
3786                 break;
3787         default:
3788                 mutex_unlock(&priv->state_lock);
3789                 return -ERANGE;
3790         }
3791
3792         memcpy(&priv->tstamp, &config, sizeof(config));
3793         mutex_unlock(&priv->state_lock);
3794
3795         return copy_to_user(ifr->ifr_data, &config,
3796                             sizeof(config)) ? -EFAULT : 0;
3797 }
3798
3799 int mlx5e_hwstamp_get(struct mlx5e_priv *priv, struct ifreq *ifr)
3800 {
3801         struct hwtstamp_config *cfg = &priv->tstamp;
3802
3803         if (!MLX5_CAP_GEN(priv->mdev, device_frequency_khz))
3804                 return -EOPNOTSUPP;
3805
3806         return copy_to_user(ifr->ifr_data, cfg, sizeof(*cfg)) ? -EFAULT : 0;
3807 }
3808
3809 static int mlx5e_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
3810 {
3811         struct mlx5e_priv *priv = netdev_priv(dev);
3812
3813         switch (cmd) {
3814         case SIOCSHWTSTAMP:
3815                 return mlx5e_hwstamp_set(priv, ifr);
3816         case SIOCGHWTSTAMP:
3817                 return mlx5e_hwstamp_get(priv, ifr);
3818         default:
3819                 return -EOPNOTSUPP;
3820         }
3821 }
3822
3823 #ifdef CONFIG_MLX5_ESWITCH
3824 static int mlx5e_set_vf_mac(struct net_device *dev, int vf, u8 *mac)
3825 {
3826         struct mlx5e_priv *priv = netdev_priv(dev);
3827         struct mlx5_core_dev *mdev = priv->mdev;
3828
3829         return mlx5_eswitch_set_vport_mac(mdev->priv.eswitch, vf + 1, mac);
3830 }
3831
3832 static int mlx5e_set_vf_vlan(struct net_device *dev, int vf, u16 vlan, u8 qos,
3833                              __be16 vlan_proto)
3834 {
3835         struct mlx5e_priv *priv = netdev_priv(dev);
3836         struct mlx5_core_dev *mdev = priv->mdev;
3837
3838         if (vlan_proto != htons(ETH_P_8021Q))
3839                 return -EPROTONOSUPPORT;
3840
3841         return mlx5_eswitch_set_vport_vlan(mdev->priv.eswitch, vf + 1,
3842                                            vlan, qos);
3843 }
3844
3845 static int mlx5e_set_vf_spoofchk(struct net_device *dev, int vf, bool setting)
3846 {
3847         struct mlx5e_priv *priv = netdev_priv(dev);
3848         struct mlx5_core_dev *mdev = priv->mdev;
3849
3850         return mlx5_eswitch_set_vport_spoofchk(mdev->priv.eswitch, vf + 1, setting);
3851 }
3852
3853 static int mlx5e_set_vf_trust(struct net_device *dev, int vf, bool setting)
3854 {
3855         struct mlx5e_priv *priv = netdev_priv(dev);
3856         struct mlx5_core_dev *mdev = priv->mdev;
3857
3858         return mlx5_eswitch_set_vport_trust(mdev->priv.eswitch, vf + 1, setting);
3859 }
3860
3861 static int mlx5e_set_vf_rate(struct net_device *dev, int vf, int min_tx_rate,
3862                              int max_tx_rate)
3863 {
3864         struct mlx5e_priv *priv = netdev_priv(dev);
3865         struct mlx5_core_dev *mdev = priv->mdev;
3866
3867         return mlx5_eswitch_set_vport_rate(mdev->priv.eswitch, vf + 1,
3868                                            max_tx_rate, min_tx_rate);
3869 }
3870
3871 static int mlx5_vport_link2ifla(u8 esw_link)
3872 {
3873         switch (esw_link) {
3874         case MLX5_ESW_VPORT_ADMIN_STATE_DOWN:
3875                 return IFLA_VF_LINK_STATE_DISABLE;
3876         case MLX5_ESW_VPORT_ADMIN_STATE_UP:
3877                 return IFLA_VF_LINK_STATE_ENABLE;
3878         }
3879         return IFLA_VF_LINK_STATE_AUTO;
3880 }
3881
3882 static int mlx5_ifla_link2vport(u8 ifla_link)
3883 {
3884         switch (ifla_link) {
3885         case IFLA_VF_LINK_STATE_DISABLE:
3886                 return MLX5_ESW_VPORT_ADMIN_STATE_DOWN;
3887         case IFLA_VF_LINK_STATE_ENABLE:
3888                 return MLX5_ESW_VPORT_ADMIN_STATE_UP;
3889         }
3890         return MLX5_ESW_VPORT_ADMIN_STATE_AUTO;
3891 }
3892
3893 static int mlx5e_set_vf_link_state(struct net_device *dev, int vf,
3894                                    int link_state)
3895 {
3896         struct mlx5e_priv *priv = netdev_priv(dev);
3897         struct mlx5_core_dev *mdev = priv->mdev;
3898
3899         return mlx5_eswitch_set_vport_state(mdev->priv.eswitch, vf + 1,
3900                                             mlx5_ifla_link2vport(link_state));
3901 }
3902
3903 static int mlx5e_get_vf_config(struct net_device *dev,
3904                                int vf, struct ifla_vf_info *ivi)
3905 {
3906         struct mlx5e_priv *priv = netdev_priv(dev);
3907         struct mlx5_core_dev *mdev = priv->mdev;
3908         int err;
3909
3910         err = mlx5_eswitch_get_vport_config(mdev->priv.eswitch, vf + 1, ivi);
3911         if (err)
3912                 return err;
3913         ivi->linkstate = mlx5_vport_link2ifla(ivi->linkstate);
3914         return 0;
3915 }
3916
3917 static int mlx5e_get_vf_stats(struct net_device *dev,
3918                               int vf, struct ifla_vf_stats *vf_stats)
3919 {
3920         struct mlx5e_priv *priv = netdev_priv(dev);
3921         struct mlx5_core_dev *mdev = priv->mdev;
3922
3923         return mlx5_eswitch_get_vport_stats(mdev->priv.eswitch, vf + 1,
3924                                             vf_stats);
3925 }
3926 #endif
3927
3928 static void mlx5e_add_vxlan_port(struct net_device *netdev,
3929                                  struct udp_tunnel_info *ti)
3930 {
3931         struct mlx5e_priv *priv = netdev_priv(netdev);
3932
3933         if (ti->type != UDP_TUNNEL_TYPE_VXLAN)
3934                 return;
3935
3936         if (!mlx5e_vxlan_allowed(priv->mdev))
3937                 return;
3938
3939         mlx5e_vxlan_queue_work(priv, ti->sa_family, be16_to_cpu(ti->port), 1);
3940 }
3941
3942 static void mlx5e_del_vxlan_port(struct net_device *netdev,
3943                                  struct udp_tunnel_info *ti)
3944 {
3945         struct mlx5e_priv *priv = netdev_priv(netdev);
3946
3947         if (ti->type != UDP_TUNNEL_TYPE_VXLAN)
3948                 return;
3949
3950         if (!mlx5e_vxlan_allowed(priv->mdev))
3951                 return;
3952
3953         mlx5e_vxlan_queue_work(priv, ti->sa_family, be16_to_cpu(ti->port), 0);
3954 }
3955
3956 static netdev_features_t mlx5e_tunnel_features_check(struct mlx5e_priv *priv,
3957                                                      struct sk_buff *skb,
3958                                                      netdev_features_t features)
3959 {
3960         unsigned int offset = 0;
3961         struct udphdr *udph;
3962         u8 proto;
3963         u16 port;
3964
3965         switch (vlan_get_protocol(skb)) {
3966         case htons(ETH_P_IP):
3967                 proto = ip_hdr(skb)->protocol;
3968                 break;
3969         case htons(ETH_P_IPV6):
3970                 proto = ipv6_find_hdr(skb, &offset, -1, NULL, NULL);
3971                 break;
3972         default:
3973                 goto out;
3974         }
3975
3976         switch (proto) {
3977         case IPPROTO_GRE:
3978                 return features;
3979         case IPPROTO_UDP:
3980                 udph = udp_hdr(skb);
3981                 port = be16_to_cpu(udph->dest);
3982
3983                 /* Verify if UDP port is being offloaded by HW */
3984                 if (mlx5e_vxlan_lookup_port(priv, port))
3985                         return features;
3986         }
3987
3988 out:
3989         /* Disable CSUM and GSO if the udp dport is not offloaded by HW */
3990         return features & ~(NETIF_F_CSUM_MASK | NETIF_F_GSO_MASK);
3991 }
3992
3993 static netdev_features_t mlx5e_features_check(struct sk_buff *skb,
3994                                               struct net_device *netdev,
3995                                               netdev_features_t features)
3996 {
3997         struct mlx5e_priv *priv = netdev_priv(netdev);
3998
3999         features = vlan_features_check(skb, features);
4000         features = vxlan_features_check(skb, features);
4001
4002 #ifdef CONFIG_MLX5_EN_IPSEC
4003         if (mlx5e_ipsec_feature_check(skb, netdev, features))
4004                 return features;
4005 #endif
4006
4007         /* Validate if the tunneled packet is being offloaded by HW */
4008         if (skb->encapsulation &&
4009             (features & NETIF_F_CSUM_MASK || features & NETIF_F_GSO_MASK))
4010                 return mlx5e_tunnel_features_check(priv, skb, features);
4011
4012         return features;
4013 }
4014
4015 static bool mlx5e_tx_timeout_eq_recover(struct net_device *dev,
4016                                         struct mlx5e_txqsq *sq)
4017 {
4018         struct mlx5_eq *eq = sq->cq.mcq.eq;
4019         u32 eqe_count;
4020
4021         netdev_err(dev, "EQ 0x%x: Cons = 0x%x, irqn = 0x%x\n",
4022                    eq->eqn, eq->cons_index, eq->irqn);
4023
4024         eqe_count = mlx5_eq_poll_irq_disabled(eq);
4025         if (!eqe_count)
4026                 return false;
4027
4028         netdev_err(dev, "Recover %d eqes on EQ 0x%x\n", eqe_count, eq->eqn);
4029         sq->channel->stats->eq_rearm++;
4030         return true;
4031 }
4032
4033 static void mlx5e_tx_timeout_work(struct work_struct *work)
4034 {
4035         struct mlx5e_priv *priv = container_of(work, struct mlx5e_priv,
4036                                                tx_timeout_work);
4037         struct net_device *dev = priv->netdev;
4038         bool reopen_channels = false;
4039         int i, err;
4040
4041         rtnl_lock();
4042         mutex_lock(&priv->state_lock);
4043
4044         if (!test_bit(MLX5E_STATE_OPENED, &priv->state))
4045                 goto unlock;
4046
4047         for (i = 0; i < priv->channels.num * priv->channels.params.num_tc; i++) {
4048                 struct netdev_queue *dev_queue = netdev_get_tx_queue(dev, i);
4049                 struct mlx5e_txqsq *sq = priv->txq2sq[i];
4050
4051                 if (!netif_xmit_stopped(dev_queue))
4052                         continue;
4053
4054                 netdev_err(dev,
4055                            "TX timeout on queue: %d, SQ: 0x%x, CQ: 0x%x, SQ Cons: 0x%x SQ Prod: 0x%x, usecs since last trans: %u\n",
4056                            i, sq->sqn, sq->cq.mcq.cqn, sq->cc, sq->pc,
4057                            jiffies_to_usecs(jiffies - dev_queue->trans_start));
4058
4059                 /* If we recover a lost interrupt, most likely TX timeout will
4060                  * be resolved, skip reopening channels
4061                  */
4062                 if (!mlx5e_tx_timeout_eq_recover(dev, sq)) {
4063                         clear_bit(MLX5E_SQ_STATE_ENABLED, &sq->state);
4064                         reopen_channels = true;
4065                 }
4066         }
4067
4068         if (!reopen_channels)
4069                 goto unlock;
4070
4071         mlx5e_close_locked(dev);
4072         err = mlx5e_open_locked(dev);
4073         if (err)
4074                 netdev_err(priv->netdev,
4075                            "mlx5e_open_locked failed recovering from a tx_timeout, err(%d).\n",
4076                            err);
4077
4078 unlock:
4079         mutex_unlock(&priv->state_lock);
4080         rtnl_unlock();
4081 }
4082
4083 static void mlx5e_tx_timeout(struct net_device *dev)
4084 {
4085         struct mlx5e_priv *priv = netdev_priv(dev);
4086
4087         netdev_err(dev, "TX timeout detected\n");
4088         queue_work(priv->wq, &priv->tx_timeout_work);
4089 }
4090
4091 static int mlx5e_xdp_set(struct net_device *netdev, struct bpf_prog *prog)
4092 {
4093         struct mlx5e_priv *priv = netdev_priv(netdev);
4094         struct bpf_prog *old_prog;
4095         int err = 0;
4096         bool reset, was_opened;
4097         int i;
4098
4099         mutex_lock(&priv->state_lock);
4100
4101         if ((netdev->features & NETIF_F_LRO) && prog) {
4102                 netdev_warn(netdev, "can't set XDP while LRO is on, disable LRO first\n");
4103                 err = -EINVAL;
4104                 goto unlock;
4105         }
4106
4107         if ((netdev->features & NETIF_F_HW_ESP) && prog) {
4108                 netdev_warn(netdev, "can't set XDP with IPSec offload\n");
4109                 err = -EINVAL;
4110                 goto unlock;
4111         }
4112
4113         was_opened = test_bit(MLX5E_STATE_OPENED, &priv->state);
4114         /* no need for full reset when exchanging programs */
4115         reset = (!priv->channels.params.xdp_prog || !prog);
4116
4117         if (was_opened && reset)
4118                 mlx5e_close_locked(netdev);
4119         if (was_opened && !reset) {
4120                 /* num_channels is invariant here, so we can take the
4121                  * batched reference right upfront.
4122                  */
4123                 prog = bpf_prog_add(prog, priv->channels.num);
4124                 if (IS_ERR(prog)) {
4125                         err = PTR_ERR(prog);
4126                         goto unlock;
4127                 }
4128         }
4129
4130         /* exchange programs, extra prog reference we got from caller
4131          * as long as we don't fail from this point onwards.
4132          */
4133         old_prog = xchg(&priv->channels.params.xdp_prog, prog);
4134         if (old_prog)
4135                 bpf_prog_put(old_prog);
4136
4137         if (reset) /* change RQ type according to priv->xdp_prog */
4138                 mlx5e_set_rq_type(priv->mdev, &priv->channels.params);
4139
4140         if (was_opened && reset)
4141                 mlx5e_open_locked(netdev);
4142
4143         if (!test_bit(MLX5E_STATE_OPENED, &priv->state) || reset)
4144                 goto unlock;
4145
4146         /* exchanging programs w/o reset, we update ref counts on behalf
4147          * of the channels RQs here.
4148          */
4149         for (i = 0; i < priv->channels.num; i++) {
4150                 struct mlx5e_channel *c = priv->channels.c[i];
4151
4152                 clear_bit(MLX5E_RQ_STATE_ENABLED, &c->rq.state);
4153                 napi_synchronize(&c->napi);
4154                 /* prevent mlx5e_poll_rx_cq from accessing rq->xdp_prog */
4155
4156                 old_prog = xchg(&c->rq.xdp_prog, prog);
4157
4158                 set_bit(MLX5E_RQ_STATE_ENABLED, &c->rq.state);
4159                 /* napi_schedule in case we have missed anything */
4160                 napi_schedule(&c->napi);
4161
4162                 if (old_prog)
4163                         bpf_prog_put(old_prog);
4164         }
4165
4166 unlock:
4167         mutex_unlock(&priv->state_lock);
4168         return err;
4169 }
4170
4171 static u32 mlx5e_xdp_query(struct net_device *dev)
4172 {
4173         struct mlx5e_priv *priv = netdev_priv(dev);
4174         const struct bpf_prog *xdp_prog;
4175         u32 prog_id = 0;
4176
4177         mutex_lock(&priv->state_lock);
4178         xdp_prog = priv->channels.params.xdp_prog;
4179         if (xdp_prog)
4180                 prog_id = xdp_prog->aux->id;
4181         mutex_unlock(&priv->state_lock);
4182
4183         return prog_id;
4184 }
4185
4186 static int mlx5e_xdp(struct net_device *dev, struct netdev_bpf *xdp)
4187 {
4188         switch (xdp->command) {
4189         case XDP_SETUP_PROG:
4190                 return mlx5e_xdp_set(dev, xdp->prog);
4191         case XDP_QUERY_PROG:
4192                 xdp->prog_id = mlx5e_xdp_query(dev);
4193                 xdp->prog_attached = !!xdp->prog_id;
4194                 return 0;
4195         default:
4196                 return -EINVAL;
4197         }
4198 }
4199
4200 #ifdef CONFIG_NET_POLL_CONTROLLER
4201 /* Fake "interrupt" called by netpoll (eg netconsole) to send skbs without
4202  * reenabling interrupts.
4203  */
4204 static void mlx5e_netpoll(struct net_device *dev)
4205 {
4206         struct mlx5e_priv *priv = netdev_priv(dev);
4207         struct mlx5e_channels *chs = &priv->channels;
4208
4209         int i;
4210
4211         for (i = 0; i < chs->num; i++)
4212                 napi_schedule(&chs->c[i]->napi);
4213 }
4214 #endif
4215
4216 static const struct net_device_ops mlx5e_netdev_ops = {
4217         .ndo_open                = mlx5e_open,
4218         .ndo_stop                = mlx5e_close,
4219         .ndo_start_xmit          = mlx5e_xmit,
4220         .ndo_setup_tc            = mlx5e_setup_tc,
4221         .ndo_select_queue        = mlx5e_select_queue,
4222         .ndo_get_stats64         = mlx5e_get_stats,
4223         .ndo_set_rx_mode         = mlx5e_set_rx_mode,
4224         .ndo_set_mac_address     = mlx5e_set_mac,
4225         .ndo_vlan_rx_add_vid     = mlx5e_vlan_rx_add_vid,
4226         .ndo_vlan_rx_kill_vid    = mlx5e_vlan_rx_kill_vid,
4227         .ndo_set_features        = mlx5e_set_features,
4228         .ndo_fix_features        = mlx5e_fix_features,
4229         .ndo_change_mtu          = mlx5e_change_nic_mtu,
4230         .ndo_do_ioctl            = mlx5e_ioctl,
4231         .ndo_set_tx_maxrate      = mlx5e_set_tx_maxrate,
4232         .ndo_udp_tunnel_add      = mlx5e_add_vxlan_port,
4233         .ndo_udp_tunnel_del      = mlx5e_del_vxlan_port,
4234         .ndo_features_check      = mlx5e_features_check,
4235 #ifdef CONFIG_RFS_ACCEL
4236         .ndo_rx_flow_steer       = mlx5e_rx_flow_steer,
4237 #endif
4238         .ndo_tx_timeout          = mlx5e_tx_timeout,
4239         .ndo_bpf                 = mlx5e_xdp,
4240 #ifdef CONFIG_NET_POLL_CONTROLLER
4241         .ndo_poll_controller     = mlx5e_netpoll,
4242 #endif
4243 #ifdef CONFIG_MLX5_ESWITCH
4244         /* SRIOV E-Switch NDOs */
4245         .ndo_set_vf_mac          = mlx5e_set_vf_mac,
4246         .ndo_set_vf_vlan         = mlx5e_set_vf_vlan,
4247         .ndo_set_vf_spoofchk     = mlx5e_set_vf_spoofchk,
4248         .ndo_set_vf_trust        = mlx5e_set_vf_trust,
4249         .ndo_set_vf_rate         = mlx5e_set_vf_rate,
4250         .ndo_get_vf_config       = mlx5e_get_vf_config,
4251         .ndo_set_vf_link_state   = mlx5e_set_vf_link_state,
4252         .ndo_get_vf_stats        = mlx5e_get_vf_stats,
4253         .ndo_has_offload_stats   = mlx5e_has_offload_stats,
4254         .ndo_get_offload_stats   = mlx5e_get_offload_stats,
4255 #endif
4256 };
4257
4258 static int mlx5e_check_required_hca_cap(struct mlx5_core_dev *mdev)
4259 {
4260         if (MLX5_CAP_GEN(mdev, port_type) != MLX5_CAP_PORT_TYPE_ETH)
4261                 return -EOPNOTSUPP;
4262         if (!MLX5_CAP_GEN(mdev, eth_net_offloads) ||
4263             !MLX5_CAP_GEN(mdev, nic_flow_table) ||
4264             !MLX5_CAP_ETH(mdev, csum_cap) ||
4265             !MLX5_CAP_ETH(mdev, max_lso_cap) ||
4266             !MLX5_CAP_ETH(mdev, vlan_cap) ||
4267             !MLX5_CAP_ETH(mdev, rss_ind_tbl_cap) ||
4268             MLX5_CAP_FLOWTABLE(mdev,
4269                                flow_table_properties_nic_receive.max_ft_level)
4270                                < 3) {
4271                 mlx5_core_warn(mdev,
4272                                "Not creating net device, some required device capabilities are missing\n");
4273                 return -EOPNOTSUPP;
4274         }
4275         if (!MLX5_CAP_ETH(mdev, self_lb_en_modifiable))
4276                 mlx5_core_warn(mdev, "Self loop back prevention is not supported\n");
4277         if (!MLX5_CAP_GEN(mdev, cq_moderation))
4278                 mlx5_core_warn(mdev, "CQ moderation is not supported\n");
4279
4280         return 0;
4281 }
4282
4283 void mlx5e_build_default_indir_rqt(u32 *indirection_rqt, int len,
4284                                    int num_channels)
4285 {
4286         int i;
4287
4288         for (i = 0; i < len; i++)
4289                 indirection_rqt[i] = i % num_channels;
4290 }
4291
4292 static bool slow_pci_heuristic(struct mlx5_core_dev *mdev)
4293 {
4294         u32 link_speed = 0;
4295         u32 pci_bw = 0;
4296
4297         mlx5e_port_max_linkspeed(mdev, &link_speed);
4298         pci_bw = pcie_bandwidth_available(mdev->pdev, NULL, NULL, NULL);
4299         mlx5_core_dbg_once(mdev, "Max link speed = %d, PCI BW = %d\n",
4300                            link_speed, pci_bw);
4301
4302 #define MLX5E_SLOW_PCI_RATIO (2)
4303
4304         return link_speed && pci_bw &&
4305                 link_speed > MLX5E_SLOW_PCI_RATIO * pci_bw;
4306 }
4307
4308 static struct net_dim_cq_moder mlx5e_get_def_tx_moderation(u8 cq_period_mode)
4309 {
4310         struct net_dim_cq_moder moder;
4311
4312         moder.cq_period_mode = cq_period_mode;
4313         moder.pkts = MLX5E_PARAMS_DEFAULT_TX_CQ_MODERATION_PKTS;
4314         moder.usec = MLX5E_PARAMS_DEFAULT_TX_CQ_MODERATION_USEC;
4315         if (cq_period_mode == MLX5_CQ_PERIOD_MODE_START_FROM_CQE)
4316                 moder.usec = MLX5E_PARAMS_DEFAULT_TX_CQ_MODERATION_USEC_FROM_CQE;
4317
4318         return moder;
4319 }
4320
4321 static struct net_dim_cq_moder mlx5e_get_def_rx_moderation(u8 cq_period_mode)
4322 {
4323         struct net_dim_cq_moder moder;
4324
4325         moder.cq_period_mode = cq_period_mode;
4326         moder.pkts = MLX5E_PARAMS_DEFAULT_RX_CQ_MODERATION_PKTS;
4327         moder.usec = MLX5E_PARAMS_DEFAULT_RX_CQ_MODERATION_USEC;
4328         if (cq_period_mode == MLX5_CQ_PERIOD_MODE_START_FROM_CQE)
4329                 moder.usec = MLX5E_PARAMS_DEFAULT_RX_CQ_MODERATION_USEC_FROM_CQE;
4330
4331         return moder;
4332 }
4333
4334 static u8 mlx5_to_net_dim_cq_period_mode(u8 cq_period_mode)
4335 {
4336         return cq_period_mode == MLX5_CQ_PERIOD_MODE_START_FROM_CQE ?
4337                 NET_DIM_CQ_PERIOD_MODE_START_FROM_CQE :
4338                 NET_DIM_CQ_PERIOD_MODE_START_FROM_EQE;
4339 }
4340
4341 void mlx5e_set_tx_cq_mode_params(struct mlx5e_params *params, u8 cq_period_mode)
4342 {
4343         if (params->tx_dim_enabled) {
4344                 u8 dim_period_mode = mlx5_to_net_dim_cq_period_mode(cq_period_mode);
4345
4346                 params->tx_cq_moderation = net_dim_get_def_tx_moderation(dim_period_mode);
4347         } else {
4348                 params->tx_cq_moderation = mlx5e_get_def_tx_moderation(cq_period_mode);
4349         }
4350
4351         MLX5E_SET_PFLAG(params, MLX5E_PFLAG_TX_CQE_BASED_MODER,
4352                         params->tx_cq_moderation.cq_period_mode ==
4353                                 MLX5_CQ_PERIOD_MODE_START_FROM_CQE);
4354 }
4355
4356 void mlx5e_set_rx_cq_mode_params(struct mlx5e_params *params, u8 cq_period_mode)
4357 {
4358         if (params->rx_dim_enabled) {
4359                 u8 dim_period_mode = mlx5_to_net_dim_cq_period_mode(cq_period_mode);
4360
4361                 params->rx_cq_moderation = net_dim_get_def_rx_moderation(dim_period_mode);
4362         } else {
4363                 params->rx_cq_moderation = mlx5e_get_def_rx_moderation(cq_period_mode);
4364         }
4365
4366         MLX5E_SET_PFLAG(params, MLX5E_PFLAG_RX_CQE_BASED_MODER,
4367                         params->rx_cq_moderation.cq_period_mode ==
4368                                 MLX5_CQ_PERIOD_MODE_START_FROM_CQE);
4369 }
4370
4371 static u32 mlx5e_choose_lro_timeout(struct mlx5_core_dev *mdev, u32 wanted_timeout)
4372 {
4373         int i;
4374
4375         /* The supported periods are organized in ascending order */
4376         for (i = 0; i < MLX5E_LRO_TIMEOUT_ARR_SIZE - 1; i++)
4377                 if (MLX5_CAP_ETH(mdev, lro_timer_supported_periods[i]) >= wanted_timeout)
4378                         break;
4379
4380         return MLX5_CAP_ETH(mdev, lro_timer_supported_periods[i]);
4381 }
4382
4383 void mlx5e_build_nic_params(struct mlx5_core_dev *mdev,
4384                             struct mlx5e_params *params,
4385                             u16 max_channels, u16 mtu)
4386 {
4387         u8 rx_cq_period_mode;
4388
4389         params->sw_mtu = mtu;
4390         params->hard_mtu = MLX5E_ETH_HARD_MTU;
4391         params->num_channels = max_channels;
4392         params->num_tc       = 1;
4393
4394         /* SQ */
4395         params->log_sq_size = is_kdump_kernel() ?
4396                 MLX5E_PARAMS_MINIMUM_LOG_SQ_SIZE :
4397                 MLX5E_PARAMS_DEFAULT_LOG_SQ_SIZE;
4398
4399         /* set CQE compression */
4400         params->rx_cqe_compress_def = false;
4401         if (MLX5_CAP_GEN(mdev, cqe_compression) &&
4402             MLX5_CAP_GEN(mdev, vport_group_manager))
4403                 params->rx_cqe_compress_def = slow_pci_heuristic(mdev);
4404
4405         MLX5E_SET_PFLAG(params, MLX5E_PFLAG_RX_CQE_COMPRESS, params->rx_cqe_compress_def);
4406
4407         /* RQ */
4408         /* Prefer Striding RQ, unless any of the following holds:
4409          * - Striding RQ configuration is not possible/supported.
4410          * - Slow PCI heuristic.
4411          * - Legacy RQ would use linear SKB while Striding RQ would use non-linear.
4412          */
4413         if (!slow_pci_heuristic(mdev) &&
4414             mlx5e_striding_rq_possible(mdev, params) &&
4415             (mlx5e_rx_mpwqe_is_linear_skb(mdev, params) ||
4416              !mlx5e_rx_is_linear_skb(mdev, params)))
4417                 MLX5E_SET_PFLAG(params, MLX5E_PFLAG_RX_STRIDING_RQ, true);
4418         mlx5e_set_rq_type(mdev, params);
4419         mlx5e_init_rq_type_params(mdev, params);
4420
4421         /* HW LRO */
4422
4423         /* TODO: && MLX5_CAP_ETH(mdev, lro_cap) */
4424         if (params->rq_wq_type == MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ)
4425                 if (!mlx5e_rx_mpwqe_is_linear_skb(mdev, params))
4426                         params->lro_en = !slow_pci_heuristic(mdev);
4427         params->lro_timeout = mlx5e_choose_lro_timeout(mdev, MLX5E_DEFAULT_LRO_TIMEOUT);
4428
4429         /* CQ moderation params */
4430         rx_cq_period_mode = MLX5_CAP_GEN(mdev, cq_period_start_from_cqe) ?
4431                         MLX5_CQ_PERIOD_MODE_START_FROM_CQE :
4432                         MLX5_CQ_PERIOD_MODE_START_FROM_EQE;
4433         params->rx_dim_enabled = MLX5_CAP_GEN(mdev, cq_moderation);
4434         params->tx_dim_enabled = MLX5_CAP_GEN(mdev, cq_moderation);
4435         mlx5e_set_rx_cq_mode_params(params, rx_cq_period_mode);
4436         mlx5e_set_tx_cq_mode_params(params, MLX5_CQ_PERIOD_MODE_START_FROM_EQE);
4437
4438         /* TX inline */
4439         params->tx_min_inline_mode = mlx5e_params_calculate_tx_min_inline(mdev);
4440
4441         /* RSS */
4442         params->rss_hfunc = ETH_RSS_HASH_XOR;
4443         netdev_rss_key_fill(params->toeplitz_hash_key, sizeof(params->toeplitz_hash_key));
4444         mlx5e_build_default_indir_rqt(params->indirection_rqt,
4445                                       MLX5E_INDIR_RQT_SIZE, max_channels);
4446 }
4447
4448 static void mlx5e_build_nic_netdev_priv(struct mlx5_core_dev *mdev,
4449                                         struct net_device *netdev,
4450                                         const struct mlx5e_profile *profile,
4451                                         void *ppriv)
4452 {
4453         struct mlx5e_priv *priv = netdev_priv(netdev);
4454
4455         priv->mdev        = mdev;
4456         priv->netdev      = netdev;
4457         priv->profile     = profile;
4458         priv->ppriv       = ppriv;
4459         priv->msglevel    = MLX5E_MSG_LEVEL;
4460         priv->max_opened_tc = 1;
4461
4462         mlx5e_build_nic_params(mdev, &priv->channels.params,
4463                                profile->max_nch(mdev), netdev->mtu);
4464
4465         mutex_init(&priv->state_lock);
4466
4467         INIT_WORK(&priv->update_carrier_work, mlx5e_update_carrier_work);
4468         INIT_WORK(&priv->set_rx_mode_work, mlx5e_set_rx_mode_work);
4469         INIT_WORK(&priv->tx_timeout_work, mlx5e_tx_timeout_work);
4470         INIT_DELAYED_WORK(&priv->update_stats_work, mlx5e_update_stats_work);
4471
4472         mlx5e_timestamp_init(priv);
4473 }
4474
4475 static void mlx5e_set_netdev_dev_addr(struct net_device *netdev)
4476 {
4477         struct mlx5e_priv *priv = netdev_priv(netdev);
4478
4479         mlx5_query_nic_vport_mac_address(priv->mdev, 0, netdev->dev_addr);
4480         if (is_zero_ether_addr(netdev->dev_addr) &&
4481             !MLX5_CAP_GEN(priv->mdev, vport_group_manager)) {
4482                 eth_hw_addr_random(netdev);
4483                 mlx5_core_info(priv->mdev, "Assigned random MAC address %pM\n", netdev->dev_addr);
4484         }
4485 }
4486
4487 #if IS_ENABLED(CONFIG_MLX5_ESWITCH)
4488 static const struct switchdev_ops mlx5e_switchdev_ops = {
4489         .switchdev_port_attr_get        = mlx5e_attr_get,
4490 };
4491 #endif
4492
4493 static void mlx5e_build_nic_netdev(struct net_device *netdev)
4494 {
4495         struct mlx5e_priv *priv = netdev_priv(netdev);
4496         struct mlx5_core_dev *mdev = priv->mdev;
4497         bool fcs_supported;
4498         bool fcs_enabled;
4499
4500         SET_NETDEV_DEV(netdev, &mdev->pdev->dev);
4501
4502         netdev->netdev_ops = &mlx5e_netdev_ops;
4503
4504 #ifdef CONFIG_MLX5_CORE_EN_DCB
4505         if (MLX5_CAP_GEN(mdev, vport_group_manager) && MLX5_CAP_GEN(mdev, qos))
4506                 netdev->dcbnl_ops = &mlx5e_dcbnl_ops;
4507 #endif
4508
4509         netdev->watchdog_timeo    = 15 * HZ;
4510
4511         netdev->ethtool_ops       = &mlx5e_ethtool_ops;
4512
4513         netdev->vlan_features    |= NETIF_F_SG;
4514         netdev->vlan_features    |= NETIF_F_IP_CSUM;
4515         netdev->vlan_features    |= NETIF_F_IPV6_CSUM;
4516         netdev->vlan_features    |= NETIF_F_GRO;
4517         netdev->vlan_features    |= NETIF_F_TSO;
4518         netdev->vlan_features    |= NETIF_F_TSO6;
4519         netdev->vlan_features    |= NETIF_F_RXCSUM;
4520         netdev->vlan_features    |= NETIF_F_RXHASH;
4521
4522         netdev->hw_enc_features  |= NETIF_F_HW_VLAN_CTAG_TX;
4523         netdev->hw_enc_features  |= NETIF_F_HW_VLAN_CTAG_RX;
4524
4525         if (!!MLX5_CAP_ETH(mdev, lro_cap) &&
4526             mlx5e_check_fragmented_striding_rq_cap(mdev))
4527                 netdev->vlan_features    |= NETIF_F_LRO;
4528
4529         netdev->hw_features       = netdev->vlan_features;
4530         netdev->hw_features      |= NETIF_F_HW_VLAN_CTAG_TX;
4531         netdev->hw_features      |= NETIF_F_HW_VLAN_CTAG_RX;
4532         netdev->hw_features      |= NETIF_F_HW_VLAN_CTAG_FILTER;
4533         netdev->hw_features      |= NETIF_F_HW_VLAN_STAG_TX;
4534
4535         if (mlx5e_vxlan_allowed(mdev) || MLX5_CAP_ETH(mdev, tunnel_stateless_gre)) {
4536                 netdev->hw_features     |= NETIF_F_GSO_PARTIAL;
4537                 netdev->hw_enc_features |= NETIF_F_IP_CSUM;
4538                 netdev->hw_enc_features |= NETIF_F_IPV6_CSUM;
4539                 netdev->hw_enc_features |= NETIF_F_TSO;
4540                 netdev->hw_enc_features |= NETIF_F_TSO6;
4541                 netdev->hw_enc_features |= NETIF_F_GSO_PARTIAL;
4542         }
4543
4544         if (mlx5e_vxlan_allowed(mdev)) {
4545                 netdev->hw_features     |= NETIF_F_GSO_UDP_TUNNEL |
4546                                            NETIF_F_GSO_UDP_TUNNEL_CSUM;
4547                 netdev->hw_enc_features |= NETIF_F_GSO_UDP_TUNNEL |
4548                                            NETIF_F_GSO_UDP_TUNNEL_CSUM;
4549                 netdev->gso_partial_features = NETIF_F_GSO_UDP_TUNNEL_CSUM;
4550         }
4551
4552         if (MLX5_CAP_ETH(mdev, tunnel_stateless_gre)) {
4553                 netdev->hw_features     |= NETIF_F_GSO_GRE |
4554                                            NETIF_F_GSO_GRE_CSUM;
4555                 netdev->hw_enc_features |= NETIF_F_GSO_GRE |
4556                                            NETIF_F_GSO_GRE_CSUM;
4557                 netdev->gso_partial_features |= NETIF_F_GSO_GRE |
4558                                                 NETIF_F_GSO_GRE_CSUM;
4559         }
4560
4561         mlx5_query_port_fcs(mdev, &fcs_supported, &fcs_enabled);
4562
4563         if (fcs_supported)
4564                 netdev->hw_features |= NETIF_F_RXALL;
4565
4566         if (MLX5_CAP_ETH(mdev, scatter_fcs))
4567                 netdev->hw_features |= NETIF_F_RXFCS;
4568
4569         netdev->features          = netdev->hw_features;
4570         if (!priv->channels.params.lro_en)
4571                 netdev->features  &= ~NETIF_F_LRO;
4572
4573         if (fcs_enabled)
4574                 netdev->features  &= ~NETIF_F_RXALL;
4575
4576         if (!priv->channels.params.scatter_fcs_en)
4577                 netdev->features  &= ~NETIF_F_RXFCS;
4578
4579 #define FT_CAP(f) MLX5_CAP_FLOWTABLE(mdev, flow_table_properties_nic_receive.f)
4580         if (FT_CAP(flow_modify_en) &&
4581             FT_CAP(modify_root) &&
4582             FT_CAP(identified_miss_table_mode) &&
4583             FT_CAP(flow_table_modify)) {
4584                 netdev->hw_features      |= NETIF_F_HW_TC;
4585 #ifdef CONFIG_RFS_ACCEL
4586                 netdev->hw_features      |= NETIF_F_NTUPLE;
4587 #endif
4588         }
4589
4590         netdev->features         |= NETIF_F_HIGHDMA;
4591         netdev->features         |= NETIF_F_HW_VLAN_STAG_FILTER;
4592
4593         netdev->priv_flags       |= IFF_UNICAST_FLT;
4594
4595         mlx5e_set_netdev_dev_addr(netdev);
4596
4597 #if IS_ENABLED(CONFIG_MLX5_ESWITCH)
4598         if (MLX5_VPORT_MANAGER(mdev))
4599                 netdev->switchdev_ops = &mlx5e_switchdev_ops;
4600 #endif
4601
4602         mlx5e_ipsec_build_netdev(priv);
4603         mlx5e_tls_build_netdev(priv);
4604 }
4605
4606 static void mlx5e_create_q_counters(struct mlx5e_priv *priv)
4607 {
4608         struct mlx5_core_dev *mdev = priv->mdev;
4609         int err;
4610
4611         err = mlx5_core_alloc_q_counter(mdev, &priv->q_counter);
4612         if (err) {
4613                 mlx5_core_warn(mdev, "alloc queue counter failed, %d\n", err);
4614                 priv->q_counter = 0;
4615         }
4616
4617         err = mlx5_core_alloc_q_counter(mdev, &priv->drop_rq_q_counter);
4618         if (err) {
4619                 mlx5_core_warn(mdev, "alloc drop RQ counter failed, %d\n", err);
4620                 priv->drop_rq_q_counter = 0;
4621         }
4622 }
4623
4624 static void mlx5e_destroy_q_counters(struct mlx5e_priv *priv)
4625 {
4626         if (priv->q_counter)
4627                 mlx5_core_dealloc_q_counter(priv->mdev, priv->q_counter);
4628
4629         if (priv->drop_rq_q_counter)
4630                 mlx5_core_dealloc_q_counter(priv->mdev, priv->drop_rq_q_counter);
4631 }
4632
4633 static void mlx5e_nic_init(struct mlx5_core_dev *mdev,
4634                            struct net_device *netdev,
4635                            const struct mlx5e_profile *profile,
4636                            void *ppriv)
4637 {
4638         struct mlx5e_priv *priv = netdev_priv(netdev);
4639         int err;
4640
4641         mlx5e_build_nic_netdev_priv(mdev, netdev, profile, ppriv);
4642         err = mlx5e_ipsec_init(priv);
4643         if (err)
4644                 mlx5_core_err(mdev, "IPSec initialization failed, %d\n", err);
4645         err = mlx5e_tls_init(priv);
4646         if (err)
4647                 mlx5_core_err(mdev, "TLS initialization failed, %d\n", err);
4648         mlx5e_build_nic_netdev(netdev);
4649         mlx5e_build_tc2txq_maps(priv);
4650         mlx5e_vxlan_init(priv);
4651 }
4652
4653 static void mlx5e_nic_cleanup(struct mlx5e_priv *priv)
4654 {
4655         mlx5e_tls_cleanup(priv);
4656         mlx5e_ipsec_cleanup(priv);
4657         mlx5e_vxlan_cleanup(priv);
4658 }
4659
4660 static int mlx5e_init_nic_rx(struct mlx5e_priv *priv)
4661 {
4662         struct mlx5_core_dev *mdev = priv->mdev;
4663         int err;
4664
4665         err = mlx5e_create_indirect_rqt(priv);
4666         if (err)
4667                 return err;
4668
4669         err = mlx5e_create_direct_rqts(priv);
4670         if (err)
4671                 goto err_destroy_indirect_rqts;
4672
4673         err = mlx5e_create_indirect_tirs(priv);
4674         if (err)
4675                 goto err_destroy_direct_rqts;
4676
4677         err = mlx5e_create_direct_tirs(priv);
4678         if (err)
4679                 goto err_destroy_indirect_tirs;
4680
4681         err = mlx5e_create_flow_steering(priv);
4682         if (err) {
4683                 mlx5_core_warn(mdev, "create flow steering failed, %d\n", err);
4684                 goto err_destroy_direct_tirs;
4685         }
4686
4687         err = mlx5e_tc_nic_init(priv);
4688         if (err)
4689                 goto err_destroy_flow_steering;
4690
4691         return 0;
4692
4693 err_destroy_flow_steering:
4694         mlx5e_destroy_flow_steering(priv);
4695 err_destroy_direct_tirs:
4696         mlx5e_destroy_direct_tirs(priv);
4697 err_destroy_indirect_tirs:
4698         mlx5e_destroy_indirect_tirs(priv);
4699 err_destroy_direct_rqts:
4700         mlx5e_destroy_direct_rqts(priv);
4701 err_destroy_indirect_rqts:
4702         mlx5e_destroy_rqt(priv, &priv->indir_rqt);
4703         return err;
4704 }
4705
4706 static void mlx5e_cleanup_nic_rx(struct mlx5e_priv *priv)
4707 {
4708         mlx5e_tc_nic_cleanup(priv);
4709         mlx5e_destroy_flow_steering(priv);
4710         mlx5e_destroy_direct_tirs(priv);
4711         mlx5e_destroy_indirect_tirs(priv);
4712         mlx5e_destroy_direct_rqts(priv);
4713         mlx5e_destroy_rqt(priv, &priv->indir_rqt);
4714 }
4715
4716 static int mlx5e_init_nic_tx(struct mlx5e_priv *priv)
4717 {
4718         int err;
4719
4720         err = mlx5e_create_tises(priv);
4721         if (err) {
4722                 mlx5_core_warn(priv->mdev, "create tises failed, %d\n", err);
4723                 return err;
4724         }
4725
4726 #ifdef CONFIG_MLX5_CORE_EN_DCB
4727         mlx5e_dcbnl_initialize(priv);
4728 #endif
4729         return 0;
4730 }
4731
4732 static void mlx5e_nic_enable(struct mlx5e_priv *priv)
4733 {
4734         struct net_device *netdev = priv->netdev;
4735         struct mlx5_core_dev *mdev = priv->mdev;
4736         u16 max_mtu;
4737
4738         mlx5e_init_l2_addr(priv);
4739
4740         /* Marking the link as currently not needed by the Driver */
4741         if (!netif_running(netdev))
4742                 mlx5_set_port_admin_status(mdev, MLX5_PORT_DOWN);
4743
4744         /* MTU range: 68 - hw-specific max */
4745         netdev->min_mtu = ETH_MIN_MTU;
4746         mlx5_query_port_max_mtu(priv->mdev, &max_mtu, 1);
4747         netdev->max_mtu = MLX5E_HW2SW_MTU(&priv->channels.params, max_mtu);
4748         mlx5e_set_dev_port_mtu(priv);
4749
4750         mlx5_lag_add(mdev, netdev);
4751
4752         mlx5e_enable_async_events(priv);
4753
4754         if (MLX5_VPORT_MANAGER(priv->mdev))
4755                 mlx5e_register_vport_reps(priv);
4756
4757         if (netdev->reg_state != NETREG_REGISTERED)
4758                 return;
4759 #ifdef CONFIG_MLX5_CORE_EN_DCB
4760         mlx5e_dcbnl_init_app(priv);
4761 #endif
4762
4763         queue_work(priv->wq, &priv->set_rx_mode_work);
4764
4765         rtnl_lock();
4766         if (netif_running(netdev))
4767                 mlx5e_open(netdev);
4768         netif_device_attach(netdev);
4769         rtnl_unlock();
4770 }
4771
4772 static void mlx5e_nic_disable(struct mlx5e_priv *priv)
4773 {
4774         struct mlx5_core_dev *mdev = priv->mdev;
4775
4776 #ifdef CONFIG_MLX5_CORE_EN_DCB
4777         if (priv->netdev->reg_state == NETREG_REGISTERED)
4778                 mlx5e_dcbnl_delete_app(priv);
4779 #endif
4780
4781         rtnl_lock();
4782         if (netif_running(priv->netdev))
4783                 mlx5e_close(priv->netdev);
4784         netif_device_detach(priv->netdev);
4785         rtnl_unlock();
4786
4787         queue_work(priv->wq, &priv->set_rx_mode_work);
4788
4789         if (MLX5_VPORT_MANAGER(priv->mdev))
4790                 mlx5e_unregister_vport_reps(priv);
4791
4792         mlx5e_disable_async_events(priv);
4793         mlx5_lag_remove(mdev);
4794 }
4795
4796 static const struct mlx5e_profile mlx5e_nic_profile = {
4797         .init              = mlx5e_nic_init,
4798         .cleanup           = mlx5e_nic_cleanup,
4799         .init_rx           = mlx5e_init_nic_rx,
4800         .cleanup_rx        = mlx5e_cleanup_nic_rx,
4801         .init_tx           = mlx5e_init_nic_tx,
4802         .cleanup_tx        = mlx5e_cleanup_nic_tx,
4803         .enable            = mlx5e_nic_enable,
4804         .disable           = mlx5e_nic_disable,
4805         .update_stats      = mlx5e_update_ndo_stats,
4806         .max_nch           = mlx5e_get_max_num_channels,
4807         .update_carrier    = mlx5e_update_carrier,
4808         .rx_handlers.handle_rx_cqe       = mlx5e_handle_rx_cqe,
4809         .rx_handlers.handle_rx_cqe_mpwqe = mlx5e_handle_rx_cqe_mpwrq,
4810         .max_tc            = MLX5E_MAX_NUM_TC,
4811 };
4812
4813 /* mlx5e generic netdev management API (move to en_common.c) */
4814
4815 struct net_device *mlx5e_create_netdev(struct mlx5_core_dev *mdev,
4816                                        const struct mlx5e_profile *profile,
4817                                        void *ppriv)
4818 {
4819         int nch = profile->max_nch(mdev);
4820         struct net_device *netdev;
4821         struct mlx5e_priv *priv;
4822
4823         netdev = alloc_etherdev_mqs(sizeof(struct mlx5e_priv),
4824                                     nch * profile->max_tc,
4825                                     nch);
4826         if (!netdev) {
4827                 mlx5_core_err(mdev, "alloc_etherdev_mqs() failed\n");
4828                 return NULL;
4829         }
4830
4831 #ifdef CONFIG_RFS_ACCEL
4832         netdev->rx_cpu_rmap = mdev->rmap;
4833 #endif
4834
4835         profile->init(mdev, netdev, profile, ppriv);
4836
4837         netif_carrier_off(netdev);
4838
4839         priv = netdev_priv(netdev);
4840
4841         priv->wq = create_singlethread_workqueue("mlx5e");
4842         if (!priv->wq)
4843                 goto err_cleanup_nic;
4844
4845         return netdev;
4846
4847 err_cleanup_nic:
4848         if (profile->cleanup)
4849                 profile->cleanup(priv);
4850         free_netdev(netdev);
4851
4852         return NULL;
4853 }
4854
4855 int mlx5e_attach_netdev(struct mlx5e_priv *priv)
4856 {
4857         struct mlx5_core_dev *mdev = priv->mdev;
4858         const struct mlx5e_profile *profile;
4859         int err;
4860
4861         profile = priv->profile;
4862         clear_bit(MLX5E_STATE_DESTROYING, &priv->state);
4863
4864         err = profile->init_tx(priv);
4865         if (err)
4866                 goto out;
4867
4868         mlx5e_create_q_counters(priv);
4869
4870         err = mlx5e_open_drop_rq(priv, &priv->drop_rq);
4871         if (err) {
4872                 mlx5_core_err(mdev, "open drop rq failed, %d\n", err);
4873                 goto err_destroy_q_counters;
4874         }
4875
4876         err = profile->init_rx(priv);
4877         if (err)
4878                 goto err_close_drop_rq;
4879
4880         if (profile->enable)
4881                 profile->enable(priv);
4882
4883         return 0;
4884
4885 err_close_drop_rq:
4886         mlx5e_close_drop_rq(&priv->drop_rq);
4887
4888 err_destroy_q_counters:
4889         mlx5e_destroy_q_counters(priv);
4890         profile->cleanup_tx(priv);
4891
4892 out:
4893         return err;
4894 }
4895
4896 void mlx5e_detach_netdev(struct mlx5e_priv *priv)
4897 {
4898         const struct mlx5e_profile *profile = priv->profile;
4899
4900         set_bit(MLX5E_STATE_DESTROYING, &priv->state);
4901
4902         if (profile->disable)
4903                 profile->disable(priv);
4904         flush_workqueue(priv->wq);
4905
4906         profile->cleanup_rx(priv);
4907         mlx5e_close_drop_rq(&priv->drop_rq);
4908         mlx5e_destroy_q_counters(priv);
4909         profile->cleanup_tx(priv);
4910         cancel_delayed_work_sync(&priv->update_stats_work);
4911 }
4912
4913 void mlx5e_destroy_netdev(struct mlx5e_priv *priv)
4914 {
4915         const struct mlx5e_profile *profile = priv->profile;
4916         struct net_device *netdev = priv->netdev;
4917
4918         destroy_workqueue(priv->wq);
4919         if (profile->cleanup)
4920                 profile->cleanup(priv);
4921         free_netdev(netdev);
4922 }
4923
4924 /* mlx5e_attach and mlx5e_detach scope should be only creating/destroying
4925  * hardware contexts and to connect it to the current netdev.
4926  */
4927 static int mlx5e_attach(struct mlx5_core_dev *mdev, void *vpriv)
4928 {
4929         struct mlx5e_priv *priv = vpriv;
4930         struct net_device *netdev = priv->netdev;
4931         int err;
4932
4933         if (netif_device_present(netdev))
4934                 return 0;
4935
4936         err = mlx5e_create_mdev_resources(mdev);
4937         if (err)
4938                 return err;
4939
4940         err = mlx5e_attach_netdev(priv);
4941         if (err) {
4942                 mlx5e_destroy_mdev_resources(mdev);
4943                 return err;
4944         }
4945
4946         return 0;
4947 }
4948
4949 static void mlx5e_detach(struct mlx5_core_dev *mdev, void *vpriv)
4950 {
4951         struct mlx5e_priv *priv = vpriv;
4952         struct net_device *netdev = priv->netdev;
4953
4954         if (!netif_device_present(netdev))
4955                 return;
4956
4957         mlx5e_detach_netdev(priv);
4958         mlx5e_destroy_mdev_resources(mdev);
4959 }
4960
4961 static void *mlx5e_add(struct mlx5_core_dev *mdev)
4962 {
4963         struct net_device *netdev;
4964         void *rpriv = NULL;
4965         void *priv;
4966         int err;
4967
4968         err = mlx5e_check_required_hca_cap(mdev);
4969         if (err)
4970                 return NULL;
4971
4972 #ifdef CONFIG_MLX5_ESWITCH
4973         if (MLX5_VPORT_MANAGER(mdev)) {
4974                 rpriv = mlx5e_alloc_nic_rep_priv(mdev);
4975                 if (!rpriv) {
4976                         mlx5_core_warn(mdev, "Failed to alloc NIC rep priv data\n");
4977                         return NULL;
4978                 }
4979         }
4980 #endif
4981
4982         netdev = mlx5e_create_netdev(mdev, &mlx5e_nic_profile, rpriv);
4983         if (!netdev) {
4984                 mlx5_core_err(mdev, "mlx5e_create_netdev failed\n");
4985                 goto err_free_rpriv;
4986         }
4987
4988         priv = netdev_priv(netdev);
4989
4990         err = mlx5e_attach(mdev, priv);
4991         if (err) {
4992                 mlx5_core_err(mdev, "mlx5e_attach failed, %d\n", err);
4993                 goto err_destroy_netdev;
4994         }
4995
4996         err = register_netdev(netdev);
4997         if (err) {
4998                 mlx5_core_err(mdev, "register_netdev failed, %d\n", err);
4999                 goto err_detach;
5000         }
5001
5002 #ifdef CONFIG_MLX5_CORE_EN_DCB
5003         mlx5e_dcbnl_init_app(priv);
5004 #endif
5005         return priv;
5006
5007 err_detach:
5008         mlx5e_detach(mdev, priv);
5009 err_destroy_netdev:
5010         mlx5e_destroy_netdev(priv);
5011 err_free_rpriv:
5012         kfree(rpriv);
5013         return NULL;
5014 }
5015
5016 static void mlx5e_remove(struct mlx5_core_dev *mdev, void *vpriv)
5017 {
5018         struct mlx5e_priv *priv = vpriv;
5019         void *ppriv = priv->ppriv;
5020
5021 #ifdef CONFIG_MLX5_CORE_EN_DCB
5022         mlx5e_dcbnl_delete_app(priv);
5023 #endif
5024         unregister_netdev(priv->netdev);
5025         mlx5e_detach(mdev, vpriv);
5026         mlx5e_destroy_netdev(priv);
5027         kfree(ppriv);
5028 }
5029
5030 static void *mlx5e_get_netdev(void *vpriv)
5031 {
5032         struct mlx5e_priv *priv = vpriv;
5033
5034         return priv->netdev;
5035 }
5036
5037 static struct mlx5_interface mlx5e_interface = {
5038         .add       = mlx5e_add,
5039         .remove    = mlx5e_remove,
5040         .attach    = mlx5e_attach,
5041         .detach    = mlx5e_detach,
5042         .event     = mlx5e_async_event,
5043         .protocol  = MLX5_INTERFACE_PROTOCOL_ETH,
5044         .get_dev   = mlx5e_get_netdev,
5045 };
5046
5047 void mlx5e_init(void)
5048 {
5049         mlx5e_ipsec_build_inverse_table();
5050         mlx5e_build_ptys2ethtool_map();
5051         mlx5_register_interface(&mlx5e_interface);
5052 }
5053
5054 void mlx5e_cleanup(void)
5055 {
5056         mlx5_unregister_interface(&mlx5e_interface);
5057 }