drivers/net/ethernet/mellanox/mlx5/core/en_main.c

   1 /*
   2  * Copyright (c) 2015-2016, Mellanox Technologies. All rights reserved.
   3  *
   4  * This software is available to you under a choice of one of two
   5  * licenses.  You may choose to be licensed under the terms of the GNU
   6  * General Public License (GPL) Version 2, available from the file
   7  * COPYING in the main directory of this source tree, or the
   8  * OpenIB.org BSD license below:
   9  *
  10  *     Redistribution and use in source and binary forms, with or
  11  *     without modification, are permitted provided that the following
  12  *     conditions are met:
  13  *
  14  *      - Redistributions of source code must retain the above
  15  *        copyright notice, this list of conditions and the following
  16  *        disclaimer.
  17  *
  18  *      - Redistributions in binary form must reproduce the above
  19  *        copyright notice, this list of conditions and the following
  20  *        disclaimer in the documentation and/or other materials
  21  *        provided with the distribution.
  22  *
  23  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  24  * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  25  * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
  26  * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
  27  * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
  28  * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
  29  * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
  30  * SOFTWARE.
  31  */
  32
  33 #include <net/tc_act/tc_gact.h>
  34 #include <net/pkt_cls.h>
  35 #include <linux/mlx5/fs.h>
  36 #include <net/vxlan.h>
  37 #include <net/geneve.h>
  38 #include <linux/bpf.h>
  39 #include <linux/if_bridge.h>
  40 #include <net/page_pool.h>
  41 #include <net/xdp_sock_drv.h>
  42 #include "eswitch.h"
  43 #include "en.h"
  44 #include "en/txrx.h"
  45 #include "en_tc.h"
  46 #include "en_rep.h"
  47 #include "en_accel/ipsec.h"
  48 #include "en_accel/ipsec_rxtx.h"
  49 #include "en_accel/en_accel.h"
  50 #include "en_accel/tls.h"
  51 #include "accel/ipsec.h"
  52 #include "accel/tls.h"
  53 #include "lib/vxlan.h"
  54 #include "lib/clock.h"
  55 #include "en/port.h"
  56 #include "en/xdp.h"
  57 #include "lib/eq.h"
  58 #include "en/monitor_stats.h"
  59 #include "en/health.h"
  60 #include "en/params.h"
  61 #include "en/xsk/umem.h"
  62 #include "en/xsk/setup.h"
  63 #include "en/xsk/rx.h"
  64 #include "en/xsk/tx.h"
  65 #include "en/hv_vhca_stats.h"
  66 #include "en/devlink.h"
  67 #include "lib/mlx5.h"
  68
  69 bool mlx5e_check_fragmented_striding_rq_cap(struct mlx5_core_dev *mdev)
  70 {
  71         bool striding_rq_umr = MLX5_CAP_GEN(mdev, striding_rq) &&
  72                 MLX5_CAP_GEN(mdev, umr_ptr_rlky) &&
  73                 MLX5_CAP_ETH(mdev, reg_umr_sq);
  74         u16 max_wqe_sz_cap = MLX5_CAP_GEN(mdev, max_wqe_sz_sq);
  75         bool inline_umr = MLX5E_UMR_WQE_INLINE_SZ <= max_wqe_sz_cap;
  76
  77         if (!striding_rq_umr)
  78                 return false;
  79         if (!inline_umr) {
  80                 mlx5_core_warn(mdev, "Cannot support Striding RQ: UMR WQE size (%d) exceeds maximum supported (%d).\n",
  81                                (int)MLX5E_UMR_WQE_INLINE_SZ, max_wqe_sz_cap);
  82                 return false;
  83         }
  84         return true;
  85 }
  86
  87 void mlx5e_init_rq_type_params(struct mlx5_core_dev *mdev,
  88                                struct mlx5e_params *params)
  89 {
  90         params->log_rq_mtu_frames = is_kdump_kernel() ?
  91                 MLX5E_PARAMS_MINIMUM_LOG_RQ_SIZE :
  92                 MLX5E_PARAMS_DEFAULT_LOG_RQ_SIZE;
  93
  94         mlx5_core_info(mdev, "MLX5E: StrdRq(%d) RqSz(%ld) StrdSz(%ld) RxCqeCmprss(%d)\n",
  95                        params->rq_wq_type == MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ,
  96                        params->rq_wq_type == MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ ?
  97                        BIT(mlx5e_mpwqe_get_log_rq_size(params, NULL)) :
  98                        BIT(params->log_rq_mtu_frames),
  99                        BIT(mlx5e_mpwqe_get_log_stride_size(mdev, params, NULL)),
 100                        MLX5E_GET_PFLAG(params, MLX5E_PFLAG_RX_CQE_COMPRESS));
 101 }
 102
 103 bool mlx5e_striding_rq_possible(struct mlx5_core_dev *mdev,
 104                                 struct mlx5e_params *params)
 105 {
 106         if (!mlx5e_check_fragmented_striding_rq_cap(mdev))
 107                 return false;
 108
 109         if (MLX5_IPSEC_DEV(mdev))
 110                 return false;
 111
 112         if (params->xdp_prog) {
 113                 /* XSK params are not considered here. If striding RQ is in use,
 114                  * and an XSK is being opened, mlx5e_rx_mpwqe_is_linear_skb will
 115                  * be called with the known XSK params.
 116                  */
 117                 if (!mlx5e_rx_mpwqe_is_linear_skb(mdev, params, NULL))
 118                         return false;
 119         }
 120
 121         return true;
 122 }
 123
 124 void mlx5e_set_rq_type(struct mlx5_core_dev *mdev, struct mlx5e_params *params)
 125 {
 126         params->rq_wq_type = mlx5e_striding_rq_possible(mdev, params) &&
 127                 MLX5E_GET_PFLAG(params, MLX5E_PFLAG_RX_STRIDING_RQ) ?
 128                 MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ :
 129                 MLX5_WQ_TYPE_CYCLIC;
 130 }
 131
 132 void mlx5e_update_carrier(struct mlx5e_priv *priv)
 133 {
 134         struct mlx5_core_dev *mdev = priv->mdev;
 135         u8 port_state;
 136
 137         port_state = mlx5_query_vport_state(mdev,
 138                                             MLX5_VPORT_STATE_OP_MOD_VNIC_VPORT,
 139                                             0);
 140
 141         if (port_state == VPORT_STATE_UP) {
 142                 netdev_info(priv->netdev, "Link up\n");
 143                 netif_carrier_on(priv->netdev);
 144         } else {
 145                 netdev_info(priv->netdev, "Link down\n");
 146                 netif_carrier_off(priv->netdev);
 147         }
 148 }
 149
 150 static void mlx5e_update_carrier_work(struct work_struct *work)
 151 {
 152         struct mlx5e_priv *priv = container_of(work, struct mlx5e_priv,
 153                                                update_carrier_work);
 154
 155         mutex_lock(&priv->state_lock);
 156         if (test_bit(MLX5E_STATE_OPENED, &priv->state))
 157                 if (priv->profile->update_carrier)
 158                         priv->profile->update_carrier(priv);
 159         mutex_unlock(&priv->state_lock);
 160 }
 161
 162 void mlx5e_update_ndo_stats(struct mlx5e_priv *priv)
 163 {
 164         int i;
 165
 166         for (i = mlx5e_nic_stats_grps_num(priv) - 1; i >= 0; i--)
 167                 if (mlx5e_nic_stats_grps[i]->update_stats_mask &
 168                     MLX5E_NDO_UPDATE_STATS)
 169                         mlx5e_nic_stats_grps[i]->update_stats(priv);
 170 }
 171
 172 static void mlx5e_update_stats_work(struct work_struct *work)
 173 {
 174         struct mlx5e_priv *priv = container_of(work, struct mlx5e_priv,
 175                                                update_stats_work);
 176
 177         mutex_lock(&priv->state_lock);
 178         priv->profile->update_stats(priv);
 179         mutex_unlock(&priv->state_lock);
 180 }
 181
 182 void mlx5e_queue_update_stats(struct mlx5e_priv *priv)
 183 {
 184         if (!priv->profile->update_stats)
 185                 return;
 186
 187         if (unlikely(test_bit(MLX5E_STATE_DESTROYING, &priv->state)))
 188                 return;
 189
 190         queue_work(priv->wq, &priv->update_stats_work);
 191 }
 192
 193 static int async_event(struct notifier_block *nb, unsigned long event, void *data)
 194 {
 195         struct mlx5e_priv *priv = container_of(nb, struct mlx5e_priv, events_nb);
 196         struct mlx5_eqe   *eqe = data;
 197
 198         if (event != MLX5_EVENT_TYPE_PORT_CHANGE)
 199                 return NOTIFY_DONE;
 200
 201         switch (eqe->sub_type) {
 202         case MLX5_PORT_CHANGE_SUBTYPE_DOWN:
 203         case MLX5_PORT_CHANGE_SUBTYPE_ACTIVE:
 204                 queue_work(priv->wq, &priv->update_carrier_work);
 205                 break;
 206         default:
 207                 return NOTIFY_DONE;
 208         }
 209
 210         return NOTIFY_OK;
 211 }
 212
 213 static void mlx5e_enable_async_events(struct mlx5e_priv *priv)
 214 {
 215         priv->events_nb.notifier_call = async_event;
 216         mlx5_notifier_register(priv->mdev, &priv->events_nb);
 217 }
 218
 219 static void mlx5e_disable_async_events(struct mlx5e_priv *priv)
 220 {
 221         mlx5_notifier_unregister(priv->mdev, &priv->events_nb);
 222 }
 223
 224 static inline void mlx5e_build_umr_wqe(struct mlx5e_rq *rq,
 225                                        struct mlx5e_icosq *sq,
 226                                        struct mlx5e_umr_wqe *wqe)
 227 {
 228         struct mlx5_wqe_ctrl_seg      *cseg = &wqe->ctrl;
 229         struct mlx5_wqe_umr_ctrl_seg *ucseg = &wqe->uctrl;
 230         u8 ds_cnt = DIV_ROUND_UP(MLX5E_UMR_WQE_INLINE_SZ, MLX5_SEND_WQE_DS);
 231
 232         cseg->qpn_ds    = cpu_to_be32((sq->sqn << MLX5_WQE_CTRL_QPN_SHIFT) |
 233                                       ds_cnt);
 234         cseg->fm_ce_se  = MLX5_WQE_CTRL_CQ_UPDATE;
 235         cseg->umr_mkey  = rq->mkey_be;
 236
 237         ucseg->flags = MLX5_UMR_TRANSLATION_OFFSET_EN | MLX5_UMR_INLINE;
 238         ucseg->xlt_octowords =
 239                 cpu_to_be16(MLX5_MTT_OCTW(MLX5_MPWRQ_PAGES_PER_WQE));
 240         ucseg->mkey_mask     = cpu_to_be64(MLX5_MKEY_MASK_FREE);
 241 }
 242
 243 static int mlx5e_rq_alloc_mpwqe_info(struct mlx5e_rq *rq,
 244                                      struct mlx5e_channel *c)
 245 {
 246         int wq_sz = mlx5_wq_ll_get_size(&rq->mpwqe.wq);
 247
 248         rq->mpwqe.info = kvzalloc_node(array_size(wq_sz,
 249                                                   sizeof(*rq->mpwqe.info)),
 250                                        GFP_KERNEL, cpu_to_node(c->cpu));
 251         if (!rq->mpwqe.info)
 252                 return -ENOMEM;
 253
 254         mlx5e_build_umr_wqe(rq, &c->icosq, &rq->mpwqe.umr_wqe);
 255
 256         return 0;
 257 }
 258
 259 static int mlx5e_create_umr_mkey(struct mlx5_core_dev *mdev,
 260                                  u64 npages, u8 page_shift,
 261                                  struct mlx5_core_mkey *umr_mkey)
 262 {
 263         int inlen = MLX5_ST_SZ_BYTES(create_mkey_in);
 264         void *mkc;
 265         u32 *in;
 266         int err;
 267
 268         in = kvzalloc(inlen, GFP_KERNEL);
 269         if (!in)
 270                 return -ENOMEM;
 271
 272         mkc = MLX5_ADDR_OF(create_mkey_in, in, memory_key_mkey_entry);
 273
 274         MLX5_SET(mkc, mkc, free, 1);
 275         MLX5_SET(mkc, mkc, umr_en, 1);
 276         MLX5_SET(mkc, mkc, lw, 1);
 277         MLX5_SET(mkc, mkc, lr, 1);
 278         MLX5_SET(mkc, mkc, access_mode_1_0, MLX5_MKC_ACCESS_MODE_MTT);
 279
 280         MLX5_SET(mkc, mkc, qpn, 0xffffff);
 281         MLX5_SET(mkc, mkc, pd, mdev->mlx5e_res.pdn);
 282         MLX5_SET64(mkc, mkc, len, npages << page_shift);
 283         MLX5_SET(mkc, mkc, translations_octword_size,
 284                  MLX5_MTT_OCTW(npages));
 285         MLX5_SET(mkc, mkc, log_page_size, page_shift);
 286
 287         err = mlx5_core_create_mkey(mdev, umr_mkey, in, inlen);
 288
 289         kvfree(in);
 290         return err;
 291 }
 292
 293 static int mlx5e_create_rq_umr_mkey(struct mlx5_core_dev *mdev, struct mlx5e_rq *rq)
 294 {
 295         u64 num_mtts = MLX5E_REQUIRED_MTTS(mlx5_wq_ll_get_size(&rq->mpwqe.wq));
 296
 297         return mlx5e_create_umr_mkey(mdev, num_mtts, PAGE_SHIFT, &rq->umr_mkey);
 298 }
 299
 300 static inline u64 mlx5e_get_mpwqe_offset(struct mlx5e_rq *rq, u16 wqe_ix)
 301 {
 302         return (wqe_ix << MLX5E_LOG_ALIGNED_MPWQE_PPW) << PAGE_SHIFT;
 303 }
 304
 305 static void mlx5e_init_frags_partition(struct mlx5e_rq *rq)
 306 {
 307         struct mlx5e_wqe_frag_info next_frag = {};
 308         struct mlx5e_wqe_frag_info *prev = NULL;
 309         int i;
 310
 311         next_frag.di = &rq->wqe.di[0];
 312
 313         for (i = 0; i < mlx5_wq_cyc_get_size(&rq->wqe.wq); i++) {
 314                 struct mlx5e_rq_frag_info *frag_info = &rq->wqe.info.arr[0];
 315                 struct mlx5e_wqe_frag_info *frag =
 316                         &rq->wqe.frags[i << rq->wqe.info.log_num_frags];
 317                 int f;
 318
 319                 for (f = 0; f < rq->wqe.info.num_frags; f++, frag++) {
 320                         if (next_frag.offset + frag_info[f].frag_stride > PAGE_SIZE) {
 321                                 next_frag.di++;
 322                                 next_frag.offset = 0;
 323                                 if (prev)
 324                                         prev->last_in_page = true;
 325                         }
 326                         *frag = next_frag;
 327
 328                         /* prepare next */
 329                         next_frag.offset += frag_info[f].frag_stride;
 330                         prev = frag;
 331                 }
 332         }
 333
 334         if (prev)
 335                 prev->last_in_page = true;
 336 }
 337
 338 static int mlx5e_init_di_list(struct mlx5e_rq *rq,
 339                               int wq_sz, int cpu)
 340 {
 341         int len = wq_sz << rq->wqe.info.log_num_frags;
 342
 343         rq->wqe.di = kvzalloc_node(array_size(len, sizeof(*rq->wqe.di)),
 344                                    GFP_KERNEL, cpu_to_node(cpu));
 345         if (!rq->wqe.di)
 346                 return -ENOMEM;
 347
 348         mlx5e_init_frags_partition(rq);
 349
 350         return 0;
 351 }
 352
 353 static void mlx5e_free_di_list(struct mlx5e_rq *rq)
 354 {
 355         kvfree(rq->wqe.di);
 356 }
 357
 358 static void mlx5e_rq_err_cqe_work(struct work_struct *recover_work)
 359 {
 360         struct mlx5e_rq *rq = container_of(recover_work, struct mlx5e_rq, recover_work);
 361
 362         mlx5e_reporter_rq_cqe_err(rq);
 363 }
 364
 365 static int mlx5e_alloc_rq(struct mlx5e_channel *c,
 366                           struct mlx5e_params *params,
 367                           struct mlx5e_xsk_param *xsk,
 368                           struct xdp_umem *umem,
 369                           struct mlx5e_rq_param *rqp,
 370                           struct mlx5e_rq *rq)
 371 {
 372         struct page_pool_params pp_params = { 0 };
 373         struct mlx5_core_dev *mdev = c->mdev;
 374         void *rqc = rqp->rqc;
 375         void *rqc_wq = MLX5_ADDR_OF(rqc, rqc, wq);
 376         u32 rq_xdp_ix;
 377         u32 pool_size;
 378         int wq_sz;
 379         int err;
 380         int i;
 381
 382         rqp->wq.db_numa_node = cpu_to_node(c->cpu);
 383
 384         rq->wq_type = params->rq_wq_type;
 385         rq->pdev    = c->pdev;
 386         rq->netdev  = c->netdev;
 387         rq->tstamp  = c->tstamp;
 388         rq->clock   = &mdev->clock;
 389         rq->channel = c;
 390         rq->ix      = c->ix;
 391         rq->mdev    = mdev;
 392         rq->hw_mtu  = MLX5E_SW2HW_MTU(params, params->sw_mtu);
 393         rq->xdpsq   = &c->rq_xdpsq;
 394         rq->umem    = umem;
 395
 396         if (rq->umem)
 397                 rq->stats = &c->priv->channel_stats[c->ix].xskrq;
 398         else
 399                 rq->stats = &c->priv->channel_stats[c->ix].rq;
 400         INIT_WORK(&rq->recover_work, mlx5e_rq_err_cqe_work);
 401
 402         if (params->xdp_prog)
 403                 bpf_prog_inc(params->xdp_prog);
 404         rq->xdp_prog = params->xdp_prog;
 405
 406         rq_xdp_ix = rq->ix;
 407         if (xsk)
 408                 rq_xdp_ix += params->num_channels * MLX5E_RQ_GROUP_XSK;
 409         err = xdp_rxq_info_reg(&rq->xdp_rxq, rq->netdev, rq_xdp_ix);
 410         if (err < 0)
 411                 goto err_rq_wq_destroy;
 412
 413         rq->buff.map_dir = rq->xdp_prog ? DMA_BIDIRECTIONAL : DMA_FROM_DEVICE;
 414         rq->buff.headroom = mlx5e_get_rq_headroom(mdev, params, xsk);
 415         pool_size = 1 << params->log_rq_mtu_frames;
 416
 417         switch (rq->wq_type) {
 418         case MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ:
 419                 err = mlx5_wq_ll_create(mdev, &rqp->wq, rqc_wq, &rq->mpwqe.wq,
 420                                         &rq->wq_ctrl);
 421                 if (err)
 422                         return err;
 423
 424                 rq->mpwqe.wq.db = &rq->mpwqe.wq.db[MLX5_RCV_DBR];
 425
 426                 wq_sz = mlx5_wq_ll_get_size(&rq->mpwqe.wq);
 427
 428                 pool_size = MLX5_MPWRQ_PAGES_PER_WQE <<
 429                         mlx5e_mpwqe_get_log_rq_size(params, xsk);
 430
 431                 rq->post_wqes = mlx5e_post_rx_mpwqes;
 432                 rq->dealloc_wqe = mlx5e_dealloc_rx_mpwqe;
 433
 434                 rq->handle_rx_cqe = c->priv->profile->rx_handlers.handle_rx_cqe_mpwqe;
 435 #ifdef CONFIG_MLX5_EN_IPSEC
 436                 if (MLX5_IPSEC_DEV(mdev)) {
 437                         err = -EINVAL;
 438                         netdev_err(c->netdev, "MPWQE RQ with IPSec offload not supported\n");
 439                         goto err_rq_wq_destroy;
 440                 }
 441 #endif
 442                 if (!rq->handle_rx_cqe) {
 443                         err = -EINVAL;
 444                         netdev_err(c->netdev, "RX handler of MPWQE RQ is not set, err %d\n", err);
 445                         goto err_rq_wq_destroy;
 446                 }
 447
 448                 rq->mpwqe.skb_from_cqe_mpwrq = xsk ?
 449                         mlx5e_xsk_skb_from_cqe_mpwrq_linear :
 450                         mlx5e_rx_mpwqe_is_linear_skb(mdev, params, NULL) ?
 451                                 mlx5e_skb_from_cqe_mpwrq_linear :
 452                                 mlx5e_skb_from_cqe_mpwrq_nonlinear;
 453
 454                 rq->mpwqe.log_stride_sz = mlx5e_mpwqe_get_log_stride_size(mdev, params, xsk);
 455                 rq->mpwqe.num_strides =
 456                         BIT(mlx5e_mpwqe_get_log_num_strides(mdev, params, xsk));
 457
 458                 rq->buff.frame0_sz = (1 << rq->mpwqe.log_stride_sz);
 459
 460                 err = mlx5e_create_rq_umr_mkey(mdev, rq);
 461                 if (err)
 462                         goto err_rq_wq_destroy;
 463                 rq->mkey_be = cpu_to_be32(rq->umr_mkey.key);
 464
 465                 err = mlx5e_rq_alloc_mpwqe_info(rq, c);
 466                 if (err)
 467                         goto err_free;
 468                 break;
 469         default: /* MLX5_WQ_TYPE_CYCLIC */
 470                 err = mlx5_wq_cyc_create(mdev, &rqp->wq, rqc_wq, &rq->wqe.wq,
 471                                          &rq->wq_ctrl);
 472                 if (err)
 473                         return err;
 474
 475                 rq->wqe.wq.db = &rq->wqe.wq.db[MLX5_RCV_DBR];
 476
 477                 wq_sz = mlx5_wq_cyc_get_size(&rq->wqe.wq);
 478
 479                 rq->wqe.info = rqp->frags_info;
 480                 rq->buff.frame0_sz = rq->wqe.info.arr[0].frag_stride;
 481
 482                 rq->wqe.frags =
 483                         kvzalloc_node(array_size(sizeof(*rq->wqe.frags),
 484                                         (wq_sz << rq->wqe.info.log_num_frags)),
 485                                       GFP_KERNEL, cpu_to_node(c->cpu));
 486                 if (!rq->wqe.frags) {
 487                         err = -ENOMEM;
 488                         goto err_free;
 489                 }
 490
 491                 err = mlx5e_init_di_list(rq, wq_sz, c->cpu);
 492                 if (err)
 493                         goto err_free;
 494
 495                 rq->post_wqes = mlx5e_post_rx_wqes;
 496                 rq->dealloc_wqe = mlx5e_dealloc_rx_wqe;
 497
 498 #ifdef CONFIG_MLX5_EN_IPSEC
 499                 if (c->priv->ipsec)
 500                         rq->handle_rx_cqe = mlx5e_ipsec_handle_rx_cqe;
 501                 else
 502 #endif
 503                         rq->handle_rx_cqe = c->priv->profile->rx_handlers.handle_rx_cqe;
 504                 if (!rq->handle_rx_cqe) {
 505                         err = -EINVAL;
 506                         netdev_err(c->netdev, "RX handler of RQ is not set, err %d\n", err);
 507                         goto err_free;
 508                 }
 509
 510                 rq->wqe.skb_from_cqe = xsk ?
 511                         mlx5e_xsk_skb_from_cqe_linear :
 512                         mlx5e_rx_is_linear_skb(params, NULL) ?
 513                                 mlx5e_skb_from_cqe_linear :
 514                                 mlx5e_skb_from_cqe_nonlinear;
 515                 rq->mkey_be = c->mkey_be;
 516         }
 517
 518         if (xsk) {
 519                 err = xdp_rxq_info_reg_mem_model(&rq->xdp_rxq,
 520                                                  MEM_TYPE_XSK_BUFF_POOL, NULL);
 521                 xsk_buff_set_rxq_info(rq->umem, &rq->xdp_rxq);
 522         } else {
 523                 /* Create a page_pool and register it with rxq */
 524                 pp_params.order     = 0;
 525                 pp_params.flags     = 0; /* No-internal DMA mapping in page_pool */
 526                 pp_params.pool_size = pool_size;
 527                 pp_params.nid       = cpu_to_node(c->cpu);
 528                 pp_params.dev       = c->pdev;
 529                 pp_params.dma_dir   = rq->buff.map_dir;
 530
 531                 /* page_pool can be used even when there is no rq->xdp_prog,
 532                  * given page_pool does not handle DMA mapping there is no
 533                  * required state to clear. And page_pool gracefully handle
 534                  * elevated refcnt.
 535                  */
 536                 rq->page_pool = page_pool_create(&pp_params);
 537                 if (IS_ERR(rq->page_pool)) {
 538                         err = PTR_ERR(rq->page_pool);
 539                         rq->page_pool = NULL;
 540                         goto err_free;
 541                 }
 542                 err = xdp_rxq_info_reg_mem_model(&rq->xdp_rxq,
 543                                                  MEM_TYPE_PAGE_POOL, rq->page_pool);
 544         }
 545         if (err)
 546                 goto err_free;
 547
 548         for (i = 0; i < wq_sz; i++) {
 549                 if (rq->wq_type == MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ) {
 550                         struct mlx5e_rx_wqe_ll *wqe =
 551                                 mlx5_wq_ll_get_wqe(&rq->mpwqe.wq, i);
 552                         u32 byte_count =
 553                                 rq->mpwqe.num_strides << rq->mpwqe.log_stride_sz;
 554                         u64 dma_offset = mlx5e_get_mpwqe_offset(rq, i);
 555
 556                         wqe->data[0].addr = cpu_to_be64(dma_offset + rq->buff.headroom);
 557                         wqe->data[0].byte_count = cpu_to_be32(byte_count);
 558                         wqe->data[0].lkey = rq->mkey_be;
 559                 } else {
 560                         struct mlx5e_rx_wqe_cyc *wqe =
 561                                 mlx5_wq_cyc_get_wqe(&rq->wqe.wq, i);
 562                         int f;
 563
 564                         for (f = 0; f < rq->wqe.info.num_frags; f++) {
 565                                 u32 frag_size = rq->wqe.info.arr[f].frag_size |
 566                                         MLX5_HW_START_PADDING;
 567
 568                                 wqe->data[f].byte_count = cpu_to_be32(frag_size);
 569                                 wqe->data[f].lkey = rq->mkey_be;
 570                         }
 571                         /* check if num_frags is not a pow of two */
 572                         if (rq->wqe.info.num_frags < (1 << rq->wqe.info.log_num_frags)) {
 573                                 wqe->data[f].byte_count = 0;
 574                                 wqe->data[f].lkey = cpu_to_be32(MLX5_INVALID_LKEY);
 575                                 wqe->data[f].addr = 0;
 576                         }
 577                 }
 578         }
 579
 580         INIT_WORK(&rq->dim.work, mlx5e_rx_dim_work);
 581
 582         switch (params->rx_cq_moderation.cq_period_mode) {
 583         case MLX5_CQ_PERIOD_MODE_START_FROM_CQE:
 584                 rq->dim.mode = DIM_CQ_PERIOD_MODE_START_FROM_CQE;
 585                 break;
 586         case MLX5_CQ_PERIOD_MODE_START_FROM_EQE:
 587         default:
 588                 rq->dim.mode = DIM_CQ_PERIOD_MODE_START_FROM_EQE;
 589         }
 590
 591         rq->page_cache.head = 0;
 592         rq->page_cache.tail = 0;
 593
 594         return 0;
 595
 596 err_free:
 597         switch (rq->wq_type) {
 598         case MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ:
 599                 kvfree(rq->mpwqe.info);
 600                 mlx5_core_destroy_mkey(mdev, &rq->umr_mkey);
 601                 break;
 602         default: /* MLX5_WQ_TYPE_CYCLIC */
 603                 kvfree(rq->wqe.frags);
 604                 mlx5e_free_di_list(rq);
 605         }
 606
 607 err_rq_wq_destroy:
 608         if (rq->xdp_prog)
 609                 bpf_prog_put(rq->xdp_prog);
 610         xdp_rxq_info_unreg(&rq->xdp_rxq);
 611         page_pool_destroy(rq->page_pool);
 612         mlx5_wq_destroy(&rq->wq_ctrl);
 613
 614         return err;
 615 }
 616
 617 static void mlx5e_free_rq(struct mlx5e_rq *rq)
 618 {
 619         int i;
 620
 621         if (rq->xdp_prog)
 622                 bpf_prog_put(rq->xdp_prog);
 623
 624         switch (rq->wq_type) {
 625         case MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ:
 626                 kvfree(rq->mpwqe.info);
 627                 mlx5_core_destroy_mkey(rq->mdev, &rq->umr_mkey);
 628                 break;
 629         default: /* MLX5_WQ_TYPE_CYCLIC */
 630                 kvfree(rq->wqe.frags);
 631                 mlx5e_free_di_list(rq);
 632         }
 633
 634         for (i = rq->page_cache.head; i != rq->page_cache.tail;
 635              i = (i + 1) & (MLX5E_CACHE_SIZE - 1)) {
 636                 struct mlx5e_dma_info *dma_info = &rq->page_cache.page_cache[i];
 637
 638                 /* With AF_XDP, page_cache is not used, so this loop is not
 639                  * entered, and it's safe to call mlx5e_page_release_dynamic
 640                  * directly.
 641                  */
 642                 mlx5e_page_release_dynamic(rq, dma_info, false);
 643         }
 644
 645         xdp_rxq_info_unreg(&rq->xdp_rxq);
 646         page_pool_destroy(rq->page_pool);
 647         mlx5_wq_destroy(&rq->wq_ctrl);
 648 }
 649
 650 static int mlx5e_create_rq(struct mlx5e_rq *rq,
 651                            struct mlx5e_rq_param *param)
 652 {
 653         struct mlx5_core_dev *mdev = rq->mdev;
 654
 655         void *in;
 656         void *rqc;
 657         void *wq;
 658         int inlen;
 659         int err;
 660
 661         inlen = MLX5_ST_SZ_BYTES(create_rq_in) +
 662                 sizeof(u64) * rq->wq_ctrl.buf.npages;
 663         in = kvzalloc(inlen, GFP_KERNEL);
 664         if (!in)
 665                 return -ENOMEM;
 666
 667         rqc = MLX5_ADDR_OF(create_rq_in, in, ctx);
 668         wq  = MLX5_ADDR_OF(rqc, rqc, wq);
 669
 670         memcpy(rqc, param->rqc, sizeof(param->rqc));
 671
 672         MLX5_SET(rqc,  rqc, cqn,                rq->cq.mcq.cqn);
 673         MLX5_SET(rqc,  rqc, state,              MLX5_RQC_STATE_RST);
 674         MLX5_SET(wq,   wq,  log_wq_pg_sz,       rq->wq_ctrl.buf.page_shift -
 675                                                 MLX5_ADAPTER_PAGE_SHIFT);
 676         MLX5_SET64(wq, wq,  dbr_addr,           rq->wq_ctrl.db.dma);
 677
 678         mlx5_fill_page_frag_array(&rq->wq_ctrl.buf,
 679                                   (__be64 *)MLX5_ADDR_OF(wq, wq, pas));
 680
 681         err = mlx5_core_create_rq(mdev, in, inlen, &rq->rqn);
 682
 683         kvfree(in);
 684
 685         return err;
 686 }
 687
 688 int mlx5e_modify_rq_state(struct mlx5e_rq *rq, int curr_state, int next_state)
 689 {
 690         struct mlx5_core_dev *mdev = rq->mdev;
 691
 692         void *in;
 693         void *rqc;
 694         int inlen;
 695         int err;
 696
 697         inlen = MLX5_ST_SZ_BYTES(modify_rq_in);
 698         in = kvzalloc(inlen, GFP_KERNEL);
 699         if (!in)
 700                 return -ENOMEM;
 701
 702         if (curr_state == MLX5_RQC_STATE_RST && next_state == MLX5_RQC_STATE_RDY)
 703                 mlx5e_rqwq_reset(rq);
 704
 705         rqc = MLX5_ADDR_OF(modify_rq_in, in, ctx);
 706
 707         MLX5_SET(modify_rq_in, in, rq_state, curr_state);
 708         MLX5_SET(rqc, rqc, state, next_state);
 709
 710         err = mlx5_core_modify_rq(mdev, rq->rqn, in);
 711
 712         kvfree(in);
 713
 714         return err;
 715 }
 716
 717 static int mlx5e_modify_rq_scatter_fcs(struct mlx5e_rq *rq, bool enable)
 718 {
 719         struct mlx5e_channel *c = rq->channel;
 720         struct mlx5e_priv *priv = c->priv;
 721         struct mlx5_core_dev *mdev = priv->mdev;
 722
 723         void *in;
 724         void *rqc;
 725         int inlen;
 726         int err;
 727
 728         inlen = MLX5_ST_SZ_BYTES(modify_rq_in);
 729         in = kvzalloc(inlen, GFP_KERNEL);
 730         if (!in)
 731                 return -ENOMEM;
 732
 733         rqc = MLX5_ADDR_OF(modify_rq_in, in, ctx);
 734
 735         MLX5_SET(modify_rq_in, in, rq_state, MLX5_RQC_STATE_RDY);
 736         MLX5_SET64(modify_rq_in, in, modify_bitmask,
 737                    MLX5_MODIFY_RQ_IN_MODIFY_BITMASK_SCATTER_FCS);
 738         MLX5_SET(rqc, rqc, scatter_fcs, enable);
 739         MLX5_SET(rqc, rqc, state, MLX5_RQC_STATE_RDY);
 740
 741         err = mlx5_core_modify_rq(mdev, rq->rqn, in);
 742
 743         kvfree(in);
 744
 745         return err;
 746 }
 747
 748 static int mlx5e_modify_rq_vsd(struct mlx5e_rq *rq, bool vsd)
 749 {
 750         struct mlx5e_channel *c = rq->channel;
 751         struct mlx5_core_dev *mdev = c->mdev;
 752         void *in;
 753         void *rqc;
 754         int inlen;
 755         int err;
 756
 757         inlen = MLX5_ST_SZ_BYTES(modify_rq_in);
 758         in = kvzalloc(inlen, GFP_KERNEL);
 759         if (!in)
 760                 return -ENOMEM;
 761
 762         rqc = MLX5_ADDR_OF(modify_rq_in, in, ctx);
 763
 764         MLX5_SET(modify_rq_in, in, rq_state, MLX5_RQC_STATE_RDY);
 765         MLX5_SET64(modify_rq_in, in, modify_bitmask,
 766                    MLX5_MODIFY_RQ_IN_MODIFY_BITMASK_VSD);
 767         MLX5_SET(rqc, rqc, vsd, vsd);
 768         MLX5_SET(rqc, rqc, state, MLX5_RQC_STATE_RDY);
 769
 770         err = mlx5_core_modify_rq(mdev, rq->rqn, in);
 771
 772         kvfree(in);
 773
 774         return err;
 775 }
 776
 777 static void mlx5e_destroy_rq(struct mlx5e_rq *rq)
 778 {
 779         mlx5_core_destroy_rq(rq->mdev, rq->rqn);
 780 }
 781
 782 int mlx5e_wait_for_min_rx_wqes(struct mlx5e_rq *rq, int wait_time)
 783 {
 784         unsigned long exp_time = jiffies + msecs_to_jiffies(wait_time);
 785         struct mlx5e_channel *c = rq->channel;
 786
 787         u16 min_wqes = mlx5_min_rx_wqes(rq->wq_type, mlx5e_rqwq_get_size(rq));
 788
 789         do {
 790                 if (mlx5e_rqwq_get_cur_sz(rq) >= min_wqes)
 791                         return 0;
 792
 793                 msleep(20);
 794         } while (time_before(jiffies, exp_time));
 795
 796         netdev_warn(c->netdev, "Failed to get min RX wqes on Channel[%d] RQN[0x%x] wq cur_sz(%d) min_rx_wqes(%d)\n",
 797                     c->ix, rq->rqn, mlx5e_rqwq_get_cur_sz(rq), min_wqes);
 798
 799         mlx5e_reporter_rx_timeout(rq);
 800         return -ETIMEDOUT;
 801 }
 802
 803 void mlx5e_free_rx_in_progress_descs(struct mlx5e_rq *rq)
 804 {
 805         struct mlx5_wq_ll *wq;
 806         u16 head;
 807         int i;
 808
 809         if (rq->wq_type != MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ)
 810                 return;
 811
 812         wq = &rq->mpwqe.wq;
 813         head = wq->head;
 814
 815         /* Outstanding UMR WQEs (in progress) start at wq->head */
 816         for (i = 0; i < rq->mpwqe.umr_in_progress; i++) {
 817                 rq->dealloc_wqe(rq, head);
 818                 head = mlx5_wq_ll_get_wqe_next_ix(wq, head);
 819         }
 820
 821         rq->mpwqe.actual_wq_head = wq->head;
 822         rq->mpwqe.umr_in_progress = 0;
 823         rq->mpwqe.umr_completed = 0;
 824 }
 825
 826 void mlx5e_free_rx_descs(struct mlx5e_rq *rq)
 827 {
 828         __be16 wqe_ix_be;
 829         u16 wqe_ix;
 830
 831         if (rq->wq_type == MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ) {
 832                 struct mlx5_wq_ll *wq = &rq->mpwqe.wq;
 833
 834                 mlx5e_free_rx_in_progress_descs(rq);
 835
 836                 while (!mlx5_wq_ll_is_empty(wq)) {
 837                         struct mlx5e_rx_wqe_ll *wqe;
 838
 839                         wqe_ix_be = *wq->tail_next;
 840                         wqe_ix    = be16_to_cpu(wqe_ix_be);
 841                         wqe       = mlx5_wq_ll_get_wqe(wq, wqe_ix);
 842                         rq->dealloc_wqe(rq, wqe_ix);
 843                         mlx5_wq_ll_pop(wq, wqe_ix_be,
 844                                        &wqe->next.next_wqe_index);
 845                 }
 846         } else {
 847                 struct mlx5_wq_cyc *wq = &rq->wqe.wq;
 848
 849                 while (!mlx5_wq_cyc_is_empty(wq)) {
 850                         wqe_ix = mlx5_wq_cyc_get_tail(wq);
 851                         rq->dealloc_wqe(rq, wqe_ix);
 852                         mlx5_wq_cyc_pop(wq);
 853                 }
 854         }
 855
 856 }
 857
 858 int mlx5e_open_rq(struct mlx5e_channel *c, struct mlx5e_params *params,
 859                   struct mlx5e_rq_param *param, struct mlx5e_xsk_param *xsk,
 860                   struct xdp_umem *umem, struct mlx5e_rq *rq)
 861 {
 862         int err;
 863
 864         err = mlx5e_alloc_rq(c, params, xsk, umem, param, rq);
 865         if (err)
 866                 return err;
 867
 868         err = mlx5e_create_rq(rq, param);
 869         if (err)
 870                 goto err_free_rq;
 871
 872         err = mlx5e_modify_rq_state(rq, MLX5_RQC_STATE_RST, MLX5_RQC_STATE_RDY);
 873         if (err)
 874                 goto err_destroy_rq;
 875
 876         if (MLX5_CAP_ETH(c->mdev, cqe_checksum_full))
 877                 __set_bit(MLX5E_RQ_STATE_CSUM_FULL, &c->rq.state);
 878
 879         if (params->rx_dim_enabled)
 880                 __set_bit(MLX5E_RQ_STATE_AM, &c->rq.state);
 881
 882         /* We disable csum_complete when XDP is enabled since
 883          * XDP programs might manipulate packets which will render
 884          * skb->checksum incorrect.
 885          */
 886         if (MLX5E_GET_PFLAG(params, MLX5E_PFLAG_RX_NO_CSUM_COMPLETE) || c->xdp)
 887                 __set_bit(MLX5E_RQ_STATE_NO_CSUM_COMPLETE, &c->rq.state);
 888
 889         return 0;
 890
 891 err_destroy_rq:
 892         mlx5e_destroy_rq(rq);
 893 err_free_rq:
 894         mlx5e_free_rq(rq);
 895
 896         return err;
 897 }
 898
 899 void mlx5e_activate_rq(struct mlx5e_rq *rq)
 900 {
 901         set_bit(MLX5E_RQ_STATE_ENABLED, &rq->state);
 902         mlx5e_trigger_irq(&rq->channel->icosq);
 903 }
 904
 905 void mlx5e_deactivate_rq(struct mlx5e_rq *rq)
 906 {
 907         clear_bit(MLX5E_RQ_STATE_ENABLED, &rq->state);
 908         napi_synchronize(&rq->channel->napi); /* prevent mlx5e_post_rx_wqes */
 909 }
 910
 911 void mlx5e_close_rq(struct mlx5e_rq *rq)
 912 {
 913         cancel_work_sync(&rq->dim.work);
 914         cancel_work_sync(&rq->channel->icosq.recover_work);
 915         cancel_work_sync(&rq->recover_work);
 916         mlx5e_destroy_rq(rq);
 917         mlx5e_free_rx_descs(rq);
 918         mlx5e_free_rq(rq);
 919 }
 920
 921 static void mlx5e_free_xdpsq_db(struct mlx5e_xdpsq *sq)
 922 {
 923         kvfree(sq->db.xdpi_fifo.xi);
 924         kvfree(sq->db.wqe_info);
 925 }
 926
 927 static int mlx5e_alloc_xdpsq_fifo(struct mlx5e_xdpsq *sq, int numa)
 928 {
 929         struct mlx5e_xdp_info_fifo *xdpi_fifo = &sq->db.xdpi_fifo;
 930         int wq_sz        = mlx5_wq_cyc_get_size(&sq->wq);
 931         int dsegs_per_wq = wq_sz * MLX5_SEND_WQEBB_NUM_DS;
 932
 933         xdpi_fifo->xi = kvzalloc_node(sizeof(*xdpi_fifo->xi) * dsegs_per_wq,
 934                                       GFP_KERNEL, numa);
 935         if (!xdpi_fifo->xi)
 936                 return -ENOMEM;
 937
 938         xdpi_fifo->pc   = &sq->xdpi_fifo_pc;
 939         xdpi_fifo->cc   = &sq->xdpi_fifo_cc;
 940         xdpi_fifo->mask = dsegs_per_wq - 1;
 941
 942         return 0;
 943 }
 944
 945 static int mlx5e_alloc_xdpsq_db(struct mlx5e_xdpsq *sq, int numa)
 946 {
 947         int wq_sz = mlx5_wq_cyc_get_size(&sq->wq);
 948         int err;
 949
 950         sq->db.wqe_info = kvzalloc_node(sizeof(*sq->db.wqe_info) * wq_sz,
 951                                         GFP_KERNEL, numa);
 952         if (!sq->db.wqe_info)
 953                 return -ENOMEM;
 954
 955         err = mlx5e_alloc_xdpsq_fifo(sq, numa);
 956         if (err) {
 957                 mlx5e_free_xdpsq_db(sq);
 958                 return err;
 959         }
 960
 961         return 0;
 962 }
 963
 964 static int mlx5e_alloc_xdpsq(struct mlx5e_channel *c,
 965                              struct mlx5e_params *params,
 966                              struct xdp_umem *umem,
 967                              struct mlx5e_sq_param *param,
 968                              struct mlx5e_xdpsq *sq,
 969                              bool is_redirect)
 970 {
 971         void *sqc_wq               = MLX5_ADDR_OF(sqc, param->sqc, wq);
 972         struct mlx5_core_dev *mdev = c->mdev;
 973         struct mlx5_wq_cyc *wq = &sq->wq;
 974         int err;
 975
 976         sq->pdev      = c->pdev;
 977         sq->mkey_be   = c->mkey_be;
 978         sq->channel   = c;
 979         sq->uar_map   = mdev->mlx5e_res.bfreg.map;
 980         sq->min_inline_mode = params->tx_min_inline_mode;
 981         sq->hw_mtu    = MLX5E_SW2HW_MTU(params, params->sw_mtu);
 982         sq->umem      = umem;
 983
 984         sq->stats = sq->umem ?
 985                 &c->priv->channel_stats[c->ix].xsksq :
 986                 is_redirect ?
 987                         &c->priv->channel_stats[c->ix].xdpsq :
 988                         &c->priv->channel_stats[c->ix].rq_xdpsq;
 989
 990         param->wq.db_numa_node = cpu_to_node(c->cpu);
 991         err = mlx5_wq_cyc_create(mdev, &param->wq, sqc_wq, wq, &sq->wq_ctrl);
 992         if (err)
 993                 return err;
 994         wq->db = &wq->db[MLX5_SND_DBR];
 995
 996         err = mlx5e_alloc_xdpsq_db(sq, cpu_to_node(c->cpu));
 997         if (err)
 998                 goto err_sq_wq_destroy;
 999
1000         return 0;
1001
1002 err_sq_wq_destroy:
1003         mlx5_wq_destroy(&sq->wq_ctrl);
1004
1005         return err;
1006 }
1007
1008 static void mlx5e_free_xdpsq(struct mlx5e_xdpsq *sq)
1009 {
1010         mlx5e_free_xdpsq_db(sq);
1011         mlx5_wq_destroy(&sq->wq_ctrl);
1012 }
1013
1014 static void mlx5e_free_icosq_db(struct mlx5e_icosq *sq)
1015 {
1016         kvfree(sq->db.wqe_info);
1017 }
1018
1019 static int mlx5e_alloc_icosq_db(struct mlx5e_icosq *sq, int numa)
1020 {
1021         int wq_sz = mlx5_wq_cyc_get_size(&sq->wq);
1022         size_t size;
1023
1024         size = array_size(wq_sz, sizeof(*sq->db.wqe_info));
1025         sq->db.wqe_info = kvzalloc_node(size, GFP_KERNEL, numa);
1026         if (!sq->db.wqe_info)
1027                 return -ENOMEM;
1028
1029         return 0;
1030 }
1031
1032 static void mlx5e_icosq_err_cqe_work(struct work_struct *recover_work)
1033 {
1034         struct mlx5e_icosq *sq = container_of(recover_work, struct mlx5e_icosq,
1035                                               recover_work);
1036
1037         mlx5e_reporter_icosq_cqe_err(sq);
1038 }
1039
1040 static int mlx5e_alloc_icosq(struct mlx5e_channel *c,
1041                              struct mlx5e_sq_param *param,
1042                              struct mlx5e_icosq *sq)
1043 {
1044         void *sqc_wq               = MLX5_ADDR_OF(sqc, param->sqc, wq);
1045         struct mlx5_core_dev *mdev = c->mdev;
1046         struct mlx5_wq_cyc *wq = &sq->wq;
1047         int err;
1048
1049         sq->channel   = c;
1050         sq->uar_map   = mdev->mlx5e_res.bfreg.map;
1051
1052         param->wq.db_numa_node = cpu_to_node(c->cpu);
1053         err = mlx5_wq_cyc_create(mdev, &param->wq, sqc_wq, wq, &sq->wq_ctrl);
1054         if (err)
1055                 return err;
1056         wq->db = &wq->db[MLX5_SND_DBR];
1057
1058         err = mlx5e_alloc_icosq_db(sq, cpu_to_node(c->cpu));
1059         if (err)
1060                 goto err_sq_wq_destroy;
1061
1062         INIT_WORK(&sq->recover_work, mlx5e_icosq_err_cqe_work);
1063
1064         return 0;
1065
1066 err_sq_wq_destroy:
1067         mlx5_wq_destroy(&sq->wq_ctrl);
1068
1069         return err;
1070 }
1071
1072 static void mlx5e_free_icosq(struct mlx5e_icosq *sq)
1073 {
1074         mlx5e_free_icosq_db(sq);
1075         mlx5_wq_destroy(&sq->wq_ctrl);
1076 }
1077
1078 static void mlx5e_free_txqsq_db(struct mlx5e_txqsq *sq)
1079 {
1080         kvfree(sq->db.wqe_info);
1081         kvfree(sq->db.dma_fifo);
1082 }
1083
1084 static int mlx5e_alloc_txqsq_db(struct mlx5e_txqsq *sq, int numa)
1085 {
1086         int wq_sz = mlx5_wq_cyc_get_size(&sq->wq);
1087         int df_sz = wq_sz * MLX5_SEND_WQEBB_NUM_DS;
1088
1089         sq->db.dma_fifo = kvzalloc_node(array_size(df_sz,
1090                                                    sizeof(*sq->db.dma_fifo)),
1091                                         GFP_KERNEL, numa);
1092         sq->db.wqe_info = kvzalloc_node(array_size(wq_sz,
1093                                                    sizeof(*sq->db.wqe_info)),
1094                                         GFP_KERNEL, numa);
1095         if (!sq->db.dma_fifo || !sq->db.wqe_info) {
1096                 mlx5e_free_txqsq_db(sq);
1097                 return -ENOMEM;
1098         }
1099
1100         sq->dma_fifo_mask = df_sz - 1;
1101
1102         return 0;
1103 }
1104
1105 static int mlx5e_calc_sq_stop_room(struct mlx5e_txqsq *sq, u8 log_sq_size)
1106 {
1107         int sq_size = 1 << log_sq_size;
1108
1109         sq->stop_room  = mlx5e_tls_get_stop_room(sq);
1110         sq->stop_room += mlx5e_stop_room_for_wqe(MLX5_SEND_WQE_MAX_WQEBBS);
1111
1112         if (WARN_ON(sq->stop_room >= sq_size)) {
1113                 netdev_err(sq->channel->netdev, "Stop room %hu is bigger than the SQ size %d\n",
1114                            sq->stop_room, sq_size);
1115                 return -ENOSPC;
1116         }
1117
1118         return 0;
1119 }
1120
1121 static void mlx5e_tx_err_cqe_work(struct work_struct *recover_work);
1122 static int mlx5e_alloc_txqsq(struct mlx5e_channel *c,
1123                              int txq_ix,
1124                              struct mlx5e_params *params,
1125                              struct mlx5e_sq_param *param,
1126                              struct mlx5e_txqsq *sq,
1127                              int tc)
1128 {
1129         void *sqc_wq               = MLX5_ADDR_OF(sqc, param->sqc, wq);
1130         struct mlx5_core_dev *mdev = c->mdev;
1131         struct mlx5_wq_cyc *wq = &sq->wq;
1132         int err;
1133
1134         sq->pdev      = c->pdev;
1135         sq->tstamp    = c->tstamp;
1136         sq->clock     = &mdev->clock;
1137         sq->mkey_be   = c->mkey_be;
1138         sq->channel   = c;
1139         sq->ch_ix     = c->ix;
1140         sq->txq_ix    = txq_ix;
1141         sq->uar_map   = mdev->mlx5e_res.bfreg.map;
1142         sq->min_inline_mode = params->tx_min_inline_mode;
1143         sq->hw_mtu    = MLX5E_SW2HW_MTU(params, params->sw_mtu);
1144         sq->stats     = &c->priv->channel_stats[c->ix].sq[tc];
1145         INIT_WORK(&sq->recover_work, mlx5e_tx_err_cqe_work);
1146         if (!MLX5_CAP_ETH(mdev, wqe_vlan_insert))
1147                 set_bit(MLX5E_SQ_STATE_VLAN_NEED_L2_INLINE, &sq->state);
1148         if (MLX5_IPSEC_DEV(c->priv->mdev))
1149                 set_bit(MLX5E_SQ_STATE_IPSEC, &sq->state);
1150         if (mlx5_accel_is_tls_device(c->priv->mdev))
1151                 set_bit(MLX5E_SQ_STATE_TLS, &sq->state);
1152         err = mlx5e_calc_sq_stop_room(sq, params->log_sq_size);
1153         if (err)
1154                 return err;
1155
1156         param->wq.db_numa_node = cpu_to_node(c->cpu);
1157         err = mlx5_wq_cyc_create(mdev, &param->wq, sqc_wq, wq, &sq->wq_ctrl);
1158         if (err)
1159                 return err;
1160         wq->db    = &wq->db[MLX5_SND_DBR];
1161
1162         err = mlx5e_alloc_txqsq_db(sq, cpu_to_node(c->cpu));
1163         if (err)
1164                 goto err_sq_wq_destroy;
1165
1166         INIT_WORK(&sq->dim.work, mlx5e_tx_dim_work);
1167         sq->dim.mode = params->tx_cq_moderation.cq_period_mode;
1168
1169         return 0;
1170
1171 err_sq_wq_destroy:
1172         mlx5_wq_destroy(&sq->wq_ctrl);
1173
1174         return err;
1175 }
1176
1177 static void mlx5e_free_txqsq(struct mlx5e_txqsq *sq)
1178 {
1179         mlx5e_free_txqsq_db(sq);
1180         mlx5_wq_destroy(&sq->wq_ctrl);
1181 }
1182
1183 struct mlx5e_create_sq_param {
1184         struct mlx5_wq_ctrl        *wq_ctrl;
1185         u32                         cqn;
1186         u32                         tisn;
1187         u8                          tis_lst_sz;
1188         u8                          min_inline_mode;
1189 };
1190
1191 static int mlx5e_create_sq(struct mlx5_core_dev *mdev,
1192                            struct mlx5e_sq_param *param,
1193                            struct mlx5e_create_sq_param *csp,
1194                            u32 *sqn)
1195 {
1196         void *in;
1197         void *sqc;
1198         void *wq;
1199         int inlen;
1200         int err;
1201
1202         inlen = MLX5_ST_SZ_BYTES(create_sq_in) +
1203                 sizeof(u64) * csp->wq_ctrl->buf.npages;
1204         in = kvzalloc(inlen, GFP_KERNEL);
1205         if (!in)
1206                 return -ENOMEM;
1207
1208         sqc = MLX5_ADDR_OF(create_sq_in, in, ctx);
1209         wq = MLX5_ADDR_OF(sqc, sqc, wq);
1210
1211         memcpy(sqc, param->sqc, sizeof(param->sqc));
1212         MLX5_SET(sqc,  sqc, tis_lst_sz, csp->tis_lst_sz);
1213         MLX5_SET(sqc,  sqc, tis_num_0, csp->tisn);
1214         MLX5_SET(sqc,  sqc, cqn, csp->cqn);
1215
1216         if (MLX5_CAP_ETH(mdev, wqe_inline_mode) == MLX5_CAP_INLINE_MODE_VPORT_CONTEXT)
1217                 MLX5_SET(sqc,  sqc, min_wqe_inline_mode, csp->min_inline_mode);
1218
1219         MLX5_SET(sqc,  sqc, state, MLX5_SQC_STATE_RST);
1220         MLX5_SET(sqc,  sqc, flush_in_error_en, 1);
1221
1222         MLX5_SET(wq,   wq, wq_type,       MLX5_WQ_TYPE_CYCLIC);
1223         MLX5_SET(wq,   wq, uar_page,      mdev->mlx5e_res.bfreg.index);
1224         MLX5_SET(wq,   wq, log_wq_pg_sz,  csp->wq_ctrl->buf.page_shift -
1225                                           MLX5_ADAPTER_PAGE_SHIFT);
1226         MLX5_SET64(wq, wq, dbr_addr,      csp->wq_ctrl->db.dma);
1227
1228         mlx5_fill_page_frag_array(&csp->wq_ctrl->buf,
1229                                   (__be64 *)MLX5_ADDR_OF(wq, wq, pas));
1230
1231         err = mlx5_core_create_sq(mdev, in, inlen, sqn);
1232
1233         kvfree(in);
1234
1235         return err;
1236 }
1237
1238 int mlx5e_modify_sq(struct mlx5_core_dev *mdev, u32 sqn,
1239                     struct mlx5e_modify_sq_param *p)
1240 {
1241         void *in;
1242         void *sqc;
1243         int inlen;
1244         int err;
1245
1246         inlen = MLX5_ST_SZ_BYTES(modify_sq_in);
1247         in = kvzalloc(inlen, GFP_KERNEL);
1248         if (!in)
1249                 return -ENOMEM;
1250
1251         sqc = MLX5_ADDR_OF(modify_sq_in, in, ctx);
1252
1253         MLX5_SET(modify_sq_in, in, sq_state, p->curr_state);
1254         MLX5_SET(sqc, sqc, state, p->next_state);
1255         if (p->rl_update && p->next_state == MLX5_SQC_STATE_RDY) {
1256                 MLX5_SET64(modify_sq_in, in, modify_bitmask, 1);
1257                 MLX5_SET(sqc,  sqc, packet_pacing_rate_limit_index, p->rl_index);
1258         }
1259
1260         err = mlx5_core_modify_sq(mdev, sqn, in);
1261
1262         kvfree(in);
1263
1264         return err;
1265 }
1266
1267 static void mlx5e_destroy_sq(struct mlx5_core_dev *mdev, u32 sqn)
1268 {
1269         mlx5_core_destroy_sq(mdev, sqn);
1270 }
1271
1272 static int mlx5e_create_sq_rdy(struct mlx5_core_dev *mdev,
1273                                struct mlx5e_sq_param *param,
1274                                struct mlx5e_create_sq_param *csp,
1275                                u32 *sqn)
1276 {
1277         struct mlx5e_modify_sq_param msp = {0};
1278         int err;
1279
1280         err = mlx5e_create_sq(mdev, param, csp, sqn);
1281         if (err)
1282                 return err;
1283
1284         msp.curr_state = MLX5_SQC_STATE_RST;
1285         msp.next_state = MLX5_SQC_STATE_RDY;
1286         err = mlx5e_modify_sq(mdev, *sqn, &msp);
1287         if (err)
1288                 mlx5e_destroy_sq(mdev, *sqn);
1289
1290         return err;
1291 }
1292
1293 static int mlx5e_set_sq_maxrate(struct net_device *dev,
1294                                 struct mlx5e_txqsq *sq, u32 rate);
1295
1296 static int mlx5e_open_txqsq(struct mlx5e_channel *c,
1297                             u32 tisn,
1298                             int txq_ix,
1299                             struct mlx5e_params *params,
1300                             struct mlx5e_sq_param *param,
1301                             struct mlx5e_txqsq *sq,
1302                             int tc)
1303 {
1304         struct mlx5e_create_sq_param csp = {};
1305         u32 tx_rate;
1306         int err;
1307
1308         err = mlx5e_alloc_txqsq(c, txq_ix, params, param, sq, tc);
1309         if (err)
1310                 return err;
1311
1312         csp.tisn            = tisn;
1313         csp.tis_lst_sz      = 1;
1314         csp.cqn             = sq->cq.mcq.cqn;
1315         csp.wq_ctrl         = &sq->wq_ctrl;
1316         csp.min_inline_mode = sq->min_inline_mode;
1317         err = mlx5e_create_sq_rdy(c->mdev, param, &csp, &sq->sqn);
1318         if (err)
1319                 goto err_free_txqsq;
1320
1321         tx_rate = c->priv->tx_rates[sq->txq_ix];
1322         if (tx_rate)
1323                 mlx5e_set_sq_maxrate(c->netdev, sq, tx_rate);
1324
1325         if (params->tx_dim_enabled)
1326                 sq->state |= BIT(MLX5E_SQ_STATE_AM);
1327
1328         return 0;
1329
1330 err_free_txqsq:
1331         mlx5e_free_txqsq(sq);
1332
1333         return err;
1334 }
1335
1336 void mlx5e_activate_txqsq(struct mlx5e_txqsq *sq)
1337 {
1338         sq->txq = netdev_get_tx_queue(sq->channel->netdev, sq->txq_ix);
1339         set_bit(MLX5E_SQ_STATE_ENABLED, &sq->state);
1340         netdev_tx_reset_queue(sq->txq);
1341         netif_tx_start_queue(sq->txq);
1342 }
1343
1344 void mlx5e_tx_disable_queue(struct netdev_queue *txq)
1345 {
1346         __netif_tx_lock_bh(txq);
1347         netif_tx_stop_queue(txq);
1348         __netif_tx_unlock_bh(txq);
1349 }
1350
1351 static void mlx5e_deactivate_txqsq(struct mlx5e_txqsq *sq)
1352 {
1353         struct mlx5e_channel *c = sq->channel;
1354         struct mlx5_wq_cyc *wq = &sq->wq;
1355
1356         clear_bit(MLX5E_SQ_STATE_ENABLED, &sq->state);
1357         /* prevent netif_tx_wake_queue */
1358         napi_synchronize(&c->napi);
1359
1360         mlx5e_tx_disable_queue(sq->txq);
1361
1362         /* last doorbell out, godspeed .. */
1363         if (mlx5e_wqc_has_room_for(wq, sq->cc, sq->pc, 1)) {
1364                 u16 pi = mlx5_wq_cyc_ctr2ix(wq, sq->pc);
1365                 struct mlx5e_tx_wqe *nop;
1366
1367                 sq->db.wqe_info[pi] = (struct mlx5e_tx_wqe_info) {
1368                         .num_wqebbs = 1,
1369                 };
1370
1371                 nop = mlx5e_post_nop(wq, sq->sqn, &sq->pc);
1372                 mlx5e_notify_hw(wq, sq->pc, sq->uar_map, &nop->ctrl);
1373         }
1374 }
1375
1376 static void mlx5e_close_txqsq(struct mlx5e_txqsq *sq)
1377 {
1378         struct mlx5e_channel *c = sq->channel;
1379         struct mlx5_core_dev *mdev = c->mdev;
1380         struct mlx5_rate_limit rl = {0};
1381
1382         cancel_work_sync(&sq->dim.work);
1383         cancel_work_sync(&sq->recover_work);
1384         mlx5e_destroy_sq(mdev, sq->sqn);
1385         if (sq->rate_limit) {
1386                 rl.rate = sq->rate_limit;
1387                 mlx5_rl_remove_rate(mdev, &rl);
1388         }
1389         mlx5e_free_txqsq_descs(sq);
1390         mlx5e_free_txqsq(sq);
1391 }
1392
1393 static void mlx5e_tx_err_cqe_work(struct work_struct *recover_work)
1394 {
1395         struct mlx5e_txqsq *sq = container_of(recover_work, struct mlx5e_txqsq,
1396                                               recover_work);
1397
1398         mlx5e_reporter_tx_err_cqe(sq);
1399 }
1400
1401 int mlx5e_open_icosq(struct mlx5e_channel *c, struct mlx5e_params *params,
1402                      struct mlx5e_sq_param *param, struct mlx5e_icosq *sq)
1403 {
1404         struct mlx5e_create_sq_param csp = {};
1405         int err;
1406
1407         err = mlx5e_alloc_icosq(c, param, sq);
1408         if (err)
1409                 return err;
1410
1411         csp.cqn             = sq->cq.mcq.cqn;
1412         csp.wq_ctrl         = &sq->wq_ctrl;
1413         csp.min_inline_mode = params->tx_min_inline_mode;
1414         err = mlx5e_create_sq_rdy(c->mdev, param, &csp, &sq->sqn);
1415         if (err)
1416                 goto err_free_icosq;
1417
1418         return 0;
1419
1420 err_free_icosq:
1421         mlx5e_free_icosq(sq);
1422
1423         return err;
1424 }
1425
1426 void mlx5e_activate_icosq(struct mlx5e_icosq *icosq)
1427 {
1428         set_bit(MLX5E_SQ_STATE_ENABLED, &icosq->state);
1429 }
1430
1431 void mlx5e_deactivate_icosq(struct mlx5e_icosq *icosq)
1432 {
1433         struct mlx5e_channel *c = icosq->channel;
1434
1435         clear_bit(MLX5E_SQ_STATE_ENABLED, &icosq->state);
1436         napi_synchronize(&c->napi);
1437 }
1438
1439 void mlx5e_close_icosq(struct mlx5e_icosq *sq)
1440 {
1441         struct mlx5e_channel *c = sq->channel;
1442
1443         mlx5e_destroy_sq(c->mdev, sq->sqn);
1444         mlx5e_free_icosq(sq);
1445 }
1446
1447 int mlx5e_open_xdpsq(struct mlx5e_channel *c, struct mlx5e_params *params,
1448                      struct mlx5e_sq_param *param, struct xdp_umem *umem,
1449                      struct mlx5e_xdpsq *sq, bool is_redirect)
1450 {
1451         struct mlx5e_create_sq_param csp = {};
1452         int err;
1453
1454         err = mlx5e_alloc_xdpsq(c, params, umem, param, sq, is_redirect);
1455         if (err)
1456                 return err;
1457
1458         csp.tis_lst_sz      = 1;
1459         csp.tisn            = c->priv->tisn[c->lag_port][0]; /* tc = 0 */
1460         csp.cqn             = sq->cq.mcq.cqn;
1461         csp.wq_ctrl         = &sq->wq_ctrl;
1462         csp.min_inline_mode = sq->min_inline_mode;
1463         set_bit(MLX5E_SQ_STATE_ENABLED, &sq->state);
1464         err = mlx5e_create_sq_rdy(c->mdev, param, &csp, &sq->sqn);
1465         if (err)
1466                 goto err_free_xdpsq;
1467
1468         mlx5e_set_xmit_fp(sq, param->is_mpw);
1469
1470         if (!param->is_mpw) {
1471                 unsigned int ds_cnt = MLX5E_XDP_TX_DS_COUNT;
1472                 unsigned int inline_hdr_sz = 0;
1473                 int i;
1474
1475                 if (sq->min_inline_mode != MLX5_INLINE_MODE_NONE) {
1476                         inline_hdr_sz = MLX5E_XDP_MIN_INLINE;
1477                         ds_cnt++;
1478                 }
1479
1480                 /* Pre initialize fixed WQE fields */
1481                 for (i = 0; i < mlx5_wq_cyc_get_size(&sq->wq); i++) {
1482                         struct mlx5e_tx_wqe      *wqe  = mlx5_wq_cyc_get_wqe(&sq->wq, i);
1483                         struct mlx5_wqe_ctrl_seg *cseg = &wqe->ctrl;
1484                         struct mlx5_wqe_eth_seg  *eseg = &wqe->eth;
1485                         struct mlx5_wqe_data_seg *dseg;
1486
1487                         sq->db.wqe_info[i] = (struct mlx5e_xdp_wqe_info) {
1488                                 .num_wqebbs = 1,
1489                                 .num_pkts   = 1,
1490                         };
1491
1492                         cseg->qpn_ds = cpu_to_be32((sq->sqn << 8) | ds_cnt);
1493                         eseg->inline_hdr.sz = cpu_to_be16(inline_hdr_sz);
1494
1495                         dseg = (struct mlx5_wqe_data_seg *)cseg + (ds_cnt - 1);
1496                         dseg->lkey = sq->mkey_be;
1497                 }
1498         }
1499
1500         return 0;
1501
1502 err_free_xdpsq:
1503         clear_bit(MLX5E_SQ_STATE_ENABLED, &sq->state);
1504         mlx5e_free_xdpsq(sq);
1505
1506         return err;
1507 }
1508
1509 void mlx5e_close_xdpsq(struct mlx5e_xdpsq *sq)
1510 {
1511         struct mlx5e_channel *c = sq->channel;
1512
1513         clear_bit(MLX5E_SQ_STATE_ENABLED, &sq->state);
1514         napi_synchronize(&c->napi);
1515
1516         mlx5e_destroy_sq(c->mdev, sq->sqn);
1517         mlx5e_free_xdpsq_descs(sq);
1518         mlx5e_free_xdpsq(sq);
1519 }
1520
1521 static int mlx5e_alloc_cq_common(struct mlx5_core_dev *mdev,
1522                                  struct mlx5e_cq_param *param,
1523                                  struct mlx5e_cq *cq)
1524 {
1525         struct mlx5_core_cq *mcq = &cq->mcq;
1526         int eqn_not_used;
1527         unsigned int irqn;
1528         int err;
1529         u32 i;
1530
1531         err = mlx5_vector2eqn(mdev, param->eq_ix, &eqn_not_used, &irqn);
1532         if (err)
1533                 return err;
1534
1535         err = mlx5_cqwq_create(mdev, &param->wq, param->cqc, &cq->wq,
1536                                &cq->wq_ctrl);
1537         if (err)
1538                 return err;
1539
1540         mcq->cqe_sz     = 64;
1541         mcq->set_ci_db  = cq->wq_ctrl.db.db;
1542         mcq->arm_db     = cq->wq_ctrl.db.db + 1;
1543         *mcq->set_ci_db = 0;
1544         *mcq->arm_db    = 0;
1545         mcq->vector     = param->eq_ix;
1546         mcq->comp       = mlx5e_completion_event;
1547         mcq->event      = mlx5e_cq_error_event;
1548         mcq->irqn       = irqn;
1549
1550         for (i = 0; i < mlx5_cqwq_get_size(&cq->wq); i++) {
1551                 struct mlx5_cqe64 *cqe = mlx5_cqwq_get_wqe(&cq->wq, i);
1552
1553                 cqe->op_own = 0xf1;
1554         }
1555
1556         cq->mdev = mdev;
1557
1558         return 0;
1559 }
1560
1561 static int mlx5e_alloc_cq(struct mlx5e_channel *c,
1562                           struct mlx5e_cq_param *param,
1563                           struct mlx5e_cq *cq)
1564 {
1565         struct mlx5_core_dev *mdev = c->priv->mdev;
1566         int err;
1567
1568         param->wq.buf_numa_node = cpu_to_node(c->cpu);
1569         param->wq.db_numa_node  = cpu_to_node(c->cpu);
1570         param->eq_ix   = c->ix;
1571
1572         err = mlx5e_alloc_cq_common(mdev, param, cq);
1573
1574         cq->napi    = &c->napi;
1575         cq->channel = c;
1576
1577         return err;
1578 }
1579
1580 static void mlx5e_free_cq(struct mlx5e_cq *cq)
1581 {
1582         mlx5_wq_destroy(&cq->wq_ctrl);
1583 }
1584
1585 static int mlx5e_create_cq(struct mlx5e_cq *cq, struct mlx5e_cq_param *param)
1586 {
1587         u32 out[MLX5_ST_SZ_DW(create_cq_out)];
1588         struct mlx5_core_dev *mdev = cq->mdev;
1589         struct mlx5_core_cq *mcq = &cq->mcq;
1590
1591         void *in;
1592         void *cqc;
1593         int inlen;
1594         unsigned int irqn_not_used;
1595         int eqn;
1596         int err;
1597
1598         err = mlx5_vector2eqn(mdev, param->eq_ix, &eqn, &irqn_not_used);
1599         if (err)
1600                 return err;
1601
1602         inlen = MLX5_ST_SZ_BYTES(create_cq_in) +
1603                 sizeof(u64) * cq->wq_ctrl.buf.npages;
1604         in = kvzalloc(inlen, GFP_KERNEL);
1605         if (!in)
1606                 return -ENOMEM;
1607
1608         cqc = MLX5_ADDR_OF(create_cq_in, in, cq_context);
1609
1610         memcpy(cqc, param->cqc, sizeof(param->cqc));
1611
1612         mlx5_fill_page_frag_array(&cq->wq_ctrl.buf,
1613                                   (__be64 *)MLX5_ADDR_OF(create_cq_in, in, pas));
1614
1615         MLX5_SET(cqc,   cqc, cq_period_mode, param->cq_period_mode);
1616         MLX5_SET(cqc,   cqc, c_eqn,         eqn);
1617         MLX5_SET(cqc,   cqc, uar_page,      mdev->priv.uar->index);
1618         MLX5_SET(cqc,   cqc, log_page_size, cq->wq_ctrl.buf.page_shift -
1619                                             MLX5_ADAPTER_PAGE_SHIFT);
1620         MLX5_SET64(cqc, cqc, dbr_addr,      cq->wq_ctrl.db.dma);
1621
1622         err = mlx5_core_create_cq(mdev, mcq, in, inlen, out, sizeof(out));
1623
1624         kvfree(in);
1625
1626         if (err)
1627                 return err;
1628
1629         mlx5e_cq_arm(cq);
1630
1631         return 0;
1632 }
1633
1634 static void mlx5e_destroy_cq(struct mlx5e_cq *cq)
1635 {
1636         mlx5_core_destroy_cq(cq->mdev, &cq->mcq);
1637 }
1638
1639 int mlx5e_open_cq(struct mlx5e_channel *c, struct dim_cq_moder moder,
1640                   struct mlx5e_cq_param *param, struct mlx5e_cq *cq)
1641 {
1642         struct mlx5_core_dev *mdev = c->mdev;
1643         int err;
1644
1645         err = mlx5e_alloc_cq(c, param, cq);
1646         if (err)
1647                 return err;
1648
1649         err = mlx5e_create_cq(cq, param);
1650         if (err)
1651                 goto err_free_cq;
1652
1653         if (MLX5_CAP_GEN(mdev, cq_moderation))
1654                 mlx5_core_modify_cq_moderation(mdev, &cq->mcq, moder.usec, moder.pkts);
1655         return 0;
1656
1657 err_free_cq:
1658         mlx5e_free_cq(cq);
1659
1660         return err;
1661 }
1662
1663 void mlx5e_close_cq(struct mlx5e_cq *cq)
1664 {
1665         mlx5e_destroy_cq(cq);
1666         mlx5e_free_cq(cq);
1667 }
1668
1669 static int mlx5e_open_tx_cqs(struct mlx5e_channel *c,
1670                              struct mlx5e_params *params,
1671                              struct mlx5e_channel_param *cparam)
1672 {
1673         int err;
1674         int tc;
1675
1676         for (tc = 0; tc < c->num_tc; tc++) {
1677                 err = mlx5e_open_cq(c, params->tx_cq_moderation,
1678                                     &cparam->tx_cq, &c->sq[tc].cq);
1679                 if (err)
1680                         goto err_close_tx_cqs;
1681         }
1682
1683         return 0;
1684
1685 err_close_tx_cqs:
1686         for (tc--; tc >= 0; tc--)
1687                 mlx5e_close_cq(&c->sq[tc].cq);
1688
1689         return err;
1690 }
1691
1692 static void mlx5e_close_tx_cqs(struct mlx5e_channel *c)
1693 {
1694         int tc;
1695
1696         for (tc = 0; tc < c->num_tc; tc++)
1697                 mlx5e_close_cq(&c->sq[tc].cq);
1698 }
1699
1700 static int mlx5e_open_sqs(struct mlx5e_channel *c,
1701                           struct mlx5e_params *params,
1702                           struct mlx5e_channel_param *cparam)
1703 {
1704         int err, tc;
1705
1706         for (tc = 0; tc < params->num_tc; tc++) {
1707                 int txq_ix = c->ix + tc * params->num_channels;
1708
1709                 err = mlx5e_open_txqsq(c, c->priv->tisn[c->lag_port][tc], txq_ix,
1710                                        params, &cparam->sq, &c->sq[tc], tc);
1711                 if (err)
1712                         goto err_close_sqs;
1713         }
1714
1715         return 0;
1716
1717 err_close_sqs:
1718         for (tc--; tc >= 0; tc--)
1719                 mlx5e_close_txqsq(&c->sq[tc]);
1720
1721         return err;
1722 }
1723
1724 static void mlx5e_close_sqs(struct mlx5e_channel *c)
1725 {
1726         int tc;
1727
1728         for (tc = 0; tc < c->num_tc; tc++)
1729                 mlx5e_close_txqsq(&c->sq[tc]);
1730 }
1731
1732 static int mlx5e_set_sq_maxrate(struct net_device *dev,
1733                                 struct mlx5e_txqsq *sq, u32 rate)
1734 {
1735         struct mlx5e_priv *priv = netdev_priv(dev);
1736         struct mlx5_core_dev *mdev = priv->mdev;
1737         struct mlx5e_modify_sq_param msp = {0};
1738         struct mlx5_rate_limit rl = {0};
1739         u16 rl_index = 0;
1740         int err;
1741
1742         if (rate == sq->rate_limit)
1743                 /* nothing to do */
1744                 return 0;
1745
1746         if (sq->rate_limit) {
1747                 rl.rate = sq->rate_limit;
1748                 /* remove current rl index to free space to next ones */
1749                 mlx5_rl_remove_rate(mdev, &rl);
1750         }
1751
1752         sq->rate_limit = 0;
1753
1754         if (rate) {
1755                 rl.rate = rate;
1756                 err = mlx5_rl_add_rate(mdev, &rl_index, &rl);
1757                 if (err) {
1758                         netdev_err(dev, "Failed configuring rate %u: %d\n",
1759                                    rate, err);
1760                         return err;
1761                 }
1762         }
1763
1764         msp.curr_state = MLX5_SQC_STATE_RDY;
1765         msp.next_state = MLX5_SQC_STATE_RDY;
1766         msp.rl_index   = rl_index;
1767         msp.rl_update  = true;
1768         err = mlx5e_modify_sq(mdev, sq->sqn, &msp);
1769         if (err) {
1770                 netdev_err(dev, "Failed configuring rate %u: %d\n",
1771                            rate, err);
1772                 /* remove the rate from the table */
1773                 if (rate)
1774                         mlx5_rl_remove_rate(mdev, &rl);
1775                 return err;
1776         }
1777
1778         sq->rate_limit = rate;
1779         return 0;
1780 }
1781
1782 static int mlx5e_set_tx_maxrate(struct net_device *dev, int index, u32 rate)
1783 {
1784         struct mlx5e_priv *priv = netdev_priv(dev);
1785         struct mlx5_core_dev *mdev = priv->mdev;
1786         struct mlx5e_txqsq *sq = priv->txq2sq[index];
1787         int err = 0;
1788
1789         if (!mlx5_rl_is_supported(mdev)) {
1790                 netdev_err(dev, "Rate limiting is not supported on this device\n");
1791                 return -EINVAL;
1792         }
1793
1794         /* rate is given in Mb/sec, HW config is in Kb/sec */
1795         rate = rate << 10;
1796
1797         /* Check whether rate in valid range, 0 is always valid */
1798         if (rate && !mlx5_rl_is_in_range(mdev, rate)) {
1799                 netdev_err(dev, "TX rate %u, is not in range\n", rate);
1800                 return -ERANGE;
1801         }
1802
1803         mutex_lock(&priv->state_lock);
1804         if (test_bit(MLX5E_STATE_OPENED, &priv->state))
1805                 err = mlx5e_set_sq_maxrate(dev, sq, rate);
1806         if (!err)
1807                 priv->tx_rates[index] = rate;
1808         mutex_unlock(&priv->state_lock);
1809
1810         return err;
1811 }
1812
1813 static int mlx5e_open_queues(struct mlx5e_channel *c,
1814                              struct mlx5e_params *params,
1815                              struct mlx5e_channel_param *cparam)
1816 {
1817         struct dim_cq_moder icocq_moder = {0, 0};
1818         int err;
1819
1820         err = mlx5e_open_cq(c, icocq_moder, &cparam->icosq_cq, &c->icosq.cq);
1821         if (err)
1822                 return err;
1823
1824         err = mlx5e_open_tx_cqs(c, params, cparam);
1825         if (err)
1826                 goto err_close_icosq_cq;
1827
1828         err = mlx5e_open_cq(c, params->tx_cq_moderation, &cparam->tx_cq, &c->xdpsq.cq);
1829         if (err)
1830                 goto err_close_tx_cqs;
1831
1832         err = mlx5e_open_cq(c, params->rx_cq_moderation, &cparam->rx_cq, &c->rq.cq);
1833         if (err)
1834                 goto err_close_xdp_tx_cqs;
1835
1836         /* XDP SQ CQ params are same as normal TXQ sq CQ params */
1837         err = c->xdp ? mlx5e_open_cq(c, params->tx_cq_moderation,
1838                                      &cparam->tx_cq, &c->rq_xdpsq.cq) : 0;
1839         if (err)
1840                 goto err_close_rx_cq;
1841
1842         napi_enable(&c->napi);
1843
1844         err = mlx5e_open_icosq(c, params, &cparam->icosq, &c->icosq);
1845         if (err)
1846                 goto err_disable_napi;
1847
1848         err = mlx5e_open_sqs(c, params, cparam);
1849         if (err)
1850                 goto err_close_icosq;
1851
1852         if (c->xdp) {
1853                 err = mlx5e_open_xdpsq(c, params, &cparam->xdp_sq, NULL,
1854                                        &c->rq_xdpsq, false);
1855                 if (err)
1856                         goto err_close_sqs;
1857         }
1858
1859         err = mlx5e_open_rq(c, params, &cparam->rq, NULL, NULL, &c->rq);
1860         if (err)
1861                 goto err_close_xdp_sq;
1862
1863         err = mlx5e_open_xdpsq(c, params, &cparam->xdp_sq, NULL, &c->xdpsq, true);
1864         if (err)
1865                 goto err_close_rq;
1866
1867         return 0;
1868
1869 err_close_rq:
1870         mlx5e_close_rq(&c->rq);
1871
1872 err_close_xdp_sq:
1873         if (c->xdp)
1874                 mlx5e_close_xdpsq(&c->rq_xdpsq);
1875
1876 err_close_sqs:
1877         mlx5e_close_sqs(c);
1878
1879 err_close_icosq:
1880         mlx5e_close_icosq(&c->icosq);
1881
1882 err_disable_napi:
1883         napi_disable(&c->napi);
1884
1885         if (c->xdp)
1886                 mlx5e_close_cq(&c->rq_xdpsq.cq);
1887
1888 err_close_rx_cq:
1889         mlx5e_close_cq(&c->rq.cq);
1890
1891 err_close_xdp_tx_cqs:
1892         mlx5e_close_cq(&c->xdpsq.cq);
1893
1894 err_close_tx_cqs:
1895         mlx5e_close_tx_cqs(c);
1896
1897 err_close_icosq_cq:
1898         mlx5e_close_cq(&c->icosq.cq);
1899
1900         return err;
1901 }
1902
1903 static void mlx5e_close_queues(struct mlx5e_channel *c)
1904 {
1905         mlx5e_close_xdpsq(&c->xdpsq);
1906         mlx5e_close_rq(&c->rq);
1907         if (c->xdp)
1908                 mlx5e_close_xdpsq(&c->rq_xdpsq);
1909         mlx5e_close_sqs(c);
1910         mlx5e_close_icosq(&c->icosq);
1911         napi_disable(&c->napi);
1912         if (c->xdp)
1913                 mlx5e_close_cq(&c->rq_xdpsq.cq);
1914         mlx5e_close_cq(&c->rq.cq);
1915         mlx5e_close_cq(&c->xdpsq.cq);
1916         mlx5e_close_tx_cqs(c);
1917         mlx5e_close_cq(&c->icosq.cq);
1918 }
1919
1920 static u8 mlx5e_enumerate_lag_port(struct mlx5_core_dev *mdev, int ix)
1921 {
1922         u16 port_aff_bias = mlx5_core_is_pf(mdev) ? 0 : MLX5_CAP_GEN(mdev, vhca_id);
1923
1924         return (ix + port_aff_bias) % mlx5e_get_num_lag_ports(mdev);
1925 }
1926
1927 static int mlx5e_open_channel(struct mlx5e_priv *priv, int ix,
1928                               struct mlx5e_params *params,
1929                               struct mlx5e_channel_param *cparam,
1930                               struct xdp_umem *umem,
1931                               struct mlx5e_channel **cp)
1932 {
1933         int cpu = cpumask_first(mlx5_comp_irq_get_affinity_mask(priv->mdev, ix));
1934         struct net_device *netdev = priv->netdev;
1935         struct mlx5e_xsk_param xsk;
1936         struct mlx5e_channel *c;
1937         unsigned int irq;
1938         int err;
1939         int eqn;
1940
1941         err = mlx5_vector2eqn(priv->mdev, ix, &eqn, &irq);
1942         if (err)
1943                 return err;
1944
1945         c = kvzalloc_node(sizeof(*c), GFP_KERNEL, cpu_to_node(cpu));
1946         if (!c)
1947                 return -ENOMEM;
1948
1949         c->priv     = priv;
1950         c->mdev     = priv->mdev;
1951         c->tstamp   = &priv->tstamp;
1952         c->ix       = ix;
1953         c->cpu      = cpu;
1954         c->pdev     = priv->mdev->device;
1955         c->netdev   = priv->netdev;
1956         c->mkey_be  = cpu_to_be32(priv->mdev->mlx5e_res.mkey.key);
1957         c->num_tc   = params->num_tc;
1958         c->xdp      = !!params->xdp_prog;
1959         c->stats    = &priv->channel_stats[ix].ch;
1960         c->irq_desc = irq_to_desc(irq);
1961         c->lag_port = mlx5e_enumerate_lag_port(priv->mdev, ix);
1962
1963         netif_napi_add(netdev, &c->napi, mlx5e_napi_poll, 64);
1964
1965         err = mlx5e_open_queues(c, params, cparam);
1966         if (unlikely(err))
1967                 goto err_napi_del;
1968
1969         if (umem) {
1970                 mlx5e_build_xsk_param(umem, &xsk);
1971                 err = mlx5e_open_xsk(priv, params, &xsk, umem, c);
1972                 if (unlikely(err))
1973                         goto err_close_queues;
1974         }
1975
1976         *cp = c;
1977
1978         return 0;
1979
1980 err_close_queues:
1981         mlx5e_close_queues(c);
1982
1983 err_napi_del:
1984         netif_napi_del(&c->napi);
1985
1986         kvfree(c);
1987
1988         return err;
1989 }
1990
1991 static void mlx5e_activate_channel(struct mlx5e_channel *c)
1992 {
1993         int tc;
1994
1995         for (tc = 0; tc < c->num_tc; tc++)
1996                 mlx5e_activate_txqsq(&c->sq[tc]);
1997         mlx5e_activate_icosq(&c->icosq);
1998         mlx5e_activate_rq(&c->rq);
1999
2000         if (test_bit(MLX5E_CHANNEL_STATE_XSK, c->state))
2001                 mlx5e_activate_xsk(c);
2002 }
2003
2004 static void mlx5e_deactivate_channel(struct mlx5e_channel *c)
2005 {
2006         int tc;
2007
2008         if (test_bit(MLX5E_CHANNEL_STATE_XSK, c->state))
2009                 mlx5e_deactivate_xsk(c);
2010
2011         mlx5e_deactivate_rq(&c->rq);
2012         mlx5e_deactivate_icosq(&c->icosq);
2013         for (tc = 0; tc < c->num_tc; tc++)
2014                 mlx5e_deactivate_txqsq(&c->sq[tc]);
2015 }
2016
2017 static void mlx5e_close_channel(struct mlx5e_channel *c)
2018 {
2019         if (test_bit(MLX5E_CHANNEL_STATE_XSK, c->state))
2020                 mlx5e_close_xsk(c);
2021         mlx5e_close_queues(c);
2022         netif_napi_del(&c->napi);
2023
2024         kvfree(c);
2025 }
2026
2027 #define DEFAULT_FRAG_SIZE (2048)
2028
2029 static void mlx5e_build_rq_frags_info(struct mlx5_core_dev *mdev,
2030                                       struct mlx5e_params *params,
2031                                       struct mlx5e_xsk_param *xsk,
2032                                       struct mlx5e_rq_frags_info *info)
2033 {
2034         u32 byte_count = MLX5E_SW2HW_MTU(params, params->sw_mtu);
2035         int frag_size_max = DEFAULT_FRAG_SIZE;
2036         u32 buf_size = 0;
2037         int i;
2038
2039 #ifdef CONFIG_MLX5_EN_IPSEC
2040         if (MLX5_IPSEC_DEV(mdev))
2041                 byte_count += MLX5E_METADATA_ETHER_LEN;
2042 #endif
2043
2044         if (mlx5e_rx_is_linear_skb(params, xsk)) {
2045                 int frag_stride;
2046
2047                 frag_stride = mlx5e_rx_get_linear_frag_sz(params, xsk);
2048                 frag_stride = roundup_pow_of_two(frag_stride);
2049
2050                 info->arr[0].frag_size = byte_count;
2051                 info->arr[0].frag_stride = frag_stride;
2052                 info->num_frags = 1;
2053                 info->wqe_bulk = PAGE_SIZE / frag_stride;
2054                 goto out;
2055         }
2056
2057         if (byte_count > PAGE_SIZE +
2058             (MLX5E_MAX_RX_FRAGS - 1) * frag_size_max)
2059                 frag_size_max = PAGE_SIZE;
2060
2061         i = 0;
2062         while (buf_size < byte_count) {
2063                 int frag_size = byte_count - buf_size;
2064
2065                 if (i < MLX5E_MAX_RX_FRAGS - 1)
2066                         frag_size = min(frag_size, frag_size_max);
2067
2068                 info->arr[i].frag_size = frag_size;
2069                 info->arr[i].frag_stride = roundup_pow_of_two(frag_size);
2070
2071                 buf_size += frag_size;
2072                 i++;
2073         }
2074         info->num_frags = i;
2075         /* number of different wqes sharing a page */
2076         info->wqe_bulk = 1 + (info->num_frags % 2);
2077
2078 out:
2079         info->wqe_bulk = max_t(u8, info->wqe_bulk, 8);
2080         info->log_num_frags = order_base_2(info->num_frags);
2081 }
2082
2083 static inline u8 mlx5e_get_rqwq_log_stride(u8 wq_type, int ndsegs)
2084 {
2085         int sz = sizeof(struct mlx5_wqe_data_seg) * ndsegs;
2086
2087         switch (wq_type) {
2088         case MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ:
2089                 sz += sizeof(struct mlx5e_rx_wqe_ll);
2090                 break;
2091         default: /* MLX5_WQ_TYPE_CYCLIC */
2092                 sz += sizeof(struct mlx5e_rx_wqe_cyc);
2093         }
2094
2095         return order_base_2(sz);
2096 }
2097
2098 static u8 mlx5e_get_rq_log_wq_sz(void *rqc)
2099 {
2100         void *wq = MLX5_ADDR_OF(rqc, rqc, wq);
2101
2102         return MLX5_GET(wq, wq, log_wq_sz);
2103 }
2104
2105 void mlx5e_build_rq_param(struct mlx5e_priv *priv,
2106                           struct mlx5e_params *params,
2107                           struct mlx5e_xsk_param *xsk,
2108                           struct mlx5e_rq_param *param)
2109 {
2110         struct mlx5_core_dev *mdev = priv->mdev;
2111         void *rqc = param->rqc;
2112         void *wq = MLX5_ADDR_OF(rqc, rqc, wq);
2113         int ndsegs = 1;
2114
2115         switch (params->rq_wq_type) {
2116         case MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ:
2117                 MLX5_SET(wq, wq, log_wqe_num_of_strides,
2118                          mlx5e_mpwqe_get_log_num_strides(mdev, params, xsk) -
2119                          MLX5_MPWQE_LOG_NUM_STRIDES_BASE);
2120                 MLX5_SET(wq, wq, log_wqe_stride_size,
2121                          mlx5e_mpwqe_get_log_stride_size(mdev, params, xsk) -
2122                          MLX5_MPWQE_LOG_STRIDE_SZ_BASE);
2123                 MLX5_SET(wq, wq, log_wq_sz, mlx5e_mpwqe_get_log_rq_size(params, xsk));
2124                 break;
2125         default: /* MLX5_WQ_TYPE_CYCLIC */
2126                 MLX5_SET(wq, wq, log_wq_sz, params->log_rq_mtu_frames);
2127                 mlx5e_build_rq_frags_info(mdev, params, xsk, &param->frags_info);
2128                 ndsegs = param->frags_info.num_frags;
2129         }
2130
2131         MLX5_SET(wq, wq, wq_type,          params->rq_wq_type);
2132         MLX5_SET(wq, wq, end_padding_mode, MLX5_WQ_END_PAD_MODE_ALIGN);
2133         MLX5_SET(wq, wq, log_wq_stride,
2134                  mlx5e_get_rqwq_log_stride(params->rq_wq_type, ndsegs));
2135         MLX5_SET(wq, wq, pd,               mdev->mlx5e_res.pdn);
2136         MLX5_SET(rqc, rqc, counter_set_id, priv->q_counter);
2137         MLX5_SET(rqc, rqc, vsd,            params->vlan_strip_disable);
2138         MLX5_SET(rqc, rqc, scatter_fcs,    params->scatter_fcs_en);
2139
2140         param->wq.buf_numa_node = dev_to_node(mdev->device);
2141 }
2142
2143 static void mlx5e_build_drop_rq_param(struct mlx5e_priv *priv,
2144                                       struct mlx5e_rq_param *param)
2145 {
2146         struct mlx5_core_dev *mdev = priv->mdev;
2147         void *rqc = param->rqc;
2148         void *wq = MLX5_ADDR_OF(rqc, rqc, wq);
2149
2150         MLX5_SET(wq, wq, wq_type, MLX5_WQ_TYPE_CYCLIC);
2151         MLX5_SET(wq, wq, log_wq_stride,
2152                  mlx5e_get_rqwq_log_stride(MLX5_WQ_TYPE_CYCLIC, 1));
2153         MLX5_SET(rqc, rqc, counter_set_id, priv->drop_rq_q_counter);
2154
2155         param->wq.buf_numa_node = dev_to_node(mdev->device);
2156 }
2157
2158 void mlx5e_build_sq_param_common(struct mlx5e_priv *priv,
2159                                  struct mlx5e_sq_param *param)
2160 {
2161         void *sqc = param->sqc;
2162         void *wq = MLX5_ADDR_OF(sqc, sqc, wq);
2163
2164         MLX5_SET(wq, wq, log_wq_stride, ilog2(MLX5_SEND_WQE_BB));
2165         MLX5_SET(wq, wq, pd,            priv->mdev->mlx5e_res.pdn);
2166
2167         param->wq.buf_numa_node = dev_to_node(priv->mdev->device);
2168 }
2169
2170 static void mlx5e_build_sq_param(struct mlx5e_priv *priv,
2171                                  struct mlx5e_params *params,
2172                                  struct mlx5e_sq_param *param)
2173 {
2174         void *sqc = param->sqc;
2175         void *wq = MLX5_ADDR_OF(sqc, sqc, wq);
2176         bool allow_swp;
2177
2178         allow_swp = mlx5_geneve_tx_allowed(priv->mdev) ||
2179                     !!MLX5_IPSEC_DEV(priv->mdev);
2180         mlx5e_build_sq_param_common(priv, param);
2181         MLX5_SET(wq, wq, log_wq_sz, params->log_sq_size);
2182         MLX5_SET(sqc, sqc, allow_swp, allow_swp);
2183 }
2184
2185 static void mlx5e_build_common_cq_param(struct mlx5e_priv *priv,
2186                                         struct mlx5e_cq_param *param)
2187 {
2188         void *cqc = param->cqc;
2189
2190         MLX5_SET(cqc, cqc, uar_page, priv->mdev->priv.uar->index);
2191         if (MLX5_CAP_GEN(priv->mdev, cqe_128_always) && cache_line_size() >= 128)
2192                 MLX5_SET(cqc, cqc, cqe_sz, CQE_STRIDE_128_PAD);
2193 }
2194
2195 void mlx5e_build_rx_cq_param(struct mlx5e_priv *priv,
2196                              struct mlx5e_params *params,
2197                              struct mlx5e_xsk_param *xsk,
2198                              struct mlx5e_cq_param *param)
2199 {
2200         struct mlx5_core_dev *mdev = priv->mdev;
2201         void *cqc = param->cqc;
2202         u8 log_cq_size;
2203
2204         switch (params->rq_wq_type) {
2205         case MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ:
2206                 log_cq_size = mlx5e_mpwqe_get_log_rq_size(params, xsk) +
2207                         mlx5e_mpwqe_get_log_num_strides(mdev, params, xsk);
2208                 break;
2209         default: /* MLX5_WQ_TYPE_CYCLIC */
2210                 log_cq_size = params->log_rq_mtu_frames;
2211         }
2212
2213         MLX5_SET(cqc, cqc, log_cq_size, log_cq_size);
2214         if (MLX5E_GET_PFLAG(params, MLX5E_PFLAG_RX_CQE_COMPRESS)) {
2215                 MLX5_SET(cqc, cqc, mini_cqe_res_format, MLX5_CQE_FORMAT_CSUM);
2216                 MLX5_SET(cqc, cqc, cqe_comp_en, 1);
2217         }
2218
2219         mlx5e_build_common_cq_param(priv, param);
2220         param->cq_period_mode = params->rx_cq_moderation.cq_period_mode;
2221 }
2222
2223 void mlx5e_build_tx_cq_param(struct mlx5e_priv *priv,
2224                              struct mlx5e_params *params,
2225                              struct mlx5e_cq_param *param)
2226 {
2227         void *cqc = param->cqc;
2228
2229         MLX5_SET(cqc, cqc, log_cq_size, params->log_sq_size);
2230
2231         mlx5e_build_common_cq_param(priv, param);
2232         param->cq_period_mode = params->tx_cq_moderation.cq_period_mode;
2233 }
2234
2235 void mlx5e_build_ico_cq_param(struct mlx5e_priv *priv,
2236                               u8 log_wq_size,
2237                               struct mlx5e_cq_param *param)
2238 {
2239         void *cqc = param->cqc;
2240
2241         MLX5_SET(cqc, cqc, log_cq_size, log_wq_size);
2242
2243         mlx5e_build_common_cq_param(priv, param);
2244
2245         param->cq_period_mode = DIM_CQ_PERIOD_MODE_START_FROM_EQE;
2246 }
2247
2248 void mlx5e_build_icosq_param(struct mlx5e_priv *priv,
2249                              u8 log_wq_size,
2250                              struct mlx5e_sq_param *param)
2251 {
2252         void *sqc = param->sqc;
2253         void *wq = MLX5_ADDR_OF(sqc, sqc, wq);
2254
2255         mlx5e_build_sq_param_common(priv, param);
2256
2257         MLX5_SET(wq, wq, log_wq_sz, log_wq_size);
2258         MLX5_SET(sqc, sqc, reg_umr, MLX5_CAP_ETH(priv->mdev, reg_umr_sq));
2259 }
2260
2261 void mlx5e_build_xdpsq_param(struct mlx5e_priv *priv,
2262                              struct mlx5e_params *params,
2263                              struct mlx5e_sq_param *param)
2264 {
2265         void *sqc = param->sqc;
2266         void *wq = MLX5_ADDR_OF(sqc, sqc, wq);
2267
2268         mlx5e_build_sq_param_common(priv, param);
2269         MLX5_SET(wq, wq, log_wq_sz, params->log_sq_size);
2270         param->is_mpw = MLX5E_GET_PFLAG(params, MLX5E_PFLAG_XDP_TX_MPWQE);
2271 }
2272
2273 static u8 mlx5e_build_icosq_log_wq_sz(struct mlx5e_params *params,
2274                                       struct mlx5e_rq_param *rqp)
2275 {
2276         switch (params->rq_wq_type) {
2277         case MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ:
2278                 return order_base_2(MLX5E_UMR_WQEBBS) +
2279                         mlx5e_get_rq_log_wq_sz(rqp->rqc);
2280         default: /* MLX5_WQ_TYPE_CYCLIC */
2281                 return MLX5E_PARAMS_MINIMUM_LOG_SQ_SIZE;
2282         }
2283 }
2284
2285 static void mlx5e_build_channel_param(struct mlx5e_priv *priv,
2286                                       struct mlx5e_params *params,
2287                                       struct mlx5e_channel_param *cparam)
2288 {
2289         u8 icosq_log_wq_sz;
2290
2291         mlx5e_build_rq_param(priv, params, NULL, &cparam->rq);
2292
2293         icosq_log_wq_sz = mlx5e_build_icosq_log_wq_sz(params, &cparam->rq);
2294
2295         mlx5e_build_sq_param(priv, params, &cparam->sq);
2296         mlx5e_build_xdpsq_param(priv, params, &cparam->xdp_sq);
2297         mlx5e_build_icosq_param(priv, icosq_log_wq_sz, &cparam->icosq);
2298         mlx5e_build_rx_cq_param(priv, params, NULL, &cparam->rx_cq);
2299         mlx5e_build_tx_cq_param(priv, params, &cparam->tx_cq);
2300         mlx5e_build_ico_cq_param(priv, icosq_log_wq_sz, &cparam->icosq_cq);
2301 }
2302
2303 int mlx5e_open_channels(struct mlx5e_priv *priv,
2304                         struct mlx5e_channels *chs)
2305 {
2306         struct mlx5e_channel_param *cparam;
2307         int err = -ENOMEM;
2308         int i;
2309
2310         chs->num = chs->params.num_channels;
2311
2312         chs->c = kcalloc(chs->num, sizeof(struct mlx5e_channel *), GFP_KERNEL);
2313         cparam = kvzalloc(sizeof(struct mlx5e_channel_param), GFP_KERNEL);
2314         if (!chs->c || !cparam)
2315                 goto err_free;
2316
2317         mlx5e_build_channel_param(priv, &chs->params, cparam);
2318         for (i = 0; i < chs->num; i++) {
2319                 struct xdp_umem *umem = NULL;
2320
2321                 if (chs->params.xdp_prog)
2322                         umem = mlx5e_xsk_get_umem(&chs->params, chs->params.xsk, i);
2323
2324                 err = mlx5e_open_channel(priv, i, &chs->params, cparam, umem, &chs->c[i]);
2325                 if (err)
2326                         goto err_close_channels;
2327         }
2328
2329         mlx5e_health_channels_update(priv);
2330         kvfree(cparam);
2331         return 0;
2332
2333 err_close_channels:
2334         for (i--; i >= 0; i--)
2335                 mlx5e_close_channel(chs->c[i]);
2336
2337 err_free:
2338         kfree(chs->c);
2339         kvfree(cparam);
2340         chs->num = 0;
2341         return err;
2342 }
2343
2344 static void mlx5e_activate_channels(struct mlx5e_channels *chs)
2345 {
2346         int i;
2347
2348         for (i = 0; i < chs->num; i++)
2349                 mlx5e_activate_channel(chs->c[i]);
2350 }
2351
2352 #define MLX5E_RQ_WQES_TIMEOUT 20000 /* msecs */
2353
2354 static int mlx5e_wait_channels_min_rx_wqes(struct mlx5e_channels *chs)
2355 {
2356         int err = 0;
2357         int i;
2358
2359         for (i = 0; i < chs->num; i++) {
2360                 int timeout = err ? 0 : MLX5E_RQ_WQES_TIMEOUT;
2361
2362                 err |= mlx5e_wait_for_min_rx_wqes(&chs->c[i]->rq, timeout);
2363
2364                 /* Don't wait on the XSK RQ, because the newer xdpsock sample
2365                  * doesn't provide any Fill Ring entries at the setup stage.
2366                  */
2367         }
2368
2369         return err ? -ETIMEDOUT : 0;
2370 }
2371
2372 static void mlx5e_deactivate_channels(struct mlx5e_channels *chs)
2373 {
2374         int i;
2375
2376         for (i = 0; i < chs->num; i++)
2377                 mlx5e_deactivate_channel(chs->c[i]);
2378 }
2379
2380 void mlx5e_close_channels(struct mlx5e_channels *chs)
2381 {
2382         int i;
2383
2384         for (i = 0; i < chs->num; i++)
2385                 mlx5e_close_channel(chs->c[i]);
2386
2387         kfree(chs->c);
2388         chs->num = 0;
2389 }
2390
2391 static int
2392 mlx5e_create_rqt(struct mlx5e_priv *priv, int sz, struct mlx5e_rqt *rqt)
2393 {
2394         struct mlx5_core_dev *mdev = priv->mdev;
2395         void *rqtc;
2396         int inlen;
2397         int err;
2398         u32 *in;
2399         int i;
2400
2401         inlen = MLX5_ST_SZ_BYTES(create_rqt_in) + sizeof(u32) * sz;
2402         in = kvzalloc(inlen, GFP_KERNEL);
2403         if (!in)
2404                 return -ENOMEM;
2405
2406         rqtc = MLX5_ADDR_OF(create_rqt_in, in, rqt_context);
2407
2408         MLX5_SET(rqtc, rqtc, rqt_actual_size, sz);
2409         MLX5_SET(rqtc, rqtc, rqt_max_size, sz);
2410
2411         for (i = 0; i < sz; i++)
2412                 MLX5_SET(rqtc, rqtc, rq_num[i], priv->drop_rq.rqn);
2413
2414         err = mlx5_core_create_rqt(mdev, in, inlen, &rqt->rqtn);
2415         if (!err)
2416                 rqt->enabled = true;
2417
2418         kvfree(in);
2419         return err;
2420 }
2421
2422 void mlx5e_destroy_rqt(struct mlx5e_priv *priv, struct mlx5e_rqt *rqt)
2423 {
2424         rqt->enabled = false;
2425         mlx5_core_destroy_rqt(priv->mdev, rqt->rqtn);
2426 }
2427
2428 int mlx5e_create_indirect_rqt(struct mlx5e_priv *priv)
2429 {
2430         struct mlx5e_rqt *rqt = &priv->indir_rqt;
2431         int err;
2432
2433         err = mlx5e_create_rqt(priv, MLX5E_INDIR_RQT_SIZE, rqt);
2434         if (err)
2435                 mlx5_core_warn(priv->mdev, "create indirect rqts failed, %d\n", err);
2436         return err;
2437 }
2438
2439 int mlx5e_create_direct_rqts(struct mlx5e_priv *priv, struct mlx5e_tir *tirs)
2440 {
2441         int err;
2442         int ix;
2443
2444         for (ix = 0; ix < priv->max_nch; ix++) {
2445                 err = mlx5e_create_rqt(priv, 1 /*size */, &tirs[ix].rqt);
2446                 if (unlikely(err))
2447                         goto err_destroy_rqts;
2448         }
2449
2450         return 0;
2451
2452 err_destroy_rqts:
2453         mlx5_core_warn(priv->mdev, "create rqts failed, %d\n", err);
2454         for (ix--; ix >= 0; ix--)
2455                 mlx5e_destroy_rqt(priv, &tirs[ix].rqt);
2456
2457         return err;
2458 }
2459
2460 void mlx5e_destroy_direct_rqts(struct mlx5e_priv *priv, struct mlx5e_tir *tirs)
2461 {
2462         int i;
2463
2464         for (i = 0; i < priv->max_nch; i++)
2465                 mlx5e_destroy_rqt(priv, &tirs[i].rqt);
2466 }
2467
2468 static int mlx5e_rx_hash_fn(int hfunc)
2469 {
2470         return (hfunc == ETH_RSS_HASH_TOP) ?
2471                MLX5_RX_HASH_FN_TOEPLITZ :
2472                MLX5_RX_HASH_FN_INVERTED_XOR8;
2473 }
2474
2475 int mlx5e_bits_invert(unsigned long a, int size)
2476 {
2477         int inv = 0;
2478         int i;
2479
2480         for (i = 0; i < size; i++)
2481                 inv |= (test_bit(size - i - 1, &a) ? 1 : 0) << i;
2482
2483         return inv;
2484 }
2485
2486 static void mlx5e_fill_rqt_rqns(struct mlx5e_priv *priv, int sz,
2487                                 struct mlx5e_redirect_rqt_param rrp, void *rqtc)
2488 {
2489         int i;
2490
2491         for (i = 0; i < sz; i++) {
2492                 u32 rqn;
2493
2494                 if (rrp.is_rss) {
2495                         int ix = i;
2496
2497                         if (rrp.rss.hfunc == ETH_RSS_HASH_XOR)
2498                                 ix = mlx5e_bits_invert(i, ilog2(sz));
2499
2500                         ix = priv->rss_params.indirection_rqt[ix];
2501                         rqn = rrp.rss.channels->c[ix]->rq.rqn;
2502                 } else {
2503                         rqn = rrp.rqn;
2504                 }
2505                 MLX5_SET(rqtc, rqtc, rq_num[i], rqn);
2506         }
2507 }
2508
2509 int mlx5e_redirect_rqt(struct mlx5e_priv *priv, u32 rqtn, int sz,
2510                        struct mlx5e_redirect_rqt_param rrp)
2511 {
2512         struct mlx5_core_dev *mdev = priv->mdev;
2513         void *rqtc;
2514         int inlen;
2515         u32 *in;
2516         int err;
2517
2518         inlen = MLX5_ST_SZ_BYTES(modify_rqt_in) + sizeof(u32) * sz;
2519         in = kvzalloc(inlen, GFP_KERNEL);
2520         if (!in)
2521                 return -ENOMEM;
2522
2523         rqtc = MLX5_ADDR_OF(modify_rqt_in, in, ctx);
2524
2525         MLX5_SET(rqtc, rqtc, rqt_actual_size, sz);
2526         MLX5_SET(modify_rqt_in, in, bitmask.rqn_list, 1);
2527         mlx5e_fill_rqt_rqns(priv, sz, rrp, rqtc);
2528         err = mlx5_core_modify_rqt(mdev, rqtn, in, inlen);
2529
2530         kvfree(in);
2531         return err;
2532 }
2533
2534 static u32 mlx5e_get_direct_rqn(struct mlx5e_priv *priv, int ix,
2535                                 struct mlx5e_redirect_rqt_param rrp)
2536 {
2537         if (!rrp.is_rss)
2538                 return rrp.rqn;
2539
2540         if (ix >= rrp.rss.channels->num)
2541                 return priv->drop_rq.rqn;
2542
2543         return rrp.rss.channels->c[ix]->rq.rqn;
2544 }
2545
2546 static void mlx5e_redirect_rqts(struct mlx5e_priv *priv,
2547                                 struct mlx5e_redirect_rqt_param rrp)
2548 {
2549         u32 rqtn;
2550         int ix;
2551
2552         if (priv->indir_rqt.enabled) {
2553                 /* RSS RQ table */
2554                 rqtn = priv->indir_rqt.rqtn;
2555                 mlx5e_redirect_rqt(priv, rqtn, MLX5E_INDIR_RQT_SIZE, rrp);
2556         }
2557
2558         for (ix = 0; ix < priv->max_nch; ix++) {
2559                 struct mlx5e_redirect_rqt_param direct_rrp = {
2560                         .is_rss = false,
2561                         {
2562                                 .rqn    = mlx5e_get_direct_rqn(priv, ix, rrp)
2563                         },
2564                 };
2565
2566                 /* Direct RQ Tables */
2567                 if (!priv->direct_tir[ix].rqt.enabled)
2568                         continue;
2569
2570                 rqtn = priv->direct_tir[ix].rqt.rqtn;
2571                 mlx5e_redirect_rqt(priv, rqtn, 1, direct_rrp);
2572         }
2573 }
2574
2575 static void mlx5e_redirect_rqts_to_channels(struct mlx5e_priv *priv,
2576                                             struct mlx5e_channels *chs)
2577 {
2578         struct mlx5e_redirect_rqt_param rrp = {
2579                 .is_rss        = true,
2580                 {
2581                         .rss = {
2582                                 .channels  = chs,
2583                                 .hfunc     = priv->rss_params.hfunc,
2584                         }
2585                 },
2586         };
2587
2588         mlx5e_redirect_rqts(priv, rrp);
2589 }
2590
2591 static void mlx5e_redirect_rqts_to_drop(struct mlx5e_priv *priv)
2592 {
2593         struct mlx5e_redirect_rqt_param drop_rrp = {
2594                 .is_rss = false,
2595                 {
2596                         .rqn = priv->drop_rq.rqn,
2597                 },
2598         };
2599
2600         mlx5e_redirect_rqts(priv, drop_rrp);
2601 }
2602
2603 static const struct mlx5e_tirc_config tirc_default_config[MLX5E_NUM_INDIR_TIRS] = {
2604         [MLX5E_TT_IPV4_TCP] = { .l3_prot_type = MLX5_L3_PROT_TYPE_IPV4,
2605                                 .l4_prot_type = MLX5_L4_PROT_TYPE_TCP,
2606                                 .rx_hash_fields = MLX5_HASH_IP_L4PORTS,
2607         },
2608         [MLX5E_TT_IPV6_TCP] = { .l3_prot_type = MLX5_L3_PROT_TYPE_IPV6,
2609                                 .l4_prot_type = MLX5_L4_PROT_TYPE_TCP,
2610                                 .rx_hash_fields = MLX5_HASH_IP_L4PORTS,
2611         },
2612         [MLX5E_TT_IPV4_UDP] = { .l3_prot_type = MLX5_L3_PROT_TYPE_IPV4,
2613                                 .l4_prot_type = MLX5_L4_PROT_TYPE_UDP,
2614                                 .rx_hash_fields = MLX5_HASH_IP_L4PORTS,
2615         },
2616         [MLX5E_TT_IPV6_UDP] = { .l3_prot_type = MLX5_L3_PROT_TYPE_IPV6,
2617                                 .l4_prot_type = MLX5_L4_PROT_TYPE_UDP,
2618                                 .rx_hash_fields = MLX5_HASH_IP_L4PORTS,
2619         },
2620         [MLX5E_TT_IPV4_IPSEC_AH] = { .l3_prot_type = MLX5_L3_PROT_TYPE_IPV4,
2621                                      .l4_prot_type = 0,
2622                                      .rx_hash_fields = MLX5_HASH_IP_IPSEC_SPI,
2623         },
2624         [MLX5E_TT_IPV6_IPSEC_AH] = { .l3_prot_type = MLX5_L3_PROT_TYPE_IPV6,
2625                                      .l4_prot_type = 0,
2626                                      .rx_hash_fields = MLX5_HASH_IP_IPSEC_SPI,
2627         },
2628         [MLX5E_TT_IPV4_IPSEC_ESP] = { .l3_prot_type = MLX5_L3_PROT_TYPE_IPV4,
2629                                       .l4_prot_type = 0,
2630                                       .rx_hash_fields = MLX5_HASH_IP_IPSEC_SPI,
2631         },
2632         [MLX5E_TT_IPV6_IPSEC_ESP] = { .l3_prot_type = MLX5_L3_PROT_TYPE_IPV6,
2633                                       .l4_prot_type = 0,
2634                                       .rx_hash_fields = MLX5_HASH_IP_IPSEC_SPI,
2635         },
2636         [MLX5E_TT_IPV4] = { .l3_prot_type = MLX5_L3_PROT_TYPE_IPV4,
2637                             .l4_prot_type = 0,
2638                             .rx_hash_fields = MLX5_HASH_IP,
2639         },
2640         [MLX5E_TT_IPV6] = { .l3_prot_type = MLX5_L3_PROT_TYPE_IPV6,
2641                             .l4_prot_type = 0,
2642                             .rx_hash_fields = MLX5_HASH_IP,
2643         },
2644 };
2645
2646 struct mlx5e_tirc_config mlx5e_tirc_get_default_config(enum mlx5e_traffic_types tt)
2647 {
2648         return tirc_default_config[tt];
2649 }
2650
2651 static void mlx5e_build_tir_ctx_lro(struct mlx5e_params *params, void *tirc)
2652 {
2653         if (!params->lro_en)
2654                 return;
2655
2656 #define ROUGH_MAX_L2_L3_HDR_SZ 256
2657
2658         MLX5_SET(tirc, tirc, lro_enable_mask,
2659                  MLX5_TIRC_LRO_ENABLE_MASK_IPV4_LRO |
2660                  MLX5_TIRC_LRO_ENABLE_MASK_IPV6_LRO);
2661         MLX5_SET(tirc, tirc, lro_max_ip_payload_size,
2662                  (MLX5E_PARAMS_DEFAULT_LRO_WQE_SZ - ROUGH_MAX_L2_L3_HDR_SZ) >> 8);
2663         MLX5_SET(tirc, tirc, lro_timeout_period_usecs, params->lro_timeout);
2664 }
2665
2666 void mlx5e_build_indir_tir_ctx_hash(struct mlx5e_rss_params *rss_params,
2667                                     const struct mlx5e_tirc_config *ttconfig,
2668                                     void *tirc, bool inner)
2669 {
2670         void *hfso = inner ? MLX5_ADDR_OF(tirc, tirc, rx_hash_field_selector_inner) :
2671                              MLX5_ADDR_OF(tirc, tirc, rx_hash_field_selector_outer);
2672
2673         MLX5_SET(tirc, tirc, rx_hash_fn, mlx5e_rx_hash_fn(rss_params->hfunc));
2674         if (rss_params->hfunc == ETH_RSS_HASH_TOP) {
2675                 void *rss_key = MLX5_ADDR_OF(tirc, tirc,
2676                                              rx_hash_toeplitz_key);
2677                 size_t len = MLX5_FLD_SZ_BYTES(tirc,
2678                                                rx_hash_toeplitz_key);
2679
2680                 MLX5_SET(tirc, tirc, rx_hash_symmetric, 1);
2681                 memcpy(rss_key, rss_params->toeplitz_hash_key, len);
2682         }
2683         MLX5_SET(rx_hash_field_select, hfso, l3_prot_type,
2684                  ttconfig->l3_prot_type);
2685         MLX5_SET(rx_hash_field_select, hfso, l4_prot_type,
2686                  ttconfig->l4_prot_type);
2687         MLX5_SET(rx_hash_field_select, hfso, selected_fields,
2688                  ttconfig->rx_hash_fields);
2689 }
2690
2691 static void mlx5e_update_rx_hash_fields(struct mlx5e_tirc_config *ttconfig,
2692                                         enum mlx5e_traffic_types tt,
2693                                         u32 rx_hash_fields)
2694 {
2695         *ttconfig                = tirc_default_config[tt];
2696         ttconfig->rx_hash_fields = rx_hash_fields;
2697 }
2698
2699 void mlx5e_modify_tirs_hash(struct mlx5e_priv *priv, void *in)
2700 {
2701         void *tirc = MLX5_ADDR_OF(modify_tir_in, in, ctx);
2702         struct mlx5e_rss_params *rss = &priv->rss_params;
2703         struct mlx5_core_dev *mdev = priv->mdev;
2704         int ctxlen = MLX5_ST_SZ_BYTES(tirc);
2705         struct mlx5e_tirc_config ttconfig;
2706         int tt;
2707
2708         MLX5_SET(modify_tir_in, in, bitmask.hash, 1);
2709
2710         for (tt = 0; tt < MLX5E_NUM_INDIR_TIRS; tt++) {
2711                 memset(tirc, 0, ctxlen);
2712                 mlx5e_update_rx_hash_fields(&ttconfig, tt,
2713                                             rss->rx_hash_fields[tt]);
2714                 mlx5e_build_indir_tir_ctx_hash(rss, &ttconfig, tirc, false);
2715                 mlx5_core_modify_tir(mdev, priv->indir_tir[tt].tirn, in);
2716         }
2717
2718         /* Verify inner tirs resources allocated */
2719         if (!priv->inner_indir_tir[0].tirn)
2720                 return;
2721
2722         for (tt = 0; tt < MLX5E_NUM_INDIR_TIRS; tt++) {
2723                 memset(tirc, 0, ctxlen);
2724                 mlx5e_update_rx_hash_fields(&ttconfig, tt,
2725                                             rss->rx_hash_fields[tt]);
2726                 mlx5e_build_indir_tir_ctx_hash(rss, &ttconfig, tirc, true);
2727                 mlx5_core_modify_tir(mdev, priv->inner_indir_tir[tt].tirn, in);
2728         }
2729 }
2730
2731 static int mlx5e_modify_tirs_lro(struct mlx5e_priv *priv)
2732 {
2733         struct mlx5_core_dev *mdev = priv->mdev;
2734
2735         void *in;
2736         void *tirc;
2737         int inlen;
2738         int err;
2739         int tt;
2740         int ix;
2741
2742         inlen = MLX5_ST_SZ_BYTES(modify_tir_in);
2743         in = kvzalloc(inlen, GFP_KERNEL);
2744         if (!in)
2745                 return -ENOMEM;
2746
2747         MLX5_SET(modify_tir_in, in, bitmask.lro, 1);
2748         tirc = MLX5_ADDR_OF(modify_tir_in, in, ctx);
2749
2750         mlx5e_build_tir_ctx_lro(&priv->channels.params, tirc);
2751
2752         for (tt = 0; tt < MLX5E_NUM_INDIR_TIRS; tt++) {
2753                 err = mlx5_core_modify_tir(mdev, priv->indir_tir[tt].tirn, in);
2754                 if (err)
2755                         goto free_in;
2756         }
2757
2758         for (ix = 0; ix < priv->max_nch; ix++) {
2759                 err = mlx5_core_modify_tir(mdev, priv->direct_tir[ix].tirn, in);
2760                 if (err)
2761                         goto free_in;
2762         }
2763
2764 free_in:
2765         kvfree(in);
2766
2767         return err;
2768 }
2769
2770 static MLX5E_DEFINE_PREACTIVATE_WRAPPER_CTX(mlx5e_modify_tirs_lro);
2771
2772 static int mlx5e_set_mtu(struct mlx5_core_dev *mdev,
2773                          struct mlx5e_params *params, u16 mtu)
2774 {
2775         u16 hw_mtu = MLX5E_SW2HW_MTU(params, mtu);
2776         int err;
2777
2778         err = mlx5_set_port_mtu(mdev, hw_mtu, 1);
2779         if (err)
2780                 return err;
2781
2782         /* Update vport context MTU */
2783         mlx5_modify_nic_vport_mtu(mdev, hw_mtu);
2784         return 0;
2785 }
2786
2787 static void mlx5e_query_mtu(struct mlx5_core_dev *mdev,
2788                             struct mlx5e_params *params, u16 *mtu)
2789 {
2790         u16 hw_mtu = 0;
2791         int err;
2792
2793         err = mlx5_query_nic_vport_mtu(mdev, &hw_mtu);
2794         if (err || !hw_mtu) /* fallback to port oper mtu */
2795                 mlx5_query_port_oper_mtu(mdev, &hw_mtu, 1);
2796
2797         *mtu = MLX5E_HW2SW_MTU(params, hw_mtu);
2798 }
2799
2800 int mlx5e_set_dev_port_mtu(struct mlx5e_priv *priv)
2801 {
2802         struct mlx5e_params *params = &priv->channels.params;
2803         struct net_device *netdev = priv->netdev;
2804         struct mlx5_core_dev *mdev = priv->mdev;
2805         u16 mtu;
2806         int err;
2807
2808         err = mlx5e_set_mtu(mdev, params, params->sw_mtu);
2809         if (err)
2810                 return err;
2811
2812         mlx5e_query_mtu(mdev, params, &mtu);
2813         if (mtu != params->sw_mtu)
2814                 netdev_warn(netdev, "%s: VPort MTU %d is different than netdev mtu %d\n",
2815                             __func__, mtu, params->sw_mtu);
2816
2817         params->sw_mtu = mtu;
2818         return 0;
2819 }
2820
2821 MLX5E_DEFINE_PREACTIVATE_WRAPPER_CTX(mlx5e_set_dev_port_mtu);
2822
2823 void mlx5e_set_netdev_mtu_boundaries(struct mlx5e_priv *priv)
2824 {
2825         struct mlx5e_params *params = &priv->channels.params;
2826         struct net_device *netdev   = priv->netdev;
2827         struct mlx5_core_dev *mdev  = priv->mdev;
2828         u16 max_mtu;
2829
2830         /* MTU range: 68 - hw-specific max */
2831         netdev->min_mtu = ETH_MIN_MTU;
2832
2833         mlx5_query_port_max_mtu(mdev, &max_mtu, 1);
2834         netdev->max_mtu = min_t(unsigned int, MLX5E_HW2SW_MTU(params, max_mtu),
2835                                 ETH_MAX_MTU);
2836 }
2837
2838 static void mlx5e_netdev_set_tcs(struct net_device *netdev, u16 nch, u8 ntc)
2839 {
2840         int tc;
2841
2842         netdev_reset_tc(netdev);
2843
2844         if (ntc == 1)
2845                 return;
2846
2847         netdev_set_num_tc(netdev, ntc);
2848
2849         /* Map netdev TCs to offset 0
2850          * We have our own UP to TXQ mapping for QoS
2851          */
2852         for (tc = 0; tc < ntc; tc++)
2853                 netdev_set_tc_queue(netdev, tc, nch, 0);
2854 }
2855
2856 static int mlx5e_update_netdev_queues(struct mlx5e_priv *priv)
2857 {
2858         struct net_device *netdev = priv->netdev;
2859         int num_txqs, num_rxqs, nch, ntc;
2860         int old_num_txqs, old_ntc;
2861         int err;
2862
2863         old_num_txqs = netdev->real_num_tx_queues;
2864         old_ntc = netdev->num_tc;
2865
2866         nch = priv->channels.params.num_channels;
2867         ntc = priv->channels.params.num_tc;
2868         num_txqs = nch * ntc;
2869         num_rxqs = nch * priv->profile->rq_groups;
2870
2871         mlx5e_netdev_set_tcs(netdev, nch, ntc);
2872
2873         err = netif_set_real_num_tx_queues(netdev, num_txqs);
2874         if (err) {
2875                 netdev_warn(netdev, "netif_set_real_num_tx_queues failed, %d\n", err);
2876                 goto err_tcs;
2877         }
2878         err = netif_set_real_num_rx_queues(netdev, num_rxqs);
2879         if (err) {
2880                 netdev_warn(netdev, "netif_set_real_num_rx_queues failed, %d\n", err);
2881                 goto err_txqs;
2882         }
2883
2884         return 0;
2885
2886 err_txqs:
2887         /* netif_set_real_num_rx_queues could fail only when nch increased. Only
2888          * one of nch and ntc is changed in this function. That means, the call
2889          * to netif_set_real_num_tx_queues below should not fail, because it
2890          * decreases the number of TX queues.
2891          */
2892         WARN_ON_ONCE(netif_set_real_num_tx_queues(netdev, old_num_txqs));
2893
2894 err_tcs:
2895         mlx5e_netdev_set_tcs(netdev, old_num_txqs / old_ntc, old_ntc);
2896         return err;
2897 }
2898
2899 static void mlx5e_set_default_xps_cpumasks(struct mlx5e_priv *priv,
2900                                            struct mlx5e_params *params)
2901 {
2902         struct mlx5_core_dev *mdev = priv->mdev;
2903         int num_comp_vectors, ix, irq;
2904
2905         num_comp_vectors = mlx5_comp_vectors_count(mdev);
2906
2907         for (ix = 0; ix < params->num_channels; ix++) {
2908                 cpumask_clear(priv->scratchpad.cpumask);
2909
2910                 for (irq = ix; irq < num_comp_vectors; irq += params->num_channels) {
2911                         int cpu = cpumask_first(mlx5_comp_irq_get_affinity_mask(mdev, irq));
2912
2913                         cpumask_set_cpu(cpu, priv->scratchpad.cpumask);
2914                 }
2915
2916                 netif_set_xps_queue(priv->netdev, priv->scratchpad.cpumask, ix);
2917         }
2918 }
2919
2920 int mlx5e_num_channels_changed(struct mlx5e_priv *priv)
2921 {
2922         u16 count = priv->channels.params.num_channels;
2923         int err;
2924
2925         err = mlx5e_update_netdev_queues(priv);
2926         if (err)
2927                 return err;
2928
2929         mlx5e_set_default_xps_cpumasks(priv, &priv->channels.params);
2930
2931         if (!netif_is_rxfh_configured(priv->netdev))
2932                 mlx5e_build_default_indir_rqt(priv->rss_params.indirection_rqt,
2933                                               MLX5E_INDIR_RQT_SIZE, count);
2934
2935         return 0;
2936 }
2937
2938 MLX5E_DEFINE_PREACTIVATE_WRAPPER_CTX(mlx5e_num_channels_changed);
2939
2940 static void mlx5e_build_txq_maps(struct mlx5e_priv *priv)
2941 {
2942         int i, ch;
2943
2944         ch = priv->channels.num;
2945
2946         for (i = 0; i < ch; i++) {
2947                 int tc;
2948
2949                 for (tc = 0; tc < priv->channels.params.num_tc; tc++) {
2950                         struct mlx5e_channel *c = priv->channels.c[i];
2951                         struct mlx5e_txqsq *sq = &c->sq[tc];
2952
2953                         priv->txq2sq[sq->txq_ix] = sq;
2954                         priv->channel_tc2realtxq[i][tc] = i + tc * ch;
2955                 }
2956         }
2957 }
2958
2959 void mlx5e_activate_priv_channels(struct mlx5e_priv *priv)
2960 {
2961         mlx5e_build_txq_maps(priv);
2962         mlx5e_activate_channels(&priv->channels);
2963         mlx5e_xdp_tx_enable(priv);
2964         netif_tx_start_all_queues(priv->netdev);
2965
2966         if (mlx5e_is_vport_rep(priv))
2967                 mlx5e_add_sqs_fwd_rules(priv);
2968
2969         mlx5e_wait_channels_min_rx_wqes(&priv->channels);
2970         mlx5e_redirect_rqts_to_channels(priv, &priv->channels);
2971
2972         mlx5e_xsk_redirect_rqts_to_channels(priv, &priv->channels);
2973 }
2974
2975 void mlx5e_deactivate_priv_channels(struct mlx5e_priv *priv)
2976 {
2977         mlx5e_xsk_redirect_rqts_to_drop(priv, &priv->channels);
2978
2979         mlx5e_redirect_rqts_to_drop(priv);
2980
2981         if (mlx5e_is_vport_rep(priv))
2982                 mlx5e_remove_sqs_fwd_rules(priv);
2983
2984         /* FIXME: This is a W/A only for tx timeout watch dog false alarm when
2985          * polling for inactive tx queues.
2986          */
2987         netif_tx_stop_all_queues(priv->netdev);
2988         netif_tx_disable(priv->netdev);
2989         mlx5e_xdp_tx_disable(priv);
2990         mlx5e_deactivate_channels(&priv->channels);
2991 }
2992
2993 static int mlx5e_switch_priv_channels(struct mlx5e_priv *priv,
2994                                       struct mlx5e_channels *new_chs,
2995                                       mlx5e_fp_preactivate preactivate,
2996                                       void *context)
2997 {
2998         struct net_device *netdev = priv->netdev;
2999         struct mlx5e_channels old_chs;
3000         int carrier_ok;
3001         int err = 0;
3002
3003         carrier_ok = netif_carrier_ok(netdev);
3004         netif_carrier_off(netdev);
3005
3006         mlx5e_deactivate_priv_channels(priv);
3007
3008         old_chs = priv->channels;
3009         priv->channels = *new_chs;
3010
3011         /* New channels are ready to roll, call the preactivate hook if needed
3012          * to modify HW settings or update kernel parameters.
3013          */
3014         if (preactivate) {
3015                 err = preactivate(priv, context);
3016                 if (err) {
3017                         priv->channels = old_chs;
3018                         goto out;
3019                 }
3020         }
3021
3022         mlx5e_close_channels(&old_chs);
3023         priv->profile->update_rx(priv);
3024
3025 out:
3026         mlx5e_activate_priv_channels(priv);
3027
3028         /* return carrier back if needed */
3029         if (carrier_ok)
3030                 netif_carrier_on(netdev);
3031
3032         return err;
3033 }
3034
3035 int mlx5e_safe_switch_channels(struct mlx5e_priv *priv,
3036                                struct mlx5e_channels *new_chs,
3037                                mlx5e_fp_preactivate preactivate,
3038                                void *context)
3039 {
3040         int err;
3041
3042         err = mlx5e_open_channels(priv, new_chs);
3043         if (err)
3044                 return err;
3045
3046         err = mlx5e_switch_priv_channels(priv, new_chs, preactivate, context);
3047         if (err)
3048                 goto err_close;
3049
3050         return 0;
3051
3052 err_close:
3053         mlx5e_close_channels(new_chs);
3054
3055         return err;
3056 }
3057
3058 int mlx5e_safe_reopen_channels(struct mlx5e_priv *priv)
3059 {
3060         struct mlx5e_channels new_channels = {};
3061
3062         new_channels.params = priv->channels.params;
3063         return mlx5e_safe_switch_channels(priv, &new_channels, NULL, NULL);
3064 }
3065
3066 void mlx5e_timestamp_init(struct mlx5e_priv *priv)
3067 {
3068         priv->tstamp.tx_type   = HWTSTAMP_TX_OFF;
3069         priv->tstamp.rx_filter = HWTSTAMP_FILTER_NONE;
3070 }
3071
3072 int mlx5e_open_locked(struct net_device *netdev)
3073 {
3074         struct mlx5e_priv *priv = netdev_priv(netdev);
3075         int err;
3076
3077         set_bit(MLX5E_STATE_OPENED, &priv->state);
3078
3079         err = mlx5e_open_channels(priv, &priv->channels);
3080         if (err)
3081                 goto err_clear_state_opened_flag;
3082
3083         priv->profile->update_rx(priv);
3084         mlx5e_activate_priv_channels(priv);
3085         if (priv->profile->update_carrier)
3086                 priv->profile->update_carrier(priv);
3087
3088         mlx5e_queue_update_stats(priv);
3089         return 0;
3090
3091 err_clear_state_opened_flag:
3092         clear_bit(MLX5E_STATE_OPENED, &priv->state);
3093         return err;
3094 }
3095
3096 int mlx5e_open(struct net_device *netdev)
3097 {
3098         struct mlx5e_priv *priv = netdev_priv(netdev);
3099         int err;
3100
3101         mutex_lock(&priv->state_lock);
3102         err = mlx5e_open_locked(netdev);
3103         if (!err)
3104                 mlx5_set_port_admin_status(priv->mdev, MLX5_PORT_UP);
3105         mutex_unlock(&priv->state_lock);
3106
3107         if (mlx5_vxlan_allowed(priv->mdev->vxlan))
3108                 udp_tunnel_get_rx_info(netdev);
3109
3110         return err;
3111 }
3112
3113 int mlx5e_close_locked(struct net_device *netdev)
3114 {
3115         struct mlx5e_priv *priv = netdev_priv(netdev);
3116
3117         /* May already be CLOSED in case a previous configuration operation
3118          * (e.g RX/TX queue size change) that involves close&open failed.
3119          */
3120         if (!test_bit(MLX5E_STATE_OPENED, &priv->state))
3121                 return 0;
3122
3123         clear_bit(MLX5E_STATE_OPENED, &priv->state);
3124
3125         netif_carrier_off(priv->netdev);
3126         mlx5e_deactivate_priv_channels(priv);
3127         mlx5e_close_channels(&priv->channels);
3128
3129         return 0;
3130 }
3131
3132 int mlx5e_close(struct net_device *netdev)
3133 {
3134         struct mlx5e_priv *priv = netdev_priv(netdev);
3135         int err;
3136
3137         if (!netif_device_present(netdev))
3138                 return -ENODEV;
3139
3140         mutex_lock(&priv->state_lock);
3141         mlx5_set_port_admin_status(priv->mdev, MLX5_PORT_DOWN);
3142         err = mlx5e_close_locked(netdev);
3143         mutex_unlock(&priv->state_lock);
3144
3145         return err;
3146 }
3147
3148 static int mlx5e_alloc_drop_rq(struct mlx5_core_dev *mdev,
3149                                struct mlx5e_rq *rq,
3150                                struct mlx5e_rq_param *param)
3151 {
3152         void *rqc = param->rqc;
3153         void *rqc_wq = MLX5_ADDR_OF(rqc, rqc, wq);
3154         int err;
3155
3156         param->wq.db_numa_node = param->wq.buf_numa_node;
3157
3158         err = mlx5_wq_cyc_create(mdev, &param->wq, rqc_wq, &rq->wqe.wq,
3159                                  &rq->wq_ctrl);
3160         if (err)
3161                 return err;
3162
3163         /* Mark as unused given "Drop-RQ" packets never reach XDP */
3164         xdp_rxq_info_unused(&rq->xdp_rxq);
3165
3166         rq->mdev = mdev;
3167
3168         return 0;
3169 }
3170
3171 static int mlx5e_alloc_drop_cq(struct mlx5_core_dev *mdev,
3172                                struct mlx5e_cq *cq,
3173                                struct mlx5e_cq_param *param)
3174 {
3175         param->wq.buf_numa_node = dev_to_node(mdev->device);
3176         param->wq.db_numa_node  = dev_to_node(mdev->device);
3177
3178         return mlx5e_alloc_cq_common(mdev, param, cq);
3179 }
3180
3181 int mlx5e_open_drop_rq(struct mlx5e_priv *priv,
3182                        struct mlx5e_rq *drop_rq)
3183 {
3184         struct mlx5_core_dev *mdev = priv->mdev;
3185         struct mlx5e_cq_param cq_param = {};
3186         struct mlx5e_rq_param rq_param = {};
3187         struct mlx5e_cq *cq = &drop_rq->cq;
3188         int err;
3189
3190         mlx5e_build_drop_rq_param(priv, &rq_param);
3191
3192         err = mlx5e_alloc_drop_cq(mdev, cq, &cq_param);
3193         if (err)
3194                 return err;
3195
3196         err = mlx5e_create_cq(cq, &cq_param);
3197         if (err)
3198                 goto err_free_cq;
3199
3200         err = mlx5e_alloc_drop_rq(mdev, drop_rq, &rq_param);
3201         if (err)
3202                 goto err_destroy_cq;
3203
3204         err = mlx5e_create_rq(drop_rq, &rq_param);
3205         if (err)
3206                 goto err_free_rq;
3207
3208         err = mlx5e_modify_rq_state(drop_rq, MLX5_RQC_STATE_RST, MLX5_RQC_STATE_RDY);
3209         if (err)
3210                 mlx5_core_warn(priv->mdev, "modify_rq_state failed, rx_if_down_packets won't be counted %d\n", err);
3211
3212         return 0;
3213
3214 err_free_rq:
3215         mlx5e_free_rq(drop_rq);
3216
3217 err_destroy_cq:
3218         mlx5e_destroy_cq(cq);
3219
3220 err_free_cq:
3221         mlx5e_free_cq(cq);
3222
3223         return err;
3224 }
3225
3226 void mlx5e_close_drop_rq(struct mlx5e_rq *drop_rq)
3227 {
3228         mlx5e_destroy_rq(drop_rq);
3229         mlx5e_free_rq(drop_rq);
3230         mlx5e_destroy_cq(&drop_rq->cq);
3231         mlx5e_free_cq(&drop_rq->cq);
3232 }
3233
3234 int mlx5e_create_tis(struct mlx5_core_dev *mdev, void *in, u32 *tisn)
3235 {
3236         void *tisc = MLX5_ADDR_OF(create_tis_in, in, ctx);
3237
3238         MLX5_SET(tisc, tisc, transport_domain, mdev->mlx5e_res.td.tdn);
3239
3240         if (MLX5_GET(tisc, tisc, tls_en))
3241                 MLX5_SET(tisc, tisc, pd, mdev->mlx5e_res.pdn);
3242
3243         if (mlx5_lag_is_lacp_owner(mdev))
3244                 MLX5_SET(tisc, tisc, strict_lag_tx_port_affinity, 1);
3245
3246         return mlx5_core_create_tis(mdev, in, tisn);
3247 }
3248
3249 void mlx5e_destroy_tis(struct mlx5_core_dev *mdev, u32 tisn)
3250 {
3251         mlx5_core_destroy_tis(mdev, tisn);
3252 }
3253
3254 void mlx5e_destroy_tises(struct mlx5e_priv *priv)
3255 {
3256         int tc, i;
3257
3258         for (i = 0; i < mlx5e_get_num_lag_ports(priv->mdev); i++)
3259                 for (tc = 0; tc < priv->profile->max_tc; tc++)
3260                         mlx5e_destroy_tis(priv->mdev, priv->tisn[i][tc]);
3261 }
3262
3263 static bool mlx5e_lag_should_assign_affinity(struct mlx5_core_dev *mdev)
3264 {
3265         return MLX5_CAP_GEN(mdev, lag_tx_port_affinity) && mlx5e_get_num_lag_ports(mdev) > 1;
3266 }
3267
3268 int mlx5e_create_tises(struct mlx5e_priv *priv)
3269 {
3270         int tc, i;
3271         int err;
3272
3273         for (i = 0; i < mlx5e_get_num_lag_ports(priv->mdev); i++) {
3274                 for (tc = 0; tc < priv->profile->max_tc; tc++) {
3275                         u32 in[MLX5_ST_SZ_DW(create_tis_in)] = {};
3276                         void *tisc;
3277
3278                         tisc = MLX5_ADDR_OF(create_tis_in, in, ctx);
3279
3280                         MLX5_SET(tisc, tisc, prio, tc << 1);
3281
3282                         if (mlx5e_lag_should_assign_affinity(priv->mdev))
3283                                 MLX5_SET(tisc, tisc, lag_tx_port_affinity, i + 1);
3284
3285                         err = mlx5e_create_tis(priv->mdev, in, &priv->tisn[i][tc]);
3286                         if (err)
3287                                 goto err_close_tises;
3288                 }
3289         }
3290
3291         return 0;
3292
3293 err_close_tises:
3294         for (; i >= 0; i--) {
3295                 for (tc--; tc >= 0; tc--)
3296                         mlx5e_destroy_tis(priv->mdev, priv->tisn[i][tc]);
3297                 tc = priv->profile->max_tc;
3298         }
3299
3300         return err;
3301 }
3302
3303 static void mlx5e_cleanup_nic_tx(struct mlx5e_priv *priv)
3304 {
3305         mlx5e_destroy_tises(priv);
3306 }
3307
3308 static void mlx5e_build_indir_tir_ctx_common(struct mlx5e_priv *priv,
3309                                              u32 rqtn, u32 *tirc)
3310 {
3311         MLX5_SET(tirc, tirc, transport_domain, priv->mdev->mlx5e_res.td.tdn);
3312         MLX5_SET(tirc, tirc, disp_type, MLX5_TIRC_DISP_TYPE_INDIRECT);
3313         MLX5_SET(tirc, tirc, indirect_table, rqtn);
3314         MLX5_SET(tirc, tirc, tunneled_offload_en,
3315                  priv->channels.params.tunneled_offload_en);
3316
3317         mlx5e_build_tir_ctx_lro(&priv->channels.params, tirc);
3318 }
3319
3320 static void mlx5e_build_indir_tir_ctx(struct mlx5e_priv *priv,
3321                                       enum mlx5e_traffic_types tt,
3322                                       u32 *tirc)
3323 {
3324         mlx5e_build_indir_tir_ctx_common(priv, priv->indir_rqt.rqtn, tirc);
3325         mlx5e_build_indir_tir_ctx_hash(&priv->rss_params,
3326                                        &tirc_default_config[tt], tirc, false);
3327 }
3328
3329 static void mlx5e_build_direct_tir_ctx(struct mlx5e_priv *priv, u32 rqtn, u32 *tirc)
3330 {
3331         mlx5e_build_indir_tir_ctx_common(priv, rqtn, tirc);
3332         MLX5_SET(tirc, tirc, rx_hash_fn, MLX5_RX_HASH_FN_INVERTED_XOR8);
3333 }
3334
3335 static void mlx5e_build_inner_indir_tir_ctx(struct mlx5e_priv *priv,
3336                                             enum mlx5e_traffic_types tt,
3337                                             u32 *tirc)
3338 {
3339         mlx5e_build_indir_tir_ctx_common(priv, priv->indir_rqt.rqtn, tirc);
3340         mlx5e_build_indir_tir_ctx_hash(&priv->rss_params,
3341                                        &tirc_default_config[tt], tirc, true);
3342 }
3343
3344 int mlx5e_create_indirect_tirs(struct mlx5e_priv *priv, bool inner_ttc)
3345 {
3346         struct mlx5e_tir *tir;
3347         void *tirc;
3348         int inlen;
3349         int i = 0;
3350         int err;
3351         u32 *in;
3352         int tt;
3353
3354         inlen = MLX5_ST_SZ_BYTES(create_tir_in);
3355         in = kvzalloc(inlen, GFP_KERNEL);
3356         if (!in)
3357                 return -ENOMEM;
3358
3359         for (tt = 0; tt < MLX5E_NUM_INDIR_TIRS; tt++) {
3360                 memset(in, 0, inlen);
3361                 tir = &priv->indir_tir[tt];
3362                 tirc = MLX5_ADDR_OF(create_tir_in, in, ctx);
3363                 mlx5e_build_indir_tir_ctx(priv, tt, tirc);
3364                 err = mlx5e_create_tir(priv->mdev, tir, in);
3365                 if (err) {
3366                         mlx5_core_warn(priv->mdev, "create indirect tirs failed, %d\n", err);
3367                         goto err_destroy_inner_tirs;
3368                 }
3369         }
3370
3371         if (!inner_ttc || !mlx5e_tunnel_inner_ft_supported(priv->mdev))
3372                 goto out;
3373
3374         for (i = 0; i < MLX5E_NUM_INDIR_TIRS; i++) {
3375                 memset(in, 0, inlen);
3376                 tir = &priv->inner_indir_tir[i];
3377                 tirc = MLX5_ADDR_OF(create_tir_in, in, ctx);
3378                 mlx5e_build_inner_indir_tir_ctx(priv, i, tirc);
3379                 err = mlx5e_create_tir(priv->mdev, tir, in);
3380                 if (err) {
3381                         mlx5_core_warn(priv->mdev, "create inner indirect tirs failed, %d\n", err);
3382                         goto err_destroy_inner_tirs;
3383                 }
3384         }
3385
3386 out:
3387         kvfree(in);
3388
3389         return 0;
3390
3391 err_destroy_inner_tirs:
3392         for (i--; i >= 0; i--)
3393                 mlx5e_destroy_tir(priv->mdev, &priv->inner_indir_tir[i]);
3394
3395         for (tt--; tt >= 0; tt--)
3396                 mlx5e_destroy_tir(priv->mdev, &priv->indir_tir[tt]);
3397
3398         kvfree(in);
3399
3400         return err;
3401 }
3402
3403 int mlx5e_create_direct_tirs(struct mlx5e_priv *priv, struct mlx5e_tir *tirs)
3404 {
3405         struct mlx5e_tir *tir;
3406         void *tirc;
3407         int inlen;
3408         int err = 0;
3409         u32 *in;
3410         int ix;
3411
3412         inlen = MLX5_ST_SZ_BYTES(create_tir_in);
3413         in = kvzalloc(inlen, GFP_KERNEL);
3414         if (!in)
3415                 return -ENOMEM;
3416
3417         for (ix = 0; ix < priv->max_nch; ix++) {
3418                 memset(in, 0, inlen);
3419                 tir = &tirs[ix];
3420                 tirc = MLX5_ADDR_OF(create_tir_in, in, ctx);
3421                 mlx5e_build_direct_tir_ctx(priv, tir->rqt.rqtn, tirc);
3422                 err = mlx5e_create_tir(priv->mdev, tir, in);
3423                 if (unlikely(err))
3424                         goto err_destroy_ch_tirs;
3425         }
3426
3427         goto out;
3428
3429 err_destroy_ch_tirs:
3430         mlx5_core_warn(priv->mdev, "create tirs failed, %d\n", err);
3431         for (ix--; ix >= 0; ix--)
3432                 mlx5e_destroy_tir(priv->mdev, &tirs[ix]);
3433
3434 out:
3435         kvfree(in);
3436
3437         return err;
3438 }
3439
3440 void mlx5e_destroy_indirect_tirs(struct mlx5e_priv *priv)
3441 {
3442         int i;
3443
3444         for (i = 0; i < MLX5E_NUM_INDIR_TIRS; i++)
3445                 mlx5e_destroy_tir(priv->mdev, &priv->indir_tir[i]);
3446
3447         /* Verify inner tirs resources allocated */
3448         if (!priv->inner_indir_tir[0].tirn)
3449                 return;
3450
3451         for (i = 0; i < MLX5E_NUM_INDIR_TIRS; i++)
3452                 mlx5e_destroy_tir(priv->mdev, &priv->inner_indir_tir[i]);
3453 }
3454
3455 void mlx5e_destroy_direct_tirs(struct mlx5e_priv *priv, struct mlx5e_tir *tirs)
3456 {
3457         int i;
3458
3459         for (i = 0; i < priv->max_nch; i++)
3460                 mlx5e_destroy_tir(priv->mdev, &tirs[i]);
3461 }
3462
3463 static int mlx5e_modify_channels_scatter_fcs(struct mlx5e_channels *chs, bool enable)
3464 {
3465         int err = 0;
3466         int i;
3467
3468         for (i = 0; i < chs->num; i++) {
3469                 err = mlx5e_modify_rq_scatter_fcs(&chs->c[i]->rq, enable);
3470                 if (err)
3471                         return err;
3472         }
3473
3474         return 0;
3475 }
3476
3477 static int mlx5e_modify_channels_vsd(struct mlx5e_channels *chs, bool vsd)
3478 {
3479         int err = 0;
3480         int i;
3481
3482         for (i = 0; i < chs->num; i++) {
3483                 err = mlx5e_modify_rq_vsd(&chs->c[i]->rq, vsd);
3484                 if (err)
3485                         return err;
3486         }
3487
3488         return 0;
3489 }
3490
3491 static int mlx5e_setup_tc_mqprio(struct mlx5e_priv *priv,
3492                                  struct tc_mqprio_qopt *mqprio)
3493 {
3494         struct mlx5e_channels new_channels = {};
3495         u8 tc = mqprio->num_tc;
3496         int err = 0;
3497
3498         mqprio->hw = TC_MQPRIO_HW_OFFLOAD_TCS;
3499
3500         if (tc && tc != MLX5E_MAX_NUM_TC)
3501                 return -EINVAL;
3502
3503         mutex_lock(&priv->state_lock);
3504
3505         new_channels.params = priv->channels.params;
3506         new_channels.params.num_tc = tc ? tc : 1;
3507
3508         if (!test_bit(MLX5E_STATE_OPENED, &priv->state)) {
3509                 priv->channels.params = new_channels.params;
3510                 goto out;
3511         }
3512
3513         err = mlx5e_safe_switch_channels(priv, &new_channels,
3514                                          mlx5e_num_channels_changed_ctx, NULL);
3515         if (err)
3516                 goto out;
3517
3518         priv->max_opened_tc = max_t(u8, priv->max_opened_tc,
3519                                     new_channels.params.num_tc);
3520 out:
3521         mutex_unlock(&priv->state_lock);
3522         return err;
3523 }
3524
3525 static LIST_HEAD(mlx5e_block_cb_list);
3526
3527 static int mlx5e_setup_tc(struct net_device *dev, enum tc_setup_type type,
3528                           void *type_data)
3529 {
3530         struct mlx5e_priv *priv = netdev_priv(dev);
3531
3532         switch (type) {
3533         case TC_SETUP_BLOCK: {
3534                 struct flow_block_offload *f = type_data;
3535
3536                 f->unlocked_driver_cb = true;
3537                 return flow_block_cb_setup_simple(type_data,
3538                                                   &mlx5e_block_cb_list,
3539                                                   mlx5e_setup_tc_block_cb,
3540                                                   priv, priv, true);
3541         }
3542         case TC_SETUP_QDISC_MQPRIO:
3543                 return mlx5e_setup_tc_mqprio(priv, type_data);
3544         default:
3545                 return -EOPNOTSUPP;
3546         }
3547 }
3548
3549 void mlx5e_fold_sw_stats64(struct mlx5e_priv *priv, struct rtnl_link_stats64 *s)
3550 {
3551         int i;
3552
3553         for (i = 0; i < priv->max_nch; i++) {
3554                 struct mlx5e_channel_stats *channel_stats = &priv->channel_stats[i];
3555                 struct mlx5e_rq_stats *xskrq_stats = &channel_stats->xskrq;
3556                 struct mlx5e_rq_stats *rq_stats = &channel_stats->rq;
3557                 int j;
3558
3559                 s->rx_packets   += rq_stats->packets + xskrq_stats->packets;
3560                 s->rx_bytes     += rq_stats->bytes + xskrq_stats->bytes;
3561
3562                 for (j = 0; j < priv->max_opened_tc; j++) {
3563                         struct mlx5e_sq_stats *sq_stats = &channel_stats->sq[j];
3564
3565                         s->tx_packets    += sq_stats->packets;
3566                         s->tx_bytes      += sq_stats->bytes;
3567                         s->tx_dropped    += sq_stats->dropped;
3568                 }
3569         }
3570 }
3571
3572 void
3573 mlx5e_get_stats(struct net_device *dev, struct rtnl_link_stats64 *stats)
3574 {
3575         struct mlx5e_priv *priv = netdev_priv(dev);
3576         struct mlx5e_vport_stats *vstats = &priv->stats.vport;
3577         struct mlx5e_pport_stats *pstats = &priv->stats.pport;
3578
3579         /* In switchdev mode, monitor counters doesn't monitor
3580          * rx/tx stats of 802_3. The update stats mechanism
3581          * should keep the 802_3 layout counters updated
3582          */
3583         if (!mlx5e_monitor_counter_supported(priv) ||
3584             mlx5e_is_uplink_rep(priv)) {
3585                 /* update HW stats in background for next time */
3586                 mlx5e_queue_update_stats(priv);
3587         }
3588
3589         if (mlx5e_is_uplink_rep(priv)) {
3590                 stats->rx_packets = PPORT_802_3_GET(pstats, a_frames_received_ok);
3591                 stats->rx_bytes   = PPORT_802_3_GET(pstats, a_octets_received_ok);
3592                 stats->tx_packets = PPORT_802_3_GET(pstats, a_frames_transmitted_ok);
3593                 stats->tx_bytes   = PPORT_802_3_GET(pstats, a_octets_transmitted_ok);
3594         } else {
3595                 mlx5e_fold_sw_stats64(priv, stats);
3596         }
3597
3598         stats->rx_dropped = priv->stats.qcnt.rx_out_of_buffer;
3599
3600         stats->rx_length_errors =
3601                 PPORT_802_3_GET(pstats, a_in_range_length_errors) +
3602                 PPORT_802_3_GET(pstats, a_out_of_range_length_field) +
3603                 PPORT_802_3_GET(pstats, a_frame_too_long_errors);
3604         stats->rx_crc_errors =
3605                 PPORT_802_3_GET(pstats, a_frame_check_sequence_errors);
3606         stats->rx_frame_errors = PPORT_802_3_GET(pstats, a_alignment_errors);
3607         stats->tx_aborted_errors = PPORT_2863_GET(pstats, if_out_discards);
3608         stats->rx_errors = stats->rx_length_errors + stats->rx_crc_errors +
3609                            stats->rx_frame_errors;
3610         stats->tx_errors = stats->tx_aborted_errors + stats->tx_carrier_errors;
3611
3612         /* vport multicast also counts packets that are dropped due to steering
3613          * or rx out of buffer
3614          */
3615         stats->multicast =
3616                 VPORT_COUNTER_GET(vstats, received_eth_multicast.packets);
3617 }
3618
3619 static void mlx5e_set_rx_mode(struct net_device *dev)
3620 {
3621         struct mlx5e_priv *priv = netdev_priv(dev);
3622
3623         queue_work(priv->wq, &priv->set_rx_mode_work);
3624 }
3625
3626 static int mlx5e_set_mac(struct net_device *netdev, void *addr)
3627 {
3628         struct mlx5e_priv *priv = netdev_priv(netdev);
3629         struct sockaddr *saddr = addr;
3630
3631         if (!is_valid_ether_addr(saddr->sa_data))
3632                 return -EADDRNOTAVAIL;
3633
3634         netif_addr_lock_bh(netdev);
3635         ether_addr_copy(netdev->dev_addr, saddr->sa_data);
3636         netif_addr_unlock_bh(netdev);
3637
3638         queue_work(priv->wq, &priv->set_rx_mode_work);
3639
3640         return 0;
3641 }
3642
3643 #define MLX5E_SET_FEATURE(features, feature, enable)    \
3644         do {                                            \
3645                 if (enable)                             \
3646                         *features |= feature;           \
3647                 else                                    \
3648                         *features &= ~feature;          \
3649         } while (0)
3650
3651 typedef int (*mlx5e_feature_handler)(struct net_device *netdev, bool enable);
3652
3653 static int set_feature_lro(struct net_device *netdev, bool enable)
3654 {
3655         struct mlx5e_priv *priv = netdev_priv(netdev);
3656         struct mlx5_core_dev *mdev = priv->mdev;
3657         struct mlx5e_channels new_channels = {};
3658         struct mlx5e_params *old_params;
3659         int err = 0;
3660         bool reset;
3661
3662         mutex_lock(&priv->state_lock);
3663
3664         if (enable && priv->xsk.refcnt) {
3665                 netdev_warn(netdev, "LRO is incompatible with AF_XDP (%hu XSKs are active)\n",
3666                             priv->xsk.refcnt);
3667                 err = -EINVAL;
3668                 goto out;
3669         }
3670
3671         old_params = &priv->channels.params;
3672         if (enable && !MLX5E_GET_PFLAG(old_params, MLX5E_PFLAG_RX_STRIDING_RQ)) {
3673                 netdev_warn(netdev, "can't set LRO with legacy RQ\n");
3674                 err = -EINVAL;
3675                 goto out;
3676         }
3677
3678         reset = test_bit(MLX5E_STATE_OPENED, &priv->state);
3679
3680         new_channels.params = *old_params;
3681         new_channels.params.lro_en = enable;
3682
3683         if (old_params->rq_wq_type != MLX5_WQ_TYPE_CYCLIC) {
3684                 if (mlx5e_rx_mpwqe_is_linear_skb(mdev, old_params, NULL) ==
3685                     mlx5e_rx_mpwqe_is_linear_skb(mdev, &new_channels.params, NULL))
3686                         reset = false;
3687         }
3688
3689         if (!reset) {
3690                 *old_params = new_channels.params;
3691                 err = mlx5e_modify_tirs_lro(priv);
3692                 goto out;
3693         }
3694
3695         err = mlx5e_safe_switch_channels(priv, &new_channels,
3696                                          mlx5e_modify_tirs_lro_ctx, NULL);
3697 out:
3698         mutex_unlock(&priv->state_lock);
3699         return err;
3700 }
3701
3702 static int set_feature_cvlan_filter(struct net_device *netdev, bool enable)
3703 {
3704         struct mlx5e_priv *priv = netdev_priv(netdev);
3705
3706         if (enable)
3707                 mlx5e_enable_cvlan_filter(priv);
3708         else
3709                 mlx5e_disable_cvlan_filter(priv);
3710
3711         return 0;
3712 }
3713
3714 #if IS_ENABLED(CONFIG_MLX5_CLS_ACT)
3715 static int set_feature_tc_num_filters(struct net_device *netdev, bool enable)
3716 {
3717         struct mlx5e_priv *priv = netdev_priv(netdev);
3718
3719         if (!enable && mlx5e_tc_num_filters(priv, MLX5_TC_FLAG(NIC_OFFLOAD))) {
3720                 netdev_err(netdev,
3721                            "Active offloaded tc filters, can't turn hw_tc_offload off\n");
3722                 return -EINVAL;
3723         }
3724
3725         return 0;
3726 }
3727 #endif
3728
3729 static int set_feature_rx_all(struct net_device *netdev, bool enable)
3730 {
3731         struct mlx5e_priv *priv = netdev_priv(netdev);
3732         struct mlx5_core_dev *mdev = priv->mdev;
3733
3734         return mlx5_set_port_fcs(mdev, !enable);
3735 }
3736
3737 static int set_feature_rx_fcs(struct net_device *netdev, bool enable)
3738 {
3739         struct mlx5e_priv *priv = netdev_priv(netdev);
3740         int err;
3741
3742         mutex_lock(&priv->state_lock);
3743
3744         priv->channels.params.scatter_fcs_en = enable;
3745         err = mlx5e_modify_channels_scatter_fcs(&priv->channels, enable);
3746         if (err)
3747                 priv->channels.params.scatter_fcs_en = !enable;
3748
3749         mutex_unlock(&priv->state_lock);
3750
3751         return err;
3752 }
3753
3754 static int set_feature_rx_vlan(struct net_device *netdev, bool enable)
3755 {
3756         struct mlx5e_priv *priv = netdev_priv(netdev);
3757         int err = 0;
3758
3759         mutex_lock(&priv->state_lock);
3760
3761         priv->channels.params.vlan_strip_disable = !enable;
3762         if (!test_bit(MLX5E_STATE_OPENED, &priv->state))
3763                 goto unlock;
3764
3765         err = mlx5e_modify_channels_vsd(&priv->channels, !enable);
3766         if (err)
3767                 priv->channels.params.vlan_strip_disable = enable;
3768
3769 unlock:
3770         mutex_unlock(&priv->state_lock);
3771
3772         return err;
3773 }
3774
3775 #ifdef CONFIG_MLX5_EN_ARFS
3776 static int set_feature_arfs(struct net_device *netdev, bool enable)
3777 {
3778         struct mlx5e_priv *priv = netdev_priv(netdev);
3779         int err;
3780
3781         if (enable)
3782                 err = mlx5e_arfs_enable(priv);
3783         else
3784                 err = mlx5e_arfs_disable(priv);
3785
3786         return err;
3787 }
3788 #endif
3789
3790 static int mlx5e_handle_feature(struct net_device *netdev,
3791                                 netdev_features_t *features,
3792                                 netdev_features_t wanted_features,
3793                                 netdev_features_t feature,
3794                                 mlx5e_feature_handler feature_handler)
3795 {
3796         netdev_features_t changes = wanted_features ^ netdev->features;
3797         bool enable = !!(wanted_features & feature);
3798         int err;
3799
3800         if (!(changes & feature))
3801                 return 0;
3802
3803         err = feature_handler(netdev, enable);
3804         if (err) {
3805                 netdev_err(netdev, "%s feature %pNF failed, err %d\n",
3806                            enable ? "Enable" : "Disable", &feature, err);
3807                 return err;
3808         }
3809
3810         MLX5E_SET_FEATURE(features, feature, enable);
3811         return 0;
3812 }
3813
3814 int mlx5e_set_features(struct net_device *netdev, netdev_features_t features)
3815 {
3816         netdev_features_t oper_features = netdev->features;
3817         int err = 0;
3818
3819 #define MLX5E_HANDLE_FEATURE(feature, handler) \
3820         mlx5e_handle_feature(netdev, &oper_features, features, feature, handler)
3821
3822         err |= MLX5E_HANDLE_FEATURE(NETIF_F_LRO, set_feature_lro);
3823         err |= MLX5E_HANDLE_FEATURE(NETIF_F_HW_VLAN_CTAG_FILTER,
3824                                     set_feature_cvlan_filter);
3825 #if IS_ENABLED(CONFIG_MLX5_CLS_ACT)
3826         err |= MLX5E_HANDLE_FEATURE(NETIF_F_HW_TC, set_feature_tc_num_filters);
3827 #endif
3828         err |= MLX5E_HANDLE_FEATURE(NETIF_F_RXALL, set_feature_rx_all);
3829         err |= MLX5E_HANDLE_FEATURE(NETIF_F_RXFCS, set_feature_rx_fcs);
3830         err |= MLX5E_HANDLE_FEATURE(NETIF_F_HW_VLAN_CTAG_RX, set_feature_rx_vlan);
3831 #ifdef CONFIG_MLX5_EN_ARFS
3832         err |= MLX5E_HANDLE_FEATURE(NETIF_F_NTUPLE, set_feature_arfs);
3833 #endif
3834
3835         if (err) {
3836                 netdev->features = oper_features;
3837                 return -EINVAL;
3838         }
3839
3840         return 0;
3841 }
3842
3843 static netdev_features_t mlx5e_fix_features(struct net_device *netdev,
3844                                             netdev_features_t features)
3845 {
3846         struct mlx5e_priv *priv = netdev_priv(netdev);
3847         struct mlx5e_params *params;
3848
3849         mutex_lock(&priv->state_lock);
3850         params = &priv->channels.params;
3851         if (!bitmap_empty(priv->fs.vlan.active_svlans, VLAN_N_VID)) {
3852                 /* HW strips the outer C-tag header, this is a problem
3853                  * for S-tag traffic.
3854                  */
3855                 features &= ~NETIF_F_HW_VLAN_CTAG_RX;
3856                 if (!params->vlan_strip_disable)
3857                         netdev_warn(netdev, "Dropping C-tag vlan stripping offload due to S-tag vlan\n");
3858         }
3859         if (!MLX5E_GET_PFLAG(params, MLX5E_PFLAG_RX_STRIDING_RQ)) {
3860                 if (features & NETIF_F_LRO) {
3861                         netdev_warn(netdev, "Disabling LRO, not supported in legacy RQ\n");
3862                         features &= ~NETIF_F_LRO;
3863                 }
3864         }
3865
3866         if (MLX5E_GET_PFLAG(params, MLX5E_PFLAG_RX_CQE_COMPRESS)) {
3867                 features &= ~NETIF_F_RXHASH;
3868                 if (netdev->features & NETIF_F_RXHASH)
3869                         netdev_warn(netdev, "Disabling rxhash, not supported when CQE compress is active\n");
3870         }
3871
3872         mutex_unlock(&priv->state_lock);
3873
3874         return features;
3875 }
3876
3877 static bool mlx5e_xsk_validate_mtu(struct net_device *netdev,
3878                                    struct mlx5e_channels *chs,
3879                                    struct mlx5e_params *new_params,
3880                                    struct mlx5_core_dev *mdev)
3881 {
3882         u16 ix;
3883
3884         for (ix = 0; ix < chs->params.num_channels; ix++) {
3885                 struct xdp_umem *umem = mlx5e_xsk_get_umem(&chs->params, chs->params.xsk, ix);
3886                 struct mlx5e_xsk_param xsk;
3887
3888                 if (!umem)
3889                         continue;
3890
3891                 mlx5e_build_xsk_param(umem, &xsk);
3892
3893                 if (!mlx5e_validate_xsk_param(new_params, &xsk, mdev)) {
3894                         u32 hr = mlx5e_get_linear_rq_headroom(new_params, &xsk);
3895                         int max_mtu_frame, max_mtu_page, max_mtu;
3896
3897                         /* Two criteria must be met:
3898                          * 1. HW MTU + all headrooms <= XSK frame size.
3899                          * 2. Size of SKBs allocated on XDP_PASS <= PAGE_SIZE.
3900                          */
3901                         max_mtu_frame = MLX5E_HW2SW_MTU(new_params, xsk.chunk_size - hr);
3902                         max_mtu_page = mlx5e_xdp_max_mtu(new_params, &xsk);
3903                         max_mtu = min(max_mtu_frame, max_mtu_page);
3904
3905                         netdev_err(netdev, "MTU %d is too big for an XSK running on channel %hu. Try MTU <= %d\n",
3906                                    new_params->sw_mtu, ix, max_mtu);
3907                         return false;
3908                 }
3909         }
3910
3911         return true;
3912 }
3913
3914 int mlx5e_change_mtu(struct net_device *netdev, int new_mtu,
3915                      mlx5e_fp_preactivate preactivate)
3916 {
3917         struct mlx5e_priv *priv = netdev_priv(netdev);
3918         struct mlx5e_channels new_channels = {};
3919         struct mlx5e_params *params;
3920         int err = 0;
3921         bool reset;
3922
3923         mutex_lock(&priv->state_lock);
3924
3925         params = &priv->channels.params;
3926
3927         reset = !params->lro_en;
3928         reset = reset && test_bit(MLX5E_STATE_OPENED, &priv->state);
3929
3930         new_channels.params = *params;
3931         new_channels.params.sw_mtu = new_mtu;
3932
3933         if (params->xdp_prog &&
3934             !mlx5e_rx_is_linear_skb(&new_channels.params, NULL)) {
3935                 netdev_err(netdev, "MTU(%d) > %d is not allowed while XDP enabled\n",
3936                            new_mtu, mlx5e_xdp_max_mtu(params, NULL));
3937                 err = -EINVAL;
3938                 goto out;
3939         }
3940
3941         if (priv->xsk.refcnt &&
3942             !mlx5e_xsk_validate_mtu(netdev, &priv->channels,
3943                                     &new_channels.params, priv->mdev)) {
3944                 err = -EINVAL;
3945                 goto out;
3946         }
3947
3948         if (params->rq_wq_type == MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ) {
3949                 bool is_linear = mlx5e_rx_mpwqe_is_linear_skb(priv->mdev,
3950                                                               &new_channels.params,
3951                                                               NULL);
3952                 u8 ppw_old = mlx5e_mpwqe_log_pkts_per_wqe(params, NULL);
3953                 u8 ppw_new = mlx5e_mpwqe_log_pkts_per_wqe(&new_channels.params, NULL);
3954
3955                 /* If XSK is active, XSK RQs are linear. */
3956                 is_linear |= priv->xsk.refcnt;
3957
3958                 /* Always reset in linear mode - hw_mtu is used in data path. */
3959                 reset = reset && (is_linear || (ppw_old != ppw_new));
3960         }
3961
3962         if (!reset) {
3963                 params->sw_mtu = new_mtu;
3964                 if (preactivate)
3965                         preactivate(priv, NULL);
3966                 netdev->mtu = params->sw_mtu;
3967                 goto out;
3968         }
3969
3970         err = mlx5e_safe_switch_channels(priv, &new_channels, preactivate, NULL);
3971         if (err)
3972                 goto out;
3973
3974         netdev->mtu = new_channels.params.sw_mtu;
3975
3976 out:
3977         mutex_unlock(&priv->state_lock);
3978         return err;
3979 }
3980
3981 static int mlx5e_change_nic_mtu(struct net_device *netdev, int new_mtu)
3982 {
3983         return mlx5e_change_mtu(netdev, new_mtu, mlx5e_set_dev_port_mtu_ctx);
3984 }
3985
3986 int mlx5e_hwstamp_set(struct mlx5e_priv *priv, struct ifreq *ifr)
3987 {
3988         struct hwtstamp_config config;
3989         int err;
3990
3991         if (!MLX5_CAP_GEN(priv->mdev, device_frequency_khz) ||
3992             (mlx5_clock_get_ptp_index(priv->mdev) == -1))
3993                 return -EOPNOTSUPP;
3994
3995         if (copy_from_user(&config, ifr->ifr_data, sizeof(config)))
3996                 return -EFAULT;
3997
3998         /* TX HW timestamp */
3999         switch (config.tx_type) {
4000         case HWTSTAMP_TX_OFF:
4001         case HWTSTAMP_TX_ON:
4002                 break;
4003         default:
4004                 return -ERANGE;
4005         }
4006
4007         mutex_lock(&priv->state_lock);
4008         /* RX HW timestamp */
4009         switch (config.rx_filter) {
4010         case HWTSTAMP_FILTER_NONE:
4011                 /* Reset CQE compression to Admin default */
4012                 mlx5e_modify_rx_cqe_compression_locked(priv, priv->channels.params.rx_cqe_compress_def);
4013                 break;
4014         case HWTSTAMP_FILTER_ALL:
4015         case HWTSTAMP_FILTER_SOME:
4016         case HWTSTAMP_FILTER_PTP_V1_L4_EVENT:
4017         case HWTSTAMP_FILTER_PTP_V1_L4_SYNC:
4018         case HWTSTAMP_FILTER_PTP_V1_L4_DELAY_REQ:
4019         case HWTSTAMP_FILTER_PTP_V2_L4_EVENT:
4020         case HWTSTAMP_FILTER_PTP_V2_L4_SYNC:
4021         case HWTSTAMP_FILTER_PTP_V2_L4_DELAY_REQ:
4022         case HWTSTAMP_FILTER_PTP_V2_L2_EVENT:
4023         case HWTSTAMP_FILTER_PTP_V2_L2_SYNC:
4024         case HWTSTAMP_FILTER_PTP_V2_L2_DELAY_REQ:
4025         case HWTSTAMP_FILTER_PTP_V2_EVENT:
4026         case HWTSTAMP_FILTER_PTP_V2_SYNC:
4027         case HWTSTAMP_FILTER_PTP_V2_DELAY_REQ:
4028         case HWTSTAMP_FILTER_NTP_ALL:
4029                 /* Disable CQE compression */
4030                 if (MLX5E_GET_PFLAG(&priv->channels.params, MLX5E_PFLAG_RX_CQE_COMPRESS))
4031                         netdev_warn(priv->netdev, "Disabling RX cqe compression\n");
4032                 err = mlx5e_modify_rx_cqe_compression_locked(priv, false);
4033                 if (err) {
4034                         netdev_err(priv->netdev, "Failed disabling cqe compression err=%d\n", err);
4035                         mutex_unlock(&priv->state_lock);
4036                         return err;
4037                 }
4038                 config.rx_filter = HWTSTAMP_FILTER_ALL;
4039                 break;
4040         default:
4041                 mutex_unlock(&priv->state_lock);
4042                 return -ERANGE;
4043         }
4044
4045         memcpy(&priv->tstamp, &config, sizeof(config));
4046         mutex_unlock(&priv->state_lock);
4047
4048         /* might need to fix some features */
4049         netdev_update_features(priv->netdev);
4050
4051         return copy_to_user(ifr->ifr_data, &config,
4052                             sizeof(config)) ? -EFAULT : 0;
4053 }
4054
4055 int mlx5e_hwstamp_get(struct mlx5e_priv *priv, struct ifreq *ifr)
4056 {
4057         struct hwtstamp_config *cfg = &priv->tstamp;
4058
4059         if (!MLX5_CAP_GEN(priv->mdev, device_frequency_khz))
4060                 return -EOPNOTSUPP;
4061
4062         return copy_to_user(ifr->ifr_data, cfg, sizeof(*cfg)) ? -EFAULT : 0;
4063 }
4064
4065 static int mlx5e_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
4066 {
4067         struct mlx5e_priv *priv = netdev_priv(dev);
4068
4069         switch (cmd) {
4070         case SIOCSHWTSTAMP:
4071                 return mlx5e_hwstamp_set(priv, ifr);
4072         case SIOCGHWTSTAMP:
4073                 return mlx5e_hwstamp_get(priv, ifr);
4074         default:
4075                 return -EOPNOTSUPP;
4076         }
4077 }
4078
4079 #ifdef CONFIG_MLX5_ESWITCH
4080 int mlx5e_set_vf_mac(struct net_device *dev, int vf, u8 *mac)
4081 {
4082         struct mlx5e_priv *priv = netdev_priv(dev);
4083         struct mlx5_core_dev *mdev = priv->mdev;
4084
4085         return mlx5_eswitch_set_vport_mac(mdev->priv.eswitch, vf + 1, mac);
4086 }
4087
4088 static int mlx5e_set_vf_vlan(struct net_device *dev, int vf, u16 vlan, u8 qos,
4089                              __be16 vlan_proto)
4090 {
4091         struct mlx5e_priv *priv = netdev_priv(dev);
4092         struct mlx5_core_dev *mdev = priv->mdev;
4093
4094         if (vlan_proto != htons(ETH_P_8021Q))
4095                 return -EPROTONOSUPPORT;
4096
4097         return mlx5_eswitch_set_vport_vlan(mdev->priv.eswitch, vf + 1,
4098                                            vlan, qos);
4099 }
4100
4101 static int mlx5e_set_vf_spoofchk(struct net_device *dev, int vf, bool setting)
4102 {
4103         struct mlx5e_priv *priv = netdev_priv(dev);
4104         struct mlx5_core_dev *mdev = priv->mdev;
4105
4106         return mlx5_eswitch_set_vport_spoofchk(mdev->priv.eswitch, vf + 1, setting);
4107 }
4108
4109 static int mlx5e_set_vf_trust(struct net_device *dev, int vf, bool setting)
4110 {
4111         struct mlx5e_priv *priv = netdev_priv(dev);
4112         struct mlx5_core_dev *mdev = priv->mdev;
4113
4114         return mlx5_eswitch_set_vport_trust(mdev->priv.eswitch, vf + 1, setting);
4115 }
4116
4117 int mlx5e_set_vf_rate(struct net_device *dev, int vf, int min_tx_rate,
4118                       int max_tx_rate)
4119 {
4120         struct mlx5e_priv *priv = netdev_priv(dev);
4121         struct mlx5_core_dev *mdev = priv->mdev;
4122
4123         return mlx5_eswitch_set_vport_rate(mdev->priv.eswitch, vf + 1,
4124                                            max_tx_rate, min_tx_rate);
4125 }
4126
4127 static int mlx5_vport_link2ifla(u8 esw_link)
4128 {
4129         switch (esw_link) {
4130         case MLX5_VPORT_ADMIN_STATE_DOWN:
4131                 return IFLA_VF_LINK_STATE_DISABLE;
4132         case MLX5_VPORT_ADMIN_STATE_UP:
4133                 return IFLA_VF_LINK_STATE_ENABLE;
4134         }
4135         return IFLA_VF_LINK_STATE_AUTO;
4136 }
4137
4138 static int mlx5_ifla_link2vport(u8 ifla_link)
4139 {
4140         switch (ifla_link) {
4141         case IFLA_VF_LINK_STATE_DISABLE:
4142                 return MLX5_VPORT_ADMIN_STATE_DOWN;
4143         case IFLA_VF_LINK_STATE_ENABLE:
4144                 return MLX5_VPORT_ADMIN_STATE_UP;
4145         }
4146         return MLX5_VPORT_ADMIN_STATE_AUTO;
4147 }
4148
4149 static int mlx5e_set_vf_link_state(struct net_device *dev, int vf,
4150                                    int link_state)
4151 {
4152         struct mlx5e_priv *priv = netdev_priv(dev);
4153         struct mlx5_core_dev *mdev = priv->mdev;
4154
4155         return mlx5_eswitch_set_vport_state(mdev->priv.eswitch, vf + 1,
4156                                             mlx5_ifla_link2vport(link_state));
4157 }
4158
4159 int mlx5e_get_vf_config(struct net_device *dev,
4160                         int vf, struct ifla_vf_info *ivi)
4161 {
4162         struct mlx5e_priv *priv = netdev_priv(dev);
4163         struct mlx5_core_dev *mdev = priv->mdev;
4164         int err;
4165
4166         err = mlx5_eswitch_get_vport_config(mdev->priv.eswitch, vf + 1, ivi);
4167         if (err)
4168                 return err;
4169         ivi->linkstate = mlx5_vport_link2ifla(ivi->linkstate);
4170         return 0;
4171 }
4172
4173 int mlx5e_get_vf_stats(struct net_device *dev,
4174                        int vf, struct ifla_vf_stats *vf_stats)
4175 {
4176         struct mlx5e_priv *priv = netdev_priv(dev);
4177         struct mlx5_core_dev *mdev = priv->mdev;
4178
4179         return mlx5_eswitch_get_vport_stats(mdev->priv.eswitch, vf + 1,
4180                                             vf_stats);
4181 }
4182 #endif
4183
4184 struct mlx5e_vxlan_work {
4185         struct work_struct      work;
4186         struct mlx5e_priv       *priv;
4187         u16                     port;
4188 };
4189
4190 static void mlx5e_vxlan_add_work(struct work_struct *work)
4191 {
4192         struct mlx5e_vxlan_work *vxlan_work =
4193                 container_of(work, struct mlx5e_vxlan_work, work);
4194         struct mlx5e_priv *priv = vxlan_work->priv;
4195         u16 port = vxlan_work->port;
4196
4197         mutex_lock(&priv->state_lock);
4198         mlx5_vxlan_add_port(priv->mdev->vxlan, port);
4199         mutex_unlock(&priv->state_lock);
4200
4201         kfree(vxlan_work);
4202 }
4203
4204 static void mlx5e_vxlan_del_work(struct work_struct *work)
4205 {
4206         struct mlx5e_vxlan_work *vxlan_work =
4207                 container_of(work, struct mlx5e_vxlan_work, work);
4208         struct mlx5e_priv *priv         = vxlan_work->priv;
4209         u16 port = vxlan_work->port;
4210
4211         mutex_lock(&priv->state_lock);
4212         mlx5_vxlan_del_port(priv->mdev->vxlan, port);
4213         mutex_unlock(&priv->state_lock);
4214         kfree(vxlan_work);
4215 }
4216
4217 static void mlx5e_vxlan_queue_work(struct mlx5e_priv *priv, u16 port, int add)
4218 {
4219         struct mlx5e_vxlan_work *vxlan_work;
4220
4221         vxlan_work = kmalloc(sizeof(*vxlan_work), GFP_ATOMIC);
4222         if (!vxlan_work)
4223                 return;
4224
4225         if (add)
4226                 INIT_WORK(&vxlan_work->work, mlx5e_vxlan_add_work);
4227         else
4228                 INIT_WORK(&vxlan_work->work, mlx5e_vxlan_del_work);
4229
4230         vxlan_work->priv = priv;
4231         vxlan_work->port = port;
4232         queue_work(priv->wq, &vxlan_work->work);
4233 }
4234
4235 void mlx5e_add_vxlan_port(struct net_device *netdev, struct udp_tunnel_info *ti)
4236 {
4237         struct mlx5e_priv *priv = netdev_priv(netdev);
4238
4239         if (ti->type != UDP_TUNNEL_TYPE_VXLAN)
4240                 return;
4241
4242         if (!mlx5_vxlan_allowed(priv->mdev->vxlan))
4243                 return;
4244
4245         mlx5e_vxlan_queue_work(priv, be16_to_cpu(ti->port), 1);
4246 }
4247
4248 void mlx5e_del_vxlan_port(struct net_device *netdev, struct udp_tunnel_info *ti)
4249 {
4250         struct mlx5e_priv *priv = netdev_priv(netdev);
4251
4252         if (ti->type != UDP_TUNNEL_TYPE_VXLAN)
4253                 return;
4254
4255         if (!mlx5_vxlan_allowed(priv->mdev->vxlan))
4256                 return;
4257
4258         mlx5e_vxlan_queue_work(priv, be16_to_cpu(ti->port), 0);
4259 }
4260
4261 static netdev_features_t mlx5e_tunnel_features_check(struct mlx5e_priv *priv,
4262                                                      struct sk_buff *skb,
4263                                                      netdev_features_t features)
4264 {
4265         unsigned int offset = 0;
4266         struct udphdr *udph;
4267         u8 proto;
4268         u16 port;
4269
4270         switch (vlan_get_protocol(skb)) {
4271         case htons(ETH_P_IP):
4272                 proto = ip_hdr(skb)->protocol;
4273                 break;
4274         case htons(ETH_P_IPV6):
4275                 proto = ipv6_find_hdr(skb, &offset, -1, NULL, NULL);
4276                 break;
4277         default:
4278                 goto out;
4279         }
4280
4281         switch (proto) {
4282         case IPPROTO_GRE:
4283                 return features;
4284         case IPPROTO_IPIP:
4285         case IPPROTO_IPV6:
4286                 if (mlx5e_tunnel_proto_supported(priv->mdev, IPPROTO_IPIP))
4287                         return features;
4288                 break;
4289         case IPPROTO_UDP:
4290                 udph = udp_hdr(skb);
4291                 port = be16_to_cpu(udph->dest);
4292
4293                 /* Verify if UDP port is being offloaded by HW */
4294                 if (mlx5_vxlan_lookup_port(priv->mdev->vxlan, port))
4295                         return features;
4296
4297 #if IS_ENABLED(CONFIG_GENEVE)
4298                 /* Support Geneve offload for default UDP port */
4299                 if (port == GENEVE_UDP_PORT && mlx5_geneve_tx_allowed(priv->mdev))
4300                         return features;
4301 #endif
4302         }
4303
4304 out:
4305         /* Disable CSUM and GSO if the udp dport is not offloaded by HW */
4306         return features & ~(NETIF_F_CSUM_MASK | NETIF_F_GSO_MASK);
4307 }
4308
4309 netdev_features_t mlx5e_features_check(struct sk_buff *skb,
4310                                        struct net_device *netdev,
4311                                        netdev_features_t features)
4312 {
4313         struct mlx5e_priv *priv = netdev_priv(netdev);
4314
4315         features = vlan_features_check(skb, features);
4316         features = vxlan_features_check(skb, features);
4317
4318 #ifdef CONFIG_MLX5_EN_IPSEC
4319         if (mlx5e_ipsec_feature_check(skb, netdev, features))
4320                 return features;
4321 #endif
4322
4323         /* Validate if the tunneled packet is being offloaded by HW */
4324         if (skb->encapsulation &&
4325             (features & NETIF_F_CSUM_MASK || features & NETIF_F_GSO_MASK))
4326                 return mlx5e_tunnel_features_check(priv, skb, features);
4327
4328         return features;
4329 }
4330
4331 static void mlx5e_tx_timeout_work(struct work_struct *work)
4332 {
4333         struct mlx5e_priv *priv = container_of(work, struct mlx5e_priv,
4334                                                tx_timeout_work);
4335         bool report_failed = false;
4336         int err;
4337         int i;
4338
4339         rtnl_lock();
4340         mutex_lock(&priv->state_lock);
4341
4342         if (!test_bit(MLX5E_STATE_OPENED, &priv->state))
4343                 goto unlock;
4344
4345         for (i = 0; i < priv->channels.num * priv->channels.params.num_tc; i++) {
4346                 struct netdev_queue *dev_queue =
4347                         netdev_get_tx_queue(priv->netdev, i);
4348                 struct mlx5e_txqsq *sq = priv->txq2sq[i];
4349
4350                 if (!netif_xmit_stopped(dev_queue))
4351                         continue;
4352
4353                 if (mlx5e_reporter_tx_timeout(sq))
4354                         report_failed = true;
4355         }
4356
4357         if (!report_failed)
4358                 goto unlock;
4359
4360         err = mlx5e_safe_reopen_channels(priv);
4361         if (err)
4362                 netdev_err(priv->netdev,
4363                            "mlx5e_safe_reopen_channels failed recovering from a tx_timeout, err(%d).\n",
4364                            err);
4365
4366 unlock:
4367         mutex_unlock(&priv->state_lock);
4368         rtnl_unlock();
4369 }
4370
4371 static void mlx5e_tx_timeout(struct net_device *dev, unsigned int txqueue)
4372 {
4373         struct mlx5e_priv *priv = netdev_priv(dev);
4374
4375         netdev_err(dev, "TX timeout detected\n");
4376         queue_work(priv->wq, &priv->tx_timeout_work);
4377 }
4378
4379 static int mlx5e_xdp_allowed(struct mlx5e_priv *priv, struct bpf_prog *prog)
4380 {
4381         struct net_device *netdev = priv->netdev;
4382         struct mlx5e_channels new_channels = {};
4383
4384         if (priv->channels.params.lro_en) {
4385                 netdev_warn(netdev, "can't set XDP while LRO is on, disable LRO first\n");
4386                 return -EINVAL;
4387         }
4388
4389         if (MLX5_IPSEC_DEV(priv->mdev)) {
4390                 netdev_warn(netdev, "can't set XDP with IPSec offload\n");
4391                 return -EINVAL;
4392         }
4393
4394         new_channels.params = priv->channels.params;
4395         new_channels.params.xdp_prog = prog;
4396
4397         /* No XSK params: AF_XDP can't be enabled yet at the point of setting
4398          * the XDP program.
4399          */
4400         if (!mlx5e_rx_is_linear_skb(&new_channels.params, NULL)) {
4401                 netdev_warn(netdev, "XDP is not allowed with MTU(%d) > %d\n",
4402                             new_channels.params.sw_mtu,
4403                             mlx5e_xdp_max_mtu(&new_channels.params, NULL));
4404                 return -EINVAL;
4405         }
4406
4407         return 0;
4408 }
4409
4410 static int mlx5e_xdp_set(struct net_device *netdev, struct bpf_prog *prog)
4411 {
4412         struct mlx5e_priv *priv = netdev_priv(netdev);
4413         struct bpf_prog *old_prog;
4414         bool reset, was_opened;
4415         int err = 0;
4416         int i;
4417
4418         mutex_lock(&priv->state_lock);
4419
4420         if (prog) {
4421                 err = mlx5e_xdp_allowed(priv, prog);
4422                 if (err)
4423                         goto unlock;
4424         }
4425
4426         was_opened = test_bit(MLX5E_STATE_OPENED, &priv->state);
4427         /* no need for full reset when exchanging programs */
4428         reset = (!priv->channels.params.xdp_prog || !prog);
4429
4430         if (was_opened && !reset)
4431                 /* num_channels is invariant here, so we can take the
4432                  * batched reference right upfront.
4433                  */
4434                 bpf_prog_add(prog, priv->channels.num);
4435
4436         if (was_opened && reset) {
4437                 struct mlx5e_channels new_channels = {};
4438
4439                 new_channels.params = priv->channels.params;
4440                 new_channels.params.xdp_prog = prog;
4441                 mlx5e_set_rq_type(priv->mdev, &new_channels.params);
4442                 old_prog = priv->channels.params.xdp_prog;
4443
4444                 err = mlx5e_safe_switch_channels(priv, &new_channels, NULL, NULL);
4445                 if (err)
4446                         goto unlock;
4447         } else {
4448                 /* exchange programs, extra prog reference we got from caller
4449                  * as long as we don't fail from this point onwards.
4450                  */
4451                 old_prog = xchg(&priv->channels.params.xdp_prog, prog);
4452         }
4453
4454         if (old_prog)
4455                 bpf_prog_put(old_prog);
4456
4457         if (!was_opened && reset) /* change RQ type according to priv->xdp_prog */
4458                 mlx5e_set_rq_type(priv->mdev, &priv->channels.params);
4459
4460         if (!was_opened || reset)
4461                 goto unlock;
4462
4463         /* exchanging programs w/o reset, we update ref counts on behalf
4464          * of the channels RQs here.
4465          */
4466         for (i = 0; i < priv->channels.num; i++) {
4467                 struct mlx5e_channel *c = priv->channels.c[i];
4468                 bool xsk_open = test_bit(MLX5E_CHANNEL_STATE_XSK, c->state);
4469
4470                 clear_bit(MLX5E_RQ_STATE_ENABLED, &c->rq.state);
4471                 if (xsk_open)
4472                         clear_bit(MLX5E_RQ_STATE_ENABLED, &c->xskrq.state);
4473                 napi_synchronize(&c->napi);
4474                 /* prevent mlx5e_poll_rx_cq from accessing rq->xdp_prog */
4475
4476                 old_prog = xchg(&c->rq.xdp_prog, prog);
4477                 if (old_prog)
4478                         bpf_prog_put(old_prog);
4479
4480                 if (xsk_open) {
4481                         old_prog = xchg(&c->xskrq.xdp_prog, prog);
4482                         if (old_prog)
4483                                 bpf_prog_put(old_prog);
4484                 }
4485
4486                 set_bit(MLX5E_RQ_STATE_ENABLED, &c->rq.state);
4487                 if (xsk_open)
4488                         set_bit(MLX5E_RQ_STATE_ENABLED, &c->xskrq.state);
4489                 /* napi_schedule in case we have missed anything */
4490                 napi_schedule(&c->napi);
4491         }
4492
4493 unlock:
4494         mutex_unlock(&priv->state_lock);
4495         return err;
4496 }
4497
4498 static u32 mlx5e_xdp_query(struct net_device *dev)
4499 {
4500         struct mlx5e_priv *priv = netdev_priv(dev);
4501         const struct bpf_prog *xdp_prog;
4502         u32 prog_id = 0;
4503
4504         mutex_lock(&priv->state_lock);
4505         xdp_prog = priv->channels.params.xdp_prog;
4506         if (xdp_prog)
4507                 prog_id = xdp_prog->aux->id;
4508         mutex_unlock(&priv->state_lock);
4509
4510         return prog_id;
4511 }
4512
4513 static int mlx5e_xdp(struct net_device *dev, struct netdev_bpf *xdp)
4514 {
4515         switch (xdp->command) {
4516         case XDP_SETUP_PROG:
4517                 return mlx5e_xdp_set(dev, xdp->prog);
4518         case XDP_QUERY_PROG:
4519                 xdp->prog_id = mlx5e_xdp_query(dev);
4520                 return 0;
4521         case XDP_SETUP_XSK_UMEM:
4522                 return mlx5e_xsk_setup_umem(dev, xdp->xsk.umem,
4523                                             xdp->xsk.queue_id);
4524         default:
4525                 return -EINVAL;
4526         }
4527 }
4528
4529 #ifdef CONFIG_MLX5_ESWITCH
4530 static int mlx5e_bridge_getlink(struct sk_buff *skb, u32 pid, u32 seq,
4531                                 struct net_device *dev, u32 filter_mask,
4532                                 int nlflags)
4533 {
4534         struct mlx5e_priv *priv = netdev_priv(dev);
4535         struct mlx5_core_dev *mdev = priv->mdev;
4536         u8 mode, setting;
4537         int err;
4538
4539         err = mlx5_eswitch_get_vepa(mdev->priv.eswitch, &setting);
4540         if (err)
4541                 return err;
4542         mode = setting ? BRIDGE_MODE_VEPA : BRIDGE_MODE_VEB;
4543         return ndo_dflt_bridge_getlink(skb, pid, seq, dev,
4544                                        mode,
4545                                        0, 0, nlflags, filter_mask, NULL);
4546 }
4547
4548 static int mlx5e_bridge_setlink(struct net_device *dev, struct nlmsghdr *nlh,
4549                                 u16 flags, struct netlink_ext_ack *extack)
4550 {
4551         struct mlx5e_priv *priv = netdev_priv(dev);
4552         struct mlx5_core_dev *mdev = priv->mdev;
4553         struct nlattr *attr, *br_spec;
4554         u16 mode = BRIDGE_MODE_UNDEF;
4555         u8 setting;
4556         int rem;
4557
4558         br_spec = nlmsg_find_attr(nlh, sizeof(struct ifinfomsg), IFLA_AF_SPEC);
4559         if (!br_spec)
4560                 return -EINVAL;
4561
4562         nla_for_each_nested(attr, br_spec, rem) {
4563                 if (nla_type(attr) != IFLA_BRIDGE_MODE)
4564                         continue;
4565
4566                 if (nla_len(attr) < sizeof(mode))
4567                         return -EINVAL;
4568
4569                 mode = nla_get_u16(attr);
4570                 if (mode > BRIDGE_MODE_VEPA)
4571                         return -EINVAL;
4572
4573                 break;
4574         }
4575
4576         if (mode == BRIDGE_MODE_UNDEF)
4577                 return -EINVAL;
4578
4579         setting = (mode == BRIDGE_MODE_VEPA) ?  1 : 0;
4580         return mlx5_eswitch_set_vepa(mdev->priv.eswitch, setting);
4581 }
4582 #endif
4583
4584 const struct net_device_ops mlx5e_netdev_ops = {
4585         .ndo_open                = mlx5e_open,
4586         .ndo_stop                = mlx5e_close,
4587         .ndo_start_xmit          = mlx5e_xmit,
4588         .ndo_setup_tc            = mlx5e_setup_tc,
4589         .ndo_select_queue        = mlx5e_select_queue,
4590         .ndo_get_stats64         = mlx5e_get_stats,
4591         .ndo_set_rx_mode         = mlx5e_set_rx_mode,
4592         .ndo_set_mac_address     = mlx5e_set_mac,
4593         .ndo_vlan_rx_add_vid     = mlx5e_vlan_rx_add_vid,
4594         .ndo_vlan_rx_kill_vid    = mlx5e_vlan_rx_kill_vid,
4595         .ndo_set_features        = mlx5e_set_features,
4596         .ndo_fix_features        = mlx5e_fix_features,
4597         .ndo_change_mtu          = mlx5e_change_nic_mtu,
4598         .ndo_do_ioctl            = mlx5e_ioctl,
4599         .ndo_set_tx_maxrate      = mlx5e_set_tx_maxrate,
4600         .ndo_udp_tunnel_add      = mlx5e_add_vxlan_port,
4601         .ndo_udp_tunnel_del      = mlx5e_del_vxlan_port,
4602         .ndo_features_check      = mlx5e_features_check,
4603         .ndo_tx_timeout          = mlx5e_tx_timeout,
4604         .ndo_bpf                 = mlx5e_xdp,
4605         .ndo_xdp_xmit            = mlx5e_xdp_xmit,
4606         .ndo_xsk_wakeup          = mlx5e_xsk_wakeup,
4607 #ifdef CONFIG_MLX5_EN_ARFS
4608         .ndo_rx_flow_steer       = mlx5e_rx_flow_steer,
4609 #endif
4610 #ifdef CONFIG_MLX5_ESWITCH
4611         .ndo_bridge_setlink      = mlx5e_bridge_setlink,
4612         .ndo_bridge_getlink      = mlx5e_bridge_getlink,
4613
4614         /* SRIOV E-Switch NDOs */
4615         .ndo_set_vf_mac          = mlx5e_set_vf_mac,
4616         .ndo_set_vf_vlan         = mlx5e_set_vf_vlan,
4617         .ndo_set_vf_spoofchk     = mlx5e_set_vf_spoofchk,
4618         .ndo_set_vf_trust        = mlx5e_set_vf_trust,
4619         .ndo_set_vf_rate         = mlx5e_set_vf_rate,
4620         .ndo_get_vf_config       = mlx5e_get_vf_config,
4621         .ndo_set_vf_link_state   = mlx5e_set_vf_link_state,
4622         .ndo_get_vf_stats        = mlx5e_get_vf_stats,
4623 #endif
4624         .ndo_get_devlink_port    = mlx5e_get_devlink_port,
4625 };
4626
4627 static int mlx5e_check_required_hca_cap(struct mlx5_core_dev *mdev)
4628 {
4629         if (MLX5_CAP_GEN(mdev, port_type) != MLX5_CAP_PORT_TYPE_ETH)
4630                 return -EOPNOTSUPP;
4631         if (!MLX5_CAP_GEN(mdev, eth_net_offloads) ||
4632             !MLX5_CAP_GEN(mdev, nic_flow_table) ||
4633             !MLX5_CAP_ETH(mdev, csum_cap) ||
4634             !MLX5_CAP_ETH(mdev, max_lso_cap) ||
4635             !MLX5_CAP_ETH(mdev, vlan_cap) ||
4636             !MLX5_CAP_ETH(mdev, rss_ind_tbl_cap) ||
4637             MLX5_CAP_FLOWTABLE(mdev,
4638                                flow_table_properties_nic_receive.max_ft_level)
4639                                < 3) {
4640                 mlx5_core_warn(mdev,
4641                                "Not creating net device, some required device capabilities are missing\n");
4642                 return -EOPNOTSUPP;
4643         }
4644         if (!MLX5_CAP_ETH(mdev, self_lb_en_modifiable))
4645                 mlx5_core_warn(mdev, "Self loop back prevention is not supported\n");
4646         if (!MLX5_CAP_GEN(mdev, cq_moderation))
4647                 mlx5_core_warn(mdev, "CQ moderation is not supported\n");
4648
4649         return 0;
4650 }
4651
4652 void mlx5e_build_default_indir_rqt(u32 *indirection_rqt, int len,
4653                                    int num_channels)
4654 {
4655         int i;
4656
4657         for (i = 0; i < len; i++)
4658                 indirection_rqt[i] = i % num_channels;
4659 }
4660
4661 static bool slow_pci_heuristic(struct mlx5_core_dev *mdev)
4662 {
4663         u32 link_speed = 0;
4664         u32 pci_bw = 0;
4665
4666         mlx5e_port_max_linkspeed(mdev, &link_speed);
4667         pci_bw = pcie_bandwidth_available(mdev->pdev, NULL, NULL, NULL);
4668         mlx5_core_dbg_once(mdev, "Max link speed = %d, PCI BW = %d\n",
4669                            link_speed, pci_bw);
4670
4671 #define MLX5E_SLOW_PCI_RATIO (2)
4672
4673         return link_speed && pci_bw &&
4674                 link_speed > MLX5E_SLOW_PCI_RATIO * pci_bw;
4675 }
4676
4677 static struct dim_cq_moder mlx5e_get_def_tx_moderation(u8 cq_period_mode)
4678 {
4679         struct dim_cq_moder moder;
4680
4681         moder.cq_period_mode = cq_period_mode;
4682         moder.pkts = MLX5E_PARAMS_DEFAULT_TX_CQ_MODERATION_PKTS;
4683         moder.usec = MLX5E_PARAMS_DEFAULT_TX_CQ_MODERATION_USEC;
4684         if (cq_period_mode == MLX5_CQ_PERIOD_MODE_START_FROM_CQE)
4685                 moder.usec = MLX5E_PARAMS_DEFAULT_TX_CQ_MODERATION_USEC_FROM_CQE;
4686
4687         return moder;
4688 }
4689
4690 static struct dim_cq_moder mlx5e_get_def_rx_moderation(u8 cq_period_mode)
4691 {
4692         struct dim_cq_moder moder;
4693
4694         moder.cq_period_mode = cq_period_mode;
4695         moder.pkts = MLX5E_PARAMS_DEFAULT_RX_CQ_MODERATION_PKTS;
4696         moder.usec = MLX5E_PARAMS_DEFAULT_RX_CQ_MODERATION_USEC;
4697         if (cq_period_mode == MLX5_CQ_PERIOD_MODE_START_FROM_CQE)
4698                 moder.usec = MLX5E_PARAMS_DEFAULT_RX_CQ_MODERATION_USEC_FROM_CQE;
4699
4700         return moder;
4701 }
4702
4703 static u8 mlx5_to_net_dim_cq_period_mode(u8 cq_period_mode)
4704 {
4705         return cq_period_mode == MLX5_CQ_PERIOD_MODE_START_FROM_CQE ?
4706                 DIM_CQ_PERIOD_MODE_START_FROM_CQE :
4707                 DIM_CQ_PERIOD_MODE_START_FROM_EQE;
4708 }
4709
4710 void mlx5e_set_tx_cq_mode_params(struct mlx5e_params *params, u8 cq_period_mode)
4711 {
4712         if (params->tx_dim_enabled) {
4713                 u8 dim_period_mode = mlx5_to_net_dim_cq_period_mode(cq_period_mode);
4714
4715                 params->tx_cq_moderation = net_dim_get_def_tx_moderation(dim_period_mode);
4716         } else {
4717                 params->tx_cq_moderation = mlx5e_get_def_tx_moderation(cq_period_mode);
4718         }
4719
4720         MLX5E_SET_PFLAG(params, MLX5E_PFLAG_TX_CQE_BASED_MODER,
4721                         params->tx_cq_moderation.cq_period_mode ==
4722                                 MLX5_CQ_PERIOD_MODE_START_FROM_CQE);
4723 }
4724
4725 void mlx5e_set_rx_cq_mode_params(struct mlx5e_params *params, u8 cq_period_mode)
4726 {
4727         if (params->rx_dim_enabled) {
4728                 u8 dim_period_mode = mlx5_to_net_dim_cq_period_mode(cq_period_mode);
4729
4730                 params->rx_cq_moderation = net_dim_get_def_rx_moderation(dim_period_mode);
4731         } else {
4732                 params->rx_cq_moderation = mlx5e_get_def_rx_moderation(cq_period_mode);
4733         }
4734
4735         MLX5E_SET_PFLAG(params, MLX5E_PFLAG_RX_CQE_BASED_MODER,
4736                         params->rx_cq_moderation.cq_period_mode ==
4737                                 MLX5_CQ_PERIOD_MODE_START_FROM_CQE);
4738 }
4739
4740 static u32 mlx5e_choose_lro_timeout(struct mlx5_core_dev *mdev, u32 wanted_timeout)
4741 {
4742         int i;
4743
4744         /* The supported periods are organized in ascending order */
4745         for (i = 0; i < MLX5E_LRO_TIMEOUT_ARR_SIZE - 1; i++)
4746                 if (MLX5_CAP_ETH(mdev, lro_timer_supported_periods[i]) >= wanted_timeout)
4747                         break;
4748
4749         return MLX5_CAP_ETH(mdev, lro_timer_supported_periods[i]);
4750 }
4751
4752 void mlx5e_build_rq_params(struct mlx5_core_dev *mdev,
4753                            struct mlx5e_params *params)
4754 {
4755         /* Prefer Striding RQ, unless any of the following holds:
4756          * - Striding RQ configuration is not possible/supported.
4757          * - Slow PCI heuristic.
4758          * - Legacy RQ would use linear SKB while Striding RQ would use non-linear.
4759          *
4760          * No XSK params: checking the availability of striding RQ in general.
4761          */
4762         if (!slow_pci_heuristic(mdev) &&
4763             mlx5e_striding_rq_possible(mdev, params) &&
4764             (mlx5e_rx_mpwqe_is_linear_skb(mdev, params, NULL) ||
4765              !mlx5e_rx_is_linear_skb(params, NULL)))
4766                 MLX5E_SET_PFLAG(params, MLX5E_PFLAG_RX_STRIDING_RQ, true);
4767         mlx5e_set_rq_type(mdev, params);
4768         mlx5e_init_rq_type_params(mdev, params);
4769 }
4770
4771 void mlx5e_build_rss_params(struct mlx5e_rss_params *rss_params,
4772                             u16 num_channels)
4773 {
4774         enum mlx5e_traffic_types tt;
4775
4776         rss_params->hfunc = ETH_RSS_HASH_TOP;
4777         netdev_rss_key_fill(rss_params->toeplitz_hash_key,
4778                             sizeof(rss_params->toeplitz_hash_key));
4779         mlx5e_build_default_indir_rqt(rss_params->indirection_rqt,
4780                                       MLX5E_INDIR_RQT_SIZE, num_channels);
4781         for (tt = 0; tt < MLX5E_NUM_INDIR_TIRS; tt++)
4782                 rss_params->rx_hash_fields[tt] =
4783                         tirc_default_config[tt].rx_hash_fields;
4784 }
4785
4786 void mlx5e_build_nic_params(struct mlx5e_priv *priv,
4787                             struct mlx5e_xsk *xsk,
4788                             struct mlx5e_rss_params *rss_params,
4789                             struct mlx5e_params *params,
4790                             u16 mtu)
4791 {
4792         struct mlx5_core_dev *mdev = priv->mdev;
4793         u8 rx_cq_period_mode;
4794
4795         params->sw_mtu = mtu;
4796         params->hard_mtu = MLX5E_ETH_HARD_MTU;
4797         params->num_channels = min_t(unsigned int, MLX5E_MAX_NUM_CHANNELS / 2,
4798                                      priv->max_nch);
4799         params->num_tc       = 1;
4800
4801         /* SQ */
4802         params->log_sq_size = is_kdump_kernel() ?
4803                 MLX5E_PARAMS_MINIMUM_LOG_SQ_SIZE :
4804                 MLX5E_PARAMS_DEFAULT_LOG_SQ_SIZE;
4805
4806         /* XDP SQ */
4807         MLX5E_SET_PFLAG(params, MLX5E_PFLAG_XDP_TX_MPWQE,
4808                         MLX5_CAP_ETH(mdev, enhanced_multi_pkt_send_wqe));
4809
4810         /* set CQE compression */
4811         params->rx_cqe_compress_def = false;
4812         if (MLX5_CAP_GEN(mdev, cqe_compression) &&
4813             MLX5_CAP_GEN(mdev, vport_group_manager))
4814                 params->rx_cqe_compress_def = slow_pci_heuristic(mdev);
4815
4816         MLX5E_SET_PFLAG(params, MLX5E_PFLAG_RX_CQE_COMPRESS, params->rx_cqe_compress_def);
4817         MLX5E_SET_PFLAG(params, MLX5E_PFLAG_RX_NO_CSUM_COMPLETE, false);
4818
4819         /* RQ */
4820         mlx5e_build_rq_params(mdev, params);
4821
4822         /* HW LRO */
4823         if (MLX5_CAP_ETH(mdev, lro_cap) &&
4824             params->rq_wq_type == MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ) {
4825                 /* No XSK params: checking the availability of striding RQ in general. */
4826                 if (!mlx5e_rx_mpwqe_is_linear_skb(mdev, params, NULL))
4827                         params->lro_en = !slow_pci_heuristic(mdev);
4828         }
4829         params->lro_timeout = mlx5e_choose_lro_timeout(mdev, MLX5E_DEFAULT_LRO_TIMEOUT);
4830
4831         /* CQ moderation params */
4832         rx_cq_period_mode = MLX5_CAP_GEN(mdev, cq_period_start_from_cqe) ?
4833                         MLX5_CQ_PERIOD_MODE_START_FROM_CQE :
4834                         MLX5_CQ_PERIOD_MODE_START_FROM_EQE;
4835         params->rx_dim_enabled = MLX5_CAP_GEN(mdev, cq_moderation);
4836         params->tx_dim_enabled = MLX5_CAP_GEN(mdev, cq_moderation);
4837         mlx5e_set_rx_cq_mode_params(params, rx_cq_period_mode);
4838         mlx5e_set_tx_cq_mode_params(params, MLX5_CQ_PERIOD_MODE_START_FROM_EQE);
4839
4840         /* TX inline */
4841         mlx5_query_min_inline(mdev, &params->tx_min_inline_mode);
4842
4843         /* RSS */
4844         mlx5e_build_rss_params(rss_params, params->num_channels);
4845         params->tunneled_offload_en =
4846                 mlx5e_tunnel_inner_ft_supported(mdev);
4847
4848         /* AF_XDP */
4849         params->xsk = xsk;
4850 }
4851
4852 static void mlx5e_set_netdev_dev_addr(struct net_device *netdev)
4853 {
4854         struct mlx5e_priv *priv = netdev_priv(netdev);
4855
4856         mlx5_query_mac_address(priv->mdev, netdev->dev_addr);
4857         if (is_zero_ether_addr(netdev->dev_addr) &&
4858             !MLX5_CAP_GEN(priv->mdev, vport_group_manager)) {
4859                 eth_hw_addr_random(netdev);
4860                 mlx5_core_info(priv->mdev, "Assigned random MAC address %pM\n", netdev->dev_addr);
4861         }
4862 }
4863
4864 static void mlx5e_build_nic_netdev(struct net_device *netdev)
4865 {
4866         struct mlx5e_priv *priv = netdev_priv(netdev);
4867         struct mlx5_core_dev *mdev = priv->mdev;
4868         bool fcs_supported;
4869         bool fcs_enabled;
4870
4871         SET_NETDEV_DEV(netdev, mdev->device);
4872
4873         netdev->netdev_ops = &mlx5e_netdev_ops;
4874
4875         mlx5e_dcbnl_build_netdev(netdev);
4876
4877         netdev->watchdog_timeo    = 15 * HZ;
4878
4879         netdev->ethtool_ops       = &mlx5e_ethtool_ops;
4880
4881         netdev->vlan_features    |= NETIF_F_SG;
4882         netdev->vlan_features    |= NETIF_F_HW_CSUM;
4883         netdev->vlan_features    |= NETIF_F_GRO;
4884         netdev->vlan_features    |= NETIF_F_TSO;
4885         netdev->vlan_features    |= NETIF_F_TSO6;
4886         netdev->vlan_features    |= NETIF_F_RXCSUM;
4887         netdev->vlan_features    |= NETIF_F_RXHASH;
4888
4889         netdev->mpls_features    |= NETIF_F_SG;
4890         netdev->mpls_features    |= NETIF_F_HW_CSUM;
4891         netdev->mpls_features    |= NETIF_F_TSO;
4892         netdev->mpls_features    |= NETIF_F_TSO6;
4893
4894         netdev->hw_enc_features  |= NETIF_F_HW_VLAN_CTAG_TX;
4895         netdev->hw_enc_features  |= NETIF_F_HW_VLAN_CTAG_RX;
4896
4897         if (!!MLX5_CAP_ETH(mdev, lro_cap) &&
4898             mlx5e_check_fragmented_striding_rq_cap(mdev))
4899                 netdev->vlan_features    |= NETIF_F_LRO;
4900
4901         netdev->hw_features       = netdev->vlan_features;
4902         netdev->hw_features      |= NETIF_F_HW_VLAN_CTAG_TX;
4903         netdev->hw_features      |= NETIF_F_HW_VLAN_CTAG_RX;
4904         netdev->hw_features      |= NETIF_F_HW_VLAN_CTAG_FILTER;
4905         netdev->hw_features      |= NETIF_F_HW_VLAN_STAG_TX;
4906
4907         if (mlx5_vxlan_allowed(mdev->vxlan) || mlx5_geneve_tx_allowed(mdev) ||
4908             mlx5e_any_tunnel_proto_supported(mdev)) {
4909                 netdev->hw_enc_features |= NETIF_F_HW_CSUM;
4910                 netdev->hw_enc_features |= NETIF_F_TSO;
4911                 netdev->hw_enc_features |= NETIF_F_TSO6;
4912                 netdev->hw_enc_features |= NETIF_F_GSO_PARTIAL;
4913         }
4914
4915         if (mlx5_vxlan_allowed(mdev->vxlan) || mlx5_geneve_tx_allowed(mdev)) {
4916                 netdev->hw_features     |= NETIF_F_GSO_UDP_TUNNEL |
4917                                            NETIF_F_GSO_UDP_TUNNEL_CSUM;
4918                 netdev->hw_enc_features |= NETIF_F_GSO_UDP_TUNNEL |
4919                                            NETIF_F_GSO_UDP_TUNNEL_CSUM;
4920                 netdev->gso_partial_features = NETIF_F_GSO_UDP_TUNNEL_CSUM;
4921                 netdev->vlan_features |= NETIF_F_GSO_UDP_TUNNEL |
4922                                          NETIF_F_GSO_UDP_TUNNEL_CSUM;
4923         }
4924
4925         if (mlx5e_tunnel_proto_supported(mdev, IPPROTO_GRE)) {
4926                 netdev->hw_features     |= NETIF_F_GSO_GRE |
4927                                            NETIF_F_GSO_GRE_CSUM;
4928                 netdev->hw_enc_features |= NETIF_F_GSO_GRE |
4929                                            NETIF_F_GSO_GRE_CSUM;
4930                 netdev->gso_partial_features |= NETIF_F_GSO_GRE |
4931                                                 NETIF_F_GSO_GRE_CSUM;
4932         }
4933
4934         if (mlx5e_tunnel_proto_supported(mdev, IPPROTO_IPIP)) {
4935                 netdev->hw_features |= NETIF_F_GSO_IPXIP4 |
4936                                        NETIF_F_GSO_IPXIP6;
4937                 netdev->hw_enc_features |= NETIF_F_GSO_IPXIP4 |
4938                                            NETIF_F_GSO_IPXIP6;
4939                 netdev->gso_partial_features |= NETIF_F_GSO_IPXIP4 |
4940                                                 NETIF_F_GSO_IPXIP6;
4941         }
4942
4943         netdev->hw_features                      |= NETIF_F_GSO_PARTIAL;
4944         netdev->gso_partial_features             |= NETIF_F_GSO_UDP_L4;
4945         netdev->hw_features                      |= NETIF_F_GSO_UDP_L4;
4946         netdev->features                         |= NETIF_F_GSO_UDP_L4;
4947
4948         mlx5_query_port_fcs(mdev, &fcs_supported, &fcs_enabled);
4949
4950         if (fcs_supported)
4951                 netdev->hw_features |= NETIF_F_RXALL;
4952
4953         if (MLX5_CAP_ETH(mdev, scatter_fcs))
4954                 netdev->hw_features |= NETIF_F_RXFCS;
4955
4956         netdev->features          = netdev->hw_features;
4957         if (!priv->channels.params.lro_en)
4958                 netdev->features  &= ~NETIF_F_LRO;
4959
4960         if (fcs_enabled)
4961                 netdev->features  &= ~NETIF_F_RXALL;
4962
4963         if (!priv->channels.params.scatter_fcs_en)
4964                 netdev->features  &= ~NETIF_F_RXFCS;
4965
4966         /* prefere CQE compression over rxhash */
4967         if (MLX5E_GET_PFLAG(&priv->channels.params, MLX5E_PFLAG_RX_CQE_COMPRESS))
4968                 netdev->features &= ~NETIF_F_RXHASH;
4969
4970 #define FT_CAP(f) MLX5_CAP_FLOWTABLE(mdev, flow_table_properties_nic_receive.f)
4971         if (FT_CAP(flow_modify_en) &&
4972             FT_CAP(modify_root) &&
4973             FT_CAP(identified_miss_table_mode) &&
4974             FT_CAP(flow_table_modify)) {
4975 #ifdef CONFIG_MLX5_ESWITCH
4976                 netdev->hw_features      |= NETIF_F_HW_TC;
4977 #endif
4978 #ifdef CONFIG_MLX5_EN_ARFS
4979                 netdev->hw_features      |= NETIF_F_NTUPLE;
4980 #endif
4981         }
4982
4983         netdev->features         |= NETIF_F_HIGHDMA;
4984         netdev->features         |= NETIF_F_HW_VLAN_STAG_FILTER;
4985
4986         netdev->priv_flags       |= IFF_UNICAST_FLT;
4987
4988         mlx5e_set_netdev_dev_addr(netdev);
4989         mlx5e_ipsec_build_netdev(priv);
4990         mlx5e_tls_build_netdev(priv);
4991 }
4992
4993 void mlx5e_create_q_counters(struct mlx5e_priv *priv)
4994 {
4995         u32 out[MLX5_ST_SZ_DW(alloc_q_counter_out)] = {};
4996         u32 in[MLX5_ST_SZ_DW(alloc_q_counter_in)] = {};
4997         struct mlx5_core_dev *mdev = priv->mdev;
4998         int err;
4999
5000         MLX5_SET(alloc_q_counter_in, in, opcode, MLX5_CMD_OP_ALLOC_Q_COUNTER);
5001         err = mlx5_cmd_exec_inout(mdev, alloc_q_counter, in, out);
5002         if (!err)
5003                 priv->q_counter =
5004                         MLX5_GET(alloc_q_counter_out, out, counter_set_id);
5005
5006         err = mlx5_cmd_exec_inout(mdev, alloc_q_counter, in, out);
5007         if (!err)
5008                 priv->drop_rq_q_counter =
5009                         MLX5_GET(alloc_q_counter_out, out, counter_set_id);
5010 }
5011
5012 void mlx5e_destroy_q_counters(struct mlx5e_priv *priv)
5013 {
5014         u32 in[MLX5_ST_SZ_DW(dealloc_q_counter_in)] = {};
5015
5016         MLX5_SET(dealloc_q_counter_in, in, opcode,
5017                  MLX5_CMD_OP_DEALLOC_Q_COUNTER);
5018         if (priv->q_counter) {
5019                 MLX5_SET(dealloc_q_counter_in, in, counter_set_id,
5020                          priv->q_counter);
5021                 mlx5_cmd_exec_in(priv->mdev, dealloc_q_counter, in);
5022         }
5023
5024         if (priv->drop_rq_q_counter) {
5025                 MLX5_SET(dealloc_q_counter_in, in, counter_set_id,
5026                          priv->drop_rq_q_counter);
5027                 mlx5_cmd_exec_in(priv->mdev, dealloc_q_counter, in);
5028         }
5029 }
5030
5031 static int mlx5e_nic_init(struct mlx5_core_dev *mdev,
5032                           struct net_device *netdev,
5033                           const struct mlx5e_profile *profile,
5034                           void *ppriv)
5035 {
5036         struct mlx5e_priv *priv = netdev_priv(netdev);
5037         struct mlx5e_rss_params *rss = &priv->rss_params;
5038         int err;
5039
5040         err = mlx5e_netdev_init(netdev, priv, mdev, profile, ppriv);
5041         if (err)
5042                 return err;
5043
5044         mlx5e_build_nic_params(priv, &priv->xsk, rss, &priv->channels.params,
5045                                netdev->mtu);
5046
5047         mlx5e_timestamp_init(priv);
5048
5049         err = mlx5e_ipsec_init(priv);
5050         if (err)
5051                 mlx5_core_err(mdev, "IPSec initialization failed, %d\n", err);
5052         err = mlx5e_tls_init(priv);
5053         if (err)
5054                 mlx5_core_err(mdev, "TLS initialization failed, %d\n", err);
5055         mlx5e_build_nic_netdev(netdev);
5056         mlx5e_health_create_reporters(priv);
5057
5058         return 0;
5059 }
5060
5061 static void mlx5e_nic_cleanup(struct mlx5e_priv *priv)
5062 {
5063         mlx5e_health_destroy_reporters(priv);
5064         mlx5e_tls_cleanup(priv);
5065         mlx5e_ipsec_cleanup(priv);
5066         mlx5e_netdev_cleanup(priv->netdev, priv);
5067 }
5068
5069 static int mlx5e_init_nic_rx(struct mlx5e_priv *priv)
5070 {
5071         struct mlx5_core_dev *mdev = priv->mdev;
5072         int err;
5073
5074         mlx5e_create_q_counters(priv);
5075
5076         err = mlx5e_open_drop_rq(priv, &priv->drop_rq);
5077         if (err) {
5078                 mlx5_core_err(mdev, "open drop rq failed, %d\n", err);
5079                 goto err_destroy_q_counters;
5080         }
5081
5082         err = mlx5e_create_indirect_rqt(priv);
5083         if (err)
5084                 goto err_close_drop_rq;
5085
5086         err = mlx5e_create_direct_rqts(priv, priv->direct_tir);
5087         if (err)
5088                 goto err_destroy_indirect_rqts;
5089
5090         err = mlx5e_create_indirect_tirs(priv, true);
5091         if (err)
5092                 goto err_destroy_direct_rqts;
5093
5094         err = mlx5e_create_direct_tirs(priv, priv->direct_tir);
5095         if (err)
5096                 goto err_destroy_indirect_tirs;
5097
5098         err = mlx5e_create_direct_rqts(priv, priv->xsk_tir);
5099         if (unlikely(err))
5100                 goto err_destroy_direct_tirs;
5101
5102         err = mlx5e_create_direct_tirs(priv, priv->xsk_tir);
5103         if (unlikely(err))
5104                 goto err_destroy_xsk_rqts;
5105
5106         err = mlx5e_create_flow_steering(priv);
5107         if (err) {
5108                 mlx5_core_warn(mdev, "create flow steering failed, %d\n", err);
5109                 goto err_destroy_xsk_tirs;
5110         }
5111
5112         err = mlx5e_tc_nic_init(priv);
5113         if (err)
5114                 goto err_destroy_flow_steering;
5115
5116         return 0;
5117
5118 err_destroy_flow_steering:
5119         mlx5e_destroy_flow_steering(priv);
5120 err_destroy_xsk_tirs:
5121         mlx5e_destroy_direct_tirs(priv, priv->xsk_tir);
5122 err_destroy_xsk_rqts:
5123         mlx5e_destroy_direct_rqts(priv, priv->xsk_tir);
5124 err_destroy_direct_tirs:
5125         mlx5e_destroy_direct_tirs(priv, priv->direct_tir);
5126 err_destroy_indirect_tirs:
5127         mlx5e_destroy_indirect_tirs(priv);
5128 err_destroy_direct_rqts:
5129         mlx5e_destroy_direct_rqts(priv, priv->direct_tir);
5130 err_destroy_indirect_rqts:
5131         mlx5e_destroy_rqt(priv, &priv->indir_rqt);
5132 err_close_drop_rq:
5133         mlx5e_close_drop_rq(&priv->drop_rq);
5134 err_destroy_q_counters:
5135         mlx5e_destroy_q_counters(priv);
5136         return err;
5137 }
5138
5139 static void mlx5e_cleanup_nic_rx(struct mlx5e_priv *priv)
5140 {
5141         mlx5e_tc_nic_cleanup(priv);
5142         mlx5e_destroy_flow_steering(priv);
5143         mlx5e_destroy_direct_tirs(priv, priv->xsk_tir);
5144         mlx5e_destroy_direct_rqts(priv, priv->xsk_tir);
5145         mlx5e_destroy_direct_tirs(priv, priv->direct_tir);
5146         mlx5e_destroy_indirect_tirs(priv);
5147         mlx5e_destroy_direct_rqts(priv, priv->direct_tir);
5148         mlx5e_destroy_rqt(priv, &priv->indir_rqt);
5149         mlx5e_close_drop_rq(&priv->drop_rq);
5150         mlx5e_destroy_q_counters(priv);
5151 }
5152
5153 static int mlx5e_init_nic_tx(struct mlx5e_priv *priv)
5154 {
5155         int err;
5156
5157         err = mlx5e_create_tises(priv);
5158         if (err) {
5159                 mlx5_core_warn(priv->mdev, "create tises failed, %d\n", err);
5160                 return err;
5161         }
5162
5163         mlx5e_dcbnl_initialize(priv);
5164         return 0;
5165 }
5166
5167 static void mlx5e_nic_enable(struct mlx5e_priv *priv)
5168 {
5169         struct net_device *netdev = priv->netdev;
5170         struct mlx5_core_dev *mdev = priv->mdev;
5171
5172         mlx5e_init_l2_addr(priv);
5173
5174         /* Marking the link as currently not needed by the Driver */
5175         if (!netif_running(netdev))
5176                 mlx5_set_port_admin_status(mdev, MLX5_PORT_DOWN);
5177
5178         mlx5e_set_netdev_mtu_boundaries(priv);
5179         mlx5e_set_dev_port_mtu(priv);
5180
5181         mlx5_lag_add(mdev, netdev);
5182
5183         mlx5e_enable_async_events(priv);
5184         if (mlx5e_monitor_counter_supported(priv))
5185                 mlx5e_monitor_counter_init(priv);
5186
5187         mlx5e_hv_vhca_stats_create(priv);
5188         if (netdev->reg_state != NETREG_REGISTERED)
5189                 return;
5190         mlx5e_dcbnl_init_app(priv);
5191
5192         queue_work(priv->wq, &priv->set_rx_mode_work);
5193
5194         rtnl_lock();
5195         if (netif_running(netdev))
5196                 mlx5e_open(netdev);
5197         netif_device_attach(netdev);
5198         rtnl_unlock();
5199 }
5200
5201 static void mlx5e_nic_disable(struct mlx5e_priv *priv)
5202 {
5203         struct mlx5_core_dev *mdev = priv->mdev;
5204
5205         if (priv->netdev->reg_state == NETREG_REGISTERED)
5206                 mlx5e_dcbnl_delete_app(priv);
5207
5208         rtnl_lock();
5209         if (netif_running(priv->netdev))
5210                 mlx5e_close(priv->netdev);
5211         netif_device_detach(priv->netdev);
5212         rtnl_unlock();
5213
5214         queue_work(priv->wq, &priv->set_rx_mode_work);
5215
5216         mlx5e_hv_vhca_stats_destroy(priv);
5217         if (mlx5e_monitor_counter_supported(priv))
5218                 mlx5e_monitor_counter_cleanup(priv);
5219
5220         mlx5e_disable_async_events(priv);
5221         mlx5_lag_remove(mdev);
5222 }
5223
5224 int mlx5e_update_nic_rx(struct mlx5e_priv *priv)
5225 {
5226         return mlx5e_refresh_tirs(priv, false, false);
5227 }
5228
5229 static const struct mlx5e_profile mlx5e_nic_profile = {
5230         .init              = mlx5e_nic_init,
5231         .cleanup           = mlx5e_nic_cleanup,
5232         .init_rx           = mlx5e_init_nic_rx,
5233         .cleanup_rx        = mlx5e_cleanup_nic_rx,
5234         .init_tx           = mlx5e_init_nic_tx,
5235         .cleanup_tx        = mlx5e_cleanup_nic_tx,
5236         .enable            = mlx5e_nic_enable,
5237         .disable           = mlx5e_nic_disable,
5238         .update_rx         = mlx5e_update_nic_rx,
5239         .update_stats      = mlx5e_update_ndo_stats,
5240         .update_carrier    = mlx5e_update_carrier,
5241         .rx_handlers.handle_rx_cqe       = mlx5e_handle_rx_cqe,
5242         .rx_handlers.handle_rx_cqe_mpwqe = mlx5e_handle_rx_cqe_mpwrq,
5243         .max_tc            = MLX5E_MAX_NUM_TC,
5244         .rq_groups         = MLX5E_NUM_RQ_GROUPS(XSK),
5245         .stats_grps        = mlx5e_nic_stats_grps,
5246         .stats_grps_num    = mlx5e_nic_stats_grps_num,
5247 };
5248
5249 /* mlx5e generic netdev management API (move to en_common.c) */
5250
5251 /* mlx5e_netdev_init/cleanup must be called from profile->init/cleanup callbacks */
5252 int mlx5e_netdev_init(struct net_device *netdev,
5253                       struct mlx5e_priv *priv,
5254                       struct mlx5_core_dev *mdev,
5255                       const struct mlx5e_profile *profile,
5256                       void *ppriv)
5257 {
5258         /* priv init */
5259         priv->mdev        = mdev;
5260         priv->netdev      = netdev;
5261         priv->profile     = profile;
5262         priv->ppriv       = ppriv;
5263         priv->msglevel    = MLX5E_MSG_LEVEL;
5264         priv->max_nch     = netdev->num_rx_queues / max_t(u8, profile->rq_groups, 1);
5265         priv->max_opened_tc = 1;
5266
5267         if (!alloc_cpumask_var(&priv->scratchpad.cpumask, GFP_KERNEL))
5268                 return -ENOMEM;
5269
5270         mutex_init(&priv->state_lock);
5271         INIT_WORK(&priv->update_carrier_work, mlx5e_update_carrier_work);
5272         INIT_WORK(&priv->set_rx_mode_work, mlx5e_set_rx_mode_work);
5273         INIT_WORK(&priv->tx_timeout_work, mlx5e_tx_timeout_work);
5274         INIT_WORK(&priv->update_stats_work, mlx5e_update_stats_work);
5275
5276         priv->wq = create_singlethread_workqueue("mlx5e");
5277         if (!priv->wq)
5278                 goto err_free_cpumask;
5279
5280         /* netdev init */
5281         netif_carrier_off(netdev);
5282
5283 #ifdef CONFIG_MLX5_EN_ARFS
5284         netdev->rx_cpu_rmap =  mlx5_eq_table_get_rmap(mdev);
5285 #endif
5286
5287         return 0;
5288
5289 err_free_cpumask:
5290         free_cpumask_var(priv->scratchpad.cpumask);
5291
5292         return -ENOMEM;
5293 }
5294
5295 void mlx5e_netdev_cleanup(struct net_device *netdev, struct mlx5e_priv *priv)
5296 {
5297         destroy_workqueue(priv->wq);
5298         free_cpumask_var(priv->scratchpad.cpumask);
5299 }
5300
5301 struct net_device *mlx5e_create_netdev(struct mlx5_core_dev *mdev,
5302                                        const struct mlx5e_profile *profile,
5303                                        int nch,
5304                                        void *ppriv)
5305 {
5306         struct net_device *netdev;
5307         int err;
5308
5309         netdev = alloc_etherdev_mqs(sizeof(struct mlx5e_priv),
5310                                     nch * profile->max_tc,
5311                                     nch * profile->rq_groups);
5312         if (!netdev) {
5313                 mlx5_core_err(mdev, "alloc_etherdev_mqs() failed\n");
5314                 return NULL;
5315         }
5316
5317         err = profile->init(mdev, netdev, profile, ppriv);
5318         if (err) {
5319                 mlx5_core_err(mdev, "failed to init mlx5e profile %d\n", err);
5320                 goto err_free_netdev;
5321         }
5322
5323         return netdev;
5324
5325 err_free_netdev:
5326         free_netdev(netdev);
5327
5328         return NULL;
5329 }
5330
5331 int mlx5e_attach_netdev(struct mlx5e_priv *priv)
5332 {
5333         const bool take_rtnl = priv->netdev->reg_state == NETREG_REGISTERED;
5334         const struct mlx5e_profile *profile;
5335         int max_nch;
5336         int err;
5337
5338         profile = priv->profile;
5339         clear_bit(MLX5E_STATE_DESTROYING, &priv->state);
5340
5341         /* max number of channels may have changed */
5342         max_nch = mlx5e_get_max_num_channels(priv->mdev);
5343         if (priv->channels.params.num_channels > max_nch) {
5344                 mlx5_core_warn(priv->mdev, "MLX5E: Reducing number of channels to %d\n", max_nch);
5345                 /* Reducing the number of channels - RXFH has to be reset, and
5346                  * mlx5e_num_channels_changed below will build the RQT.
5347                  */
5348                 priv->netdev->priv_flags &= ~IFF_RXFH_CONFIGURED;
5349                 priv->channels.params.num_channels = max_nch;
5350         }
5351         /* 1. Set the real number of queues in the kernel the first time.
5352          * 2. Set our default XPS cpumask.
5353          * 3. Build the RQT.
5354          *
5355          * rtnl_lock is required by netif_set_real_num_*_queues in case the
5356          * netdev has been registered by this point (if this function was called
5357          * in the reload or resume flow).
5358          */
5359         if (take_rtnl)
5360                 rtnl_lock();
5361         err = mlx5e_num_channels_changed(priv);
5362         if (take_rtnl)
5363                 rtnl_unlock();
5364         if (err)
5365                 goto out;
5366
5367         err = profile->init_tx(priv);
5368         if (err)
5369                 goto out;
5370
5371         err = profile->init_rx(priv);
5372         if (err)
5373                 goto err_cleanup_tx;
5374
5375         if (profile->enable)
5376                 profile->enable(priv);
5377
5378         return 0;
5379
5380 err_cleanup_tx:
5381         profile->cleanup_tx(priv);
5382
5383 out:
5384         return err;
5385 }
5386
5387 void mlx5e_detach_netdev(struct mlx5e_priv *priv)
5388 {
5389         const struct mlx5e_profile *profile = priv->profile;
5390
5391         set_bit(MLX5E_STATE_DESTROYING, &priv->state);
5392
5393         if (profile->disable)
5394                 profile->disable(priv);
5395         flush_workqueue(priv->wq);
5396
5397         profile->cleanup_rx(priv);
5398         profile->cleanup_tx(priv);
5399         cancel_work_sync(&priv->update_stats_work);
5400 }
5401
5402 void mlx5e_destroy_netdev(struct mlx5e_priv *priv)
5403 {
5404         const struct mlx5e_profile *profile = priv->profile;
5405         struct net_device *netdev = priv->netdev;
5406
5407         if (profile->cleanup)
5408                 profile->cleanup(priv);
5409         free_netdev(netdev);
5410 }
5411
5412 /* mlx5e_attach and mlx5e_detach scope should be only creating/destroying
5413  * hardware contexts and to connect it to the current netdev.
5414  */
5415 static int mlx5e_attach(struct mlx5_core_dev *mdev, void *vpriv)
5416 {
5417         struct mlx5e_priv *priv = vpriv;
5418         struct net_device *netdev = priv->netdev;
5419         int err;
5420
5421         if (netif_device_present(netdev))
5422                 return 0;
5423
5424         err = mlx5e_create_mdev_resources(mdev);
5425         if (err)
5426                 return err;
5427
5428         err = mlx5e_attach_netdev(priv);
5429         if (err) {
5430                 mlx5e_destroy_mdev_resources(mdev);
5431                 return err;
5432         }
5433
5434         return 0;
5435 }
5436
5437 static void mlx5e_detach(struct mlx5_core_dev *mdev, void *vpriv)
5438 {
5439         struct mlx5e_priv *priv = vpriv;
5440         struct net_device *netdev = priv->netdev;
5441
5442 #ifdef CONFIG_MLX5_ESWITCH
5443         if (MLX5_ESWITCH_MANAGER(mdev) && vpriv == mdev)
5444                 return;
5445 #endif
5446
5447         if (!netif_device_present(netdev))
5448                 return;
5449
5450         mlx5e_detach_netdev(priv);
5451         mlx5e_destroy_mdev_resources(mdev);
5452 }
5453
5454 static void *mlx5e_add(struct mlx5_core_dev *mdev)
5455 {
5456         struct net_device *netdev;
5457         void *priv;
5458         int err;
5459         int nch;
5460
5461         err = mlx5e_check_required_hca_cap(mdev);
5462         if (err)
5463                 return NULL;
5464
5465 #ifdef CONFIG_MLX5_ESWITCH
5466         if (MLX5_ESWITCH_MANAGER(mdev) &&
5467             mlx5_eswitch_mode(mdev->priv.eswitch) == MLX5_ESWITCH_OFFLOADS) {
5468                 mlx5e_rep_register_vport_reps(mdev);
5469                 return mdev;
5470         }
5471 #endif
5472
5473         nch = mlx5e_get_max_num_channels(mdev);
5474         netdev = mlx5e_create_netdev(mdev, &mlx5e_nic_profile, nch, NULL);
5475         if (!netdev) {
5476                 mlx5_core_err(mdev, "mlx5e_create_netdev failed\n");
5477                 return NULL;
5478         }
5479
5480         dev_net_set(netdev, mlx5_core_net(mdev));
5481         priv = netdev_priv(netdev);
5482
5483         err = mlx5e_attach(mdev, priv);
5484         if (err) {
5485                 mlx5_core_err(mdev, "mlx5e_attach failed, %d\n", err);
5486                 goto err_destroy_netdev;
5487         }
5488
5489         err = mlx5e_devlink_port_register(priv);
5490         if (err) {
5491                 mlx5_core_err(mdev, "mlx5e_devlink_port_register failed, %d\n", err);
5492                 goto err_detach;
5493         }
5494
5495         err = register_netdev(netdev);
5496         if (err) {
5497                 mlx5_core_err(mdev, "register_netdev failed, %d\n", err);
5498                 goto err_devlink_port_unregister;
5499         }
5500
5501         mlx5e_devlink_port_type_eth_set(priv);
5502
5503         mlx5e_dcbnl_init_app(priv);
5504         return priv;
5505
5506 err_devlink_port_unregister:
5507         mlx5e_devlink_port_unregister(priv);
5508 err_detach:
5509         mlx5e_detach(mdev, priv);
5510 err_destroy_netdev:
5511         mlx5e_destroy_netdev(priv);
5512         return NULL;
5513 }
5514
5515 static void mlx5e_remove(struct mlx5_core_dev *mdev, void *vpriv)
5516 {
5517         struct mlx5e_priv *priv;
5518
5519 #ifdef CONFIG_MLX5_ESWITCH
5520         if (MLX5_ESWITCH_MANAGER(mdev) && vpriv == mdev) {
5521                 mlx5e_rep_unregister_vport_reps(mdev);
5522                 return;
5523         }
5524 #endif
5525         priv = vpriv;
5526         mlx5e_dcbnl_delete_app(priv);
5527         unregister_netdev(priv->netdev);
5528         mlx5e_devlink_port_unregister(priv);
5529         mlx5e_detach(mdev, vpriv);
5530         mlx5e_destroy_netdev(priv);
5531 }
5532
5533 static struct mlx5_interface mlx5e_interface = {
5534         .add       = mlx5e_add,
5535         .remove    = mlx5e_remove,
5536         .attach    = mlx5e_attach,
5537         .detach    = mlx5e_detach,
5538         .protocol  = MLX5_INTERFACE_PROTOCOL_ETH,
5539 };
5540
5541 void mlx5e_init(void)
5542 {
5543         mlx5e_ipsec_build_inverse_table();
5544         mlx5e_build_ptys2ethtool_map();
5545         mlx5_register_interface(&mlx5e_interface);
5546 }
5547
5548 void mlx5e_cleanup(void)
5549 {
5550         mlx5_unregister_interface(&mlx5e_interface);
5551 }