drivers/net/ethernet/mellanox/mlx5/core/en_main.c

   1 /*
   2  * Copyright (c) 2015-2016, Mellanox Technologies. All rights reserved.
   3  *
   4  * This software is available to you under a choice of one of two
   5  * licenses.  You may choose to be licensed under the terms of the GNU
   6  * General Public License (GPL) Version 2, available from the file
   7  * COPYING in the main directory of this source tree, or the
   8  * OpenIB.org BSD license below:
   9  *
  10  *     Redistribution and use in source and binary forms, with or
  11  *     without modification, are permitted provided that the following
  12  *     conditions are met:
  13  *
  14  *      - Redistributions of source code must retain the above
  15  *        copyright notice, this list of conditions and the following
  16  *        disclaimer.
  17  *
  18  *      - Redistributions in binary form must reproduce the above
  19  *        copyright notice, this list of conditions and the following
  20  *        disclaimer in the documentation and/or other materials
  21  *        provided with the distribution.
  22  *
  23  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  24  * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  25  * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
  26  * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
  27  * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
  28  * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
  29  * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
  30  * SOFTWARE.
  31  */
  32
  33 #include <net/tc_act/tc_gact.h>
  34 #include <net/pkt_cls.h>
  35 #include <linux/mlx5/fs.h>
  36 #include <net/vxlan.h>
  37 #include <net/geneve.h>
  38 #include <linux/bpf.h>
  39 #include <linux/if_bridge.h>
  40 #include <net/page_pool.h>
  41 #include <net/xdp_sock_drv.h>
  42 #include "eswitch.h"
  43 #include "en.h"
  44 #include "en/txrx.h"
  45 #include "en_tc.h"
  46 #include "en_rep.h"
  47 #include "en_accel/ipsec.h"
  48 #include "en_accel/en_accel.h"
  49 #include "en_accel/tls.h"
  50 #include "accel/ipsec.h"
  51 #include "accel/tls.h"
  52 #include "lib/vxlan.h"
  53 #include "lib/clock.h"
  54 #include "en/port.h"
  55 #include "en/xdp.h"
  56 #include "lib/eq.h"
  57 #include "en/monitor_stats.h"
  58 #include "en/health.h"
  59 #include "en/params.h"
  60 #include "en/xsk/pool.h"
  61 #include "en/xsk/setup.h"
  62 #include "en/xsk/rx.h"
  63 #include "en/xsk/tx.h"
  64 #include "en/hv_vhca_stats.h"
  65 #include "en/devlink.h"
  66 #include "lib/mlx5.h"
  67 #include "en/ptp.h"
  68 #include "qos.h"
  69 #include "en/trap.h"
  70 #include "fpga/ipsec.h"
  71
  72 bool mlx5e_check_fragmented_striding_rq_cap(struct mlx5_core_dev *mdev)
  73 {
  74         bool striding_rq_umr = MLX5_CAP_GEN(mdev, striding_rq) &&
  75                 MLX5_CAP_GEN(mdev, umr_ptr_rlky) &&
  76                 MLX5_CAP_ETH(mdev, reg_umr_sq);
  77         u16 max_wqe_sz_cap = MLX5_CAP_GEN(mdev, max_wqe_sz_sq);
  78         bool inline_umr = MLX5E_UMR_WQE_INLINE_SZ <= max_wqe_sz_cap;
  79
  80         if (!striding_rq_umr)
  81                 return false;
  82         if (!inline_umr) {
  83                 mlx5_core_warn(mdev, "Cannot support Striding RQ: UMR WQE size (%d) exceeds maximum supported (%d).\n",
  84                                (int)MLX5E_UMR_WQE_INLINE_SZ, max_wqe_sz_cap);
  85                 return false;
  86         }
  87         return true;
  88 }
  89
  90 void mlx5e_update_carrier(struct mlx5e_priv *priv)
  91 {
  92         struct mlx5_core_dev *mdev = priv->mdev;
  93         u8 port_state;
  94         bool up;
  95
  96         port_state = mlx5_query_vport_state(mdev,
  97                                             MLX5_VPORT_STATE_OP_MOD_VNIC_VPORT,
  98                                             0);
  99
 100         up = port_state == VPORT_STATE_UP;
 101         if (up == netif_carrier_ok(priv->netdev))
 102                 netif_carrier_event(priv->netdev);
 103         if (up) {
 104                 netdev_info(priv->netdev, "Link up\n");
 105                 netif_carrier_on(priv->netdev);
 106         } else {
 107                 netdev_info(priv->netdev, "Link down\n");
 108                 netif_carrier_off(priv->netdev);
 109         }
 110 }
 111
 112 static void mlx5e_update_carrier_work(struct work_struct *work)
 113 {
 114         struct mlx5e_priv *priv = container_of(work, struct mlx5e_priv,
 115                                                update_carrier_work);
 116
 117         mutex_lock(&priv->state_lock);
 118         if (test_bit(MLX5E_STATE_OPENED, &priv->state))
 119                 if (priv->profile->update_carrier)
 120                         priv->profile->update_carrier(priv);
 121         mutex_unlock(&priv->state_lock);
 122 }
 123
 124 static void mlx5e_update_stats_work(struct work_struct *work)
 125 {
 126         struct mlx5e_priv *priv = container_of(work, struct mlx5e_priv,
 127                                                update_stats_work);
 128
 129         mutex_lock(&priv->state_lock);
 130         priv->profile->update_stats(priv);
 131         mutex_unlock(&priv->state_lock);
 132 }
 133
 134 void mlx5e_queue_update_stats(struct mlx5e_priv *priv)
 135 {
 136         if (!priv->profile->update_stats)
 137                 return;
 138
 139         if (unlikely(test_bit(MLX5E_STATE_DESTROYING, &priv->state)))
 140                 return;
 141
 142         queue_work(priv->wq, &priv->update_stats_work);
 143 }
 144
 145 static int async_event(struct notifier_block *nb, unsigned long event, void *data)
 146 {
 147         struct mlx5e_priv *priv = container_of(nb, struct mlx5e_priv, events_nb);
 148         struct mlx5_eqe   *eqe = data;
 149
 150         if (event != MLX5_EVENT_TYPE_PORT_CHANGE)
 151                 return NOTIFY_DONE;
 152
 153         switch (eqe->sub_type) {
 154         case MLX5_PORT_CHANGE_SUBTYPE_DOWN:
 155         case MLX5_PORT_CHANGE_SUBTYPE_ACTIVE:
 156                 queue_work(priv->wq, &priv->update_carrier_work);
 157                 break;
 158         default:
 159                 return NOTIFY_DONE;
 160         }
 161
 162         return NOTIFY_OK;
 163 }
 164
 165 static void mlx5e_enable_async_events(struct mlx5e_priv *priv)
 166 {
 167         priv->events_nb.notifier_call = async_event;
 168         mlx5_notifier_register(priv->mdev, &priv->events_nb);
 169 }
 170
 171 static void mlx5e_disable_async_events(struct mlx5e_priv *priv)
 172 {
 173         mlx5_notifier_unregister(priv->mdev, &priv->events_nb);
 174 }
 175
 176 static int blocking_event(struct notifier_block *nb, unsigned long event, void *data)
 177 {
 178         struct mlx5e_priv *priv = container_of(nb, struct mlx5e_priv, blocking_events_nb);
 179         int err;
 180
 181         switch (event) {
 182         case MLX5_DRIVER_EVENT_TYPE_TRAP:
 183                 err = mlx5e_handle_trap_event(priv, data);
 184                 break;
 185         default:
 186                 netdev_warn(priv->netdev, "Sync event: Unknown event %ld\n", event);
 187                 err = -EINVAL;
 188         }
 189         return err;
 190 }
 191
 192 static void mlx5e_enable_blocking_events(struct mlx5e_priv *priv)
 193 {
 194         priv->blocking_events_nb.notifier_call = blocking_event;
 195         mlx5_blocking_notifier_register(priv->mdev, &priv->blocking_events_nb);
 196 }
 197
 198 static void mlx5e_disable_blocking_events(struct mlx5e_priv *priv)
 199 {
 200         mlx5_blocking_notifier_unregister(priv->mdev, &priv->blocking_events_nb);
 201 }
 202
 203 static inline void mlx5e_build_umr_wqe(struct mlx5e_rq *rq,
 204                                        struct mlx5e_icosq *sq,
 205                                        struct mlx5e_umr_wqe *wqe)
 206 {
 207         struct mlx5_wqe_ctrl_seg      *cseg = &wqe->ctrl;
 208         struct mlx5_wqe_umr_ctrl_seg *ucseg = &wqe->uctrl;
 209         u8 ds_cnt = DIV_ROUND_UP(MLX5E_UMR_WQE_INLINE_SZ, MLX5_SEND_WQE_DS);
 210
 211         cseg->qpn_ds    = cpu_to_be32((sq->sqn << MLX5_WQE_CTRL_QPN_SHIFT) |
 212                                       ds_cnt);
 213         cseg->umr_mkey  = rq->mkey_be;
 214
 215         ucseg->flags = MLX5_UMR_TRANSLATION_OFFSET_EN | MLX5_UMR_INLINE;
 216         ucseg->xlt_octowords =
 217                 cpu_to_be16(MLX5_MTT_OCTW(MLX5_MPWRQ_PAGES_PER_WQE));
 218         ucseg->mkey_mask     = cpu_to_be64(MLX5_MKEY_MASK_FREE);
 219 }
 220
 221 static int mlx5e_rq_alloc_mpwqe_info(struct mlx5e_rq *rq, int node)
 222 {
 223         int wq_sz = mlx5_wq_ll_get_size(&rq->mpwqe.wq);
 224
 225         rq->mpwqe.info = kvzalloc_node(array_size(wq_sz,
 226                                                   sizeof(*rq->mpwqe.info)),
 227                                        GFP_KERNEL, node);
 228         if (!rq->mpwqe.info)
 229                 return -ENOMEM;
 230
 231         mlx5e_build_umr_wqe(rq, rq->icosq, &rq->mpwqe.umr_wqe);
 232
 233         return 0;
 234 }
 235
 236 static int mlx5e_create_umr_mkey(struct mlx5_core_dev *mdev,
 237                                  u64 npages, u8 page_shift,
 238                                  struct mlx5_core_mkey *umr_mkey,
 239                                  dma_addr_t filler_addr)
 240 {
 241         struct mlx5_mtt *mtt;
 242         int inlen;
 243         void *mkc;
 244         u32 *in;
 245         int err;
 246         int i;
 247
 248         inlen = MLX5_ST_SZ_BYTES(create_mkey_in) + sizeof(*mtt) * npages;
 249
 250         in = kvzalloc(inlen, GFP_KERNEL);
 251         if (!in)
 252                 return -ENOMEM;
 253
 254         mkc = MLX5_ADDR_OF(create_mkey_in, in, memory_key_mkey_entry);
 255
 256         MLX5_SET(mkc, mkc, free, 1);
 257         MLX5_SET(mkc, mkc, umr_en, 1);
 258         MLX5_SET(mkc, mkc, lw, 1);
 259         MLX5_SET(mkc, mkc, lr, 1);
 260         MLX5_SET(mkc, mkc, access_mode_1_0, MLX5_MKC_ACCESS_MODE_MTT);
 261         mlx5e_mkey_set_relaxed_ordering(mdev, mkc);
 262         MLX5_SET(mkc, mkc, qpn, 0xffffff);
 263         MLX5_SET(mkc, mkc, pd, mdev->mlx5e_res.hw_objs.pdn);
 264         MLX5_SET64(mkc, mkc, len, npages << page_shift);
 265         MLX5_SET(mkc, mkc, translations_octword_size,
 266                  MLX5_MTT_OCTW(npages));
 267         MLX5_SET(mkc, mkc, log_page_size, page_shift);
 268         MLX5_SET(create_mkey_in, in, translations_octword_actual_size,
 269                  MLX5_MTT_OCTW(npages));
 270
 271         /* Initialize the mkey with all MTTs pointing to a default
 272          * page (filler_addr). When the channels are activated, UMR
 273          * WQEs will redirect the RX WQEs to the actual memory from
 274          * the RQ's pool, while the gaps (wqe_overflow) remain mapped
 275          * to the default page.
 276          */
 277         mtt = MLX5_ADDR_OF(create_mkey_in, in, klm_pas_mtt);
 278         for (i = 0 ; i < npages ; i++)
 279                 mtt[i].ptag = cpu_to_be64(filler_addr);
 280
 281         err = mlx5_core_create_mkey(mdev, umr_mkey, in, inlen);
 282
 283         kvfree(in);
 284         return err;
 285 }
 286
 287 static int mlx5e_create_rq_umr_mkey(struct mlx5_core_dev *mdev, struct mlx5e_rq *rq)
 288 {
 289         u64 num_mtts = MLX5E_REQUIRED_MTTS(mlx5_wq_ll_get_size(&rq->mpwqe.wq));
 290
 291         return mlx5e_create_umr_mkey(mdev, num_mtts, PAGE_SHIFT, &rq->umr_mkey,
 292                                      rq->wqe_overflow.addr);
 293 }
 294
 295 static u64 mlx5e_get_mpwqe_offset(u16 wqe_ix)
 296 {
 297         return MLX5E_REQUIRED_MTTS(wqe_ix) << PAGE_SHIFT;
 298 }
 299
 300 static void mlx5e_init_frags_partition(struct mlx5e_rq *rq)
 301 {
 302         struct mlx5e_wqe_frag_info next_frag = {};
 303         struct mlx5e_wqe_frag_info *prev = NULL;
 304         int i;
 305
 306         next_frag.di = &rq->wqe.di[0];
 307
 308         for (i = 0; i < mlx5_wq_cyc_get_size(&rq->wqe.wq); i++) {
 309                 struct mlx5e_rq_frag_info *frag_info = &rq->wqe.info.arr[0];
 310                 struct mlx5e_wqe_frag_info *frag =
 311                         &rq->wqe.frags[i << rq->wqe.info.log_num_frags];
 312                 int f;
 313
 314                 for (f = 0; f < rq->wqe.info.num_frags; f++, frag++) {
 315                         if (next_frag.offset + frag_info[f].frag_stride > PAGE_SIZE) {
 316                                 next_frag.di++;
 317                                 next_frag.offset = 0;
 318                                 if (prev)
 319                                         prev->last_in_page = true;
 320                         }
 321                         *frag = next_frag;
 322
 323                         /* prepare next */
 324                         next_frag.offset += frag_info[f].frag_stride;
 325                         prev = frag;
 326                 }
 327         }
 328
 329         if (prev)
 330                 prev->last_in_page = true;
 331 }
 332
 333 int mlx5e_init_di_list(struct mlx5e_rq *rq, int wq_sz, int node)
 334 {
 335         int len = wq_sz << rq->wqe.info.log_num_frags;
 336
 337         rq->wqe.di = kvzalloc_node(array_size(len, sizeof(*rq->wqe.di)), GFP_KERNEL, node);
 338         if (!rq->wqe.di)
 339                 return -ENOMEM;
 340
 341         mlx5e_init_frags_partition(rq);
 342
 343         return 0;
 344 }
 345
 346 void mlx5e_free_di_list(struct mlx5e_rq *rq)
 347 {
 348         kvfree(rq->wqe.di);
 349 }
 350
 351 static void mlx5e_rq_err_cqe_work(struct work_struct *recover_work)
 352 {
 353         struct mlx5e_rq *rq = container_of(recover_work, struct mlx5e_rq, recover_work);
 354
 355         mlx5e_reporter_rq_cqe_err(rq);
 356 }
 357
 358 static int mlx5e_alloc_mpwqe_rq_drop_page(struct mlx5e_rq *rq)
 359 {
 360         rq->wqe_overflow.page = alloc_page(GFP_KERNEL);
 361         if (!rq->wqe_overflow.page)
 362                 return -ENOMEM;
 363
 364         rq->wqe_overflow.addr = dma_map_page(rq->pdev, rq->wqe_overflow.page, 0,
 365                                              PAGE_SIZE, rq->buff.map_dir);
 366         if (dma_mapping_error(rq->pdev, rq->wqe_overflow.addr)) {
 367                 __free_page(rq->wqe_overflow.page);
 368                 return -ENOMEM;
 369         }
 370         return 0;
 371 }
 372
 373 static void mlx5e_free_mpwqe_rq_drop_page(struct mlx5e_rq *rq)
 374 {
 375          dma_unmap_page(rq->pdev, rq->wqe_overflow.addr, PAGE_SIZE,
 376                         rq->buff.map_dir);
 377          __free_page(rq->wqe_overflow.page);
 378 }
 379
 380 static int mlx5e_init_rxq_rq(struct mlx5e_channel *c, struct mlx5e_params *params,
 381                              struct mlx5e_rq *rq)
 382 {
 383         struct mlx5_core_dev *mdev = c->mdev;
 384         int err;
 385
 386         rq->wq_type      = params->rq_wq_type;
 387         rq->pdev         = c->pdev;
 388         rq->netdev       = c->netdev;
 389         rq->priv         = c->priv;
 390         rq->tstamp       = c->tstamp;
 391         rq->clock        = &mdev->clock;
 392         rq->icosq        = &c->icosq;
 393         rq->ix           = c->ix;
 394         rq->mdev         = mdev;
 395         rq->hw_mtu       = MLX5E_SW2HW_MTU(params, params->sw_mtu);
 396         rq->xdpsq        = &c->rq_xdpsq;
 397         rq->stats        = &c->priv->channel_stats[c->ix].rq;
 398         rq->ptp_cyc2time = mlx5_rq_ts_translator(mdev);
 399         err = mlx5e_rq_set_handlers(rq, params, NULL);
 400         if (err)
 401                 return err;
 402
 403         return xdp_rxq_info_reg(&rq->xdp_rxq, rq->netdev, rq->ix, 0);
 404 }
 405
 406 static int mlx5e_alloc_rq(struct mlx5e_params *params,
 407                           struct mlx5e_xsk_param *xsk,
 408                           struct mlx5e_rq_param *rqp,
 409                           int node, struct mlx5e_rq *rq)
 410 {
 411         struct page_pool_params pp_params = { 0 };
 412         struct mlx5_core_dev *mdev = rq->mdev;
 413         void *rqc = rqp->rqc;
 414         void *rqc_wq = MLX5_ADDR_OF(rqc, rqc, wq);
 415         u32 pool_size;
 416         int wq_sz;
 417         int err;
 418         int i;
 419
 420         rqp->wq.db_numa_node = node;
 421         INIT_WORK(&rq->recover_work, mlx5e_rq_err_cqe_work);
 422
 423         if (params->xdp_prog)
 424                 bpf_prog_inc(params->xdp_prog);
 425         RCU_INIT_POINTER(rq->xdp_prog, params->xdp_prog);
 426
 427         rq->buff.map_dir = params->xdp_prog ? DMA_BIDIRECTIONAL : DMA_FROM_DEVICE;
 428         rq->buff.headroom = mlx5e_get_rq_headroom(mdev, params, xsk);
 429         pool_size = 1 << params->log_rq_mtu_frames;
 430
 431         switch (rq->wq_type) {
 432         case MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ:
 433                 err = mlx5_wq_ll_create(mdev, &rqp->wq, rqc_wq, &rq->mpwqe.wq,
 434                                         &rq->wq_ctrl);
 435                 if (err)
 436                         goto err_rq_xdp_prog;
 437
 438                 err = mlx5e_alloc_mpwqe_rq_drop_page(rq);
 439                 if (err)
 440                         goto err_rq_wq_destroy;
 441
 442                 rq->mpwqe.wq.db = &rq->mpwqe.wq.db[MLX5_RCV_DBR];
 443
 444                 wq_sz = mlx5_wq_ll_get_size(&rq->mpwqe.wq);
 445
 446                 pool_size = MLX5_MPWRQ_PAGES_PER_WQE <<
 447                         mlx5e_mpwqe_get_log_rq_size(params, xsk);
 448
 449                 rq->mpwqe.log_stride_sz = mlx5e_mpwqe_get_log_stride_size(mdev, params, xsk);
 450                 rq->mpwqe.num_strides =
 451                         BIT(mlx5e_mpwqe_get_log_num_strides(mdev, params, xsk));
 452
 453                 rq->buff.frame0_sz = (1 << rq->mpwqe.log_stride_sz);
 454
 455                 err = mlx5e_create_rq_umr_mkey(mdev, rq);
 456                 if (err)
 457                         goto err_rq_drop_page;
 458                 rq->mkey_be = cpu_to_be32(rq->umr_mkey.key);
 459
 460                 err = mlx5e_rq_alloc_mpwqe_info(rq, node);
 461                 if (err)
 462                         goto err_rq_mkey;
 463                 break;
 464         default: /* MLX5_WQ_TYPE_CYCLIC */
 465                 err = mlx5_wq_cyc_create(mdev, &rqp->wq, rqc_wq, &rq->wqe.wq,
 466                                          &rq->wq_ctrl);
 467                 if (err)
 468                         goto err_rq_xdp_prog;
 469
 470                 rq->wqe.wq.db = &rq->wqe.wq.db[MLX5_RCV_DBR];
 471
 472                 wq_sz = mlx5_wq_cyc_get_size(&rq->wqe.wq);
 473
 474                 rq->wqe.info = rqp->frags_info;
 475                 rq->buff.frame0_sz = rq->wqe.info.arr[0].frag_stride;
 476
 477                 rq->wqe.frags =
 478                         kvzalloc_node(array_size(sizeof(*rq->wqe.frags),
 479                                         (wq_sz << rq->wqe.info.log_num_frags)),
 480                                       GFP_KERNEL, node);
 481                 if (!rq->wqe.frags) {
 482                         err = -ENOMEM;
 483                         goto err_rq_wq_destroy;
 484                 }
 485
 486                 err = mlx5e_init_di_list(rq, wq_sz, node);
 487                 if (err)
 488                         goto err_rq_frags;
 489
 490                 rq->mkey_be = cpu_to_be32(mdev->mlx5e_res.hw_objs.mkey.key);
 491         }
 492
 493         if (xsk) {
 494                 err = xdp_rxq_info_reg_mem_model(&rq->xdp_rxq,
 495                                                  MEM_TYPE_XSK_BUFF_POOL, NULL);
 496                 xsk_pool_set_rxq_info(rq->xsk_pool, &rq->xdp_rxq);
 497         } else {
 498                 /* Create a page_pool and register it with rxq */
 499                 pp_params.order     = 0;
 500                 pp_params.flags     = 0; /* No-internal DMA mapping in page_pool */
 501                 pp_params.pool_size = pool_size;
 502                 pp_params.nid       = node;
 503                 pp_params.dev       = rq->pdev;
 504                 pp_params.dma_dir   = rq->buff.map_dir;
 505
 506                 /* page_pool can be used even when there is no rq->xdp_prog,
 507                  * given page_pool does not handle DMA mapping there is no
 508                  * required state to clear. And page_pool gracefully handle
 509                  * elevated refcnt.
 510                  */
 511                 rq->page_pool = page_pool_create(&pp_params);
 512                 if (IS_ERR(rq->page_pool)) {
 513                         err = PTR_ERR(rq->page_pool);
 514                         rq->page_pool = NULL;
 515                         goto err_free_by_rq_type;
 516                 }
 517                 if (xdp_rxq_info_is_reg(&rq->xdp_rxq))
 518                         err = xdp_rxq_info_reg_mem_model(&rq->xdp_rxq,
 519                                                          MEM_TYPE_PAGE_POOL, rq->page_pool);
 520         }
 521         if (err)
 522                 goto err_free_by_rq_type;
 523
 524         for (i = 0; i < wq_sz; i++) {
 525                 if (rq->wq_type == MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ) {
 526                         struct mlx5e_rx_wqe_ll *wqe =
 527                                 mlx5_wq_ll_get_wqe(&rq->mpwqe.wq, i);
 528                         u32 byte_count =
 529                                 rq->mpwqe.num_strides << rq->mpwqe.log_stride_sz;
 530                         u64 dma_offset = mlx5e_get_mpwqe_offset(i);
 531
 532                         wqe->data[0].addr = cpu_to_be64(dma_offset + rq->buff.headroom);
 533                         wqe->data[0].byte_count = cpu_to_be32(byte_count);
 534                         wqe->data[0].lkey = rq->mkey_be;
 535                 } else {
 536                         struct mlx5e_rx_wqe_cyc *wqe =
 537                                 mlx5_wq_cyc_get_wqe(&rq->wqe.wq, i);
 538                         int f;
 539
 540                         for (f = 0; f < rq->wqe.info.num_frags; f++) {
 541                                 u32 frag_size = rq->wqe.info.arr[f].frag_size |
 542                                         MLX5_HW_START_PADDING;
 543
 544                                 wqe->data[f].byte_count = cpu_to_be32(frag_size);
 545                                 wqe->data[f].lkey = rq->mkey_be;
 546                         }
 547                         /* check if num_frags is not a pow of two */
 548                         if (rq->wqe.info.num_frags < (1 << rq->wqe.info.log_num_frags)) {
 549                                 wqe->data[f].byte_count = 0;
 550                                 wqe->data[f].lkey = cpu_to_be32(MLX5_INVALID_LKEY);
 551                                 wqe->data[f].addr = 0;
 552                         }
 553                 }
 554         }
 555
 556         INIT_WORK(&rq->dim.work, mlx5e_rx_dim_work);
 557
 558         switch (params->rx_cq_moderation.cq_period_mode) {
 559         case MLX5_CQ_PERIOD_MODE_START_FROM_CQE:
 560                 rq->dim.mode = DIM_CQ_PERIOD_MODE_START_FROM_CQE;
 561                 break;
 562         case MLX5_CQ_PERIOD_MODE_START_FROM_EQE:
 563         default:
 564                 rq->dim.mode = DIM_CQ_PERIOD_MODE_START_FROM_EQE;
 565         }
 566
 567         rq->page_cache.head = 0;
 568         rq->page_cache.tail = 0;
 569
 570         return 0;
 571
 572 err_free_by_rq_type:
 573         switch (rq->wq_type) {
 574         case MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ:
 575                 kvfree(rq->mpwqe.info);
 576 err_rq_mkey:
 577                 mlx5_core_destroy_mkey(mdev, &rq->umr_mkey);
 578 err_rq_drop_page:
 579                 mlx5e_free_mpwqe_rq_drop_page(rq);
 580                 break;
 581         default: /* MLX5_WQ_TYPE_CYCLIC */
 582                 mlx5e_free_di_list(rq);
 583 err_rq_frags:
 584                 kvfree(rq->wqe.frags);
 585         }
 586 err_rq_wq_destroy:
 587         mlx5_wq_destroy(&rq->wq_ctrl);
 588 err_rq_xdp_prog:
 589         if (params->xdp_prog)
 590                 bpf_prog_put(params->xdp_prog);
 591
 592         return err;
 593 }
 594
 595 static void mlx5e_free_rq(struct mlx5e_rq *rq)
 596 {
 597         struct bpf_prog *old_prog;
 598         int i;
 599
 600         if (xdp_rxq_info_is_reg(&rq->xdp_rxq)) {
 601                 old_prog = rcu_dereference_protected(rq->xdp_prog,
 602                                                      lockdep_is_held(&rq->priv->state_lock));
 603                 if (old_prog)
 604                         bpf_prog_put(old_prog);
 605         }
 606
 607         switch (rq->wq_type) {
 608         case MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ:
 609                 kvfree(rq->mpwqe.info);
 610                 mlx5_core_destroy_mkey(rq->mdev, &rq->umr_mkey);
 611                 mlx5e_free_mpwqe_rq_drop_page(rq);
 612                 break;
 613         default: /* MLX5_WQ_TYPE_CYCLIC */
 614                 kvfree(rq->wqe.frags);
 615                 mlx5e_free_di_list(rq);
 616         }
 617
 618         for (i = rq->page_cache.head; i != rq->page_cache.tail;
 619              i = (i + 1) & (MLX5E_CACHE_SIZE - 1)) {
 620                 struct mlx5e_dma_info *dma_info = &rq->page_cache.page_cache[i];
 621
 622                 /* With AF_XDP, page_cache is not used, so this loop is not
 623                  * entered, and it's safe to call mlx5e_page_release_dynamic
 624                  * directly.
 625                  */
 626                 mlx5e_page_release_dynamic(rq, dma_info, false);
 627         }
 628
 629         xdp_rxq_info_unreg(&rq->xdp_rxq);
 630         page_pool_destroy(rq->page_pool);
 631         mlx5_wq_destroy(&rq->wq_ctrl);
 632 }
 633
 634 int mlx5e_create_rq(struct mlx5e_rq *rq, struct mlx5e_rq_param *param)
 635 {
 636         struct mlx5_core_dev *mdev = rq->mdev;
 637         u8 ts_format;
 638         void *in;
 639         void *rqc;
 640         void *wq;
 641         int inlen;
 642         int err;
 643
 644         inlen = MLX5_ST_SZ_BYTES(create_rq_in) +
 645                 sizeof(u64) * rq->wq_ctrl.buf.npages;
 646         in = kvzalloc(inlen, GFP_KERNEL);
 647         if (!in)
 648                 return -ENOMEM;
 649
 650         ts_format = mlx5_is_real_time_rq(mdev) ?
 651                             MLX5_TIMESTAMP_FORMAT_REAL_TIME :
 652                             MLX5_TIMESTAMP_FORMAT_FREE_RUNNING;
 653         rqc = MLX5_ADDR_OF(create_rq_in, in, ctx);
 654         wq  = MLX5_ADDR_OF(rqc, rqc, wq);
 655
 656         memcpy(rqc, param->rqc, sizeof(param->rqc));
 657
 658         MLX5_SET(rqc,  rqc, cqn,                rq->cq.mcq.cqn);
 659         MLX5_SET(rqc,  rqc, state,              MLX5_RQC_STATE_RST);
 660         MLX5_SET(rqc,  rqc, ts_format,          ts_format);
 661         MLX5_SET(wq,   wq,  log_wq_pg_sz,       rq->wq_ctrl.buf.page_shift -
 662                                                 MLX5_ADAPTER_PAGE_SHIFT);
 663         MLX5_SET64(wq, wq,  dbr_addr,           rq->wq_ctrl.db.dma);
 664
 665         mlx5_fill_page_frag_array(&rq->wq_ctrl.buf,
 666                                   (__be64 *)MLX5_ADDR_OF(wq, wq, pas));
 667
 668         err = mlx5_core_create_rq(mdev, in, inlen, &rq->rqn);
 669
 670         kvfree(in);
 671
 672         return err;
 673 }
 674
 675 int mlx5e_modify_rq_state(struct mlx5e_rq *rq, int curr_state, int next_state)
 676 {
 677         struct mlx5_core_dev *mdev = rq->mdev;
 678
 679         void *in;
 680         void *rqc;
 681         int inlen;
 682         int err;
 683
 684         inlen = MLX5_ST_SZ_BYTES(modify_rq_in);
 685         in = kvzalloc(inlen, GFP_KERNEL);
 686         if (!in)
 687                 return -ENOMEM;
 688
 689         if (curr_state == MLX5_RQC_STATE_RST && next_state == MLX5_RQC_STATE_RDY)
 690                 mlx5e_rqwq_reset(rq);
 691
 692         rqc = MLX5_ADDR_OF(modify_rq_in, in, ctx);
 693
 694         MLX5_SET(modify_rq_in, in, rq_state, curr_state);
 695         MLX5_SET(rqc, rqc, state, next_state);
 696
 697         err = mlx5_core_modify_rq(mdev, rq->rqn, in);
 698
 699         kvfree(in);
 700
 701         return err;
 702 }
 703
 704 static int mlx5e_modify_rq_scatter_fcs(struct mlx5e_rq *rq, bool enable)
 705 {
 706         struct mlx5_core_dev *mdev = rq->mdev;
 707
 708         void *in;
 709         void *rqc;
 710         int inlen;
 711         int err;
 712
 713         inlen = MLX5_ST_SZ_BYTES(modify_rq_in);
 714         in = kvzalloc(inlen, GFP_KERNEL);
 715         if (!in)
 716                 return -ENOMEM;
 717
 718         rqc = MLX5_ADDR_OF(modify_rq_in, in, ctx);
 719
 720         MLX5_SET(modify_rq_in, in, rq_state, MLX5_RQC_STATE_RDY);
 721         MLX5_SET64(modify_rq_in, in, modify_bitmask,
 722                    MLX5_MODIFY_RQ_IN_MODIFY_BITMASK_SCATTER_FCS);
 723         MLX5_SET(rqc, rqc, scatter_fcs, enable);
 724         MLX5_SET(rqc, rqc, state, MLX5_RQC_STATE_RDY);
 725
 726         err = mlx5_core_modify_rq(mdev, rq->rqn, in);
 727
 728         kvfree(in);
 729
 730         return err;
 731 }
 732
 733 static int mlx5e_modify_rq_vsd(struct mlx5e_rq *rq, bool vsd)
 734 {
 735         struct mlx5_core_dev *mdev = rq->mdev;
 736         void *in;
 737         void *rqc;
 738         int inlen;
 739         int err;
 740
 741         inlen = MLX5_ST_SZ_BYTES(modify_rq_in);
 742         in = kvzalloc(inlen, GFP_KERNEL);
 743         if (!in)
 744                 return -ENOMEM;
 745
 746         rqc = MLX5_ADDR_OF(modify_rq_in, in, ctx);
 747
 748         MLX5_SET(modify_rq_in, in, rq_state, MLX5_RQC_STATE_RDY);
 749         MLX5_SET64(modify_rq_in, in, modify_bitmask,
 750                    MLX5_MODIFY_RQ_IN_MODIFY_BITMASK_VSD);
 751         MLX5_SET(rqc, rqc, vsd, vsd);
 752         MLX5_SET(rqc, rqc, state, MLX5_RQC_STATE_RDY);
 753
 754         err = mlx5_core_modify_rq(mdev, rq->rqn, in);
 755
 756         kvfree(in);
 757
 758         return err;
 759 }
 760
 761 void mlx5e_destroy_rq(struct mlx5e_rq *rq)
 762 {
 763         mlx5_core_destroy_rq(rq->mdev, rq->rqn);
 764 }
 765
 766 int mlx5e_wait_for_min_rx_wqes(struct mlx5e_rq *rq, int wait_time)
 767 {
 768         unsigned long exp_time = jiffies + msecs_to_jiffies(wait_time);
 769
 770         u16 min_wqes = mlx5_min_rx_wqes(rq->wq_type, mlx5e_rqwq_get_size(rq));
 771
 772         do {
 773                 if (mlx5e_rqwq_get_cur_sz(rq) >= min_wqes)
 774                         return 0;
 775
 776                 msleep(20);
 777         } while (time_before(jiffies, exp_time));
 778
 779         netdev_warn(rq->netdev, "Failed to get min RX wqes on Channel[%d] RQN[0x%x] wq cur_sz(%d) min_rx_wqes(%d)\n",
 780                     rq->ix, rq->rqn, mlx5e_rqwq_get_cur_sz(rq), min_wqes);
 781
 782         mlx5e_reporter_rx_timeout(rq);
 783         return -ETIMEDOUT;
 784 }
 785
 786 void mlx5e_free_rx_in_progress_descs(struct mlx5e_rq *rq)
 787 {
 788         struct mlx5_wq_ll *wq;
 789         u16 head;
 790         int i;
 791
 792         if (rq->wq_type != MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ)
 793                 return;
 794
 795         wq = &rq->mpwqe.wq;
 796         head = wq->head;
 797
 798         /* Outstanding UMR WQEs (in progress) start at wq->head */
 799         for (i = 0; i < rq->mpwqe.umr_in_progress; i++) {
 800                 rq->dealloc_wqe(rq, head);
 801                 head = mlx5_wq_ll_get_wqe_next_ix(wq, head);
 802         }
 803
 804         rq->mpwqe.actual_wq_head = wq->head;
 805         rq->mpwqe.umr_in_progress = 0;
 806         rq->mpwqe.umr_completed = 0;
 807 }
 808
 809 void mlx5e_free_rx_descs(struct mlx5e_rq *rq)
 810 {
 811         __be16 wqe_ix_be;
 812         u16 wqe_ix;
 813
 814         if (rq->wq_type == MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ) {
 815                 struct mlx5_wq_ll *wq = &rq->mpwqe.wq;
 816
 817                 mlx5e_free_rx_in_progress_descs(rq);
 818
 819                 while (!mlx5_wq_ll_is_empty(wq)) {
 820                         struct mlx5e_rx_wqe_ll *wqe;
 821
 822                         wqe_ix_be = *wq->tail_next;
 823                         wqe_ix    = be16_to_cpu(wqe_ix_be);
 824                         wqe       = mlx5_wq_ll_get_wqe(wq, wqe_ix);
 825                         rq->dealloc_wqe(rq, wqe_ix);
 826                         mlx5_wq_ll_pop(wq, wqe_ix_be,
 827                                        &wqe->next.next_wqe_index);
 828                 }
 829         } else {
 830                 struct mlx5_wq_cyc *wq = &rq->wqe.wq;
 831
 832                 while (!mlx5_wq_cyc_is_empty(wq)) {
 833                         wqe_ix = mlx5_wq_cyc_get_tail(wq);
 834                         rq->dealloc_wqe(rq, wqe_ix);
 835                         mlx5_wq_cyc_pop(wq);
 836                 }
 837         }
 838
 839 }
 840
 841 int mlx5e_open_rq(struct mlx5e_params *params, struct mlx5e_rq_param *param,
 842                   struct mlx5e_xsk_param *xsk, int node,
 843                   struct mlx5e_rq *rq)
 844 {
 845         struct mlx5_core_dev *mdev = rq->mdev;
 846         int err;
 847
 848         err = mlx5e_alloc_rq(params, xsk, param, node, rq);
 849         if (err)
 850                 return err;
 851
 852         err = mlx5e_create_rq(rq, param);
 853         if (err)
 854                 goto err_free_rq;
 855
 856         err = mlx5e_modify_rq_state(rq, MLX5_RQC_STATE_RST, MLX5_RQC_STATE_RDY);
 857         if (err)
 858                 goto err_destroy_rq;
 859
 860         if (mlx5e_is_tls_on(rq->priv) && !mlx5e_accel_is_ktls_device(mdev))
 861                 __set_bit(MLX5E_RQ_STATE_FPGA_TLS, &rq->state); /* must be FPGA */
 862
 863         if (MLX5_CAP_ETH(mdev, cqe_checksum_full))
 864                 __set_bit(MLX5E_RQ_STATE_CSUM_FULL, &rq->state);
 865
 866         if (params->rx_dim_enabled)
 867                 __set_bit(MLX5E_RQ_STATE_AM, &rq->state);
 868
 869         /* We disable csum_complete when XDP is enabled since
 870          * XDP programs might manipulate packets which will render
 871          * skb->checksum incorrect.
 872          */
 873         if (MLX5E_GET_PFLAG(params, MLX5E_PFLAG_RX_NO_CSUM_COMPLETE) || params->xdp_prog)
 874                 __set_bit(MLX5E_RQ_STATE_NO_CSUM_COMPLETE, &rq->state);
 875
 876         /* For CQE compression on striding RQ, use stride index provided by
 877          * HW if capability is supported.
 878          */
 879         if (MLX5E_GET_PFLAG(params, MLX5E_PFLAG_RX_STRIDING_RQ) &&
 880             MLX5_CAP_GEN(mdev, mini_cqe_resp_stride_index))
 881                 __set_bit(MLX5E_RQ_STATE_MINI_CQE_HW_STRIDX, &rq->state);
 882
 883         return 0;
 884
 885 err_destroy_rq:
 886         mlx5e_destroy_rq(rq);
 887 err_free_rq:
 888         mlx5e_free_rq(rq);
 889
 890         return err;
 891 }
 892
 893 void mlx5e_activate_rq(struct mlx5e_rq *rq)
 894 {
 895         set_bit(MLX5E_RQ_STATE_ENABLED, &rq->state);
 896         if (rq->icosq) {
 897                 mlx5e_trigger_irq(rq->icosq);
 898         } else {
 899                 local_bh_disable();
 900                 napi_schedule(rq->cq.napi);
 901                 local_bh_enable();
 902         }
 903 }
 904
 905 void mlx5e_deactivate_rq(struct mlx5e_rq *rq)
 906 {
 907         clear_bit(MLX5E_RQ_STATE_ENABLED, &rq->state);
 908         synchronize_net(); /* Sync with NAPI to prevent mlx5e_post_rx_wqes. */
 909 }
 910
 911 void mlx5e_close_rq(struct mlx5e_rq *rq)
 912 {
 913         cancel_work_sync(&rq->dim.work);
 914         if (rq->icosq)
 915                 cancel_work_sync(&rq->icosq->recover_work);
 916         cancel_work_sync(&rq->recover_work);
 917         mlx5e_destroy_rq(rq);
 918         mlx5e_free_rx_descs(rq);
 919         mlx5e_free_rq(rq);
 920 }
 921
 922 static void mlx5e_free_xdpsq_db(struct mlx5e_xdpsq *sq)
 923 {
 924         kvfree(sq->db.xdpi_fifo.xi);
 925         kvfree(sq->db.wqe_info);
 926 }
 927
 928 static int mlx5e_alloc_xdpsq_fifo(struct mlx5e_xdpsq *sq, int numa)
 929 {
 930         struct mlx5e_xdp_info_fifo *xdpi_fifo = &sq->db.xdpi_fifo;
 931         int wq_sz        = mlx5_wq_cyc_get_size(&sq->wq);
 932         int dsegs_per_wq = wq_sz * MLX5_SEND_WQEBB_NUM_DS;
 933
 934         xdpi_fifo->xi = kvzalloc_node(sizeof(*xdpi_fifo->xi) * dsegs_per_wq,
 935                                       GFP_KERNEL, numa);
 936         if (!xdpi_fifo->xi)
 937                 return -ENOMEM;
 938
 939         xdpi_fifo->pc   = &sq->xdpi_fifo_pc;
 940         xdpi_fifo->cc   = &sq->xdpi_fifo_cc;
 941         xdpi_fifo->mask = dsegs_per_wq - 1;
 942
 943         return 0;
 944 }
 945
 946 static int mlx5e_alloc_xdpsq_db(struct mlx5e_xdpsq *sq, int numa)
 947 {
 948         int wq_sz = mlx5_wq_cyc_get_size(&sq->wq);
 949         int err;
 950
 951         sq->db.wqe_info = kvzalloc_node(sizeof(*sq->db.wqe_info) * wq_sz,
 952                                         GFP_KERNEL, numa);
 953         if (!sq->db.wqe_info)
 954                 return -ENOMEM;
 955
 956         err = mlx5e_alloc_xdpsq_fifo(sq, numa);
 957         if (err) {
 958                 mlx5e_free_xdpsq_db(sq);
 959                 return err;
 960         }
 961
 962         return 0;
 963 }
 964
 965 static int mlx5e_alloc_xdpsq(struct mlx5e_channel *c,
 966                              struct mlx5e_params *params,
 967                              struct xsk_buff_pool *xsk_pool,
 968                              struct mlx5e_sq_param *param,
 969                              struct mlx5e_xdpsq *sq,
 970                              bool is_redirect)
 971 {
 972         void *sqc_wq               = MLX5_ADDR_OF(sqc, param->sqc, wq);
 973         struct mlx5_core_dev *mdev = c->mdev;
 974         struct mlx5_wq_cyc *wq = &sq->wq;
 975         int err;
 976
 977         sq->pdev      = c->pdev;
 978         sq->mkey_be   = c->mkey_be;
 979         sq->channel   = c;
 980         sq->uar_map   = mdev->mlx5e_res.hw_objs.bfreg.map;
 981         sq->min_inline_mode = params->tx_min_inline_mode;
 982         sq->hw_mtu    = MLX5E_SW2HW_MTU(params, params->sw_mtu);
 983         sq->xsk_pool  = xsk_pool;
 984
 985         sq->stats = sq->xsk_pool ?
 986                 &c->priv->channel_stats[c->ix].xsksq :
 987                 is_redirect ?
 988                         &c->priv->channel_stats[c->ix].xdpsq :
 989                         &c->priv->channel_stats[c->ix].rq_xdpsq;
 990
 991         param->wq.db_numa_node = cpu_to_node(c->cpu);
 992         err = mlx5_wq_cyc_create(mdev, &param->wq, sqc_wq, wq, &sq->wq_ctrl);
 993         if (err)
 994                 return err;
 995         wq->db = &wq->db[MLX5_SND_DBR];
 996
 997         err = mlx5e_alloc_xdpsq_db(sq, cpu_to_node(c->cpu));
 998         if (err)
 999                 goto err_sq_wq_destroy;
1000
1001         return 0;
1002
1003 err_sq_wq_destroy:
1004         mlx5_wq_destroy(&sq->wq_ctrl);
1005
1006         return err;
1007 }
1008
1009 static void mlx5e_free_xdpsq(struct mlx5e_xdpsq *sq)
1010 {
1011         mlx5e_free_xdpsq_db(sq);
1012         mlx5_wq_destroy(&sq->wq_ctrl);
1013 }
1014
1015 static void mlx5e_free_icosq_db(struct mlx5e_icosq *sq)
1016 {
1017         kvfree(sq->db.wqe_info);
1018 }
1019
1020 static int mlx5e_alloc_icosq_db(struct mlx5e_icosq *sq, int numa)
1021 {
1022         int wq_sz = mlx5_wq_cyc_get_size(&sq->wq);
1023         size_t size;
1024
1025         size = array_size(wq_sz, sizeof(*sq->db.wqe_info));
1026         sq->db.wqe_info = kvzalloc_node(size, GFP_KERNEL, numa);
1027         if (!sq->db.wqe_info)
1028                 return -ENOMEM;
1029
1030         return 0;
1031 }
1032
1033 static void mlx5e_icosq_err_cqe_work(struct work_struct *recover_work)
1034 {
1035         struct mlx5e_icosq *sq = container_of(recover_work, struct mlx5e_icosq,
1036                                               recover_work);
1037
1038         mlx5e_reporter_icosq_cqe_err(sq);
1039 }
1040
1041 static int mlx5e_alloc_icosq(struct mlx5e_channel *c,
1042                              struct mlx5e_sq_param *param,
1043                              struct mlx5e_icosq *sq)
1044 {
1045         void *sqc_wq               = MLX5_ADDR_OF(sqc, param->sqc, wq);
1046         struct mlx5_core_dev *mdev = c->mdev;
1047         struct mlx5_wq_cyc *wq = &sq->wq;
1048         int err;
1049
1050         sq->channel   = c;
1051         sq->uar_map   = mdev->mlx5e_res.hw_objs.bfreg.map;
1052         sq->reserved_room = param->stop_room;
1053
1054         param->wq.db_numa_node = cpu_to_node(c->cpu);
1055         err = mlx5_wq_cyc_create(mdev, &param->wq, sqc_wq, wq, &sq->wq_ctrl);
1056         if (err)
1057                 return err;
1058         wq->db = &wq->db[MLX5_SND_DBR];
1059
1060         err = mlx5e_alloc_icosq_db(sq, cpu_to_node(c->cpu));
1061         if (err)
1062                 goto err_sq_wq_destroy;
1063
1064         INIT_WORK(&sq->recover_work, mlx5e_icosq_err_cqe_work);
1065
1066         return 0;
1067
1068 err_sq_wq_destroy:
1069         mlx5_wq_destroy(&sq->wq_ctrl);
1070
1071         return err;
1072 }
1073
1074 static void mlx5e_free_icosq(struct mlx5e_icosq *sq)
1075 {
1076         mlx5e_free_icosq_db(sq);
1077         mlx5_wq_destroy(&sq->wq_ctrl);
1078 }
1079
1080 void mlx5e_free_txqsq_db(struct mlx5e_txqsq *sq)
1081 {
1082         kvfree(sq->db.wqe_info);
1083         kvfree(sq->db.skb_fifo.fifo);
1084         kvfree(sq->db.dma_fifo);
1085 }
1086
1087 int mlx5e_alloc_txqsq_db(struct mlx5e_txqsq *sq, int numa)
1088 {
1089         int wq_sz = mlx5_wq_cyc_get_size(&sq->wq);
1090         int df_sz = wq_sz * MLX5_SEND_WQEBB_NUM_DS;
1091
1092         sq->db.dma_fifo = kvzalloc_node(array_size(df_sz,
1093                                                    sizeof(*sq->db.dma_fifo)),
1094                                         GFP_KERNEL, numa);
1095         sq->db.skb_fifo.fifo = kvzalloc_node(array_size(df_sz,
1096                                                         sizeof(*sq->db.skb_fifo.fifo)),
1097                                         GFP_KERNEL, numa);
1098         sq->db.wqe_info = kvzalloc_node(array_size(wq_sz,
1099                                                    sizeof(*sq->db.wqe_info)),
1100                                         GFP_KERNEL, numa);
1101         if (!sq->db.dma_fifo || !sq->db.skb_fifo.fifo || !sq->db.wqe_info) {
1102                 mlx5e_free_txqsq_db(sq);
1103                 return -ENOMEM;
1104         }
1105
1106         sq->dma_fifo_mask = df_sz - 1;
1107
1108         sq->db.skb_fifo.pc   = &sq->skb_fifo_pc;
1109         sq->db.skb_fifo.cc   = &sq->skb_fifo_cc;
1110         sq->db.skb_fifo.mask = df_sz - 1;
1111
1112         return 0;
1113 }
1114
1115 static int mlx5e_alloc_txqsq(struct mlx5e_channel *c,
1116                              int txq_ix,
1117                              struct mlx5e_params *params,
1118                              struct mlx5e_sq_param *param,
1119                              struct mlx5e_txqsq *sq,
1120                              int tc)
1121 {
1122         void *sqc_wq               = MLX5_ADDR_OF(sqc, param->sqc, wq);
1123         struct mlx5_core_dev *mdev = c->mdev;
1124         struct mlx5_wq_cyc *wq = &sq->wq;
1125         int err;
1126
1127         sq->pdev      = c->pdev;
1128         sq->tstamp    = c->tstamp;
1129         sq->clock     = &mdev->clock;
1130         sq->mkey_be   = c->mkey_be;
1131         sq->netdev    = c->netdev;
1132         sq->mdev      = c->mdev;
1133         sq->priv      = c->priv;
1134         sq->ch_ix     = c->ix;
1135         sq->txq_ix    = txq_ix;
1136         sq->uar_map   = mdev->mlx5e_res.hw_objs.bfreg.map;
1137         sq->min_inline_mode = params->tx_min_inline_mode;
1138         sq->hw_mtu    = MLX5E_SW2HW_MTU(params, params->sw_mtu);
1139         INIT_WORK(&sq->recover_work, mlx5e_tx_err_cqe_work);
1140         if (!MLX5_CAP_ETH(mdev, wqe_vlan_insert))
1141                 set_bit(MLX5E_SQ_STATE_VLAN_NEED_L2_INLINE, &sq->state);
1142         if (MLX5_IPSEC_DEV(c->priv->mdev))
1143                 set_bit(MLX5E_SQ_STATE_IPSEC, &sq->state);
1144         if (param->is_mpw)
1145                 set_bit(MLX5E_SQ_STATE_MPWQE, &sq->state);
1146         sq->stop_room = param->stop_room;
1147         sq->ptp_cyc2time = mlx5_sq_ts_translator(mdev);
1148
1149         param->wq.db_numa_node = cpu_to_node(c->cpu);
1150         err = mlx5_wq_cyc_create(mdev, &param->wq, sqc_wq, wq, &sq->wq_ctrl);
1151         if (err)
1152                 return err;
1153         wq->db    = &wq->db[MLX5_SND_DBR];
1154
1155         err = mlx5e_alloc_txqsq_db(sq, cpu_to_node(c->cpu));
1156         if (err)
1157                 goto err_sq_wq_destroy;
1158
1159         INIT_WORK(&sq->dim.work, mlx5e_tx_dim_work);
1160         sq->dim.mode = params->tx_cq_moderation.cq_period_mode;
1161
1162         return 0;
1163
1164 err_sq_wq_destroy:
1165         mlx5_wq_destroy(&sq->wq_ctrl);
1166
1167         return err;
1168 }
1169
1170 void mlx5e_free_txqsq(struct mlx5e_txqsq *sq)
1171 {
1172         mlx5e_free_txqsq_db(sq);
1173         mlx5_wq_destroy(&sq->wq_ctrl);
1174 }
1175
1176 static int mlx5e_create_sq(struct mlx5_core_dev *mdev,
1177                            struct mlx5e_sq_param *param,
1178                            struct mlx5e_create_sq_param *csp,
1179                            u32 *sqn)
1180 {
1181         u8 ts_format;
1182         void *in;
1183         void *sqc;
1184         void *wq;
1185         int inlen;
1186         int err;
1187
1188         inlen = MLX5_ST_SZ_BYTES(create_sq_in) +
1189                 sizeof(u64) * csp->wq_ctrl->buf.npages;
1190         in = kvzalloc(inlen, GFP_KERNEL);
1191         if (!in)
1192                 return -ENOMEM;
1193
1194         ts_format = mlx5_is_real_time_sq(mdev) ?
1195                             MLX5_TIMESTAMP_FORMAT_REAL_TIME :
1196                             MLX5_TIMESTAMP_FORMAT_FREE_RUNNING;
1197         sqc = MLX5_ADDR_OF(create_sq_in, in, ctx);
1198         wq = MLX5_ADDR_OF(sqc, sqc, wq);
1199
1200         memcpy(sqc, param->sqc, sizeof(param->sqc));
1201         MLX5_SET(sqc,  sqc, tis_lst_sz, csp->tis_lst_sz);
1202         MLX5_SET(sqc,  sqc, tis_num_0, csp->tisn);
1203         MLX5_SET(sqc,  sqc, cqn, csp->cqn);
1204         MLX5_SET(sqc,  sqc, ts_cqe_to_dest_cqn, csp->ts_cqe_to_dest_cqn);
1205         MLX5_SET(sqc,  sqc, ts_format, ts_format);
1206
1207
1208         if (MLX5_CAP_ETH(mdev, wqe_inline_mode) == MLX5_CAP_INLINE_MODE_VPORT_CONTEXT)
1209                 MLX5_SET(sqc,  sqc, min_wqe_inline_mode, csp->min_inline_mode);
1210
1211         MLX5_SET(sqc,  sqc, state, MLX5_SQC_STATE_RST);
1212         MLX5_SET(sqc,  sqc, flush_in_error_en, 1);
1213
1214         MLX5_SET(wq,   wq, wq_type,       MLX5_WQ_TYPE_CYCLIC);
1215         MLX5_SET(wq,   wq, uar_page,      mdev->mlx5e_res.hw_objs.bfreg.index);
1216         MLX5_SET(wq,   wq, log_wq_pg_sz,  csp->wq_ctrl->buf.page_shift -
1217                                           MLX5_ADAPTER_PAGE_SHIFT);
1218         MLX5_SET64(wq, wq, dbr_addr,      csp->wq_ctrl->db.dma);
1219
1220         mlx5_fill_page_frag_array(&csp->wq_ctrl->buf,
1221                                   (__be64 *)MLX5_ADDR_OF(wq, wq, pas));
1222
1223         err = mlx5_core_create_sq(mdev, in, inlen, sqn);
1224
1225         kvfree(in);
1226
1227         return err;
1228 }
1229
1230 int mlx5e_modify_sq(struct mlx5_core_dev *mdev, u32 sqn,
1231                     struct mlx5e_modify_sq_param *p)
1232 {
1233         u64 bitmask = 0;
1234         void *in;
1235         void *sqc;
1236         int inlen;
1237         int err;
1238
1239         inlen = MLX5_ST_SZ_BYTES(modify_sq_in);
1240         in = kvzalloc(inlen, GFP_KERNEL);
1241         if (!in)
1242                 return -ENOMEM;
1243
1244         sqc = MLX5_ADDR_OF(modify_sq_in, in, ctx);
1245
1246         MLX5_SET(modify_sq_in, in, sq_state, p->curr_state);
1247         MLX5_SET(sqc, sqc, state, p->next_state);
1248         if (p->rl_update && p->next_state == MLX5_SQC_STATE_RDY) {
1249                 bitmask |= 1;
1250                 MLX5_SET(sqc, sqc, packet_pacing_rate_limit_index, p->rl_index);
1251         }
1252         if (p->qos_update && p->next_state == MLX5_SQC_STATE_RDY) {
1253                 bitmask |= 1 << 2;
1254                 MLX5_SET(sqc, sqc, qos_queue_group_id, p->qos_queue_group_id);
1255         }
1256         MLX5_SET64(modify_sq_in, in, modify_bitmask, bitmask);
1257
1258         err = mlx5_core_modify_sq(mdev, sqn, in);
1259
1260         kvfree(in);
1261
1262         return err;
1263 }
1264
1265 static void mlx5e_destroy_sq(struct mlx5_core_dev *mdev, u32 sqn)
1266 {
1267         mlx5_core_destroy_sq(mdev, sqn);
1268 }
1269
1270 int mlx5e_create_sq_rdy(struct mlx5_core_dev *mdev,
1271                         struct mlx5e_sq_param *param,
1272                         struct mlx5e_create_sq_param *csp,
1273                         u16 qos_queue_group_id,
1274                         u32 *sqn)
1275 {
1276         struct mlx5e_modify_sq_param msp = {0};
1277         int err;
1278
1279         err = mlx5e_create_sq(mdev, param, csp, sqn);
1280         if (err)
1281                 return err;
1282
1283         msp.curr_state = MLX5_SQC_STATE_RST;
1284         msp.next_state = MLX5_SQC_STATE_RDY;
1285         if (qos_queue_group_id) {
1286                 msp.qos_update = true;
1287                 msp.qos_queue_group_id = qos_queue_group_id;
1288         }
1289         err = mlx5e_modify_sq(mdev, *sqn, &msp);
1290         if (err)
1291                 mlx5e_destroy_sq(mdev, *sqn);
1292
1293         return err;
1294 }
1295
1296 static int mlx5e_set_sq_maxrate(struct net_device *dev,
1297                                 struct mlx5e_txqsq *sq, u32 rate);
1298
1299 int mlx5e_open_txqsq(struct mlx5e_channel *c, u32 tisn, int txq_ix,
1300                      struct mlx5e_params *params, struct mlx5e_sq_param *param,
1301                      struct mlx5e_txqsq *sq, int tc, u16 qos_queue_group_id, u16 qos_qid)
1302 {
1303         struct mlx5e_create_sq_param csp = {};
1304         u32 tx_rate;
1305         int err;
1306
1307         err = mlx5e_alloc_txqsq(c, txq_ix, params, param, sq, tc);
1308         if (err)
1309                 return err;
1310
1311         if (qos_queue_group_id)
1312                 sq->stats = c->priv->htb.qos_sq_stats[qos_qid];
1313         else
1314                 sq->stats = &c->priv->channel_stats[c->ix].sq[tc];
1315
1316         csp.tisn            = tisn;
1317         csp.tis_lst_sz      = 1;
1318         csp.cqn             = sq->cq.mcq.cqn;
1319         csp.wq_ctrl         = &sq->wq_ctrl;
1320         csp.min_inline_mode = sq->min_inline_mode;
1321         err = mlx5e_create_sq_rdy(c->mdev, param, &csp, qos_queue_group_id, &sq->sqn);
1322         if (err)
1323                 goto err_free_txqsq;
1324
1325         tx_rate = c->priv->tx_rates[sq->txq_ix];
1326         if (tx_rate)
1327                 mlx5e_set_sq_maxrate(c->netdev, sq, tx_rate);
1328
1329         if (params->tx_dim_enabled)
1330                 sq->state |= BIT(MLX5E_SQ_STATE_AM);
1331
1332         return 0;
1333
1334 err_free_txqsq:
1335         mlx5e_free_txqsq(sq);
1336
1337         return err;
1338 }
1339
1340 void mlx5e_activate_txqsq(struct mlx5e_txqsq *sq)
1341 {
1342         sq->txq = netdev_get_tx_queue(sq->netdev, sq->txq_ix);
1343         set_bit(MLX5E_SQ_STATE_ENABLED, &sq->state);
1344         netdev_tx_reset_queue(sq->txq);
1345         netif_tx_start_queue(sq->txq);
1346 }
1347
1348 void mlx5e_tx_disable_queue(struct netdev_queue *txq)
1349 {
1350         __netif_tx_lock_bh(txq);
1351         netif_tx_stop_queue(txq);
1352         __netif_tx_unlock_bh(txq);
1353 }
1354
1355 void mlx5e_deactivate_txqsq(struct mlx5e_txqsq *sq)
1356 {
1357         struct mlx5_wq_cyc *wq = &sq->wq;
1358
1359         clear_bit(MLX5E_SQ_STATE_ENABLED, &sq->state);
1360         synchronize_net(); /* Sync with NAPI to prevent netif_tx_wake_queue. */
1361
1362         mlx5e_tx_disable_queue(sq->txq);
1363
1364         /* last doorbell out, godspeed .. */
1365         if (mlx5e_wqc_has_room_for(wq, sq->cc, sq->pc, 1)) {
1366                 u16 pi = mlx5_wq_cyc_ctr2ix(wq, sq->pc);
1367                 struct mlx5e_tx_wqe *nop;
1368
1369                 sq->db.wqe_info[pi] = (struct mlx5e_tx_wqe_info) {
1370                         .num_wqebbs = 1,
1371                 };
1372
1373                 nop = mlx5e_post_nop(wq, sq->sqn, &sq->pc);
1374                 mlx5e_notify_hw(wq, sq->pc, sq->uar_map, &nop->ctrl);
1375         }
1376 }
1377
1378 void mlx5e_close_txqsq(struct mlx5e_txqsq *sq)
1379 {
1380         struct mlx5_core_dev *mdev = sq->mdev;
1381         struct mlx5_rate_limit rl = {0};
1382
1383         cancel_work_sync(&sq->dim.work);
1384         cancel_work_sync(&sq->recover_work);
1385         mlx5e_destroy_sq(mdev, sq->sqn);
1386         if (sq->rate_limit) {
1387                 rl.rate = sq->rate_limit;
1388                 mlx5_rl_remove_rate(mdev, &rl);
1389         }
1390         mlx5e_free_txqsq_descs(sq);
1391         mlx5e_free_txqsq(sq);
1392 }
1393
1394 void mlx5e_tx_err_cqe_work(struct work_struct *recover_work)
1395 {
1396         struct mlx5e_txqsq *sq = container_of(recover_work, struct mlx5e_txqsq,
1397                                               recover_work);
1398
1399         mlx5e_reporter_tx_err_cqe(sq);
1400 }
1401
1402 int mlx5e_open_icosq(struct mlx5e_channel *c, struct mlx5e_params *params,
1403                      struct mlx5e_sq_param *param, struct mlx5e_icosq *sq)
1404 {
1405         struct mlx5e_create_sq_param csp = {};
1406         int err;
1407
1408         err = mlx5e_alloc_icosq(c, param, sq);
1409         if (err)
1410                 return err;
1411
1412         csp.cqn             = sq->cq.mcq.cqn;
1413         csp.wq_ctrl         = &sq->wq_ctrl;
1414         csp.min_inline_mode = params->tx_min_inline_mode;
1415         err = mlx5e_create_sq_rdy(c->mdev, param, &csp, 0, &sq->sqn);
1416         if (err)
1417                 goto err_free_icosq;
1418
1419         if (param->is_tls) {
1420                 sq->ktls_resync = mlx5e_ktls_rx_resync_create_resp_list();
1421                 if (IS_ERR(sq->ktls_resync)) {
1422                         err = PTR_ERR(sq->ktls_resync);
1423                         goto err_destroy_icosq;
1424                 }
1425         }
1426         return 0;
1427
1428 err_destroy_icosq:
1429         mlx5e_destroy_sq(c->mdev, sq->sqn);
1430 err_free_icosq:
1431         mlx5e_free_icosq(sq);
1432
1433         return err;
1434 }
1435
1436 void mlx5e_activate_icosq(struct mlx5e_icosq *icosq)
1437 {
1438         set_bit(MLX5E_SQ_STATE_ENABLED, &icosq->state);
1439 }
1440
1441 void mlx5e_deactivate_icosq(struct mlx5e_icosq *icosq)
1442 {
1443         clear_bit(MLX5E_SQ_STATE_ENABLED, &icosq->state);
1444         synchronize_net(); /* Sync with NAPI. */
1445 }
1446
1447 void mlx5e_close_icosq(struct mlx5e_icosq *sq)
1448 {
1449         struct mlx5e_channel *c = sq->channel;
1450
1451         if (sq->ktls_resync)
1452                 mlx5e_ktls_rx_resync_destroy_resp_list(sq->ktls_resync);
1453         mlx5e_destroy_sq(c->mdev, sq->sqn);
1454         mlx5e_free_icosq_descs(sq);
1455         mlx5e_free_icosq(sq);
1456 }
1457
1458 int mlx5e_open_xdpsq(struct mlx5e_channel *c, struct mlx5e_params *params,
1459                      struct mlx5e_sq_param *param, struct xsk_buff_pool *xsk_pool,
1460                      struct mlx5e_xdpsq *sq, bool is_redirect)
1461 {
1462         struct mlx5e_create_sq_param csp = {};
1463         int err;
1464
1465         err = mlx5e_alloc_xdpsq(c, params, xsk_pool, param, sq, is_redirect);
1466         if (err)
1467                 return err;
1468
1469         csp.tis_lst_sz      = 1;
1470         csp.tisn            = c->priv->tisn[c->lag_port][0]; /* tc = 0 */
1471         csp.cqn             = sq->cq.mcq.cqn;
1472         csp.wq_ctrl         = &sq->wq_ctrl;
1473         csp.min_inline_mode = sq->min_inline_mode;
1474         set_bit(MLX5E_SQ_STATE_ENABLED, &sq->state);
1475         err = mlx5e_create_sq_rdy(c->mdev, param, &csp, 0, &sq->sqn);
1476         if (err)
1477                 goto err_free_xdpsq;
1478
1479         mlx5e_set_xmit_fp(sq, param->is_mpw);
1480
1481         if (!param->is_mpw) {
1482                 unsigned int ds_cnt = MLX5E_XDP_TX_DS_COUNT;
1483                 unsigned int inline_hdr_sz = 0;
1484                 int i;
1485
1486                 if (sq->min_inline_mode != MLX5_INLINE_MODE_NONE) {
1487                         inline_hdr_sz = MLX5E_XDP_MIN_INLINE;
1488                         ds_cnt++;
1489                 }
1490
1491                 /* Pre initialize fixed WQE fields */
1492                 for (i = 0; i < mlx5_wq_cyc_get_size(&sq->wq); i++) {
1493                         struct mlx5e_tx_wqe      *wqe  = mlx5_wq_cyc_get_wqe(&sq->wq, i);
1494                         struct mlx5_wqe_ctrl_seg *cseg = &wqe->ctrl;
1495                         struct mlx5_wqe_eth_seg  *eseg = &wqe->eth;
1496                         struct mlx5_wqe_data_seg *dseg;
1497
1498                         sq->db.wqe_info[i] = (struct mlx5e_xdp_wqe_info) {
1499                                 .num_wqebbs = 1,
1500                                 .num_pkts   = 1,
1501                         };
1502
1503                         cseg->qpn_ds = cpu_to_be32((sq->sqn << 8) | ds_cnt);
1504                         eseg->inline_hdr.sz = cpu_to_be16(inline_hdr_sz);
1505
1506                         dseg = (struct mlx5_wqe_data_seg *)cseg + (ds_cnt - 1);
1507                         dseg->lkey = sq->mkey_be;
1508                 }
1509         }
1510
1511         return 0;
1512
1513 err_free_xdpsq:
1514         clear_bit(MLX5E_SQ_STATE_ENABLED, &sq->state);
1515         mlx5e_free_xdpsq(sq);
1516
1517         return err;
1518 }
1519
1520 void mlx5e_close_xdpsq(struct mlx5e_xdpsq *sq)
1521 {
1522         struct mlx5e_channel *c = sq->channel;
1523
1524         clear_bit(MLX5E_SQ_STATE_ENABLED, &sq->state);
1525         synchronize_net(); /* Sync with NAPI. */
1526
1527         mlx5e_destroy_sq(c->mdev, sq->sqn);
1528         mlx5e_free_xdpsq_descs(sq);
1529         mlx5e_free_xdpsq(sq);
1530 }
1531
1532 static int mlx5e_alloc_cq_common(struct mlx5e_priv *priv,
1533                                  struct mlx5e_cq_param *param,
1534                                  struct mlx5e_cq *cq)
1535 {
1536         struct mlx5_core_dev *mdev = priv->mdev;
1537         struct mlx5_core_cq *mcq = &cq->mcq;
1538         int eqn_not_used;
1539         unsigned int irqn;
1540         int err;
1541         u32 i;
1542
1543         err = mlx5_vector2eqn(mdev, param->eq_ix, &eqn_not_used, &irqn);
1544         if (err)
1545                 return err;
1546
1547         err = mlx5_cqwq_create(mdev, &param->wq, param->cqc, &cq->wq,
1548                                &cq->wq_ctrl);
1549         if (err)
1550                 return err;
1551
1552         mcq->cqe_sz     = 64;
1553         mcq->set_ci_db  = cq->wq_ctrl.db.db;
1554         mcq->arm_db     = cq->wq_ctrl.db.db + 1;
1555         *mcq->set_ci_db = 0;
1556         *mcq->arm_db    = 0;
1557         mcq->vector     = param->eq_ix;
1558         mcq->comp       = mlx5e_completion_event;
1559         mcq->event      = mlx5e_cq_error_event;
1560         mcq->irqn       = irqn;
1561
1562         for (i = 0; i < mlx5_cqwq_get_size(&cq->wq); i++) {
1563                 struct mlx5_cqe64 *cqe = mlx5_cqwq_get_wqe(&cq->wq, i);
1564
1565                 cqe->op_own = 0xf1;
1566         }
1567
1568         cq->mdev = mdev;
1569         cq->netdev = priv->netdev;
1570         cq->priv = priv;
1571
1572         return 0;
1573 }
1574
1575 static int mlx5e_alloc_cq(struct mlx5e_priv *priv,
1576                           struct mlx5e_cq_param *param,
1577                           struct mlx5e_create_cq_param *ccp,
1578                           struct mlx5e_cq *cq)
1579 {
1580         int err;
1581
1582         param->wq.buf_numa_node = ccp->node;
1583         param->wq.db_numa_node  = ccp->node;
1584         param->eq_ix            = ccp->ix;
1585
1586         err = mlx5e_alloc_cq_common(priv, param, cq);
1587
1588         cq->napi     = ccp->napi;
1589         cq->ch_stats = ccp->ch_stats;
1590
1591         return err;
1592 }
1593
1594 static void mlx5e_free_cq(struct mlx5e_cq *cq)
1595 {
1596         mlx5_wq_destroy(&cq->wq_ctrl);
1597 }
1598
1599 static int mlx5e_create_cq(struct mlx5e_cq *cq, struct mlx5e_cq_param *param)
1600 {
1601         u32 out[MLX5_ST_SZ_DW(create_cq_out)];
1602         struct mlx5_core_dev *mdev = cq->mdev;
1603         struct mlx5_core_cq *mcq = &cq->mcq;
1604
1605         void *in;
1606         void *cqc;
1607         int inlen;
1608         unsigned int irqn_not_used;
1609         int eqn;
1610         int err;
1611
1612         err = mlx5_vector2eqn(mdev, param->eq_ix, &eqn, &irqn_not_used);
1613         if (err)
1614                 return err;
1615
1616         inlen = MLX5_ST_SZ_BYTES(create_cq_in) +
1617                 sizeof(u64) * cq->wq_ctrl.buf.npages;
1618         in = kvzalloc(inlen, GFP_KERNEL);
1619         if (!in)
1620                 return -ENOMEM;
1621
1622         cqc = MLX5_ADDR_OF(create_cq_in, in, cq_context);
1623
1624         memcpy(cqc, param->cqc, sizeof(param->cqc));
1625
1626         mlx5_fill_page_frag_array(&cq->wq_ctrl.buf,
1627                                   (__be64 *)MLX5_ADDR_OF(create_cq_in, in, pas));
1628
1629         MLX5_SET(cqc,   cqc, cq_period_mode, param->cq_period_mode);
1630         MLX5_SET(cqc,   cqc, c_eqn,         eqn);
1631         MLX5_SET(cqc,   cqc, uar_page,      mdev->priv.uar->index);
1632         MLX5_SET(cqc,   cqc, log_page_size, cq->wq_ctrl.buf.page_shift -
1633                                             MLX5_ADAPTER_PAGE_SHIFT);
1634         MLX5_SET64(cqc, cqc, dbr_addr,      cq->wq_ctrl.db.dma);
1635
1636         err = mlx5_core_create_cq(mdev, mcq, in, inlen, out, sizeof(out));
1637
1638         kvfree(in);
1639
1640         if (err)
1641                 return err;
1642
1643         mlx5e_cq_arm(cq);
1644
1645         return 0;
1646 }
1647
1648 static void mlx5e_destroy_cq(struct mlx5e_cq *cq)
1649 {
1650         mlx5_core_destroy_cq(cq->mdev, &cq->mcq);
1651 }
1652
1653 int mlx5e_open_cq(struct mlx5e_priv *priv, struct dim_cq_moder moder,
1654                   struct mlx5e_cq_param *param, struct mlx5e_create_cq_param *ccp,
1655                   struct mlx5e_cq *cq)
1656 {
1657         struct mlx5_core_dev *mdev = priv->mdev;
1658         int err;
1659
1660         err = mlx5e_alloc_cq(priv, param, ccp, cq);
1661         if (err)
1662                 return err;
1663
1664         err = mlx5e_create_cq(cq, param);
1665         if (err)
1666                 goto err_free_cq;
1667
1668         if (MLX5_CAP_GEN(mdev, cq_moderation))
1669                 mlx5_core_modify_cq_moderation(mdev, &cq->mcq, moder.usec, moder.pkts);
1670         return 0;
1671
1672 err_free_cq:
1673         mlx5e_free_cq(cq);
1674
1675         return err;
1676 }
1677
1678 void mlx5e_close_cq(struct mlx5e_cq *cq)
1679 {
1680         mlx5e_destroy_cq(cq);
1681         mlx5e_free_cq(cq);
1682 }
1683
1684 static int mlx5e_open_tx_cqs(struct mlx5e_channel *c,
1685                              struct mlx5e_params *params,
1686                              struct mlx5e_create_cq_param *ccp,
1687                              struct mlx5e_channel_param *cparam)
1688 {
1689         int err;
1690         int tc;
1691
1692         for (tc = 0; tc < c->num_tc; tc++) {
1693                 err = mlx5e_open_cq(c->priv, params->tx_cq_moderation, &cparam->txq_sq.cqp,
1694                                     ccp, &c->sq[tc].cq);
1695                 if (err)
1696                         goto err_close_tx_cqs;
1697         }
1698
1699         return 0;
1700
1701 err_close_tx_cqs:
1702         for (tc--; tc >= 0; tc--)
1703                 mlx5e_close_cq(&c->sq[tc].cq);
1704
1705         return err;
1706 }
1707
1708 static void mlx5e_close_tx_cqs(struct mlx5e_channel *c)
1709 {
1710         int tc;
1711
1712         for (tc = 0; tc < c->num_tc; tc++)
1713                 mlx5e_close_cq(&c->sq[tc].cq);
1714 }
1715
1716 static int mlx5e_open_sqs(struct mlx5e_channel *c,
1717                           struct mlx5e_params *params,
1718                           struct mlx5e_channel_param *cparam)
1719 {
1720         int err, tc;
1721
1722         for (tc = 0; tc < params->num_tc; tc++) {
1723                 int txq_ix = c->ix + tc * params->num_channels;
1724
1725                 err = mlx5e_open_txqsq(c, c->priv->tisn[c->lag_port][tc], txq_ix,
1726                                        params, &cparam->txq_sq, &c->sq[tc], tc, 0, 0);
1727                 if (err)
1728                         goto err_close_sqs;
1729         }
1730
1731         return 0;
1732
1733 err_close_sqs:
1734         for (tc--; tc >= 0; tc--)
1735                 mlx5e_close_txqsq(&c->sq[tc]);
1736
1737         return err;
1738 }
1739
1740 static void mlx5e_close_sqs(struct mlx5e_channel *c)
1741 {
1742         int tc;
1743
1744         for (tc = 0; tc < c->num_tc; tc++)
1745                 mlx5e_close_txqsq(&c->sq[tc]);
1746 }
1747
1748 static int mlx5e_set_sq_maxrate(struct net_device *dev,
1749                                 struct mlx5e_txqsq *sq, u32 rate)
1750 {
1751         struct mlx5e_priv *priv = netdev_priv(dev);
1752         struct mlx5_core_dev *mdev = priv->mdev;
1753         struct mlx5e_modify_sq_param msp = {0};
1754         struct mlx5_rate_limit rl = {0};
1755         u16 rl_index = 0;
1756         int err;
1757
1758         if (rate == sq->rate_limit)
1759                 /* nothing to do */
1760                 return 0;
1761
1762         if (sq->rate_limit) {
1763                 rl.rate = sq->rate_limit;
1764                 /* remove current rl index to free space to next ones */
1765                 mlx5_rl_remove_rate(mdev, &rl);
1766         }
1767
1768         sq->rate_limit = 0;
1769
1770         if (rate) {
1771                 rl.rate = rate;
1772                 err = mlx5_rl_add_rate(mdev, &rl_index, &rl);
1773                 if (err) {
1774                         netdev_err(dev, "Failed configuring rate %u: %d\n",
1775                                    rate, err);
1776                         return err;
1777                 }
1778         }
1779
1780         msp.curr_state = MLX5_SQC_STATE_RDY;
1781         msp.next_state = MLX5_SQC_STATE_RDY;
1782         msp.rl_index   = rl_index;
1783         msp.rl_update  = true;
1784         err = mlx5e_modify_sq(mdev, sq->sqn, &msp);
1785         if (err) {
1786                 netdev_err(dev, "Failed configuring rate %u: %d\n",
1787                            rate, err);
1788                 /* remove the rate from the table */
1789                 if (rate)
1790                         mlx5_rl_remove_rate(mdev, &rl);
1791                 return err;
1792         }
1793
1794         sq->rate_limit = rate;
1795         return 0;
1796 }
1797
1798 static int mlx5e_set_tx_maxrate(struct net_device *dev, int index, u32 rate)
1799 {
1800         struct mlx5e_priv *priv = netdev_priv(dev);
1801         struct mlx5_core_dev *mdev = priv->mdev;
1802         struct mlx5e_txqsq *sq = priv->txq2sq[index];
1803         int err = 0;
1804
1805         if (!mlx5_rl_is_supported(mdev)) {
1806                 netdev_err(dev, "Rate limiting is not supported on this device\n");
1807                 return -EINVAL;
1808         }
1809
1810         /* rate is given in Mb/sec, HW config is in Kb/sec */
1811         rate = rate << 10;
1812
1813         /* Check whether rate in valid range, 0 is always valid */
1814         if (rate && !mlx5_rl_is_in_range(mdev, rate)) {
1815                 netdev_err(dev, "TX rate %u, is not in range\n", rate);
1816                 return -ERANGE;
1817         }
1818
1819         mutex_lock(&priv->state_lock);
1820         if (test_bit(MLX5E_STATE_OPENED, &priv->state))
1821                 err = mlx5e_set_sq_maxrate(dev, sq, rate);
1822         if (!err)
1823                 priv->tx_rates[index] = rate;
1824         mutex_unlock(&priv->state_lock);
1825
1826         return err;
1827 }
1828
1829 static int mlx5e_open_rxq_rq(struct mlx5e_channel *c, struct mlx5e_params *params,
1830                              struct mlx5e_rq_param *rq_params)
1831 {
1832         int err;
1833
1834         err = mlx5e_init_rxq_rq(c, params, &c->rq);
1835         if (err)
1836                 return err;
1837
1838         return mlx5e_open_rq(params, rq_params, NULL, cpu_to_node(c->cpu), &c->rq);
1839 }
1840
1841 static int mlx5e_open_queues(struct mlx5e_channel *c,
1842                              struct mlx5e_params *params,
1843                              struct mlx5e_channel_param *cparam)
1844 {
1845         struct dim_cq_moder icocq_moder = {0, 0};
1846         struct mlx5e_create_cq_param ccp;
1847         int err;
1848
1849         mlx5e_build_create_cq_param(&ccp, c);
1850
1851         err = mlx5e_open_cq(c->priv, icocq_moder, &cparam->async_icosq.cqp, &ccp,
1852                             &c->async_icosq.cq);
1853         if (err)
1854                 return err;
1855
1856         err = mlx5e_open_cq(c->priv, icocq_moder, &cparam->icosq.cqp, &ccp,
1857                             &c->icosq.cq);
1858         if (err)
1859                 goto err_close_async_icosq_cq;
1860
1861         err = mlx5e_open_tx_cqs(c, params, &ccp, cparam);
1862         if (err)
1863                 goto err_close_icosq_cq;
1864
1865         err = mlx5e_open_cq(c->priv, params->tx_cq_moderation, &cparam->xdp_sq.cqp, &ccp,
1866                             &c->xdpsq.cq);
1867         if (err)
1868                 goto err_close_tx_cqs;
1869
1870         err = mlx5e_open_cq(c->priv, params->rx_cq_moderation, &cparam->rq.cqp, &ccp,
1871                             &c->rq.cq);
1872         if (err)
1873                 goto err_close_xdp_tx_cqs;
1874
1875         err = c->xdp ? mlx5e_open_cq(c->priv, params->tx_cq_moderation, &cparam->xdp_sq.cqp,
1876                                      &ccp, &c->rq_xdpsq.cq) : 0;
1877         if (err)
1878                 goto err_close_rx_cq;
1879
1880         spin_lock_init(&c->async_icosq_lock);
1881
1882         err = mlx5e_open_icosq(c, params, &cparam->async_icosq, &c->async_icosq);
1883         if (err)
1884                 goto err_close_xdpsq_cq;
1885
1886         err = mlx5e_open_icosq(c, params, &cparam->icosq, &c->icosq);
1887         if (err)
1888                 goto err_close_async_icosq;
1889
1890         err = mlx5e_open_sqs(c, params, cparam);
1891         if (err)
1892                 goto err_close_icosq;
1893
1894         if (c->xdp) {
1895                 err = mlx5e_open_xdpsq(c, params, &cparam->xdp_sq, NULL,
1896                                        &c->rq_xdpsq, false);
1897                 if (err)
1898                         goto err_close_sqs;
1899         }
1900
1901         err = mlx5e_open_rxq_rq(c, params, &cparam->rq);
1902         if (err)
1903                 goto err_close_xdp_sq;
1904
1905         err = mlx5e_open_xdpsq(c, params, &cparam->xdp_sq, NULL, &c->xdpsq, true);
1906         if (err)
1907                 goto err_close_rq;
1908
1909         return 0;
1910
1911 err_close_rq:
1912         mlx5e_close_rq(&c->rq);
1913
1914 err_close_xdp_sq:
1915         if (c->xdp)
1916                 mlx5e_close_xdpsq(&c->rq_xdpsq);
1917
1918 err_close_sqs:
1919         mlx5e_close_sqs(c);
1920
1921 err_close_icosq:
1922         mlx5e_close_icosq(&c->icosq);
1923
1924 err_close_async_icosq:
1925         mlx5e_close_icosq(&c->async_icosq);
1926
1927 err_close_xdpsq_cq:
1928         if (c->xdp)
1929                 mlx5e_close_cq(&c->rq_xdpsq.cq);
1930
1931 err_close_rx_cq:
1932         mlx5e_close_cq(&c->rq.cq);
1933
1934 err_close_xdp_tx_cqs:
1935         mlx5e_close_cq(&c->xdpsq.cq);
1936
1937 err_close_tx_cqs:
1938         mlx5e_close_tx_cqs(c);
1939
1940 err_close_icosq_cq:
1941         mlx5e_close_cq(&c->icosq.cq);
1942
1943 err_close_async_icosq_cq:
1944         mlx5e_close_cq(&c->async_icosq.cq);
1945
1946         return err;
1947 }
1948
1949 static void mlx5e_close_queues(struct mlx5e_channel *c)
1950 {
1951         mlx5e_close_xdpsq(&c->xdpsq);
1952         mlx5e_close_rq(&c->rq);
1953         if (c->xdp)
1954                 mlx5e_close_xdpsq(&c->rq_xdpsq);
1955         mlx5e_close_sqs(c);
1956         mlx5e_close_icosq(&c->icosq);
1957         mlx5e_close_icosq(&c->async_icosq);
1958         if (c->xdp)
1959                 mlx5e_close_cq(&c->rq_xdpsq.cq);
1960         mlx5e_close_cq(&c->rq.cq);
1961         mlx5e_close_cq(&c->xdpsq.cq);
1962         mlx5e_close_tx_cqs(c);
1963         mlx5e_close_cq(&c->icosq.cq);
1964         mlx5e_close_cq(&c->async_icosq.cq);
1965 }
1966
1967 static u8 mlx5e_enumerate_lag_port(struct mlx5_core_dev *mdev, int ix)
1968 {
1969         u16 port_aff_bias = mlx5_core_is_pf(mdev) ? 0 : MLX5_CAP_GEN(mdev, vhca_id);
1970
1971         return (ix + port_aff_bias) % mlx5e_get_num_lag_ports(mdev);
1972 }
1973
1974 static int mlx5e_open_channel(struct mlx5e_priv *priv, int ix,
1975                               struct mlx5e_params *params,
1976                               struct mlx5e_channel_param *cparam,
1977                               struct xsk_buff_pool *xsk_pool,
1978                               struct mlx5e_channel **cp)
1979 {
1980         int cpu = cpumask_first(mlx5_comp_irq_get_affinity_mask(priv->mdev, ix));
1981         struct net_device *netdev = priv->netdev;
1982         struct mlx5e_xsk_param xsk;
1983         struct mlx5e_channel *c;
1984         unsigned int irq;
1985         int err;
1986         int eqn;
1987
1988         err = mlx5_vector2eqn(priv->mdev, ix, &eqn, &irq);
1989         if (err)
1990                 return err;
1991
1992         c = kvzalloc_node(sizeof(*c), GFP_KERNEL, cpu_to_node(cpu));
1993         if (!c)
1994                 return -ENOMEM;
1995
1996         c->priv     = priv;
1997         c->mdev     = priv->mdev;
1998         c->tstamp   = &priv->tstamp;
1999         c->ix       = ix;
2000         c->cpu      = cpu;
2001         c->pdev     = mlx5_core_dma_dev(priv->mdev);
2002         c->netdev   = priv->netdev;
2003         c->mkey_be  = cpu_to_be32(priv->mdev->mlx5e_res.hw_objs.mkey.key);
2004         c->num_tc   = params->num_tc;
2005         c->xdp      = !!params->xdp_prog;
2006         c->stats    = &priv->channel_stats[ix].ch;
2007         c->aff_mask = irq_get_effective_affinity_mask(irq);
2008         c->lag_port = mlx5e_enumerate_lag_port(priv->mdev, ix);
2009
2010         netif_napi_add(netdev, &c->napi, mlx5e_napi_poll, 64);
2011
2012         err = mlx5e_open_queues(c, params, cparam);
2013         if (unlikely(err))
2014                 goto err_napi_del;
2015
2016         if (xsk_pool) {
2017                 mlx5e_build_xsk_param(xsk_pool, &xsk);
2018                 err = mlx5e_open_xsk(priv, params, &xsk, xsk_pool, c);
2019                 if (unlikely(err))
2020                         goto err_close_queues;
2021         }
2022
2023         *cp = c;
2024
2025         return 0;
2026
2027 err_close_queues:
2028         mlx5e_close_queues(c);
2029
2030 err_napi_del:
2031         netif_napi_del(&c->napi);
2032
2033         kvfree(c);
2034
2035         return err;
2036 }
2037
2038 static void mlx5e_activate_channel(struct mlx5e_channel *c)
2039 {
2040         int tc;
2041
2042         napi_enable(&c->napi);
2043
2044         for (tc = 0; tc < c->num_tc; tc++)
2045                 mlx5e_activate_txqsq(&c->sq[tc]);
2046         mlx5e_activate_icosq(&c->icosq);
2047         mlx5e_activate_icosq(&c->async_icosq);
2048         mlx5e_activate_rq(&c->rq);
2049
2050         if (test_bit(MLX5E_CHANNEL_STATE_XSK, c->state))
2051                 mlx5e_activate_xsk(c);
2052 }
2053
2054 static void mlx5e_deactivate_channel(struct mlx5e_channel *c)
2055 {
2056         int tc;
2057
2058         if (test_bit(MLX5E_CHANNEL_STATE_XSK, c->state))
2059                 mlx5e_deactivate_xsk(c);
2060
2061         mlx5e_deactivate_rq(&c->rq);
2062         mlx5e_deactivate_icosq(&c->async_icosq);
2063         mlx5e_deactivate_icosq(&c->icosq);
2064         for (tc = 0; tc < c->num_tc; tc++)
2065                 mlx5e_deactivate_txqsq(&c->sq[tc]);
2066         mlx5e_qos_deactivate_queues(c);
2067
2068         napi_disable(&c->napi);
2069 }
2070
2071 static void mlx5e_close_channel(struct mlx5e_channel *c)
2072 {
2073         if (test_bit(MLX5E_CHANNEL_STATE_XSK, c->state))
2074                 mlx5e_close_xsk(c);
2075         mlx5e_close_queues(c);
2076         mlx5e_qos_close_queues(c);
2077         netif_napi_del(&c->napi);
2078
2079         kvfree(c);
2080 }
2081
2082 int mlx5e_open_channels(struct mlx5e_priv *priv,
2083                         struct mlx5e_channels *chs)
2084 {
2085         struct mlx5e_channel_param *cparam;
2086         int err = -ENOMEM;
2087         int i;
2088
2089         chs->num = chs->params.num_channels;
2090
2091         chs->c = kcalloc(chs->num, sizeof(struct mlx5e_channel *), GFP_KERNEL);
2092         cparam = kvzalloc(sizeof(struct mlx5e_channel_param), GFP_KERNEL);
2093         if (!chs->c || !cparam)
2094                 goto err_free;
2095
2096         err = mlx5e_build_channel_param(priv->mdev, &chs->params, priv->q_counter, cparam);
2097         if (err)
2098                 goto err_free;
2099
2100         for (i = 0; i < chs->num; i++) {
2101                 struct xsk_buff_pool *xsk_pool = NULL;
2102
2103                 if (chs->params.xdp_prog)
2104                         xsk_pool = mlx5e_xsk_get_pool(&chs->params, chs->params.xsk, i);
2105
2106                 err = mlx5e_open_channel(priv, i, &chs->params, cparam, xsk_pool, &chs->c[i]);
2107                 if (err)
2108                         goto err_close_channels;
2109         }
2110
2111         if (MLX5E_GET_PFLAG(&chs->params, MLX5E_PFLAG_TX_PORT_TS) || chs->params.ptp_rx) {
2112                 err = mlx5e_ptp_open(priv, &chs->params, chs->c[0]->lag_port, &chs->ptp);
2113                 if (err)
2114                         goto err_close_channels;
2115         }
2116
2117         err = mlx5e_qos_open_queues(priv, chs);
2118         if (err)
2119                 goto err_close_ptp;
2120
2121         mlx5e_health_channels_update(priv);
2122         kvfree(cparam);
2123         return 0;
2124
2125 err_close_ptp:
2126         if (chs->ptp)
2127                 mlx5e_ptp_close(chs->ptp);
2128
2129 err_close_channels:
2130         for (i--; i >= 0; i--)
2131                 mlx5e_close_channel(chs->c[i]);
2132
2133 err_free:
2134         kfree(chs->c);
2135         kvfree(cparam);
2136         chs->num = 0;
2137         return err;
2138 }
2139
2140 static void mlx5e_activate_channels(struct mlx5e_channels *chs)
2141 {
2142         int i;
2143
2144         for (i = 0; i < chs->num; i++)
2145                 mlx5e_activate_channel(chs->c[i]);
2146
2147         if (chs->ptp)
2148                 mlx5e_ptp_activate_channel(chs->ptp);
2149 }
2150
2151 #define MLX5E_RQ_WQES_TIMEOUT 20000 /* msecs */
2152
2153 static int mlx5e_wait_channels_min_rx_wqes(struct mlx5e_channels *chs)
2154 {
2155         int err = 0;
2156         int i;
2157
2158         for (i = 0; i < chs->num; i++) {
2159                 int timeout = err ? 0 : MLX5E_RQ_WQES_TIMEOUT;
2160
2161                 err |= mlx5e_wait_for_min_rx_wqes(&chs->c[i]->rq, timeout);
2162
2163                 /* Don't wait on the XSK RQ, because the newer xdpsock sample
2164                  * doesn't provide any Fill Ring entries at the setup stage.
2165                  */
2166         }
2167
2168         return err ? -ETIMEDOUT : 0;
2169 }
2170
2171 static void mlx5e_deactivate_channels(struct mlx5e_channels *chs)
2172 {
2173         int i;
2174
2175         if (chs->ptp)
2176                 mlx5e_ptp_deactivate_channel(chs->ptp);
2177
2178         for (i = 0; i < chs->num; i++)
2179                 mlx5e_deactivate_channel(chs->c[i]);
2180 }
2181
2182 void mlx5e_close_channels(struct mlx5e_channels *chs)
2183 {
2184         int i;
2185
2186         if (chs->ptp) {
2187                 mlx5e_ptp_close(chs->ptp);
2188                 chs->ptp = NULL;
2189         }
2190         for (i = 0; i < chs->num; i++)
2191                 mlx5e_close_channel(chs->c[i]);
2192
2193         kfree(chs->c);
2194         chs->num = 0;
2195 }
2196
2197 int mlx5e_create_indirect_rqt(struct mlx5e_priv *priv)
2198 {
2199         int err;
2200
2201         err = mlx5e_rqt_init_direct(&priv->rx_res->indir_rqt, priv->mdev, true,
2202                                     priv->drop_rq.rqn);
2203         if (err)
2204                 mlx5_core_warn(priv->mdev, "create indirect rqts failed, %d\n", err);
2205         return err;
2206 }
2207
2208 int mlx5e_create_direct_rqts(struct mlx5e_priv *priv)
2209 {
2210         int err;
2211         int ix;
2212
2213         for (ix = 0; ix < priv->max_nch; ix++) {
2214                 err = mlx5e_rqt_init_direct(&priv->rx_res->channels[ix].direct_rqt,
2215                                             priv->mdev, false, priv->drop_rq.rqn);
2216                 if (unlikely(err))
2217                         goto err_destroy_rqts;
2218         }
2219
2220         return 0;
2221
2222 err_destroy_rqts:
2223         mlx5_core_warn(priv->mdev, "create direct rqts failed, %d\n", err);
2224         while (--ix >= 0)
2225                 mlx5e_rqt_destroy(&priv->rx_res->channels[ix].direct_rqt);
2226
2227         return err;
2228 }
2229
2230 static int mlx5e_create_xsk_rqts(struct mlx5e_priv *priv)
2231 {
2232         int err;
2233         int ix;
2234
2235         for (ix = 0; ix < priv->max_nch; ix++) {
2236                 err = mlx5e_rqt_init_direct(&priv->rx_res->channels[ix].xsk_rqt,
2237                                             priv->mdev, false, priv->drop_rq.rqn);
2238                 if (unlikely(err))
2239                         goto err_destroy_rqts;
2240         }
2241
2242         return 0;
2243
2244 err_destroy_rqts:
2245         mlx5_core_warn(priv->mdev, "create xsk rqts failed, %d\n", err);
2246         while (--ix >= 0)
2247                 mlx5e_rqt_destroy(&priv->rx_res->channels[ix].xsk_rqt);
2248
2249         return err;
2250 }
2251
2252 void mlx5e_destroy_direct_rqts(struct mlx5e_priv *priv)
2253 {
2254         unsigned int ix;
2255
2256         for (ix = 0; ix < priv->max_nch; ix++)
2257                 mlx5e_rqt_destroy(&priv->rx_res->channels[ix].direct_rqt);
2258 }
2259
2260 static void mlx5e_destroy_xsk_rqts(struct mlx5e_priv *priv)
2261 {
2262         unsigned int ix;
2263
2264         for (ix = 0; ix < priv->max_nch; ix++)
2265                 mlx5e_rqt_destroy(&priv->rx_res->channels[ix].xsk_rqt);
2266 }
2267
2268 static int mlx5e_rx_hash_fn(int hfunc)
2269 {
2270         return (hfunc == ETH_RSS_HASH_TOP) ?
2271                MLX5_RX_HASH_FN_TOEPLITZ :
2272                MLX5_RX_HASH_FN_INVERTED_XOR8;
2273 }
2274
2275 static void mlx5e_redirect_rqts_to_channels(struct mlx5e_priv *priv,
2276                                             struct mlx5e_channels *chs)
2277 {
2278         struct mlx5e_rx_res *res = priv->rx_res;
2279         unsigned int ix;
2280         u32 *rqns;
2281
2282         rqns = kvmalloc_array(chs->num, sizeof(*rqns), GFP_KERNEL);
2283         if (rqns) {
2284                 for (ix = 0; ix < chs->num; ix++)
2285                         rqns[ix] = chs->c[ix]->rq.rqn;
2286
2287                 mlx5e_rqt_redirect_indir(&res->indir_rqt, rqns, chs->num,
2288                                          res->rss_params.hash.hfunc,
2289                                          &res->rss_params.indir);
2290                 kvfree(rqns);
2291         }
2292
2293         for (ix = 0; ix < priv->max_nch; ix++) {
2294                 u32 rqn = priv->drop_rq.rqn;
2295
2296                 if (ix < chs->num)
2297                         rqn = chs->c[ix]->rq.rqn;
2298
2299                 mlx5e_rqt_redirect_direct(&res->channels[ix].direct_rqt, rqn);
2300         }
2301
2302         if (priv->profile->rx_ptp_support) {
2303                 u32 rqn;
2304
2305                 if (mlx5e_ptp_get_rqn(priv->channels.ptp, &rqn))
2306                         rqn = priv->drop_rq.rqn;
2307
2308                 mlx5e_rqt_redirect_direct(&res->ptp.rqt, rqn);
2309         }
2310 }
2311
2312 static void mlx5e_redirect_rqts_to_drop(struct mlx5e_priv *priv)
2313 {
2314         struct mlx5e_rx_res *res = priv->rx_res;
2315         unsigned int ix;
2316
2317         mlx5e_rqt_redirect_direct(&res->indir_rqt, priv->drop_rq.rqn);
2318
2319         for (ix = 0; ix < priv->max_nch; ix++)
2320                 mlx5e_rqt_redirect_direct(&res->channels[ix].direct_rqt, priv->drop_rq.rqn);
2321
2322         if (priv->profile->rx_ptp_support)
2323                 mlx5e_rqt_redirect_direct(&res->ptp.rqt, priv->drop_rq.rqn);
2324 }
2325
2326 static const struct mlx5e_tirc_config tirc_default_config[MLX5E_NUM_INDIR_TIRS] = {
2327         [MLX5E_TT_IPV4_TCP] = { .l3_prot_type = MLX5_L3_PROT_TYPE_IPV4,
2328                                 .l4_prot_type = MLX5_L4_PROT_TYPE_TCP,
2329                                 .rx_hash_fields = MLX5_HASH_IP_L4PORTS,
2330         },
2331         [MLX5E_TT_IPV6_TCP] = { .l3_prot_type = MLX5_L3_PROT_TYPE_IPV6,
2332                                 .l4_prot_type = MLX5_L4_PROT_TYPE_TCP,
2333                                 .rx_hash_fields = MLX5_HASH_IP_L4PORTS,
2334         },
2335         [MLX5E_TT_IPV4_UDP] = { .l3_prot_type = MLX5_L3_PROT_TYPE_IPV4,
2336                                 .l4_prot_type = MLX5_L4_PROT_TYPE_UDP,
2337                                 .rx_hash_fields = MLX5_HASH_IP_L4PORTS,
2338         },
2339         [MLX5E_TT_IPV6_UDP] = { .l3_prot_type = MLX5_L3_PROT_TYPE_IPV6,
2340                                 .l4_prot_type = MLX5_L4_PROT_TYPE_UDP,
2341                                 .rx_hash_fields = MLX5_HASH_IP_L4PORTS,
2342         },
2343         [MLX5E_TT_IPV4_IPSEC_AH] = { .l3_prot_type = MLX5_L3_PROT_TYPE_IPV4,
2344                                      .l4_prot_type = 0,
2345                                      .rx_hash_fields = MLX5_HASH_IP_IPSEC_SPI,
2346         },
2347         [MLX5E_TT_IPV6_IPSEC_AH] = { .l3_prot_type = MLX5_L3_PROT_TYPE_IPV6,
2348                                      .l4_prot_type = 0,
2349                                      .rx_hash_fields = MLX5_HASH_IP_IPSEC_SPI,
2350         },
2351         [MLX5E_TT_IPV4_IPSEC_ESP] = { .l3_prot_type = MLX5_L3_PROT_TYPE_IPV4,
2352                                       .l4_prot_type = 0,
2353                                       .rx_hash_fields = MLX5_HASH_IP_IPSEC_SPI,
2354         },
2355         [MLX5E_TT_IPV6_IPSEC_ESP] = { .l3_prot_type = MLX5_L3_PROT_TYPE_IPV6,
2356                                       .l4_prot_type = 0,
2357                                       .rx_hash_fields = MLX5_HASH_IP_IPSEC_SPI,
2358         },
2359         [MLX5E_TT_IPV4] = { .l3_prot_type = MLX5_L3_PROT_TYPE_IPV4,
2360                             .l4_prot_type = 0,
2361                             .rx_hash_fields = MLX5_HASH_IP,
2362         },
2363         [MLX5E_TT_IPV6] = { .l3_prot_type = MLX5_L3_PROT_TYPE_IPV6,
2364                             .l4_prot_type = 0,
2365                             .rx_hash_fields = MLX5_HASH_IP,
2366         },
2367 };
2368
2369 struct mlx5e_tirc_config mlx5e_tirc_get_default_config(enum mlx5e_traffic_types tt)
2370 {
2371         return tirc_default_config[tt];
2372 }
2373
2374 static void mlx5e_build_tir_ctx_lro(struct mlx5e_lro_param *lro_param, void *tirc)
2375 {
2376         if (!lro_param->enabled)
2377                 return;
2378
2379 #define ROUGH_MAX_L2_L3_HDR_SZ 256
2380
2381         MLX5_SET(tirc, tirc, lro_enable_mask,
2382                  MLX5_TIRC_LRO_ENABLE_MASK_IPV4_LRO |
2383                  MLX5_TIRC_LRO_ENABLE_MASK_IPV6_LRO);
2384         MLX5_SET(tirc, tirc, lro_max_ip_payload_size,
2385                  (MLX5E_PARAMS_DEFAULT_LRO_WQE_SZ - ROUGH_MAX_L2_L3_HDR_SZ) >> 8);
2386         MLX5_SET(tirc, tirc, lro_timeout_period_usecs, lro_param->timeout);
2387 }
2388
2389 void mlx5e_build_indir_tir_ctx_hash(struct mlx5e_rss_params *rss_params,
2390                                     const struct mlx5e_tirc_config *ttconfig,
2391                                     void *tirc, bool inner)
2392 {
2393         void *hfso = inner ? MLX5_ADDR_OF(tirc, tirc, rx_hash_field_selector_inner) :
2394                              MLX5_ADDR_OF(tirc, tirc, rx_hash_field_selector_outer);
2395
2396         MLX5_SET(tirc, tirc, rx_hash_fn, mlx5e_rx_hash_fn(rss_params->hash.hfunc));
2397         if (rss_params->hash.hfunc == ETH_RSS_HASH_TOP) {
2398                 void *rss_key = MLX5_ADDR_OF(tirc, tirc,
2399                                              rx_hash_toeplitz_key);
2400                 size_t len = MLX5_FLD_SZ_BYTES(tirc,
2401                                                rx_hash_toeplitz_key);
2402
2403                 MLX5_SET(tirc, tirc, rx_hash_symmetric, 1);
2404                 memcpy(rss_key, rss_params->hash.toeplitz_hash_key, len);
2405         }
2406         MLX5_SET(rx_hash_field_select, hfso, l3_prot_type,
2407                  ttconfig->l3_prot_type);
2408         MLX5_SET(rx_hash_field_select, hfso, l4_prot_type,
2409                  ttconfig->l4_prot_type);
2410         MLX5_SET(rx_hash_field_select, hfso, selected_fields,
2411                  ttconfig->rx_hash_fields);
2412 }
2413
2414 static void mlx5e_update_rx_hash_fields(struct mlx5e_tirc_config *ttconfig,
2415                                         enum mlx5e_traffic_types tt,
2416                                         u32 rx_hash_fields)
2417 {
2418         *ttconfig                = tirc_default_config[tt];
2419         ttconfig->rx_hash_fields = rx_hash_fields;
2420 }
2421
2422 void mlx5e_modify_tirs_hash(struct mlx5e_priv *priv, void *in)
2423 {
2424         struct mlx5e_rss_params *rss = &priv->rx_res->rss_params;
2425         void *tirc = MLX5_ADDR_OF(modify_tir_in, in, ctx);
2426         struct mlx5e_rx_res *res = priv->rx_res;
2427         struct mlx5_core_dev *mdev = priv->mdev;
2428         int ctxlen = MLX5_ST_SZ_BYTES(tirc);
2429         struct mlx5e_tirc_config ttconfig;
2430         int tt;
2431
2432         MLX5_SET(modify_tir_in, in, bitmask.hash, 1);
2433
2434         for (tt = 0; tt < MLX5E_NUM_INDIR_TIRS; tt++) {
2435                 memset(tirc, 0, ctxlen);
2436                 mlx5e_update_rx_hash_fields(&ttconfig, tt,
2437                                             rss->rx_hash_fields[tt]);
2438                 mlx5e_build_indir_tir_ctx_hash(rss, &ttconfig, tirc, false);
2439                 mlx5_core_modify_tir(mdev, res->rss[tt].indir_tir.tirn, in);
2440         }
2441
2442         /* Verify inner tirs resources allocated */
2443         if (!res->rss[0].inner_indir_tir.tirn)
2444                 return;
2445
2446         for (tt = 0; tt < MLX5E_NUM_INDIR_TIRS; tt++) {
2447                 memset(tirc, 0, ctxlen);
2448                 mlx5e_update_rx_hash_fields(&ttconfig, tt,
2449                                             rss->rx_hash_fields[tt]);
2450                 mlx5e_build_indir_tir_ctx_hash(rss, &ttconfig, tirc, true);
2451                 mlx5_core_modify_tir(mdev, res->rss[tt].inner_indir_tir.tirn, in);
2452         }
2453 }
2454
2455 static int mlx5e_modify_tirs_lro(struct mlx5e_priv *priv)
2456 {
2457         struct mlx5_core_dev *mdev = priv->mdev;
2458         struct mlx5e_rx_res *res = priv->rx_res;
2459         struct mlx5e_lro_param lro_param;
2460
2461         void *in;
2462         void *tirc;
2463         int inlen;
2464         int err;
2465         int tt;
2466         int ix;
2467
2468         inlen = MLX5_ST_SZ_BYTES(modify_tir_in);
2469         in = kvzalloc(inlen, GFP_KERNEL);
2470         if (!in)
2471                 return -ENOMEM;
2472
2473         MLX5_SET(modify_tir_in, in, bitmask.lro, 1);
2474         tirc = MLX5_ADDR_OF(modify_tir_in, in, ctx);
2475
2476         lro_param = mlx5e_get_lro_param(&priv->channels.params);
2477         mlx5e_build_tir_ctx_lro(&lro_param, tirc);
2478
2479         for (tt = 0; tt < MLX5E_NUM_INDIR_TIRS; tt++) {
2480                 err = mlx5_core_modify_tir(mdev, res->rss[tt].indir_tir.tirn, in);
2481                 if (err)
2482                         goto free_in;
2483
2484                 /* Verify inner tirs resources allocated */
2485                 if (!res->rss[0].inner_indir_tir.tirn)
2486                         continue;
2487
2488                 err = mlx5_core_modify_tir(mdev, res->rss[tt].inner_indir_tir.tirn, in);
2489                 if (err)
2490                         goto free_in;
2491         }
2492
2493         for (ix = 0; ix < priv->max_nch; ix++) {
2494                 err = mlx5_core_modify_tir(mdev, res->channels[ix].direct_tir.tirn, in);
2495                 if (err)
2496                         goto free_in;
2497         }
2498
2499 free_in:
2500         kvfree(in);
2501
2502         return err;
2503 }
2504
2505 static MLX5E_DEFINE_PREACTIVATE_WRAPPER_CTX(mlx5e_modify_tirs_lro);
2506
2507 static int mlx5e_set_mtu(struct mlx5_core_dev *mdev,
2508                          struct mlx5e_params *params, u16 mtu)
2509 {
2510         u16 hw_mtu = MLX5E_SW2HW_MTU(params, mtu);
2511         int err;
2512
2513         err = mlx5_set_port_mtu(mdev, hw_mtu, 1);
2514         if (err)
2515                 return err;
2516
2517         /* Update vport context MTU */
2518         mlx5_modify_nic_vport_mtu(mdev, hw_mtu);
2519         return 0;
2520 }
2521
2522 static void mlx5e_query_mtu(struct mlx5_core_dev *mdev,
2523                             struct mlx5e_params *params, u16 *mtu)
2524 {
2525         u16 hw_mtu = 0;
2526         int err;
2527
2528         err = mlx5_query_nic_vport_mtu(mdev, &hw_mtu);
2529         if (err || !hw_mtu) /* fallback to port oper mtu */
2530                 mlx5_query_port_oper_mtu(mdev, &hw_mtu, 1);
2531
2532         *mtu = MLX5E_HW2SW_MTU(params, hw_mtu);
2533 }
2534
2535 int mlx5e_set_dev_port_mtu(struct mlx5e_priv *priv)
2536 {
2537         struct mlx5e_params *params = &priv->channels.params;
2538         struct net_device *netdev = priv->netdev;
2539         struct mlx5_core_dev *mdev = priv->mdev;
2540         u16 mtu;
2541         int err;
2542
2543         err = mlx5e_set_mtu(mdev, params, params->sw_mtu);
2544         if (err)
2545                 return err;
2546
2547         mlx5e_query_mtu(mdev, params, &mtu);
2548         if (mtu != params->sw_mtu)
2549                 netdev_warn(netdev, "%s: VPort MTU %d is different than netdev mtu %d\n",
2550                             __func__, mtu, params->sw_mtu);
2551
2552         params->sw_mtu = mtu;
2553         return 0;
2554 }
2555
2556 MLX5E_DEFINE_PREACTIVATE_WRAPPER_CTX(mlx5e_set_dev_port_mtu);
2557
2558 void mlx5e_set_netdev_mtu_boundaries(struct mlx5e_priv *priv)
2559 {
2560         struct mlx5e_params *params = &priv->channels.params;
2561         struct net_device *netdev   = priv->netdev;
2562         struct mlx5_core_dev *mdev  = priv->mdev;
2563         u16 max_mtu;
2564
2565         /* MTU range: 68 - hw-specific max */
2566         netdev->min_mtu = ETH_MIN_MTU;
2567
2568         mlx5_query_port_max_mtu(mdev, &max_mtu, 1);
2569         netdev->max_mtu = min_t(unsigned int, MLX5E_HW2SW_MTU(params, max_mtu),
2570                                 ETH_MAX_MTU);
2571 }
2572
2573 static void mlx5e_netdev_set_tcs(struct net_device *netdev, u16 nch, u8 ntc)
2574 {
2575         int tc;
2576
2577         netdev_reset_tc(netdev);
2578
2579         if (ntc == 1)
2580                 return;
2581
2582         netdev_set_num_tc(netdev, ntc);
2583
2584         /* Map netdev TCs to offset 0
2585          * We have our own UP to TXQ mapping for QoS
2586          */
2587         for (tc = 0; tc < ntc; tc++)
2588                 netdev_set_tc_queue(netdev, tc, nch, 0);
2589 }
2590
2591 int mlx5e_update_tx_netdev_queues(struct mlx5e_priv *priv)
2592 {
2593         int qos_queues, nch, ntc, num_txqs, err;
2594
2595         qos_queues = mlx5e_qos_cur_leaf_nodes(priv);
2596
2597         nch = priv->channels.params.num_channels;
2598         ntc = priv->channels.params.num_tc;
2599         num_txqs = nch * ntc + qos_queues;
2600         if (MLX5E_GET_PFLAG(&priv->channels.params, MLX5E_PFLAG_TX_PORT_TS))
2601                 num_txqs += ntc;
2602
2603         mlx5e_dbg(DRV, priv, "Setting num_txqs %d\n", num_txqs);
2604         err = netif_set_real_num_tx_queues(priv->netdev, num_txqs);
2605         if (err)
2606                 netdev_warn(priv->netdev, "netif_set_real_num_tx_queues failed, %d\n", err);
2607
2608         return err;
2609 }
2610
2611 static int mlx5e_update_netdev_queues(struct mlx5e_priv *priv)
2612 {
2613         struct net_device *netdev = priv->netdev;
2614         int old_num_txqs, old_ntc;
2615         int num_rxqs, nch, ntc;
2616         int err;
2617
2618         old_num_txqs = netdev->real_num_tx_queues;
2619         old_ntc = netdev->num_tc ? : 1;
2620
2621         nch = priv->channels.params.num_channels;
2622         ntc = priv->channels.params.num_tc;
2623         num_rxqs = nch * priv->profile->rq_groups;
2624
2625         mlx5e_netdev_set_tcs(netdev, nch, ntc);
2626
2627         err = mlx5e_update_tx_netdev_queues(priv);
2628         if (err)
2629                 goto err_tcs;
2630         err = netif_set_real_num_rx_queues(netdev, num_rxqs);
2631         if (err) {
2632                 netdev_warn(netdev, "netif_set_real_num_rx_queues failed, %d\n", err);
2633                 goto err_txqs;
2634         }
2635
2636         return 0;
2637
2638 err_txqs:
2639         /* netif_set_real_num_rx_queues could fail only when nch increased. Only
2640          * one of nch and ntc is changed in this function. That means, the call
2641          * to netif_set_real_num_tx_queues below should not fail, because it
2642          * decreases the number of TX queues.
2643          */
2644         WARN_ON_ONCE(netif_set_real_num_tx_queues(netdev, old_num_txqs));
2645
2646 err_tcs:
2647         mlx5e_netdev_set_tcs(netdev, old_num_txqs / old_ntc, old_ntc);
2648         return err;
2649 }
2650
2651 static void mlx5e_set_default_xps_cpumasks(struct mlx5e_priv *priv,
2652                                            struct mlx5e_params *params)
2653 {
2654         struct mlx5_core_dev *mdev = priv->mdev;
2655         int num_comp_vectors, ix, irq;
2656
2657         num_comp_vectors = mlx5_comp_vectors_count(mdev);
2658
2659         for (ix = 0; ix < params->num_channels; ix++) {
2660                 cpumask_clear(priv->scratchpad.cpumask);
2661
2662                 for (irq = ix; irq < num_comp_vectors; irq += params->num_channels) {
2663                         int cpu = cpumask_first(mlx5_comp_irq_get_affinity_mask(mdev, irq));
2664
2665                         cpumask_set_cpu(cpu, priv->scratchpad.cpumask);
2666                 }
2667
2668                 netif_set_xps_queue(priv->netdev, priv->scratchpad.cpumask, ix);
2669         }
2670 }
2671
2672 int mlx5e_num_channels_changed(struct mlx5e_priv *priv)
2673 {
2674         u16 count = priv->channels.params.num_channels;
2675         int err;
2676
2677         err = mlx5e_update_netdev_queues(priv);
2678         if (err)
2679                 return err;
2680
2681         mlx5e_set_default_xps_cpumasks(priv, &priv->channels.params);
2682
2683         /* This function may be called on attach, before priv->rx_res is created. */
2684         if (!netif_is_rxfh_configured(priv->netdev) && priv->rx_res)
2685                 mlx5e_build_default_indir_rqt(priv->rx_res->rss_params.indir.table,
2686                                               MLX5E_INDIR_RQT_SIZE, count);
2687
2688         return 0;
2689 }
2690
2691 MLX5E_DEFINE_PREACTIVATE_WRAPPER_CTX(mlx5e_num_channels_changed);
2692
2693 static void mlx5e_build_txq_maps(struct mlx5e_priv *priv)
2694 {
2695         int i, ch, tc, num_tc;
2696
2697         ch = priv->channels.num;
2698         num_tc = priv->channels.params.num_tc;
2699
2700         for (i = 0; i < ch; i++) {
2701                 for (tc = 0; tc < num_tc; tc++) {
2702                         struct mlx5e_channel *c = priv->channels.c[i];
2703                         struct mlx5e_txqsq *sq = &c->sq[tc];
2704
2705                         priv->txq2sq[sq->txq_ix] = sq;
2706                         priv->channel_tc2realtxq[i][tc] = i + tc * ch;
2707                 }
2708         }
2709
2710         if (!priv->channels.ptp)
2711                 return;
2712
2713         if (!test_bit(MLX5E_PTP_STATE_TX, priv->channels.ptp->state))
2714                 return;
2715
2716         for (tc = 0; tc < num_tc; tc++) {
2717                 struct mlx5e_ptp *c = priv->channels.ptp;
2718                 struct mlx5e_txqsq *sq = &c->ptpsq[tc].txqsq;
2719
2720                 priv->txq2sq[sq->txq_ix] = sq;
2721                 priv->port_ptp_tc2realtxq[tc] = priv->num_tc_x_num_ch + tc;
2722         }
2723 }
2724
2725 static void mlx5e_update_num_tc_x_num_ch(struct mlx5e_priv *priv)
2726 {
2727         /* Sync with mlx5e_select_queue. */
2728         WRITE_ONCE(priv->num_tc_x_num_ch,
2729                    priv->channels.params.num_tc * priv->channels.num);
2730 }
2731
2732 void mlx5e_activate_priv_channels(struct mlx5e_priv *priv)
2733 {
2734         mlx5e_update_num_tc_x_num_ch(priv);
2735         mlx5e_build_txq_maps(priv);
2736         mlx5e_activate_channels(&priv->channels);
2737         mlx5e_qos_activate_queues(priv);
2738         mlx5e_xdp_tx_enable(priv);
2739         netif_tx_start_all_queues(priv->netdev);
2740
2741         if (mlx5e_is_vport_rep(priv))
2742                 mlx5e_add_sqs_fwd_rules(priv);
2743
2744         mlx5e_wait_channels_min_rx_wqes(&priv->channels);
2745
2746         if (priv->rx_res) {
2747                 mlx5e_redirect_rqts_to_channels(priv, &priv->channels);
2748                 mlx5e_xsk_redirect_rqts_to_channels(priv, &priv->channels);
2749         }
2750 }
2751
2752 void mlx5e_deactivate_priv_channels(struct mlx5e_priv *priv)
2753 {
2754         if (priv->rx_res) {
2755                 mlx5e_xsk_redirect_rqts_to_drop(priv, &priv->channels);
2756                 mlx5e_redirect_rqts_to_drop(priv);
2757         }
2758
2759         if (mlx5e_is_vport_rep(priv))
2760                 mlx5e_remove_sqs_fwd_rules(priv);
2761
2762         /* FIXME: This is a W/A only for tx timeout watch dog false alarm when
2763          * polling for inactive tx queues.
2764          */
2765         netif_tx_stop_all_queues(priv->netdev);
2766         netif_tx_disable(priv->netdev);
2767         mlx5e_xdp_tx_disable(priv);
2768         mlx5e_deactivate_channels(&priv->channels);
2769 }
2770
2771 static int mlx5e_switch_priv_params(struct mlx5e_priv *priv,
2772                                     struct mlx5e_params *new_params,
2773                                     mlx5e_fp_preactivate preactivate,
2774                                     void *context)
2775 {
2776         struct mlx5e_params old_params;
2777
2778         old_params = priv->channels.params;
2779         priv->channels.params = *new_params;
2780
2781         if (preactivate) {
2782                 int err;
2783
2784                 err = preactivate(priv, context);
2785                 if (err) {
2786                         priv->channels.params = old_params;
2787                         return err;
2788                 }
2789         }
2790
2791         return 0;
2792 }
2793
2794 static int mlx5e_switch_priv_channels(struct mlx5e_priv *priv,
2795                                       struct mlx5e_channels *new_chs,
2796                                       mlx5e_fp_preactivate preactivate,
2797                                       void *context)
2798 {
2799         struct net_device *netdev = priv->netdev;
2800         struct mlx5e_channels old_chs;
2801         int carrier_ok;
2802         int err = 0;
2803
2804         carrier_ok = netif_carrier_ok(netdev);
2805         netif_carrier_off(netdev);
2806
2807         mlx5e_deactivate_priv_channels(priv);
2808
2809         old_chs = priv->channels;
2810         priv->channels = *new_chs;
2811
2812         /* New channels are ready to roll, call the preactivate hook if needed
2813          * to modify HW settings or update kernel parameters.
2814          */
2815         if (preactivate) {
2816                 err = preactivate(priv, context);
2817                 if (err) {
2818                         priv->channels = old_chs;
2819                         goto out;
2820                 }
2821         }
2822
2823         mlx5e_close_channels(&old_chs);
2824         priv->profile->update_rx(priv);
2825
2826 out:
2827         mlx5e_activate_priv_channels(priv);
2828
2829         /* return carrier back if needed */
2830         if (carrier_ok)
2831                 netif_carrier_on(netdev);
2832
2833         return err;
2834 }
2835
2836 int mlx5e_safe_switch_params(struct mlx5e_priv *priv,
2837                              struct mlx5e_params *params,
2838                              mlx5e_fp_preactivate preactivate,
2839                              void *context, bool reset)
2840 {
2841         struct mlx5e_channels new_chs = {};
2842         int err;
2843
2844         reset &= test_bit(MLX5E_STATE_OPENED, &priv->state);
2845         if (!reset)
2846                 return mlx5e_switch_priv_params(priv, params, preactivate, context);
2847
2848         new_chs.params = *params;
2849         err = mlx5e_open_channels(priv, &new_chs);
2850         if (err)
2851                 return err;
2852         err = mlx5e_switch_priv_channels(priv, &new_chs, preactivate, context);
2853         if (err)
2854                 mlx5e_close_channels(&new_chs);
2855
2856         return err;
2857 }
2858
2859 int mlx5e_safe_reopen_channels(struct mlx5e_priv *priv)
2860 {
2861         return mlx5e_safe_switch_params(priv, &priv->channels.params, NULL, NULL, true);
2862 }
2863
2864 void mlx5e_timestamp_init(struct mlx5e_priv *priv)
2865 {
2866         priv->tstamp.tx_type   = HWTSTAMP_TX_OFF;
2867         priv->tstamp.rx_filter = HWTSTAMP_FILTER_NONE;
2868 }
2869
2870 static void mlx5e_modify_admin_state(struct mlx5_core_dev *mdev,
2871                                      enum mlx5_port_status state)
2872 {
2873         struct mlx5_eswitch *esw = mdev->priv.eswitch;
2874         int vport_admin_state;
2875
2876         mlx5_set_port_admin_status(mdev, state);
2877
2878         if (mlx5_eswitch_mode(mdev) == MLX5_ESWITCH_OFFLOADS ||
2879             !MLX5_CAP_GEN(mdev, uplink_follow))
2880                 return;
2881
2882         if (state == MLX5_PORT_UP)
2883                 vport_admin_state = MLX5_VPORT_ADMIN_STATE_AUTO;
2884         else
2885                 vport_admin_state = MLX5_VPORT_ADMIN_STATE_DOWN;
2886
2887         mlx5_eswitch_set_vport_state(esw, MLX5_VPORT_UPLINK, vport_admin_state);
2888 }
2889
2890 int mlx5e_open_locked(struct net_device *netdev)
2891 {
2892         struct mlx5e_priv *priv = netdev_priv(netdev);
2893         int err;
2894
2895         set_bit(MLX5E_STATE_OPENED, &priv->state);
2896
2897         err = mlx5e_open_channels(priv, &priv->channels);
2898         if (err)
2899                 goto err_clear_state_opened_flag;
2900
2901         priv->profile->update_rx(priv);
2902         mlx5e_activate_priv_channels(priv);
2903         mlx5e_apply_traps(priv, true);
2904         if (priv->profile->update_carrier)
2905                 priv->profile->update_carrier(priv);
2906
2907         mlx5e_queue_update_stats(priv);
2908         return 0;
2909
2910 err_clear_state_opened_flag:
2911         clear_bit(MLX5E_STATE_OPENED, &priv->state);
2912         return err;
2913 }
2914
2915 int mlx5e_open(struct net_device *netdev)
2916 {
2917         struct mlx5e_priv *priv = netdev_priv(netdev);
2918         int err;
2919
2920         mutex_lock(&priv->state_lock);
2921         err = mlx5e_open_locked(netdev);
2922         if (!err)
2923                 mlx5e_modify_admin_state(priv->mdev, MLX5_PORT_UP);
2924         mutex_unlock(&priv->state_lock);
2925
2926         return err;
2927 }
2928
2929 int mlx5e_close_locked(struct net_device *netdev)
2930 {
2931         struct mlx5e_priv *priv = netdev_priv(netdev);
2932
2933         /* May already be CLOSED in case a previous configuration operation
2934          * (e.g RX/TX queue size change) that involves close&open failed.
2935          */
2936         if (!test_bit(MLX5E_STATE_OPENED, &priv->state))
2937                 return 0;
2938
2939         mlx5e_apply_traps(priv, false);
2940         clear_bit(MLX5E_STATE_OPENED, &priv->state);
2941
2942         netif_carrier_off(priv->netdev);
2943         mlx5e_deactivate_priv_channels(priv);
2944         mlx5e_close_channels(&priv->channels);
2945
2946         return 0;
2947 }
2948
2949 int mlx5e_close(struct net_device *netdev)
2950 {
2951         struct mlx5e_priv *priv = netdev_priv(netdev);
2952         int err;
2953
2954         if (!netif_device_present(netdev))
2955                 return -ENODEV;
2956
2957         mutex_lock(&priv->state_lock);
2958         mlx5e_modify_admin_state(priv->mdev, MLX5_PORT_DOWN);
2959         err = mlx5e_close_locked(netdev);
2960         mutex_unlock(&priv->state_lock);
2961
2962         return err;
2963 }
2964
2965 static void mlx5e_free_drop_rq(struct mlx5e_rq *rq)
2966 {
2967         mlx5_wq_destroy(&rq->wq_ctrl);
2968 }
2969
2970 static int mlx5e_alloc_drop_rq(struct mlx5_core_dev *mdev,
2971                                struct mlx5e_rq *rq,
2972                                struct mlx5e_rq_param *param)
2973 {
2974         void *rqc = param->rqc;
2975         void *rqc_wq = MLX5_ADDR_OF(rqc, rqc, wq);
2976         int err;
2977
2978         param->wq.db_numa_node = param->wq.buf_numa_node;
2979
2980         err = mlx5_wq_cyc_create(mdev, &param->wq, rqc_wq, &rq->wqe.wq,
2981                                  &rq->wq_ctrl);
2982         if (err)
2983                 return err;
2984
2985         /* Mark as unused given "Drop-RQ" packets never reach XDP */
2986         xdp_rxq_info_unused(&rq->xdp_rxq);
2987
2988         rq->mdev = mdev;
2989
2990         return 0;
2991 }
2992
2993 static int mlx5e_alloc_drop_cq(struct mlx5e_priv *priv,
2994                                struct mlx5e_cq *cq,
2995                                struct mlx5e_cq_param *param)
2996 {
2997         struct mlx5_core_dev *mdev = priv->mdev;
2998
2999         param->wq.buf_numa_node = dev_to_node(mlx5_core_dma_dev(mdev));
3000         param->wq.db_numa_node  = dev_to_node(mlx5_core_dma_dev(mdev));
3001
3002         return mlx5e_alloc_cq_common(priv, param, cq);
3003 }
3004
3005 int mlx5e_open_drop_rq(struct mlx5e_priv *priv,
3006                        struct mlx5e_rq *drop_rq)
3007 {
3008         struct mlx5_core_dev *mdev = priv->mdev;
3009         struct mlx5e_cq_param cq_param = {};
3010         struct mlx5e_rq_param rq_param = {};
3011         struct mlx5e_cq *cq = &drop_rq->cq;
3012         int err;
3013
3014         mlx5e_build_drop_rq_param(mdev, priv->drop_rq_q_counter, &rq_param);
3015
3016         err = mlx5e_alloc_drop_cq(priv, cq, &cq_param);
3017         if (err)
3018                 return err;
3019
3020         err = mlx5e_create_cq(cq, &cq_param);
3021         if (err)
3022                 goto err_free_cq;
3023
3024         err = mlx5e_alloc_drop_rq(mdev, drop_rq, &rq_param);
3025         if (err)
3026                 goto err_destroy_cq;
3027
3028         err = mlx5e_create_rq(drop_rq, &rq_param);
3029         if (err)
3030                 goto err_free_rq;
3031
3032         err = mlx5e_modify_rq_state(drop_rq, MLX5_RQC_STATE_RST, MLX5_RQC_STATE_RDY);
3033         if (err)
3034                 mlx5_core_warn(priv->mdev, "modify_rq_state failed, rx_if_down_packets won't be counted %d\n", err);
3035
3036         return 0;
3037
3038 err_free_rq:
3039         mlx5e_free_drop_rq(drop_rq);
3040
3041 err_destroy_cq:
3042         mlx5e_destroy_cq(cq);
3043
3044 err_free_cq:
3045         mlx5e_free_cq(cq);
3046
3047         return err;
3048 }
3049
3050 void mlx5e_close_drop_rq(struct mlx5e_rq *drop_rq)
3051 {
3052         mlx5e_destroy_rq(drop_rq);
3053         mlx5e_free_drop_rq(drop_rq);
3054         mlx5e_destroy_cq(&drop_rq->cq);
3055         mlx5e_free_cq(&drop_rq->cq);
3056 }
3057
3058 int mlx5e_create_tis(struct mlx5_core_dev *mdev, void *in, u32 *tisn)
3059 {
3060         void *tisc = MLX5_ADDR_OF(create_tis_in, in, ctx);
3061
3062         MLX5_SET(tisc, tisc, transport_domain, mdev->mlx5e_res.hw_objs.td.tdn);
3063
3064         if (MLX5_GET(tisc, tisc, tls_en))
3065                 MLX5_SET(tisc, tisc, pd, mdev->mlx5e_res.hw_objs.pdn);
3066
3067         if (mlx5_lag_is_lacp_owner(mdev))
3068                 MLX5_SET(tisc, tisc, strict_lag_tx_port_affinity, 1);
3069
3070         return mlx5_core_create_tis(mdev, in, tisn);
3071 }
3072
3073 void mlx5e_destroy_tis(struct mlx5_core_dev *mdev, u32 tisn)
3074 {
3075         mlx5_core_destroy_tis(mdev, tisn);
3076 }
3077
3078 void mlx5e_destroy_tises(struct mlx5e_priv *priv)
3079 {
3080         int tc, i;
3081
3082         for (i = 0; i < mlx5e_get_num_lag_ports(priv->mdev); i++)
3083                 for (tc = 0; tc < priv->profile->max_tc; tc++)
3084                         mlx5e_destroy_tis(priv->mdev, priv->tisn[i][tc]);
3085 }
3086
3087 static bool mlx5e_lag_should_assign_affinity(struct mlx5_core_dev *mdev)
3088 {
3089         return MLX5_CAP_GEN(mdev, lag_tx_port_affinity) && mlx5e_get_num_lag_ports(mdev) > 1;
3090 }
3091
3092 int mlx5e_create_tises(struct mlx5e_priv *priv)
3093 {
3094         int tc, i;
3095         int err;
3096
3097         for (i = 0; i < mlx5e_get_num_lag_ports(priv->mdev); i++) {
3098                 for (tc = 0; tc < priv->profile->max_tc; tc++) {
3099                         u32 in[MLX5_ST_SZ_DW(create_tis_in)] = {};
3100                         void *tisc;
3101
3102                         tisc = MLX5_ADDR_OF(create_tis_in, in, ctx);
3103
3104                         MLX5_SET(tisc, tisc, prio, tc << 1);
3105
3106                         if (mlx5e_lag_should_assign_affinity(priv->mdev))
3107                                 MLX5_SET(tisc, tisc, lag_tx_port_affinity, i + 1);
3108
3109                         err = mlx5e_create_tis(priv->mdev, in, &priv->tisn[i][tc]);
3110                         if (err)
3111                                 goto err_close_tises;
3112                 }
3113         }
3114
3115         return 0;
3116
3117 err_close_tises:
3118         for (; i >= 0; i--) {
3119                 for (tc--; tc >= 0; tc--)
3120                         mlx5e_destroy_tis(priv->mdev, priv->tisn[i][tc]);
3121                 tc = priv->profile->max_tc;
3122         }
3123
3124         return err;
3125 }
3126
3127 static void mlx5e_cleanup_nic_tx(struct mlx5e_priv *priv)
3128 {
3129         mlx5e_destroy_tises(priv);
3130 }
3131
3132 static void mlx5e_build_indir_tir_ctx_common(u32 tdn, bool inner_ft_support,
3133                                              u32 rqtn, u32 *tirc)
3134 {
3135         MLX5_SET(tirc, tirc, transport_domain, tdn);
3136         MLX5_SET(tirc, tirc, disp_type, MLX5_TIRC_DISP_TYPE_INDIRECT);
3137         MLX5_SET(tirc, tirc, indirect_table, rqtn);
3138         MLX5_SET(tirc, tirc, tunneled_offload_en, inner_ft_support);
3139 }
3140
3141 static void mlx5e_build_direct_tir_ctx(struct mlx5e_lro_param *lro_param,
3142                                        u32 tdn, bool inner_ft_support,
3143                                        u32 rqtn, u32 *tirc)
3144 {
3145         mlx5e_build_indir_tir_ctx_common(tdn, inner_ft_support, rqtn, tirc);
3146         mlx5e_build_tir_ctx_lro(lro_param, tirc);
3147         MLX5_SET(tirc, tirc, rx_hash_fn, MLX5_RX_HASH_FN_INVERTED_XOR8);
3148 }
3149
3150 int mlx5e_create_indirect_tirs(struct mlx5e_priv *priv, bool inner_ttc)
3151 {
3152         struct mlx5e_rx_res *res = priv->rx_res;
3153         struct mlx5e_lro_param lro_param;
3154         struct mlx5e_tir *tir;
3155         u32 indir_rqtn;
3156         void *tirc;
3157         int inlen;
3158         int i = 0;
3159         int err;
3160         u32 *in;
3161         int tt;
3162
3163         inlen = MLX5_ST_SZ_BYTES(create_tir_in);
3164         in = kvzalloc(inlen, GFP_KERNEL);
3165         if (!in)
3166                 return -ENOMEM;
3167
3168         lro_param = mlx5e_get_lro_param(&priv->channels.params);
3169         indir_rqtn = mlx5e_rqt_get_rqtn(&priv->rx_res->indir_rqt);
3170
3171         for (tt = 0; tt < MLX5E_NUM_INDIR_TIRS; tt++) {
3172                 memset(in, 0, inlen);
3173                 tir = &res->rss[tt].indir_tir;
3174                 tirc = MLX5_ADDR_OF(create_tir_in, in, ctx);
3175                 mlx5e_build_indir_tir_ctx_common(priv->mdev->mlx5e_res.hw_objs.td.tdn,
3176                                                  priv->channels.params.tunneled_offload_en,
3177                                                  indir_rqtn, tirc);
3178                 mlx5e_build_tir_ctx_lro(&lro_param, tirc);
3179                 mlx5e_build_indir_tir_ctx_hash(&priv->rx_res->rss_params,
3180                                                &tirc_default_config[tt], tirc, false);
3181
3182                 err = mlx5e_create_tir(priv->mdev, tir, in);
3183                 if (err) {
3184                         mlx5_core_warn(priv->mdev, "create indirect tirs failed, %d\n", err);
3185                         goto err_destroy_inner_tirs;
3186                 }
3187         }
3188
3189         if (!inner_ttc || !mlx5e_tunnel_inner_ft_supported(priv->mdev))
3190                 goto out;
3191
3192         for (i = 0; i < MLX5E_NUM_INDIR_TIRS; i++) {
3193                 memset(in, 0, inlen);
3194                 tir = &res->rss[i].inner_indir_tir;
3195                 tirc = MLX5_ADDR_OF(create_tir_in, in, ctx);
3196                 mlx5e_build_indir_tir_ctx_common(priv->mdev->mlx5e_res.hw_objs.td.tdn,
3197                                                  priv->channels.params.tunneled_offload_en,
3198                                                  indir_rqtn, tirc);
3199                 mlx5e_build_tir_ctx_lro(&lro_param, tirc);
3200                 mlx5e_build_indir_tir_ctx_hash(&priv->rx_res->rss_params,
3201                                                &tirc_default_config[i], tirc, true);
3202                 err = mlx5e_create_tir(priv->mdev, tir, in);
3203                 if (err) {
3204                         mlx5_core_warn(priv->mdev, "create inner indirect tirs failed, %d\n", err);
3205                         goto err_destroy_inner_tirs;
3206                 }
3207         }
3208
3209 out:
3210         kvfree(in);
3211
3212         return 0;
3213
3214 err_destroy_inner_tirs:
3215         for (i--; i >= 0; i--)
3216                 mlx5e_destroy_tir(priv->mdev, &res->rss[i].inner_indir_tir);
3217
3218         for (tt--; tt >= 0; tt--)
3219                 mlx5e_destroy_tir(priv->mdev, &res->rss[tt].indir_tir);
3220
3221         kvfree(in);
3222
3223         return err;
3224 }
3225
3226 static int mlx5e_create_direct_tir(struct mlx5e_priv *priv, struct mlx5e_tir *tir,
3227                                    struct mlx5e_rqt *rqt)
3228 {
3229         struct mlx5e_lro_param lro_param;
3230         void *tirc;
3231         int inlen;
3232         int err = 0;
3233         u32 *in;
3234
3235         inlen = MLX5_ST_SZ_BYTES(create_tir_in);
3236         in = kvzalloc(inlen, GFP_KERNEL);
3237         if (!in)
3238                 return -ENOMEM;
3239
3240         tirc = MLX5_ADDR_OF(create_tir_in, in, ctx);
3241         lro_param = mlx5e_get_lro_param(&priv->channels.params);
3242         mlx5e_build_direct_tir_ctx(&lro_param,
3243                                    priv->mdev->mlx5e_res.hw_objs.td.tdn,
3244                                    priv->channels.params.tunneled_offload_en,
3245                                    mlx5e_rqt_get_rqtn(rqt), tirc);
3246         err = mlx5e_create_tir(priv->mdev, tir, in);
3247         if (unlikely(err))
3248                 mlx5_core_warn(priv->mdev, "create tirs failed, %d\n", err);
3249
3250         kvfree(in);
3251
3252         return err;
3253 }
3254
3255 int mlx5e_create_direct_tirs(struct mlx5e_priv *priv)
3256 {
3257         int err;
3258         int ix;
3259
3260         for (ix = 0; ix < priv->max_nch; ix++) {
3261                 err = mlx5e_create_direct_tir(priv, &priv->rx_res->channels[ix].direct_tir,
3262                                               &priv->rx_res->channels[ix].direct_rqt);
3263                 if (err)
3264                         goto err_destroy_tirs;
3265         }
3266
3267         return 0;
3268
3269 err_destroy_tirs:
3270         while (--ix >= 0)
3271                 mlx5e_destroy_tir(priv->mdev, &priv->rx_res->channels[ix].direct_tir);
3272
3273         return err;
3274 }
3275
3276 static int mlx5e_create_xsk_tirs(struct mlx5e_priv *priv)
3277 {
3278         int err;
3279         int ix;
3280
3281         for (ix = 0; ix < priv->max_nch; ix++) {
3282                 err = mlx5e_create_direct_tir(priv, &priv->rx_res->channels[ix].xsk_tir,
3283                                               &priv->rx_res->channels[ix].xsk_rqt);
3284                 if (err)
3285                         goto err_destroy_tirs;
3286         }
3287
3288         return 0;
3289
3290 err_destroy_tirs:
3291         while (--ix >= 0)
3292                 mlx5e_destroy_tir(priv->mdev, &priv->rx_res->channels[ix].xsk_tir);
3293
3294         return err;
3295 }
3296
3297 void mlx5e_destroy_indirect_tirs(struct mlx5e_priv *priv)
3298 {
3299         struct mlx5e_rx_res *res = priv->rx_res;
3300         int i;
3301
3302         for (i = 0; i < MLX5E_NUM_INDIR_TIRS; i++)
3303                 mlx5e_destroy_tir(priv->mdev, &res->rss[i].indir_tir);
3304
3305         /* Verify inner tirs resources allocated */
3306         if (!res->rss[0].inner_indir_tir.tirn)
3307                 return;
3308
3309         for (i = 0; i < MLX5E_NUM_INDIR_TIRS; i++)
3310                 mlx5e_destroy_tir(priv->mdev, &res->rss[i].inner_indir_tir);
3311 }
3312
3313 void mlx5e_destroy_direct_tirs(struct mlx5e_priv *priv)
3314 {
3315         unsigned int ix;
3316
3317         for (ix = 0; ix < priv->max_nch; ix++)
3318                 mlx5e_destroy_tir(priv->mdev, &priv->rx_res->channels[ix].direct_tir);
3319 }
3320
3321 static void mlx5e_destroy_xsk_tirs(struct mlx5e_priv *priv)
3322 {
3323         unsigned int ix;
3324
3325         for (ix = 0; ix < priv->max_nch; ix++)
3326                 mlx5e_destroy_tir(priv->mdev, &priv->rx_res->channels[ix].xsk_tir);
3327 }
3328
3329 static int mlx5e_modify_channels_scatter_fcs(struct mlx5e_channels *chs, bool enable)
3330 {
3331         int err = 0;
3332         int i;
3333
3334         for (i = 0; i < chs->num; i++) {
3335                 err = mlx5e_modify_rq_scatter_fcs(&chs->c[i]->rq, enable);
3336                 if (err)
3337                         return err;
3338         }
3339
3340         return 0;
3341 }
3342
3343 static int mlx5e_modify_channels_vsd(struct mlx5e_channels *chs, bool vsd)
3344 {
3345         int err = 0;
3346         int i;
3347
3348         for (i = 0; i < chs->num; i++) {
3349                 err = mlx5e_modify_rq_vsd(&chs->c[i]->rq, vsd);
3350                 if (err)
3351                         return err;
3352         }
3353
3354         return 0;
3355 }
3356
3357 static int mlx5e_setup_tc_mqprio(struct mlx5e_priv *priv,
3358                                  struct tc_mqprio_qopt *mqprio)
3359 {
3360         struct mlx5e_params new_params;
3361         u8 tc = mqprio->num_tc;
3362         int err = 0;
3363
3364         mqprio->hw = TC_MQPRIO_HW_OFFLOAD_TCS;
3365
3366         if (tc && tc != MLX5E_MAX_NUM_TC)
3367                 return -EINVAL;
3368
3369         mutex_lock(&priv->state_lock);
3370
3371         /* MQPRIO is another toplevel qdisc that can't be attached
3372          * simultaneously with the offloaded HTB.
3373          */
3374         if (WARN_ON(priv->htb.maj_id)) {
3375                 err = -EINVAL;
3376                 goto out;
3377         }
3378
3379         new_params = priv->channels.params;
3380         new_params.num_tc = tc ? tc : 1;
3381
3382         err = mlx5e_safe_switch_params(priv, &new_params,
3383                                        mlx5e_num_channels_changed_ctx, NULL, true);
3384
3385 out:
3386         priv->max_opened_tc = max_t(u8, priv->max_opened_tc,
3387                                     priv->channels.params.num_tc);
3388         mutex_unlock(&priv->state_lock);
3389         return err;
3390 }
3391
3392 static int mlx5e_setup_tc_htb(struct mlx5e_priv *priv, struct tc_htb_qopt_offload *htb)
3393 {
3394         int res;
3395
3396         switch (htb->command) {
3397         case TC_HTB_CREATE:
3398                 return mlx5e_htb_root_add(priv, htb->parent_classid, htb->classid,
3399                                           htb->extack);
3400         case TC_HTB_DESTROY:
3401                 return mlx5e_htb_root_del(priv);
3402         case TC_HTB_LEAF_ALLOC_QUEUE:
3403                 res = mlx5e_htb_leaf_alloc_queue(priv, htb->classid, htb->parent_classid,
3404                                                  htb->rate, htb->ceil, htb->extack);
3405                 if (res < 0)
3406                         return res;
3407                 htb->qid = res;
3408                 return 0;
3409         case TC_HTB_LEAF_TO_INNER:
3410                 return mlx5e_htb_leaf_to_inner(priv, htb->parent_classid, htb->classid,
3411                                                htb->rate, htb->ceil, htb->extack);
3412         case TC_HTB_LEAF_DEL:
3413                 return mlx5e_htb_leaf_del(priv, htb->classid, &htb->moved_qid, &htb->qid,
3414                                           htb->extack);
3415         case TC_HTB_LEAF_DEL_LAST:
3416         case TC_HTB_LEAF_DEL_LAST_FORCE:
3417                 return mlx5e_htb_leaf_del_last(priv, htb->classid,
3418                                                htb->command == TC_HTB_LEAF_DEL_LAST_FORCE,
3419                                                htb->extack);
3420         case TC_HTB_NODE_MODIFY:
3421                 return mlx5e_htb_node_modify(priv, htb->classid, htb->rate, htb->ceil,
3422                                              htb->extack);
3423         case TC_HTB_LEAF_QUERY_QUEUE:
3424                 res = mlx5e_get_txq_by_classid(priv, htb->classid);
3425                 if (res < 0)
3426                         return res;
3427                 htb->qid = res;
3428                 return 0;
3429         default:
3430                 return -EOPNOTSUPP;
3431         }
3432 }
3433
3434 static LIST_HEAD(mlx5e_block_cb_list);
3435
3436 static int mlx5e_setup_tc(struct net_device *dev, enum tc_setup_type type,
3437                           void *type_data)
3438 {
3439         struct mlx5e_priv *priv = netdev_priv(dev);
3440         bool tc_unbind = false;
3441         int err;
3442
3443         if (type == TC_SETUP_BLOCK &&
3444             ((struct flow_block_offload *)type_data)->command == FLOW_BLOCK_UNBIND)
3445                 tc_unbind = true;
3446
3447         if (!netif_device_present(dev) && !tc_unbind)
3448                 return -ENODEV;
3449
3450         switch (type) {
3451         case TC_SETUP_BLOCK: {
3452                 struct flow_block_offload *f = type_data;
3453
3454                 f->unlocked_driver_cb = true;
3455                 return flow_block_cb_setup_simple(type_data,
3456                                                   &mlx5e_block_cb_list,
3457                                                   mlx5e_setup_tc_block_cb,
3458                                                   priv, priv, true);
3459         }
3460         case TC_SETUP_QDISC_MQPRIO:
3461                 return mlx5e_setup_tc_mqprio(priv, type_data);
3462         case TC_SETUP_QDISC_HTB:
3463                 mutex_lock(&priv->state_lock);
3464                 err = mlx5e_setup_tc_htb(priv, type_data);
3465                 mutex_unlock(&priv->state_lock);
3466                 return err;
3467         default:
3468                 return -EOPNOTSUPP;
3469         }
3470 }
3471
3472 void mlx5e_fold_sw_stats64(struct mlx5e_priv *priv, struct rtnl_link_stats64 *s)
3473 {
3474         int i;
3475
3476         for (i = 0; i < priv->max_nch; i++) {
3477                 struct mlx5e_channel_stats *channel_stats = &priv->channel_stats[i];
3478                 struct mlx5e_rq_stats *xskrq_stats = &channel_stats->xskrq;
3479                 struct mlx5e_rq_stats *rq_stats = &channel_stats->rq;
3480                 int j;
3481
3482                 s->rx_packets   += rq_stats->packets + xskrq_stats->packets;
3483                 s->rx_bytes     += rq_stats->bytes + xskrq_stats->bytes;
3484                 s->multicast    += rq_stats->mcast_packets + xskrq_stats->mcast_packets;
3485
3486                 for (j = 0; j < priv->max_opened_tc; j++) {
3487                         struct mlx5e_sq_stats *sq_stats = &channel_stats->sq[j];
3488
3489                         s->tx_packets    += sq_stats->packets;
3490                         s->tx_bytes      += sq_stats->bytes;
3491                         s->tx_dropped    += sq_stats->dropped;
3492                 }
3493         }
3494         if (priv->tx_ptp_opened) {
3495                 for (i = 0; i < priv->max_opened_tc; i++) {
3496                         struct mlx5e_sq_stats *sq_stats = &priv->ptp_stats.sq[i];
3497
3498                         s->tx_packets    += sq_stats->packets;
3499                         s->tx_bytes      += sq_stats->bytes;
3500                         s->tx_dropped    += sq_stats->dropped;
3501                 }
3502         }
3503         if (priv->rx_ptp_opened) {
3504                 struct mlx5e_rq_stats *rq_stats = &priv->ptp_stats.rq;
3505
3506                 s->rx_packets   += rq_stats->packets;
3507                 s->rx_bytes     += rq_stats->bytes;
3508                 s->multicast    += rq_stats->mcast_packets;
3509         }
3510 }
3511
3512 void
3513 mlx5e_get_stats(struct net_device *dev, struct rtnl_link_stats64 *stats)
3514 {
3515         struct mlx5e_priv *priv = netdev_priv(dev);
3516         struct mlx5e_pport_stats *pstats = &priv->stats.pport;
3517
3518         if (!netif_device_present(dev))
3519                 return;
3520
3521         /* In switchdev mode, monitor counters doesn't monitor
3522          * rx/tx stats of 802_3. The update stats mechanism
3523          * should keep the 802_3 layout counters updated
3524          */
3525         if (!mlx5e_monitor_counter_supported(priv) ||
3526             mlx5e_is_uplink_rep(priv)) {
3527                 /* update HW stats in background for next time */
3528                 mlx5e_queue_update_stats(priv);
3529         }
3530
3531         if (mlx5e_is_uplink_rep(priv)) {
3532                 struct mlx5e_vport_stats *vstats = &priv->stats.vport;
3533
3534                 stats->rx_packets = PPORT_802_3_GET(pstats, a_frames_received_ok);
3535                 stats->rx_bytes   = PPORT_802_3_GET(pstats, a_octets_received_ok);
3536                 stats->tx_packets = PPORT_802_3_GET(pstats, a_frames_transmitted_ok);
3537                 stats->tx_bytes   = PPORT_802_3_GET(pstats, a_octets_transmitted_ok);
3538
3539                 /* vport multicast also counts packets that are dropped due to steering
3540                  * or rx out of buffer
3541                  */
3542                 stats->multicast = VPORT_COUNTER_GET(vstats, received_eth_multicast.packets);
3543         } else {
3544                 mlx5e_fold_sw_stats64(priv, stats);
3545         }
3546
3547         stats->rx_dropped = priv->stats.qcnt.rx_out_of_buffer;
3548
3549         stats->rx_length_errors =
3550                 PPORT_802_3_GET(pstats, a_in_range_length_errors) +
3551                 PPORT_802_3_GET(pstats, a_out_of_range_length_field) +
3552                 PPORT_802_3_GET(pstats, a_frame_too_long_errors);
3553         stats->rx_crc_errors =
3554                 PPORT_802_3_GET(pstats, a_frame_check_sequence_errors);
3555         stats->rx_frame_errors = PPORT_802_3_GET(pstats, a_alignment_errors);
3556         stats->tx_aborted_errors = PPORT_2863_GET(pstats, if_out_discards);
3557         stats->rx_errors = stats->rx_length_errors + stats->rx_crc_errors +
3558                            stats->rx_frame_errors;
3559         stats->tx_errors = stats->tx_aborted_errors + stats->tx_carrier_errors;
3560 }
3561
3562 static void mlx5e_nic_set_rx_mode(struct mlx5e_priv *priv)
3563 {
3564         if (mlx5e_is_uplink_rep(priv))
3565                 return; /* no rx mode for uplink rep */
3566
3567         queue_work(priv->wq, &priv->set_rx_mode_work);
3568 }
3569
3570 static void mlx5e_set_rx_mode(struct net_device *dev)
3571 {
3572         struct mlx5e_priv *priv = netdev_priv(dev);
3573
3574         mlx5e_nic_set_rx_mode(priv);
3575 }
3576
3577 static int mlx5e_set_mac(struct net_device *netdev, void *addr)
3578 {
3579         struct mlx5e_priv *priv = netdev_priv(netdev);
3580         struct sockaddr *saddr = addr;
3581
3582         if (!is_valid_ether_addr(saddr->sa_data))
3583                 return -EADDRNOTAVAIL;
3584
3585         netif_addr_lock_bh(netdev);
3586         ether_addr_copy(netdev->dev_addr, saddr->sa_data);
3587         netif_addr_unlock_bh(netdev);
3588
3589         mlx5e_nic_set_rx_mode(priv);
3590
3591         return 0;
3592 }
3593
3594 #define MLX5E_SET_FEATURE(features, feature, enable)    \
3595         do {                                            \
3596                 if (enable)                             \
3597                         *features |= feature;           \
3598                 else                                    \
3599                         *features &= ~feature;          \
3600         } while (0)
3601
3602 typedef int (*mlx5e_feature_handler)(struct net_device *netdev, bool enable);
3603
3604 static int set_feature_lro(struct net_device *netdev, bool enable)
3605 {
3606         struct mlx5e_priv *priv = netdev_priv(netdev);
3607         struct mlx5_core_dev *mdev = priv->mdev;
3608         struct mlx5e_params *cur_params;
3609         struct mlx5e_params new_params;
3610         bool reset = true;
3611         int err = 0;
3612
3613         mutex_lock(&priv->state_lock);
3614
3615         if (enable && priv->xsk.refcnt) {
3616                 netdev_warn(netdev, "LRO is incompatible with AF_XDP (%u XSKs are active)\n",
3617                             priv->xsk.refcnt);
3618                 err = -EINVAL;
3619                 goto out;
3620         }
3621
3622         cur_params = &priv->channels.params;
3623         if (enable && !MLX5E_GET_PFLAG(cur_params, MLX5E_PFLAG_RX_STRIDING_RQ)) {
3624                 netdev_warn(netdev, "can't set LRO with legacy RQ\n");
3625                 err = -EINVAL;
3626                 goto out;
3627         }
3628
3629         new_params = *cur_params;
3630         new_params.lro_en = enable;
3631
3632         if (cur_params->rq_wq_type == MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ) {
3633                 if (mlx5e_rx_mpwqe_is_linear_skb(mdev, cur_params, NULL) ==
3634                     mlx5e_rx_mpwqe_is_linear_skb(mdev, &new_params, NULL))
3635                         reset = false;
3636         }
3637
3638         err = mlx5e_safe_switch_params(priv, &new_params,
3639                                        mlx5e_modify_tirs_lro_ctx, NULL, reset);
3640 out:
3641         mutex_unlock(&priv->state_lock);
3642         return err;
3643 }
3644
3645 static int set_feature_cvlan_filter(struct net_device *netdev, bool enable)
3646 {
3647         struct mlx5e_priv *priv = netdev_priv(netdev);
3648
3649         if (enable)
3650                 mlx5e_enable_cvlan_filter(priv);
3651         else
3652                 mlx5e_disable_cvlan_filter(priv);
3653
3654         return 0;
3655 }
3656
3657 static int set_feature_hw_tc(struct net_device *netdev, bool enable)
3658 {
3659         struct mlx5e_priv *priv = netdev_priv(netdev);
3660
3661 #if IS_ENABLED(CONFIG_MLX5_CLS_ACT)
3662         if (!enable && mlx5e_tc_num_filters(priv, MLX5_TC_FLAG(NIC_OFFLOAD))) {
3663                 netdev_err(netdev,
3664                            "Active offloaded tc filters, can't turn hw_tc_offload off\n");
3665                 return -EINVAL;
3666         }
3667 #endif
3668
3669         if (!enable && priv->htb.maj_id) {
3670                 netdev_err(netdev, "Active HTB offload, can't turn hw_tc_offload off\n");
3671                 return -EINVAL;
3672         }
3673
3674         return 0;
3675 }
3676
3677 static int set_feature_rx_all(struct net_device *netdev, bool enable)
3678 {
3679         struct mlx5e_priv *priv = netdev_priv(netdev);
3680         struct mlx5_core_dev *mdev = priv->mdev;
3681
3682         return mlx5_set_port_fcs(mdev, !enable);
3683 }
3684
3685 static int set_feature_rx_fcs(struct net_device *netdev, bool enable)
3686 {
3687         struct mlx5e_priv *priv = netdev_priv(netdev);
3688         int err;
3689
3690         mutex_lock(&priv->state_lock);
3691
3692         priv->channels.params.scatter_fcs_en = enable;
3693         err = mlx5e_modify_channels_scatter_fcs(&priv->channels, enable);
3694         if (err)
3695                 priv->channels.params.scatter_fcs_en = !enable;
3696
3697         mutex_unlock(&priv->state_lock);
3698
3699         return err;
3700 }
3701
3702 static int set_feature_rx_vlan(struct net_device *netdev, bool enable)
3703 {
3704         struct mlx5e_priv *priv = netdev_priv(netdev);
3705         int err = 0;
3706
3707         mutex_lock(&priv->state_lock);
3708
3709         priv->channels.params.vlan_strip_disable = !enable;
3710         if (!test_bit(MLX5E_STATE_OPENED, &priv->state))
3711                 goto unlock;
3712
3713         err = mlx5e_modify_channels_vsd(&priv->channels, !enable);
3714         if (err)
3715                 priv->channels.params.vlan_strip_disable = enable;
3716
3717 unlock:
3718         mutex_unlock(&priv->state_lock);
3719
3720         return err;
3721 }
3722
3723 #ifdef CONFIG_MLX5_EN_ARFS
3724 static int set_feature_arfs(struct net_device *netdev, bool enable)
3725 {
3726         struct mlx5e_priv *priv = netdev_priv(netdev);
3727         int err;
3728
3729         if (enable)
3730                 err = mlx5e_arfs_enable(priv);
3731         else
3732                 err = mlx5e_arfs_disable(priv);
3733
3734         return err;
3735 }
3736 #endif
3737
3738 static int mlx5e_handle_feature(struct net_device *netdev,
3739                                 netdev_features_t *features,
3740                                 netdev_features_t wanted_features,
3741                                 netdev_features_t feature,
3742                                 mlx5e_feature_handler feature_handler)
3743 {
3744         netdev_features_t changes = wanted_features ^ netdev->features;
3745         bool enable = !!(wanted_features & feature);
3746         int err;
3747
3748         if (!(changes & feature))
3749                 return 0;
3750
3751         err = feature_handler(netdev, enable);
3752         if (err) {
3753                 netdev_err(netdev, "%s feature %pNF failed, err %d\n",
3754                            enable ? "Enable" : "Disable", &feature, err);
3755                 return err;
3756         }
3757
3758         MLX5E_SET_FEATURE(features, feature, enable);
3759         return 0;
3760 }
3761
3762 int mlx5e_set_features(struct net_device *netdev, netdev_features_t features)
3763 {
3764         netdev_features_t oper_features = netdev->features;
3765         int err = 0;
3766
3767 #define MLX5E_HANDLE_FEATURE(feature, handler) \
3768         mlx5e_handle_feature(netdev, &oper_features, features, feature, handler)
3769
3770         err |= MLX5E_HANDLE_FEATURE(NETIF_F_LRO, set_feature_lro);
3771         err |= MLX5E_HANDLE_FEATURE(NETIF_F_HW_VLAN_CTAG_FILTER,
3772                                     set_feature_cvlan_filter);
3773         err |= MLX5E_HANDLE_FEATURE(NETIF_F_HW_TC, set_feature_hw_tc);
3774         err |= MLX5E_HANDLE_FEATURE(NETIF_F_RXALL, set_feature_rx_all);
3775         err |= MLX5E_HANDLE_FEATURE(NETIF_F_RXFCS, set_feature_rx_fcs);
3776         err |= MLX5E_HANDLE_FEATURE(NETIF_F_HW_VLAN_CTAG_RX, set_feature_rx_vlan);
3777 #ifdef CONFIG_MLX5_EN_ARFS
3778         err |= MLX5E_HANDLE_FEATURE(NETIF_F_NTUPLE, set_feature_arfs);
3779 #endif
3780         err |= MLX5E_HANDLE_FEATURE(NETIF_F_HW_TLS_RX, mlx5e_ktls_set_feature_rx);
3781
3782         if (err) {
3783                 netdev->features = oper_features;
3784                 return -EINVAL;
3785         }
3786
3787         return 0;
3788 }
3789
3790 static netdev_features_t mlx5e_fix_features(struct net_device *netdev,
3791                                             netdev_features_t features)
3792 {
3793         struct mlx5e_priv *priv = netdev_priv(netdev);
3794         struct mlx5e_params *params;
3795
3796         mutex_lock(&priv->state_lock);
3797         params = &priv->channels.params;
3798         if (!priv->fs.vlan ||
3799             !bitmap_empty(mlx5e_vlan_get_active_svlans(priv->fs.vlan), VLAN_N_VID)) {
3800                 /* HW strips the outer C-tag header, this is a problem
3801                  * for S-tag traffic.
3802                  */
3803                 features &= ~NETIF_F_HW_VLAN_CTAG_RX;
3804                 if (!params->vlan_strip_disable)
3805                         netdev_warn(netdev, "Dropping C-tag vlan stripping offload due to S-tag vlan\n");
3806         }
3807
3808         if (!MLX5E_GET_PFLAG(params, MLX5E_PFLAG_RX_STRIDING_RQ)) {
3809                 if (features & NETIF_F_LRO) {
3810                         netdev_warn(netdev, "Disabling LRO, not supported in legacy RQ\n");
3811                         features &= ~NETIF_F_LRO;
3812                 }
3813         }
3814
3815         if (MLX5E_GET_PFLAG(params, MLX5E_PFLAG_RX_CQE_COMPRESS)) {
3816                 features &= ~NETIF_F_RXHASH;
3817                 if (netdev->features & NETIF_F_RXHASH)
3818                         netdev_warn(netdev, "Disabling rxhash, not supported when CQE compress is active\n");
3819         }
3820
3821         if (mlx5e_is_uplink_rep(priv)) {
3822                 features &= ~NETIF_F_HW_TLS_RX;
3823                 if (netdev->features & NETIF_F_HW_TLS_RX)
3824                         netdev_warn(netdev, "Disabling hw_tls_rx, not supported in switchdev mode\n");
3825
3826                 features &= ~NETIF_F_HW_TLS_TX;
3827                 if (netdev->features & NETIF_F_HW_TLS_TX)
3828                         netdev_warn(netdev, "Disabling hw_tls_tx, not supported in switchdev mode\n");
3829         }
3830
3831         mutex_unlock(&priv->state_lock);
3832
3833         return features;
3834 }
3835
3836 static bool mlx5e_xsk_validate_mtu(struct net_device *netdev,
3837                                    struct mlx5e_channels *chs,
3838                                    struct mlx5e_params *new_params,
3839                                    struct mlx5_core_dev *mdev)
3840 {
3841         u16 ix;
3842
3843         for (ix = 0; ix < chs->params.num_channels; ix++) {
3844                 struct xsk_buff_pool *xsk_pool =
3845                         mlx5e_xsk_get_pool(&chs->params, chs->params.xsk, ix);
3846                 struct mlx5e_xsk_param xsk;
3847
3848                 if (!xsk_pool)
3849                         continue;
3850
3851                 mlx5e_build_xsk_param(xsk_pool, &xsk);
3852
3853                 if (!mlx5e_validate_xsk_param(new_params, &xsk, mdev)) {
3854                         u32 hr = mlx5e_get_linear_rq_headroom(new_params, &xsk);
3855                         int max_mtu_frame, max_mtu_page, max_mtu;
3856
3857                         /* Two criteria must be met:
3858                          * 1. HW MTU + all headrooms <= XSK frame size.
3859                          * 2. Size of SKBs allocated on XDP_PASS <= PAGE_SIZE.
3860                          */
3861                         max_mtu_frame = MLX5E_HW2SW_MTU(new_params, xsk.chunk_size - hr);
3862                         max_mtu_page = mlx5e_xdp_max_mtu(new_params, &xsk);
3863                         max_mtu = min(max_mtu_frame, max_mtu_page);
3864
3865                         netdev_err(netdev, "MTU %d is too big for an XSK running on channel %u. Try MTU <= %d\n",
3866                                    new_params->sw_mtu, ix, max_mtu);
3867                         return false;
3868                 }
3869         }
3870
3871         return true;
3872 }
3873
3874 int mlx5e_change_mtu(struct net_device *netdev, int new_mtu,
3875                      mlx5e_fp_preactivate preactivate)
3876 {
3877         struct mlx5e_priv *priv = netdev_priv(netdev);
3878         struct mlx5e_params new_params;
3879         struct mlx5e_params *params;
3880         bool reset = true;
3881         int err = 0;
3882
3883         mutex_lock(&priv->state_lock);
3884
3885         params = &priv->channels.params;
3886
3887         new_params = *params;
3888         new_params.sw_mtu = new_mtu;
3889         err = mlx5e_validate_params(priv->mdev, &new_params);
3890         if (err)
3891                 goto out;
3892
3893         if (params->xdp_prog &&
3894             !mlx5e_rx_is_linear_skb(&new_params, NULL)) {
3895                 netdev_err(netdev, "MTU(%d) > %d is not allowed while XDP enabled\n",
3896                            new_mtu, mlx5e_xdp_max_mtu(params, NULL));
3897                 err = -EINVAL;
3898                 goto out;
3899         }
3900
3901         if (priv->xsk.refcnt &&
3902             !mlx5e_xsk_validate_mtu(netdev, &priv->channels,
3903                                     &new_params, priv->mdev)) {
3904                 err = -EINVAL;
3905                 goto out;
3906         }
3907
3908         if (params->lro_en)
3909                 reset = false;
3910
3911         if (params->rq_wq_type == MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ) {
3912                 bool is_linear_old = mlx5e_rx_mpwqe_is_linear_skb(priv->mdev, params, NULL);
3913                 bool is_linear_new = mlx5e_rx_mpwqe_is_linear_skb(priv->mdev,
3914                                                                   &new_params, NULL);
3915                 u8 ppw_old = mlx5e_mpwqe_log_pkts_per_wqe(params, NULL);
3916                 u8 ppw_new = mlx5e_mpwqe_log_pkts_per_wqe(&new_params, NULL);
3917
3918                 /* Always reset in linear mode - hw_mtu is used in data path.
3919                  * Check that the mode was non-linear and didn't change.
3920                  * If XSK is active, XSK RQs are linear.
3921                  */
3922                 if (!is_linear_old && !is_linear_new && !priv->xsk.refcnt &&
3923                     ppw_old == ppw_new)
3924                         reset = false;
3925         }
3926
3927         err = mlx5e_safe_switch_params(priv, &new_params, preactivate, NULL, reset);
3928
3929 out:
3930         netdev->mtu = params->sw_mtu;
3931         mutex_unlock(&priv->state_lock);
3932         return err;
3933 }
3934
3935 static int mlx5e_change_nic_mtu(struct net_device *netdev, int new_mtu)
3936 {
3937         return mlx5e_change_mtu(netdev, new_mtu, mlx5e_set_dev_port_mtu_ctx);
3938 }
3939
3940 int mlx5e_ptp_rx_manage_fs_ctx(struct mlx5e_priv *priv, void *ctx)
3941 {
3942         bool set  = *(bool *)ctx;
3943
3944         return mlx5e_ptp_rx_manage_fs(priv, set);
3945 }
3946
3947 static int mlx5e_hwstamp_config_no_ptp_rx(struct mlx5e_priv *priv, bool rx_filter)
3948 {
3949         bool rx_cqe_compress_def = priv->channels.params.rx_cqe_compress_def;
3950         int err;
3951
3952         if (!rx_filter)
3953                 /* Reset CQE compression to Admin default */
3954                 return mlx5e_modify_rx_cqe_compression_locked(priv, rx_cqe_compress_def);
3955
3956         if (!MLX5E_GET_PFLAG(&priv->channels.params, MLX5E_PFLAG_RX_CQE_COMPRESS))
3957                 return 0;
3958
3959         /* Disable CQE compression */
3960         netdev_warn(priv->netdev, "Disabling RX cqe compression\n");
3961         err = mlx5e_modify_rx_cqe_compression_locked(priv, false);
3962         if (err)
3963                 netdev_err(priv->netdev, "Failed disabling cqe compression err=%d\n", err);
3964
3965         return err;
3966 }
3967
3968 static int mlx5e_hwstamp_config_ptp_rx(struct mlx5e_priv *priv, bool ptp_rx)
3969 {
3970         struct mlx5e_params new_params;
3971
3972         if (ptp_rx == priv->channels.params.ptp_rx)
3973                 return 0;
3974
3975         new_params = priv->channels.params;
3976         new_params.ptp_rx = ptp_rx;
3977         return mlx5e_safe_switch_params(priv, &new_params, mlx5e_ptp_rx_manage_fs_ctx,
3978                                         &new_params.ptp_rx, true);
3979 }
3980
3981 int mlx5e_hwstamp_set(struct mlx5e_priv *priv, struct ifreq *ifr)
3982 {
3983         struct hwtstamp_config config;
3984         bool rx_cqe_compress_def;
3985         bool ptp_rx;
3986         int err;
3987
3988         if (!MLX5_CAP_GEN(priv->mdev, device_frequency_khz) ||
3989             (mlx5_clock_get_ptp_index(priv->mdev) == -1))
3990                 return -EOPNOTSUPP;
3991
3992         if (copy_from_user(&config, ifr->ifr_data, sizeof(config)))
3993                 return -EFAULT;
3994
3995         /* TX HW timestamp */
3996         switch (config.tx_type) {
3997         case HWTSTAMP_TX_OFF:
3998         case HWTSTAMP_TX_ON:
3999                 break;
4000         default:
4001                 return -ERANGE;
4002         }
4003
4004         mutex_lock(&priv->state_lock);
4005         rx_cqe_compress_def = priv->channels.params.rx_cqe_compress_def;
4006
4007         /* RX HW timestamp */
4008         switch (config.rx_filter) {
4009         case HWTSTAMP_FILTER_NONE:
4010                 ptp_rx = false;
4011                 break;
4012         case HWTSTAMP_FILTER_ALL:
4013         case HWTSTAMP_FILTER_SOME:
4014         case HWTSTAMP_FILTER_PTP_V1_L4_EVENT:
4015         case HWTSTAMP_FILTER_PTP_V1_L4_SYNC:
4016         case HWTSTAMP_FILTER_PTP_V1_L4_DELAY_REQ:
4017         case HWTSTAMP_FILTER_PTP_V2_L4_EVENT:
4018         case HWTSTAMP_FILTER_PTP_V2_L4_SYNC:
4019         case HWTSTAMP_FILTER_PTP_V2_L4_DELAY_REQ:
4020         case HWTSTAMP_FILTER_PTP_V2_L2_EVENT:
4021         case HWTSTAMP_FILTER_PTP_V2_L2_SYNC:
4022         case HWTSTAMP_FILTER_PTP_V2_L2_DELAY_REQ:
4023         case HWTSTAMP_FILTER_PTP_V2_EVENT:
4024         case HWTSTAMP_FILTER_PTP_V2_SYNC:
4025         case HWTSTAMP_FILTER_PTP_V2_DELAY_REQ:
4026         case HWTSTAMP_FILTER_NTP_ALL:
4027                 config.rx_filter = HWTSTAMP_FILTER_ALL;
4028                 /* ptp_rx is set if both HW TS is set and CQE
4029                  * compression is set
4030                  */
4031                 ptp_rx = rx_cqe_compress_def;
4032                 break;
4033         default:
4034                 err = -ERANGE;
4035                 goto err_unlock;
4036         }
4037
4038         if (!priv->profile->rx_ptp_support)
4039                 err = mlx5e_hwstamp_config_no_ptp_rx(priv,
4040                                                      config.rx_filter != HWTSTAMP_FILTER_NONE);
4041         else
4042                 err = mlx5e_hwstamp_config_ptp_rx(priv, ptp_rx);
4043         if (err)
4044                 goto err_unlock;
4045
4046         memcpy(&priv->tstamp, &config, sizeof(config));
4047         mutex_unlock(&priv->state_lock);
4048
4049         /* might need to fix some features */
4050         netdev_update_features(priv->netdev);
4051
4052         return copy_to_user(ifr->ifr_data, &config,
4053                             sizeof(config)) ? -EFAULT : 0;
4054 err_unlock:
4055         mutex_unlock(&priv->state_lock);
4056         return err;
4057 }
4058
4059 int mlx5e_hwstamp_get(struct mlx5e_priv *priv, struct ifreq *ifr)
4060 {
4061         struct hwtstamp_config *cfg = &priv->tstamp;
4062
4063         if (!MLX5_CAP_GEN(priv->mdev, device_frequency_khz))
4064                 return -EOPNOTSUPP;
4065
4066         return copy_to_user(ifr->ifr_data, cfg, sizeof(*cfg)) ? -EFAULT : 0;
4067 }
4068
4069 static int mlx5e_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
4070 {
4071         struct mlx5e_priv *priv = netdev_priv(dev);
4072
4073         switch (cmd) {
4074         case SIOCSHWTSTAMP:
4075                 return mlx5e_hwstamp_set(priv, ifr);
4076         case SIOCGHWTSTAMP:
4077                 return mlx5e_hwstamp_get(priv, ifr);
4078         default:
4079                 return -EOPNOTSUPP;
4080         }
4081 }
4082
4083 #ifdef CONFIG_MLX5_ESWITCH
4084 int mlx5e_set_vf_mac(struct net_device *dev, int vf, u8 *mac)
4085 {
4086         struct mlx5e_priv *priv = netdev_priv(dev);
4087         struct mlx5_core_dev *mdev = priv->mdev;
4088
4089         return mlx5_eswitch_set_vport_mac(mdev->priv.eswitch, vf + 1, mac);
4090 }
4091
4092 static int mlx5e_set_vf_vlan(struct net_device *dev, int vf, u16 vlan, u8 qos,
4093                              __be16 vlan_proto)
4094 {
4095         struct mlx5e_priv *priv = netdev_priv(dev);
4096         struct mlx5_core_dev *mdev = priv->mdev;
4097
4098         if (vlan_proto != htons(ETH_P_8021Q))
4099                 return -EPROTONOSUPPORT;
4100
4101         return mlx5_eswitch_set_vport_vlan(mdev->priv.eswitch, vf + 1,
4102                                            vlan, qos);
4103 }
4104
4105 static int mlx5e_set_vf_spoofchk(struct net_device *dev, int vf, bool setting)
4106 {
4107         struct mlx5e_priv *priv = netdev_priv(dev);
4108         struct mlx5_core_dev *mdev = priv->mdev;
4109
4110         return mlx5_eswitch_set_vport_spoofchk(mdev->priv.eswitch, vf + 1, setting);
4111 }
4112
4113 static int mlx5e_set_vf_trust(struct net_device *dev, int vf, bool setting)
4114 {
4115         struct mlx5e_priv *priv = netdev_priv(dev);
4116         struct mlx5_core_dev *mdev = priv->mdev;
4117
4118         return mlx5_eswitch_set_vport_trust(mdev->priv.eswitch, vf + 1, setting);
4119 }
4120
4121 int mlx5e_set_vf_rate(struct net_device *dev, int vf, int min_tx_rate,
4122                       int max_tx_rate)
4123 {
4124         struct mlx5e_priv *priv = netdev_priv(dev);
4125         struct mlx5_core_dev *mdev = priv->mdev;
4126
4127         return mlx5_eswitch_set_vport_rate(mdev->priv.eswitch, vf + 1,
4128                                            max_tx_rate, min_tx_rate);
4129 }
4130
4131 static int mlx5_vport_link2ifla(u8 esw_link)
4132 {
4133         switch (esw_link) {
4134         case MLX5_VPORT_ADMIN_STATE_DOWN:
4135                 return IFLA_VF_LINK_STATE_DISABLE;
4136         case MLX5_VPORT_ADMIN_STATE_UP:
4137                 return IFLA_VF_LINK_STATE_ENABLE;
4138         }
4139         return IFLA_VF_LINK_STATE_AUTO;
4140 }
4141
4142 static int mlx5_ifla_link2vport(u8 ifla_link)
4143 {
4144         switch (ifla_link) {
4145         case IFLA_VF_LINK_STATE_DISABLE:
4146                 return MLX5_VPORT_ADMIN_STATE_DOWN;
4147         case IFLA_VF_LINK_STATE_ENABLE:
4148                 return MLX5_VPORT_ADMIN_STATE_UP;
4149         }
4150         return MLX5_VPORT_ADMIN_STATE_AUTO;
4151 }
4152
4153 static int mlx5e_set_vf_link_state(struct net_device *dev, int vf,
4154                                    int link_state)
4155 {
4156         struct mlx5e_priv *priv = netdev_priv(dev);
4157         struct mlx5_core_dev *mdev = priv->mdev;
4158
4159         if (mlx5e_is_uplink_rep(priv))
4160                 return -EOPNOTSUPP;
4161
4162         return mlx5_eswitch_set_vport_state(mdev->priv.eswitch, vf + 1,
4163                                             mlx5_ifla_link2vport(link_state));
4164 }
4165
4166 int mlx5e_get_vf_config(struct net_device *dev,
4167                         int vf, struct ifla_vf_info *ivi)
4168 {
4169         struct mlx5e_priv *priv = netdev_priv(dev);
4170         struct mlx5_core_dev *mdev = priv->mdev;
4171         int err;
4172
4173         if (!netif_device_present(dev))
4174                 return -EOPNOTSUPP;
4175
4176         err = mlx5_eswitch_get_vport_config(mdev->priv.eswitch, vf + 1, ivi);
4177         if (err)
4178                 return err;
4179         ivi->linkstate = mlx5_vport_link2ifla(ivi->linkstate);
4180         return 0;
4181 }
4182
4183 int mlx5e_get_vf_stats(struct net_device *dev,
4184                        int vf, struct ifla_vf_stats *vf_stats)
4185 {
4186         struct mlx5e_priv *priv = netdev_priv(dev);
4187         struct mlx5_core_dev *mdev = priv->mdev;
4188
4189         return mlx5_eswitch_get_vport_stats(mdev->priv.eswitch, vf + 1,
4190                                             vf_stats);
4191 }
4192
4193 static bool
4194 mlx5e_has_offload_stats(const struct net_device *dev, int attr_id)
4195 {
4196         struct mlx5e_priv *priv = netdev_priv(dev);
4197
4198         if (!netif_device_present(dev))
4199                 return false;
4200
4201         if (!mlx5e_is_uplink_rep(priv))
4202                 return false;
4203
4204         return mlx5e_rep_has_offload_stats(dev, attr_id);
4205 }
4206
4207 static int
4208 mlx5e_get_offload_stats(int attr_id, const struct net_device *dev,
4209                         void *sp)
4210 {
4211         struct mlx5e_priv *priv = netdev_priv(dev);
4212
4213         if (!mlx5e_is_uplink_rep(priv))
4214                 return -EOPNOTSUPP;
4215
4216         return mlx5e_rep_get_offload_stats(attr_id, dev, sp);
4217 }
4218 #endif
4219
4220 static bool mlx5e_tunnel_proto_supported_tx(struct mlx5_core_dev *mdev, u8 proto_type)
4221 {
4222         switch (proto_type) {
4223         case IPPROTO_GRE:
4224                 return MLX5_CAP_ETH(mdev, tunnel_stateless_gre);
4225         case IPPROTO_IPIP:
4226         case IPPROTO_IPV6:
4227                 return (MLX5_CAP_ETH(mdev, tunnel_stateless_ip_over_ip) ||
4228                         MLX5_CAP_ETH(mdev, tunnel_stateless_ip_over_ip_tx));
4229         default:
4230                 return false;
4231         }
4232 }
4233
4234 static bool mlx5e_gre_tunnel_inner_proto_offload_supported(struct mlx5_core_dev *mdev,
4235                                                            struct sk_buff *skb)
4236 {
4237         switch (skb->inner_protocol) {
4238         case htons(ETH_P_IP):
4239         case htons(ETH_P_IPV6):
4240         case htons(ETH_P_TEB):
4241                 return true;
4242         case htons(ETH_P_MPLS_UC):
4243         case htons(ETH_P_MPLS_MC):
4244                 return MLX5_CAP_ETH(mdev, tunnel_stateless_mpls_over_gre);
4245         }
4246         return false;
4247 }
4248
4249 static netdev_features_t mlx5e_tunnel_features_check(struct mlx5e_priv *priv,
4250                                                      struct sk_buff *skb,
4251                                                      netdev_features_t features)
4252 {
4253         unsigned int offset = 0;
4254         struct udphdr *udph;
4255         u8 proto;
4256         u16 port;
4257
4258         switch (vlan_get_protocol(skb)) {
4259         case htons(ETH_P_IP):
4260                 proto = ip_hdr(skb)->protocol;
4261                 break;
4262         case htons(ETH_P_IPV6):
4263                 proto = ipv6_find_hdr(skb, &offset, -1, NULL, NULL);
4264                 break;
4265         default:
4266                 goto out;
4267         }
4268
4269         switch (proto) {
4270         case IPPROTO_GRE:
4271                 if (mlx5e_gre_tunnel_inner_proto_offload_supported(priv->mdev, skb))
4272                         return features;
4273                 break;
4274         case IPPROTO_IPIP:
4275         case IPPROTO_IPV6:
4276                 if (mlx5e_tunnel_proto_supported_tx(priv->mdev, IPPROTO_IPIP))
4277                         return features;
4278                 break;
4279         case IPPROTO_UDP:
4280                 udph = udp_hdr(skb);
4281                 port = be16_to_cpu(udph->dest);
4282
4283                 /* Verify if UDP port is being offloaded by HW */
4284                 if (mlx5_vxlan_lookup_port(priv->mdev->vxlan, port))
4285                         return features;
4286
4287 #if IS_ENABLED(CONFIG_GENEVE)
4288                 /* Support Geneve offload for default UDP port */
4289                 if (port == GENEVE_UDP_PORT && mlx5_geneve_tx_allowed(priv->mdev))
4290                         return features;
4291 #endif
4292                 break;
4293 #ifdef CONFIG_MLX5_EN_IPSEC
4294         case IPPROTO_ESP:
4295                 return mlx5e_ipsec_feature_check(skb, features);
4296 #endif
4297         }
4298
4299 out:
4300         /* Disable CSUM and GSO if the udp dport is not offloaded by HW */
4301         return features & ~(NETIF_F_CSUM_MASK | NETIF_F_GSO_MASK);
4302 }
4303
4304 netdev_features_t mlx5e_features_check(struct sk_buff *skb,
4305                                        struct net_device *netdev,
4306                                        netdev_features_t features)
4307 {
4308         struct mlx5e_priv *priv = netdev_priv(netdev);
4309
4310         features = vlan_features_check(skb, features);
4311         features = vxlan_features_check(skb, features);
4312
4313         /* Validate if the tunneled packet is being offloaded by HW */
4314         if (skb->encapsulation &&
4315             (features & NETIF_F_CSUM_MASK || features & NETIF_F_GSO_MASK))
4316                 return mlx5e_tunnel_features_check(priv, skb, features);
4317
4318         return features;
4319 }
4320
4321 static void mlx5e_tx_timeout_work(struct work_struct *work)
4322 {
4323         struct mlx5e_priv *priv = container_of(work, struct mlx5e_priv,
4324                                                tx_timeout_work);
4325         struct net_device *netdev = priv->netdev;
4326         int i;
4327
4328         rtnl_lock();
4329         mutex_lock(&priv->state_lock);
4330
4331         if (!test_bit(MLX5E_STATE_OPENED, &priv->state))
4332                 goto unlock;
4333
4334         for (i = 0; i < netdev->real_num_tx_queues; i++) {
4335                 struct netdev_queue *dev_queue =
4336                         netdev_get_tx_queue(netdev, i);
4337                 struct mlx5e_txqsq *sq = priv->txq2sq[i];
4338
4339                 if (!netif_xmit_stopped(dev_queue))
4340                         continue;
4341
4342                 if (mlx5e_reporter_tx_timeout(sq))
4343                 /* break if tried to reopened channels */
4344                         break;
4345         }
4346
4347 unlock:
4348         mutex_unlock(&priv->state_lock);
4349         rtnl_unlock();
4350 }
4351
4352 static void mlx5e_tx_timeout(struct net_device *dev, unsigned int txqueue)
4353 {
4354         struct mlx5e_priv *priv = netdev_priv(dev);
4355
4356         netdev_err(dev, "TX timeout detected\n");
4357         queue_work(priv->wq, &priv->tx_timeout_work);
4358 }
4359
4360 static int mlx5e_xdp_allowed(struct mlx5e_priv *priv, struct bpf_prog *prog)
4361 {
4362         struct net_device *netdev = priv->netdev;
4363         struct mlx5e_params new_params;
4364
4365         if (priv->channels.params.lro_en) {
4366                 netdev_warn(netdev, "can't set XDP while LRO is on, disable LRO first\n");
4367                 return -EINVAL;
4368         }
4369
4370         if (mlx5_fpga_is_ipsec_device(priv->mdev)) {
4371                 netdev_warn(netdev,
4372                             "XDP is not available on Innova cards with IPsec support\n");
4373                 return -EINVAL;
4374         }
4375
4376         new_params = priv->channels.params;
4377         new_params.xdp_prog = prog;
4378
4379         /* No XSK params: AF_XDP can't be enabled yet at the point of setting
4380          * the XDP program.
4381          */
4382         if (!mlx5e_rx_is_linear_skb(&new_params, NULL)) {
4383                 netdev_warn(netdev, "XDP is not allowed with MTU(%d) > %d\n",
4384                             new_params.sw_mtu,
4385                             mlx5e_xdp_max_mtu(&new_params, NULL));
4386                 return -EINVAL;
4387         }
4388
4389         return 0;
4390 }
4391
4392 static void mlx5e_rq_replace_xdp_prog(struct mlx5e_rq *rq, struct bpf_prog *prog)
4393 {
4394         struct bpf_prog *old_prog;
4395
4396         old_prog = rcu_replace_pointer(rq->xdp_prog, prog,
4397                                        lockdep_is_held(&rq->priv->state_lock));
4398         if (old_prog)
4399                 bpf_prog_put(old_prog);
4400 }
4401
4402 static int mlx5e_xdp_set(struct net_device *netdev, struct bpf_prog *prog)
4403 {
4404         struct mlx5e_priv *priv = netdev_priv(netdev);
4405         struct mlx5e_params new_params;
4406         struct bpf_prog *old_prog;
4407         int err = 0;
4408         bool reset;
4409         int i;
4410
4411         mutex_lock(&priv->state_lock);
4412
4413         if (prog) {
4414                 err = mlx5e_xdp_allowed(priv, prog);
4415                 if (err)
4416                         goto unlock;
4417         }
4418
4419         /* no need for full reset when exchanging programs */
4420         reset = (!priv->channels.params.xdp_prog || !prog);
4421
4422         new_params = priv->channels.params;
4423         new_params.xdp_prog = prog;
4424         if (reset)
4425                 mlx5e_set_rq_type(priv->mdev, &new_params);
4426         old_prog = priv->channels.params.xdp_prog;
4427
4428         err = mlx5e_safe_switch_params(priv, &new_params, NULL, NULL, reset);
4429         if (err)
4430                 goto unlock;
4431
4432         if (old_prog)
4433                 bpf_prog_put(old_prog);
4434
4435         if (!test_bit(MLX5E_STATE_OPENED, &priv->state) || reset)
4436                 goto unlock;
4437
4438         /* exchanging programs w/o reset, we update ref counts on behalf
4439          * of the channels RQs here.
4440          */
4441         bpf_prog_add(prog, priv->channels.num);
4442         for (i = 0; i < priv->channels.num; i++) {
4443                 struct mlx5e_channel *c = priv->channels.c[i];
4444
4445                 mlx5e_rq_replace_xdp_prog(&c->rq, prog);
4446                 if (test_bit(MLX5E_CHANNEL_STATE_XSK, c->state)) {
4447                         bpf_prog_inc(prog);
4448                         mlx5e_rq_replace_xdp_prog(&c->xskrq, prog);
4449                 }
4450         }
4451
4452 unlock:
4453         mutex_unlock(&priv->state_lock);
4454         return err;
4455 }
4456
4457 static int mlx5e_xdp(struct net_device *dev, struct netdev_bpf *xdp)
4458 {
4459         switch (xdp->command) {
4460         case XDP_SETUP_PROG:
4461                 return mlx5e_xdp_set(dev, xdp->prog);
4462         case XDP_SETUP_XSK_POOL:
4463                 return mlx5e_xsk_setup_pool(dev, xdp->xsk.pool,
4464                                             xdp->xsk.queue_id);
4465         default:
4466                 return -EINVAL;
4467         }
4468 }
4469
4470 #ifdef CONFIG_MLX5_ESWITCH
4471 static int mlx5e_bridge_getlink(struct sk_buff *skb, u32 pid, u32 seq,
4472                                 struct net_device *dev, u32 filter_mask,
4473                                 int nlflags)
4474 {
4475         struct mlx5e_priv *priv = netdev_priv(dev);
4476         struct mlx5_core_dev *mdev = priv->mdev;
4477         u8 mode, setting;
4478         int err;
4479
4480         err = mlx5_eswitch_get_vepa(mdev->priv.eswitch, &setting);
4481         if (err)
4482                 return err;
4483         mode = setting ? BRIDGE_MODE_VEPA : BRIDGE_MODE_VEB;
4484         return ndo_dflt_bridge_getlink(skb, pid, seq, dev,
4485                                        mode,
4486                                        0, 0, nlflags, filter_mask, NULL);
4487 }
4488
4489 static int mlx5e_bridge_setlink(struct net_device *dev, struct nlmsghdr *nlh,
4490                                 u16 flags, struct netlink_ext_ack *extack)
4491 {
4492         struct mlx5e_priv *priv = netdev_priv(dev);
4493         struct mlx5_core_dev *mdev = priv->mdev;
4494         struct nlattr *attr, *br_spec;
4495         u16 mode = BRIDGE_MODE_UNDEF;
4496         u8 setting;
4497         int rem;
4498
4499         br_spec = nlmsg_find_attr(nlh, sizeof(struct ifinfomsg), IFLA_AF_SPEC);
4500         if (!br_spec)
4501                 return -EINVAL;
4502
4503         nla_for_each_nested(attr, br_spec, rem) {
4504                 if (nla_type(attr) != IFLA_BRIDGE_MODE)
4505                         continue;
4506
4507                 if (nla_len(attr) < sizeof(mode))
4508                         return -EINVAL;
4509
4510                 mode = nla_get_u16(attr);
4511                 if (mode > BRIDGE_MODE_VEPA)
4512                         return -EINVAL;
4513
4514                 break;
4515         }
4516
4517         if (mode == BRIDGE_MODE_UNDEF)
4518                 return -EINVAL;
4519
4520         setting = (mode == BRIDGE_MODE_VEPA) ?  1 : 0;
4521         return mlx5_eswitch_set_vepa(mdev->priv.eswitch, setting);
4522 }
4523 #endif
4524
4525 const struct net_device_ops mlx5e_netdev_ops = {
4526         .ndo_open                = mlx5e_open,
4527         .ndo_stop                = mlx5e_close,
4528         .ndo_start_xmit          = mlx5e_xmit,
4529         .ndo_setup_tc            = mlx5e_setup_tc,
4530         .ndo_select_queue        = mlx5e_select_queue,
4531         .ndo_get_stats64         = mlx5e_get_stats,
4532         .ndo_set_rx_mode         = mlx5e_set_rx_mode,
4533         .ndo_set_mac_address     = mlx5e_set_mac,
4534         .ndo_vlan_rx_add_vid     = mlx5e_vlan_rx_add_vid,
4535         .ndo_vlan_rx_kill_vid    = mlx5e_vlan_rx_kill_vid,
4536         .ndo_set_features        = mlx5e_set_features,
4537         .ndo_fix_features        = mlx5e_fix_features,
4538         .ndo_change_mtu          = mlx5e_change_nic_mtu,
4539         .ndo_do_ioctl            = mlx5e_ioctl,
4540         .ndo_set_tx_maxrate      = mlx5e_set_tx_maxrate,
4541         .ndo_features_check      = mlx5e_features_check,
4542         .ndo_tx_timeout          = mlx5e_tx_timeout,
4543         .ndo_bpf                 = mlx5e_xdp,
4544         .ndo_xdp_xmit            = mlx5e_xdp_xmit,
4545         .ndo_xsk_wakeup          = mlx5e_xsk_wakeup,
4546 #ifdef CONFIG_MLX5_EN_ARFS
4547         .ndo_rx_flow_steer       = mlx5e_rx_flow_steer,
4548 #endif
4549 #ifdef CONFIG_MLX5_ESWITCH
4550         .ndo_bridge_setlink      = mlx5e_bridge_setlink,
4551         .ndo_bridge_getlink      = mlx5e_bridge_getlink,
4552
4553         /* SRIOV E-Switch NDOs */
4554         .ndo_set_vf_mac          = mlx5e_set_vf_mac,
4555         .ndo_set_vf_vlan         = mlx5e_set_vf_vlan,
4556         .ndo_set_vf_spoofchk     = mlx5e_set_vf_spoofchk,
4557         .ndo_set_vf_trust        = mlx5e_set_vf_trust,
4558         .ndo_set_vf_rate         = mlx5e_set_vf_rate,
4559         .ndo_get_vf_config       = mlx5e_get_vf_config,
4560         .ndo_set_vf_link_state   = mlx5e_set_vf_link_state,
4561         .ndo_get_vf_stats        = mlx5e_get_vf_stats,
4562         .ndo_has_offload_stats   = mlx5e_has_offload_stats,
4563         .ndo_get_offload_stats   = mlx5e_get_offload_stats,
4564 #endif
4565         .ndo_get_devlink_port    = mlx5e_get_devlink_port,
4566 };
4567
4568 void mlx5e_build_default_indir_rqt(u32 *indirection_rqt, int len,
4569                                    int num_channels)
4570 {
4571         int i;
4572
4573         for (i = 0; i < len; i++)
4574                 indirection_rqt[i] = i % num_channels;
4575 }
4576
4577 static u32 mlx5e_choose_lro_timeout(struct mlx5_core_dev *mdev, u32 wanted_timeout)
4578 {
4579         int i;
4580
4581         /* The supported periods are organized in ascending order */
4582         for (i = 0; i < MLX5E_LRO_TIMEOUT_ARR_SIZE - 1; i++)
4583                 if (MLX5_CAP_ETH(mdev, lro_timer_supported_periods[i]) >= wanted_timeout)
4584                         break;
4585
4586         return MLX5_CAP_ETH(mdev, lro_timer_supported_periods[i]);
4587 }
4588
4589 void mlx5e_build_rss_params(struct mlx5e_rss_params *rss_params,
4590                             u16 num_channels)
4591 {
4592         enum mlx5e_traffic_types tt;
4593
4594         rss_params->hash.hfunc = ETH_RSS_HASH_TOP;
4595         netdev_rss_key_fill(rss_params->hash.toeplitz_hash_key,
4596                             sizeof(rss_params->hash.toeplitz_hash_key));
4597         mlx5e_build_default_indir_rqt(rss_params->indir.table,
4598                                       MLX5E_INDIR_RQT_SIZE, num_channels);
4599         for (tt = 0; tt < MLX5E_NUM_INDIR_TIRS; tt++)
4600                 rss_params->rx_hash_fields[tt] =
4601                         tirc_default_config[tt].rx_hash_fields;
4602 }
4603
4604 void mlx5e_build_nic_params(struct mlx5e_priv *priv, struct mlx5e_xsk *xsk, u16 mtu)
4605 {
4606         struct mlx5e_params *params = &priv->channels.params;
4607         struct mlx5_core_dev *mdev = priv->mdev;
4608         u8 rx_cq_period_mode;
4609
4610         priv->max_nch = mlx5e_calc_max_nch(priv, priv->profile);
4611
4612         params->sw_mtu = mtu;
4613         params->hard_mtu = MLX5E_ETH_HARD_MTU;
4614         params->num_channels = min_t(unsigned int, MLX5E_MAX_NUM_CHANNELS / 2,
4615                                      priv->max_nch);
4616         params->num_tc       = 1;
4617
4618         /* Set an initial non-zero value, so that mlx5e_select_queue won't
4619          * divide by zero if called before first activating channels.
4620          */
4621         priv->num_tc_x_num_ch = params->num_channels * params->num_tc;
4622
4623         /* SQ */
4624         params->log_sq_size = is_kdump_kernel() ?
4625                 MLX5E_PARAMS_MINIMUM_LOG_SQ_SIZE :
4626                 MLX5E_PARAMS_DEFAULT_LOG_SQ_SIZE;
4627         MLX5E_SET_PFLAG(params, MLX5E_PFLAG_SKB_TX_MPWQE, mlx5e_tx_mpwqe_supported(mdev));
4628
4629         /* XDP SQ */
4630         MLX5E_SET_PFLAG(params, MLX5E_PFLAG_XDP_TX_MPWQE, mlx5e_tx_mpwqe_supported(mdev));
4631
4632         /* set CQE compression */
4633         params->rx_cqe_compress_def = false;
4634         if (MLX5_CAP_GEN(mdev, cqe_compression) &&
4635             MLX5_CAP_GEN(mdev, vport_group_manager))
4636                 params->rx_cqe_compress_def = slow_pci_heuristic(mdev);
4637
4638         MLX5E_SET_PFLAG(params, MLX5E_PFLAG_RX_CQE_COMPRESS, params->rx_cqe_compress_def);
4639         MLX5E_SET_PFLAG(params, MLX5E_PFLAG_RX_NO_CSUM_COMPLETE, false);
4640
4641         /* RQ */
4642         mlx5e_build_rq_params(mdev, params);
4643
4644         /* HW LRO */
4645         if (MLX5_CAP_ETH(mdev, lro_cap) &&
4646             params->rq_wq_type == MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ) {
4647                 /* No XSK params: checking the availability of striding RQ in general. */
4648                 if (!mlx5e_rx_mpwqe_is_linear_skb(mdev, params, NULL))
4649                         params->lro_en = !slow_pci_heuristic(mdev);
4650         }
4651         params->lro_timeout = mlx5e_choose_lro_timeout(mdev, MLX5E_DEFAULT_LRO_TIMEOUT);
4652
4653         /* CQ moderation params */
4654         rx_cq_period_mode = MLX5_CAP_GEN(mdev, cq_period_start_from_cqe) ?
4655                         MLX5_CQ_PERIOD_MODE_START_FROM_CQE :
4656                         MLX5_CQ_PERIOD_MODE_START_FROM_EQE;
4657         params->rx_dim_enabled = MLX5_CAP_GEN(mdev, cq_moderation);
4658         params->tx_dim_enabled = MLX5_CAP_GEN(mdev, cq_moderation);
4659         mlx5e_set_rx_cq_mode_params(params, rx_cq_period_mode);
4660         mlx5e_set_tx_cq_mode_params(params, MLX5_CQ_PERIOD_MODE_START_FROM_EQE);
4661
4662         /* TX inline */
4663         mlx5_query_min_inline(mdev, &params->tx_min_inline_mode);
4664
4665         params->tunneled_offload_en = mlx5e_tunnel_inner_ft_supported(mdev);
4666
4667         /* AF_XDP */
4668         params->xsk = xsk;
4669
4670         /* Do not update netdev->features directly in here
4671          * on mlx5e_attach_netdev() we will call mlx5e_update_features()
4672          * To update netdev->features please modify mlx5e_fix_features()
4673          */
4674 }
4675
4676 static void mlx5e_set_netdev_dev_addr(struct net_device *netdev)
4677 {
4678         struct mlx5e_priv *priv = netdev_priv(netdev);
4679
4680         mlx5_query_mac_address(priv->mdev, netdev->dev_addr);
4681         if (is_zero_ether_addr(netdev->dev_addr) &&
4682             !MLX5_CAP_GEN(priv->mdev, vport_group_manager)) {
4683                 eth_hw_addr_random(netdev);
4684                 mlx5_core_info(priv->mdev, "Assigned random MAC address %pM\n", netdev->dev_addr);
4685         }
4686 }
4687
4688 static int mlx5e_vxlan_set_port(struct net_device *netdev, unsigned int table,
4689                                 unsigned int entry, struct udp_tunnel_info *ti)
4690 {
4691         struct mlx5e_priv *priv = netdev_priv(netdev);
4692
4693         return mlx5_vxlan_add_port(priv->mdev->vxlan, ntohs(ti->port));
4694 }
4695
4696 static int mlx5e_vxlan_unset_port(struct net_device *netdev, unsigned int table,
4697                                   unsigned int entry, struct udp_tunnel_info *ti)
4698 {
4699         struct mlx5e_priv *priv = netdev_priv(netdev);
4700
4701         return mlx5_vxlan_del_port(priv->mdev->vxlan, ntohs(ti->port));
4702 }
4703
4704 void mlx5e_vxlan_set_netdev_info(struct mlx5e_priv *priv)
4705 {
4706         if (!mlx5_vxlan_allowed(priv->mdev->vxlan))
4707                 return;
4708
4709         priv->nic_info.set_port = mlx5e_vxlan_set_port;
4710         priv->nic_info.unset_port = mlx5e_vxlan_unset_port;
4711         priv->nic_info.flags = UDP_TUNNEL_NIC_INFO_MAY_SLEEP |
4712                                 UDP_TUNNEL_NIC_INFO_STATIC_IANA_VXLAN;
4713         priv->nic_info.tables[0].tunnel_types = UDP_TUNNEL_TYPE_VXLAN;
4714         /* Don't count the space hard-coded to the IANA port */
4715         priv->nic_info.tables[0].n_entries =
4716                 mlx5_vxlan_max_udp_ports(priv->mdev) - 1;
4717
4718         priv->netdev->udp_tunnel_nic_info = &priv->nic_info;
4719 }
4720
4721 static bool mlx5e_tunnel_any_tx_proto_supported(struct mlx5_core_dev *mdev)
4722 {
4723         int tt;
4724
4725         for (tt = 0; tt < MLX5E_NUM_TUNNEL_TT; tt++) {
4726                 if (mlx5e_tunnel_proto_supported_tx(mdev, mlx5e_get_proto_by_tunnel_type(tt)))
4727                         return true;
4728         }
4729         return (mlx5_vxlan_allowed(mdev->vxlan) || mlx5_geneve_tx_allowed(mdev));
4730 }
4731
4732 static void mlx5e_build_nic_netdev(struct net_device *netdev)
4733 {
4734         struct mlx5e_priv *priv = netdev_priv(netdev);
4735         struct mlx5_core_dev *mdev = priv->mdev;
4736         bool fcs_supported;
4737         bool fcs_enabled;
4738
4739         SET_NETDEV_DEV(netdev, mdev->device);
4740
4741         netdev->netdev_ops = &mlx5e_netdev_ops;
4742
4743         mlx5e_dcbnl_build_netdev(netdev);
4744
4745         netdev->watchdog_timeo    = 15 * HZ;
4746
4747         netdev->ethtool_ops       = &mlx5e_ethtool_ops;
4748
4749         netdev->vlan_features    |= NETIF_F_SG;
4750         netdev->vlan_features    |= NETIF_F_HW_CSUM;
4751         netdev->vlan_features    |= NETIF_F_GRO;
4752         netdev->vlan_features    |= NETIF_F_TSO;
4753         netdev->vlan_features    |= NETIF_F_TSO6;
4754         netdev->vlan_features    |= NETIF_F_RXCSUM;
4755         netdev->vlan_features    |= NETIF_F_RXHASH;
4756
4757         netdev->mpls_features    |= NETIF_F_SG;
4758         netdev->mpls_features    |= NETIF_F_HW_CSUM;
4759         netdev->mpls_features    |= NETIF_F_TSO;
4760         netdev->mpls_features    |= NETIF_F_TSO6;
4761
4762         netdev->hw_enc_features  |= NETIF_F_HW_VLAN_CTAG_TX;
4763         netdev->hw_enc_features  |= NETIF_F_HW_VLAN_CTAG_RX;
4764
4765         /* Tunneled LRO is not supported in the driver, and the same RQs are
4766          * shared between inner and outer TIRs, so the driver can't disable LRO
4767          * for inner TIRs while having it enabled for outer TIRs. Due to this,
4768          * block LRO altogether if the firmware declares tunneled LRO support.
4769          */
4770         if (!!MLX5_CAP_ETH(mdev, lro_cap) &&
4771             !MLX5_CAP_ETH(mdev, tunnel_lro_vxlan) &&
4772             !MLX5_CAP_ETH(mdev, tunnel_lro_gre) &&
4773             mlx5e_check_fragmented_striding_rq_cap(mdev))
4774                 netdev->vlan_features    |= NETIF_F_LRO;
4775
4776         netdev->hw_features       = netdev->vlan_features;
4777         netdev->hw_features      |= NETIF_F_HW_VLAN_CTAG_TX;
4778         netdev->hw_features      |= NETIF_F_HW_VLAN_CTAG_RX;
4779         netdev->hw_features      |= NETIF_F_HW_VLAN_CTAG_FILTER;
4780         netdev->hw_features      |= NETIF_F_HW_VLAN_STAG_TX;
4781
4782         if (mlx5e_tunnel_any_tx_proto_supported(mdev)) {
4783                 netdev->hw_enc_features |= NETIF_F_HW_CSUM;
4784                 netdev->hw_enc_features |= NETIF_F_TSO;
4785                 netdev->hw_enc_features |= NETIF_F_TSO6;
4786                 netdev->hw_enc_features |= NETIF_F_GSO_PARTIAL;
4787         }
4788
4789         if (mlx5_vxlan_allowed(mdev->vxlan) || mlx5_geneve_tx_allowed(mdev)) {
4790                 netdev->hw_features     |= NETIF_F_GSO_UDP_TUNNEL;
4791                 netdev->hw_enc_features |= NETIF_F_GSO_UDP_TUNNEL;
4792                 netdev->vlan_features |= NETIF_F_GSO_UDP_TUNNEL;
4793         }
4794
4795         if (mlx5e_tunnel_proto_supported_tx(mdev, IPPROTO_GRE)) {
4796                 netdev->hw_features     |= NETIF_F_GSO_GRE;
4797                 netdev->hw_enc_features |= NETIF_F_GSO_GRE;
4798                 netdev->gso_partial_features |= NETIF_F_GSO_GRE;
4799         }
4800
4801         if (mlx5e_tunnel_proto_supported_tx(mdev, IPPROTO_IPIP)) {
4802                 netdev->hw_features |= NETIF_F_GSO_IPXIP4 |
4803                                        NETIF_F_GSO_IPXIP6;
4804                 netdev->hw_enc_features |= NETIF_F_GSO_IPXIP4 |
4805                                            NETIF_F_GSO_IPXIP6;
4806                 netdev->gso_partial_features |= NETIF_F_GSO_IPXIP4 |
4807                                                 NETIF_F_GSO_IPXIP6;
4808         }
4809
4810         netdev->hw_features                      |= NETIF_F_GSO_PARTIAL;
4811         netdev->gso_partial_features             |= NETIF_F_GSO_UDP_L4;
4812         netdev->hw_features                      |= NETIF_F_GSO_UDP_L4;
4813         netdev->features                         |= NETIF_F_GSO_UDP_L4;
4814
4815         mlx5_query_port_fcs(mdev, &fcs_supported, &fcs_enabled);
4816
4817         if (fcs_supported)
4818                 netdev->hw_features |= NETIF_F_RXALL;
4819
4820         if (MLX5_CAP_ETH(mdev, scatter_fcs))
4821                 netdev->hw_features |= NETIF_F_RXFCS;
4822
4823         netdev->features          = netdev->hw_features;
4824
4825         /* Defaults */
4826         if (fcs_enabled)
4827                 netdev->features  &= ~NETIF_F_RXALL;
4828         netdev->features  &= ~NETIF_F_LRO;
4829         netdev->features  &= ~NETIF_F_RXFCS;
4830
4831 #define FT_CAP(f) MLX5_CAP_FLOWTABLE(mdev, flow_table_properties_nic_receive.f)
4832         if (FT_CAP(flow_modify_en) &&
4833             FT_CAP(modify_root) &&
4834             FT_CAP(identified_miss_table_mode) &&
4835             FT_CAP(flow_table_modify)) {
4836 #if IS_ENABLED(CONFIG_MLX5_CLS_ACT)
4837                 netdev->hw_features      |= NETIF_F_HW_TC;
4838 #endif
4839 #ifdef CONFIG_MLX5_EN_ARFS
4840                 netdev->hw_features      |= NETIF_F_NTUPLE;
4841 #endif
4842         }
4843         if (mlx5_qos_is_supported(mdev))
4844                 netdev->features |= NETIF_F_HW_TC;
4845
4846         netdev->features         |= NETIF_F_HIGHDMA;
4847         netdev->features         |= NETIF_F_HW_VLAN_STAG_FILTER;
4848
4849         netdev->priv_flags       |= IFF_UNICAST_FLT;
4850
4851         mlx5e_set_netdev_dev_addr(netdev);
4852         mlx5e_ipsec_build_netdev(priv);
4853         mlx5e_tls_build_netdev(priv);
4854 }
4855
4856 void mlx5e_create_q_counters(struct mlx5e_priv *priv)
4857 {
4858         u32 out[MLX5_ST_SZ_DW(alloc_q_counter_out)] = {};
4859         u32 in[MLX5_ST_SZ_DW(alloc_q_counter_in)] = {};
4860         struct mlx5_core_dev *mdev = priv->mdev;
4861         int err;
4862
4863         MLX5_SET(alloc_q_counter_in, in, opcode, MLX5_CMD_OP_ALLOC_Q_COUNTER);
4864         err = mlx5_cmd_exec_inout(mdev, alloc_q_counter, in, out);
4865         if (!err)
4866                 priv->q_counter =
4867                         MLX5_GET(alloc_q_counter_out, out, counter_set_id);
4868
4869         err = mlx5_cmd_exec_inout(mdev, alloc_q_counter, in, out);
4870         if (!err)
4871                 priv->drop_rq_q_counter =
4872                         MLX5_GET(alloc_q_counter_out, out, counter_set_id);
4873 }
4874
4875 void mlx5e_destroy_q_counters(struct mlx5e_priv *priv)
4876 {
4877         u32 in[MLX5_ST_SZ_DW(dealloc_q_counter_in)] = {};
4878
4879         MLX5_SET(dealloc_q_counter_in, in, opcode,
4880                  MLX5_CMD_OP_DEALLOC_Q_COUNTER);
4881         if (priv->q_counter) {
4882                 MLX5_SET(dealloc_q_counter_in, in, counter_set_id,
4883                          priv->q_counter);
4884                 mlx5_cmd_exec_in(priv->mdev, dealloc_q_counter, in);
4885         }
4886
4887         if (priv->drop_rq_q_counter) {
4888                 MLX5_SET(dealloc_q_counter_in, in, counter_set_id,
4889                          priv->drop_rq_q_counter);
4890                 mlx5_cmd_exec_in(priv->mdev, dealloc_q_counter, in);
4891         }
4892 }
4893
4894 static int mlx5e_nic_init(struct mlx5_core_dev *mdev,
4895                           struct net_device *netdev)
4896 {
4897         struct mlx5e_priv *priv = netdev_priv(netdev);
4898         struct devlink_port *dl_port;
4899         int err;
4900
4901         mlx5e_build_nic_params(priv, &priv->xsk, netdev->mtu);
4902         mlx5e_vxlan_set_netdev_info(priv);
4903
4904         mlx5e_timestamp_init(priv);
4905
4906         err = mlx5e_ipsec_init(priv);
4907         if (err)
4908                 mlx5_core_err(mdev, "IPSec initialization failed, %d\n", err);
4909
4910         err = mlx5e_tls_init(priv);
4911         if (err)
4912                 mlx5_core_err(mdev, "TLS initialization failed, %d\n", err);
4913
4914         dl_port = mlx5e_devlink_get_dl_port(priv);
4915         if (dl_port->registered)
4916                 mlx5e_health_create_reporters(priv);
4917
4918         return 0;
4919 }
4920
4921 static void mlx5e_nic_cleanup(struct mlx5e_priv *priv)
4922 {
4923         struct devlink_port *dl_port = mlx5e_devlink_get_dl_port(priv);
4924
4925         if (dl_port->registered)
4926                 mlx5e_health_destroy_reporters(priv);
4927         mlx5e_tls_cleanup(priv);
4928         mlx5e_ipsec_cleanup(priv);
4929 }
4930
4931 static int mlx5e_init_nic_rx(struct mlx5e_priv *priv)
4932 {
4933         struct mlx5_core_dev *mdev = priv->mdev;
4934         int err;
4935
4936         priv->rx_res = kvzalloc(sizeof(*priv->rx_res), GFP_KERNEL);
4937         if (!priv->rx_res)
4938                 return -ENOMEM;
4939
4940         mlx5e_build_rss_params(&priv->rx_res->rss_params, priv->channels.params.num_channels);
4941
4942         mlx5e_create_q_counters(priv);
4943
4944         err = mlx5e_open_drop_rq(priv, &priv->drop_rq);
4945         if (err) {
4946                 mlx5_core_err(mdev, "open drop rq failed, %d\n", err);
4947                 goto err_destroy_q_counters;
4948         }
4949
4950         err = mlx5e_create_indirect_rqt(priv);
4951         if (err)
4952                 goto err_close_drop_rq;
4953
4954         err = mlx5e_create_direct_rqts(priv);
4955         if (err)
4956                 goto err_destroy_indirect_rqts;
4957
4958         err = mlx5e_create_indirect_tirs(priv, true);
4959         if (err)
4960                 goto err_destroy_direct_rqts;
4961
4962         err = mlx5e_create_direct_tirs(priv);
4963         if (err)
4964                 goto err_destroy_indirect_tirs;
4965
4966         err = mlx5e_create_xsk_rqts(priv);
4967         if (unlikely(err))
4968                 goto err_destroy_direct_tirs;
4969
4970         err = mlx5e_create_xsk_tirs(priv);
4971         if (unlikely(err))
4972                 goto err_destroy_xsk_rqts;
4973
4974         err = mlx5e_rqt_init_direct(&priv->rx_res->ptp.rqt, priv->mdev, false,
4975                                     priv->drop_rq.rqn);
4976         if (err)
4977                 goto err_destroy_xsk_tirs;
4978
4979         err = mlx5e_create_direct_tir(priv, &priv->rx_res->ptp.tir, &priv->rx_res->ptp.rqt);
4980         if (err)
4981                 goto err_destroy_ptp_rqt;
4982
4983         err = mlx5e_create_flow_steering(priv);
4984         if (err) {
4985                 mlx5_core_warn(mdev, "create flow steering failed, %d\n", err);
4986                 goto err_destroy_ptp_direct_tir;
4987         }
4988
4989         err = mlx5e_tc_nic_init(priv);
4990         if (err)
4991                 goto err_destroy_flow_steering;
4992
4993         err = mlx5e_accel_init_rx(priv);
4994         if (err)
4995                 goto err_tc_nic_cleanup;
4996
4997 #ifdef CONFIG_MLX5_EN_ARFS
4998         priv->netdev->rx_cpu_rmap =  mlx5_eq_table_get_rmap(priv->mdev);
4999 #endif
5000
5001         return 0;
5002
5003 err_tc_nic_cleanup:
5004         mlx5e_tc_nic_cleanup(priv);
5005 err_destroy_flow_steering:
5006         mlx5e_destroy_flow_steering(priv);
5007 err_destroy_ptp_direct_tir:
5008         mlx5e_destroy_tir(priv->mdev, &priv->rx_res->ptp.tir);
5009 err_destroy_ptp_rqt:
5010         mlx5e_rqt_destroy(&priv->rx_res->ptp.rqt);
5011 err_destroy_xsk_tirs:
5012         mlx5e_destroy_xsk_tirs(priv);
5013 err_destroy_xsk_rqts:
5014         mlx5e_destroy_xsk_rqts(priv);
5015 err_destroy_direct_tirs:
5016         mlx5e_destroy_direct_tirs(priv);
5017 err_destroy_indirect_tirs:
5018         mlx5e_destroy_indirect_tirs(priv);
5019 err_destroy_direct_rqts:
5020         mlx5e_destroy_direct_rqts(priv);
5021 err_destroy_indirect_rqts:
5022         mlx5e_rqt_destroy(&priv->rx_res->indir_rqt);
5023 err_close_drop_rq:
5024         mlx5e_close_drop_rq(&priv->drop_rq);
5025 err_destroy_q_counters:
5026         mlx5e_destroy_q_counters(priv);
5027         kvfree(priv->rx_res);
5028         priv->rx_res = NULL;
5029         return err;
5030 }
5031
5032 static void mlx5e_cleanup_nic_rx(struct mlx5e_priv *priv)
5033 {
5034         mlx5e_accel_cleanup_rx(priv);
5035         mlx5e_tc_nic_cleanup(priv);
5036         mlx5e_destroy_flow_steering(priv);
5037         mlx5e_destroy_tir(priv->mdev, &priv->rx_res->ptp.tir);
5038         mlx5e_rqt_destroy(&priv->rx_res->ptp.rqt);
5039         mlx5e_destroy_xsk_tirs(priv);
5040         mlx5e_destroy_xsk_rqts(priv);
5041         mlx5e_destroy_direct_tirs(priv);
5042         mlx5e_destroy_indirect_tirs(priv);
5043         mlx5e_destroy_direct_rqts(priv);
5044         mlx5e_rqt_destroy(&priv->rx_res->indir_rqt);
5045         mlx5e_close_drop_rq(&priv->drop_rq);
5046         mlx5e_destroy_q_counters(priv);
5047         kvfree(priv->rx_res);
5048         priv->rx_res = NULL;
5049 }
5050
5051 static int mlx5e_init_nic_tx(struct mlx5e_priv *priv)
5052 {
5053         int err;
5054
5055         err = mlx5e_create_tises(priv);
5056         if (err) {
5057                 mlx5_core_warn(priv->mdev, "create tises failed, %d\n", err);
5058                 return err;
5059         }
5060
5061         mlx5e_dcbnl_initialize(priv);
5062         return 0;
5063 }
5064
5065 static void mlx5e_nic_enable(struct mlx5e_priv *priv)
5066 {
5067         struct net_device *netdev = priv->netdev;
5068         struct mlx5_core_dev *mdev = priv->mdev;
5069
5070         mlx5e_init_l2_addr(priv);
5071
5072         /* Marking the link as currently not needed by the Driver */
5073         if (!netif_running(netdev))
5074                 mlx5e_modify_admin_state(mdev, MLX5_PORT_DOWN);
5075
5076         mlx5e_set_netdev_mtu_boundaries(priv);
5077         mlx5e_set_dev_port_mtu(priv);
5078
5079         mlx5_lag_add_netdev(mdev, netdev);
5080
5081         mlx5e_enable_async_events(priv);
5082         mlx5e_enable_blocking_events(priv);
5083         if (mlx5e_monitor_counter_supported(priv))
5084                 mlx5e_monitor_counter_init(priv);
5085
5086         mlx5e_hv_vhca_stats_create(priv);
5087         if (netdev->reg_state != NETREG_REGISTERED)
5088                 return;
5089         mlx5e_dcbnl_init_app(priv);
5090
5091         mlx5e_nic_set_rx_mode(priv);
5092
5093         rtnl_lock();
5094         if (netif_running(netdev))
5095                 mlx5e_open(netdev);
5096         udp_tunnel_nic_reset_ntf(priv->netdev);
5097         netif_device_attach(netdev);
5098         rtnl_unlock();
5099 }
5100
5101 static void mlx5e_nic_disable(struct mlx5e_priv *priv)
5102 {
5103         struct mlx5_core_dev *mdev = priv->mdev;
5104
5105         if (priv->netdev->reg_state == NETREG_REGISTERED)
5106                 mlx5e_dcbnl_delete_app(priv);
5107
5108         rtnl_lock();
5109         if (netif_running(priv->netdev))
5110                 mlx5e_close(priv->netdev);
5111         netif_device_detach(priv->netdev);
5112         rtnl_unlock();
5113
5114         mlx5e_nic_set_rx_mode(priv);
5115
5116         mlx5e_hv_vhca_stats_destroy(priv);
5117         if (mlx5e_monitor_counter_supported(priv))
5118                 mlx5e_monitor_counter_cleanup(priv);
5119
5120         mlx5e_disable_blocking_events(priv);
5121         if (priv->en_trap) {
5122                 mlx5e_deactivate_trap(priv);
5123                 mlx5e_close_trap(priv->en_trap);
5124                 priv->en_trap = NULL;
5125         }
5126         mlx5e_disable_async_events(priv);
5127         mlx5_lag_remove_netdev(mdev, priv->netdev);
5128         mlx5_vxlan_reset_to_default(mdev->vxlan);
5129 }
5130
5131 int mlx5e_update_nic_rx(struct mlx5e_priv *priv)
5132 {
5133         return mlx5e_refresh_tirs(priv, false, false);
5134 }
5135
5136 static const struct mlx5e_profile mlx5e_nic_profile = {
5137         .init              = mlx5e_nic_init,
5138         .cleanup           = mlx5e_nic_cleanup,
5139         .init_rx           = mlx5e_init_nic_rx,
5140         .cleanup_rx        = mlx5e_cleanup_nic_rx,
5141         .init_tx           = mlx5e_init_nic_tx,
5142         .cleanup_tx        = mlx5e_cleanup_nic_tx,
5143         .enable            = mlx5e_nic_enable,
5144         .disable           = mlx5e_nic_disable,
5145         .update_rx         = mlx5e_update_nic_rx,
5146         .update_stats      = mlx5e_stats_update_ndo_stats,
5147         .update_carrier    = mlx5e_update_carrier,
5148         .rx_handlers       = &mlx5e_rx_handlers_nic,
5149         .max_tc            = MLX5E_MAX_NUM_TC,
5150         .rq_groups         = MLX5E_NUM_RQ_GROUPS(XSK),
5151         .stats_grps        = mlx5e_nic_stats_grps,
5152         .stats_grps_num    = mlx5e_nic_stats_grps_num,
5153         .rx_ptp_support    = true,
5154 };
5155
5156 /* mlx5e generic netdev management API (move to en_common.c) */
5157 int mlx5e_priv_init(struct mlx5e_priv *priv,
5158                     struct net_device *netdev,
5159                     struct mlx5_core_dev *mdev)
5160 {
5161         /* priv init */
5162         priv->mdev        = mdev;
5163         priv->netdev      = netdev;
5164         priv->msglevel    = MLX5E_MSG_LEVEL;
5165         priv->max_opened_tc = 1;
5166
5167         if (!alloc_cpumask_var(&priv->scratchpad.cpumask, GFP_KERNEL))
5168                 return -ENOMEM;
5169
5170         mutex_init(&priv->state_lock);
5171         hash_init(priv->htb.qos_tc2node);
5172         INIT_WORK(&priv->update_carrier_work, mlx5e_update_carrier_work);
5173         INIT_WORK(&priv->set_rx_mode_work, mlx5e_set_rx_mode_work);
5174         INIT_WORK(&priv->tx_timeout_work, mlx5e_tx_timeout_work);
5175         INIT_WORK(&priv->update_stats_work, mlx5e_update_stats_work);
5176
5177         priv->wq = create_singlethread_workqueue("mlx5e");
5178         if (!priv->wq)
5179                 goto err_free_cpumask;
5180
5181         return 0;
5182
5183 err_free_cpumask:
5184         free_cpumask_var(priv->scratchpad.cpumask);
5185
5186         return -ENOMEM;
5187 }
5188
5189 void mlx5e_priv_cleanup(struct mlx5e_priv *priv)
5190 {
5191         int i;
5192
5193         /* bail if change profile failed and also rollback failed */
5194         if (!priv->mdev)
5195                 return;
5196
5197         destroy_workqueue(priv->wq);
5198         free_cpumask_var(priv->scratchpad.cpumask);
5199
5200         for (i = 0; i < priv->htb.max_qos_sqs; i++)
5201                 kfree(priv->htb.qos_sq_stats[i]);
5202         kvfree(priv->htb.qos_sq_stats);
5203
5204         memset(priv, 0, sizeof(*priv));
5205 }
5206
5207 struct net_device *
5208 mlx5e_create_netdev(struct mlx5_core_dev *mdev, unsigned int txqs, unsigned int rxqs)
5209 {
5210         struct net_device *netdev;
5211         int err;
5212
5213         netdev = alloc_etherdev_mqs(sizeof(struct mlx5e_priv), txqs, rxqs);
5214         if (!netdev) {
5215                 mlx5_core_err(mdev, "alloc_etherdev_mqs() failed\n");
5216                 return NULL;
5217         }
5218
5219         err = mlx5e_priv_init(netdev_priv(netdev), netdev, mdev);
5220         if (err) {
5221                 mlx5_core_err(mdev, "mlx5e_priv_init failed, err=%d\n", err);
5222                 goto err_free_netdev;
5223         }
5224
5225         netif_carrier_off(netdev);
5226         dev_net_set(netdev, mlx5_core_net(mdev));
5227
5228         return netdev;
5229
5230 err_free_netdev:
5231         free_netdev(netdev);
5232
5233         return NULL;
5234 }
5235
5236 static void mlx5e_update_features(struct net_device *netdev)
5237 {
5238         if (netdev->reg_state != NETREG_REGISTERED)
5239                 return; /* features will be updated on netdev registration */
5240
5241         rtnl_lock();
5242         netdev_update_features(netdev);
5243         rtnl_unlock();
5244 }
5245
5246 static void mlx5e_reset_channels(struct net_device *netdev)
5247 {
5248         netdev_reset_tc(netdev);
5249 }
5250
5251 int mlx5e_attach_netdev(struct mlx5e_priv *priv)
5252 {
5253         const bool take_rtnl = priv->netdev->reg_state == NETREG_REGISTERED;
5254         const struct mlx5e_profile *profile = priv->profile;
5255         int max_nch;
5256         int err;
5257
5258         clear_bit(MLX5E_STATE_DESTROYING, &priv->state);
5259
5260         /* max number of channels may have changed */
5261         max_nch = mlx5e_get_max_num_channels(priv->mdev);
5262         if (priv->channels.params.num_channels > max_nch) {
5263                 mlx5_core_warn(priv->mdev, "MLX5E: Reducing number of channels to %d\n", max_nch);
5264                 /* Reducing the number of channels - RXFH has to be reset, and
5265                  * mlx5e_num_channels_changed below will build the RQT.
5266                  */
5267                 priv->netdev->priv_flags &= ~IFF_RXFH_CONFIGURED;
5268                 priv->channels.params.num_channels = max_nch;
5269         }
5270         /* 1. Set the real number of queues in the kernel the first time.
5271          * 2. Set our default XPS cpumask.
5272          * 3. Build the RQT.
5273          *
5274          * rtnl_lock is required by netif_set_real_num_*_queues in case the
5275          * netdev has been registered by this point (if this function was called
5276          * in the reload or resume flow).
5277          */
5278         if (take_rtnl)
5279                 rtnl_lock();
5280         err = mlx5e_num_channels_changed(priv);
5281         if (take_rtnl)
5282                 rtnl_unlock();
5283         if (err)
5284                 goto out;
5285
5286         err = profile->init_tx(priv);
5287         if (err)
5288                 goto out;
5289
5290         err = profile->init_rx(priv);
5291         if (err)
5292                 goto err_cleanup_tx;
5293
5294         if (profile->enable)
5295                 profile->enable(priv);
5296
5297         mlx5e_update_features(priv->netdev);
5298
5299         return 0;
5300
5301 err_cleanup_tx:
5302         profile->cleanup_tx(priv);
5303
5304 out:
5305         mlx5e_reset_channels(priv->netdev);
5306         set_bit(MLX5E_STATE_DESTROYING, &priv->state);
5307         cancel_work_sync(&priv->update_stats_work);
5308         return err;
5309 }
5310
5311 void mlx5e_detach_netdev(struct mlx5e_priv *priv)
5312 {
5313         const struct mlx5e_profile *profile = priv->profile;
5314
5315         set_bit(MLX5E_STATE_DESTROYING, &priv->state);
5316
5317         if (profile->disable)
5318                 profile->disable(priv);
5319         flush_workqueue(priv->wq);
5320
5321         profile->cleanup_rx(priv);
5322         profile->cleanup_tx(priv);
5323         mlx5e_reset_channels(priv->netdev);
5324         cancel_work_sync(&priv->update_stats_work);
5325 }
5326
5327 static int
5328 mlx5e_netdev_attach_profile(struct net_device *netdev, struct mlx5_core_dev *mdev,
5329                             const struct mlx5e_profile *new_profile, void *new_ppriv)
5330 {
5331         struct mlx5e_priv *priv = netdev_priv(netdev);
5332         int err;
5333
5334         err = mlx5e_priv_init(priv, netdev, mdev);
5335         if (err) {
5336                 mlx5_core_err(mdev, "mlx5e_priv_init failed, err=%d\n", err);
5337                 return err;
5338         }
5339         netif_carrier_off(netdev);
5340         priv->profile = new_profile;
5341         priv->ppriv = new_ppriv;
5342         err = new_profile->init(priv->mdev, priv->netdev);
5343         if (err)
5344                 goto priv_cleanup;
5345         err = mlx5e_attach_netdev(priv);
5346         if (err)
5347                 goto profile_cleanup;
5348         return err;
5349
5350 profile_cleanup:
5351         new_profile->cleanup(priv);
5352 priv_cleanup:
5353         mlx5e_priv_cleanup(priv);
5354         return err;
5355 }
5356
5357 int mlx5e_netdev_change_profile(struct mlx5e_priv *priv,
5358                                 const struct mlx5e_profile *new_profile, void *new_ppriv)
5359 {
5360         unsigned int new_max_nch = mlx5e_calc_max_nch(priv, new_profile);
5361         const struct mlx5e_profile *orig_profile = priv->profile;
5362         struct net_device *netdev = priv->netdev;
5363         struct mlx5_core_dev *mdev = priv->mdev;
5364         void *orig_ppriv = priv->ppriv;
5365         int err, rollback_err;
5366
5367         /* sanity */
5368         if (new_max_nch != priv->max_nch) {
5369                 netdev_warn(netdev, "%s: Replacing profile with different max channels\n",
5370                             __func__);
5371                 return -EINVAL;
5372         }
5373
5374         /* cleanup old profile */
5375         mlx5e_detach_netdev(priv);
5376         priv->profile->cleanup(priv);
5377         mlx5e_priv_cleanup(priv);
5378
5379         err = mlx5e_netdev_attach_profile(netdev, mdev, new_profile, new_ppriv);
5380         if (err) { /* roll back to original profile */
5381                 netdev_warn(netdev, "%s: new profile init failed, %d\n", __func__, err);
5382                 goto rollback;
5383         }
5384
5385         return 0;
5386
5387 rollback:
5388         rollback_err = mlx5e_netdev_attach_profile(netdev, mdev, orig_profile, orig_ppriv);
5389         if (rollback_err)
5390                 netdev_err(netdev, "%s: failed to rollback to orig profile, %d\n",
5391                            __func__, rollback_err);
5392         return err;
5393 }
5394
5395 void mlx5e_netdev_attach_nic_profile(struct mlx5e_priv *priv)
5396 {
5397         mlx5e_netdev_change_profile(priv, &mlx5e_nic_profile, NULL);
5398 }
5399
5400 void mlx5e_destroy_netdev(struct mlx5e_priv *priv)
5401 {
5402         struct net_device *netdev = priv->netdev;
5403
5404         mlx5e_priv_cleanup(priv);
5405         free_netdev(netdev);
5406 }
5407
5408 static int mlx5e_resume(struct auxiliary_device *adev)
5409 {
5410         struct mlx5_adev *edev = container_of(adev, struct mlx5_adev, adev);
5411         struct mlx5e_priv *priv = dev_get_drvdata(&adev->dev);
5412         struct net_device *netdev = priv->netdev;
5413         struct mlx5_core_dev *mdev = edev->mdev;
5414         int err;
5415
5416         if (netif_device_present(netdev))
5417                 return 0;
5418
5419         err = mlx5e_create_mdev_resources(mdev);
5420         if (err)
5421                 return err;
5422
5423         err = mlx5e_attach_netdev(priv);
5424         if (err) {
5425                 mlx5e_destroy_mdev_resources(mdev);
5426                 return err;
5427         }
5428
5429         return 0;
5430 }
5431
5432 static int mlx5e_suspend(struct auxiliary_device *adev, pm_message_t state)
5433 {
5434         struct mlx5e_priv *priv = dev_get_drvdata(&adev->dev);
5435         struct net_device *netdev = priv->netdev;
5436         struct mlx5_core_dev *mdev = priv->mdev;
5437
5438         if (!netif_device_present(netdev))
5439                 return -ENODEV;
5440
5441         mlx5e_detach_netdev(priv);
5442         mlx5e_destroy_mdev_resources(mdev);
5443         return 0;
5444 }
5445
5446 static int mlx5e_probe(struct auxiliary_device *adev,
5447                        const struct auxiliary_device_id *id)
5448 {
5449         struct mlx5_adev *edev = container_of(adev, struct mlx5_adev, adev);
5450         const struct mlx5e_profile *profile = &mlx5e_nic_profile;
5451         struct mlx5_core_dev *mdev = edev->mdev;
5452         struct net_device *netdev;
5453         pm_message_t state = {};
5454         unsigned int txqs, rxqs, ptp_txqs = 0;
5455         struct mlx5e_priv *priv;
5456         int qos_sqs = 0;
5457         int err;
5458         int nch;
5459
5460         if (MLX5_CAP_GEN(mdev, ts_cqe_to_dest_cqn))
5461                 ptp_txqs = profile->max_tc;
5462
5463         if (mlx5_qos_is_supported(mdev))
5464                 qos_sqs = mlx5e_qos_max_leaf_nodes(mdev);
5465
5466         nch = mlx5e_get_max_num_channels(mdev);
5467         txqs = nch * profile->max_tc + ptp_txqs + qos_sqs;
5468         rxqs = nch * profile->rq_groups;
5469         netdev = mlx5e_create_netdev(mdev, txqs, rxqs);
5470         if (!netdev) {
5471                 mlx5_core_err(mdev, "mlx5e_create_netdev failed\n");
5472                 return -ENOMEM;
5473         }
5474
5475         mlx5e_build_nic_netdev(netdev);
5476
5477         priv = netdev_priv(netdev);
5478         dev_set_drvdata(&adev->dev, priv);
5479
5480         priv->profile = profile;
5481         priv->ppriv = NULL;
5482
5483         err = mlx5e_devlink_port_register(priv);
5484         if (err) {
5485                 mlx5_core_err(mdev, "mlx5e_devlink_port_register failed, %d\n", err);
5486                 goto err_destroy_netdev;
5487         }
5488
5489         err = profile->init(mdev, netdev);
5490         if (err) {
5491                 mlx5_core_err(mdev, "mlx5e_nic_profile init failed, %d\n", err);
5492                 goto err_devlink_cleanup;
5493         }
5494
5495         err = mlx5e_resume(adev);
5496         if (err) {
5497                 mlx5_core_err(mdev, "mlx5e_resume failed, %d\n", err);
5498                 goto err_profile_cleanup;
5499         }
5500
5501         err = register_netdev(netdev);
5502         if (err) {
5503                 mlx5_core_err(mdev, "register_netdev failed, %d\n", err);
5504                 goto err_resume;
5505         }
5506
5507         mlx5e_devlink_port_type_eth_set(priv);
5508
5509         mlx5e_dcbnl_init_app(priv);
5510         mlx5_uplink_netdev_set(mdev, netdev);
5511         return 0;
5512
5513 err_resume:
5514         mlx5e_suspend(adev, state);
5515 err_profile_cleanup:
5516         profile->cleanup(priv);
5517 err_devlink_cleanup:
5518         mlx5e_devlink_port_unregister(priv);
5519 err_destroy_netdev:
5520         mlx5e_destroy_netdev(priv);
5521         return err;
5522 }
5523
5524 static void mlx5e_remove(struct auxiliary_device *adev)
5525 {
5526         struct mlx5e_priv *priv = dev_get_drvdata(&adev->dev);
5527         pm_message_t state = {};
5528
5529         mlx5e_dcbnl_delete_app(priv);
5530         unregister_netdev(priv->netdev);
5531         mlx5e_suspend(adev, state);
5532         priv->profile->cleanup(priv);
5533         mlx5e_devlink_port_unregister(priv);
5534         mlx5e_destroy_netdev(priv);
5535 }
5536
5537 static const struct auxiliary_device_id mlx5e_id_table[] = {
5538         { .name = MLX5_ADEV_NAME ".eth", },
5539         {},
5540 };
5541
5542 MODULE_DEVICE_TABLE(auxiliary, mlx5e_id_table);
5543
5544 static struct auxiliary_driver mlx5e_driver = {
5545         .name = "eth",
5546         .probe = mlx5e_probe,
5547         .remove = mlx5e_remove,
5548         .suspend = mlx5e_suspend,
5549         .resume = mlx5e_resume,
5550         .id_table = mlx5e_id_table,
5551 };
5552
5553 int mlx5e_init(void)
5554 {
5555         int ret;
5556
5557         mlx5e_ipsec_build_inverse_table();
5558         mlx5e_build_ptys2ethtool_map();
5559         ret = auxiliary_driver_register(&mlx5e_driver);
5560         if (ret)
5561                 return ret;
5562
5563         ret = mlx5e_rep_init();
5564         if (ret)
5565                 auxiliary_driver_unregister(&mlx5e_driver);
5566         return ret;
5567 }
5568
5569 void mlx5e_cleanup(void)
5570 {
5571         mlx5e_rep_cleanup();
5572         auxiliary_driver_unregister(&mlx5e_driver);
5573 }