2 * Copyright (c) 2015-2016, Mellanox Technologies. All rights reserved.
4 * This software is available to you under a choice of one of two
5 * licenses. You may choose to be licensed under the terms of the GNU
6 * General Public License (GPL) Version 2, available from the file
7 * COPYING in the main directory of this source tree, or the
8 * OpenIB.org BSD license below:
10 * Redistribution and use in source and binary forms, with or
11 * without modification, are permitted provided that the following
14 * - Redistributions of source code must retain the above
15 * copyright notice, this list of conditions and the following
18 * - Redistributions in binary form must reproduce the above
19 * copyright notice, this list of conditions and the following
20 * disclaimer in the documentation and/or other materials
21 * provided with the distribution.
23 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
24 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
25 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
26 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
27 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
28 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
29 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
33 #include <net/tc_act/tc_gact.h>
34 #include <net/pkt_cls.h>
35 #include <linux/mlx5/fs.h>
36 #include <net/vxlan.h>
37 #include <net/geneve.h>
38 #include <linux/bpf.h>
39 #include <linux/if_bridge.h>
40 #include <net/page_pool.h>
41 #include <net/xdp_sock_drv.h>
47 #include "en_accel/ipsec.h"
48 #include "en_accel/ipsec_rxtx.h"
49 #include "en_accel/en_accel.h"
50 #include "en_accel/tls.h"
51 #include "accel/ipsec.h"
52 #include "accel/tls.h"
53 #include "lib/vxlan.h"
54 #include "lib/clock.h"
58 #include "en/monitor_stats.h"
59 #include "en/health.h"
60 #include "en/params.h"
61 #include "en/xsk/umem.h"
62 #include "en/xsk/setup.h"
63 #include "en/xsk/rx.h"
64 #include "en/xsk/tx.h"
65 #include "en/hv_vhca_stats.h"
66 #include "en/devlink.h"
69 bool mlx5e_check_fragmented_striding_rq_cap(struct mlx5_core_dev *mdev)
71 bool striding_rq_umr = MLX5_CAP_GEN(mdev, striding_rq) &&
72 MLX5_CAP_GEN(mdev, umr_ptr_rlky) &&
73 MLX5_CAP_ETH(mdev, reg_umr_sq);
74 u16 max_wqe_sz_cap = MLX5_CAP_GEN(mdev, max_wqe_sz_sq);
75 bool inline_umr = MLX5E_UMR_WQE_INLINE_SZ <= max_wqe_sz_cap;
80 mlx5_core_warn(mdev, "Cannot support Striding RQ: UMR WQE size (%d) exceeds maximum supported (%d).\n",
81 (int)MLX5E_UMR_WQE_INLINE_SZ, max_wqe_sz_cap);
87 void mlx5e_init_rq_type_params(struct mlx5_core_dev *mdev,
88 struct mlx5e_params *params)
90 params->log_rq_mtu_frames = is_kdump_kernel() ?
91 MLX5E_PARAMS_MINIMUM_LOG_RQ_SIZE :
92 MLX5E_PARAMS_DEFAULT_LOG_RQ_SIZE;
94 mlx5_core_info(mdev, "MLX5E: StrdRq(%d) RqSz(%ld) StrdSz(%ld) RxCqeCmprss(%d)\n",
95 params->rq_wq_type == MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ,
96 params->rq_wq_type == MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ ?
97 BIT(mlx5e_mpwqe_get_log_rq_size(params, NULL)) :
98 BIT(params->log_rq_mtu_frames),
99 BIT(mlx5e_mpwqe_get_log_stride_size(mdev, params, NULL)),
100 MLX5E_GET_PFLAG(params, MLX5E_PFLAG_RX_CQE_COMPRESS));
103 bool mlx5e_striding_rq_possible(struct mlx5_core_dev *mdev,
104 struct mlx5e_params *params)
106 if (!mlx5e_check_fragmented_striding_rq_cap(mdev))
109 if (MLX5_IPSEC_DEV(mdev))
112 if (params->xdp_prog) {
113 /* XSK params are not considered here. If striding RQ is in use,
114 * and an XSK is being opened, mlx5e_rx_mpwqe_is_linear_skb will
115 * be called with the known XSK params.
117 if (!mlx5e_rx_mpwqe_is_linear_skb(mdev, params, NULL))
124 void mlx5e_set_rq_type(struct mlx5_core_dev *mdev, struct mlx5e_params *params)
126 params->rq_wq_type = mlx5e_striding_rq_possible(mdev, params) &&
127 MLX5E_GET_PFLAG(params, MLX5E_PFLAG_RX_STRIDING_RQ) ?
128 MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ :
132 void mlx5e_update_carrier(struct mlx5e_priv *priv)
134 struct mlx5_core_dev *mdev = priv->mdev;
137 port_state = mlx5_query_vport_state(mdev,
138 MLX5_VPORT_STATE_OP_MOD_VNIC_VPORT,
141 if (port_state == VPORT_STATE_UP) {
142 netdev_info(priv->netdev, "Link up\n");
143 netif_carrier_on(priv->netdev);
145 netdev_info(priv->netdev, "Link down\n");
146 netif_carrier_off(priv->netdev);
150 static void mlx5e_update_carrier_work(struct work_struct *work)
152 struct mlx5e_priv *priv = container_of(work, struct mlx5e_priv,
153 update_carrier_work);
155 mutex_lock(&priv->state_lock);
156 if (test_bit(MLX5E_STATE_OPENED, &priv->state))
157 if (priv->profile->update_carrier)
158 priv->profile->update_carrier(priv);
159 mutex_unlock(&priv->state_lock);
162 void mlx5e_update_ndo_stats(struct mlx5e_priv *priv)
166 for (i = mlx5e_nic_stats_grps_num(priv) - 1; i >= 0; i--)
167 if (mlx5e_nic_stats_grps[i]->update_stats_mask &
168 MLX5E_NDO_UPDATE_STATS)
169 mlx5e_nic_stats_grps[i]->update_stats(priv);
172 static void mlx5e_update_stats_work(struct work_struct *work)
174 struct mlx5e_priv *priv = container_of(work, struct mlx5e_priv,
177 mutex_lock(&priv->state_lock);
178 priv->profile->update_stats(priv);
179 mutex_unlock(&priv->state_lock);
182 void mlx5e_queue_update_stats(struct mlx5e_priv *priv)
184 if (!priv->profile->update_stats)
187 if (unlikely(test_bit(MLX5E_STATE_DESTROYING, &priv->state)))
190 queue_work(priv->wq, &priv->update_stats_work);
193 static int async_event(struct notifier_block *nb, unsigned long event, void *data)
195 struct mlx5e_priv *priv = container_of(nb, struct mlx5e_priv, events_nb);
196 struct mlx5_eqe *eqe = data;
198 if (event != MLX5_EVENT_TYPE_PORT_CHANGE)
201 switch (eqe->sub_type) {
202 case MLX5_PORT_CHANGE_SUBTYPE_DOWN:
203 case MLX5_PORT_CHANGE_SUBTYPE_ACTIVE:
204 queue_work(priv->wq, &priv->update_carrier_work);
213 static void mlx5e_enable_async_events(struct mlx5e_priv *priv)
215 priv->events_nb.notifier_call = async_event;
216 mlx5_notifier_register(priv->mdev, &priv->events_nb);
219 static void mlx5e_disable_async_events(struct mlx5e_priv *priv)
221 mlx5_notifier_unregister(priv->mdev, &priv->events_nb);
224 static inline void mlx5e_build_umr_wqe(struct mlx5e_rq *rq,
225 struct mlx5e_icosq *sq,
226 struct mlx5e_umr_wqe *wqe)
228 struct mlx5_wqe_ctrl_seg *cseg = &wqe->ctrl;
229 struct mlx5_wqe_umr_ctrl_seg *ucseg = &wqe->uctrl;
230 u8 ds_cnt = DIV_ROUND_UP(MLX5E_UMR_WQE_INLINE_SZ, MLX5_SEND_WQE_DS);
232 cseg->qpn_ds = cpu_to_be32((sq->sqn << MLX5_WQE_CTRL_QPN_SHIFT) |
234 cseg->fm_ce_se = MLX5_WQE_CTRL_CQ_UPDATE;
235 cseg->umr_mkey = rq->mkey_be;
237 ucseg->flags = MLX5_UMR_TRANSLATION_OFFSET_EN | MLX5_UMR_INLINE;
238 ucseg->xlt_octowords =
239 cpu_to_be16(MLX5_MTT_OCTW(MLX5_MPWRQ_PAGES_PER_WQE));
240 ucseg->mkey_mask = cpu_to_be64(MLX5_MKEY_MASK_FREE);
243 static int mlx5e_rq_alloc_mpwqe_info(struct mlx5e_rq *rq,
244 struct mlx5e_channel *c)
246 int wq_sz = mlx5_wq_ll_get_size(&rq->mpwqe.wq);
248 rq->mpwqe.info = kvzalloc_node(array_size(wq_sz,
249 sizeof(*rq->mpwqe.info)),
250 GFP_KERNEL, cpu_to_node(c->cpu));
254 mlx5e_build_umr_wqe(rq, &c->icosq, &rq->mpwqe.umr_wqe);
259 static int mlx5e_create_umr_mkey(struct mlx5_core_dev *mdev,
260 u64 npages, u8 page_shift,
261 struct mlx5_core_mkey *umr_mkey)
263 int inlen = MLX5_ST_SZ_BYTES(create_mkey_in);
268 in = kvzalloc(inlen, GFP_KERNEL);
272 mkc = MLX5_ADDR_OF(create_mkey_in, in, memory_key_mkey_entry);
274 MLX5_SET(mkc, mkc, free, 1);
275 MLX5_SET(mkc, mkc, umr_en, 1);
276 MLX5_SET(mkc, mkc, lw, 1);
277 MLX5_SET(mkc, mkc, lr, 1);
278 MLX5_SET(mkc, mkc, access_mode_1_0, MLX5_MKC_ACCESS_MODE_MTT);
280 MLX5_SET(mkc, mkc, qpn, 0xffffff);
281 MLX5_SET(mkc, mkc, pd, mdev->mlx5e_res.pdn);
282 MLX5_SET64(mkc, mkc, len, npages << page_shift);
283 MLX5_SET(mkc, mkc, translations_octword_size,
284 MLX5_MTT_OCTW(npages));
285 MLX5_SET(mkc, mkc, log_page_size, page_shift);
287 err = mlx5_core_create_mkey(mdev, umr_mkey, in, inlen);
293 static int mlx5e_create_rq_umr_mkey(struct mlx5_core_dev *mdev, struct mlx5e_rq *rq)
295 u64 num_mtts = MLX5E_REQUIRED_MTTS(mlx5_wq_ll_get_size(&rq->mpwqe.wq));
297 return mlx5e_create_umr_mkey(mdev, num_mtts, PAGE_SHIFT, &rq->umr_mkey);
300 static inline u64 mlx5e_get_mpwqe_offset(struct mlx5e_rq *rq, u16 wqe_ix)
302 return (wqe_ix << MLX5E_LOG_ALIGNED_MPWQE_PPW) << PAGE_SHIFT;
305 static void mlx5e_init_frags_partition(struct mlx5e_rq *rq)
307 struct mlx5e_wqe_frag_info next_frag = {};
308 struct mlx5e_wqe_frag_info *prev = NULL;
311 next_frag.di = &rq->wqe.di[0];
313 for (i = 0; i < mlx5_wq_cyc_get_size(&rq->wqe.wq); i++) {
314 struct mlx5e_rq_frag_info *frag_info = &rq->wqe.info.arr[0];
315 struct mlx5e_wqe_frag_info *frag =
316 &rq->wqe.frags[i << rq->wqe.info.log_num_frags];
319 for (f = 0; f < rq->wqe.info.num_frags; f++, frag++) {
320 if (next_frag.offset + frag_info[f].frag_stride > PAGE_SIZE) {
322 next_frag.offset = 0;
324 prev->last_in_page = true;
329 next_frag.offset += frag_info[f].frag_stride;
335 prev->last_in_page = true;
338 static int mlx5e_init_di_list(struct mlx5e_rq *rq,
341 int len = wq_sz << rq->wqe.info.log_num_frags;
343 rq->wqe.di = kvzalloc_node(array_size(len, sizeof(*rq->wqe.di)),
344 GFP_KERNEL, cpu_to_node(cpu));
348 mlx5e_init_frags_partition(rq);
353 static void mlx5e_free_di_list(struct mlx5e_rq *rq)
358 static void mlx5e_rq_err_cqe_work(struct work_struct *recover_work)
360 struct mlx5e_rq *rq = container_of(recover_work, struct mlx5e_rq, recover_work);
362 mlx5e_reporter_rq_cqe_err(rq);
365 static int mlx5e_alloc_rq(struct mlx5e_channel *c,
366 struct mlx5e_params *params,
367 struct mlx5e_xsk_param *xsk,
368 struct xdp_umem *umem,
369 struct mlx5e_rq_param *rqp,
372 struct page_pool_params pp_params = { 0 };
373 struct mlx5_core_dev *mdev = c->mdev;
374 void *rqc = rqp->rqc;
375 void *rqc_wq = MLX5_ADDR_OF(rqc, rqc, wq);
382 rqp->wq.db_numa_node = cpu_to_node(c->cpu);
384 rq->wq_type = params->rq_wq_type;
386 rq->netdev = c->netdev;
387 rq->tstamp = c->tstamp;
388 rq->clock = &mdev->clock;
392 rq->hw_mtu = MLX5E_SW2HW_MTU(params, params->sw_mtu);
393 rq->xdpsq = &c->rq_xdpsq;
397 rq->stats = &c->priv->channel_stats[c->ix].xskrq;
399 rq->stats = &c->priv->channel_stats[c->ix].rq;
400 INIT_WORK(&rq->recover_work, mlx5e_rq_err_cqe_work);
402 if (params->xdp_prog)
403 bpf_prog_inc(params->xdp_prog);
404 rq->xdp_prog = params->xdp_prog;
408 rq_xdp_ix += params->num_channels * MLX5E_RQ_GROUP_XSK;
409 err = xdp_rxq_info_reg(&rq->xdp_rxq, rq->netdev, rq_xdp_ix);
411 goto err_rq_wq_destroy;
413 rq->buff.map_dir = rq->xdp_prog ? DMA_BIDIRECTIONAL : DMA_FROM_DEVICE;
414 rq->buff.headroom = mlx5e_get_rq_headroom(mdev, params, xsk);
415 pool_size = 1 << params->log_rq_mtu_frames;
417 switch (rq->wq_type) {
418 case MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ:
419 err = mlx5_wq_ll_create(mdev, &rqp->wq, rqc_wq, &rq->mpwqe.wq,
424 rq->mpwqe.wq.db = &rq->mpwqe.wq.db[MLX5_RCV_DBR];
426 wq_sz = mlx5_wq_ll_get_size(&rq->mpwqe.wq);
428 pool_size = MLX5_MPWRQ_PAGES_PER_WQE <<
429 mlx5e_mpwqe_get_log_rq_size(params, xsk);
431 rq->post_wqes = mlx5e_post_rx_mpwqes;
432 rq->dealloc_wqe = mlx5e_dealloc_rx_mpwqe;
434 rq->handle_rx_cqe = c->priv->profile->rx_handlers.handle_rx_cqe_mpwqe;
435 #ifdef CONFIG_MLX5_EN_IPSEC
436 if (MLX5_IPSEC_DEV(mdev)) {
438 netdev_err(c->netdev, "MPWQE RQ with IPSec offload not supported\n");
439 goto err_rq_wq_destroy;
442 if (!rq->handle_rx_cqe) {
444 netdev_err(c->netdev, "RX handler of MPWQE RQ is not set, err %d\n", err);
445 goto err_rq_wq_destroy;
448 rq->mpwqe.skb_from_cqe_mpwrq = xsk ?
449 mlx5e_xsk_skb_from_cqe_mpwrq_linear :
450 mlx5e_rx_mpwqe_is_linear_skb(mdev, params, NULL) ?
451 mlx5e_skb_from_cqe_mpwrq_linear :
452 mlx5e_skb_from_cqe_mpwrq_nonlinear;
454 rq->mpwqe.log_stride_sz = mlx5e_mpwqe_get_log_stride_size(mdev, params, xsk);
455 rq->mpwqe.num_strides =
456 BIT(mlx5e_mpwqe_get_log_num_strides(mdev, params, xsk));
458 rq->buff.frame0_sz = (1 << rq->mpwqe.log_stride_sz);
460 err = mlx5e_create_rq_umr_mkey(mdev, rq);
462 goto err_rq_wq_destroy;
463 rq->mkey_be = cpu_to_be32(rq->umr_mkey.key);
465 err = mlx5e_rq_alloc_mpwqe_info(rq, c);
469 default: /* MLX5_WQ_TYPE_CYCLIC */
470 err = mlx5_wq_cyc_create(mdev, &rqp->wq, rqc_wq, &rq->wqe.wq,
475 rq->wqe.wq.db = &rq->wqe.wq.db[MLX5_RCV_DBR];
477 wq_sz = mlx5_wq_cyc_get_size(&rq->wqe.wq);
479 rq->wqe.info = rqp->frags_info;
480 rq->buff.frame0_sz = rq->wqe.info.arr[0].frag_stride;
483 kvzalloc_node(array_size(sizeof(*rq->wqe.frags),
484 (wq_sz << rq->wqe.info.log_num_frags)),
485 GFP_KERNEL, cpu_to_node(c->cpu));
486 if (!rq->wqe.frags) {
491 err = mlx5e_init_di_list(rq, wq_sz, c->cpu);
495 rq->post_wqes = mlx5e_post_rx_wqes;
496 rq->dealloc_wqe = mlx5e_dealloc_rx_wqe;
498 #ifdef CONFIG_MLX5_EN_IPSEC
500 rq->handle_rx_cqe = mlx5e_ipsec_handle_rx_cqe;
503 rq->handle_rx_cqe = c->priv->profile->rx_handlers.handle_rx_cqe;
504 if (!rq->handle_rx_cqe) {
506 netdev_err(c->netdev, "RX handler of RQ is not set, err %d\n", err);
510 rq->wqe.skb_from_cqe = xsk ?
511 mlx5e_xsk_skb_from_cqe_linear :
512 mlx5e_rx_is_linear_skb(params, NULL) ?
513 mlx5e_skb_from_cqe_linear :
514 mlx5e_skb_from_cqe_nonlinear;
515 rq->mkey_be = c->mkey_be;
519 err = xdp_rxq_info_reg_mem_model(&rq->xdp_rxq,
520 MEM_TYPE_XSK_BUFF_POOL, NULL);
521 xsk_buff_set_rxq_info(rq->umem, &rq->xdp_rxq);
523 /* Create a page_pool and register it with rxq */
525 pp_params.flags = 0; /* No-internal DMA mapping in page_pool */
526 pp_params.pool_size = pool_size;
527 pp_params.nid = cpu_to_node(c->cpu);
528 pp_params.dev = c->pdev;
529 pp_params.dma_dir = rq->buff.map_dir;
531 /* page_pool can be used even when there is no rq->xdp_prog,
532 * given page_pool does not handle DMA mapping there is no
533 * required state to clear. And page_pool gracefully handle
536 rq->page_pool = page_pool_create(&pp_params);
537 if (IS_ERR(rq->page_pool)) {
538 err = PTR_ERR(rq->page_pool);
539 rq->page_pool = NULL;
542 err = xdp_rxq_info_reg_mem_model(&rq->xdp_rxq,
543 MEM_TYPE_PAGE_POOL, rq->page_pool);
548 for (i = 0; i < wq_sz; i++) {
549 if (rq->wq_type == MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ) {
550 struct mlx5e_rx_wqe_ll *wqe =
551 mlx5_wq_ll_get_wqe(&rq->mpwqe.wq, i);
553 rq->mpwqe.num_strides << rq->mpwqe.log_stride_sz;
554 u64 dma_offset = mlx5e_get_mpwqe_offset(rq, i);
556 wqe->data[0].addr = cpu_to_be64(dma_offset + rq->buff.headroom);
557 wqe->data[0].byte_count = cpu_to_be32(byte_count);
558 wqe->data[0].lkey = rq->mkey_be;
560 struct mlx5e_rx_wqe_cyc *wqe =
561 mlx5_wq_cyc_get_wqe(&rq->wqe.wq, i);
564 for (f = 0; f < rq->wqe.info.num_frags; f++) {
565 u32 frag_size = rq->wqe.info.arr[f].frag_size |
566 MLX5_HW_START_PADDING;
568 wqe->data[f].byte_count = cpu_to_be32(frag_size);
569 wqe->data[f].lkey = rq->mkey_be;
571 /* check if num_frags is not a pow of two */
572 if (rq->wqe.info.num_frags < (1 << rq->wqe.info.log_num_frags)) {
573 wqe->data[f].byte_count = 0;
574 wqe->data[f].lkey = cpu_to_be32(MLX5_INVALID_LKEY);
575 wqe->data[f].addr = 0;
580 INIT_WORK(&rq->dim.work, mlx5e_rx_dim_work);
582 switch (params->rx_cq_moderation.cq_period_mode) {
583 case MLX5_CQ_PERIOD_MODE_START_FROM_CQE:
584 rq->dim.mode = DIM_CQ_PERIOD_MODE_START_FROM_CQE;
586 case MLX5_CQ_PERIOD_MODE_START_FROM_EQE:
588 rq->dim.mode = DIM_CQ_PERIOD_MODE_START_FROM_EQE;
591 rq->page_cache.head = 0;
592 rq->page_cache.tail = 0;
597 switch (rq->wq_type) {
598 case MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ:
599 kvfree(rq->mpwqe.info);
600 mlx5_core_destroy_mkey(mdev, &rq->umr_mkey);
602 default: /* MLX5_WQ_TYPE_CYCLIC */
603 kvfree(rq->wqe.frags);
604 mlx5e_free_di_list(rq);
609 bpf_prog_put(rq->xdp_prog);
610 xdp_rxq_info_unreg(&rq->xdp_rxq);
611 page_pool_destroy(rq->page_pool);
612 mlx5_wq_destroy(&rq->wq_ctrl);
617 static void mlx5e_free_rq(struct mlx5e_rq *rq)
622 bpf_prog_put(rq->xdp_prog);
624 switch (rq->wq_type) {
625 case MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ:
626 kvfree(rq->mpwqe.info);
627 mlx5_core_destroy_mkey(rq->mdev, &rq->umr_mkey);
629 default: /* MLX5_WQ_TYPE_CYCLIC */
630 kvfree(rq->wqe.frags);
631 mlx5e_free_di_list(rq);
634 for (i = rq->page_cache.head; i != rq->page_cache.tail;
635 i = (i + 1) & (MLX5E_CACHE_SIZE - 1)) {
636 struct mlx5e_dma_info *dma_info = &rq->page_cache.page_cache[i];
638 /* With AF_XDP, page_cache is not used, so this loop is not
639 * entered, and it's safe to call mlx5e_page_release_dynamic
642 mlx5e_page_release_dynamic(rq, dma_info, false);
645 xdp_rxq_info_unreg(&rq->xdp_rxq);
646 page_pool_destroy(rq->page_pool);
647 mlx5_wq_destroy(&rq->wq_ctrl);
650 static int mlx5e_create_rq(struct mlx5e_rq *rq,
651 struct mlx5e_rq_param *param)
653 struct mlx5_core_dev *mdev = rq->mdev;
661 inlen = MLX5_ST_SZ_BYTES(create_rq_in) +
662 sizeof(u64) * rq->wq_ctrl.buf.npages;
663 in = kvzalloc(inlen, GFP_KERNEL);
667 rqc = MLX5_ADDR_OF(create_rq_in, in, ctx);
668 wq = MLX5_ADDR_OF(rqc, rqc, wq);
670 memcpy(rqc, param->rqc, sizeof(param->rqc));
672 MLX5_SET(rqc, rqc, cqn, rq->cq.mcq.cqn);
673 MLX5_SET(rqc, rqc, state, MLX5_RQC_STATE_RST);
674 MLX5_SET(wq, wq, log_wq_pg_sz, rq->wq_ctrl.buf.page_shift -
675 MLX5_ADAPTER_PAGE_SHIFT);
676 MLX5_SET64(wq, wq, dbr_addr, rq->wq_ctrl.db.dma);
678 mlx5_fill_page_frag_array(&rq->wq_ctrl.buf,
679 (__be64 *)MLX5_ADDR_OF(wq, wq, pas));
681 err = mlx5_core_create_rq(mdev, in, inlen, &rq->rqn);
688 int mlx5e_modify_rq_state(struct mlx5e_rq *rq, int curr_state, int next_state)
690 struct mlx5_core_dev *mdev = rq->mdev;
697 inlen = MLX5_ST_SZ_BYTES(modify_rq_in);
698 in = kvzalloc(inlen, GFP_KERNEL);
702 if (curr_state == MLX5_RQC_STATE_RST && next_state == MLX5_RQC_STATE_RDY)
703 mlx5e_rqwq_reset(rq);
705 rqc = MLX5_ADDR_OF(modify_rq_in, in, ctx);
707 MLX5_SET(modify_rq_in, in, rq_state, curr_state);
708 MLX5_SET(rqc, rqc, state, next_state);
710 err = mlx5_core_modify_rq(mdev, rq->rqn, in);
717 static int mlx5e_modify_rq_scatter_fcs(struct mlx5e_rq *rq, bool enable)
719 struct mlx5e_channel *c = rq->channel;
720 struct mlx5e_priv *priv = c->priv;
721 struct mlx5_core_dev *mdev = priv->mdev;
728 inlen = MLX5_ST_SZ_BYTES(modify_rq_in);
729 in = kvzalloc(inlen, GFP_KERNEL);
733 rqc = MLX5_ADDR_OF(modify_rq_in, in, ctx);
735 MLX5_SET(modify_rq_in, in, rq_state, MLX5_RQC_STATE_RDY);
736 MLX5_SET64(modify_rq_in, in, modify_bitmask,
737 MLX5_MODIFY_RQ_IN_MODIFY_BITMASK_SCATTER_FCS);
738 MLX5_SET(rqc, rqc, scatter_fcs, enable);
739 MLX5_SET(rqc, rqc, state, MLX5_RQC_STATE_RDY);
741 err = mlx5_core_modify_rq(mdev, rq->rqn, in);
748 static int mlx5e_modify_rq_vsd(struct mlx5e_rq *rq, bool vsd)
750 struct mlx5e_channel *c = rq->channel;
751 struct mlx5_core_dev *mdev = c->mdev;
757 inlen = MLX5_ST_SZ_BYTES(modify_rq_in);
758 in = kvzalloc(inlen, GFP_KERNEL);
762 rqc = MLX5_ADDR_OF(modify_rq_in, in, ctx);
764 MLX5_SET(modify_rq_in, in, rq_state, MLX5_RQC_STATE_RDY);
765 MLX5_SET64(modify_rq_in, in, modify_bitmask,
766 MLX5_MODIFY_RQ_IN_MODIFY_BITMASK_VSD);
767 MLX5_SET(rqc, rqc, vsd, vsd);
768 MLX5_SET(rqc, rqc, state, MLX5_RQC_STATE_RDY);
770 err = mlx5_core_modify_rq(mdev, rq->rqn, in);
777 static void mlx5e_destroy_rq(struct mlx5e_rq *rq)
779 mlx5_core_destroy_rq(rq->mdev, rq->rqn);
782 int mlx5e_wait_for_min_rx_wqes(struct mlx5e_rq *rq, int wait_time)
784 unsigned long exp_time = jiffies + msecs_to_jiffies(wait_time);
785 struct mlx5e_channel *c = rq->channel;
787 u16 min_wqes = mlx5_min_rx_wqes(rq->wq_type, mlx5e_rqwq_get_size(rq));
790 if (mlx5e_rqwq_get_cur_sz(rq) >= min_wqes)
794 } while (time_before(jiffies, exp_time));
796 netdev_warn(c->netdev, "Failed to get min RX wqes on Channel[%d] RQN[0x%x] wq cur_sz(%d) min_rx_wqes(%d)\n",
797 c->ix, rq->rqn, mlx5e_rqwq_get_cur_sz(rq), min_wqes);
799 mlx5e_reporter_rx_timeout(rq);
803 void mlx5e_free_rx_in_progress_descs(struct mlx5e_rq *rq)
805 struct mlx5_wq_ll *wq;
809 if (rq->wq_type != MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ)
815 /* Outstanding UMR WQEs (in progress) start at wq->head */
816 for (i = 0; i < rq->mpwqe.umr_in_progress; i++) {
817 rq->dealloc_wqe(rq, head);
818 head = mlx5_wq_ll_get_wqe_next_ix(wq, head);
821 rq->mpwqe.actual_wq_head = wq->head;
822 rq->mpwqe.umr_in_progress = 0;
823 rq->mpwqe.umr_completed = 0;
826 void mlx5e_free_rx_descs(struct mlx5e_rq *rq)
831 if (rq->wq_type == MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ) {
832 struct mlx5_wq_ll *wq = &rq->mpwqe.wq;
834 mlx5e_free_rx_in_progress_descs(rq);
836 while (!mlx5_wq_ll_is_empty(wq)) {
837 struct mlx5e_rx_wqe_ll *wqe;
839 wqe_ix_be = *wq->tail_next;
840 wqe_ix = be16_to_cpu(wqe_ix_be);
841 wqe = mlx5_wq_ll_get_wqe(wq, wqe_ix);
842 rq->dealloc_wqe(rq, wqe_ix);
843 mlx5_wq_ll_pop(wq, wqe_ix_be,
844 &wqe->next.next_wqe_index);
847 struct mlx5_wq_cyc *wq = &rq->wqe.wq;
849 while (!mlx5_wq_cyc_is_empty(wq)) {
850 wqe_ix = mlx5_wq_cyc_get_tail(wq);
851 rq->dealloc_wqe(rq, wqe_ix);
858 int mlx5e_open_rq(struct mlx5e_channel *c, struct mlx5e_params *params,
859 struct mlx5e_rq_param *param, struct mlx5e_xsk_param *xsk,
860 struct xdp_umem *umem, struct mlx5e_rq *rq)
864 err = mlx5e_alloc_rq(c, params, xsk, umem, param, rq);
868 err = mlx5e_create_rq(rq, param);
872 err = mlx5e_modify_rq_state(rq, MLX5_RQC_STATE_RST, MLX5_RQC_STATE_RDY);
876 if (MLX5_CAP_ETH(c->mdev, cqe_checksum_full))
877 __set_bit(MLX5E_RQ_STATE_CSUM_FULL, &c->rq.state);
879 if (params->rx_dim_enabled)
880 __set_bit(MLX5E_RQ_STATE_AM, &c->rq.state);
882 /* We disable csum_complete when XDP is enabled since
883 * XDP programs might manipulate packets which will render
884 * skb->checksum incorrect.
886 if (MLX5E_GET_PFLAG(params, MLX5E_PFLAG_RX_NO_CSUM_COMPLETE) || c->xdp)
887 __set_bit(MLX5E_RQ_STATE_NO_CSUM_COMPLETE, &c->rq.state);
892 mlx5e_destroy_rq(rq);
899 void mlx5e_activate_rq(struct mlx5e_rq *rq)
901 set_bit(MLX5E_RQ_STATE_ENABLED, &rq->state);
902 mlx5e_trigger_irq(&rq->channel->icosq);
905 void mlx5e_deactivate_rq(struct mlx5e_rq *rq)
907 clear_bit(MLX5E_RQ_STATE_ENABLED, &rq->state);
908 napi_synchronize(&rq->channel->napi); /* prevent mlx5e_post_rx_wqes */
911 void mlx5e_close_rq(struct mlx5e_rq *rq)
913 cancel_work_sync(&rq->dim.work);
914 cancel_work_sync(&rq->channel->icosq.recover_work);
915 cancel_work_sync(&rq->recover_work);
916 mlx5e_destroy_rq(rq);
917 mlx5e_free_rx_descs(rq);
921 static void mlx5e_free_xdpsq_db(struct mlx5e_xdpsq *sq)
923 kvfree(sq->db.xdpi_fifo.xi);
924 kvfree(sq->db.wqe_info);
927 static int mlx5e_alloc_xdpsq_fifo(struct mlx5e_xdpsq *sq, int numa)
929 struct mlx5e_xdp_info_fifo *xdpi_fifo = &sq->db.xdpi_fifo;
930 int wq_sz = mlx5_wq_cyc_get_size(&sq->wq);
931 int dsegs_per_wq = wq_sz * MLX5_SEND_WQEBB_NUM_DS;
933 xdpi_fifo->xi = kvzalloc_node(sizeof(*xdpi_fifo->xi) * dsegs_per_wq,
938 xdpi_fifo->pc = &sq->xdpi_fifo_pc;
939 xdpi_fifo->cc = &sq->xdpi_fifo_cc;
940 xdpi_fifo->mask = dsegs_per_wq - 1;
945 static int mlx5e_alloc_xdpsq_db(struct mlx5e_xdpsq *sq, int numa)
947 int wq_sz = mlx5_wq_cyc_get_size(&sq->wq);
950 sq->db.wqe_info = kvzalloc_node(sizeof(*sq->db.wqe_info) * wq_sz,
952 if (!sq->db.wqe_info)
955 err = mlx5e_alloc_xdpsq_fifo(sq, numa);
957 mlx5e_free_xdpsq_db(sq);
964 static int mlx5e_alloc_xdpsq(struct mlx5e_channel *c,
965 struct mlx5e_params *params,
966 struct xdp_umem *umem,
967 struct mlx5e_sq_param *param,
968 struct mlx5e_xdpsq *sq,
971 void *sqc_wq = MLX5_ADDR_OF(sqc, param->sqc, wq);
972 struct mlx5_core_dev *mdev = c->mdev;
973 struct mlx5_wq_cyc *wq = &sq->wq;
977 sq->mkey_be = c->mkey_be;
979 sq->uar_map = mdev->mlx5e_res.bfreg.map;
980 sq->min_inline_mode = params->tx_min_inline_mode;
981 sq->hw_mtu = MLX5E_SW2HW_MTU(params, params->sw_mtu);
984 sq->stats = sq->umem ?
985 &c->priv->channel_stats[c->ix].xsksq :
987 &c->priv->channel_stats[c->ix].xdpsq :
988 &c->priv->channel_stats[c->ix].rq_xdpsq;
990 param->wq.db_numa_node = cpu_to_node(c->cpu);
991 err = mlx5_wq_cyc_create(mdev, ¶m->wq, sqc_wq, wq, &sq->wq_ctrl);
994 wq->db = &wq->db[MLX5_SND_DBR];
996 err = mlx5e_alloc_xdpsq_db(sq, cpu_to_node(c->cpu));
998 goto err_sq_wq_destroy;
1003 mlx5_wq_destroy(&sq->wq_ctrl);
1008 static void mlx5e_free_xdpsq(struct mlx5e_xdpsq *sq)
1010 mlx5e_free_xdpsq_db(sq);
1011 mlx5_wq_destroy(&sq->wq_ctrl);
1014 static void mlx5e_free_icosq_db(struct mlx5e_icosq *sq)
1016 kvfree(sq->db.wqe_info);
1019 static int mlx5e_alloc_icosq_db(struct mlx5e_icosq *sq, int numa)
1021 int wq_sz = mlx5_wq_cyc_get_size(&sq->wq);
1024 size = array_size(wq_sz, sizeof(*sq->db.wqe_info));
1025 sq->db.wqe_info = kvzalloc_node(size, GFP_KERNEL, numa);
1026 if (!sq->db.wqe_info)
1032 static void mlx5e_icosq_err_cqe_work(struct work_struct *recover_work)
1034 struct mlx5e_icosq *sq = container_of(recover_work, struct mlx5e_icosq,
1037 mlx5e_reporter_icosq_cqe_err(sq);
1040 static int mlx5e_alloc_icosq(struct mlx5e_channel *c,
1041 struct mlx5e_sq_param *param,
1042 struct mlx5e_icosq *sq)
1044 void *sqc_wq = MLX5_ADDR_OF(sqc, param->sqc, wq);
1045 struct mlx5_core_dev *mdev = c->mdev;
1046 struct mlx5_wq_cyc *wq = &sq->wq;
1050 sq->uar_map = mdev->mlx5e_res.bfreg.map;
1052 param->wq.db_numa_node = cpu_to_node(c->cpu);
1053 err = mlx5_wq_cyc_create(mdev, ¶m->wq, sqc_wq, wq, &sq->wq_ctrl);
1056 wq->db = &wq->db[MLX5_SND_DBR];
1058 err = mlx5e_alloc_icosq_db(sq, cpu_to_node(c->cpu));
1060 goto err_sq_wq_destroy;
1062 INIT_WORK(&sq->recover_work, mlx5e_icosq_err_cqe_work);
1067 mlx5_wq_destroy(&sq->wq_ctrl);
1072 static void mlx5e_free_icosq(struct mlx5e_icosq *sq)
1074 mlx5e_free_icosq_db(sq);
1075 mlx5_wq_destroy(&sq->wq_ctrl);
1078 static void mlx5e_free_txqsq_db(struct mlx5e_txqsq *sq)
1080 kvfree(sq->db.wqe_info);
1081 kvfree(sq->db.dma_fifo);
1084 static int mlx5e_alloc_txqsq_db(struct mlx5e_txqsq *sq, int numa)
1086 int wq_sz = mlx5_wq_cyc_get_size(&sq->wq);
1087 int df_sz = wq_sz * MLX5_SEND_WQEBB_NUM_DS;
1089 sq->db.dma_fifo = kvzalloc_node(array_size(df_sz,
1090 sizeof(*sq->db.dma_fifo)),
1092 sq->db.wqe_info = kvzalloc_node(array_size(wq_sz,
1093 sizeof(*sq->db.wqe_info)),
1095 if (!sq->db.dma_fifo || !sq->db.wqe_info) {
1096 mlx5e_free_txqsq_db(sq);
1100 sq->dma_fifo_mask = df_sz - 1;
1105 static int mlx5e_calc_sq_stop_room(struct mlx5e_txqsq *sq, u8 log_sq_size)
1107 int sq_size = 1 << log_sq_size;
1109 sq->stop_room = mlx5e_tls_get_stop_room(sq);
1110 sq->stop_room += mlx5e_stop_room_for_wqe(MLX5_SEND_WQE_MAX_WQEBBS);
1112 if (WARN_ON(sq->stop_room >= sq_size)) {
1113 netdev_err(sq->channel->netdev, "Stop room %hu is bigger than the SQ size %d\n",
1114 sq->stop_room, sq_size);
1121 static void mlx5e_tx_err_cqe_work(struct work_struct *recover_work);
1122 static int mlx5e_alloc_txqsq(struct mlx5e_channel *c,
1124 struct mlx5e_params *params,
1125 struct mlx5e_sq_param *param,
1126 struct mlx5e_txqsq *sq,
1129 void *sqc_wq = MLX5_ADDR_OF(sqc, param->sqc, wq);
1130 struct mlx5_core_dev *mdev = c->mdev;
1131 struct mlx5_wq_cyc *wq = &sq->wq;
1135 sq->tstamp = c->tstamp;
1136 sq->clock = &mdev->clock;
1137 sq->mkey_be = c->mkey_be;
1140 sq->txq_ix = txq_ix;
1141 sq->uar_map = mdev->mlx5e_res.bfreg.map;
1142 sq->min_inline_mode = params->tx_min_inline_mode;
1143 sq->hw_mtu = MLX5E_SW2HW_MTU(params, params->sw_mtu);
1144 sq->stats = &c->priv->channel_stats[c->ix].sq[tc];
1145 INIT_WORK(&sq->recover_work, mlx5e_tx_err_cqe_work);
1146 if (!MLX5_CAP_ETH(mdev, wqe_vlan_insert))
1147 set_bit(MLX5E_SQ_STATE_VLAN_NEED_L2_INLINE, &sq->state);
1148 if (MLX5_IPSEC_DEV(c->priv->mdev))
1149 set_bit(MLX5E_SQ_STATE_IPSEC, &sq->state);
1150 if (mlx5_accel_is_tls_device(c->priv->mdev))
1151 set_bit(MLX5E_SQ_STATE_TLS, &sq->state);
1152 err = mlx5e_calc_sq_stop_room(sq, params->log_sq_size);
1156 param->wq.db_numa_node = cpu_to_node(c->cpu);
1157 err = mlx5_wq_cyc_create(mdev, ¶m->wq, sqc_wq, wq, &sq->wq_ctrl);
1160 wq->db = &wq->db[MLX5_SND_DBR];
1162 err = mlx5e_alloc_txqsq_db(sq, cpu_to_node(c->cpu));
1164 goto err_sq_wq_destroy;
1166 INIT_WORK(&sq->dim.work, mlx5e_tx_dim_work);
1167 sq->dim.mode = params->tx_cq_moderation.cq_period_mode;
1172 mlx5_wq_destroy(&sq->wq_ctrl);
1177 static void mlx5e_free_txqsq(struct mlx5e_txqsq *sq)
1179 mlx5e_free_txqsq_db(sq);
1180 mlx5_wq_destroy(&sq->wq_ctrl);
1183 struct mlx5e_create_sq_param {
1184 struct mlx5_wq_ctrl *wq_ctrl;
1191 static int mlx5e_create_sq(struct mlx5_core_dev *mdev,
1192 struct mlx5e_sq_param *param,
1193 struct mlx5e_create_sq_param *csp,
1202 inlen = MLX5_ST_SZ_BYTES(create_sq_in) +
1203 sizeof(u64) * csp->wq_ctrl->buf.npages;
1204 in = kvzalloc(inlen, GFP_KERNEL);
1208 sqc = MLX5_ADDR_OF(create_sq_in, in, ctx);
1209 wq = MLX5_ADDR_OF(sqc, sqc, wq);
1211 memcpy(sqc, param->sqc, sizeof(param->sqc));
1212 MLX5_SET(sqc, sqc, tis_lst_sz, csp->tis_lst_sz);
1213 MLX5_SET(sqc, sqc, tis_num_0, csp->tisn);
1214 MLX5_SET(sqc, sqc, cqn, csp->cqn);
1216 if (MLX5_CAP_ETH(mdev, wqe_inline_mode) == MLX5_CAP_INLINE_MODE_VPORT_CONTEXT)
1217 MLX5_SET(sqc, sqc, min_wqe_inline_mode, csp->min_inline_mode);
1219 MLX5_SET(sqc, sqc, state, MLX5_SQC_STATE_RST);
1220 MLX5_SET(sqc, sqc, flush_in_error_en, 1);
1222 MLX5_SET(wq, wq, wq_type, MLX5_WQ_TYPE_CYCLIC);
1223 MLX5_SET(wq, wq, uar_page, mdev->mlx5e_res.bfreg.index);
1224 MLX5_SET(wq, wq, log_wq_pg_sz, csp->wq_ctrl->buf.page_shift -
1225 MLX5_ADAPTER_PAGE_SHIFT);
1226 MLX5_SET64(wq, wq, dbr_addr, csp->wq_ctrl->db.dma);
1228 mlx5_fill_page_frag_array(&csp->wq_ctrl->buf,
1229 (__be64 *)MLX5_ADDR_OF(wq, wq, pas));
1231 err = mlx5_core_create_sq(mdev, in, inlen, sqn);
1238 int mlx5e_modify_sq(struct mlx5_core_dev *mdev, u32 sqn,
1239 struct mlx5e_modify_sq_param *p)
1246 inlen = MLX5_ST_SZ_BYTES(modify_sq_in);
1247 in = kvzalloc(inlen, GFP_KERNEL);
1251 sqc = MLX5_ADDR_OF(modify_sq_in, in, ctx);
1253 MLX5_SET(modify_sq_in, in, sq_state, p->curr_state);
1254 MLX5_SET(sqc, sqc, state, p->next_state);
1255 if (p->rl_update && p->next_state == MLX5_SQC_STATE_RDY) {
1256 MLX5_SET64(modify_sq_in, in, modify_bitmask, 1);
1257 MLX5_SET(sqc, sqc, packet_pacing_rate_limit_index, p->rl_index);
1260 err = mlx5_core_modify_sq(mdev, sqn, in);
1267 static void mlx5e_destroy_sq(struct mlx5_core_dev *mdev, u32 sqn)
1269 mlx5_core_destroy_sq(mdev, sqn);
1272 static int mlx5e_create_sq_rdy(struct mlx5_core_dev *mdev,
1273 struct mlx5e_sq_param *param,
1274 struct mlx5e_create_sq_param *csp,
1277 struct mlx5e_modify_sq_param msp = {0};
1280 err = mlx5e_create_sq(mdev, param, csp, sqn);
1284 msp.curr_state = MLX5_SQC_STATE_RST;
1285 msp.next_state = MLX5_SQC_STATE_RDY;
1286 err = mlx5e_modify_sq(mdev, *sqn, &msp);
1288 mlx5e_destroy_sq(mdev, *sqn);
1293 static int mlx5e_set_sq_maxrate(struct net_device *dev,
1294 struct mlx5e_txqsq *sq, u32 rate);
1296 static int mlx5e_open_txqsq(struct mlx5e_channel *c,
1299 struct mlx5e_params *params,
1300 struct mlx5e_sq_param *param,
1301 struct mlx5e_txqsq *sq,
1304 struct mlx5e_create_sq_param csp = {};
1308 err = mlx5e_alloc_txqsq(c, txq_ix, params, param, sq, tc);
1314 csp.cqn = sq->cq.mcq.cqn;
1315 csp.wq_ctrl = &sq->wq_ctrl;
1316 csp.min_inline_mode = sq->min_inline_mode;
1317 err = mlx5e_create_sq_rdy(c->mdev, param, &csp, &sq->sqn);
1319 goto err_free_txqsq;
1321 tx_rate = c->priv->tx_rates[sq->txq_ix];
1323 mlx5e_set_sq_maxrate(c->netdev, sq, tx_rate);
1325 if (params->tx_dim_enabled)
1326 sq->state |= BIT(MLX5E_SQ_STATE_AM);
1331 mlx5e_free_txqsq(sq);
1336 void mlx5e_activate_txqsq(struct mlx5e_txqsq *sq)
1338 sq->txq = netdev_get_tx_queue(sq->channel->netdev, sq->txq_ix);
1339 set_bit(MLX5E_SQ_STATE_ENABLED, &sq->state);
1340 netdev_tx_reset_queue(sq->txq);
1341 netif_tx_start_queue(sq->txq);
1344 void mlx5e_tx_disable_queue(struct netdev_queue *txq)
1346 __netif_tx_lock_bh(txq);
1347 netif_tx_stop_queue(txq);
1348 __netif_tx_unlock_bh(txq);
1351 static void mlx5e_deactivate_txqsq(struct mlx5e_txqsq *sq)
1353 struct mlx5e_channel *c = sq->channel;
1354 struct mlx5_wq_cyc *wq = &sq->wq;
1356 clear_bit(MLX5E_SQ_STATE_ENABLED, &sq->state);
1357 /* prevent netif_tx_wake_queue */
1358 napi_synchronize(&c->napi);
1360 mlx5e_tx_disable_queue(sq->txq);
1362 /* last doorbell out, godspeed .. */
1363 if (mlx5e_wqc_has_room_for(wq, sq->cc, sq->pc, 1)) {
1364 u16 pi = mlx5_wq_cyc_ctr2ix(wq, sq->pc);
1365 struct mlx5e_tx_wqe *nop;
1367 sq->db.wqe_info[pi] = (struct mlx5e_tx_wqe_info) {
1371 nop = mlx5e_post_nop(wq, sq->sqn, &sq->pc);
1372 mlx5e_notify_hw(wq, sq->pc, sq->uar_map, &nop->ctrl);
1376 static void mlx5e_close_txqsq(struct mlx5e_txqsq *sq)
1378 struct mlx5e_channel *c = sq->channel;
1379 struct mlx5_core_dev *mdev = c->mdev;
1380 struct mlx5_rate_limit rl = {0};
1382 cancel_work_sync(&sq->dim.work);
1383 cancel_work_sync(&sq->recover_work);
1384 mlx5e_destroy_sq(mdev, sq->sqn);
1385 if (sq->rate_limit) {
1386 rl.rate = sq->rate_limit;
1387 mlx5_rl_remove_rate(mdev, &rl);
1389 mlx5e_free_txqsq_descs(sq);
1390 mlx5e_free_txqsq(sq);
1393 static void mlx5e_tx_err_cqe_work(struct work_struct *recover_work)
1395 struct mlx5e_txqsq *sq = container_of(recover_work, struct mlx5e_txqsq,
1398 mlx5e_reporter_tx_err_cqe(sq);
1401 int mlx5e_open_icosq(struct mlx5e_channel *c, struct mlx5e_params *params,
1402 struct mlx5e_sq_param *param, struct mlx5e_icosq *sq)
1404 struct mlx5e_create_sq_param csp = {};
1407 err = mlx5e_alloc_icosq(c, param, sq);
1411 csp.cqn = sq->cq.mcq.cqn;
1412 csp.wq_ctrl = &sq->wq_ctrl;
1413 csp.min_inline_mode = params->tx_min_inline_mode;
1414 err = mlx5e_create_sq_rdy(c->mdev, param, &csp, &sq->sqn);
1416 goto err_free_icosq;
1421 mlx5e_free_icosq(sq);
1426 void mlx5e_activate_icosq(struct mlx5e_icosq *icosq)
1428 set_bit(MLX5E_SQ_STATE_ENABLED, &icosq->state);
1431 void mlx5e_deactivate_icosq(struct mlx5e_icosq *icosq)
1433 struct mlx5e_channel *c = icosq->channel;
1435 clear_bit(MLX5E_SQ_STATE_ENABLED, &icosq->state);
1436 napi_synchronize(&c->napi);
1439 void mlx5e_close_icosq(struct mlx5e_icosq *sq)
1441 struct mlx5e_channel *c = sq->channel;
1443 mlx5e_destroy_sq(c->mdev, sq->sqn);
1444 mlx5e_free_icosq(sq);
1447 int mlx5e_open_xdpsq(struct mlx5e_channel *c, struct mlx5e_params *params,
1448 struct mlx5e_sq_param *param, struct xdp_umem *umem,
1449 struct mlx5e_xdpsq *sq, bool is_redirect)
1451 struct mlx5e_create_sq_param csp = {};
1454 err = mlx5e_alloc_xdpsq(c, params, umem, param, sq, is_redirect);
1459 csp.tisn = c->priv->tisn[c->lag_port][0]; /* tc = 0 */
1460 csp.cqn = sq->cq.mcq.cqn;
1461 csp.wq_ctrl = &sq->wq_ctrl;
1462 csp.min_inline_mode = sq->min_inline_mode;
1463 set_bit(MLX5E_SQ_STATE_ENABLED, &sq->state);
1464 err = mlx5e_create_sq_rdy(c->mdev, param, &csp, &sq->sqn);
1466 goto err_free_xdpsq;
1468 mlx5e_set_xmit_fp(sq, param->is_mpw);
1470 if (!param->is_mpw) {
1471 unsigned int ds_cnt = MLX5E_XDP_TX_DS_COUNT;
1472 unsigned int inline_hdr_sz = 0;
1475 if (sq->min_inline_mode != MLX5_INLINE_MODE_NONE) {
1476 inline_hdr_sz = MLX5E_XDP_MIN_INLINE;
1480 /* Pre initialize fixed WQE fields */
1481 for (i = 0; i < mlx5_wq_cyc_get_size(&sq->wq); i++) {
1482 struct mlx5e_tx_wqe *wqe = mlx5_wq_cyc_get_wqe(&sq->wq, i);
1483 struct mlx5_wqe_ctrl_seg *cseg = &wqe->ctrl;
1484 struct mlx5_wqe_eth_seg *eseg = &wqe->eth;
1485 struct mlx5_wqe_data_seg *dseg;
1487 sq->db.wqe_info[i] = (struct mlx5e_xdp_wqe_info) {
1492 cseg->qpn_ds = cpu_to_be32((sq->sqn << 8) | ds_cnt);
1493 eseg->inline_hdr.sz = cpu_to_be16(inline_hdr_sz);
1495 dseg = (struct mlx5_wqe_data_seg *)cseg + (ds_cnt - 1);
1496 dseg->lkey = sq->mkey_be;
1503 clear_bit(MLX5E_SQ_STATE_ENABLED, &sq->state);
1504 mlx5e_free_xdpsq(sq);
1509 void mlx5e_close_xdpsq(struct mlx5e_xdpsq *sq)
1511 struct mlx5e_channel *c = sq->channel;
1513 clear_bit(MLX5E_SQ_STATE_ENABLED, &sq->state);
1514 napi_synchronize(&c->napi);
1516 mlx5e_destroy_sq(c->mdev, sq->sqn);
1517 mlx5e_free_xdpsq_descs(sq);
1518 mlx5e_free_xdpsq(sq);
1521 static int mlx5e_alloc_cq_common(struct mlx5_core_dev *mdev,
1522 struct mlx5e_cq_param *param,
1523 struct mlx5e_cq *cq)
1525 struct mlx5_core_cq *mcq = &cq->mcq;
1531 err = mlx5_vector2eqn(mdev, param->eq_ix, &eqn_not_used, &irqn);
1535 err = mlx5_cqwq_create(mdev, ¶m->wq, param->cqc, &cq->wq,
1541 mcq->set_ci_db = cq->wq_ctrl.db.db;
1542 mcq->arm_db = cq->wq_ctrl.db.db + 1;
1543 *mcq->set_ci_db = 0;
1545 mcq->vector = param->eq_ix;
1546 mcq->comp = mlx5e_completion_event;
1547 mcq->event = mlx5e_cq_error_event;
1550 for (i = 0; i < mlx5_cqwq_get_size(&cq->wq); i++) {
1551 struct mlx5_cqe64 *cqe = mlx5_cqwq_get_wqe(&cq->wq, i);
1561 static int mlx5e_alloc_cq(struct mlx5e_channel *c,
1562 struct mlx5e_cq_param *param,
1563 struct mlx5e_cq *cq)
1565 struct mlx5_core_dev *mdev = c->priv->mdev;
1568 param->wq.buf_numa_node = cpu_to_node(c->cpu);
1569 param->wq.db_numa_node = cpu_to_node(c->cpu);
1570 param->eq_ix = c->ix;
1572 err = mlx5e_alloc_cq_common(mdev, param, cq);
1574 cq->napi = &c->napi;
1580 static void mlx5e_free_cq(struct mlx5e_cq *cq)
1582 mlx5_wq_destroy(&cq->wq_ctrl);
1585 static int mlx5e_create_cq(struct mlx5e_cq *cq, struct mlx5e_cq_param *param)
1587 u32 out[MLX5_ST_SZ_DW(create_cq_out)];
1588 struct mlx5_core_dev *mdev = cq->mdev;
1589 struct mlx5_core_cq *mcq = &cq->mcq;
1594 unsigned int irqn_not_used;
1598 err = mlx5_vector2eqn(mdev, param->eq_ix, &eqn, &irqn_not_used);
1602 inlen = MLX5_ST_SZ_BYTES(create_cq_in) +
1603 sizeof(u64) * cq->wq_ctrl.buf.npages;
1604 in = kvzalloc(inlen, GFP_KERNEL);
1608 cqc = MLX5_ADDR_OF(create_cq_in, in, cq_context);
1610 memcpy(cqc, param->cqc, sizeof(param->cqc));
1612 mlx5_fill_page_frag_array(&cq->wq_ctrl.buf,
1613 (__be64 *)MLX5_ADDR_OF(create_cq_in, in, pas));
1615 MLX5_SET(cqc, cqc, cq_period_mode, param->cq_period_mode);
1616 MLX5_SET(cqc, cqc, c_eqn, eqn);
1617 MLX5_SET(cqc, cqc, uar_page, mdev->priv.uar->index);
1618 MLX5_SET(cqc, cqc, log_page_size, cq->wq_ctrl.buf.page_shift -
1619 MLX5_ADAPTER_PAGE_SHIFT);
1620 MLX5_SET64(cqc, cqc, dbr_addr, cq->wq_ctrl.db.dma);
1622 err = mlx5_core_create_cq(mdev, mcq, in, inlen, out, sizeof(out));
1634 static void mlx5e_destroy_cq(struct mlx5e_cq *cq)
1636 mlx5_core_destroy_cq(cq->mdev, &cq->mcq);
1639 int mlx5e_open_cq(struct mlx5e_channel *c, struct dim_cq_moder moder,
1640 struct mlx5e_cq_param *param, struct mlx5e_cq *cq)
1642 struct mlx5_core_dev *mdev = c->mdev;
1645 err = mlx5e_alloc_cq(c, param, cq);
1649 err = mlx5e_create_cq(cq, param);
1653 if (MLX5_CAP_GEN(mdev, cq_moderation))
1654 mlx5_core_modify_cq_moderation(mdev, &cq->mcq, moder.usec, moder.pkts);
1663 void mlx5e_close_cq(struct mlx5e_cq *cq)
1665 mlx5e_destroy_cq(cq);
1669 static int mlx5e_open_tx_cqs(struct mlx5e_channel *c,
1670 struct mlx5e_params *params,
1671 struct mlx5e_channel_param *cparam)
1676 for (tc = 0; tc < c->num_tc; tc++) {
1677 err = mlx5e_open_cq(c, params->tx_cq_moderation,
1678 &cparam->tx_cq, &c->sq[tc].cq);
1680 goto err_close_tx_cqs;
1686 for (tc--; tc >= 0; tc--)
1687 mlx5e_close_cq(&c->sq[tc].cq);
1692 static void mlx5e_close_tx_cqs(struct mlx5e_channel *c)
1696 for (tc = 0; tc < c->num_tc; tc++)
1697 mlx5e_close_cq(&c->sq[tc].cq);
1700 static int mlx5e_open_sqs(struct mlx5e_channel *c,
1701 struct mlx5e_params *params,
1702 struct mlx5e_channel_param *cparam)
1706 for (tc = 0; tc < params->num_tc; tc++) {
1707 int txq_ix = c->ix + tc * params->num_channels;
1709 err = mlx5e_open_txqsq(c, c->priv->tisn[c->lag_port][tc], txq_ix,
1710 params, &cparam->sq, &c->sq[tc], tc);
1718 for (tc--; tc >= 0; tc--)
1719 mlx5e_close_txqsq(&c->sq[tc]);
1724 static void mlx5e_close_sqs(struct mlx5e_channel *c)
1728 for (tc = 0; tc < c->num_tc; tc++)
1729 mlx5e_close_txqsq(&c->sq[tc]);
1732 static int mlx5e_set_sq_maxrate(struct net_device *dev,
1733 struct mlx5e_txqsq *sq, u32 rate)
1735 struct mlx5e_priv *priv = netdev_priv(dev);
1736 struct mlx5_core_dev *mdev = priv->mdev;
1737 struct mlx5e_modify_sq_param msp = {0};
1738 struct mlx5_rate_limit rl = {0};
1742 if (rate == sq->rate_limit)
1746 if (sq->rate_limit) {
1747 rl.rate = sq->rate_limit;
1748 /* remove current rl index to free space to next ones */
1749 mlx5_rl_remove_rate(mdev, &rl);
1756 err = mlx5_rl_add_rate(mdev, &rl_index, &rl);
1758 netdev_err(dev, "Failed configuring rate %u: %d\n",
1764 msp.curr_state = MLX5_SQC_STATE_RDY;
1765 msp.next_state = MLX5_SQC_STATE_RDY;
1766 msp.rl_index = rl_index;
1767 msp.rl_update = true;
1768 err = mlx5e_modify_sq(mdev, sq->sqn, &msp);
1770 netdev_err(dev, "Failed configuring rate %u: %d\n",
1772 /* remove the rate from the table */
1774 mlx5_rl_remove_rate(mdev, &rl);
1778 sq->rate_limit = rate;
1782 static int mlx5e_set_tx_maxrate(struct net_device *dev, int index, u32 rate)
1784 struct mlx5e_priv *priv = netdev_priv(dev);
1785 struct mlx5_core_dev *mdev = priv->mdev;
1786 struct mlx5e_txqsq *sq = priv->txq2sq[index];
1789 if (!mlx5_rl_is_supported(mdev)) {
1790 netdev_err(dev, "Rate limiting is not supported on this device\n");
1794 /* rate is given in Mb/sec, HW config is in Kb/sec */
1797 /* Check whether rate in valid range, 0 is always valid */
1798 if (rate && !mlx5_rl_is_in_range(mdev, rate)) {
1799 netdev_err(dev, "TX rate %u, is not in range\n", rate);
1803 mutex_lock(&priv->state_lock);
1804 if (test_bit(MLX5E_STATE_OPENED, &priv->state))
1805 err = mlx5e_set_sq_maxrate(dev, sq, rate);
1807 priv->tx_rates[index] = rate;
1808 mutex_unlock(&priv->state_lock);
1813 static int mlx5e_open_queues(struct mlx5e_channel *c,
1814 struct mlx5e_params *params,
1815 struct mlx5e_channel_param *cparam)
1817 struct dim_cq_moder icocq_moder = {0, 0};
1820 err = mlx5e_open_cq(c, icocq_moder, &cparam->icosq_cq, &c->icosq.cq);
1824 err = mlx5e_open_tx_cqs(c, params, cparam);
1826 goto err_close_icosq_cq;
1828 err = mlx5e_open_cq(c, params->tx_cq_moderation, &cparam->tx_cq, &c->xdpsq.cq);
1830 goto err_close_tx_cqs;
1832 err = mlx5e_open_cq(c, params->rx_cq_moderation, &cparam->rx_cq, &c->rq.cq);
1834 goto err_close_xdp_tx_cqs;
1836 /* XDP SQ CQ params are same as normal TXQ sq CQ params */
1837 err = c->xdp ? mlx5e_open_cq(c, params->tx_cq_moderation,
1838 &cparam->tx_cq, &c->rq_xdpsq.cq) : 0;
1840 goto err_close_rx_cq;
1842 napi_enable(&c->napi);
1844 err = mlx5e_open_icosq(c, params, &cparam->icosq, &c->icosq);
1846 goto err_disable_napi;
1848 err = mlx5e_open_sqs(c, params, cparam);
1850 goto err_close_icosq;
1853 err = mlx5e_open_xdpsq(c, params, &cparam->xdp_sq, NULL,
1854 &c->rq_xdpsq, false);
1859 err = mlx5e_open_rq(c, params, &cparam->rq, NULL, NULL, &c->rq);
1861 goto err_close_xdp_sq;
1863 err = mlx5e_open_xdpsq(c, params, &cparam->xdp_sq, NULL, &c->xdpsq, true);
1870 mlx5e_close_rq(&c->rq);
1874 mlx5e_close_xdpsq(&c->rq_xdpsq);
1880 mlx5e_close_icosq(&c->icosq);
1883 napi_disable(&c->napi);
1886 mlx5e_close_cq(&c->rq_xdpsq.cq);
1889 mlx5e_close_cq(&c->rq.cq);
1891 err_close_xdp_tx_cqs:
1892 mlx5e_close_cq(&c->xdpsq.cq);
1895 mlx5e_close_tx_cqs(c);
1898 mlx5e_close_cq(&c->icosq.cq);
1903 static void mlx5e_close_queues(struct mlx5e_channel *c)
1905 mlx5e_close_xdpsq(&c->xdpsq);
1906 mlx5e_close_rq(&c->rq);
1908 mlx5e_close_xdpsq(&c->rq_xdpsq);
1910 mlx5e_close_icosq(&c->icosq);
1911 napi_disable(&c->napi);
1913 mlx5e_close_cq(&c->rq_xdpsq.cq);
1914 mlx5e_close_cq(&c->rq.cq);
1915 mlx5e_close_cq(&c->xdpsq.cq);
1916 mlx5e_close_tx_cqs(c);
1917 mlx5e_close_cq(&c->icosq.cq);
1920 static u8 mlx5e_enumerate_lag_port(struct mlx5_core_dev *mdev, int ix)
1922 u16 port_aff_bias = mlx5_core_is_pf(mdev) ? 0 : MLX5_CAP_GEN(mdev, vhca_id);
1924 return (ix + port_aff_bias) % mlx5e_get_num_lag_ports(mdev);
1927 static int mlx5e_open_channel(struct mlx5e_priv *priv, int ix,
1928 struct mlx5e_params *params,
1929 struct mlx5e_channel_param *cparam,
1930 struct xdp_umem *umem,
1931 struct mlx5e_channel **cp)
1933 int cpu = cpumask_first(mlx5_comp_irq_get_affinity_mask(priv->mdev, ix));
1934 struct net_device *netdev = priv->netdev;
1935 struct mlx5e_xsk_param xsk;
1936 struct mlx5e_channel *c;
1941 err = mlx5_vector2eqn(priv->mdev, ix, &eqn, &irq);
1945 c = kvzalloc_node(sizeof(*c), GFP_KERNEL, cpu_to_node(cpu));
1950 c->mdev = priv->mdev;
1951 c->tstamp = &priv->tstamp;
1954 c->pdev = priv->mdev->device;
1955 c->netdev = priv->netdev;
1956 c->mkey_be = cpu_to_be32(priv->mdev->mlx5e_res.mkey.key);
1957 c->num_tc = params->num_tc;
1958 c->xdp = !!params->xdp_prog;
1959 c->stats = &priv->channel_stats[ix].ch;
1960 c->irq_desc = irq_to_desc(irq);
1961 c->lag_port = mlx5e_enumerate_lag_port(priv->mdev, ix);
1963 netif_napi_add(netdev, &c->napi, mlx5e_napi_poll, 64);
1965 err = mlx5e_open_queues(c, params, cparam);
1970 mlx5e_build_xsk_param(umem, &xsk);
1971 err = mlx5e_open_xsk(priv, params, &xsk, umem, c);
1973 goto err_close_queues;
1981 mlx5e_close_queues(c);
1984 netif_napi_del(&c->napi);
1991 static void mlx5e_activate_channel(struct mlx5e_channel *c)
1995 for (tc = 0; tc < c->num_tc; tc++)
1996 mlx5e_activate_txqsq(&c->sq[tc]);
1997 mlx5e_activate_icosq(&c->icosq);
1998 mlx5e_activate_rq(&c->rq);
2000 if (test_bit(MLX5E_CHANNEL_STATE_XSK, c->state))
2001 mlx5e_activate_xsk(c);
2004 static void mlx5e_deactivate_channel(struct mlx5e_channel *c)
2008 if (test_bit(MLX5E_CHANNEL_STATE_XSK, c->state))
2009 mlx5e_deactivate_xsk(c);
2011 mlx5e_deactivate_rq(&c->rq);
2012 mlx5e_deactivate_icosq(&c->icosq);
2013 for (tc = 0; tc < c->num_tc; tc++)
2014 mlx5e_deactivate_txqsq(&c->sq[tc]);
2017 static void mlx5e_close_channel(struct mlx5e_channel *c)
2019 if (test_bit(MLX5E_CHANNEL_STATE_XSK, c->state))
2021 mlx5e_close_queues(c);
2022 netif_napi_del(&c->napi);
2027 #define DEFAULT_FRAG_SIZE (2048)
2029 static void mlx5e_build_rq_frags_info(struct mlx5_core_dev *mdev,
2030 struct mlx5e_params *params,
2031 struct mlx5e_xsk_param *xsk,
2032 struct mlx5e_rq_frags_info *info)
2034 u32 byte_count = MLX5E_SW2HW_MTU(params, params->sw_mtu);
2035 int frag_size_max = DEFAULT_FRAG_SIZE;
2039 #ifdef CONFIG_MLX5_EN_IPSEC
2040 if (MLX5_IPSEC_DEV(mdev))
2041 byte_count += MLX5E_METADATA_ETHER_LEN;
2044 if (mlx5e_rx_is_linear_skb(params, xsk)) {
2047 frag_stride = mlx5e_rx_get_linear_frag_sz(params, xsk);
2048 frag_stride = roundup_pow_of_two(frag_stride);
2050 info->arr[0].frag_size = byte_count;
2051 info->arr[0].frag_stride = frag_stride;
2052 info->num_frags = 1;
2053 info->wqe_bulk = PAGE_SIZE / frag_stride;
2057 if (byte_count > PAGE_SIZE +
2058 (MLX5E_MAX_RX_FRAGS - 1) * frag_size_max)
2059 frag_size_max = PAGE_SIZE;
2062 while (buf_size < byte_count) {
2063 int frag_size = byte_count - buf_size;
2065 if (i < MLX5E_MAX_RX_FRAGS - 1)
2066 frag_size = min(frag_size, frag_size_max);
2068 info->arr[i].frag_size = frag_size;
2069 info->arr[i].frag_stride = roundup_pow_of_two(frag_size);
2071 buf_size += frag_size;
2074 info->num_frags = i;
2075 /* number of different wqes sharing a page */
2076 info->wqe_bulk = 1 + (info->num_frags % 2);
2079 info->wqe_bulk = max_t(u8, info->wqe_bulk, 8);
2080 info->log_num_frags = order_base_2(info->num_frags);
2083 static inline u8 mlx5e_get_rqwq_log_stride(u8 wq_type, int ndsegs)
2085 int sz = sizeof(struct mlx5_wqe_data_seg) * ndsegs;
2088 case MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ:
2089 sz += sizeof(struct mlx5e_rx_wqe_ll);
2091 default: /* MLX5_WQ_TYPE_CYCLIC */
2092 sz += sizeof(struct mlx5e_rx_wqe_cyc);
2095 return order_base_2(sz);
2098 static u8 mlx5e_get_rq_log_wq_sz(void *rqc)
2100 void *wq = MLX5_ADDR_OF(rqc, rqc, wq);
2102 return MLX5_GET(wq, wq, log_wq_sz);
2105 void mlx5e_build_rq_param(struct mlx5e_priv *priv,
2106 struct mlx5e_params *params,
2107 struct mlx5e_xsk_param *xsk,
2108 struct mlx5e_rq_param *param)
2110 struct mlx5_core_dev *mdev = priv->mdev;
2111 void *rqc = param->rqc;
2112 void *wq = MLX5_ADDR_OF(rqc, rqc, wq);
2115 switch (params->rq_wq_type) {
2116 case MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ:
2117 MLX5_SET(wq, wq, log_wqe_num_of_strides,
2118 mlx5e_mpwqe_get_log_num_strides(mdev, params, xsk) -
2119 MLX5_MPWQE_LOG_NUM_STRIDES_BASE);
2120 MLX5_SET(wq, wq, log_wqe_stride_size,
2121 mlx5e_mpwqe_get_log_stride_size(mdev, params, xsk) -
2122 MLX5_MPWQE_LOG_STRIDE_SZ_BASE);
2123 MLX5_SET(wq, wq, log_wq_sz, mlx5e_mpwqe_get_log_rq_size(params, xsk));
2125 default: /* MLX5_WQ_TYPE_CYCLIC */
2126 MLX5_SET(wq, wq, log_wq_sz, params->log_rq_mtu_frames);
2127 mlx5e_build_rq_frags_info(mdev, params, xsk, ¶m->frags_info);
2128 ndsegs = param->frags_info.num_frags;
2131 MLX5_SET(wq, wq, wq_type, params->rq_wq_type);
2132 MLX5_SET(wq, wq, end_padding_mode, MLX5_WQ_END_PAD_MODE_ALIGN);
2133 MLX5_SET(wq, wq, log_wq_stride,
2134 mlx5e_get_rqwq_log_stride(params->rq_wq_type, ndsegs));
2135 MLX5_SET(wq, wq, pd, mdev->mlx5e_res.pdn);
2136 MLX5_SET(rqc, rqc, counter_set_id, priv->q_counter);
2137 MLX5_SET(rqc, rqc, vsd, params->vlan_strip_disable);
2138 MLX5_SET(rqc, rqc, scatter_fcs, params->scatter_fcs_en);
2140 param->wq.buf_numa_node = dev_to_node(mdev->device);
2143 static void mlx5e_build_drop_rq_param(struct mlx5e_priv *priv,
2144 struct mlx5e_rq_param *param)
2146 struct mlx5_core_dev *mdev = priv->mdev;
2147 void *rqc = param->rqc;
2148 void *wq = MLX5_ADDR_OF(rqc, rqc, wq);
2150 MLX5_SET(wq, wq, wq_type, MLX5_WQ_TYPE_CYCLIC);
2151 MLX5_SET(wq, wq, log_wq_stride,
2152 mlx5e_get_rqwq_log_stride(MLX5_WQ_TYPE_CYCLIC, 1));
2153 MLX5_SET(rqc, rqc, counter_set_id, priv->drop_rq_q_counter);
2155 param->wq.buf_numa_node = dev_to_node(mdev->device);
2158 void mlx5e_build_sq_param_common(struct mlx5e_priv *priv,
2159 struct mlx5e_sq_param *param)
2161 void *sqc = param->sqc;
2162 void *wq = MLX5_ADDR_OF(sqc, sqc, wq);
2164 MLX5_SET(wq, wq, log_wq_stride, ilog2(MLX5_SEND_WQE_BB));
2165 MLX5_SET(wq, wq, pd, priv->mdev->mlx5e_res.pdn);
2167 param->wq.buf_numa_node = dev_to_node(priv->mdev->device);
2170 static void mlx5e_build_sq_param(struct mlx5e_priv *priv,
2171 struct mlx5e_params *params,
2172 struct mlx5e_sq_param *param)
2174 void *sqc = param->sqc;
2175 void *wq = MLX5_ADDR_OF(sqc, sqc, wq);
2178 allow_swp = mlx5_geneve_tx_allowed(priv->mdev) ||
2179 !!MLX5_IPSEC_DEV(priv->mdev);
2180 mlx5e_build_sq_param_common(priv, param);
2181 MLX5_SET(wq, wq, log_wq_sz, params->log_sq_size);
2182 MLX5_SET(sqc, sqc, allow_swp, allow_swp);
2185 static void mlx5e_build_common_cq_param(struct mlx5e_priv *priv,
2186 struct mlx5e_cq_param *param)
2188 void *cqc = param->cqc;
2190 MLX5_SET(cqc, cqc, uar_page, priv->mdev->priv.uar->index);
2191 if (MLX5_CAP_GEN(priv->mdev, cqe_128_always) && cache_line_size() >= 128)
2192 MLX5_SET(cqc, cqc, cqe_sz, CQE_STRIDE_128_PAD);
2195 void mlx5e_build_rx_cq_param(struct mlx5e_priv *priv,
2196 struct mlx5e_params *params,
2197 struct mlx5e_xsk_param *xsk,
2198 struct mlx5e_cq_param *param)
2200 struct mlx5_core_dev *mdev = priv->mdev;
2201 void *cqc = param->cqc;
2204 switch (params->rq_wq_type) {
2205 case MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ:
2206 log_cq_size = mlx5e_mpwqe_get_log_rq_size(params, xsk) +
2207 mlx5e_mpwqe_get_log_num_strides(mdev, params, xsk);
2209 default: /* MLX5_WQ_TYPE_CYCLIC */
2210 log_cq_size = params->log_rq_mtu_frames;
2213 MLX5_SET(cqc, cqc, log_cq_size, log_cq_size);
2214 if (MLX5E_GET_PFLAG(params, MLX5E_PFLAG_RX_CQE_COMPRESS)) {
2215 MLX5_SET(cqc, cqc, mini_cqe_res_format, MLX5_CQE_FORMAT_CSUM);
2216 MLX5_SET(cqc, cqc, cqe_comp_en, 1);
2219 mlx5e_build_common_cq_param(priv, param);
2220 param->cq_period_mode = params->rx_cq_moderation.cq_period_mode;
2223 void mlx5e_build_tx_cq_param(struct mlx5e_priv *priv,
2224 struct mlx5e_params *params,
2225 struct mlx5e_cq_param *param)
2227 void *cqc = param->cqc;
2229 MLX5_SET(cqc, cqc, log_cq_size, params->log_sq_size);
2231 mlx5e_build_common_cq_param(priv, param);
2232 param->cq_period_mode = params->tx_cq_moderation.cq_period_mode;
2235 void mlx5e_build_ico_cq_param(struct mlx5e_priv *priv,
2237 struct mlx5e_cq_param *param)
2239 void *cqc = param->cqc;
2241 MLX5_SET(cqc, cqc, log_cq_size, log_wq_size);
2243 mlx5e_build_common_cq_param(priv, param);
2245 param->cq_period_mode = DIM_CQ_PERIOD_MODE_START_FROM_EQE;
2248 void mlx5e_build_icosq_param(struct mlx5e_priv *priv,
2250 struct mlx5e_sq_param *param)
2252 void *sqc = param->sqc;
2253 void *wq = MLX5_ADDR_OF(sqc, sqc, wq);
2255 mlx5e_build_sq_param_common(priv, param);
2257 MLX5_SET(wq, wq, log_wq_sz, log_wq_size);
2258 MLX5_SET(sqc, sqc, reg_umr, MLX5_CAP_ETH(priv->mdev, reg_umr_sq));
2261 void mlx5e_build_xdpsq_param(struct mlx5e_priv *priv,
2262 struct mlx5e_params *params,
2263 struct mlx5e_sq_param *param)
2265 void *sqc = param->sqc;
2266 void *wq = MLX5_ADDR_OF(sqc, sqc, wq);
2268 mlx5e_build_sq_param_common(priv, param);
2269 MLX5_SET(wq, wq, log_wq_sz, params->log_sq_size);
2270 param->is_mpw = MLX5E_GET_PFLAG(params, MLX5E_PFLAG_XDP_TX_MPWQE);
2273 static u8 mlx5e_build_icosq_log_wq_sz(struct mlx5e_params *params,
2274 struct mlx5e_rq_param *rqp)
2276 switch (params->rq_wq_type) {
2277 case MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ:
2278 return order_base_2(MLX5E_UMR_WQEBBS) +
2279 mlx5e_get_rq_log_wq_sz(rqp->rqc);
2280 default: /* MLX5_WQ_TYPE_CYCLIC */
2281 return MLX5E_PARAMS_MINIMUM_LOG_SQ_SIZE;
2285 static void mlx5e_build_channel_param(struct mlx5e_priv *priv,
2286 struct mlx5e_params *params,
2287 struct mlx5e_channel_param *cparam)
2291 mlx5e_build_rq_param(priv, params, NULL, &cparam->rq);
2293 icosq_log_wq_sz = mlx5e_build_icosq_log_wq_sz(params, &cparam->rq);
2295 mlx5e_build_sq_param(priv, params, &cparam->sq);
2296 mlx5e_build_xdpsq_param(priv, params, &cparam->xdp_sq);
2297 mlx5e_build_icosq_param(priv, icosq_log_wq_sz, &cparam->icosq);
2298 mlx5e_build_rx_cq_param(priv, params, NULL, &cparam->rx_cq);
2299 mlx5e_build_tx_cq_param(priv, params, &cparam->tx_cq);
2300 mlx5e_build_ico_cq_param(priv, icosq_log_wq_sz, &cparam->icosq_cq);
2303 int mlx5e_open_channels(struct mlx5e_priv *priv,
2304 struct mlx5e_channels *chs)
2306 struct mlx5e_channel_param *cparam;
2310 chs->num = chs->params.num_channels;
2312 chs->c = kcalloc(chs->num, sizeof(struct mlx5e_channel *), GFP_KERNEL);
2313 cparam = kvzalloc(sizeof(struct mlx5e_channel_param), GFP_KERNEL);
2314 if (!chs->c || !cparam)
2317 mlx5e_build_channel_param(priv, &chs->params, cparam);
2318 for (i = 0; i < chs->num; i++) {
2319 struct xdp_umem *umem = NULL;
2321 if (chs->params.xdp_prog)
2322 umem = mlx5e_xsk_get_umem(&chs->params, chs->params.xsk, i);
2324 err = mlx5e_open_channel(priv, i, &chs->params, cparam, umem, &chs->c[i]);
2326 goto err_close_channels;
2329 mlx5e_health_channels_update(priv);
2334 for (i--; i >= 0; i--)
2335 mlx5e_close_channel(chs->c[i]);
2344 static void mlx5e_activate_channels(struct mlx5e_channels *chs)
2348 for (i = 0; i < chs->num; i++)
2349 mlx5e_activate_channel(chs->c[i]);
2352 #define MLX5E_RQ_WQES_TIMEOUT 20000 /* msecs */
2354 static int mlx5e_wait_channels_min_rx_wqes(struct mlx5e_channels *chs)
2359 for (i = 0; i < chs->num; i++) {
2360 int timeout = err ? 0 : MLX5E_RQ_WQES_TIMEOUT;
2362 err |= mlx5e_wait_for_min_rx_wqes(&chs->c[i]->rq, timeout);
2364 /* Don't wait on the XSK RQ, because the newer xdpsock sample
2365 * doesn't provide any Fill Ring entries at the setup stage.
2369 return err ? -ETIMEDOUT : 0;
2372 static void mlx5e_deactivate_channels(struct mlx5e_channels *chs)
2376 for (i = 0; i < chs->num; i++)
2377 mlx5e_deactivate_channel(chs->c[i]);
2380 void mlx5e_close_channels(struct mlx5e_channels *chs)
2384 for (i = 0; i < chs->num; i++)
2385 mlx5e_close_channel(chs->c[i]);
2392 mlx5e_create_rqt(struct mlx5e_priv *priv, int sz, struct mlx5e_rqt *rqt)
2394 struct mlx5_core_dev *mdev = priv->mdev;
2401 inlen = MLX5_ST_SZ_BYTES(create_rqt_in) + sizeof(u32) * sz;
2402 in = kvzalloc(inlen, GFP_KERNEL);
2406 rqtc = MLX5_ADDR_OF(create_rqt_in, in, rqt_context);
2408 MLX5_SET(rqtc, rqtc, rqt_actual_size, sz);
2409 MLX5_SET(rqtc, rqtc, rqt_max_size, sz);
2411 for (i = 0; i < sz; i++)
2412 MLX5_SET(rqtc, rqtc, rq_num[i], priv->drop_rq.rqn);
2414 err = mlx5_core_create_rqt(mdev, in, inlen, &rqt->rqtn);
2416 rqt->enabled = true;
2422 void mlx5e_destroy_rqt(struct mlx5e_priv *priv, struct mlx5e_rqt *rqt)
2424 rqt->enabled = false;
2425 mlx5_core_destroy_rqt(priv->mdev, rqt->rqtn);
2428 int mlx5e_create_indirect_rqt(struct mlx5e_priv *priv)
2430 struct mlx5e_rqt *rqt = &priv->indir_rqt;
2433 err = mlx5e_create_rqt(priv, MLX5E_INDIR_RQT_SIZE, rqt);
2435 mlx5_core_warn(priv->mdev, "create indirect rqts failed, %d\n", err);
2439 int mlx5e_create_direct_rqts(struct mlx5e_priv *priv, struct mlx5e_tir *tirs)
2444 for (ix = 0; ix < priv->max_nch; ix++) {
2445 err = mlx5e_create_rqt(priv, 1 /*size */, &tirs[ix].rqt);
2447 goto err_destroy_rqts;
2453 mlx5_core_warn(priv->mdev, "create rqts failed, %d\n", err);
2454 for (ix--; ix >= 0; ix--)
2455 mlx5e_destroy_rqt(priv, &tirs[ix].rqt);
2460 void mlx5e_destroy_direct_rqts(struct mlx5e_priv *priv, struct mlx5e_tir *tirs)
2464 for (i = 0; i < priv->max_nch; i++)
2465 mlx5e_destroy_rqt(priv, &tirs[i].rqt);
2468 static int mlx5e_rx_hash_fn(int hfunc)
2470 return (hfunc == ETH_RSS_HASH_TOP) ?
2471 MLX5_RX_HASH_FN_TOEPLITZ :
2472 MLX5_RX_HASH_FN_INVERTED_XOR8;
2475 int mlx5e_bits_invert(unsigned long a, int size)
2480 for (i = 0; i < size; i++)
2481 inv |= (test_bit(size - i - 1, &a) ? 1 : 0) << i;
2486 static void mlx5e_fill_rqt_rqns(struct mlx5e_priv *priv, int sz,
2487 struct mlx5e_redirect_rqt_param rrp, void *rqtc)
2491 for (i = 0; i < sz; i++) {
2497 if (rrp.rss.hfunc == ETH_RSS_HASH_XOR)
2498 ix = mlx5e_bits_invert(i, ilog2(sz));
2500 ix = priv->rss_params.indirection_rqt[ix];
2501 rqn = rrp.rss.channels->c[ix]->rq.rqn;
2505 MLX5_SET(rqtc, rqtc, rq_num[i], rqn);
2509 int mlx5e_redirect_rqt(struct mlx5e_priv *priv, u32 rqtn, int sz,
2510 struct mlx5e_redirect_rqt_param rrp)
2512 struct mlx5_core_dev *mdev = priv->mdev;
2518 inlen = MLX5_ST_SZ_BYTES(modify_rqt_in) + sizeof(u32) * sz;
2519 in = kvzalloc(inlen, GFP_KERNEL);
2523 rqtc = MLX5_ADDR_OF(modify_rqt_in, in, ctx);
2525 MLX5_SET(rqtc, rqtc, rqt_actual_size, sz);
2526 MLX5_SET(modify_rqt_in, in, bitmask.rqn_list, 1);
2527 mlx5e_fill_rqt_rqns(priv, sz, rrp, rqtc);
2528 err = mlx5_core_modify_rqt(mdev, rqtn, in, inlen);
2534 static u32 mlx5e_get_direct_rqn(struct mlx5e_priv *priv, int ix,
2535 struct mlx5e_redirect_rqt_param rrp)
2540 if (ix >= rrp.rss.channels->num)
2541 return priv->drop_rq.rqn;
2543 return rrp.rss.channels->c[ix]->rq.rqn;
2546 static void mlx5e_redirect_rqts(struct mlx5e_priv *priv,
2547 struct mlx5e_redirect_rqt_param rrp)
2552 if (priv->indir_rqt.enabled) {
2554 rqtn = priv->indir_rqt.rqtn;
2555 mlx5e_redirect_rqt(priv, rqtn, MLX5E_INDIR_RQT_SIZE, rrp);
2558 for (ix = 0; ix < priv->max_nch; ix++) {
2559 struct mlx5e_redirect_rqt_param direct_rrp = {
2562 .rqn = mlx5e_get_direct_rqn(priv, ix, rrp)
2566 /* Direct RQ Tables */
2567 if (!priv->direct_tir[ix].rqt.enabled)
2570 rqtn = priv->direct_tir[ix].rqt.rqtn;
2571 mlx5e_redirect_rqt(priv, rqtn, 1, direct_rrp);
2575 static void mlx5e_redirect_rqts_to_channels(struct mlx5e_priv *priv,
2576 struct mlx5e_channels *chs)
2578 struct mlx5e_redirect_rqt_param rrp = {
2583 .hfunc = priv->rss_params.hfunc,
2588 mlx5e_redirect_rqts(priv, rrp);
2591 static void mlx5e_redirect_rqts_to_drop(struct mlx5e_priv *priv)
2593 struct mlx5e_redirect_rqt_param drop_rrp = {
2596 .rqn = priv->drop_rq.rqn,
2600 mlx5e_redirect_rqts(priv, drop_rrp);
2603 static const struct mlx5e_tirc_config tirc_default_config[MLX5E_NUM_INDIR_TIRS] = {
2604 [MLX5E_TT_IPV4_TCP] = { .l3_prot_type = MLX5_L3_PROT_TYPE_IPV4,
2605 .l4_prot_type = MLX5_L4_PROT_TYPE_TCP,
2606 .rx_hash_fields = MLX5_HASH_IP_L4PORTS,
2608 [MLX5E_TT_IPV6_TCP] = { .l3_prot_type = MLX5_L3_PROT_TYPE_IPV6,
2609 .l4_prot_type = MLX5_L4_PROT_TYPE_TCP,
2610 .rx_hash_fields = MLX5_HASH_IP_L4PORTS,
2612 [MLX5E_TT_IPV4_UDP] = { .l3_prot_type = MLX5_L3_PROT_TYPE_IPV4,
2613 .l4_prot_type = MLX5_L4_PROT_TYPE_UDP,
2614 .rx_hash_fields = MLX5_HASH_IP_L4PORTS,
2616 [MLX5E_TT_IPV6_UDP] = { .l3_prot_type = MLX5_L3_PROT_TYPE_IPV6,
2617 .l4_prot_type = MLX5_L4_PROT_TYPE_UDP,
2618 .rx_hash_fields = MLX5_HASH_IP_L4PORTS,
2620 [MLX5E_TT_IPV4_IPSEC_AH] = { .l3_prot_type = MLX5_L3_PROT_TYPE_IPV4,
2622 .rx_hash_fields = MLX5_HASH_IP_IPSEC_SPI,
2624 [MLX5E_TT_IPV6_IPSEC_AH] = { .l3_prot_type = MLX5_L3_PROT_TYPE_IPV6,
2626 .rx_hash_fields = MLX5_HASH_IP_IPSEC_SPI,
2628 [MLX5E_TT_IPV4_IPSEC_ESP] = { .l3_prot_type = MLX5_L3_PROT_TYPE_IPV4,
2630 .rx_hash_fields = MLX5_HASH_IP_IPSEC_SPI,
2632 [MLX5E_TT_IPV6_IPSEC_ESP] = { .l3_prot_type = MLX5_L3_PROT_TYPE_IPV6,
2634 .rx_hash_fields = MLX5_HASH_IP_IPSEC_SPI,
2636 [MLX5E_TT_IPV4] = { .l3_prot_type = MLX5_L3_PROT_TYPE_IPV4,
2638 .rx_hash_fields = MLX5_HASH_IP,
2640 [MLX5E_TT_IPV6] = { .l3_prot_type = MLX5_L3_PROT_TYPE_IPV6,
2642 .rx_hash_fields = MLX5_HASH_IP,
2646 struct mlx5e_tirc_config mlx5e_tirc_get_default_config(enum mlx5e_traffic_types tt)
2648 return tirc_default_config[tt];
2651 static void mlx5e_build_tir_ctx_lro(struct mlx5e_params *params, void *tirc)
2653 if (!params->lro_en)
2656 #define ROUGH_MAX_L2_L3_HDR_SZ 256
2658 MLX5_SET(tirc, tirc, lro_enable_mask,
2659 MLX5_TIRC_LRO_ENABLE_MASK_IPV4_LRO |
2660 MLX5_TIRC_LRO_ENABLE_MASK_IPV6_LRO);
2661 MLX5_SET(tirc, tirc, lro_max_ip_payload_size,
2662 (MLX5E_PARAMS_DEFAULT_LRO_WQE_SZ - ROUGH_MAX_L2_L3_HDR_SZ) >> 8);
2663 MLX5_SET(tirc, tirc, lro_timeout_period_usecs, params->lro_timeout);
2666 void mlx5e_build_indir_tir_ctx_hash(struct mlx5e_rss_params *rss_params,
2667 const struct mlx5e_tirc_config *ttconfig,
2668 void *tirc, bool inner)
2670 void *hfso = inner ? MLX5_ADDR_OF(tirc, tirc, rx_hash_field_selector_inner) :
2671 MLX5_ADDR_OF(tirc, tirc, rx_hash_field_selector_outer);
2673 MLX5_SET(tirc, tirc, rx_hash_fn, mlx5e_rx_hash_fn(rss_params->hfunc));
2674 if (rss_params->hfunc == ETH_RSS_HASH_TOP) {
2675 void *rss_key = MLX5_ADDR_OF(tirc, tirc,
2676 rx_hash_toeplitz_key);
2677 size_t len = MLX5_FLD_SZ_BYTES(tirc,
2678 rx_hash_toeplitz_key);
2680 MLX5_SET(tirc, tirc, rx_hash_symmetric, 1);
2681 memcpy(rss_key, rss_params->toeplitz_hash_key, len);
2683 MLX5_SET(rx_hash_field_select, hfso, l3_prot_type,
2684 ttconfig->l3_prot_type);
2685 MLX5_SET(rx_hash_field_select, hfso, l4_prot_type,
2686 ttconfig->l4_prot_type);
2687 MLX5_SET(rx_hash_field_select, hfso, selected_fields,
2688 ttconfig->rx_hash_fields);
2691 static void mlx5e_update_rx_hash_fields(struct mlx5e_tirc_config *ttconfig,
2692 enum mlx5e_traffic_types tt,
2695 *ttconfig = tirc_default_config[tt];
2696 ttconfig->rx_hash_fields = rx_hash_fields;
2699 void mlx5e_modify_tirs_hash(struct mlx5e_priv *priv, void *in)
2701 void *tirc = MLX5_ADDR_OF(modify_tir_in, in, ctx);
2702 struct mlx5e_rss_params *rss = &priv->rss_params;
2703 struct mlx5_core_dev *mdev = priv->mdev;
2704 int ctxlen = MLX5_ST_SZ_BYTES(tirc);
2705 struct mlx5e_tirc_config ttconfig;
2708 MLX5_SET(modify_tir_in, in, bitmask.hash, 1);
2710 for (tt = 0; tt < MLX5E_NUM_INDIR_TIRS; tt++) {
2711 memset(tirc, 0, ctxlen);
2712 mlx5e_update_rx_hash_fields(&ttconfig, tt,
2713 rss->rx_hash_fields[tt]);
2714 mlx5e_build_indir_tir_ctx_hash(rss, &ttconfig, tirc, false);
2715 mlx5_core_modify_tir(mdev, priv->indir_tir[tt].tirn, in);
2718 /* Verify inner tirs resources allocated */
2719 if (!priv->inner_indir_tir[0].tirn)
2722 for (tt = 0; tt < MLX5E_NUM_INDIR_TIRS; tt++) {
2723 memset(tirc, 0, ctxlen);
2724 mlx5e_update_rx_hash_fields(&ttconfig, tt,
2725 rss->rx_hash_fields[tt]);
2726 mlx5e_build_indir_tir_ctx_hash(rss, &ttconfig, tirc, true);
2727 mlx5_core_modify_tir(mdev, priv->inner_indir_tir[tt].tirn, in);
2731 static int mlx5e_modify_tirs_lro(struct mlx5e_priv *priv)
2733 struct mlx5_core_dev *mdev = priv->mdev;
2742 inlen = MLX5_ST_SZ_BYTES(modify_tir_in);
2743 in = kvzalloc(inlen, GFP_KERNEL);
2747 MLX5_SET(modify_tir_in, in, bitmask.lro, 1);
2748 tirc = MLX5_ADDR_OF(modify_tir_in, in, ctx);
2750 mlx5e_build_tir_ctx_lro(&priv->channels.params, tirc);
2752 for (tt = 0; tt < MLX5E_NUM_INDIR_TIRS; tt++) {
2753 err = mlx5_core_modify_tir(mdev, priv->indir_tir[tt].tirn, in);
2758 for (ix = 0; ix < priv->max_nch; ix++) {
2759 err = mlx5_core_modify_tir(mdev, priv->direct_tir[ix].tirn, in);
2770 static MLX5E_DEFINE_PREACTIVATE_WRAPPER_CTX(mlx5e_modify_tirs_lro);
2772 static int mlx5e_set_mtu(struct mlx5_core_dev *mdev,
2773 struct mlx5e_params *params, u16 mtu)
2775 u16 hw_mtu = MLX5E_SW2HW_MTU(params, mtu);
2778 err = mlx5_set_port_mtu(mdev, hw_mtu, 1);
2782 /* Update vport context MTU */
2783 mlx5_modify_nic_vport_mtu(mdev, hw_mtu);
2787 static void mlx5e_query_mtu(struct mlx5_core_dev *mdev,
2788 struct mlx5e_params *params, u16 *mtu)
2793 err = mlx5_query_nic_vport_mtu(mdev, &hw_mtu);
2794 if (err || !hw_mtu) /* fallback to port oper mtu */
2795 mlx5_query_port_oper_mtu(mdev, &hw_mtu, 1);
2797 *mtu = MLX5E_HW2SW_MTU(params, hw_mtu);
2800 int mlx5e_set_dev_port_mtu(struct mlx5e_priv *priv)
2802 struct mlx5e_params *params = &priv->channels.params;
2803 struct net_device *netdev = priv->netdev;
2804 struct mlx5_core_dev *mdev = priv->mdev;
2808 err = mlx5e_set_mtu(mdev, params, params->sw_mtu);
2812 mlx5e_query_mtu(mdev, params, &mtu);
2813 if (mtu != params->sw_mtu)
2814 netdev_warn(netdev, "%s: VPort MTU %d is different than netdev mtu %d\n",
2815 __func__, mtu, params->sw_mtu);
2817 params->sw_mtu = mtu;
2821 MLX5E_DEFINE_PREACTIVATE_WRAPPER_CTX(mlx5e_set_dev_port_mtu);
2823 void mlx5e_set_netdev_mtu_boundaries(struct mlx5e_priv *priv)
2825 struct mlx5e_params *params = &priv->channels.params;
2826 struct net_device *netdev = priv->netdev;
2827 struct mlx5_core_dev *mdev = priv->mdev;
2830 /* MTU range: 68 - hw-specific max */
2831 netdev->min_mtu = ETH_MIN_MTU;
2833 mlx5_query_port_max_mtu(mdev, &max_mtu, 1);
2834 netdev->max_mtu = min_t(unsigned int, MLX5E_HW2SW_MTU(params, max_mtu),
2838 static void mlx5e_netdev_set_tcs(struct net_device *netdev, u16 nch, u8 ntc)
2842 netdev_reset_tc(netdev);
2847 netdev_set_num_tc(netdev, ntc);
2849 /* Map netdev TCs to offset 0
2850 * We have our own UP to TXQ mapping for QoS
2852 for (tc = 0; tc < ntc; tc++)
2853 netdev_set_tc_queue(netdev, tc, nch, 0);
2856 static int mlx5e_update_netdev_queues(struct mlx5e_priv *priv)
2858 struct net_device *netdev = priv->netdev;
2859 int num_txqs, num_rxqs, nch, ntc;
2860 int old_num_txqs, old_ntc;
2863 old_num_txqs = netdev->real_num_tx_queues;
2864 old_ntc = netdev->num_tc;
2866 nch = priv->channels.params.num_channels;
2867 ntc = priv->channels.params.num_tc;
2868 num_txqs = nch * ntc;
2869 num_rxqs = nch * priv->profile->rq_groups;
2871 mlx5e_netdev_set_tcs(netdev, nch, ntc);
2873 err = netif_set_real_num_tx_queues(netdev, num_txqs);
2875 netdev_warn(netdev, "netif_set_real_num_tx_queues failed, %d\n", err);
2878 err = netif_set_real_num_rx_queues(netdev, num_rxqs);
2880 netdev_warn(netdev, "netif_set_real_num_rx_queues failed, %d\n", err);
2887 /* netif_set_real_num_rx_queues could fail only when nch increased. Only
2888 * one of nch and ntc is changed in this function. That means, the call
2889 * to netif_set_real_num_tx_queues below should not fail, because it
2890 * decreases the number of TX queues.
2892 WARN_ON_ONCE(netif_set_real_num_tx_queues(netdev, old_num_txqs));
2895 mlx5e_netdev_set_tcs(netdev, old_num_txqs / old_ntc, old_ntc);
2899 static void mlx5e_set_default_xps_cpumasks(struct mlx5e_priv *priv,
2900 struct mlx5e_params *params)
2902 struct mlx5_core_dev *mdev = priv->mdev;
2903 int num_comp_vectors, ix, irq;
2905 num_comp_vectors = mlx5_comp_vectors_count(mdev);
2907 for (ix = 0; ix < params->num_channels; ix++) {
2908 cpumask_clear(priv->scratchpad.cpumask);
2910 for (irq = ix; irq < num_comp_vectors; irq += params->num_channels) {
2911 int cpu = cpumask_first(mlx5_comp_irq_get_affinity_mask(mdev, irq));
2913 cpumask_set_cpu(cpu, priv->scratchpad.cpumask);
2916 netif_set_xps_queue(priv->netdev, priv->scratchpad.cpumask, ix);
2920 int mlx5e_num_channels_changed(struct mlx5e_priv *priv)
2922 u16 count = priv->channels.params.num_channels;
2925 err = mlx5e_update_netdev_queues(priv);
2929 mlx5e_set_default_xps_cpumasks(priv, &priv->channels.params);
2931 if (!netif_is_rxfh_configured(priv->netdev))
2932 mlx5e_build_default_indir_rqt(priv->rss_params.indirection_rqt,
2933 MLX5E_INDIR_RQT_SIZE, count);
2938 MLX5E_DEFINE_PREACTIVATE_WRAPPER_CTX(mlx5e_num_channels_changed);
2940 static void mlx5e_build_txq_maps(struct mlx5e_priv *priv)
2944 ch = priv->channels.num;
2946 for (i = 0; i < ch; i++) {
2949 for (tc = 0; tc < priv->channels.params.num_tc; tc++) {
2950 struct mlx5e_channel *c = priv->channels.c[i];
2951 struct mlx5e_txqsq *sq = &c->sq[tc];
2953 priv->txq2sq[sq->txq_ix] = sq;
2954 priv->channel_tc2realtxq[i][tc] = i + tc * ch;
2959 void mlx5e_activate_priv_channels(struct mlx5e_priv *priv)
2961 mlx5e_build_txq_maps(priv);
2962 mlx5e_activate_channels(&priv->channels);
2963 mlx5e_xdp_tx_enable(priv);
2964 netif_tx_start_all_queues(priv->netdev);
2966 if (mlx5e_is_vport_rep(priv))
2967 mlx5e_add_sqs_fwd_rules(priv);
2969 mlx5e_wait_channels_min_rx_wqes(&priv->channels);
2970 mlx5e_redirect_rqts_to_channels(priv, &priv->channels);
2972 mlx5e_xsk_redirect_rqts_to_channels(priv, &priv->channels);
2975 void mlx5e_deactivate_priv_channels(struct mlx5e_priv *priv)
2977 mlx5e_xsk_redirect_rqts_to_drop(priv, &priv->channels);
2979 mlx5e_redirect_rqts_to_drop(priv);
2981 if (mlx5e_is_vport_rep(priv))
2982 mlx5e_remove_sqs_fwd_rules(priv);
2984 /* FIXME: This is a W/A only for tx timeout watch dog false alarm when
2985 * polling for inactive tx queues.
2987 netif_tx_stop_all_queues(priv->netdev);
2988 netif_tx_disable(priv->netdev);
2989 mlx5e_xdp_tx_disable(priv);
2990 mlx5e_deactivate_channels(&priv->channels);
2993 static int mlx5e_switch_priv_channels(struct mlx5e_priv *priv,
2994 struct mlx5e_channels *new_chs,
2995 mlx5e_fp_preactivate preactivate,
2998 struct net_device *netdev = priv->netdev;
2999 struct mlx5e_channels old_chs;
3003 carrier_ok = netif_carrier_ok(netdev);
3004 netif_carrier_off(netdev);
3006 mlx5e_deactivate_priv_channels(priv);
3008 old_chs = priv->channels;
3009 priv->channels = *new_chs;
3011 /* New channels are ready to roll, call the preactivate hook if needed
3012 * to modify HW settings or update kernel parameters.
3015 err = preactivate(priv, context);
3017 priv->channels = old_chs;
3022 mlx5e_close_channels(&old_chs);
3023 priv->profile->update_rx(priv);
3026 mlx5e_activate_priv_channels(priv);
3028 /* return carrier back if needed */
3030 netif_carrier_on(netdev);
3035 int mlx5e_safe_switch_channels(struct mlx5e_priv *priv,
3036 struct mlx5e_channels *new_chs,
3037 mlx5e_fp_preactivate preactivate,
3042 err = mlx5e_open_channels(priv, new_chs);
3046 err = mlx5e_switch_priv_channels(priv, new_chs, preactivate, context);
3053 mlx5e_close_channels(new_chs);
3058 int mlx5e_safe_reopen_channels(struct mlx5e_priv *priv)
3060 struct mlx5e_channels new_channels = {};
3062 new_channels.params = priv->channels.params;
3063 return mlx5e_safe_switch_channels(priv, &new_channels, NULL, NULL);
3066 void mlx5e_timestamp_init(struct mlx5e_priv *priv)
3068 priv->tstamp.tx_type = HWTSTAMP_TX_OFF;
3069 priv->tstamp.rx_filter = HWTSTAMP_FILTER_NONE;
3072 static void mlx5e_modify_admin_state(struct mlx5_core_dev *mdev,
3073 enum mlx5_port_status state)
3075 struct mlx5_eswitch *esw = mdev->priv.eswitch;
3076 int vport_admin_state;
3078 mlx5_set_port_admin_status(mdev, state);
3080 if (!MLX5_ESWITCH_MANAGER(mdev) || mlx5_eswitch_mode(esw) == MLX5_ESWITCH_OFFLOADS)
3083 if (state == MLX5_PORT_UP)
3084 vport_admin_state = MLX5_VPORT_ADMIN_STATE_AUTO;
3086 vport_admin_state = MLX5_VPORT_ADMIN_STATE_DOWN;
3088 mlx5_eswitch_set_vport_state(esw, MLX5_VPORT_UPLINK, vport_admin_state);
3091 int mlx5e_open_locked(struct net_device *netdev)
3093 struct mlx5e_priv *priv = netdev_priv(netdev);
3096 set_bit(MLX5E_STATE_OPENED, &priv->state);
3098 err = mlx5e_open_channels(priv, &priv->channels);
3100 goto err_clear_state_opened_flag;
3102 priv->profile->update_rx(priv);
3103 mlx5e_activate_priv_channels(priv);
3104 if (priv->profile->update_carrier)
3105 priv->profile->update_carrier(priv);
3107 mlx5e_queue_update_stats(priv);
3110 err_clear_state_opened_flag:
3111 clear_bit(MLX5E_STATE_OPENED, &priv->state);
3115 int mlx5e_open(struct net_device *netdev)
3117 struct mlx5e_priv *priv = netdev_priv(netdev);
3120 mutex_lock(&priv->state_lock);
3121 err = mlx5e_open_locked(netdev);
3123 mlx5e_modify_admin_state(priv->mdev, MLX5_PORT_UP);
3124 mutex_unlock(&priv->state_lock);
3129 int mlx5e_close_locked(struct net_device *netdev)
3131 struct mlx5e_priv *priv = netdev_priv(netdev);
3133 /* May already be CLOSED in case a previous configuration operation
3134 * (e.g RX/TX queue size change) that involves close&open failed.
3136 if (!test_bit(MLX5E_STATE_OPENED, &priv->state))
3139 clear_bit(MLX5E_STATE_OPENED, &priv->state);
3141 netif_carrier_off(priv->netdev);
3142 mlx5e_deactivate_priv_channels(priv);
3143 mlx5e_close_channels(&priv->channels);
3148 int mlx5e_close(struct net_device *netdev)
3150 struct mlx5e_priv *priv = netdev_priv(netdev);
3153 if (!netif_device_present(netdev))
3156 mutex_lock(&priv->state_lock);
3157 mlx5e_modify_admin_state(priv->mdev, MLX5_PORT_DOWN);
3158 err = mlx5e_close_locked(netdev);
3159 mutex_unlock(&priv->state_lock);
3164 static int mlx5e_alloc_drop_rq(struct mlx5_core_dev *mdev,
3165 struct mlx5e_rq *rq,
3166 struct mlx5e_rq_param *param)
3168 void *rqc = param->rqc;
3169 void *rqc_wq = MLX5_ADDR_OF(rqc, rqc, wq);
3172 param->wq.db_numa_node = param->wq.buf_numa_node;
3174 err = mlx5_wq_cyc_create(mdev, ¶m->wq, rqc_wq, &rq->wqe.wq,
3179 /* Mark as unused given "Drop-RQ" packets never reach XDP */
3180 xdp_rxq_info_unused(&rq->xdp_rxq);
3187 static int mlx5e_alloc_drop_cq(struct mlx5_core_dev *mdev,
3188 struct mlx5e_cq *cq,
3189 struct mlx5e_cq_param *param)
3191 param->wq.buf_numa_node = dev_to_node(mdev->device);
3192 param->wq.db_numa_node = dev_to_node(mdev->device);
3194 return mlx5e_alloc_cq_common(mdev, param, cq);
3197 int mlx5e_open_drop_rq(struct mlx5e_priv *priv,
3198 struct mlx5e_rq *drop_rq)
3200 struct mlx5_core_dev *mdev = priv->mdev;
3201 struct mlx5e_cq_param cq_param = {};
3202 struct mlx5e_rq_param rq_param = {};
3203 struct mlx5e_cq *cq = &drop_rq->cq;
3206 mlx5e_build_drop_rq_param(priv, &rq_param);
3208 err = mlx5e_alloc_drop_cq(mdev, cq, &cq_param);
3212 err = mlx5e_create_cq(cq, &cq_param);
3216 err = mlx5e_alloc_drop_rq(mdev, drop_rq, &rq_param);
3218 goto err_destroy_cq;
3220 err = mlx5e_create_rq(drop_rq, &rq_param);
3224 err = mlx5e_modify_rq_state(drop_rq, MLX5_RQC_STATE_RST, MLX5_RQC_STATE_RDY);
3226 mlx5_core_warn(priv->mdev, "modify_rq_state failed, rx_if_down_packets won't be counted %d\n", err);
3231 mlx5e_free_rq(drop_rq);
3234 mlx5e_destroy_cq(cq);
3242 void mlx5e_close_drop_rq(struct mlx5e_rq *drop_rq)
3244 mlx5e_destroy_rq(drop_rq);
3245 mlx5e_free_rq(drop_rq);
3246 mlx5e_destroy_cq(&drop_rq->cq);
3247 mlx5e_free_cq(&drop_rq->cq);
3250 int mlx5e_create_tis(struct mlx5_core_dev *mdev, void *in, u32 *tisn)
3252 void *tisc = MLX5_ADDR_OF(create_tis_in, in, ctx);
3254 MLX5_SET(tisc, tisc, transport_domain, mdev->mlx5e_res.td.tdn);
3256 if (MLX5_GET(tisc, tisc, tls_en))
3257 MLX5_SET(tisc, tisc, pd, mdev->mlx5e_res.pdn);
3259 if (mlx5_lag_is_lacp_owner(mdev))
3260 MLX5_SET(tisc, tisc, strict_lag_tx_port_affinity, 1);
3262 return mlx5_core_create_tis(mdev, in, tisn);
3265 void mlx5e_destroy_tis(struct mlx5_core_dev *mdev, u32 tisn)
3267 mlx5_core_destroy_tis(mdev, tisn);
3270 void mlx5e_destroy_tises(struct mlx5e_priv *priv)
3274 for (i = 0; i < mlx5e_get_num_lag_ports(priv->mdev); i++)
3275 for (tc = 0; tc < priv->profile->max_tc; tc++)
3276 mlx5e_destroy_tis(priv->mdev, priv->tisn[i][tc]);
3279 static bool mlx5e_lag_should_assign_affinity(struct mlx5_core_dev *mdev)
3281 return MLX5_CAP_GEN(mdev, lag_tx_port_affinity) && mlx5e_get_num_lag_ports(mdev) > 1;
3284 int mlx5e_create_tises(struct mlx5e_priv *priv)
3289 for (i = 0; i < mlx5e_get_num_lag_ports(priv->mdev); i++) {
3290 for (tc = 0; tc < priv->profile->max_tc; tc++) {
3291 u32 in[MLX5_ST_SZ_DW(create_tis_in)] = {};
3294 tisc = MLX5_ADDR_OF(create_tis_in, in, ctx);
3296 MLX5_SET(tisc, tisc, prio, tc << 1);
3298 if (mlx5e_lag_should_assign_affinity(priv->mdev))
3299 MLX5_SET(tisc, tisc, lag_tx_port_affinity, i + 1);
3301 err = mlx5e_create_tis(priv->mdev, in, &priv->tisn[i][tc]);
3303 goto err_close_tises;
3310 for (; i >= 0; i--) {
3311 for (tc--; tc >= 0; tc--)
3312 mlx5e_destroy_tis(priv->mdev, priv->tisn[i][tc]);
3313 tc = priv->profile->max_tc;
3319 static void mlx5e_cleanup_nic_tx(struct mlx5e_priv *priv)
3321 mlx5e_destroy_tises(priv);
3324 static void mlx5e_build_indir_tir_ctx_common(struct mlx5e_priv *priv,
3325 u32 rqtn, u32 *tirc)
3327 MLX5_SET(tirc, tirc, transport_domain, priv->mdev->mlx5e_res.td.tdn);
3328 MLX5_SET(tirc, tirc, disp_type, MLX5_TIRC_DISP_TYPE_INDIRECT);
3329 MLX5_SET(tirc, tirc, indirect_table, rqtn);
3330 MLX5_SET(tirc, tirc, tunneled_offload_en,
3331 priv->channels.params.tunneled_offload_en);
3333 mlx5e_build_tir_ctx_lro(&priv->channels.params, tirc);
3336 static void mlx5e_build_indir_tir_ctx(struct mlx5e_priv *priv,
3337 enum mlx5e_traffic_types tt,
3340 mlx5e_build_indir_tir_ctx_common(priv, priv->indir_rqt.rqtn, tirc);
3341 mlx5e_build_indir_tir_ctx_hash(&priv->rss_params,
3342 &tirc_default_config[tt], tirc, false);
3345 static void mlx5e_build_direct_tir_ctx(struct mlx5e_priv *priv, u32 rqtn, u32 *tirc)
3347 mlx5e_build_indir_tir_ctx_common(priv, rqtn, tirc);
3348 MLX5_SET(tirc, tirc, rx_hash_fn, MLX5_RX_HASH_FN_INVERTED_XOR8);
3351 static void mlx5e_build_inner_indir_tir_ctx(struct mlx5e_priv *priv,
3352 enum mlx5e_traffic_types tt,
3355 mlx5e_build_indir_tir_ctx_common(priv, priv->indir_rqt.rqtn, tirc);
3356 mlx5e_build_indir_tir_ctx_hash(&priv->rss_params,
3357 &tirc_default_config[tt], tirc, true);
3360 int mlx5e_create_indirect_tirs(struct mlx5e_priv *priv, bool inner_ttc)
3362 struct mlx5e_tir *tir;
3370 inlen = MLX5_ST_SZ_BYTES(create_tir_in);
3371 in = kvzalloc(inlen, GFP_KERNEL);
3375 for (tt = 0; tt < MLX5E_NUM_INDIR_TIRS; tt++) {
3376 memset(in, 0, inlen);
3377 tir = &priv->indir_tir[tt];
3378 tirc = MLX5_ADDR_OF(create_tir_in, in, ctx);
3379 mlx5e_build_indir_tir_ctx(priv, tt, tirc);
3380 err = mlx5e_create_tir(priv->mdev, tir, in);
3382 mlx5_core_warn(priv->mdev, "create indirect tirs failed, %d\n", err);
3383 goto err_destroy_inner_tirs;
3387 if (!inner_ttc || !mlx5e_tunnel_inner_ft_supported(priv->mdev))
3390 for (i = 0; i < MLX5E_NUM_INDIR_TIRS; i++) {
3391 memset(in, 0, inlen);
3392 tir = &priv->inner_indir_tir[i];
3393 tirc = MLX5_ADDR_OF(create_tir_in, in, ctx);
3394 mlx5e_build_inner_indir_tir_ctx(priv, i, tirc);
3395 err = mlx5e_create_tir(priv->mdev, tir, in);
3397 mlx5_core_warn(priv->mdev, "create inner indirect tirs failed, %d\n", err);
3398 goto err_destroy_inner_tirs;
3407 err_destroy_inner_tirs:
3408 for (i--; i >= 0; i--)
3409 mlx5e_destroy_tir(priv->mdev, &priv->inner_indir_tir[i]);
3411 for (tt--; tt >= 0; tt--)
3412 mlx5e_destroy_tir(priv->mdev, &priv->indir_tir[tt]);
3419 int mlx5e_create_direct_tirs(struct mlx5e_priv *priv, struct mlx5e_tir *tirs)
3421 struct mlx5e_tir *tir;
3428 inlen = MLX5_ST_SZ_BYTES(create_tir_in);
3429 in = kvzalloc(inlen, GFP_KERNEL);
3433 for (ix = 0; ix < priv->max_nch; ix++) {
3434 memset(in, 0, inlen);
3436 tirc = MLX5_ADDR_OF(create_tir_in, in, ctx);
3437 mlx5e_build_direct_tir_ctx(priv, tir->rqt.rqtn, tirc);
3438 err = mlx5e_create_tir(priv->mdev, tir, in);
3440 goto err_destroy_ch_tirs;
3445 err_destroy_ch_tirs:
3446 mlx5_core_warn(priv->mdev, "create tirs failed, %d\n", err);
3447 for (ix--; ix >= 0; ix--)
3448 mlx5e_destroy_tir(priv->mdev, &tirs[ix]);
3456 void mlx5e_destroy_indirect_tirs(struct mlx5e_priv *priv)
3460 for (i = 0; i < MLX5E_NUM_INDIR_TIRS; i++)
3461 mlx5e_destroy_tir(priv->mdev, &priv->indir_tir[i]);
3463 /* Verify inner tirs resources allocated */
3464 if (!priv->inner_indir_tir[0].tirn)
3467 for (i = 0; i < MLX5E_NUM_INDIR_TIRS; i++)
3468 mlx5e_destroy_tir(priv->mdev, &priv->inner_indir_tir[i]);
3471 void mlx5e_destroy_direct_tirs(struct mlx5e_priv *priv, struct mlx5e_tir *tirs)
3475 for (i = 0; i < priv->max_nch; i++)
3476 mlx5e_destroy_tir(priv->mdev, &tirs[i]);
3479 static int mlx5e_modify_channels_scatter_fcs(struct mlx5e_channels *chs, bool enable)
3484 for (i = 0; i < chs->num; i++) {
3485 err = mlx5e_modify_rq_scatter_fcs(&chs->c[i]->rq, enable);
3493 static int mlx5e_modify_channels_vsd(struct mlx5e_channels *chs, bool vsd)
3498 for (i = 0; i < chs->num; i++) {
3499 err = mlx5e_modify_rq_vsd(&chs->c[i]->rq, vsd);
3507 static int mlx5e_setup_tc_mqprio(struct mlx5e_priv *priv,
3508 struct tc_mqprio_qopt *mqprio)
3510 struct mlx5e_channels new_channels = {};
3511 u8 tc = mqprio->num_tc;
3514 mqprio->hw = TC_MQPRIO_HW_OFFLOAD_TCS;
3516 if (tc && tc != MLX5E_MAX_NUM_TC)
3519 mutex_lock(&priv->state_lock);
3521 new_channels.params = priv->channels.params;
3522 new_channels.params.num_tc = tc ? tc : 1;
3524 if (!test_bit(MLX5E_STATE_OPENED, &priv->state)) {
3525 priv->channels.params = new_channels.params;
3529 err = mlx5e_safe_switch_channels(priv, &new_channels,
3530 mlx5e_num_channels_changed_ctx, NULL);
3534 priv->max_opened_tc = max_t(u8, priv->max_opened_tc,
3535 new_channels.params.num_tc);
3537 mutex_unlock(&priv->state_lock);
3541 static LIST_HEAD(mlx5e_block_cb_list);
3543 static int mlx5e_setup_tc(struct net_device *dev, enum tc_setup_type type,
3546 struct mlx5e_priv *priv = netdev_priv(dev);
3549 case TC_SETUP_BLOCK: {
3550 struct flow_block_offload *f = type_data;
3552 f->unlocked_driver_cb = true;
3553 return flow_block_cb_setup_simple(type_data,
3554 &mlx5e_block_cb_list,
3555 mlx5e_setup_tc_block_cb,
3558 case TC_SETUP_QDISC_MQPRIO:
3559 return mlx5e_setup_tc_mqprio(priv, type_data);
3565 void mlx5e_fold_sw_stats64(struct mlx5e_priv *priv, struct rtnl_link_stats64 *s)
3569 for (i = 0; i < priv->max_nch; i++) {
3570 struct mlx5e_channel_stats *channel_stats = &priv->channel_stats[i];
3571 struct mlx5e_rq_stats *xskrq_stats = &channel_stats->xskrq;
3572 struct mlx5e_rq_stats *rq_stats = &channel_stats->rq;
3575 s->rx_packets += rq_stats->packets + xskrq_stats->packets;
3576 s->rx_bytes += rq_stats->bytes + xskrq_stats->bytes;
3578 for (j = 0; j < priv->max_opened_tc; j++) {
3579 struct mlx5e_sq_stats *sq_stats = &channel_stats->sq[j];
3581 s->tx_packets += sq_stats->packets;
3582 s->tx_bytes += sq_stats->bytes;
3583 s->tx_dropped += sq_stats->dropped;
3589 mlx5e_get_stats(struct net_device *dev, struct rtnl_link_stats64 *stats)
3591 struct mlx5e_priv *priv = netdev_priv(dev);
3592 struct mlx5e_vport_stats *vstats = &priv->stats.vport;
3593 struct mlx5e_pport_stats *pstats = &priv->stats.pport;
3595 /* In switchdev mode, monitor counters doesn't monitor
3596 * rx/tx stats of 802_3. The update stats mechanism
3597 * should keep the 802_3 layout counters updated
3599 if (!mlx5e_monitor_counter_supported(priv) ||
3600 mlx5e_is_uplink_rep(priv)) {
3601 /* update HW stats in background for next time */
3602 mlx5e_queue_update_stats(priv);
3605 if (mlx5e_is_uplink_rep(priv)) {
3606 stats->rx_packets = PPORT_802_3_GET(pstats, a_frames_received_ok);
3607 stats->rx_bytes = PPORT_802_3_GET(pstats, a_octets_received_ok);
3608 stats->tx_packets = PPORT_802_3_GET(pstats, a_frames_transmitted_ok);
3609 stats->tx_bytes = PPORT_802_3_GET(pstats, a_octets_transmitted_ok);
3611 mlx5e_fold_sw_stats64(priv, stats);
3614 stats->rx_dropped = priv->stats.qcnt.rx_out_of_buffer;
3616 stats->rx_length_errors =
3617 PPORT_802_3_GET(pstats, a_in_range_length_errors) +
3618 PPORT_802_3_GET(pstats, a_out_of_range_length_field) +
3619 PPORT_802_3_GET(pstats, a_frame_too_long_errors);
3620 stats->rx_crc_errors =
3621 PPORT_802_3_GET(pstats, a_frame_check_sequence_errors);
3622 stats->rx_frame_errors = PPORT_802_3_GET(pstats, a_alignment_errors);
3623 stats->tx_aborted_errors = PPORT_2863_GET(pstats, if_out_discards);
3624 stats->rx_errors = stats->rx_length_errors + stats->rx_crc_errors +
3625 stats->rx_frame_errors;
3626 stats->tx_errors = stats->tx_aborted_errors + stats->tx_carrier_errors;
3628 /* vport multicast also counts packets that are dropped due to steering
3629 * or rx out of buffer
3632 VPORT_COUNTER_GET(vstats, received_eth_multicast.packets);
3635 static void mlx5e_set_rx_mode(struct net_device *dev)
3637 struct mlx5e_priv *priv = netdev_priv(dev);
3639 queue_work(priv->wq, &priv->set_rx_mode_work);
3642 static int mlx5e_set_mac(struct net_device *netdev, void *addr)
3644 struct mlx5e_priv *priv = netdev_priv(netdev);
3645 struct sockaddr *saddr = addr;
3647 if (!is_valid_ether_addr(saddr->sa_data))
3648 return -EADDRNOTAVAIL;
3650 netif_addr_lock_bh(netdev);
3651 ether_addr_copy(netdev->dev_addr, saddr->sa_data);
3652 netif_addr_unlock_bh(netdev);
3654 queue_work(priv->wq, &priv->set_rx_mode_work);
3659 #define MLX5E_SET_FEATURE(features, feature, enable) \
3662 *features |= feature; \
3664 *features &= ~feature; \
3667 typedef int (*mlx5e_feature_handler)(struct net_device *netdev, bool enable);
3669 static int set_feature_lro(struct net_device *netdev, bool enable)
3671 struct mlx5e_priv *priv = netdev_priv(netdev);
3672 struct mlx5_core_dev *mdev = priv->mdev;
3673 struct mlx5e_channels new_channels = {};
3674 struct mlx5e_params *old_params;
3678 mutex_lock(&priv->state_lock);
3680 if (enable && priv->xsk.refcnt) {
3681 netdev_warn(netdev, "LRO is incompatible with AF_XDP (%hu XSKs are active)\n",
3687 old_params = &priv->channels.params;
3688 if (enable && !MLX5E_GET_PFLAG(old_params, MLX5E_PFLAG_RX_STRIDING_RQ)) {
3689 netdev_warn(netdev, "can't set LRO with legacy RQ\n");
3694 reset = test_bit(MLX5E_STATE_OPENED, &priv->state);
3696 new_channels.params = *old_params;
3697 new_channels.params.lro_en = enable;
3699 if (old_params->rq_wq_type != MLX5_WQ_TYPE_CYCLIC) {
3700 if (mlx5e_rx_mpwqe_is_linear_skb(mdev, old_params, NULL) ==
3701 mlx5e_rx_mpwqe_is_linear_skb(mdev, &new_channels.params, NULL))
3706 *old_params = new_channels.params;
3707 err = mlx5e_modify_tirs_lro(priv);
3711 err = mlx5e_safe_switch_channels(priv, &new_channels,
3712 mlx5e_modify_tirs_lro_ctx, NULL);
3714 mutex_unlock(&priv->state_lock);
3718 static int set_feature_cvlan_filter(struct net_device *netdev, bool enable)
3720 struct mlx5e_priv *priv = netdev_priv(netdev);
3723 mlx5e_enable_cvlan_filter(priv);
3725 mlx5e_disable_cvlan_filter(priv);
3730 #if IS_ENABLED(CONFIG_MLX5_CLS_ACT)
3731 static int set_feature_tc_num_filters(struct net_device *netdev, bool enable)
3733 struct mlx5e_priv *priv = netdev_priv(netdev);
3735 if (!enable && mlx5e_tc_num_filters(priv, MLX5_TC_FLAG(NIC_OFFLOAD))) {
3737 "Active offloaded tc filters, can't turn hw_tc_offload off\n");
3745 static int set_feature_rx_all(struct net_device *netdev, bool enable)
3747 struct mlx5e_priv *priv = netdev_priv(netdev);
3748 struct mlx5_core_dev *mdev = priv->mdev;
3750 return mlx5_set_port_fcs(mdev, !enable);
3753 static int set_feature_rx_fcs(struct net_device *netdev, bool enable)
3755 struct mlx5e_priv *priv = netdev_priv(netdev);
3758 mutex_lock(&priv->state_lock);
3760 priv->channels.params.scatter_fcs_en = enable;
3761 err = mlx5e_modify_channels_scatter_fcs(&priv->channels, enable);
3763 priv->channels.params.scatter_fcs_en = !enable;
3765 mutex_unlock(&priv->state_lock);
3770 static int set_feature_rx_vlan(struct net_device *netdev, bool enable)
3772 struct mlx5e_priv *priv = netdev_priv(netdev);
3775 mutex_lock(&priv->state_lock);
3777 priv->channels.params.vlan_strip_disable = !enable;
3778 if (!test_bit(MLX5E_STATE_OPENED, &priv->state))
3781 err = mlx5e_modify_channels_vsd(&priv->channels, !enable);
3783 priv->channels.params.vlan_strip_disable = enable;
3786 mutex_unlock(&priv->state_lock);
3791 #ifdef CONFIG_MLX5_EN_ARFS
3792 static int set_feature_arfs(struct net_device *netdev, bool enable)
3794 struct mlx5e_priv *priv = netdev_priv(netdev);
3798 err = mlx5e_arfs_enable(priv);
3800 err = mlx5e_arfs_disable(priv);
3806 static int mlx5e_handle_feature(struct net_device *netdev,
3807 netdev_features_t *features,
3808 netdev_features_t wanted_features,
3809 netdev_features_t feature,
3810 mlx5e_feature_handler feature_handler)
3812 netdev_features_t changes = wanted_features ^ netdev->features;
3813 bool enable = !!(wanted_features & feature);
3816 if (!(changes & feature))
3819 err = feature_handler(netdev, enable);
3821 netdev_err(netdev, "%s feature %pNF failed, err %d\n",
3822 enable ? "Enable" : "Disable", &feature, err);
3826 MLX5E_SET_FEATURE(features, feature, enable);
3830 int mlx5e_set_features(struct net_device *netdev, netdev_features_t features)
3832 netdev_features_t oper_features = netdev->features;
3835 #define MLX5E_HANDLE_FEATURE(feature, handler) \
3836 mlx5e_handle_feature(netdev, &oper_features, features, feature, handler)
3838 err |= MLX5E_HANDLE_FEATURE(NETIF_F_LRO, set_feature_lro);
3839 err |= MLX5E_HANDLE_FEATURE(NETIF_F_HW_VLAN_CTAG_FILTER,
3840 set_feature_cvlan_filter);
3841 #if IS_ENABLED(CONFIG_MLX5_CLS_ACT)
3842 err |= MLX5E_HANDLE_FEATURE(NETIF_F_HW_TC, set_feature_tc_num_filters);
3844 err |= MLX5E_HANDLE_FEATURE(NETIF_F_RXALL, set_feature_rx_all);
3845 err |= MLX5E_HANDLE_FEATURE(NETIF_F_RXFCS, set_feature_rx_fcs);
3846 err |= MLX5E_HANDLE_FEATURE(NETIF_F_HW_VLAN_CTAG_RX, set_feature_rx_vlan);
3847 #ifdef CONFIG_MLX5_EN_ARFS
3848 err |= MLX5E_HANDLE_FEATURE(NETIF_F_NTUPLE, set_feature_arfs);
3852 netdev->features = oper_features;
3859 static netdev_features_t mlx5e_fix_features(struct net_device *netdev,
3860 netdev_features_t features)
3862 struct mlx5e_priv *priv = netdev_priv(netdev);
3863 struct mlx5e_params *params;
3865 mutex_lock(&priv->state_lock);
3866 params = &priv->channels.params;
3867 if (!bitmap_empty(priv->fs.vlan.active_svlans, VLAN_N_VID)) {
3868 /* HW strips the outer C-tag header, this is a problem
3869 * for S-tag traffic.
3871 features &= ~NETIF_F_HW_VLAN_CTAG_RX;
3872 if (!params->vlan_strip_disable)
3873 netdev_warn(netdev, "Dropping C-tag vlan stripping offload due to S-tag vlan\n");
3875 if (!MLX5E_GET_PFLAG(params, MLX5E_PFLAG_RX_STRIDING_RQ)) {
3876 if (features & NETIF_F_LRO) {
3877 netdev_warn(netdev, "Disabling LRO, not supported in legacy RQ\n");
3878 features &= ~NETIF_F_LRO;
3882 if (MLX5E_GET_PFLAG(params, MLX5E_PFLAG_RX_CQE_COMPRESS)) {
3883 features &= ~NETIF_F_RXHASH;
3884 if (netdev->features & NETIF_F_RXHASH)
3885 netdev_warn(netdev, "Disabling rxhash, not supported when CQE compress is active\n");
3888 mutex_unlock(&priv->state_lock);
3893 static bool mlx5e_xsk_validate_mtu(struct net_device *netdev,
3894 struct mlx5e_channels *chs,
3895 struct mlx5e_params *new_params,
3896 struct mlx5_core_dev *mdev)
3900 for (ix = 0; ix < chs->params.num_channels; ix++) {
3901 struct xdp_umem *umem = mlx5e_xsk_get_umem(&chs->params, chs->params.xsk, ix);
3902 struct mlx5e_xsk_param xsk;
3907 mlx5e_build_xsk_param(umem, &xsk);
3909 if (!mlx5e_validate_xsk_param(new_params, &xsk, mdev)) {
3910 u32 hr = mlx5e_get_linear_rq_headroom(new_params, &xsk);
3911 int max_mtu_frame, max_mtu_page, max_mtu;
3913 /* Two criteria must be met:
3914 * 1. HW MTU + all headrooms <= XSK frame size.
3915 * 2. Size of SKBs allocated on XDP_PASS <= PAGE_SIZE.
3917 max_mtu_frame = MLX5E_HW2SW_MTU(new_params, xsk.chunk_size - hr);
3918 max_mtu_page = mlx5e_xdp_max_mtu(new_params, &xsk);
3919 max_mtu = min(max_mtu_frame, max_mtu_page);
3921 netdev_err(netdev, "MTU %d is too big for an XSK running on channel %hu. Try MTU <= %d\n",
3922 new_params->sw_mtu, ix, max_mtu);
3930 int mlx5e_change_mtu(struct net_device *netdev, int new_mtu,
3931 mlx5e_fp_preactivate preactivate)
3933 struct mlx5e_priv *priv = netdev_priv(netdev);
3934 struct mlx5e_channels new_channels = {};
3935 struct mlx5e_params *params;
3939 mutex_lock(&priv->state_lock);
3941 params = &priv->channels.params;
3943 reset = !params->lro_en;
3944 reset = reset && test_bit(MLX5E_STATE_OPENED, &priv->state);
3946 new_channels.params = *params;
3947 new_channels.params.sw_mtu = new_mtu;
3949 if (params->xdp_prog &&
3950 !mlx5e_rx_is_linear_skb(&new_channels.params, NULL)) {
3951 netdev_err(netdev, "MTU(%d) > %d is not allowed while XDP enabled\n",
3952 new_mtu, mlx5e_xdp_max_mtu(params, NULL));
3957 if (priv->xsk.refcnt &&
3958 !mlx5e_xsk_validate_mtu(netdev, &priv->channels,
3959 &new_channels.params, priv->mdev)) {
3964 if (params->rq_wq_type == MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ) {
3965 bool is_linear = mlx5e_rx_mpwqe_is_linear_skb(priv->mdev,
3966 &new_channels.params,
3968 u8 ppw_old = mlx5e_mpwqe_log_pkts_per_wqe(params, NULL);
3969 u8 ppw_new = mlx5e_mpwqe_log_pkts_per_wqe(&new_channels.params, NULL);
3971 /* If XSK is active, XSK RQs are linear. */
3972 is_linear |= priv->xsk.refcnt;
3974 /* Always reset in linear mode - hw_mtu is used in data path. */
3975 reset = reset && (is_linear || (ppw_old != ppw_new));
3979 params->sw_mtu = new_mtu;
3981 preactivate(priv, NULL);
3982 netdev->mtu = params->sw_mtu;
3986 err = mlx5e_safe_switch_channels(priv, &new_channels, preactivate, NULL);
3990 netdev->mtu = new_channels.params.sw_mtu;
3993 mutex_unlock(&priv->state_lock);
3997 static int mlx5e_change_nic_mtu(struct net_device *netdev, int new_mtu)
3999 return mlx5e_change_mtu(netdev, new_mtu, mlx5e_set_dev_port_mtu_ctx);
4002 int mlx5e_hwstamp_set(struct mlx5e_priv *priv, struct ifreq *ifr)
4004 struct hwtstamp_config config;
4007 if (!MLX5_CAP_GEN(priv->mdev, device_frequency_khz) ||
4008 (mlx5_clock_get_ptp_index(priv->mdev) == -1))
4011 if (copy_from_user(&config, ifr->ifr_data, sizeof(config)))
4014 /* TX HW timestamp */
4015 switch (config.tx_type) {
4016 case HWTSTAMP_TX_OFF:
4017 case HWTSTAMP_TX_ON:
4023 mutex_lock(&priv->state_lock);
4024 /* RX HW timestamp */
4025 switch (config.rx_filter) {
4026 case HWTSTAMP_FILTER_NONE:
4027 /* Reset CQE compression to Admin default */
4028 mlx5e_modify_rx_cqe_compression_locked(priv, priv->channels.params.rx_cqe_compress_def);
4030 case HWTSTAMP_FILTER_ALL:
4031 case HWTSTAMP_FILTER_SOME:
4032 case HWTSTAMP_FILTER_PTP_V1_L4_EVENT:
4033 case HWTSTAMP_FILTER_PTP_V1_L4_SYNC:
4034 case HWTSTAMP_FILTER_PTP_V1_L4_DELAY_REQ:
4035 case HWTSTAMP_FILTER_PTP_V2_L4_EVENT:
4036 case HWTSTAMP_FILTER_PTP_V2_L4_SYNC:
4037 case HWTSTAMP_FILTER_PTP_V2_L4_DELAY_REQ:
4038 case HWTSTAMP_FILTER_PTP_V2_L2_EVENT:
4039 case HWTSTAMP_FILTER_PTP_V2_L2_SYNC:
4040 case HWTSTAMP_FILTER_PTP_V2_L2_DELAY_REQ:
4041 case HWTSTAMP_FILTER_PTP_V2_EVENT:
4042 case HWTSTAMP_FILTER_PTP_V2_SYNC:
4043 case HWTSTAMP_FILTER_PTP_V2_DELAY_REQ:
4044 case HWTSTAMP_FILTER_NTP_ALL:
4045 /* Disable CQE compression */
4046 if (MLX5E_GET_PFLAG(&priv->channels.params, MLX5E_PFLAG_RX_CQE_COMPRESS))
4047 netdev_warn(priv->netdev, "Disabling RX cqe compression\n");
4048 err = mlx5e_modify_rx_cqe_compression_locked(priv, false);
4050 netdev_err(priv->netdev, "Failed disabling cqe compression err=%d\n", err);
4051 mutex_unlock(&priv->state_lock);
4054 config.rx_filter = HWTSTAMP_FILTER_ALL;
4057 mutex_unlock(&priv->state_lock);
4061 memcpy(&priv->tstamp, &config, sizeof(config));
4062 mutex_unlock(&priv->state_lock);
4064 /* might need to fix some features */
4065 netdev_update_features(priv->netdev);
4067 return copy_to_user(ifr->ifr_data, &config,
4068 sizeof(config)) ? -EFAULT : 0;
4071 int mlx5e_hwstamp_get(struct mlx5e_priv *priv, struct ifreq *ifr)
4073 struct hwtstamp_config *cfg = &priv->tstamp;
4075 if (!MLX5_CAP_GEN(priv->mdev, device_frequency_khz))
4078 return copy_to_user(ifr->ifr_data, cfg, sizeof(*cfg)) ? -EFAULT : 0;
4081 static int mlx5e_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
4083 struct mlx5e_priv *priv = netdev_priv(dev);
4087 return mlx5e_hwstamp_set(priv, ifr);
4089 return mlx5e_hwstamp_get(priv, ifr);
4095 #ifdef CONFIG_MLX5_ESWITCH
4096 int mlx5e_set_vf_mac(struct net_device *dev, int vf, u8 *mac)
4098 struct mlx5e_priv *priv = netdev_priv(dev);
4099 struct mlx5_core_dev *mdev = priv->mdev;
4101 return mlx5_eswitch_set_vport_mac(mdev->priv.eswitch, vf + 1, mac);
4104 static int mlx5e_set_vf_vlan(struct net_device *dev, int vf, u16 vlan, u8 qos,
4107 struct mlx5e_priv *priv = netdev_priv(dev);
4108 struct mlx5_core_dev *mdev = priv->mdev;
4110 if (vlan_proto != htons(ETH_P_8021Q))
4111 return -EPROTONOSUPPORT;
4113 return mlx5_eswitch_set_vport_vlan(mdev->priv.eswitch, vf + 1,
4117 static int mlx5e_set_vf_spoofchk(struct net_device *dev, int vf, bool setting)
4119 struct mlx5e_priv *priv = netdev_priv(dev);
4120 struct mlx5_core_dev *mdev = priv->mdev;
4122 return mlx5_eswitch_set_vport_spoofchk(mdev->priv.eswitch, vf + 1, setting);
4125 static int mlx5e_set_vf_trust(struct net_device *dev, int vf, bool setting)
4127 struct mlx5e_priv *priv = netdev_priv(dev);
4128 struct mlx5_core_dev *mdev = priv->mdev;
4130 return mlx5_eswitch_set_vport_trust(mdev->priv.eswitch, vf + 1, setting);
4133 int mlx5e_set_vf_rate(struct net_device *dev, int vf, int min_tx_rate,
4136 struct mlx5e_priv *priv = netdev_priv(dev);
4137 struct mlx5_core_dev *mdev = priv->mdev;
4139 return mlx5_eswitch_set_vport_rate(mdev->priv.eswitch, vf + 1,
4140 max_tx_rate, min_tx_rate);
4143 static int mlx5_vport_link2ifla(u8 esw_link)
4146 case MLX5_VPORT_ADMIN_STATE_DOWN:
4147 return IFLA_VF_LINK_STATE_DISABLE;
4148 case MLX5_VPORT_ADMIN_STATE_UP:
4149 return IFLA_VF_LINK_STATE_ENABLE;
4151 return IFLA_VF_LINK_STATE_AUTO;
4154 static int mlx5_ifla_link2vport(u8 ifla_link)
4156 switch (ifla_link) {
4157 case IFLA_VF_LINK_STATE_DISABLE:
4158 return MLX5_VPORT_ADMIN_STATE_DOWN;
4159 case IFLA_VF_LINK_STATE_ENABLE:
4160 return MLX5_VPORT_ADMIN_STATE_UP;
4162 return MLX5_VPORT_ADMIN_STATE_AUTO;
4165 static int mlx5e_set_vf_link_state(struct net_device *dev, int vf,
4168 struct mlx5e_priv *priv = netdev_priv(dev);
4169 struct mlx5_core_dev *mdev = priv->mdev;
4171 return mlx5_eswitch_set_vport_state(mdev->priv.eswitch, vf + 1,
4172 mlx5_ifla_link2vport(link_state));
4175 int mlx5e_get_vf_config(struct net_device *dev,
4176 int vf, struct ifla_vf_info *ivi)
4178 struct mlx5e_priv *priv = netdev_priv(dev);
4179 struct mlx5_core_dev *mdev = priv->mdev;
4182 err = mlx5_eswitch_get_vport_config(mdev->priv.eswitch, vf + 1, ivi);
4185 ivi->linkstate = mlx5_vport_link2ifla(ivi->linkstate);
4189 int mlx5e_get_vf_stats(struct net_device *dev,
4190 int vf, struct ifla_vf_stats *vf_stats)
4192 struct mlx5e_priv *priv = netdev_priv(dev);
4193 struct mlx5_core_dev *mdev = priv->mdev;
4195 return mlx5_eswitch_get_vport_stats(mdev->priv.eswitch, vf + 1,
4200 struct mlx5e_vxlan_work {
4201 struct work_struct work;
4202 struct mlx5e_priv *priv;
4206 static void mlx5e_vxlan_add_work(struct work_struct *work)
4208 struct mlx5e_vxlan_work *vxlan_work =
4209 container_of(work, struct mlx5e_vxlan_work, work);
4210 struct mlx5e_priv *priv = vxlan_work->priv;
4211 u16 port = vxlan_work->port;
4213 mutex_lock(&priv->state_lock);
4214 mlx5_vxlan_add_port(priv->mdev->vxlan, port);
4215 mutex_unlock(&priv->state_lock);
4220 static void mlx5e_vxlan_del_work(struct work_struct *work)
4222 struct mlx5e_vxlan_work *vxlan_work =
4223 container_of(work, struct mlx5e_vxlan_work, work);
4224 struct mlx5e_priv *priv = vxlan_work->priv;
4225 u16 port = vxlan_work->port;
4227 mutex_lock(&priv->state_lock);
4228 mlx5_vxlan_del_port(priv->mdev->vxlan, port);
4229 mutex_unlock(&priv->state_lock);
4233 static void mlx5e_vxlan_queue_work(struct mlx5e_priv *priv, u16 port, int add)
4235 struct mlx5e_vxlan_work *vxlan_work;
4237 vxlan_work = kmalloc(sizeof(*vxlan_work), GFP_ATOMIC);
4242 INIT_WORK(&vxlan_work->work, mlx5e_vxlan_add_work);
4244 INIT_WORK(&vxlan_work->work, mlx5e_vxlan_del_work);
4246 vxlan_work->priv = priv;
4247 vxlan_work->port = port;
4248 queue_work(priv->wq, &vxlan_work->work);
4251 void mlx5e_add_vxlan_port(struct net_device *netdev, struct udp_tunnel_info *ti)
4253 struct mlx5e_priv *priv = netdev_priv(netdev);
4255 if (ti->type != UDP_TUNNEL_TYPE_VXLAN)
4258 if (!mlx5_vxlan_allowed(priv->mdev->vxlan))
4261 mlx5e_vxlan_queue_work(priv, be16_to_cpu(ti->port), 1);
4264 void mlx5e_del_vxlan_port(struct net_device *netdev, struct udp_tunnel_info *ti)
4266 struct mlx5e_priv *priv = netdev_priv(netdev);
4268 if (ti->type != UDP_TUNNEL_TYPE_VXLAN)
4271 if (!mlx5_vxlan_allowed(priv->mdev->vxlan))
4274 mlx5e_vxlan_queue_work(priv, be16_to_cpu(ti->port), 0);
4277 static netdev_features_t mlx5e_tunnel_features_check(struct mlx5e_priv *priv,
4278 struct sk_buff *skb,
4279 netdev_features_t features)
4281 unsigned int offset = 0;
4282 struct udphdr *udph;
4286 switch (vlan_get_protocol(skb)) {
4287 case htons(ETH_P_IP):
4288 proto = ip_hdr(skb)->protocol;
4290 case htons(ETH_P_IPV6):
4291 proto = ipv6_find_hdr(skb, &offset, -1, NULL, NULL);
4302 if (mlx5e_tunnel_proto_supported(priv->mdev, IPPROTO_IPIP))
4306 udph = udp_hdr(skb);
4307 port = be16_to_cpu(udph->dest);
4309 /* Verify if UDP port is being offloaded by HW */
4310 if (mlx5_vxlan_lookup_port(priv->mdev->vxlan, port))
4313 #if IS_ENABLED(CONFIG_GENEVE)
4314 /* Support Geneve offload for default UDP port */
4315 if (port == GENEVE_UDP_PORT && mlx5_geneve_tx_allowed(priv->mdev))
4321 /* Disable CSUM and GSO if the udp dport is not offloaded by HW */
4322 return features & ~(NETIF_F_CSUM_MASK | NETIF_F_GSO_MASK);
4325 netdev_features_t mlx5e_features_check(struct sk_buff *skb,
4326 struct net_device *netdev,
4327 netdev_features_t features)
4329 struct mlx5e_priv *priv = netdev_priv(netdev);
4331 features = vlan_features_check(skb, features);
4332 features = vxlan_features_check(skb, features);
4334 #ifdef CONFIG_MLX5_EN_IPSEC
4335 if (mlx5e_ipsec_feature_check(skb, netdev, features))
4339 /* Validate if the tunneled packet is being offloaded by HW */
4340 if (skb->encapsulation &&
4341 (features & NETIF_F_CSUM_MASK || features & NETIF_F_GSO_MASK))
4342 return mlx5e_tunnel_features_check(priv, skb, features);
4347 static void mlx5e_tx_timeout_work(struct work_struct *work)
4349 struct mlx5e_priv *priv = container_of(work, struct mlx5e_priv,
4351 bool report_failed = false;
4356 mutex_lock(&priv->state_lock);
4358 if (!test_bit(MLX5E_STATE_OPENED, &priv->state))
4361 for (i = 0; i < priv->channels.num * priv->channels.params.num_tc; i++) {
4362 struct netdev_queue *dev_queue =
4363 netdev_get_tx_queue(priv->netdev, i);
4364 struct mlx5e_txqsq *sq = priv->txq2sq[i];
4366 if (!netif_xmit_stopped(dev_queue))
4369 if (mlx5e_reporter_tx_timeout(sq))
4370 report_failed = true;
4376 err = mlx5e_safe_reopen_channels(priv);
4378 netdev_err(priv->netdev,
4379 "mlx5e_safe_reopen_channels failed recovering from a tx_timeout, err(%d).\n",
4383 mutex_unlock(&priv->state_lock);
4387 static void mlx5e_tx_timeout(struct net_device *dev, unsigned int txqueue)
4389 struct mlx5e_priv *priv = netdev_priv(dev);
4391 netdev_err(dev, "TX timeout detected\n");
4392 queue_work(priv->wq, &priv->tx_timeout_work);
4395 static int mlx5e_xdp_allowed(struct mlx5e_priv *priv, struct bpf_prog *prog)
4397 struct net_device *netdev = priv->netdev;
4398 struct mlx5e_channels new_channels = {};
4400 if (priv->channels.params.lro_en) {
4401 netdev_warn(netdev, "can't set XDP while LRO is on, disable LRO first\n");
4405 if (MLX5_IPSEC_DEV(priv->mdev)) {
4406 netdev_warn(netdev, "can't set XDP with IPSec offload\n");
4410 new_channels.params = priv->channels.params;
4411 new_channels.params.xdp_prog = prog;
4413 /* No XSK params: AF_XDP can't be enabled yet at the point of setting
4416 if (!mlx5e_rx_is_linear_skb(&new_channels.params, NULL)) {
4417 netdev_warn(netdev, "XDP is not allowed with MTU(%d) > %d\n",
4418 new_channels.params.sw_mtu,
4419 mlx5e_xdp_max_mtu(&new_channels.params, NULL));
4426 static int mlx5e_xdp_set(struct net_device *netdev, struct bpf_prog *prog)
4428 struct mlx5e_priv *priv = netdev_priv(netdev);
4429 struct bpf_prog *old_prog;
4430 bool reset, was_opened;
4434 mutex_lock(&priv->state_lock);
4437 err = mlx5e_xdp_allowed(priv, prog);
4442 was_opened = test_bit(MLX5E_STATE_OPENED, &priv->state);
4443 /* no need for full reset when exchanging programs */
4444 reset = (!priv->channels.params.xdp_prog || !prog);
4446 if (was_opened && !reset)
4447 /* num_channels is invariant here, so we can take the
4448 * batched reference right upfront.
4450 bpf_prog_add(prog, priv->channels.num);
4452 if (was_opened && reset) {
4453 struct mlx5e_channels new_channels = {};
4455 new_channels.params = priv->channels.params;
4456 new_channels.params.xdp_prog = prog;
4457 mlx5e_set_rq_type(priv->mdev, &new_channels.params);
4458 old_prog = priv->channels.params.xdp_prog;
4460 err = mlx5e_safe_switch_channels(priv, &new_channels, NULL, NULL);
4464 /* exchange programs, extra prog reference we got from caller
4465 * as long as we don't fail from this point onwards.
4467 old_prog = xchg(&priv->channels.params.xdp_prog, prog);
4471 bpf_prog_put(old_prog);
4473 if (!was_opened && reset) /* change RQ type according to priv->xdp_prog */
4474 mlx5e_set_rq_type(priv->mdev, &priv->channels.params);
4476 if (!was_opened || reset)
4479 /* exchanging programs w/o reset, we update ref counts on behalf
4480 * of the channels RQs here.
4482 for (i = 0; i < priv->channels.num; i++) {
4483 struct mlx5e_channel *c = priv->channels.c[i];
4484 bool xsk_open = test_bit(MLX5E_CHANNEL_STATE_XSK, c->state);
4486 clear_bit(MLX5E_RQ_STATE_ENABLED, &c->rq.state);
4488 clear_bit(MLX5E_RQ_STATE_ENABLED, &c->xskrq.state);
4489 napi_synchronize(&c->napi);
4490 /* prevent mlx5e_poll_rx_cq from accessing rq->xdp_prog */
4492 old_prog = xchg(&c->rq.xdp_prog, prog);
4494 bpf_prog_put(old_prog);
4497 old_prog = xchg(&c->xskrq.xdp_prog, prog);
4499 bpf_prog_put(old_prog);
4502 set_bit(MLX5E_RQ_STATE_ENABLED, &c->rq.state);
4504 set_bit(MLX5E_RQ_STATE_ENABLED, &c->xskrq.state);
4505 /* napi_schedule in case we have missed anything */
4506 napi_schedule(&c->napi);
4510 mutex_unlock(&priv->state_lock);
4514 static u32 mlx5e_xdp_query(struct net_device *dev)
4516 struct mlx5e_priv *priv = netdev_priv(dev);
4517 const struct bpf_prog *xdp_prog;
4520 mutex_lock(&priv->state_lock);
4521 xdp_prog = priv->channels.params.xdp_prog;
4523 prog_id = xdp_prog->aux->id;
4524 mutex_unlock(&priv->state_lock);
4529 static int mlx5e_xdp(struct net_device *dev, struct netdev_bpf *xdp)
4531 switch (xdp->command) {
4532 case XDP_SETUP_PROG:
4533 return mlx5e_xdp_set(dev, xdp->prog);
4534 case XDP_QUERY_PROG:
4535 xdp->prog_id = mlx5e_xdp_query(dev);
4537 case XDP_SETUP_XSK_UMEM:
4538 return mlx5e_xsk_setup_umem(dev, xdp->xsk.umem,
4545 #ifdef CONFIG_MLX5_ESWITCH
4546 static int mlx5e_bridge_getlink(struct sk_buff *skb, u32 pid, u32 seq,
4547 struct net_device *dev, u32 filter_mask,
4550 struct mlx5e_priv *priv = netdev_priv(dev);
4551 struct mlx5_core_dev *mdev = priv->mdev;
4555 err = mlx5_eswitch_get_vepa(mdev->priv.eswitch, &setting);
4558 mode = setting ? BRIDGE_MODE_VEPA : BRIDGE_MODE_VEB;
4559 return ndo_dflt_bridge_getlink(skb, pid, seq, dev,
4561 0, 0, nlflags, filter_mask, NULL);
4564 static int mlx5e_bridge_setlink(struct net_device *dev, struct nlmsghdr *nlh,
4565 u16 flags, struct netlink_ext_ack *extack)
4567 struct mlx5e_priv *priv = netdev_priv(dev);
4568 struct mlx5_core_dev *mdev = priv->mdev;
4569 struct nlattr *attr, *br_spec;
4570 u16 mode = BRIDGE_MODE_UNDEF;
4574 br_spec = nlmsg_find_attr(nlh, sizeof(struct ifinfomsg), IFLA_AF_SPEC);
4578 nla_for_each_nested(attr, br_spec, rem) {
4579 if (nla_type(attr) != IFLA_BRIDGE_MODE)
4582 if (nla_len(attr) < sizeof(mode))
4585 mode = nla_get_u16(attr);
4586 if (mode > BRIDGE_MODE_VEPA)
4592 if (mode == BRIDGE_MODE_UNDEF)
4595 setting = (mode == BRIDGE_MODE_VEPA) ? 1 : 0;
4596 return mlx5_eswitch_set_vepa(mdev->priv.eswitch, setting);
4600 const struct net_device_ops mlx5e_netdev_ops = {
4601 .ndo_open = mlx5e_open,
4602 .ndo_stop = mlx5e_close,
4603 .ndo_start_xmit = mlx5e_xmit,
4604 .ndo_setup_tc = mlx5e_setup_tc,
4605 .ndo_select_queue = mlx5e_select_queue,
4606 .ndo_get_stats64 = mlx5e_get_stats,
4607 .ndo_set_rx_mode = mlx5e_set_rx_mode,
4608 .ndo_set_mac_address = mlx5e_set_mac,
4609 .ndo_vlan_rx_add_vid = mlx5e_vlan_rx_add_vid,
4610 .ndo_vlan_rx_kill_vid = mlx5e_vlan_rx_kill_vid,
4611 .ndo_set_features = mlx5e_set_features,
4612 .ndo_fix_features = mlx5e_fix_features,
4613 .ndo_change_mtu = mlx5e_change_nic_mtu,
4614 .ndo_do_ioctl = mlx5e_ioctl,
4615 .ndo_set_tx_maxrate = mlx5e_set_tx_maxrate,
4616 .ndo_udp_tunnel_add = mlx5e_add_vxlan_port,
4617 .ndo_udp_tunnel_del = mlx5e_del_vxlan_port,
4618 .ndo_features_check = mlx5e_features_check,
4619 .ndo_tx_timeout = mlx5e_tx_timeout,
4620 .ndo_bpf = mlx5e_xdp,
4621 .ndo_xdp_xmit = mlx5e_xdp_xmit,
4622 .ndo_xsk_wakeup = mlx5e_xsk_wakeup,
4623 #ifdef CONFIG_MLX5_EN_ARFS
4624 .ndo_rx_flow_steer = mlx5e_rx_flow_steer,
4626 #ifdef CONFIG_MLX5_ESWITCH
4627 .ndo_bridge_setlink = mlx5e_bridge_setlink,
4628 .ndo_bridge_getlink = mlx5e_bridge_getlink,
4630 /* SRIOV E-Switch NDOs */
4631 .ndo_set_vf_mac = mlx5e_set_vf_mac,
4632 .ndo_set_vf_vlan = mlx5e_set_vf_vlan,
4633 .ndo_set_vf_spoofchk = mlx5e_set_vf_spoofchk,
4634 .ndo_set_vf_trust = mlx5e_set_vf_trust,
4635 .ndo_set_vf_rate = mlx5e_set_vf_rate,
4636 .ndo_get_vf_config = mlx5e_get_vf_config,
4637 .ndo_set_vf_link_state = mlx5e_set_vf_link_state,
4638 .ndo_get_vf_stats = mlx5e_get_vf_stats,
4640 .ndo_get_devlink_port = mlx5e_get_devlink_port,
4643 static int mlx5e_check_required_hca_cap(struct mlx5_core_dev *mdev)
4645 if (MLX5_CAP_GEN(mdev, port_type) != MLX5_CAP_PORT_TYPE_ETH)
4647 if (!MLX5_CAP_GEN(mdev, eth_net_offloads) ||
4648 !MLX5_CAP_GEN(mdev, nic_flow_table) ||
4649 !MLX5_CAP_ETH(mdev, csum_cap) ||
4650 !MLX5_CAP_ETH(mdev, max_lso_cap) ||
4651 !MLX5_CAP_ETH(mdev, vlan_cap) ||
4652 !MLX5_CAP_ETH(mdev, rss_ind_tbl_cap) ||
4653 MLX5_CAP_FLOWTABLE(mdev,
4654 flow_table_properties_nic_receive.max_ft_level)
4656 mlx5_core_warn(mdev,
4657 "Not creating net device, some required device capabilities are missing\n");
4660 if (!MLX5_CAP_ETH(mdev, self_lb_en_modifiable))
4661 mlx5_core_warn(mdev, "Self loop back prevention is not supported\n");
4662 if (!MLX5_CAP_GEN(mdev, cq_moderation))
4663 mlx5_core_warn(mdev, "CQ moderation is not supported\n");
4668 void mlx5e_build_default_indir_rqt(u32 *indirection_rqt, int len,
4673 for (i = 0; i < len; i++)
4674 indirection_rqt[i] = i % num_channels;
4677 static bool slow_pci_heuristic(struct mlx5_core_dev *mdev)
4682 mlx5e_port_max_linkspeed(mdev, &link_speed);
4683 pci_bw = pcie_bandwidth_available(mdev->pdev, NULL, NULL, NULL);
4684 mlx5_core_dbg_once(mdev, "Max link speed = %d, PCI BW = %d\n",
4685 link_speed, pci_bw);
4687 #define MLX5E_SLOW_PCI_RATIO (2)
4689 return link_speed && pci_bw &&
4690 link_speed > MLX5E_SLOW_PCI_RATIO * pci_bw;
4693 static struct dim_cq_moder mlx5e_get_def_tx_moderation(u8 cq_period_mode)
4695 struct dim_cq_moder moder;
4697 moder.cq_period_mode = cq_period_mode;
4698 moder.pkts = MLX5E_PARAMS_DEFAULT_TX_CQ_MODERATION_PKTS;
4699 moder.usec = MLX5E_PARAMS_DEFAULT_TX_CQ_MODERATION_USEC;
4700 if (cq_period_mode == MLX5_CQ_PERIOD_MODE_START_FROM_CQE)
4701 moder.usec = MLX5E_PARAMS_DEFAULT_TX_CQ_MODERATION_USEC_FROM_CQE;
4706 static struct dim_cq_moder mlx5e_get_def_rx_moderation(u8 cq_period_mode)
4708 struct dim_cq_moder moder;
4710 moder.cq_period_mode = cq_period_mode;
4711 moder.pkts = MLX5E_PARAMS_DEFAULT_RX_CQ_MODERATION_PKTS;
4712 moder.usec = MLX5E_PARAMS_DEFAULT_RX_CQ_MODERATION_USEC;
4713 if (cq_period_mode == MLX5_CQ_PERIOD_MODE_START_FROM_CQE)
4714 moder.usec = MLX5E_PARAMS_DEFAULT_RX_CQ_MODERATION_USEC_FROM_CQE;
4719 static u8 mlx5_to_net_dim_cq_period_mode(u8 cq_period_mode)
4721 return cq_period_mode == MLX5_CQ_PERIOD_MODE_START_FROM_CQE ?
4722 DIM_CQ_PERIOD_MODE_START_FROM_CQE :
4723 DIM_CQ_PERIOD_MODE_START_FROM_EQE;
4726 void mlx5e_reset_tx_moderation(struct mlx5e_params *params, u8 cq_period_mode)
4728 if (params->tx_dim_enabled) {
4729 u8 dim_period_mode = mlx5_to_net_dim_cq_period_mode(cq_period_mode);
4731 params->tx_cq_moderation = net_dim_get_def_tx_moderation(dim_period_mode);
4733 params->tx_cq_moderation = mlx5e_get_def_tx_moderation(cq_period_mode);
4737 void mlx5e_reset_rx_moderation(struct mlx5e_params *params, u8 cq_period_mode)
4739 if (params->rx_dim_enabled) {
4740 u8 dim_period_mode = mlx5_to_net_dim_cq_period_mode(cq_period_mode);
4742 params->rx_cq_moderation = net_dim_get_def_rx_moderation(dim_period_mode);
4744 params->rx_cq_moderation = mlx5e_get_def_rx_moderation(cq_period_mode);
4748 void mlx5e_set_tx_cq_mode_params(struct mlx5e_params *params, u8 cq_period_mode)
4750 mlx5e_reset_tx_moderation(params, cq_period_mode);
4751 MLX5E_SET_PFLAG(params, MLX5E_PFLAG_TX_CQE_BASED_MODER,
4752 params->tx_cq_moderation.cq_period_mode ==
4753 MLX5_CQ_PERIOD_MODE_START_FROM_CQE);
4756 void mlx5e_set_rx_cq_mode_params(struct mlx5e_params *params, u8 cq_period_mode)
4758 mlx5e_reset_rx_moderation(params, cq_period_mode);
4759 MLX5E_SET_PFLAG(params, MLX5E_PFLAG_RX_CQE_BASED_MODER,
4760 params->rx_cq_moderation.cq_period_mode ==
4761 MLX5_CQ_PERIOD_MODE_START_FROM_CQE);
4764 static u32 mlx5e_choose_lro_timeout(struct mlx5_core_dev *mdev, u32 wanted_timeout)
4768 /* The supported periods are organized in ascending order */
4769 for (i = 0; i < MLX5E_LRO_TIMEOUT_ARR_SIZE - 1; i++)
4770 if (MLX5_CAP_ETH(mdev, lro_timer_supported_periods[i]) >= wanted_timeout)
4773 return MLX5_CAP_ETH(mdev, lro_timer_supported_periods[i]);
4776 void mlx5e_build_rq_params(struct mlx5_core_dev *mdev,
4777 struct mlx5e_params *params)
4779 /* Prefer Striding RQ, unless any of the following holds:
4780 * - Striding RQ configuration is not possible/supported.
4781 * - Slow PCI heuristic.
4782 * - Legacy RQ would use linear SKB while Striding RQ would use non-linear.
4784 * No XSK params: checking the availability of striding RQ in general.
4786 if (!slow_pci_heuristic(mdev) &&
4787 mlx5e_striding_rq_possible(mdev, params) &&
4788 (mlx5e_rx_mpwqe_is_linear_skb(mdev, params, NULL) ||
4789 !mlx5e_rx_is_linear_skb(params, NULL)))
4790 MLX5E_SET_PFLAG(params, MLX5E_PFLAG_RX_STRIDING_RQ, true);
4791 mlx5e_set_rq_type(mdev, params);
4792 mlx5e_init_rq_type_params(mdev, params);
4795 void mlx5e_build_rss_params(struct mlx5e_rss_params *rss_params,
4798 enum mlx5e_traffic_types tt;
4800 rss_params->hfunc = ETH_RSS_HASH_TOP;
4801 netdev_rss_key_fill(rss_params->toeplitz_hash_key,
4802 sizeof(rss_params->toeplitz_hash_key));
4803 mlx5e_build_default_indir_rqt(rss_params->indirection_rqt,
4804 MLX5E_INDIR_RQT_SIZE, num_channels);
4805 for (tt = 0; tt < MLX5E_NUM_INDIR_TIRS; tt++)
4806 rss_params->rx_hash_fields[tt] =
4807 tirc_default_config[tt].rx_hash_fields;
4810 void mlx5e_build_nic_params(struct mlx5e_priv *priv,
4811 struct mlx5e_xsk *xsk,
4812 struct mlx5e_rss_params *rss_params,
4813 struct mlx5e_params *params,
4816 struct mlx5_core_dev *mdev = priv->mdev;
4817 u8 rx_cq_period_mode;
4819 params->sw_mtu = mtu;
4820 params->hard_mtu = MLX5E_ETH_HARD_MTU;
4821 params->num_channels = min_t(unsigned int, MLX5E_MAX_NUM_CHANNELS / 2,
4826 params->log_sq_size = is_kdump_kernel() ?
4827 MLX5E_PARAMS_MINIMUM_LOG_SQ_SIZE :
4828 MLX5E_PARAMS_DEFAULT_LOG_SQ_SIZE;
4831 MLX5E_SET_PFLAG(params, MLX5E_PFLAG_XDP_TX_MPWQE,
4832 MLX5_CAP_ETH(mdev, enhanced_multi_pkt_send_wqe));
4834 /* set CQE compression */
4835 params->rx_cqe_compress_def = false;
4836 if (MLX5_CAP_GEN(mdev, cqe_compression) &&
4837 MLX5_CAP_GEN(mdev, vport_group_manager))
4838 params->rx_cqe_compress_def = slow_pci_heuristic(mdev);
4840 MLX5E_SET_PFLAG(params, MLX5E_PFLAG_RX_CQE_COMPRESS, params->rx_cqe_compress_def);
4841 MLX5E_SET_PFLAG(params, MLX5E_PFLAG_RX_NO_CSUM_COMPLETE, false);
4844 mlx5e_build_rq_params(mdev, params);
4847 if (MLX5_CAP_ETH(mdev, lro_cap) &&
4848 params->rq_wq_type == MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ) {
4849 /* No XSK params: checking the availability of striding RQ in general. */
4850 if (!mlx5e_rx_mpwqe_is_linear_skb(mdev, params, NULL))
4851 params->lro_en = !slow_pci_heuristic(mdev);
4853 params->lro_timeout = mlx5e_choose_lro_timeout(mdev, MLX5E_DEFAULT_LRO_TIMEOUT);
4855 /* CQ moderation params */
4856 rx_cq_period_mode = MLX5_CAP_GEN(mdev, cq_period_start_from_cqe) ?
4857 MLX5_CQ_PERIOD_MODE_START_FROM_CQE :
4858 MLX5_CQ_PERIOD_MODE_START_FROM_EQE;
4859 params->rx_dim_enabled = MLX5_CAP_GEN(mdev, cq_moderation);
4860 params->tx_dim_enabled = MLX5_CAP_GEN(mdev, cq_moderation);
4861 mlx5e_set_rx_cq_mode_params(params, rx_cq_period_mode);
4862 mlx5e_set_tx_cq_mode_params(params, MLX5_CQ_PERIOD_MODE_START_FROM_EQE);
4865 mlx5_query_min_inline(mdev, ¶ms->tx_min_inline_mode);
4868 mlx5e_build_rss_params(rss_params, params->num_channels);
4869 params->tunneled_offload_en =
4870 mlx5e_tunnel_inner_ft_supported(mdev);
4876 static void mlx5e_set_netdev_dev_addr(struct net_device *netdev)
4878 struct mlx5e_priv *priv = netdev_priv(netdev);
4880 mlx5_query_mac_address(priv->mdev, netdev->dev_addr);
4881 if (is_zero_ether_addr(netdev->dev_addr) &&
4882 !MLX5_CAP_GEN(priv->mdev, vport_group_manager)) {
4883 eth_hw_addr_random(netdev);
4884 mlx5_core_info(priv->mdev, "Assigned random MAC address %pM\n", netdev->dev_addr);
4888 static void mlx5e_build_nic_netdev(struct net_device *netdev)
4890 struct mlx5e_priv *priv = netdev_priv(netdev);
4891 struct mlx5_core_dev *mdev = priv->mdev;
4895 SET_NETDEV_DEV(netdev, mdev->device);
4897 netdev->netdev_ops = &mlx5e_netdev_ops;
4899 mlx5e_dcbnl_build_netdev(netdev);
4901 netdev->watchdog_timeo = 15 * HZ;
4903 netdev->ethtool_ops = &mlx5e_ethtool_ops;
4905 netdev->vlan_features |= NETIF_F_SG;
4906 netdev->vlan_features |= NETIF_F_HW_CSUM;
4907 netdev->vlan_features |= NETIF_F_GRO;
4908 netdev->vlan_features |= NETIF_F_TSO;
4909 netdev->vlan_features |= NETIF_F_TSO6;
4910 netdev->vlan_features |= NETIF_F_RXCSUM;
4911 netdev->vlan_features |= NETIF_F_RXHASH;
4913 netdev->mpls_features |= NETIF_F_SG;
4914 netdev->mpls_features |= NETIF_F_HW_CSUM;
4915 netdev->mpls_features |= NETIF_F_TSO;
4916 netdev->mpls_features |= NETIF_F_TSO6;
4918 netdev->hw_enc_features |= NETIF_F_HW_VLAN_CTAG_TX;
4919 netdev->hw_enc_features |= NETIF_F_HW_VLAN_CTAG_RX;
4921 if (!!MLX5_CAP_ETH(mdev, lro_cap) &&
4922 mlx5e_check_fragmented_striding_rq_cap(mdev))
4923 netdev->vlan_features |= NETIF_F_LRO;
4925 netdev->hw_features = netdev->vlan_features;
4926 netdev->hw_features |= NETIF_F_HW_VLAN_CTAG_TX;
4927 netdev->hw_features |= NETIF_F_HW_VLAN_CTAG_RX;
4928 netdev->hw_features |= NETIF_F_HW_VLAN_CTAG_FILTER;
4929 netdev->hw_features |= NETIF_F_HW_VLAN_STAG_TX;
4931 if (mlx5_vxlan_allowed(mdev->vxlan) || mlx5_geneve_tx_allowed(mdev) ||
4932 mlx5e_any_tunnel_proto_supported(mdev)) {
4933 netdev->hw_enc_features |= NETIF_F_HW_CSUM;
4934 netdev->hw_enc_features |= NETIF_F_TSO;
4935 netdev->hw_enc_features |= NETIF_F_TSO6;
4936 netdev->hw_enc_features |= NETIF_F_GSO_PARTIAL;
4939 if (mlx5_vxlan_allowed(mdev->vxlan) || mlx5_geneve_tx_allowed(mdev)) {
4940 netdev->hw_features |= NETIF_F_GSO_UDP_TUNNEL |
4941 NETIF_F_GSO_UDP_TUNNEL_CSUM;
4942 netdev->hw_enc_features |= NETIF_F_GSO_UDP_TUNNEL |
4943 NETIF_F_GSO_UDP_TUNNEL_CSUM;
4944 netdev->gso_partial_features = NETIF_F_GSO_UDP_TUNNEL_CSUM;
4945 netdev->vlan_features |= NETIF_F_GSO_UDP_TUNNEL |
4946 NETIF_F_GSO_UDP_TUNNEL_CSUM;
4949 if (mlx5e_tunnel_proto_supported(mdev, IPPROTO_GRE)) {
4950 netdev->hw_features |= NETIF_F_GSO_GRE |
4951 NETIF_F_GSO_GRE_CSUM;
4952 netdev->hw_enc_features |= NETIF_F_GSO_GRE |
4953 NETIF_F_GSO_GRE_CSUM;
4954 netdev->gso_partial_features |= NETIF_F_GSO_GRE |
4955 NETIF_F_GSO_GRE_CSUM;
4958 if (mlx5e_tunnel_proto_supported(mdev, IPPROTO_IPIP)) {
4959 netdev->hw_features |= NETIF_F_GSO_IPXIP4 |
4961 netdev->hw_enc_features |= NETIF_F_GSO_IPXIP4 |
4963 netdev->gso_partial_features |= NETIF_F_GSO_IPXIP4 |
4967 netdev->hw_features |= NETIF_F_GSO_PARTIAL;
4968 netdev->gso_partial_features |= NETIF_F_GSO_UDP_L4;
4969 netdev->hw_features |= NETIF_F_GSO_UDP_L4;
4970 netdev->features |= NETIF_F_GSO_UDP_L4;
4972 mlx5_query_port_fcs(mdev, &fcs_supported, &fcs_enabled);
4975 netdev->hw_features |= NETIF_F_RXALL;
4977 if (MLX5_CAP_ETH(mdev, scatter_fcs))
4978 netdev->hw_features |= NETIF_F_RXFCS;
4980 netdev->features = netdev->hw_features;
4981 if (!priv->channels.params.lro_en)
4982 netdev->features &= ~NETIF_F_LRO;
4985 netdev->features &= ~NETIF_F_RXALL;
4987 if (!priv->channels.params.scatter_fcs_en)
4988 netdev->features &= ~NETIF_F_RXFCS;
4990 /* prefere CQE compression over rxhash */
4991 if (MLX5E_GET_PFLAG(&priv->channels.params, MLX5E_PFLAG_RX_CQE_COMPRESS))
4992 netdev->features &= ~NETIF_F_RXHASH;
4994 #define FT_CAP(f) MLX5_CAP_FLOWTABLE(mdev, flow_table_properties_nic_receive.f)
4995 if (FT_CAP(flow_modify_en) &&
4996 FT_CAP(modify_root) &&
4997 FT_CAP(identified_miss_table_mode) &&
4998 FT_CAP(flow_table_modify)) {
4999 #ifdef CONFIG_MLX5_ESWITCH
5000 netdev->hw_features |= NETIF_F_HW_TC;
5002 #ifdef CONFIG_MLX5_EN_ARFS
5003 netdev->hw_features |= NETIF_F_NTUPLE;
5007 netdev->features |= NETIF_F_HIGHDMA;
5008 netdev->features |= NETIF_F_HW_VLAN_STAG_FILTER;
5010 netdev->priv_flags |= IFF_UNICAST_FLT;
5012 mlx5e_set_netdev_dev_addr(netdev);
5013 mlx5e_ipsec_build_netdev(priv);
5014 mlx5e_tls_build_netdev(priv);
5017 void mlx5e_create_q_counters(struct mlx5e_priv *priv)
5019 u32 out[MLX5_ST_SZ_DW(alloc_q_counter_out)] = {};
5020 u32 in[MLX5_ST_SZ_DW(alloc_q_counter_in)] = {};
5021 struct mlx5_core_dev *mdev = priv->mdev;
5024 MLX5_SET(alloc_q_counter_in, in, opcode, MLX5_CMD_OP_ALLOC_Q_COUNTER);
5025 err = mlx5_cmd_exec_inout(mdev, alloc_q_counter, in, out);
5028 MLX5_GET(alloc_q_counter_out, out, counter_set_id);
5030 err = mlx5_cmd_exec_inout(mdev, alloc_q_counter, in, out);
5032 priv->drop_rq_q_counter =
5033 MLX5_GET(alloc_q_counter_out, out, counter_set_id);
5036 void mlx5e_destroy_q_counters(struct mlx5e_priv *priv)
5038 u32 in[MLX5_ST_SZ_DW(dealloc_q_counter_in)] = {};
5040 MLX5_SET(dealloc_q_counter_in, in, opcode,
5041 MLX5_CMD_OP_DEALLOC_Q_COUNTER);
5042 if (priv->q_counter) {
5043 MLX5_SET(dealloc_q_counter_in, in, counter_set_id,
5045 mlx5_cmd_exec_in(priv->mdev, dealloc_q_counter, in);
5048 if (priv->drop_rq_q_counter) {
5049 MLX5_SET(dealloc_q_counter_in, in, counter_set_id,
5050 priv->drop_rq_q_counter);
5051 mlx5_cmd_exec_in(priv->mdev, dealloc_q_counter, in);
5055 static int mlx5e_nic_init(struct mlx5_core_dev *mdev,
5056 struct net_device *netdev,
5057 const struct mlx5e_profile *profile,
5060 struct mlx5e_priv *priv = netdev_priv(netdev);
5061 struct mlx5e_rss_params *rss = &priv->rss_params;
5064 err = mlx5e_netdev_init(netdev, priv, mdev, profile, ppriv);
5068 mlx5e_build_nic_params(priv, &priv->xsk, rss, &priv->channels.params,
5071 mlx5e_timestamp_init(priv);
5073 err = mlx5e_ipsec_init(priv);
5075 mlx5_core_err(mdev, "IPSec initialization failed, %d\n", err);
5076 err = mlx5e_tls_init(priv);
5078 mlx5_core_err(mdev, "TLS initialization failed, %d\n", err);
5079 mlx5e_build_nic_netdev(netdev);
5080 mlx5e_health_create_reporters(priv);
5085 static void mlx5e_nic_cleanup(struct mlx5e_priv *priv)
5087 mlx5e_health_destroy_reporters(priv);
5088 mlx5e_tls_cleanup(priv);
5089 mlx5e_ipsec_cleanup(priv);
5090 mlx5e_netdev_cleanup(priv->netdev, priv);
5093 static int mlx5e_init_nic_rx(struct mlx5e_priv *priv)
5095 struct mlx5_core_dev *mdev = priv->mdev;
5098 mlx5e_create_q_counters(priv);
5100 err = mlx5e_open_drop_rq(priv, &priv->drop_rq);
5102 mlx5_core_err(mdev, "open drop rq failed, %d\n", err);
5103 goto err_destroy_q_counters;
5106 err = mlx5e_create_indirect_rqt(priv);
5108 goto err_close_drop_rq;
5110 err = mlx5e_create_direct_rqts(priv, priv->direct_tir);
5112 goto err_destroy_indirect_rqts;
5114 err = mlx5e_create_indirect_tirs(priv, true);
5116 goto err_destroy_direct_rqts;
5118 err = mlx5e_create_direct_tirs(priv, priv->direct_tir);
5120 goto err_destroy_indirect_tirs;
5122 err = mlx5e_create_direct_rqts(priv, priv->xsk_tir);
5124 goto err_destroy_direct_tirs;
5126 err = mlx5e_create_direct_tirs(priv, priv->xsk_tir);
5128 goto err_destroy_xsk_rqts;
5130 err = mlx5e_create_flow_steering(priv);
5132 mlx5_core_warn(mdev, "create flow steering failed, %d\n", err);
5133 goto err_destroy_xsk_tirs;
5136 err = mlx5e_tc_nic_init(priv);
5138 goto err_destroy_flow_steering;
5140 #ifdef CONFIG_MLX5_EN_ARFS
5141 priv->netdev->rx_cpu_rmap = mlx5_eq_table_get_rmap(priv->mdev);
5146 err_destroy_flow_steering:
5147 mlx5e_destroy_flow_steering(priv);
5148 err_destroy_xsk_tirs:
5149 mlx5e_destroy_direct_tirs(priv, priv->xsk_tir);
5150 err_destroy_xsk_rqts:
5151 mlx5e_destroy_direct_rqts(priv, priv->xsk_tir);
5152 err_destroy_direct_tirs:
5153 mlx5e_destroy_direct_tirs(priv, priv->direct_tir);
5154 err_destroy_indirect_tirs:
5155 mlx5e_destroy_indirect_tirs(priv);
5156 err_destroy_direct_rqts:
5157 mlx5e_destroy_direct_rqts(priv, priv->direct_tir);
5158 err_destroy_indirect_rqts:
5159 mlx5e_destroy_rqt(priv, &priv->indir_rqt);
5161 mlx5e_close_drop_rq(&priv->drop_rq);
5162 err_destroy_q_counters:
5163 mlx5e_destroy_q_counters(priv);
5167 static void mlx5e_cleanup_nic_rx(struct mlx5e_priv *priv)
5169 mlx5e_tc_nic_cleanup(priv);
5170 mlx5e_destroy_flow_steering(priv);
5171 mlx5e_destroy_direct_tirs(priv, priv->xsk_tir);
5172 mlx5e_destroy_direct_rqts(priv, priv->xsk_tir);
5173 mlx5e_destroy_direct_tirs(priv, priv->direct_tir);
5174 mlx5e_destroy_indirect_tirs(priv);
5175 mlx5e_destroy_direct_rqts(priv, priv->direct_tir);
5176 mlx5e_destroy_rqt(priv, &priv->indir_rqt);
5177 mlx5e_close_drop_rq(&priv->drop_rq);
5178 mlx5e_destroy_q_counters(priv);
5181 static int mlx5e_init_nic_tx(struct mlx5e_priv *priv)
5185 err = mlx5e_create_tises(priv);
5187 mlx5_core_warn(priv->mdev, "create tises failed, %d\n", err);
5191 mlx5e_dcbnl_initialize(priv);
5195 static void mlx5e_nic_enable(struct mlx5e_priv *priv)
5197 struct net_device *netdev = priv->netdev;
5198 struct mlx5_core_dev *mdev = priv->mdev;
5200 mlx5e_init_l2_addr(priv);
5202 /* Marking the link as currently not needed by the Driver */
5203 if (!netif_running(netdev))
5204 mlx5e_modify_admin_state(mdev, MLX5_PORT_DOWN);
5206 mlx5e_set_netdev_mtu_boundaries(priv);
5207 mlx5e_set_dev_port_mtu(priv);
5209 mlx5_lag_add(mdev, netdev);
5211 mlx5e_enable_async_events(priv);
5212 if (mlx5e_monitor_counter_supported(priv))
5213 mlx5e_monitor_counter_init(priv);
5215 mlx5e_hv_vhca_stats_create(priv);
5216 if (netdev->reg_state != NETREG_REGISTERED)
5218 mlx5e_dcbnl_init_app(priv);
5220 queue_work(priv->wq, &priv->set_rx_mode_work);
5223 if (netif_running(netdev))
5225 if (mlx5_vxlan_allowed(priv->mdev->vxlan))
5226 udp_tunnel_get_rx_info(netdev);
5227 netif_device_attach(netdev);
5231 static void mlx5e_nic_disable(struct mlx5e_priv *priv)
5233 struct mlx5_core_dev *mdev = priv->mdev;
5235 if (priv->netdev->reg_state == NETREG_REGISTERED)
5236 mlx5e_dcbnl_delete_app(priv);
5239 if (netif_running(priv->netdev))
5240 mlx5e_close(priv->netdev);
5241 if (mlx5_vxlan_allowed(priv->mdev->vxlan))
5242 udp_tunnel_drop_rx_info(priv->netdev);
5243 netif_device_detach(priv->netdev);
5246 queue_work(priv->wq, &priv->set_rx_mode_work);
5248 mlx5e_hv_vhca_stats_destroy(priv);
5249 if (mlx5e_monitor_counter_supported(priv))
5250 mlx5e_monitor_counter_cleanup(priv);
5252 mlx5e_disable_async_events(priv);
5253 mlx5_lag_remove(mdev);
5256 int mlx5e_update_nic_rx(struct mlx5e_priv *priv)
5258 return mlx5e_refresh_tirs(priv, false, false);
5261 static const struct mlx5e_profile mlx5e_nic_profile = {
5262 .init = mlx5e_nic_init,
5263 .cleanup = mlx5e_nic_cleanup,
5264 .init_rx = mlx5e_init_nic_rx,
5265 .cleanup_rx = mlx5e_cleanup_nic_rx,
5266 .init_tx = mlx5e_init_nic_tx,
5267 .cleanup_tx = mlx5e_cleanup_nic_tx,
5268 .enable = mlx5e_nic_enable,
5269 .disable = mlx5e_nic_disable,
5270 .update_rx = mlx5e_update_nic_rx,
5271 .update_stats = mlx5e_update_ndo_stats,
5272 .update_carrier = mlx5e_update_carrier,
5273 .rx_handlers.handle_rx_cqe = mlx5e_handle_rx_cqe,
5274 .rx_handlers.handle_rx_cqe_mpwqe = mlx5e_handle_rx_cqe_mpwrq,
5275 .max_tc = MLX5E_MAX_NUM_TC,
5276 .rq_groups = MLX5E_NUM_RQ_GROUPS(XSK),
5277 .stats_grps = mlx5e_nic_stats_grps,
5278 .stats_grps_num = mlx5e_nic_stats_grps_num,
5281 /* mlx5e generic netdev management API (move to en_common.c) */
5283 /* mlx5e_netdev_init/cleanup must be called from profile->init/cleanup callbacks */
5284 int mlx5e_netdev_init(struct net_device *netdev,
5285 struct mlx5e_priv *priv,
5286 struct mlx5_core_dev *mdev,
5287 const struct mlx5e_profile *profile,
5292 priv->netdev = netdev;
5293 priv->profile = profile;
5294 priv->ppriv = ppriv;
5295 priv->msglevel = MLX5E_MSG_LEVEL;
5296 priv->max_nch = netdev->num_rx_queues / max_t(u8, profile->rq_groups, 1);
5297 priv->max_opened_tc = 1;
5299 if (!alloc_cpumask_var(&priv->scratchpad.cpumask, GFP_KERNEL))
5302 mutex_init(&priv->state_lock);
5303 INIT_WORK(&priv->update_carrier_work, mlx5e_update_carrier_work);
5304 INIT_WORK(&priv->set_rx_mode_work, mlx5e_set_rx_mode_work);
5305 INIT_WORK(&priv->tx_timeout_work, mlx5e_tx_timeout_work);
5306 INIT_WORK(&priv->update_stats_work, mlx5e_update_stats_work);
5308 priv->wq = create_singlethread_workqueue("mlx5e");
5310 goto err_free_cpumask;
5313 netif_carrier_off(netdev);
5318 free_cpumask_var(priv->scratchpad.cpumask);
5323 void mlx5e_netdev_cleanup(struct net_device *netdev, struct mlx5e_priv *priv)
5325 destroy_workqueue(priv->wq);
5326 free_cpumask_var(priv->scratchpad.cpumask);
5329 struct net_device *mlx5e_create_netdev(struct mlx5_core_dev *mdev,
5330 const struct mlx5e_profile *profile,
5334 struct net_device *netdev;
5337 netdev = alloc_etherdev_mqs(sizeof(struct mlx5e_priv),
5338 nch * profile->max_tc,
5339 nch * profile->rq_groups);
5341 mlx5_core_err(mdev, "alloc_etherdev_mqs() failed\n");
5345 err = profile->init(mdev, netdev, profile, ppriv);
5347 mlx5_core_err(mdev, "failed to init mlx5e profile %d\n", err);
5348 goto err_free_netdev;
5354 free_netdev(netdev);
5359 int mlx5e_attach_netdev(struct mlx5e_priv *priv)
5361 const bool take_rtnl = priv->netdev->reg_state == NETREG_REGISTERED;
5362 const struct mlx5e_profile *profile;
5366 profile = priv->profile;
5367 clear_bit(MLX5E_STATE_DESTROYING, &priv->state);
5369 /* max number of channels may have changed */
5370 max_nch = mlx5e_get_max_num_channels(priv->mdev);
5371 if (priv->channels.params.num_channels > max_nch) {
5372 mlx5_core_warn(priv->mdev, "MLX5E: Reducing number of channels to %d\n", max_nch);
5373 /* Reducing the number of channels - RXFH has to be reset, and
5374 * mlx5e_num_channels_changed below will build the RQT.
5376 priv->netdev->priv_flags &= ~IFF_RXFH_CONFIGURED;
5377 priv->channels.params.num_channels = max_nch;
5379 /* 1. Set the real number of queues in the kernel the first time.
5380 * 2. Set our default XPS cpumask.
5383 * rtnl_lock is required by netif_set_real_num_*_queues in case the
5384 * netdev has been registered by this point (if this function was called
5385 * in the reload or resume flow).
5389 err = mlx5e_num_channels_changed(priv);
5395 err = profile->init_tx(priv);
5399 err = profile->init_rx(priv);
5401 goto err_cleanup_tx;
5403 if (profile->enable)
5404 profile->enable(priv);
5409 profile->cleanup_tx(priv);
5412 set_bit(MLX5E_STATE_DESTROYING, &priv->state);
5413 cancel_work_sync(&priv->update_stats_work);
5417 void mlx5e_detach_netdev(struct mlx5e_priv *priv)
5419 const struct mlx5e_profile *profile = priv->profile;
5421 set_bit(MLX5E_STATE_DESTROYING, &priv->state);
5423 if (profile->disable)
5424 profile->disable(priv);
5425 flush_workqueue(priv->wq);
5427 profile->cleanup_rx(priv);
5428 profile->cleanup_tx(priv);
5429 cancel_work_sync(&priv->update_stats_work);
5432 void mlx5e_destroy_netdev(struct mlx5e_priv *priv)
5434 const struct mlx5e_profile *profile = priv->profile;
5435 struct net_device *netdev = priv->netdev;
5437 if (profile->cleanup)
5438 profile->cleanup(priv);
5439 free_netdev(netdev);
5442 /* mlx5e_attach and mlx5e_detach scope should be only creating/destroying
5443 * hardware contexts and to connect it to the current netdev.
5445 static int mlx5e_attach(struct mlx5_core_dev *mdev, void *vpriv)
5447 struct mlx5e_priv *priv = vpriv;
5448 struct net_device *netdev = priv->netdev;
5451 if (netif_device_present(netdev))
5454 err = mlx5e_create_mdev_resources(mdev);
5458 err = mlx5e_attach_netdev(priv);
5460 mlx5e_destroy_mdev_resources(mdev);
5467 static void mlx5e_detach(struct mlx5_core_dev *mdev, void *vpriv)
5469 struct mlx5e_priv *priv = vpriv;
5470 struct net_device *netdev = priv->netdev;
5472 #ifdef CONFIG_MLX5_ESWITCH
5473 if (MLX5_ESWITCH_MANAGER(mdev) && vpriv == mdev)
5477 if (!netif_device_present(netdev))
5480 mlx5e_detach_netdev(priv);
5481 mlx5e_destroy_mdev_resources(mdev);
5484 static void *mlx5e_add(struct mlx5_core_dev *mdev)
5486 struct net_device *netdev;
5491 err = mlx5e_check_required_hca_cap(mdev);
5495 #ifdef CONFIG_MLX5_ESWITCH
5496 if (MLX5_ESWITCH_MANAGER(mdev) &&
5497 mlx5_eswitch_mode(mdev->priv.eswitch) == MLX5_ESWITCH_OFFLOADS) {
5498 mlx5e_rep_register_vport_reps(mdev);
5503 nch = mlx5e_get_max_num_channels(mdev);
5504 netdev = mlx5e_create_netdev(mdev, &mlx5e_nic_profile, nch, NULL);
5506 mlx5_core_err(mdev, "mlx5e_create_netdev failed\n");
5510 dev_net_set(netdev, mlx5_core_net(mdev));
5511 priv = netdev_priv(netdev);
5513 err = mlx5e_attach(mdev, priv);
5515 mlx5_core_err(mdev, "mlx5e_attach failed, %d\n", err);
5516 goto err_destroy_netdev;
5519 err = mlx5e_devlink_port_register(priv);
5521 mlx5_core_err(mdev, "mlx5e_devlink_port_register failed, %d\n", err);
5525 err = register_netdev(netdev);
5527 mlx5_core_err(mdev, "register_netdev failed, %d\n", err);
5528 goto err_devlink_port_unregister;
5531 mlx5e_devlink_port_type_eth_set(priv);
5533 mlx5e_dcbnl_init_app(priv);
5536 err_devlink_port_unregister:
5537 mlx5e_devlink_port_unregister(priv);
5539 mlx5e_detach(mdev, priv);
5541 mlx5e_destroy_netdev(priv);
5545 static void mlx5e_remove(struct mlx5_core_dev *mdev, void *vpriv)
5547 struct mlx5e_priv *priv;
5549 #ifdef CONFIG_MLX5_ESWITCH
5550 if (MLX5_ESWITCH_MANAGER(mdev) && vpriv == mdev) {
5551 mlx5e_rep_unregister_vport_reps(mdev);
5556 mlx5e_dcbnl_delete_app(priv);
5557 unregister_netdev(priv->netdev);
5558 mlx5e_devlink_port_unregister(priv);
5559 mlx5e_detach(mdev, vpriv);
5560 mlx5e_destroy_netdev(priv);
5563 static struct mlx5_interface mlx5e_interface = {
5565 .remove = mlx5e_remove,
5566 .attach = mlx5e_attach,
5567 .detach = mlx5e_detach,
5568 .protocol = MLX5_INTERFACE_PROTOCOL_ETH,
5571 void mlx5e_init(void)
5573 mlx5e_ipsec_build_inverse_table();
5574 mlx5e_build_ptys2ethtool_map();
5575 mlx5_register_interface(&mlx5e_interface);
5578 void mlx5e_cleanup(void)
5580 mlx5_unregister_interface(&mlx5e_interface);