drivers/net/ethernet/mellanox/mlx5/core/en_main.c

   1 /*
   2  * Copyright (c) 2015-2016, Mellanox Technologies. All rights reserved.
   3  *
   4  * This software is available to you under a choice of one of two
   5  * licenses.  You may choose to be licensed under the terms of the GNU
   6  * General Public License (GPL) Version 2, available from the file
   7  * COPYING in the main directory of this source tree, or the
   8  * OpenIB.org BSD license below:
   9  *
  10  *     Redistribution and use in source and binary forms, with or
  11  *     without modification, are permitted provided that the following
  12  *     conditions are met:
  13  *
  14  *      - Redistributions of source code must retain the above
  15  *        copyright notice, this list of conditions and the following
  16  *        disclaimer.
  17  *
  18  *      - Redistributions in binary form must reproduce the above
  19  *        copyright notice, this list of conditions and the following
  20  *        disclaimer in the documentation and/or other materials
  21  *        provided with the distribution.
  22  *
  23  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  24  * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  25  * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
  26  * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
  27  * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
  28  * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
  29  * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
  30  * SOFTWARE.
  31  */
  32
  33 #include <net/tc_act/tc_gact.h>
  34 #include <net/pkt_cls.h>
  35 #include <linux/mlx5/fs.h>
  36 #include <net/vxlan.h>
  37 #include <net/geneve.h>
  38 #include <linux/bpf.h>
  39 #include <linux/if_bridge.h>
  40 #include <net/page_pool.h>
  41 #include <net/xdp_sock_drv.h>
  42 #include "eswitch.h"
  43 #include "en.h"
  44 #include "en/txrx.h"
  45 #include "en_tc.h"
  46 #include "en_rep.h"
  47 #include "en_accel/ipsec.h"
  48 #include "en_accel/en_accel.h"
  49 #include "en_accel/tls.h"
  50 #include "accel/ipsec.h"
  51 #include "accel/tls.h"
  52 #include "lib/vxlan.h"
  53 #include "lib/clock.h"
  54 #include "en/port.h"
  55 #include "en/xdp.h"
  56 #include "lib/eq.h"
  57 #include "en/monitor_stats.h"
  58 #include "en/health.h"
  59 #include "en/params.h"
  60 #include "en/xsk/pool.h"
  61 #include "en/xsk/setup.h"
  62 #include "en/xsk/rx.h"
  63 #include "en/xsk/tx.h"
  64 #include "en/hv_vhca_stats.h"
  65 #include "en/devlink.h"
  66 #include "lib/mlx5.h"
  67 #include "en/ptp.h"
  68 #include "qos.h"
  69 #include "en/trap.h"
  70 #include "fpga/ipsec.h"
  71
  72 bool mlx5e_check_fragmented_striding_rq_cap(struct mlx5_core_dev *mdev)
  73 {
  74         bool striding_rq_umr = MLX5_CAP_GEN(mdev, striding_rq) &&
  75                 MLX5_CAP_GEN(mdev, umr_ptr_rlky) &&
  76                 MLX5_CAP_ETH(mdev, reg_umr_sq);
  77         u16 max_wqe_sz_cap = MLX5_CAP_GEN(mdev, max_wqe_sz_sq);
  78         bool inline_umr = MLX5E_UMR_WQE_INLINE_SZ <= max_wqe_sz_cap;
  79
  80         if (!striding_rq_umr)
  81                 return false;
  82         if (!inline_umr) {
  83                 mlx5_core_warn(mdev, "Cannot support Striding RQ: UMR WQE size (%d) exceeds maximum supported (%d).\n",
  84                                (int)MLX5E_UMR_WQE_INLINE_SZ, max_wqe_sz_cap);
  85                 return false;
  86         }
  87         return true;
  88 }
  89
  90 void mlx5e_update_carrier(struct mlx5e_priv *priv)
  91 {
  92         struct mlx5_core_dev *mdev = priv->mdev;
  93         u8 port_state;
  94         bool up;
  95
  96         port_state = mlx5_query_vport_state(mdev,
  97                                             MLX5_VPORT_STATE_OP_MOD_VNIC_VPORT,
  98                                             0);
  99
 100         up = port_state == VPORT_STATE_UP;
 101         if (up == netif_carrier_ok(priv->netdev))
 102                 netif_carrier_event(priv->netdev);
 103         if (up) {
 104                 netdev_info(priv->netdev, "Link up\n");
 105                 netif_carrier_on(priv->netdev);
 106         } else {
 107                 netdev_info(priv->netdev, "Link down\n");
 108                 netif_carrier_off(priv->netdev);
 109         }
 110 }
 111
 112 static void mlx5e_update_carrier_work(struct work_struct *work)
 113 {
 114         struct mlx5e_priv *priv = container_of(work, struct mlx5e_priv,
 115                                                update_carrier_work);
 116
 117         mutex_lock(&priv->state_lock);
 118         if (test_bit(MLX5E_STATE_OPENED, &priv->state))
 119                 if (priv->profile->update_carrier)
 120                         priv->profile->update_carrier(priv);
 121         mutex_unlock(&priv->state_lock);
 122 }
 123
 124 static void mlx5e_update_stats_work(struct work_struct *work)
 125 {
 126         struct mlx5e_priv *priv = container_of(work, struct mlx5e_priv,
 127                                                update_stats_work);
 128
 129         mutex_lock(&priv->state_lock);
 130         priv->profile->update_stats(priv);
 131         mutex_unlock(&priv->state_lock);
 132 }
 133
 134 void mlx5e_queue_update_stats(struct mlx5e_priv *priv)
 135 {
 136         if (!priv->profile->update_stats)
 137                 return;
 138
 139         if (unlikely(test_bit(MLX5E_STATE_DESTROYING, &priv->state)))
 140                 return;
 141
 142         queue_work(priv->wq, &priv->update_stats_work);
 143 }
 144
 145 static int async_event(struct notifier_block *nb, unsigned long event, void *data)
 146 {
 147         struct mlx5e_priv *priv = container_of(nb, struct mlx5e_priv, events_nb);
 148         struct mlx5_eqe   *eqe = data;
 149
 150         if (event != MLX5_EVENT_TYPE_PORT_CHANGE)
 151                 return NOTIFY_DONE;
 152
 153         switch (eqe->sub_type) {
 154         case MLX5_PORT_CHANGE_SUBTYPE_DOWN:
 155         case MLX5_PORT_CHANGE_SUBTYPE_ACTIVE:
 156                 queue_work(priv->wq, &priv->update_carrier_work);
 157                 break;
 158         default:
 159                 return NOTIFY_DONE;
 160         }
 161
 162         return NOTIFY_OK;
 163 }
 164
 165 static void mlx5e_enable_async_events(struct mlx5e_priv *priv)
 166 {
 167         priv->events_nb.notifier_call = async_event;
 168         mlx5_notifier_register(priv->mdev, &priv->events_nb);
 169 }
 170
 171 static void mlx5e_disable_async_events(struct mlx5e_priv *priv)
 172 {
 173         mlx5_notifier_unregister(priv->mdev, &priv->events_nb);
 174 }
 175
 176 static int blocking_event(struct notifier_block *nb, unsigned long event, void *data)
 177 {
 178         struct mlx5e_priv *priv = container_of(nb, struct mlx5e_priv, blocking_events_nb);
 179         int err;
 180
 181         switch (event) {
 182         case MLX5_DRIVER_EVENT_TYPE_TRAP:
 183                 err = mlx5e_handle_trap_event(priv, data);
 184                 break;
 185         default:
 186                 netdev_warn(priv->netdev, "Sync event: Unknown event %ld\n", event);
 187                 err = -EINVAL;
 188         }
 189         return err;
 190 }
 191
 192 static void mlx5e_enable_blocking_events(struct mlx5e_priv *priv)
 193 {
 194         priv->blocking_events_nb.notifier_call = blocking_event;
 195         mlx5_blocking_notifier_register(priv->mdev, &priv->blocking_events_nb);
 196 }
 197
 198 static void mlx5e_disable_blocking_events(struct mlx5e_priv *priv)
 199 {
 200         mlx5_blocking_notifier_unregister(priv->mdev, &priv->blocking_events_nb);
 201 }
 202
 203 static inline void mlx5e_build_umr_wqe(struct mlx5e_rq *rq,
 204                                        struct mlx5e_icosq *sq,
 205                                        struct mlx5e_umr_wqe *wqe)
 206 {
 207         struct mlx5_wqe_ctrl_seg      *cseg = &wqe->ctrl;
 208         struct mlx5_wqe_umr_ctrl_seg *ucseg = &wqe->uctrl;
 209         u8 ds_cnt = DIV_ROUND_UP(MLX5E_UMR_WQE_INLINE_SZ, MLX5_SEND_WQE_DS);
 210
 211         cseg->qpn_ds    = cpu_to_be32((sq->sqn << MLX5_WQE_CTRL_QPN_SHIFT) |
 212                                       ds_cnt);
 213         cseg->umr_mkey  = rq->mkey_be;
 214
 215         ucseg->flags = MLX5_UMR_TRANSLATION_OFFSET_EN | MLX5_UMR_INLINE;
 216         ucseg->xlt_octowords =
 217                 cpu_to_be16(MLX5_MTT_OCTW(MLX5_MPWRQ_PAGES_PER_WQE));
 218         ucseg->mkey_mask     = cpu_to_be64(MLX5_MKEY_MASK_FREE);
 219 }
 220
 221 static int mlx5e_rq_alloc_mpwqe_info(struct mlx5e_rq *rq, int node)
 222 {
 223         int wq_sz = mlx5_wq_ll_get_size(&rq->mpwqe.wq);
 224
 225         rq->mpwqe.info = kvzalloc_node(array_size(wq_sz,
 226                                                   sizeof(*rq->mpwqe.info)),
 227                                        GFP_KERNEL, node);
 228         if (!rq->mpwqe.info)
 229                 return -ENOMEM;
 230
 231         mlx5e_build_umr_wqe(rq, rq->icosq, &rq->mpwqe.umr_wqe);
 232
 233         return 0;
 234 }
 235
 236 static int mlx5e_create_umr_mkey(struct mlx5_core_dev *mdev,
 237                                  u64 npages, u8 page_shift,
 238                                  struct mlx5_core_mkey *umr_mkey,
 239                                  dma_addr_t filler_addr)
 240 {
 241         struct mlx5_mtt *mtt;
 242         int inlen;
 243         void *mkc;
 244         u32 *in;
 245         int err;
 246         int i;
 247
 248         inlen = MLX5_ST_SZ_BYTES(create_mkey_in) + sizeof(*mtt) * npages;
 249
 250         in = kvzalloc(inlen, GFP_KERNEL);
 251         if (!in)
 252                 return -ENOMEM;
 253
 254         mkc = MLX5_ADDR_OF(create_mkey_in, in, memory_key_mkey_entry);
 255
 256         MLX5_SET(mkc, mkc, free, 1);
 257         MLX5_SET(mkc, mkc, umr_en, 1);
 258         MLX5_SET(mkc, mkc, lw, 1);
 259         MLX5_SET(mkc, mkc, lr, 1);
 260         MLX5_SET(mkc, mkc, access_mode_1_0, MLX5_MKC_ACCESS_MODE_MTT);
 261         mlx5e_mkey_set_relaxed_ordering(mdev, mkc);
 262         MLX5_SET(mkc, mkc, qpn, 0xffffff);
 263         MLX5_SET(mkc, mkc, pd, mdev->mlx5e_res.hw_objs.pdn);
 264         MLX5_SET64(mkc, mkc, len, npages << page_shift);
 265         MLX5_SET(mkc, mkc, translations_octword_size,
 266                  MLX5_MTT_OCTW(npages));
 267         MLX5_SET(mkc, mkc, log_page_size, page_shift);
 268         MLX5_SET(create_mkey_in, in, translations_octword_actual_size,
 269                  MLX5_MTT_OCTW(npages));
 270
 271         /* Initialize the mkey with all MTTs pointing to a default
 272          * page (filler_addr). When the channels are activated, UMR
 273          * WQEs will redirect the RX WQEs to the actual memory from
 274          * the RQ's pool, while the gaps (wqe_overflow) remain mapped
 275          * to the default page.
 276          */
 277         mtt = MLX5_ADDR_OF(create_mkey_in, in, klm_pas_mtt);
 278         for (i = 0 ; i < npages ; i++)
 279                 mtt[i].ptag = cpu_to_be64(filler_addr);
 280
 281         err = mlx5_core_create_mkey(mdev, umr_mkey, in, inlen);
 282
 283         kvfree(in);
 284         return err;
 285 }
 286
 287 static int mlx5e_create_rq_umr_mkey(struct mlx5_core_dev *mdev, struct mlx5e_rq *rq)
 288 {
 289         u64 num_mtts = MLX5E_REQUIRED_MTTS(mlx5_wq_ll_get_size(&rq->mpwqe.wq));
 290
 291         return mlx5e_create_umr_mkey(mdev, num_mtts, PAGE_SHIFT, &rq->umr_mkey,
 292                                      rq->wqe_overflow.addr);
 293 }
 294
 295 static u64 mlx5e_get_mpwqe_offset(u16 wqe_ix)
 296 {
 297         return MLX5E_REQUIRED_MTTS(wqe_ix) << PAGE_SHIFT;
 298 }
 299
 300 static void mlx5e_init_frags_partition(struct mlx5e_rq *rq)
 301 {
 302         struct mlx5e_wqe_frag_info next_frag = {};
 303         struct mlx5e_wqe_frag_info *prev = NULL;
 304         int i;
 305
 306         next_frag.di = &rq->wqe.di[0];
 307
 308         for (i = 0; i < mlx5_wq_cyc_get_size(&rq->wqe.wq); i++) {
 309                 struct mlx5e_rq_frag_info *frag_info = &rq->wqe.info.arr[0];
 310                 struct mlx5e_wqe_frag_info *frag =
 311                         &rq->wqe.frags[i << rq->wqe.info.log_num_frags];
 312                 int f;
 313
 314                 for (f = 0; f < rq->wqe.info.num_frags; f++, frag++) {
 315                         if (next_frag.offset + frag_info[f].frag_stride > PAGE_SIZE) {
 316                                 next_frag.di++;
 317                                 next_frag.offset = 0;
 318                                 if (prev)
 319                                         prev->last_in_page = true;
 320                         }
 321                         *frag = next_frag;
 322
 323                         /* prepare next */
 324                         next_frag.offset += frag_info[f].frag_stride;
 325                         prev = frag;
 326                 }
 327         }
 328
 329         if (prev)
 330                 prev->last_in_page = true;
 331 }
 332
 333 int mlx5e_init_di_list(struct mlx5e_rq *rq, int wq_sz, int node)
 334 {
 335         int len = wq_sz << rq->wqe.info.log_num_frags;
 336
 337         rq->wqe.di = kvzalloc_node(array_size(len, sizeof(*rq->wqe.di)), GFP_KERNEL, node);
 338         if (!rq->wqe.di)
 339                 return -ENOMEM;
 340
 341         mlx5e_init_frags_partition(rq);
 342
 343         return 0;
 344 }
 345
 346 void mlx5e_free_di_list(struct mlx5e_rq *rq)
 347 {
 348         kvfree(rq->wqe.di);
 349 }
 350
 351 static void mlx5e_rq_err_cqe_work(struct work_struct *recover_work)
 352 {
 353         struct mlx5e_rq *rq = container_of(recover_work, struct mlx5e_rq, recover_work);
 354
 355         mlx5e_reporter_rq_cqe_err(rq);
 356 }
 357
 358 static int mlx5e_alloc_mpwqe_rq_drop_page(struct mlx5e_rq *rq)
 359 {
 360         rq->wqe_overflow.page = alloc_page(GFP_KERNEL);
 361         if (!rq->wqe_overflow.page)
 362                 return -ENOMEM;
 363
 364         rq->wqe_overflow.addr = dma_map_page(rq->pdev, rq->wqe_overflow.page, 0,
 365                                              PAGE_SIZE, rq->buff.map_dir);
 366         if (dma_mapping_error(rq->pdev, rq->wqe_overflow.addr)) {
 367                 __free_page(rq->wqe_overflow.page);
 368                 return -ENOMEM;
 369         }
 370         return 0;
 371 }
 372
 373 static void mlx5e_free_mpwqe_rq_drop_page(struct mlx5e_rq *rq)
 374 {
 375          dma_unmap_page(rq->pdev, rq->wqe_overflow.addr, PAGE_SIZE,
 376                         rq->buff.map_dir);
 377          __free_page(rq->wqe_overflow.page);
 378 }
 379
 380 static int mlx5e_init_rxq_rq(struct mlx5e_channel *c, struct mlx5e_params *params,
 381                              struct mlx5e_rq *rq)
 382 {
 383         struct mlx5_core_dev *mdev = c->mdev;
 384         int err;
 385
 386         rq->wq_type      = params->rq_wq_type;
 387         rq->pdev         = c->pdev;
 388         rq->netdev       = c->netdev;
 389         rq->priv         = c->priv;
 390         rq->tstamp       = c->tstamp;
 391         rq->clock        = &mdev->clock;
 392         rq->icosq        = &c->icosq;
 393         rq->ix           = c->ix;
 394         rq->mdev         = mdev;
 395         rq->hw_mtu       = MLX5E_SW2HW_MTU(params, params->sw_mtu);
 396         rq->xdpsq        = &c->rq_xdpsq;
 397         rq->stats        = &c->priv->channel_stats[c->ix].rq;
 398         rq->ptp_cyc2time = mlx5_rq_ts_translator(mdev);
 399         err = mlx5e_rq_set_handlers(rq, params, NULL);
 400         if (err)
 401                 return err;
 402
 403         return xdp_rxq_info_reg(&rq->xdp_rxq, rq->netdev, rq->ix, 0);
 404 }
 405
 406 static int mlx5e_alloc_rq(struct mlx5e_params *params,
 407                           struct mlx5e_xsk_param *xsk,
 408                           struct mlx5e_rq_param *rqp,
 409                           int node, struct mlx5e_rq *rq)
 410 {
 411         struct page_pool_params pp_params = { 0 };
 412         struct mlx5_core_dev *mdev = rq->mdev;
 413         void *rqc = rqp->rqc;
 414         void *rqc_wq = MLX5_ADDR_OF(rqc, rqc, wq);
 415         u32 pool_size;
 416         int wq_sz;
 417         int err;
 418         int i;
 419
 420         rqp->wq.db_numa_node = node;
 421         INIT_WORK(&rq->recover_work, mlx5e_rq_err_cqe_work);
 422
 423         if (params->xdp_prog)
 424                 bpf_prog_inc(params->xdp_prog);
 425         RCU_INIT_POINTER(rq->xdp_prog, params->xdp_prog);
 426
 427         rq->buff.map_dir = params->xdp_prog ? DMA_BIDIRECTIONAL : DMA_FROM_DEVICE;
 428         rq->buff.headroom = mlx5e_get_rq_headroom(mdev, params, xsk);
 429         pool_size = 1 << params->log_rq_mtu_frames;
 430
 431         switch (rq->wq_type) {
 432         case MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ:
 433                 err = mlx5_wq_ll_create(mdev, &rqp->wq, rqc_wq, &rq->mpwqe.wq,
 434                                         &rq->wq_ctrl);
 435                 if (err)
 436                         goto err_rq_xdp_prog;
 437
 438                 err = mlx5e_alloc_mpwqe_rq_drop_page(rq);
 439                 if (err)
 440                         goto err_rq_wq_destroy;
 441
 442                 rq->mpwqe.wq.db = &rq->mpwqe.wq.db[MLX5_RCV_DBR];
 443
 444                 wq_sz = mlx5_wq_ll_get_size(&rq->mpwqe.wq);
 445
 446                 pool_size = MLX5_MPWRQ_PAGES_PER_WQE <<
 447                         mlx5e_mpwqe_get_log_rq_size(params, xsk);
 448
 449                 rq->mpwqe.log_stride_sz = mlx5e_mpwqe_get_log_stride_size(mdev, params, xsk);
 450                 rq->mpwqe.num_strides =
 451                         BIT(mlx5e_mpwqe_get_log_num_strides(mdev, params, xsk));
 452
 453                 rq->buff.frame0_sz = (1 << rq->mpwqe.log_stride_sz);
 454
 455                 err = mlx5e_create_rq_umr_mkey(mdev, rq);
 456                 if (err)
 457                         goto err_rq_drop_page;
 458                 rq->mkey_be = cpu_to_be32(rq->umr_mkey.key);
 459
 460                 err = mlx5e_rq_alloc_mpwqe_info(rq, node);
 461                 if (err)
 462                         goto err_rq_mkey;
 463                 break;
 464         default: /* MLX5_WQ_TYPE_CYCLIC */
 465                 err = mlx5_wq_cyc_create(mdev, &rqp->wq, rqc_wq, &rq->wqe.wq,
 466                                          &rq->wq_ctrl);
 467                 if (err)
 468                         goto err_rq_xdp_prog;
 469
 470                 rq->wqe.wq.db = &rq->wqe.wq.db[MLX5_RCV_DBR];
 471
 472                 wq_sz = mlx5_wq_cyc_get_size(&rq->wqe.wq);
 473
 474                 rq->wqe.info = rqp->frags_info;
 475                 rq->buff.frame0_sz = rq->wqe.info.arr[0].frag_stride;
 476
 477                 rq->wqe.frags =
 478                         kvzalloc_node(array_size(sizeof(*rq->wqe.frags),
 479                                         (wq_sz << rq->wqe.info.log_num_frags)),
 480                                       GFP_KERNEL, node);
 481                 if (!rq->wqe.frags) {
 482                         err = -ENOMEM;
 483                         goto err_rq_wq_destroy;
 484                 }
 485
 486                 err = mlx5e_init_di_list(rq, wq_sz, node);
 487                 if (err)
 488                         goto err_rq_frags;
 489
 490                 rq->mkey_be = cpu_to_be32(mdev->mlx5e_res.hw_objs.mkey.key);
 491         }
 492
 493         if (xsk) {
 494                 err = xdp_rxq_info_reg_mem_model(&rq->xdp_rxq,
 495                                                  MEM_TYPE_XSK_BUFF_POOL, NULL);
 496                 xsk_pool_set_rxq_info(rq->xsk_pool, &rq->xdp_rxq);
 497         } else {
 498                 /* Create a page_pool and register it with rxq */
 499                 pp_params.order     = 0;
 500                 pp_params.flags     = 0; /* No-internal DMA mapping in page_pool */
 501                 pp_params.pool_size = pool_size;
 502                 pp_params.nid       = node;
 503                 pp_params.dev       = rq->pdev;
 504                 pp_params.dma_dir   = rq->buff.map_dir;
 505
 506                 /* page_pool can be used even when there is no rq->xdp_prog,
 507                  * given page_pool does not handle DMA mapping there is no
 508                  * required state to clear. And page_pool gracefully handle
 509                  * elevated refcnt.
 510                  */
 511                 rq->page_pool = page_pool_create(&pp_params);
 512                 if (IS_ERR(rq->page_pool)) {
 513                         err = PTR_ERR(rq->page_pool);
 514                         rq->page_pool = NULL;
 515                         goto err_free_by_rq_type;
 516                 }
 517                 if (xdp_rxq_info_is_reg(&rq->xdp_rxq))
 518                         err = xdp_rxq_info_reg_mem_model(&rq->xdp_rxq,
 519                                                          MEM_TYPE_PAGE_POOL, rq->page_pool);
 520         }
 521         if (err)
 522                 goto err_free_by_rq_type;
 523
 524         for (i = 0; i < wq_sz; i++) {
 525                 if (rq->wq_type == MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ) {
 526                         struct mlx5e_rx_wqe_ll *wqe =
 527                                 mlx5_wq_ll_get_wqe(&rq->mpwqe.wq, i);
 528                         u32 byte_count =
 529                                 rq->mpwqe.num_strides << rq->mpwqe.log_stride_sz;
 530                         u64 dma_offset = mlx5e_get_mpwqe_offset(i);
 531
 532                         wqe->data[0].addr = cpu_to_be64(dma_offset + rq->buff.headroom);
 533                         wqe->data[0].byte_count = cpu_to_be32(byte_count);
 534                         wqe->data[0].lkey = rq->mkey_be;
 535                 } else {
 536                         struct mlx5e_rx_wqe_cyc *wqe =
 537                                 mlx5_wq_cyc_get_wqe(&rq->wqe.wq, i);
 538                         int f;
 539
 540                         for (f = 0; f < rq->wqe.info.num_frags; f++) {
 541                                 u32 frag_size = rq->wqe.info.arr[f].frag_size |
 542                                         MLX5_HW_START_PADDING;
 543
 544                                 wqe->data[f].byte_count = cpu_to_be32(frag_size);
 545                                 wqe->data[f].lkey = rq->mkey_be;
 546                         }
 547                         /* check if num_frags is not a pow of two */
 548                         if (rq->wqe.info.num_frags < (1 << rq->wqe.info.log_num_frags)) {
 549                                 wqe->data[f].byte_count = 0;
 550                                 wqe->data[f].lkey = cpu_to_be32(MLX5_INVALID_LKEY);
 551                                 wqe->data[f].addr = 0;
 552                         }
 553                 }
 554         }
 555
 556         INIT_WORK(&rq->dim.work, mlx5e_rx_dim_work);
 557
 558         switch (params->rx_cq_moderation.cq_period_mode) {
 559         case MLX5_CQ_PERIOD_MODE_START_FROM_CQE:
 560                 rq->dim.mode = DIM_CQ_PERIOD_MODE_START_FROM_CQE;
 561                 break;
 562         case MLX5_CQ_PERIOD_MODE_START_FROM_EQE:
 563         default:
 564                 rq->dim.mode = DIM_CQ_PERIOD_MODE_START_FROM_EQE;
 565         }
 566
 567         rq->page_cache.head = 0;
 568         rq->page_cache.tail = 0;
 569
 570         return 0;
 571
 572 err_free_by_rq_type:
 573         switch (rq->wq_type) {
 574         case MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ:
 575                 kvfree(rq->mpwqe.info);
 576 err_rq_mkey:
 577                 mlx5_core_destroy_mkey(mdev, &rq->umr_mkey);
 578 err_rq_drop_page:
 579                 mlx5e_free_mpwqe_rq_drop_page(rq);
 580                 break;
 581         default: /* MLX5_WQ_TYPE_CYCLIC */
 582                 mlx5e_free_di_list(rq);
 583 err_rq_frags:
 584                 kvfree(rq->wqe.frags);
 585         }
 586 err_rq_wq_destroy:
 587         mlx5_wq_destroy(&rq->wq_ctrl);
 588 err_rq_xdp_prog:
 589         if (params->xdp_prog)
 590                 bpf_prog_put(params->xdp_prog);
 591
 592         return err;
 593 }
 594
 595 static void mlx5e_free_rq(struct mlx5e_rq *rq)
 596 {
 597         struct bpf_prog *old_prog;
 598         int i;
 599
 600         if (xdp_rxq_info_is_reg(&rq->xdp_rxq)) {
 601                 old_prog = rcu_dereference_protected(rq->xdp_prog,
 602                                                      lockdep_is_held(&rq->priv->state_lock));
 603                 if (old_prog)
 604                         bpf_prog_put(old_prog);
 605         }
 606
 607         switch (rq->wq_type) {
 608         case MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ:
 609                 kvfree(rq->mpwqe.info);
 610                 mlx5_core_destroy_mkey(rq->mdev, &rq->umr_mkey);
 611                 mlx5e_free_mpwqe_rq_drop_page(rq);
 612                 break;
 613         default: /* MLX5_WQ_TYPE_CYCLIC */
 614                 kvfree(rq->wqe.frags);
 615                 mlx5e_free_di_list(rq);
 616         }
 617
 618         for (i = rq->page_cache.head; i != rq->page_cache.tail;
 619              i = (i + 1) & (MLX5E_CACHE_SIZE - 1)) {
 620                 struct mlx5e_dma_info *dma_info = &rq->page_cache.page_cache[i];
 621
 622                 /* With AF_XDP, page_cache is not used, so this loop is not
 623                  * entered, and it's safe to call mlx5e_page_release_dynamic
 624                  * directly.
 625                  */
 626                 mlx5e_page_release_dynamic(rq, dma_info, false);
 627         }
 628
 629         xdp_rxq_info_unreg(&rq->xdp_rxq);
 630         page_pool_destroy(rq->page_pool);
 631         mlx5_wq_destroy(&rq->wq_ctrl);
 632 }
 633
 634 int mlx5e_create_rq(struct mlx5e_rq *rq, struct mlx5e_rq_param *param)
 635 {
 636         struct mlx5_core_dev *mdev = rq->mdev;
 637         u8 ts_format;
 638         void *in;
 639         void *rqc;
 640         void *wq;
 641         int inlen;
 642         int err;
 643
 644         inlen = MLX5_ST_SZ_BYTES(create_rq_in) +
 645                 sizeof(u64) * rq->wq_ctrl.buf.npages;
 646         in = kvzalloc(inlen, GFP_KERNEL);
 647         if (!in)
 648                 return -ENOMEM;
 649
 650         ts_format = mlx5_is_real_time_rq(mdev) ?
 651                             MLX5_TIMESTAMP_FORMAT_REAL_TIME :
 652                             MLX5_TIMESTAMP_FORMAT_FREE_RUNNING;
 653         rqc = MLX5_ADDR_OF(create_rq_in, in, ctx);
 654         wq  = MLX5_ADDR_OF(rqc, rqc, wq);
 655
 656         memcpy(rqc, param->rqc, sizeof(param->rqc));
 657
 658         MLX5_SET(rqc,  rqc, cqn,                rq->cq.mcq.cqn);
 659         MLX5_SET(rqc,  rqc, state,              MLX5_RQC_STATE_RST);
 660         MLX5_SET(rqc,  rqc, ts_format,          ts_format);
 661         MLX5_SET(wq,   wq,  log_wq_pg_sz,       rq->wq_ctrl.buf.page_shift -
 662                                                 MLX5_ADAPTER_PAGE_SHIFT);
 663         MLX5_SET64(wq, wq,  dbr_addr,           rq->wq_ctrl.db.dma);
 664
 665         mlx5_fill_page_frag_array(&rq->wq_ctrl.buf,
 666                                   (__be64 *)MLX5_ADDR_OF(wq, wq, pas));
 667
 668         err = mlx5_core_create_rq(mdev, in, inlen, &rq->rqn);
 669
 670         kvfree(in);
 671
 672         return err;
 673 }
 674
 675 int mlx5e_modify_rq_state(struct mlx5e_rq *rq, int curr_state, int next_state)
 676 {
 677         struct mlx5_core_dev *mdev = rq->mdev;
 678
 679         void *in;
 680         void *rqc;
 681         int inlen;
 682         int err;
 683
 684         inlen = MLX5_ST_SZ_BYTES(modify_rq_in);
 685         in = kvzalloc(inlen, GFP_KERNEL);
 686         if (!in)
 687                 return -ENOMEM;
 688
 689         if (curr_state == MLX5_RQC_STATE_RST && next_state == MLX5_RQC_STATE_RDY)
 690                 mlx5e_rqwq_reset(rq);
 691
 692         rqc = MLX5_ADDR_OF(modify_rq_in, in, ctx);
 693
 694         MLX5_SET(modify_rq_in, in, rq_state, curr_state);
 695         MLX5_SET(rqc, rqc, state, next_state);
 696
 697         err = mlx5_core_modify_rq(mdev, rq->rqn, in);
 698
 699         kvfree(in);
 700
 701         return err;
 702 }
 703
 704 static int mlx5e_modify_rq_scatter_fcs(struct mlx5e_rq *rq, bool enable)
 705 {
 706         struct mlx5_core_dev *mdev = rq->mdev;
 707
 708         void *in;
 709         void *rqc;
 710         int inlen;
 711         int err;
 712
 713         inlen = MLX5_ST_SZ_BYTES(modify_rq_in);
 714         in = kvzalloc(inlen, GFP_KERNEL);
 715         if (!in)
 716                 return -ENOMEM;
 717
 718         rqc = MLX5_ADDR_OF(modify_rq_in, in, ctx);
 719
 720         MLX5_SET(modify_rq_in, in, rq_state, MLX5_RQC_STATE_RDY);
 721         MLX5_SET64(modify_rq_in, in, modify_bitmask,
 722                    MLX5_MODIFY_RQ_IN_MODIFY_BITMASK_SCATTER_FCS);
 723         MLX5_SET(rqc, rqc, scatter_fcs, enable);
 724         MLX5_SET(rqc, rqc, state, MLX5_RQC_STATE_RDY);
 725
 726         err = mlx5_core_modify_rq(mdev, rq->rqn, in);
 727
 728         kvfree(in);
 729
 730         return err;
 731 }
 732
 733 static int mlx5e_modify_rq_vsd(struct mlx5e_rq *rq, bool vsd)
 734 {
 735         struct mlx5_core_dev *mdev = rq->mdev;
 736         void *in;
 737         void *rqc;
 738         int inlen;
 739         int err;
 740
 741         inlen = MLX5_ST_SZ_BYTES(modify_rq_in);
 742         in = kvzalloc(inlen, GFP_KERNEL);
 743         if (!in)
 744                 return -ENOMEM;
 745
 746         rqc = MLX5_ADDR_OF(modify_rq_in, in, ctx);
 747
 748         MLX5_SET(modify_rq_in, in, rq_state, MLX5_RQC_STATE_RDY);
 749         MLX5_SET64(modify_rq_in, in, modify_bitmask,
 750                    MLX5_MODIFY_RQ_IN_MODIFY_BITMASK_VSD);
 751         MLX5_SET(rqc, rqc, vsd, vsd);
 752         MLX5_SET(rqc, rqc, state, MLX5_RQC_STATE_RDY);
 753
 754         err = mlx5_core_modify_rq(mdev, rq->rqn, in);
 755
 756         kvfree(in);
 757
 758         return err;
 759 }
 760
 761 void mlx5e_destroy_rq(struct mlx5e_rq *rq)
 762 {
 763         mlx5_core_destroy_rq(rq->mdev, rq->rqn);
 764 }
 765
 766 int mlx5e_wait_for_min_rx_wqes(struct mlx5e_rq *rq, int wait_time)
 767 {
 768         unsigned long exp_time = jiffies + msecs_to_jiffies(wait_time);
 769
 770         u16 min_wqes = mlx5_min_rx_wqes(rq->wq_type, mlx5e_rqwq_get_size(rq));
 771
 772         do {
 773                 if (mlx5e_rqwq_get_cur_sz(rq) >= min_wqes)
 774                         return 0;
 775
 776                 msleep(20);
 777         } while (time_before(jiffies, exp_time));
 778
 779         netdev_warn(rq->netdev, "Failed to get min RX wqes on Channel[%d] RQN[0x%x] wq cur_sz(%d) min_rx_wqes(%d)\n",
 780                     rq->ix, rq->rqn, mlx5e_rqwq_get_cur_sz(rq), min_wqes);
 781
 782         mlx5e_reporter_rx_timeout(rq);
 783         return -ETIMEDOUT;
 784 }
 785
 786 void mlx5e_free_rx_in_progress_descs(struct mlx5e_rq *rq)
 787 {
 788         struct mlx5_wq_ll *wq;
 789         u16 head;
 790         int i;
 791
 792         if (rq->wq_type != MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ)
 793                 return;
 794
 795         wq = &rq->mpwqe.wq;
 796         head = wq->head;
 797
 798         /* Outstanding UMR WQEs (in progress) start at wq->head */
 799         for (i = 0; i < rq->mpwqe.umr_in_progress; i++) {
 800                 rq->dealloc_wqe(rq, head);
 801                 head = mlx5_wq_ll_get_wqe_next_ix(wq, head);
 802         }
 803
 804         rq->mpwqe.actual_wq_head = wq->head;
 805         rq->mpwqe.umr_in_progress = 0;
 806         rq->mpwqe.umr_completed = 0;
 807 }
 808
 809 void mlx5e_free_rx_descs(struct mlx5e_rq *rq)
 810 {
 811         __be16 wqe_ix_be;
 812         u16 wqe_ix;
 813
 814         if (rq->wq_type == MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ) {
 815                 struct mlx5_wq_ll *wq = &rq->mpwqe.wq;
 816
 817                 mlx5e_free_rx_in_progress_descs(rq);
 818
 819                 while (!mlx5_wq_ll_is_empty(wq)) {
 820                         struct mlx5e_rx_wqe_ll *wqe;
 821
 822                         wqe_ix_be = *wq->tail_next;
 823                         wqe_ix    = be16_to_cpu(wqe_ix_be);
 824                         wqe       = mlx5_wq_ll_get_wqe(wq, wqe_ix);
 825                         rq->dealloc_wqe(rq, wqe_ix);
 826                         mlx5_wq_ll_pop(wq, wqe_ix_be,
 827                                        &wqe->next.next_wqe_index);
 828                 }
 829         } else {
 830                 struct mlx5_wq_cyc *wq = &rq->wqe.wq;
 831
 832                 while (!mlx5_wq_cyc_is_empty(wq)) {
 833                         wqe_ix = mlx5_wq_cyc_get_tail(wq);
 834                         rq->dealloc_wqe(rq, wqe_ix);
 835                         mlx5_wq_cyc_pop(wq);
 836                 }
 837         }
 838
 839 }
 840
 841 int mlx5e_open_rq(struct mlx5e_params *params, struct mlx5e_rq_param *param,
 842                   struct mlx5e_xsk_param *xsk, int node,
 843                   struct mlx5e_rq *rq)
 844 {
 845         struct mlx5_core_dev *mdev = rq->mdev;
 846         int err;
 847
 848         err = mlx5e_alloc_rq(params, xsk, param, node, rq);
 849         if (err)
 850                 return err;
 851
 852         err = mlx5e_create_rq(rq, param);
 853         if (err)
 854                 goto err_free_rq;
 855
 856         err = mlx5e_modify_rq_state(rq, MLX5_RQC_STATE_RST, MLX5_RQC_STATE_RDY);
 857         if (err)
 858                 goto err_destroy_rq;
 859
 860         if (mlx5e_is_tls_on(rq->priv) && !mlx5e_accel_is_ktls_device(mdev))
 861                 __set_bit(MLX5E_RQ_STATE_FPGA_TLS, &rq->state); /* must be FPGA */
 862
 863         if (MLX5_CAP_ETH(mdev, cqe_checksum_full))
 864                 __set_bit(MLX5E_RQ_STATE_CSUM_FULL, &rq->state);
 865
 866         if (params->rx_dim_enabled)
 867                 __set_bit(MLX5E_RQ_STATE_AM, &rq->state);
 868
 869         /* We disable csum_complete when XDP is enabled since
 870          * XDP programs might manipulate packets which will render
 871          * skb->checksum incorrect.
 872          */
 873         if (MLX5E_GET_PFLAG(params, MLX5E_PFLAG_RX_NO_CSUM_COMPLETE) || params->xdp_prog)
 874                 __set_bit(MLX5E_RQ_STATE_NO_CSUM_COMPLETE, &rq->state);
 875
 876         /* For CQE compression on striding RQ, use stride index provided by
 877          * HW if capability is supported.
 878          */
 879         if (MLX5E_GET_PFLAG(params, MLX5E_PFLAG_RX_STRIDING_RQ) &&
 880             MLX5_CAP_GEN(mdev, mini_cqe_resp_stride_index))
 881                 __set_bit(MLX5E_RQ_STATE_MINI_CQE_HW_STRIDX, &rq->state);
 882
 883         return 0;
 884
 885 err_destroy_rq:
 886         mlx5e_destroy_rq(rq);
 887 err_free_rq:
 888         mlx5e_free_rq(rq);
 889
 890         return err;
 891 }
 892
 893 void mlx5e_activate_rq(struct mlx5e_rq *rq)
 894 {
 895         set_bit(MLX5E_RQ_STATE_ENABLED, &rq->state);
 896         if (rq->icosq) {
 897                 mlx5e_trigger_irq(rq->icosq);
 898         } else {
 899                 local_bh_disable();
 900                 napi_schedule(rq->cq.napi);
 901                 local_bh_enable();
 902         }
 903 }
 904
 905 void mlx5e_deactivate_rq(struct mlx5e_rq *rq)
 906 {
 907         clear_bit(MLX5E_RQ_STATE_ENABLED, &rq->state);
 908         synchronize_net(); /* Sync with NAPI to prevent mlx5e_post_rx_wqes. */
 909 }
 910
 911 void mlx5e_close_rq(struct mlx5e_rq *rq)
 912 {
 913         cancel_work_sync(&rq->dim.work);
 914         if (rq->icosq)
 915                 cancel_work_sync(&rq->icosq->recover_work);
 916         cancel_work_sync(&rq->recover_work);
 917         mlx5e_destroy_rq(rq);
 918         mlx5e_free_rx_descs(rq);
 919         mlx5e_free_rq(rq);
 920 }
 921
 922 static void mlx5e_free_xdpsq_db(struct mlx5e_xdpsq *sq)
 923 {
 924         kvfree(sq->db.xdpi_fifo.xi);
 925         kvfree(sq->db.wqe_info);
 926 }
 927
 928 static int mlx5e_alloc_xdpsq_fifo(struct mlx5e_xdpsq *sq, int numa)
 929 {
 930         struct mlx5e_xdp_info_fifo *xdpi_fifo = &sq->db.xdpi_fifo;
 931         int wq_sz        = mlx5_wq_cyc_get_size(&sq->wq);
 932         int dsegs_per_wq = wq_sz * MLX5_SEND_WQEBB_NUM_DS;
 933         size_t size;
 934
 935         size = array_size(sizeof(*xdpi_fifo->xi), dsegs_per_wq);
 936         xdpi_fifo->xi = kvzalloc_node(size, GFP_KERNEL, numa);
 937         if (!xdpi_fifo->xi)
 938                 return -ENOMEM;
 939
 940         xdpi_fifo->pc   = &sq->xdpi_fifo_pc;
 941         xdpi_fifo->cc   = &sq->xdpi_fifo_cc;
 942         xdpi_fifo->mask = dsegs_per_wq - 1;
 943
 944         return 0;
 945 }
 946
 947 static int mlx5e_alloc_xdpsq_db(struct mlx5e_xdpsq *sq, int numa)
 948 {
 949         int wq_sz = mlx5_wq_cyc_get_size(&sq->wq);
 950         size_t size;
 951         int err;
 952
 953         size = array_size(sizeof(*sq->db.wqe_info), wq_sz);
 954         sq->db.wqe_info = kvzalloc_node(size, GFP_KERNEL, numa);
 955         if (!sq->db.wqe_info)
 956                 return -ENOMEM;
 957
 958         err = mlx5e_alloc_xdpsq_fifo(sq, numa);
 959         if (err) {
 960                 mlx5e_free_xdpsq_db(sq);
 961                 return err;
 962         }
 963
 964         return 0;
 965 }
 966
 967 static int mlx5e_alloc_xdpsq(struct mlx5e_channel *c,
 968                              struct mlx5e_params *params,
 969                              struct xsk_buff_pool *xsk_pool,
 970                              struct mlx5e_sq_param *param,
 971                              struct mlx5e_xdpsq *sq,
 972                              bool is_redirect)
 973 {
 974         void *sqc_wq               = MLX5_ADDR_OF(sqc, param->sqc, wq);
 975         struct mlx5_core_dev *mdev = c->mdev;
 976         struct mlx5_wq_cyc *wq = &sq->wq;
 977         int err;
 978
 979         sq->pdev      = c->pdev;
 980         sq->mkey_be   = c->mkey_be;
 981         sq->channel   = c;
 982         sq->uar_map   = mdev->mlx5e_res.hw_objs.bfreg.map;
 983         sq->min_inline_mode = params->tx_min_inline_mode;
 984         sq->hw_mtu    = MLX5E_SW2HW_MTU(params, params->sw_mtu);
 985         sq->xsk_pool  = xsk_pool;
 986
 987         sq->stats = sq->xsk_pool ?
 988                 &c->priv->channel_stats[c->ix].xsksq :
 989                 is_redirect ?
 990                         &c->priv->channel_stats[c->ix].xdpsq :
 991                         &c->priv->channel_stats[c->ix].rq_xdpsq;
 992
 993         param->wq.db_numa_node = cpu_to_node(c->cpu);
 994         err = mlx5_wq_cyc_create(mdev, &param->wq, sqc_wq, wq, &sq->wq_ctrl);
 995         if (err)
 996                 return err;
 997         wq->db = &wq->db[MLX5_SND_DBR];
 998
 999         err = mlx5e_alloc_xdpsq_db(sq, cpu_to_node(c->cpu));
1000         if (err)
1001                 goto err_sq_wq_destroy;
1002
1003         return 0;
1004
1005 err_sq_wq_destroy:
1006         mlx5_wq_destroy(&sq->wq_ctrl);
1007
1008         return err;
1009 }
1010
1011 static void mlx5e_free_xdpsq(struct mlx5e_xdpsq *sq)
1012 {
1013         mlx5e_free_xdpsq_db(sq);
1014         mlx5_wq_destroy(&sq->wq_ctrl);
1015 }
1016
1017 static void mlx5e_free_icosq_db(struct mlx5e_icosq *sq)
1018 {
1019         kvfree(sq->db.wqe_info);
1020 }
1021
1022 static int mlx5e_alloc_icosq_db(struct mlx5e_icosq *sq, int numa)
1023 {
1024         int wq_sz = mlx5_wq_cyc_get_size(&sq->wq);
1025         size_t size;
1026
1027         size = array_size(wq_sz, sizeof(*sq->db.wqe_info));
1028         sq->db.wqe_info = kvzalloc_node(size, GFP_KERNEL, numa);
1029         if (!sq->db.wqe_info)
1030                 return -ENOMEM;
1031
1032         return 0;
1033 }
1034
1035 static void mlx5e_icosq_err_cqe_work(struct work_struct *recover_work)
1036 {
1037         struct mlx5e_icosq *sq = container_of(recover_work, struct mlx5e_icosq,
1038                                               recover_work);
1039
1040         mlx5e_reporter_icosq_cqe_err(sq);
1041 }
1042
1043 static int mlx5e_alloc_icosq(struct mlx5e_channel *c,
1044                              struct mlx5e_sq_param *param,
1045                              struct mlx5e_icosq *sq)
1046 {
1047         void *sqc_wq               = MLX5_ADDR_OF(sqc, param->sqc, wq);
1048         struct mlx5_core_dev *mdev = c->mdev;
1049         struct mlx5_wq_cyc *wq = &sq->wq;
1050         int err;
1051
1052         sq->channel   = c;
1053         sq->uar_map   = mdev->mlx5e_res.hw_objs.bfreg.map;
1054         sq->reserved_room = param->stop_room;
1055
1056         param->wq.db_numa_node = cpu_to_node(c->cpu);
1057         err = mlx5_wq_cyc_create(mdev, &param->wq, sqc_wq, wq, &sq->wq_ctrl);
1058         if (err)
1059                 return err;
1060         wq->db = &wq->db[MLX5_SND_DBR];
1061
1062         err = mlx5e_alloc_icosq_db(sq, cpu_to_node(c->cpu));
1063         if (err)
1064                 goto err_sq_wq_destroy;
1065
1066         INIT_WORK(&sq->recover_work, mlx5e_icosq_err_cqe_work);
1067
1068         return 0;
1069
1070 err_sq_wq_destroy:
1071         mlx5_wq_destroy(&sq->wq_ctrl);
1072
1073         return err;
1074 }
1075
1076 static void mlx5e_free_icosq(struct mlx5e_icosq *sq)
1077 {
1078         mlx5e_free_icosq_db(sq);
1079         mlx5_wq_destroy(&sq->wq_ctrl);
1080 }
1081
1082 void mlx5e_free_txqsq_db(struct mlx5e_txqsq *sq)
1083 {
1084         kvfree(sq->db.wqe_info);
1085         kvfree(sq->db.skb_fifo.fifo);
1086         kvfree(sq->db.dma_fifo);
1087 }
1088
1089 int mlx5e_alloc_txqsq_db(struct mlx5e_txqsq *sq, int numa)
1090 {
1091         int wq_sz = mlx5_wq_cyc_get_size(&sq->wq);
1092         int df_sz = wq_sz * MLX5_SEND_WQEBB_NUM_DS;
1093
1094         sq->db.dma_fifo = kvzalloc_node(array_size(df_sz,
1095                                                    sizeof(*sq->db.dma_fifo)),
1096                                         GFP_KERNEL, numa);
1097         sq->db.skb_fifo.fifo = kvzalloc_node(array_size(df_sz,
1098                                                         sizeof(*sq->db.skb_fifo.fifo)),
1099                                         GFP_KERNEL, numa);
1100         sq->db.wqe_info = kvzalloc_node(array_size(wq_sz,
1101                                                    sizeof(*sq->db.wqe_info)),
1102                                         GFP_KERNEL, numa);
1103         if (!sq->db.dma_fifo || !sq->db.skb_fifo.fifo || !sq->db.wqe_info) {
1104                 mlx5e_free_txqsq_db(sq);
1105                 return -ENOMEM;
1106         }
1107
1108         sq->dma_fifo_mask = df_sz - 1;
1109
1110         sq->db.skb_fifo.pc   = &sq->skb_fifo_pc;
1111         sq->db.skb_fifo.cc   = &sq->skb_fifo_cc;
1112         sq->db.skb_fifo.mask = df_sz - 1;
1113
1114         return 0;
1115 }
1116
1117 static int mlx5e_alloc_txqsq(struct mlx5e_channel *c,
1118                              int txq_ix,
1119                              struct mlx5e_params *params,
1120                              struct mlx5e_sq_param *param,
1121                              struct mlx5e_txqsq *sq,
1122                              int tc)
1123 {
1124         void *sqc_wq               = MLX5_ADDR_OF(sqc, param->sqc, wq);
1125         struct mlx5_core_dev *mdev = c->mdev;
1126         struct mlx5_wq_cyc *wq = &sq->wq;
1127         int err;
1128
1129         sq->pdev      = c->pdev;
1130         sq->tstamp    = c->tstamp;
1131         sq->clock     = &mdev->clock;
1132         sq->mkey_be   = c->mkey_be;
1133         sq->netdev    = c->netdev;
1134         sq->mdev      = c->mdev;
1135         sq->priv      = c->priv;
1136         sq->ch_ix     = c->ix;
1137         sq->txq_ix    = txq_ix;
1138         sq->uar_map   = mdev->mlx5e_res.hw_objs.bfreg.map;
1139         sq->min_inline_mode = params->tx_min_inline_mode;
1140         sq->hw_mtu    = MLX5E_SW2HW_MTU(params, params->sw_mtu);
1141         INIT_WORK(&sq->recover_work, mlx5e_tx_err_cqe_work);
1142         if (!MLX5_CAP_ETH(mdev, wqe_vlan_insert))
1143                 set_bit(MLX5E_SQ_STATE_VLAN_NEED_L2_INLINE, &sq->state);
1144         if (MLX5_IPSEC_DEV(c->priv->mdev))
1145                 set_bit(MLX5E_SQ_STATE_IPSEC, &sq->state);
1146         if (param->is_mpw)
1147                 set_bit(MLX5E_SQ_STATE_MPWQE, &sq->state);
1148         sq->stop_room = param->stop_room;
1149         sq->ptp_cyc2time = mlx5_sq_ts_translator(mdev);
1150
1151         param->wq.db_numa_node = cpu_to_node(c->cpu);
1152         err = mlx5_wq_cyc_create(mdev, &param->wq, sqc_wq, wq, &sq->wq_ctrl);
1153         if (err)
1154                 return err;
1155         wq->db    = &wq->db[MLX5_SND_DBR];
1156
1157         err = mlx5e_alloc_txqsq_db(sq, cpu_to_node(c->cpu));
1158         if (err)
1159                 goto err_sq_wq_destroy;
1160
1161         INIT_WORK(&sq->dim.work, mlx5e_tx_dim_work);
1162         sq->dim.mode = params->tx_cq_moderation.cq_period_mode;
1163
1164         return 0;
1165
1166 err_sq_wq_destroy:
1167         mlx5_wq_destroy(&sq->wq_ctrl);
1168
1169         return err;
1170 }
1171
1172 void mlx5e_free_txqsq(struct mlx5e_txqsq *sq)
1173 {
1174         mlx5e_free_txqsq_db(sq);
1175         mlx5_wq_destroy(&sq->wq_ctrl);
1176 }
1177
1178 static int mlx5e_create_sq(struct mlx5_core_dev *mdev,
1179                            struct mlx5e_sq_param *param,
1180                            struct mlx5e_create_sq_param *csp,
1181                            u32 *sqn)
1182 {
1183         u8 ts_format;
1184         void *in;
1185         void *sqc;
1186         void *wq;
1187         int inlen;
1188         int err;
1189
1190         inlen = MLX5_ST_SZ_BYTES(create_sq_in) +
1191                 sizeof(u64) * csp->wq_ctrl->buf.npages;
1192         in = kvzalloc(inlen, GFP_KERNEL);
1193         if (!in)
1194                 return -ENOMEM;
1195
1196         ts_format = mlx5_is_real_time_sq(mdev) ?
1197                             MLX5_TIMESTAMP_FORMAT_REAL_TIME :
1198                             MLX5_TIMESTAMP_FORMAT_FREE_RUNNING;
1199         sqc = MLX5_ADDR_OF(create_sq_in, in, ctx);
1200         wq = MLX5_ADDR_OF(sqc, sqc, wq);
1201
1202         memcpy(sqc, param->sqc, sizeof(param->sqc));
1203         MLX5_SET(sqc,  sqc, tis_lst_sz, csp->tis_lst_sz);
1204         MLX5_SET(sqc,  sqc, tis_num_0, csp->tisn);
1205         MLX5_SET(sqc,  sqc, cqn, csp->cqn);
1206         MLX5_SET(sqc,  sqc, ts_cqe_to_dest_cqn, csp->ts_cqe_to_dest_cqn);
1207         MLX5_SET(sqc,  sqc, ts_format, ts_format);
1208
1209
1210         if (MLX5_CAP_ETH(mdev, wqe_inline_mode) == MLX5_CAP_INLINE_MODE_VPORT_CONTEXT)
1211                 MLX5_SET(sqc,  sqc, min_wqe_inline_mode, csp->min_inline_mode);
1212
1213         MLX5_SET(sqc,  sqc, state, MLX5_SQC_STATE_RST);
1214         MLX5_SET(sqc,  sqc, flush_in_error_en, 1);
1215
1216         MLX5_SET(wq,   wq, wq_type,       MLX5_WQ_TYPE_CYCLIC);
1217         MLX5_SET(wq,   wq, uar_page,      mdev->mlx5e_res.hw_objs.bfreg.index);
1218         MLX5_SET(wq,   wq, log_wq_pg_sz,  csp->wq_ctrl->buf.page_shift -
1219                                           MLX5_ADAPTER_PAGE_SHIFT);
1220         MLX5_SET64(wq, wq, dbr_addr,      csp->wq_ctrl->db.dma);
1221
1222         mlx5_fill_page_frag_array(&csp->wq_ctrl->buf,
1223                                   (__be64 *)MLX5_ADDR_OF(wq, wq, pas));
1224
1225         err = mlx5_core_create_sq(mdev, in, inlen, sqn);
1226
1227         kvfree(in);
1228
1229         return err;
1230 }
1231
1232 int mlx5e_modify_sq(struct mlx5_core_dev *mdev, u32 sqn,
1233                     struct mlx5e_modify_sq_param *p)
1234 {
1235         u64 bitmask = 0;
1236         void *in;
1237         void *sqc;
1238         int inlen;
1239         int err;
1240
1241         inlen = MLX5_ST_SZ_BYTES(modify_sq_in);
1242         in = kvzalloc(inlen, GFP_KERNEL);
1243         if (!in)
1244                 return -ENOMEM;
1245
1246         sqc = MLX5_ADDR_OF(modify_sq_in, in, ctx);
1247
1248         MLX5_SET(modify_sq_in, in, sq_state, p->curr_state);
1249         MLX5_SET(sqc, sqc, state, p->next_state);
1250         if (p->rl_update && p->next_state == MLX5_SQC_STATE_RDY) {
1251                 bitmask |= 1;
1252                 MLX5_SET(sqc, sqc, packet_pacing_rate_limit_index, p->rl_index);
1253         }
1254         if (p->qos_update && p->next_state == MLX5_SQC_STATE_RDY) {
1255                 bitmask |= 1 << 2;
1256                 MLX5_SET(sqc, sqc, qos_queue_group_id, p->qos_queue_group_id);
1257         }
1258         MLX5_SET64(modify_sq_in, in, modify_bitmask, bitmask);
1259
1260         err = mlx5_core_modify_sq(mdev, sqn, in);
1261
1262         kvfree(in);
1263
1264         return err;
1265 }
1266
1267 static void mlx5e_destroy_sq(struct mlx5_core_dev *mdev, u32 sqn)
1268 {
1269         mlx5_core_destroy_sq(mdev, sqn);
1270 }
1271
1272 int mlx5e_create_sq_rdy(struct mlx5_core_dev *mdev,
1273                         struct mlx5e_sq_param *param,
1274                         struct mlx5e_create_sq_param *csp,
1275                         u16 qos_queue_group_id,
1276                         u32 *sqn)
1277 {
1278         struct mlx5e_modify_sq_param msp = {0};
1279         int err;
1280
1281         err = mlx5e_create_sq(mdev, param, csp, sqn);
1282         if (err)
1283                 return err;
1284
1285         msp.curr_state = MLX5_SQC_STATE_RST;
1286         msp.next_state = MLX5_SQC_STATE_RDY;
1287         if (qos_queue_group_id) {
1288                 msp.qos_update = true;
1289                 msp.qos_queue_group_id = qos_queue_group_id;
1290         }
1291         err = mlx5e_modify_sq(mdev, *sqn, &msp);
1292         if (err)
1293                 mlx5e_destroy_sq(mdev, *sqn);
1294
1295         return err;
1296 }
1297
1298 static int mlx5e_set_sq_maxrate(struct net_device *dev,
1299                                 struct mlx5e_txqsq *sq, u32 rate);
1300
1301 int mlx5e_open_txqsq(struct mlx5e_channel *c, u32 tisn, int txq_ix,
1302                      struct mlx5e_params *params, struct mlx5e_sq_param *param,
1303                      struct mlx5e_txqsq *sq, int tc, u16 qos_queue_group_id, u16 qos_qid)
1304 {
1305         struct mlx5e_create_sq_param csp = {};
1306         u32 tx_rate;
1307         int err;
1308
1309         err = mlx5e_alloc_txqsq(c, txq_ix, params, param, sq, tc);
1310         if (err)
1311                 return err;
1312
1313         if (qos_queue_group_id)
1314                 sq->stats = c->priv->htb.qos_sq_stats[qos_qid];
1315         else
1316                 sq->stats = &c->priv->channel_stats[c->ix].sq[tc];
1317
1318         csp.tisn            = tisn;
1319         csp.tis_lst_sz      = 1;
1320         csp.cqn             = sq->cq.mcq.cqn;
1321         csp.wq_ctrl         = &sq->wq_ctrl;
1322         csp.min_inline_mode = sq->min_inline_mode;
1323         err = mlx5e_create_sq_rdy(c->mdev, param, &csp, qos_queue_group_id, &sq->sqn);
1324         if (err)
1325                 goto err_free_txqsq;
1326
1327         tx_rate = c->priv->tx_rates[sq->txq_ix];
1328         if (tx_rate)
1329                 mlx5e_set_sq_maxrate(c->netdev, sq, tx_rate);
1330
1331         if (params->tx_dim_enabled)
1332                 sq->state |= BIT(MLX5E_SQ_STATE_AM);
1333
1334         return 0;
1335
1336 err_free_txqsq:
1337         mlx5e_free_txqsq(sq);
1338
1339         return err;
1340 }
1341
1342 void mlx5e_activate_txqsq(struct mlx5e_txqsq *sq)
1343 {
1344         sq->txq = netdev_get_tx_queue(sq->netdev, sq->txq_ix);
1345         set_bit(MLX5E_SQ_STATE_ENABLED, &sq->state);
1346         netdev_tx_reset_queue(sq->txq);
1347         netif_tx_start_queue(sq->txq);
1348 }
1349
1350 void mlx5e_tx_disable_queue(struct netdev_queue *txq)
1351 {
1352         __netif_tx_lock_bh(txq);
1353         netif_tx_stop_queue(txq);
1354         __netif_tx_unlock_bh(txq);
1355 }
1356
1357 void mlx5e_deactivate_txqsq(struct mlx5e_txqsq *sq)
1358 {
1359         struct mlx5_wq_cyc *wq = &sq->wq;
1360
1361         clear_bit(MLX5E_SQ_STATE_ENABLED, &sq->state);
1362         synchronize_net(); /* Sync with NAPI to prevent netif_tx_wake_queue. */
1363
1364         mlx5e_tx_disable_queue(sq->txq);
1365
1366         /* last doorbell out, godspeed .. */
1367         if (mlx5e_wqc_has_room_for(wq, sq->cc, sq->pc, 1)) {
1368                 u16 pi = mlx5_wq_cyc_ctr2ix(wq, sq->pc);
1369                 struct mlx5e_tx_wqe *nop;
1370
1371                 sq->db.wqe_info[pi] = (struct mlx5e_tx_wqe_info) {
1372                         .num_wqebbs = 1,
1373                 };
1374
1375                 nop = mlx5e_post_nop(wq, sq->sqn, &sq->pc);
1376                 mlx5e_notify_hw(wq, sq->pc, sq->uar_map, &nop->ctrl);
1377         }
1378 }
1379
1380 void mlx5e_close_txqsq(struct mlx5e_txqsq *sq)
1381 {
1382         struct mlx5_core_dev *mdev = sq->mdev;
1383         struct mlx5_rate_limit rl = {0};
1384
1385         cancel_work_sync(&sq->dim.work);
1386         cancel_work_sync(&sq->recover_work);
1387         mlx5e_destroy_sq(mdev, sq->sqn);
1388         if (sq->rate_limit) {
1389                 rl.rate = sq->rate_limit;
1390                 mlx5_rl_remove_rate(mdev, &rl);
1391         }
1392         mlx5e_free_txqsq_descs(sq);
1393         mlx5e_free_txqsq(sq);
1394 }
1395
1396 void mlx5e_tx_err_cqe_work(struct work_struct *recover_work)
1397 {
1398         struct mlx5e_txqsq *sq = container_of(recover_work, struct mlx5e_txqsq,
1399                                               recover_work);
1400
1401         mlx5e_reporter_tx_err_cqe(sq);
1402 }
1403
1404 int mlx5e_open_icosq(struct mlx5e_channel *c, struct mlx5e_params *params,
1405                      struct mlx5e_sq_param *param, struct mlx5e_icosq *sq)
1406 {
1407         struct mlx5e_create_sq_param csp = {};
1408         int err;
1409
1410         err = mlx5e_alloc_icosq(c, param, sq);
1411         if (err)
1412                 return err;
1413
1414         csp.cqn             = sq->cq.mcq.cqn;
1415         csp.wq_ctrl         = &sq->wq_ctrl;
1416         csp.min_inline_mode = params->tx_min_inline_mode;
1417         err = mlx5e_create_sq_rdy(c->mdev, param, &csp, 0, &sq->sqn);
1418         if (err)
1419                 goto err_free_icosq;
1420
1421         if (param->is_tls) {
1422                 sq->ktls_resync = mlx5e_ktls_rx_resync_create_resp_list();
1423                 if (IS_ERR(sq->ktls_resync)) {
1424                         err = PTR_ERR(sq->ktls_resync);
1425                         goto err_destroy_icosq;
1426                 }
1427         }
1428         return 0;
1429
1430 err_destroy_icosq:
1431         mlx5e_destroy_sq(c->mdev, sq->sqn);
1432 err_free_icosq:
1433         mlx5e_free_icosq(sq);
1434
1435         return err;
1436 }
1437
1438 void mlx5e_activate_icosq(struct mlx5e_icosq *icosq)
1439 {
1440         set_bit(MLX5E_SQ_STATE_ENABLED, &icosq->state);
1441 }
1442
1443 void mlx5e_deactivate_icosq(struct mlx5e_icosq *icosq)
1444 {
1445         clear_bit(MLX5E_SQ_STATE_ENABLED, &icosq->state);
1446         synchronize_net(); /* Sync with NAPI. */
1447 }
1448
1449 void mlx5e_close_icosq(struct mlx5e_icosq *sq)
1450 {
1451         struct mlx5e_channel *c = sq->channel;
1452
1453         if (sq->ktls_resync)
1454                 mlx5e_ktls_rx_resync_destroy_resp_list(sq->ktls_resync);
1455         mlx5e_destroy_sq(c->mdev, sq->sqn);
1456         mlx5e_free_icosq_descs(sq);
1457         mlx5e_free_icosq(sq);
1458 }
1459
1460 int mlx5e_open_xdpsq(struct mlx5e_channel *c, struct mlx5e_params *params,
1461                      struct mlx5e_sq_param *param, struct xsk_buff_pool *xsk_pool,
1462                      struct mlx5e_xdpsq *sq, bool is_redirect)
1463 {
1464         struct mlx5e_create_sq_param csp = {};
1465         int err;
1466
1467         err = mlx5e_alloc_xdpsq(c, params, xsk_pool, param, sq, is_redirect);
1468         if (err)
1469                 return err;
1470
1471         csp.tis_lst_sz      = 1;
1472         csp.tisn            = c->priv->tisn[c->lag_port][0]; /* tc = 0 */
1473         csp.cqn             = sq->cq.mcq.cqn;
1474         csp.wq_ctrl         = &sq->wq_ctrl;
1475         csp.min_inline_mode = sq->min_inline_mode;
1476         set_bit(MLX5E_SQ_STATE_ENABLED, &sq->state);
1477         err = mlx5e_create_sq_rdy(c->mdev, param, &csp, 0, &sq->sqn);
1478         if (err)
1479                 goto err_free_xdpsq;
1480
1481         mlx5e_set_xmit_fp(sq, param->is_mpw);
1482
1483         if (!param->is_mpw) {
1484                 unsigned int ds_cnt = MLX5E_XDP_TX_DS_COUNT;
1485                 unsigned int inline_hdr_sz = 0;
1486                 int i;
1487
1488                 if (sq->min_inline_mode != MLX5_INLINE_MODE_NONE) {
1489                         inline_hdr_sz = MLX5E_XDP_MIN_INLINE;
1490                         ds_cnt++;
1491                 }
1492
1493                 /* Pre initialize fixed WQE fields */
1494                 for (i = 0; i < mlx5_wq_cyc_get_size(&sq->wq); i++) {
1495                         struct mlx5e_tx_wqe      *wqe  = mlx5_wq_cyc_get_wqe(&sq->wq, i);
1496                         struct mlx5_wqe_ctrl_seg *cseg = &wqe->ctrl;
1497                         struct mlx5_wqe_eth_seg  *eseg = &wqe->eth;
1498                         struct mlx5_wqe_data_seg *dseg;
1499
1500                         sq->db.wqe_info[i] = (struct mlx5e_xdp_wqe_info) {
1501                                 .num_wqebbs = 1,
1502                                 .num_pkts   = 1,
1503                         };
1504
1505                         cseg->qpn_ds = cpu_to_be32((sq->sqn << 8) | ds_cnt);
1506                         eseg->inline_hdr.sz = cpu_to_be16(inline_hdr_sz);
1507
1508                         dseg = (struct mlx5_wqe_data_seg *)cseg + (ds_cnt - 1);
1509                         dseg->lkey = sq->mkey_be;
1510                 }
1511         }
1512
1513         return 0;
1514
1515 err_free_xdpsq:
1516         clear_bit(MLX5E_SQ_STATE_ENABLED, &sq->state);
1517         mlx5e_free_xdpsq(sq);
1518
1519         return err;
1520 }
1521
1522 void mlx5e_close_xdpsq(struct mlx5e_xdpsq *sq)
1523 {
1524         struct mlx5e_channel *c = sq->channel;
1525
1526         clear_bit(MLX5E_SQ_STATE_ENABLED, &sq->state);
1527         synchronize_net(); /* Sync with NAPI. */
1528
1529         mlx5e_destroy_sq(c->mdev, sq->sqn);
1530         mlx5e_free_xdpsq_descs(sq);
1531         mlx5e_free_xdpsq(sq);
1532 }
1533
1534 static int mlx5e_alloc_cq_common(struct mlx5e_priv *priv,
1535                                  struct mlx5e_cq_param *param,
1536                                  struct mlx5e_cq *cq)
1537 {
1538         struct mlx5_core_dev *mdev = priv->mdev;
1539         struct mlx5_core_cq *mcq = &cq->mcq;
1540         int err;
1541         u32 i;
1542
1543         err = mlx5_cqwq_create(mdev, &param->wq, param->cqc, &cq->wq,
1544                                &cq->wq_ctrl);
1545         if (err)
1546                 return err;
1547
1548         mcq->cqe_sz     = 64;
1549         mcq->set_ci_db  = cq->wq_ctrl.db.db;
1550         mcq->arm_db     = cq->wq_ctrl.db.db + 1;
1551         *mcq->set_ci_db = 0;
1552         *mcq->arm_db    = 0;
1553         mcq->vector     = param->eq_ix;
1554         mcq->comp       = mlx5e_completion_event;
1555         mcq->event      = mlx5e_cq_error_event;
1556
1557         for (i = 0; i < mlx5_cqwq_get_size(&cq->wq); i++) {
1558                 struct mlx5_cqe64 *cqe = mlx5_cqwq_get_wqe(&cq->wq, i);
1559
1560                 cqe->op_own = 0xf1;
1561         }
1562
1563         cq->mdev = mdev;
1564         cq->netdev = priv->netdev;
1565         cq->priv = priv;
1566
1567         return 0;
1568 }
1569
1570 static int mlx5e_alloc_cq(struct mlx5e_priv *priv,
1571                           struct mlx5e_cq_param *param,
1572                           struct mlx5e_create_cq_param *ccp,
1573                           struct mlx5e_cq *cq)
1574 {
1575         int err;
1576
1577         param->wq.buf_numa_node = ccp->node;
1578         param->wq.db_numa_node  = ccp->node;
1579         param->eq_ix            = ccp->ix;
1580
1581         err = mlx5e_alloc_cq_common(priv, param, cq);
1582
1583         cq->napi     = ccp->napi;
1584         cq->ch_stats = ccp->ch_stats;
1585
1586         return err;
1587 }
1588
1589 static void mlx5e_free_cq(struct mlx5e_cq *cq)
1590 {
1591         mlx5_wq_destroy(&cq->wq_ctrl);
1592 }
1593
1594 static int mlx5e_create_cq(struct mlx5e_cq *cq, struct mlx5e_cq_param *param)
1595 {
1596         u32 out[MLX5_ST_SZ_DW(create_cq_out)];
1597         struct mlx5_core_dev *mdev = cq->mdev;
1598         struct mlx5_core_cq *mcq = &cq->mcq;
1599
1600         void *in;
1601         void *cqc;
1602         int inlen;
1603         int eqn;
1604         int err;
1605
1606         err = mlx5_vector2eqn(mdev, param->eq_ix, &eqn);
1607         if (err)
1608                 return err;
1609
1610         inlen = MLX5_ST_SZ_BYTES(create_cq_in) +
1611                 sizeof(u64) * cq->wq_ctrl.buf.npages;
1612         in = kvzalloc(inlen, GFP_KERNEL);
1613         if (!in)
1614                 return -ENOMEM;
1615
1616         cqc = MLX5_ADDR_OF(create_cq_in, in, cq_context);
1617
1618         memcpy(cqc, param->cqc, sizeof(param->cqc));
1619
1620         mlx5_fill_page_frag_array(&cq->wq_ctrl.buf,
1621                                   (__be64 *)MLX5_ADDR_OF(create_cq_in, in, pas));
1622
1623         MLX5_SET(cqc,   cqc, cq_period_mode, param->cq_period_mode);
1624         MLX5_SET(cqc,   cqc, c_eqn_or_apu_element, eqn);
1625         MLX5_SET(cqc,   cqc, uar_page,      mdev->priv.uar->index);
1626         MLX5_SET(cqc,   cqc, log_page_size, cq->wq_ctrl.buf.page_shift -
1627                                             MLX5_ADAPTER_PAGE_SHIFT);
1628         MLX5_SET64(cqc, cqc, dbr_addr,      cq->wq_ctrl.db.dma);
1629
1630         err = mlx5_core_create_cq(mdev, mcq, in, inlen, out, sizeof(out));
1631
1632         kvfree(in);
1633
1634         if (err)
1635                 return err;
1636
1637         mlx5e_cq_arm(cq);
1638
1639         return 0;
1640 }
1641
1642 static void mlx5e_destroy_cq(struct mlx5e_cq *cq)
1643 {
1644         mlx5_core_destroy_cq(cq->mdev, &cq->mcq);
1645 }
1646
1647 int mlx5e_open_cq(struct mlx5e_priv *priv, struct dim_cq_moder moder,
1648                   struct mlx5e_cq_param *param, struct mlx5e_create_cq_param *ccp,
1649                   struct mlx5e_cq *cq)
1650 {
1651         struct mlx5_core_dev *mdev = priv->mdev;
1652         int err;
1653
1654         err = mlx5e_alloc_cq(priv, param, ccp, cq);
1655         if (err)
1656                 return err;
1657
1658         err = mlx5e_create_cq(cq, param);
1659         if (err)
1660                 goto err_free_cq;
1661
1662         if (MLX5_CAP_GEN(mdev, cq_moderation))
1663                 mlx5_core_modify_cq_moderation(mdev, &cq->mcq, moder.usec, moder.pkts);
1664         return 0;
1665
1666 err_free_cq:
1667         mlx5e_free_cq(cq);
1668
1669         return err;
1670 }
1671
1672 void mlx5e_close_cq(struct mlx5e_cq *cq)
1673 {
1674         mlx5e_destroy_cq(cq);
1675         mlx5e_free_cq(cq);
1676 }
1677
1678 static int mlx5e_open_tx_cqs(struct mlx5e_channel *c,
1679                              struct mlx5e_params *params,
1680                              struct mlx5e_create_cq_param *ccp,
1681                              struct mlx5e_channel_param *cparam)
1682 {
1683         int err;
1684         int tc;
1685
1686         for (tc = 0; tc < c->num_tc; tc++) {
1687                 err = mlx5e_open_cq(c->priv, params->tx_cq_moderation, &cparam->txq_sq.cqp,
1688                                     ccp, &c->sq[tc].cq);
1689                 if (err)
1690                         goto err_close_tx_cqs;
1691         }
1692
1693         return 0;
1694
1695 err_close_tx_cqs:
1696         for (tc--; tc >= 0; tc--)
1697                 mlx5e_close_cq(&c->sq[tc].cq);
1698
1699         return err;
1700 }
1701
1702 static void mlx5e_close_tx_cqs(struct mlx5e_channel *c)
1703 {
1704         int tc;
1705
1706         for (tc = 0; tc < c->num_tc; tc++)
1707                 mlx5e_close_cq(&c->sq[tc].cq);
1708 }
1709
1710 static int mlx5e_open_sqs(struct mlx5e_channel *c,
1711                           struct mlx5e_params *params,
1712                           struct mlx5e_channel_param *cparam)
1713 {
1714         int err, tc;
1715
1716         for (tc = 0; tc < mlx5e_get_dcb_num_tc(params); tc++) {
1717                 int txq_ix = c->ix + tc * params->num_channels;
1718
1719                 err = mlx5e_open_txqsq(c, c->priv->tisn[c->lag_port][tc], txq_ix,
1720                                        params, &cparam->txq_sq, &c->sq[tc], tc, 0, 0);
1721                 if (err)
1722                         goto err_close_sqs;
1723         }
1724
1725         return 0;
1726
1727 err_close_sqs:
1728         for (tc--; tc >= 0; tc--)
1729                 mlx5e_close_txqsq(&c->sq[tc]);
1730
1731         return err;
1732 }
1733
1734 static void mlx5e_close_sqs(struct mlx5e_channel *c)
1735 {
1736         int tc;
1737
1738         for (tc = 0; tc < c->num_tc; tc++)
1739                 mlx5e_close_txqsq(&c->sq[tc]);
1740 }
1741
1742 static int mlx5e_set_sq_maxrate(struct net_device *dev,
1743                                 struct mlx5e_txqsq *sq, u32 rate)
1744 {
1745         struct mlx5e_priv *priv = netdev_priv(dev);
1746         struct mlx5_core_dev *mdev = priv->mdev;
1747         struct mlx5e_modify_sq_param msp = {0};
1748         struct mlx5_rate_limit rl = {0};
1749         u16 rl_index = 0;
1750         int err;
1751
1752         if (rate == sq->rate_limit)
1753                 /* nothing to do */
1754                 return 0;
1755
1756         if (sq->rate_limit) {
1757                 rl.rate = sq->rate_limit;
1758                 /* remove current rl index to free space to next ones */
1759                 mlx5_rl_remove_rate(mdev, &rl);
1760         }
1761
1762         sq->rate_limit = 0;
1763
1764         if (rate) {
1765                 rl.rate = rate;
1766                 err = mlx5_rl_add_rate(mdev, &rl_index, &rl);
1767                 if (err) {
1768                         netdev_err(dev, "Failed configuring rate %u: %d\n",
1769                                    rate, err);
1770                         return err;
1771                 }
1772         }
1773
1774         msp.curr_state = MLX5_SQC_STATE_RDY;
1775         msp.next_state = MLX5_SQC_STATE_RDY;
1776         msp.rl_index   = rl_index;
1777         msp.rl_update  = true;
1778         err = mlx5e_modify_sq(mdev, sq->sqn, &msp);
1779         if (err) {
1780                 netdev_err(dev, "Failed configuring rate %u: %d\n",
1781                            rate, err);
1782                 /* remove the rate from the table */
1783                 if (rate)
1784                         mlx5_rl_remove_rate(mdev, &rl);
1785                 return err;
1786         }
1787
1788         sq->rate_limit = rate;
1789         return 0;
1790 }
1791
1792 static int mlx5e_set_tx_maxrate(struct net_device *dev, int index, u32 rate)
1793 {
1794         struct mlx5e_priv *priv = netdev_priv(dev);
1795         struct mlx5_core_dev *mdev = priv->mdev;
1796         struct mlx5e_txqsq *sq = priv->txq2sq[index];
1797         int err = 0;
1798
1799         if (!mlx5_rl_is_supported(mdev)) {
1800                 netdev_err(dev, "Rate limiting is not supported on this device\n");
1801                 return -EINVAL;
1802         }
1803
1804         /* rate is given in Mb/sec, HW config is in Kb/sec */
1805         rate = rate << 10;
1806
1807         /* Check whether rate in valid range, 0 is always valid */
1808         if (rate && !mlx5_rl_is_in_range(mdev, rate)) {
1809                 netdev_err(dev, "TX rate %u, is not in range\n", rate);
1810                 return -ERANGE;
1811         }
1812
1813         mutex_lock(&priv->state_lock);
1814         if (test_bit(MLX5E_STATE_OPENED, &priv->state))
1815                 err = mlx5e_set_sq_maxrate(dev, sq, rate);
1816         if (!err)
1817                 priv->tx_rates[index] = rate;
1818         mutex_unlock(&priv->state_lock);
1819
1820         return err;
1821 }
1822
1823 static int mlx5e_open_rxq_rq(struct mlx5e_channel *c, struct mlx5e_params *params,
1824                              struct mlx5e_rq_param *rq_params)
1825 {
1826         int err;
1827
1828         err = mlx5e_init_rxq_rq(c, params, &c->rq);
1829         if (err)
1830                 return err;
1831
1832         return mlx5e_open_rq(params, rq_params, NULL, cpu_to_node(c->cpu), &c->rq);
1833 }
1834
1835 static int mlx5e_open_queues(struct mlx5e_channel *c,
1836                              struct mlx5e_params *params,
1837                              struct mlx5e_channel_param *cparam)
1838 {
1839         struct dim_cq_moder icocq_moder = {0, 0};
1840         struct mlx5e_create_cq_param ccp;
1841         int err;
1842
1843         mlx5e_build_create_cq_param(&ccp, c);
1844
1845         err = mlx5e_open_cq(c->priv, icocq_moder, &cparam->async_icosq.cqp, &ccp,
1846                             &c->async_icosq.cq);
1847         if (err)
1848                 return err;
1849
1850         err = mlx5e_open_cq(c->priv, icocq_moder, &cparam->icosq.cqp, &ccp,
1851                             &c->icosq.cq);
1852         if (err)
1853                 goto err_close_async_icosq_cq;
1854
1855         err = mlx5e_open_tx_cqs(c, params, &ccp, cparam);
1856         if (err)
1857                 goto err_close_icosq_cq;
1858
1859         err = mlx5e_open_cq(c->priv, params->tx_cq_moderation, &cparam->xdp_sq.cqp, &ccp,
1860                             &c->xdpsq.cq);
1861         if (err)
1862                 goto err_close_tx_cqs;
1863
1864         err = mlx5e_open_cq(c->priv, params->rx_cq_moderation, &cparam->rq.cqp, &ccp,
1865                             &c->rq.cq);
1866         if (err)
1867                 goto err_close_xdp_tx_cqs;
1868
1869         err = c->xdp ? mlx5e_open_cq(c->priv, params->tx_cq_moderation, &cparam->xdp_sq.cqp,
1870                                      &ccp, &c->rq_xdpsq.cq) : 0;
1871         if (err)
1872                 goto err_close_rx_cq;
1873
1874         spin_lock_init(&c->async_icosq_lock);
1875
1876         err = mlx5e_open_icosq(c, params, &cparam->async_icosq, &c->async_icosq);
1877         if (err)
1878                 goto err_close_xdpsq_cq;
1879
1880         err = mlx5e_open_icosq(c, params, &cparam->icosq, &c->icosq);
1881         if (err)
1882                 goto err_close_async_icosq;
1883
1884         err = mlx5e_open_sqs(c, params, cparam);
1885         if (err)
1886                 goto err_close_icosq;
1887
1888         err = mlx5e_open_rxq_rq(c, params, &cparam->rq);
1889         if (err)
1890                 goto err_close_sqs;
1891
1892         if (c->xdp) {
1893                 err = mlx5e_open_xdpsq(c, params, &cparam->xdp_sq, NULL,
1894                                        &c->rq_xdpsq, false);
1895                 if (err)
1896                         goto err_close_rq;
1897         }
1898
1899         err = mlx5e_open_xdpsq(c, params, &cparam->xdp_sq, NULL, &c->xdpsq, true);
1900         if (err)
1901                 goto err_close_xdp_sq;
1902
1903         return 0;
1904
1905 err_close_xdp_sq:
1906         if (c->xdp)
1907                 mlx5e_close_xdpsq(&c->rq_xdpsq);
1908
1909 err_close_rq:
1910         mlx5e_close_rq(&c->rq);
1911
1912 err_close_sqs:
1913         mlx5e_close_sqs(c);
1914
1915 err_close_icosq:
1916         mlx5e_close_icosq(&c->icosq);
1917
1918 err_close_async_icosq:
1919         mlx5e_close_icosq(&c->async_icosq);
1920
1921 err_close_xdpsq_cq:
1922         if (c->xdp)
1923                 mlx5e_close_cq(&c->rq_xdpsq.cq);
1924
1925 err_close_rx_cq:
1926         mlx5e_close_cq(&c->rq.cq);
1927
1928 err_close_xdp_tx_cqs:
1929         mlx5e_close_cq(&c->xdpsq.cq);
1930
1931 err_close_tx_cqs:
1932         mlx5e_close_tx_cqs(c);
1933
1934 err_close_icosq_cq:
1935         mlx5e_close_cq(&c->icosq.cq);
1936
1937 err_close_async_icosq_cq:
1938         mlx5e_close_cq(&c->async_icosq.cq);
1939
1940         return err;
1941 }
1942
1943 static void mlx5e_close_queues(struct mlx5e_channel *c)
1944 {
1945         mlx5e_close_xdpsq(&c->xdpsq);
1946         if (c->xdp)
1947                 mlx5e_close_xdpsq(&c->rq_xdpsq);
1948         mlx5e_close_rq(&c->rq);
1949         mlx5e_close_sqs(c);
1950         mlx5e_close_icosq(&c->icosq);
1951         mlx5e_close_icosq(&c->async_icosq);
1952         if (c->xdp)
1953                 mlx5e_close_cq(&c->rq_xdpsq.cq);
1954         mlx5e_close_cq(&c->rq.cq);
1955         mlx5e_close_cq(&c->xdpsq.cq);
1956         mlx5e_close_tx_cqs(c);
1957         mlx5e_close_cq(&c->icosq.cq);
1958         mlx5e_close_cq(&c->async_icosq.cq);
1959 }
1960
1961 static u8 mlx5e_enumerate_lag_port(struct mlx5_core_dev *mdev, int ix)
1962 {
1963         u16 port_aff_bias = mlx5_core_is_pf(mdev) ? 0 : MLX5_CAP_GEN(mdev, vhca_id);
1964
1965         return (ix + port_aff_bias) % mlx5e_get_num_lag_ports(mdev);
1966 }
1967
1968 static int mlx5e_open_channel(struct mlx5e_priv *priv, int ix,
1969                               struct mlx5e_params *params,
1970                               struct mlx5e_channel_param *cparam,
1971                               struct xsk_buff_pool *xsk_pool,
1972                               struct mlx5e_channel **cp)
1973 {
1974         int cpu = cpumask_first(mlx5_comp_irq_get_affinity_mask(priv->mdev, ix));
1975         struct net_device *netdev = priv->netdev;
1976         struct mlx5e_xsk_param xsk;
1977         struct mlx5e_channel *c;
1978         unsigned int irq;
1979         int err;
1980
1981         err = mlx5_vector2irqn(priv->mdev, ix, &irq);
1982         if (err)
1983                 return err;
1984
1985         c = kvzalloc_node(sizeof(*c), GFP_KERNEL, cpu_to_node(cpu));
1986         if (!c)
1987                 return -ENOMEM;
1988
1989         c->priv     = priv;
1990         c->mdev     = priv->mdev;
1991         c->tstamp   = &priv->tstamp;
1992         c->ix       = ix;
1993         c->cpu      = cpu;
1994         c->pdev     = mlx5_core_dma_dev(priv->mdev);
1995         c->netdev   = priv->netdev;
1996         c->mkey_be  = cpu_to_be32(priv->mdev->mlx5e_res.hw_objs.mkey.key);
1997         c->num_tc   = mlx5e_get_dcb_num_tc(params);
1998         c->xdp      = !!params->xdp_prog;
1999         c->stats    = &priv->channel_stats[ix].ch;
2000         c->aff_mask = irq_get_effective_affinity_mask(irq);
2001         c->lag_port = mlx5e_enumerate_lag_port(priv->mdev, ix);
2002
2003         netif_napi_add(netdev, &c->napi, mlx5e_napi_poll, 64);
2004
2005         err = mlx5e_open_queues(c, params, cparam);
2006         if (unlikely(err))
2007                 goto err_napi_del;
2008
2009         if (xsk_pool) {
2010                 mlx5e_build_xsk_param(xsk_pool, &xsk);
2011                 err = mlx5e_open_xsk(priv, params, &xsk, xsk_pool, c);
2012                 if (unlikely(err))
2013                         goto err_close_queues;
2014         }
2015
2016         *cp = c;
2017
2018         return 0;
2019
2020 err_close_queues:
2021         mlx5e_close_queues(c);
2022
2023 err_napi_del:
2024         netif_napi_del(&c->napi);
2025
2026         kvfree(c);
2027
2028         return err;
2029 }
2030
2031 static void mlx5e_activate_channel(struct mlx5e_channel *c)
2032 {
2033         int tc;
2034
2035         napi_enable(&c->napi);
2036
2037         for (tc = 0; tc < c->num_tc; tc++)
2038                 mlx5e_activate_txqsq(&c->sq[tc]);
2039         mlx5e_activate_icosq(&c->icosq);
2040         mlx5e_activate_icosq(&c->async_icosq);
2041         mlx5e_activate_rq(&c->rq);
2042
2043         if (test_bit(MLX5E_CHANNEL_STATE_XSK, c->state))
2044                 mlx5e_activate_xsk(c);
2045 }
2046
2047 static void mlx5e_deactivate_channel(struct mlx5e_channel *c)
2048 {
2049         int tc;
2050
2051         if (test_bit(MLX5E_CHANNEL_STATE_XSK, c->state))
2052                 mlx5e_deactivate_xsk(c);
2053
2054         mlx5e_deactivate_rq(&c->rq);
2055         mlx5e_deactivate_icosq(&c->async_icosq);
2056         mlx5e_deactivate_icosq(&c->icosq);
2057         for (tc = 0; tc < c->num_tc; tc++)
2058                 mlx5e_deactivate_txqsq(&c->sq[tc]);
2059         mlx5e_qos_deactivate_queues(c);
2060
2061         napi_disable(&c->napi);
2062 }
2063
2064 static void mlx5e_close_channel(struct mlx5e_channel *c)
2065 {
2066         if (test_bit(MLX5E_CHANNEL_STATE_XSK, c->state))
2067                 mlx5e_close_xsk(c);
2068         mlx5e_close_queues(c);
2069         mlx5e_qos_close_queues(c);
2070         netif_napi_del(&c->napi);
2071
2072         kvfree(c);
2073 }
2074
2075 int mlx5e_open_channels(struct mlx5e_priv *priv,
2076                         struct mlx5e_channels *chs)
2077 {
2078         struct mlx5e_channel_param *cparam;
2079         int err = -ENOMEM;
2080         int i;
2081
2082         chs->num = chs->params.num_channels;
2083
2084         chs->c = kcalloc(chs->num, sizeof(struct mlx5e_channel *), GFP_KERNEL);
2085         cparam = kvzalloc(sizeof(struct mlx5e_channel_param), GFP_KERNEL);
2086         if (!chs->c || !cparam)
2087                 goto err_free;
2088
2089         err = mlx5e_build_channel_param(priv->mdev, &chs->params, priv->q_counter, cparam);
2090         if (err)
2091                 goto err_free;
2092
2093         for (i = 0; i < chs->num; i++) {
2094                 struct xsk_buff_pool *xsk_pool = NULL;
2095
2096                 if (chs->params.xdp_prog)
2097                         xsk_pool = mlx5e_xsk_get_pool(&chs->params, chs->params.xsk, i);
2098
2099                 err = mlx5e_open_channel(priv, i, &chs->params, cparam, xsk_pool, &chs->c[i]);
2100                 if (err)
2101                         goto err_close_channels;
2102         }
2103
2104         if (MLX5E_GET_PFLAG(&chs->params, MLX5E_PFLAG_TX_PORT_TS) || chs->params.ptp_rx) {
2105                 err = mlx5e_ptp_open(priv, &chs->params, chs->c[0]->lag_port, &chs->ptp);
2106                 if (err)
2107                         goto err_close_channels;
2108         }
2109
2110         err = mlx5e_qos_open_queues(priv, chs);
2111         if (err)
2112                 goto err_close_ptp;
2113
2114         mlx5e_health_channels_update(priv);
2115         kvfree(cparam);
2116         return 0;
2117
2118 err_close_ptp:
2119         if (chs->ptp)
2120                 mlx5e_ptp_close(chs->ptp);
2121
2122 err_close_channels:
2123         for (i--; i >= 0; i--)
2124                 mlx5e_close_channel(chs->c[i]);
2125
2126 err_free:
2127         kfree(chs->c);
2128         kvfree(cparam);
2129         chs->num = 0;
2130         return err;
2131 }
2132
2133 static void mlx5e_activate_channels(struct mlx5e_channels *chs)
2134 {
2135         int i;
2136
2137         for (i = 0; i < chs->num; i++)
2138                 mlx5e_activate_channel(chs->c[i]);
2139
2140         if (chs->ptp)
2141                 mlx5e_ptp_activate_channel(chs->ptp);
2142 }
2143
2144 #define MLX5E_RQ_WQES_TIMEOUT 20000 /* msecs */
2145
2146 static int mlx5e_wait_channels_min_rx_wqes(struct mlx5e_channels *chs)
2147 {
2148         int err = 0;
2149         int i;
2150
2151         for (i = 0; i < chs->num; i++) {
2152                 int timeout = err ? 0 : MLX5E_RQ_WQES_TIMEOUT;
2153
2154                 err |= mlx5e_wait_for_min_rx_wqes(&chs->c[i]->rq, timeout);
2155
2156                 /* Don't wait on the XSK RQ, because the newer xdpsock sample
2157                  * doesn't provide any Fill Ring entries at the setup stage.
2158                  */
2159         }
2160
2161         return err ? -ETIMEDOUT : 0;
2162 }
2163
2164 static void mlx5e_deactivate_channels(struct mlx5e_channels *chs)
2165 {
2166         int i;
2167
2168         if (chs->ptp)
2169                 mlx5e_ptp_deactivate_channel(chs->ptp);
2170
2171         for (i = 0; i < chs->num; i++)
2172                 mlx5e_deactivate_channel(chs->c[i]);
2173 }
2174
2175 void mlx5e_close_channels(struct mlx5e_channels *chs)
2176 {
2177         int i;
2178
2179         if (chs->ptp) {
2180                 mlx5e_ptp_close(chs->ptp);
2181                 chs->ptp = NULL;
2182         }
2183         for (i = 0; i < chs->num; i++)
2184                 mlx5e_close_channel(chs->c[i]);
2185
2186         kfree(chs->c);
2187         chs->num = 0;
2188 }
2189
2190 static int mlx5e_modify_tirs_lro(struct mlx5e_priv *priv)
2191 {
2192         struct mlx5e_rx_res *res = priv->rx_res;
2193         struct mlx5e_lro_param lro_param;
2194
2195         lro_param = mlx5e_get_lro_param(&priv->channels.params);
2196
2197         return mlx5e_rx_res_lro_set_param(res, &lro_param);
2198 }
2199
2200 static MLX5E_DEFINE_PREACTIVATE_WRAPPER_CTX(mlx5e_modify_tirs_lro);
2201
2202 static int mlx5e_set_mtu(struct mlx5_core_dev *mdev,
2203                          struct mlx5e_params *params, u16 mtu)
2204 {
2205         u16 hw_mtu = MLX5E_SW2HW_MTU(params, mtu);
2206         int err;
2207
2208         err = mlx5_set_port_mtu(mdev, hw_mtu, 1);
2209         if (err)
2210                 return err;
2211
2212         /* Update vport context MTU */
2213         mlx5_modify_nic_vport_mtu(mdev, hw_mtu);
2214         return 0;
2215 }
2216
2217 static void mlx5e_query_mtu(struct mlx5_core_dev *mdev,
2218                             struct mlx5e_params *params, u16 *mtu)
2219 {
2220         u16 hw_mtu = 0;
2221         int err;
2222
2223         err = mlx5_query_nic_vport_mtu(mdev, &hw_mtu);
2224         if (err || !hw_mtu) /* fallback to port oper mtu */
2225                 mlx5_query_port_oper_mtu(mdev, &hw_mtu, 1);
2226
2227         *mtu = MLX5E_HW2SW_MTU(params, hw_mtu);
2228 }
2229
2230 int mlx5e_set_dev_port_mtu(struct mlx5e_priv *priv)
2231 {
2232         struct mlx5e_params *params = &priv->channels.params;
2233         struct net_device *netdev = priv->netdev;
2234         struct mlx5_core_dev *mdev = priv->mdev;
2235         u16 mtu;
2236         int err;
2237
2238         err = mlx5e_set_mtu(mdev, params, params->sw_mtu);
2239         if (err)
2240                 return err;
2241
2242         mlx5e_query_mtu(mdev, params, &mtu);
2243         if (mtu != params->sw_mtu)
2244                 netdev_warn(netdev, "%s: VPort MTU %d is different than netdev mtu %d\n",
2245                             __func__, mtu, params->sw_mtu);
2246
2247         params->sw_mtu = mtu;
2248         return 0;
2249 }
2250
2251 MLX5E_DEFINE_PREACTIVATE_WRAPPER_CTX(mlx5e_set_dev_port_mtu);
2252
2253 void mlx5e_set_netdev_mtu_boundaries(struct mlx5e_priv *priv)
2254 {
2255         struct mlx5e_params *params = &priv->channels.params;
2256         struct net_device *netdev   = priv->netdev;
2257         struct mlx5_core_dev *mdev  = priv->mdev;
2258         u16 max_mtu;
2259
2260         /* MTU range: 68 - hw-specific max */
2261         netdev->min_mtu = ETH_MIN_MTU;
2262
2263         mlx5_query_port_max_mtu(mdev, &max_mtu, 1);
2264         netdev->max_mtu = min_t(unsigned int, MLX5E_HW2SW_MTU(params, max_mtu),
2265                                 ETH_MAX_MTU);
2266 }
2267
2268 static int mlx5e_netdev_set_tcs(struct net_device *netdev, u16 nch, u8 ntc,
2269                                 struct netdev_tc_txq *tc_to_txq)
2270 {
2271         int tc, err;
2272
2273         netdev_reset_tc(netdev);
2274
2275         if (ntc == 1)
2276                 return 0;
2277
2278         err = netdev_set_num_tc(netdev, ntc);
2279         if (err) {
2280                 netdev_WARN(netdev, "netdev_set_num_tc failed (%d), ntc = %d\n", err, ntc);
2281                 return err;
2282         }
2283
2284         for (tc = 0; tc < ntc; tc++) {
2285                 u16 count, offset;
2286
2287                 count = tc_to_txq[tc].count;
2288                 offset = tc_to_txq[tc].offset;
2289                 netdev_set_tc_queue(netdev, tc, count, offset);
2290         }
2291
2292         return 0;
2293 }
2294
2295 int mlx5e_update_tx_netdev_queues(struct mlx5e_priv *priv)
2296 {
2297         int qos_queues, nch, ntc, num_txqs, err;
2298
2299         qos_queues = mlx5e_qos_cur_leaf_nodes(priv);
2300
2301         nch = priv->channels.params.num_channels;
2302         ntc = mlx5e_get_dcb_num_tc(&priv->channels.params);
2303         num_txqs = nch * ntc + qos_queues;
2304         if (MLX5E_GET_PFLAG(&priv->channels.params, MLX5E_PFLAG_TX_PORT_TS))
2305                 num_txqs += ntc;
2306
2307         mlx5e_dbg(DRV, priv, "Setting num_txqs %d\n", num_txqs);
2308         err = netif_set_real_num_tx_queues(priv->netdev, num_txqs);
2309         if (err)
2310                 netdev_warn(priv->netdev, "netif_set_real_num_tx_queues failed, %d\n", err);
2311
2312         return err;
2313 }
2314
2315 static int mlx5e_update_netdev_queues(struct mlx5e_priv *priv)
2316 {
2317         struct netdev_tc_txq old_tc_to_txq[TC_MAX_QUEUE], *tc_to_txq;
2318         struct net_device *netdev = priv->netdev;
2319         int old_num_txqs, old_ntc;
2320         int num_rxqs, nch, ntc;
2321         int err;
2322         int i;
2323
2324         old_num_txqs = netdev->real_num_tx_queues;
2325         old_ntc = netdev->num_tc ? : 1;
2326         for (i = 0; i < ARRAY_SIZE(old_tc_to_txq); i++)
2327                 old_tc_to_txq[i] = netdev->tc_to_txq[i];
2328
2329         nch = priv->channels.params.num_channels;
2330         ntc = priv->channels.params.mqprio.num_tc;
2331         num_rxqs = nch * priv->profile->rq_groups;
2332         tc_to_txq = priv->channels.params.mqprio.tc_to_txq;
2333
2334         err = mlx5e_netdev_set_tcs(netdev, nch, ntc, tc_to_txq);
2335         if (err)
2336                 goto err_out;
2337         err = mlx5e_update_tx_netdev_queues(priv);
2338         if (err)
2339                 goto err_tcs;
2340         err = netif_set_real_num_rx_queues(netdev, num_rxqs);
2341         if (err) {
2342                 netdev_warn(netdev, "netif_set_real_num_rx_queues failed, %d\n", err);
2343                 goto err_txqs;
2344         }
2345
2346         return 0;
2347
2348 err_txqs:
2349         /* netif_set_real_num_rx_queues could fail only when nch increased. Only
2350          * one of nch and ntc is changed in this function. That means, the call
2351          * to netif_set_real_num_tx_queues below should not fail, because it
2352          * decreases the number of TX queues.
2353          */
2354         WARN_ON_ONCE(netif_set_real_num_tx_queues(netdev, old_num_txqs));
2355
2356 err_tcs:
2357         WARN_ON_ONCE(mlx5e_netdev_set_tcs(netdev, old_num_txqs / old_ntc, old_ntc,
2358                                           old_tc_to_txq));
2359 err_out:
2360         return err;
2361 }
2362
2363 static MLX5E_DEFINE_PREACTIVATE_WRAPPER_CTX(mlx5e_update_netdev_queues);
2364
2365 static void mlx5e_set_default_xps_cpumasks(struct mlx5e_priv *priv,
2366                                            struct mlx5e_params *params)
2367 {
2368         struct mlx5_core_dev *mdev = priv->mdev;
2369         int num_comp_vectors, ix, irq;
2370
2371         num_comp_vectors = mlx5_comp_vectors_count(mdev);
2372
2373         for (ix = 0; ix < params->num_channels; ix++) {
2374                 cpumask_clear(priv->scratchpad.cpumask);
2375
2376                 for (irq = ix; irq < num_comp_vectors; irq += params->num_channels) {
2377                         int cpu = cpumask_first(mlx5_comp_irq_get_affinity_mask(mdev, irq));
2378
2379                         cpumask_set_cpu(cpu, priv->scratchpad.cpumask);
2380                 }
2381
2382                 netif_set_xps_queue(priv->netdev, priv->scratchpad.cpumask, ix);
2383         }
2384 }
2385
2386 int mlx5e_num_channels_changed(struct mlx5e_priv *priv)
2387 {
2388         u16 count = priv->channels.params.num_channels;
2389         int err;
2390
2391         err = mlx5e_update_netdev_queues(priv);
2392         if (err)
2393                 return err;
2394
2395         mlx5e_set_default_xps_cpumasks(priv, &priv->channels.params);
2396
2397         /* This function may be called on attach, before priv->rx_res is created. */
2398         if (!netif_is_rxfh_configured(priv->netdev) && priv->rx_res)
2399                 mlx5e_rx_res_rss_set_indir_uniform(priv->rx_res, count);
2400
2401         return 0;
2402 }
2403
2404 MLX5E_DEFINE_PREACTIVATE_WRAPPER_CTX(mlx5e_num_channels_changed);
2405
2406 static void mlx5e_build_txq_maps(struct mlx5e_priv *priv)
2407 {
2408         int i, ch, tc, num_tc;
2409
2410         ch = priv->channels.num;
2411         num_tc = mlx5e_get_dcb_num_tc(&priv->channels.params);
2412
2413         for (i = 0; i < ch; i++) {
2414                 for (tc = 0; tc < num_tc; tc++) {
2415                         struct mlx5e_channel *c = priv->channels.c[i];
2416                         struct mlx5e_txqsq *sq = &c->sq[tc];
2417
2418                         priv->txq2sq[sq->txq_ix] = sq;
2419                         priv->channel_tc2realtxq[i][tc] = i + tc * ch;
2420                 }
2421         }
2422
2423         if (!priv->channels.ptp)
2424                 return;
2425
2426         if (!test_bit(MLX5E_PTP_STATE_TX, priv->channels.ptp->state))
2427                 return;
2428
2429         for (tc = 0; tc < num_tc; tc++) {
2430                 struct mlx5e_ptp *c = priv->channels.ptp;
2431                 struct mlx5e_txqsq *sq = &c->ptpsq[tc].txqsq;
2432
2433                 priv->txq2sq[sq->txq_ix] = sq;
2434                 priv->port_ptp_tc2realtxq[tc] = priv->num_tc_x_num_ch + tc;
2435         }
2436 }
2437
2438 static void mlx5e_update_num_tc_x_num_ch(struct mlx5e_priv *priv)
2439 {
2440         /* Sync with mlx5e_select_queue. */
2441         WRITE_ONCE(priv->num_tc_x_num_ch,
2442                    mlx5e_get_dcb_num_tc(&priv->channels.params) * priv->channels.num);
2443 }
2444
2445 void mlx5e_activate_priv_channels(struct mlx5e_priv *priv)
2446 {
2447         mlx5e_update_num_tc_x_num_ch(priv);
2448         mlx5e_build_txq_maps(priv);
2449         mlx5e_activate_channels(&priv->channels);
2450         mlx5e_qos_activate_queues(priv);
2451         mlx5e_xdp_tx_enable(priv);
2452         netif_tx_start_all_queues(priv->netdev);
2453
2454         if (mlx5e_is_vport_rep(priv))
2455                 mlx5e_add_sqs_fwd_rules(priv);
2456
2457         mlx5e_wait_channels_min_rx_wqes(&priv->channels);
2458
2459         if (priv->rx_res)
2460                 mlx5e_rx_res_channels_activate(priv->rx_res, &priv->channels);
2461 }
2462
2463 void mlx5e_deactivate_priv_channels(struct mlx5e_priv *priv)
2464 {
2465         if (priv->rx_res)
2466                 mlx5e_rx_res_channels_deactivate(priv->rx_res);
2467
2468         if (mlx5e_is_vport_rep(priv))
2469                 mlx5e_remove_sqs_fwd_rules(priv);
2470
2471         /* FIXME: This is a W/A only for tx timeout watch dog false alarm when
2472          * polling for inactive tx queues.
2473          */
2474         netif_tx_stop_all_queues(priv->netdev);
2475         netif_tx_disable(priv->netdev);
2476         mlx5e_xdp_tx_disable(priv);
2477         mlx5e_deactivate_channels(&priv->channels);
2478 }
2479
2480 static int mlx5e_switch_priv_params(struct mlx5e_priv *priv,
2481                                     struct mlx5e_params *new_params,
2482                                     mlx5e_fp_preactivate preactivate,
2483                                     void *context)
2484 {
2485         struct mlx5e_params old_params;
2486
2487         old_params = priv->channels.params;
2488         priv->channels.params = *new_params;
2489
2490         if (preactivate) {
2491                 int err;
2492
2493                 err = preactivate(priv, context);
2494                 if (err) {
2495                         priv->channels.params = old_params;
2496                         return err;
2497                 }
2498         }
2499
2500         return 0;
2501 }
2502
2503 static int mlx5e_switch_priv_channels(struct mlx5e_priv *priv,
2504                                       struct mlx5e_channels *new_chs,
2505                                       mlx5e_fp_preactivate preactivate,
2506                                       void *context)
2507 {
2508         struct net_device *netdev = priv->netdev;
2509         struct mlx5e_channels old_chs;
2510         int carrier_ok;
2511         int err = 0;
2512
2513         carrier_ok = netif_carrier_ok(netdev);
2514         netif_carrier_off(netdev);
2515
2516         mlx5e_deactivate_priv_channels(priv);
2517
2518         old_chs = priv->channels;
2519         priv->channels = *new_chs;
2520
2521         /* New channels are ready to roll, call the preactivate hook if needed
2522          * to modify HW settings or update kernel parameters.
2523          */
2524         if (preactivate) {
2525                 err = preactivate(priv, context);
2526                 if (err) {
2527                         priv->channels = old_chs;
2528                         goto out;
2529                 }
2530         }
2531
2532         mlx5e_close_channels(&old_chs);
2533         priv->profile->update_rx(priv);
2534
2535 out:
2536         mlx5e_activate_priv_channels(priv);
2537
2538         /* return carrier back if needed */
2539         if (carrier_ok)
2540                 netif_carrier_on(netdev);
2541
2542         return err;
2543 }
2544
2545 int mlx5e_safe_switch_params(struct mlx5e_priv *priv,
2546                              struct mlx5e_params *params,
2547                              mlx5e_fp_preactivate preactivate,
2548                              void *context, bool reset)
2549 {
2550         struct mlx5e_channels new_chs = {};
2551         int err;
2552
2553         reset &= test_bit(MLX5E_STATE_OPENED, &priv->state);
2554         if (!reset)
2555                 return mlx5e_switch_priv_params(priv, params, preactivate, context);
2556
2557         new_chs.params = *params;
2558         err = mlx5e_open_channels(priv, &new_chs);
2559         if (err)
2560                 return err;
2561         err = mlx5e_switch_priv_channels(priv, &new_chs, preactivate, context);
2562         if (err)
2563                 mlx5e_close_channels(&new_chs);
2564
2565         return err;
2566 }
2567
2568 int mlx5e_safe_reopen_channels(struct mlx5e_priv *priv)
2569 {
2570         return mlx5e_safe_switch_params(priv, &priv->channels.params, NULL, NULL, true);
2571 }
2572
2573 void mlx5e_timestamp_init(struct mlx5e_priv *priv)
2574 {
2575         priv->tstamp.tx_type   = HWTSTAMP_TX_OFF;
2576         priv->tstamp.rx_filter = HWTSTAMP_FILTER_NONE;
2577 }
2578
2579 static void mlx5e_modify_admin_state(struct mlx5_core_dev *mdev,
2580                                      enum mlx5_port_status state)
2581 {
2582         struct mlx5_eswitch *esw = mdev->priv.eswitch;
2583         int vport_admin_state;
2584
2585         mlx5_set_port_admin_status(mdev, state);
2586
2587         if (mlx5_eswitch_mode(mdev) == MLX5_ESWITCH_OFFLOADS ||
2588             !MLX5_CAP_GEN(mdev, uplink_follow))
2589                 return;
2590
2591         if (state == MLX5_PORT_UP)
2592                 vport_admin_state = MLX5_VPORT_ADMIN_STATE_AUTO;
2593         else
2594                 vport_admin_state = MLX5_VPORT_ADMIN_STATE_DOWN;
2595
2596         mlx5_eswitch_set_vport_state(esw, MLX5_VPORT_UPLINK, vport_admin_state);
2597 }
2598
2599 int mlx5e_open_locked(struct net_device *netdev)
2600 {
2601         struct mlx5e_priv *priv = netdev_priv(netdev);
2602         int err;
2603
2604         set_bit(MLX5E_STATE_OPENED, &priv->state);
2605
2606         err = mlx5e_open_channels(priv, &priv->channels);
2607         if (err)
2608                 goto err_clear_state_opened_flag;
2609
2610         priv->profile->update_rx(priv);
2611         mlx5e_activate_priv_channels(priv);
2612         mlx5e_apply_traps(priv, true);
2613         if (priv->profile->update_carrier)
2614                 priv->profile->update_carrier(priv);
2615
2616         mlx5e_queue_update_stats(priv);
2617         return 0;
2618
2619 err_clear_state_opened_flag:
2620         clear_bit(MLX5E_STATE_OPENED, &priv->state);
2621         return err;
2622 }
2623
2624 int mlx5e_open(struct net_device *netdev)
2625 {
2626         struct mlx5e_priv *priv = netdev_priv(netdev);
2627         int err;
2628
2629         mutex_lock(&priv->state_lock);
2630         err = mlx5e_open_locked(netdev);
2631         if (!err)
2632                 mlx5e_modify_admin_state(priv->mdev, MLX5_PORT_UP);
2633         mutex_unlock(&priv->state_lock);
2634
2635         return err;
2636 }
2637
2638 int mlx5e_close_locked(struct net_device *netdev)
2639 {
2640         struct mlx5e_priv *priv = netdev_priv(netdev);
2641
2642         /* May already be CLOSED in case a previous configuration operation
2643          * (e.g RX/TX queue size change) that involves close&open failed.
2644          */
2645         if (!test_bit(MLX5E_STATE_OPENED, &priv->state))
2646                 return 0;
2647
2648         mlx5e_apply_traps(priv, false);
2649         clear_bit(MLX5E_STATE_OPENED, &priv->state);
2650
2651         netif_carrier_off(priv->netdev);
2652         mlx5e_deactivate_priv_channels(priv);
2653         mlx5e_close_channels(&priv->channels);
2654
2655         return 0;
2656 }
2657
2658 int mlx5e_close(struct net_device *netdev)
2659 {
2660         struct mlx5e_priv *priv = netdev_priv(netdev);
2661         int err;
2662
2663         if (!netif_device_present(netdev))
2664                 return -ENODEV;
2665
2666         mutex_lock(&priv->state_lock);
2667         mlx5e_modify_admin_state(priv->mdev, MLX5_PORT_DOWN);
2668         err = mlx5e_close_locked(netdev);
2669         mutex_unlock(&priv->state_lock);
2670
2671         return err;
2672 }
2673
2674 static void mlx5e_free_drop_rq(struct mlx5e_rq *rq)
2675 {
2676         mlx5_wq_destroy(&rq->wq_ctrl);
2677 }
2678
2679 static int mlx5e_alloc_drop_rq(struct mlx5_core_dev *mdev,
2680                                struct mlx5e_rq *rq,
2681                                struct mlx5e_rq_param *param)
2682 {
2683         void *rqc = param->rqc;
2684         void *rqc_wq = MLX5_ADDR_OF(rqc, rqc, wq);
2685         int err;
2686
2687         param->wq.db_numa_node = param->wq.buf_numa_node;
2688
2689         err = mlx5_wq_cyc_create(mdev, &param->wq, rqc_wq, &rq->wqe.wq,
2690                                  &rq->wq_ctrl);
2691         if (err)
2692                 return err;
2693
2694         /* Mark as unused given "Drop-RQ" packets never reach XDP */
2695         xdp_rxq_info_unused(&rq->xdp_rxq);
2696
2697         rq->mdev = mdev;
2698
2699         return 0;
2700 }
2701
2702 static int mlx5e_alloc_drop_cq(struct mlx5e_priv *priv,
2703                                struct mlx5e_cq *cq,
2704                                struct mlx5e_cq_param *param)
2705 {
2706         struct mlx5_core_dev *mdev = priv->mdev;
2707
2708         param->wq.buf_numa_node = dev_to_node(mlx5_core_dma_dev(mdev));
2709         param->wq.db_numa_node  = dev_to_node(mlx5_core_dma_dev(mdev));
2710
2711         return mlx5e_alloc_cq_common(priv, param, cq);
2712 }
2713
2714 int mlx5e_open_drop_rq(struct mlx5e_priv *priv,
2715                        struct mlx5e_rq *drop_rq)
2716 {
2717         struct mlx5_core_dev *mdev = priv->mdev;
2718         struct mlx5e_cq_param cq_param = {};
2719         struct mlx5e_rq_param rq_param = {};
2720         struct mlx5e_cq *cq = &drop_rq->cq;
2721         int err;
2722
2723         mlx5e_build_drop_rq_param(mdev, priv->drop_rq_q_counter, &rq_param);
2724
2725         err = mlx5e_alloc_drop_cq(priv, cq, &cq_param);
2726         if (err)
2727                 return err;
2728
2729         err = mlx5e_create_cq(cq, &cq_param);
2730         if (err)
2731                 goto err_free_cq;
2732
2733         err = mlx5e_alloc_drop_rq(mdev, drop_rq, &rq_param);
2734         if (err)
2735                 goto err_destroy_cq;
2736
2737         err = mlx5e_create_rq(drop_rq, &rq_param);
2738         if (err)
2739                 goto err_free_rq;
2740
2741         err = mlx5e_modify_rq_state(drop_rq, MLX5_RQC_STATE_RST, MLX5_RQC_STATE_RDY);
2742         if (err)
2743                 mlx5_core_warn(priv->mdev, "modify_rq_state failed, rx_if_down_packets won't be counted %d\n", err);
2744
2745         return 0;
2746
2747 err_free_rq:
2748         mlx5e_free_drop_rq(drop_rq);
2749
2750 err_destroy_cq:
2751         mlx5e_destroy_cq(cq);
2752
2753 err_free_cq:
2754         mlx5e_free_cq(cq);
2755
2756         return err;
2757 }
2758
2759 void mlx5e_close_drop_rq(struct mlx5e_rq *drop_rq)
2760 {
2761         mlx5e_destroy_rq(drop_rq);
2762         mlx5e_free_drop_rq(drop_rq);
2763         mlx5e_destroy_cq(&drop_rq->cq);
2764         mlx5e_free_cq(&drop_rq->cq);
2765 }
2766
2767 int mlx5e_create_tis(struct mlx5_core_dev *mdev, void *in, u32 *tisn)
2768 {
2769         void *tisc = MLX5_ADDR_OF(create_tis_in, in, ctx);
2770
2771         MLX5_SET(tisc, tisc, transport_domain, mdev->mlx5e_res.hw_objs.td.tdn);
2772
2773         if (MLX5_GET(tisc, tisc, tls_en))
2774                 MLX5_SET(tisc, tisc, pd, mdev->mlx5e_res.hw_objs.pdn);
2775
2776         if (mlx5_lag_is_lacp_owner(mdev))
2777                 MLX5_SET(tisc, tisc, strict_lag_tx_port_affinity, 1);
2778
2779         return mlx5_core_create_tis(mdev, in, tisn);
2780 }
2781
2782 void mlx5e_destroy_tis(struct mlx5_core_dev *mdev, u32 tisn)
2783 {
2784         mlx5_core_destroy_tis(mdev, tisn);
2785 }
2786
2787 void mlx5e_destroy_tises(struct mlx5e_priv *priv)
2788 {
2789         int tc, i;
2790
2791         for (i = 0; i < mlx5e_get_num_lag_ports(priv->mdev); i++)
2792                 for (tc = 0; tc < priv->profile->max_tc; tc++)
2793                         mlx5e_destroy_tis(priv->mdev, priv->tisn[i][tc]);
2794 }
2795
2796 static bool mlx5e_lag_should_assign_affinity(struct mlx5_core_dev *mdev)
2797 {
2798         return MLX5_CAP_GEN(mdev, lag_tx_port_affinity) && mlx5e_get_num_lag_ports(mdev) > 1;
2799 }
2800
2801 int mlx5e_create_tises(struct mlx5e_priv *priv)
2802 {
2803         int tc, i;
2804         int err;
2805
2806         for (i = 0; i < mlx5e_get_num_lag_ports(priv->mdev); i++) {
2807                 for (tc = 0; tc < priv->profile->max_tc; tc++) {
2808                         u32 in[MLX5_ST_SZ_DW(create_tis_in)] = {};
2809                         void *tisc;
2810
2811                         tisc = MLX5_ADDR_OF(create_tis_in, in, ctx);
2812
2813                         MLX5_SET(tisc, tisc, prio, tc << 1);
2814
2815                         if (mlx5e_lag_should_assign_affinity(priv->mdev))
2816                                 MLX5_SET(tisc, tisc, lag_tx_port_affinity, i + 1);
2817
2818                         err = mlx5e_create_tis(priv->mdev, in, &priv->tisn[i][tc]);
2819                         if (err)
2820                                 goto err_close_tises;
2821                 }
2822         }
2823
2824         return 0;
2825
2826 err_close_tises:
2827         for (; i >= 0; i--) {
2828                 for (tc--; tc >= 0; tc--)
2829                         mlx5e_destroy_tis(priv->mdev, priv->tisn[i][tc]);
2830                 tc = priv->profile->max_tc;
2831         }
2832
2833         return err;
2834 }
2835
2836 static void mlx5e_cleanup_nic_tx(struct mlx5e_priv *priv)
2837 {
2838         mlx5e_destroy_tises(priv);
2839 }
2840
2841 static int mlx5e_modify_channels_scatter_fcs(struct mlx5e_channels *chs, bool enable)
2842 {
2843         int err = 0;
2844         int i;
2845
2846         for (i = 0; i < chs->num; i++) {
2847                 err = mlx5e_modify_rq_scatter_fcs(&chs->c[i]->rq, enable);
2848                 if (err)
2849                         return err;
2850         }
2851
2852         return 0;
2853 }
2854
2855 static int mlx5e_modify_channels_vsd(struct mlx5e_channels *chs, bool vsd)
2856 {
2857         int err;
2858         int i;
2859
2860         for (i = 0; i < chs->num; i++) {
2861                 err = mlx5e_modify_rq_vsd(&chs->c[i]->rq, vsd);
2862                 if (err)
2863                         return err;
2864         }
2865         if (chs->ptp && test_bit(MLX5E_PTP_STATE_RX, chs->ptp->state))
2866                 return mlx5e_modify_rq_vsd(&chs->ptp->rq, vsd);
2867
2868         return 0;
2869 }
2870
2871 static void mlx5e_mqprio_build_default_tc_to_txq(struct netdev_tc_txq *tc_to_txq,
2872                                                  int ntc, int nch)
2873 {
2874         int tc;
2875
2876         memset(tc_to_txq, 0, sizeof(*tc_to_txq) * TC_MAX_QUEUE);
2877
2878         /* Map netdev TCs to offset 0.
2879          * We have our own UP to TXQ mapping for DCB mode of QoS
2880          */
2881         for (tc = 0; tc < ntc; tc++) {
2882                 tc_to_txq[tc] = (struct netdev_tc_txq) {
2883                         .count = nch,
2884                         .offset = 0,
2885                 };
2886         }
2887 }
2888
2889 static void mlx5e_mqprio_build_tc_to_txq(struct netdev_tc_txq *tc_to_txq,
2890                                          struct tc_mqprio_qopt *qopt)
2891 {
2892         int tc;
2893
2894         for (tc = 0; tc < TC_MAX_QUEUE; tc++) {
2895                 tc_to_txq[tc] = (struct netdev_tc_txq) {
2896                         .count = qopt->count[tc],
2897                         .offset = qopt->offset[tc],
2898                 };
2899         }
2900 }
2901
2902 static void mlx5e_params_mqprio_dcb_set(struct mlx5e_params *params, u8 num_tc)
2903 {
2904         params->mqprio.mode = TC_MQPRIO_MODE_DCB;
2905         params->mqprio.num_tc = num_tc;
2906         mlx5e_mqprio_build_default_tc_to_txq(params->mqprio.tc_to_txq, num_tc,
2907                                              params->num_channels);
2908 }
2909
2910 static void mlx5e_params_mqprio_channel_set(struct mlx5e_params *params,
2911                                             struct tc_mqprio_qopt *qopt)
2912 {
2913         params->mqprio.mode = TC_MQPRIO_MODE_CHANNEL;
2914         params->mqprio.num_tc = qopt->num_tc;
2915         mlx5e_mqprio_build_tc_to_txq(params->mqprio.tc_to_txq, qopt);
2916 }
2917
2918 static void mlx5e_params_mqprio_reset(struct mlx5e_params *params)
2919 {
2920         mlx5e_params_mqprio_dcb_set(params, 1);
2921 }
2922
2923 static int mlx5e_setup_tc_mqprio_dcb(struct mlx5e_priv *priv,
2924                                      struct tc_mqprio_qopt *mqprio)
2925 {
2926         struct mlx5e_params new_params;
2927         u8 tc = mqprio->num_tc;
2928         int err;
2929
2930         mqprio->hw = TC_MQPRIO_HW_OFFLOAD_TCS;
2931
2932         if (tc && tc != MLX5E_MAX_NUM_TC)
2933                 return -EINVAL;
2934
2935         new_params = priv->channels.params;
2936         mlx5e_params_mqprio_dcb_set(&new_params, tc ? tc : 1);
2937
2938         err = mlx5e_safe_switch_params(priv, &new_params,
2939                                        mlx5e_num_channels_changed_ctx, NULL, true);
2940
2941         priv->max_opened_tc = max_t(u8, priv->max_opened_tc,
2942                                     mlx5e_get_dcb_num_tc(&priv->channels.params));
2943         return err;
2944 }
2945
2946 static int mlx5e_mqprio_channel_validate(struct mlx5e_priv *priv,
2947                                          struct tc_mqprio_qopt_offload *mqprio)
2948 {
2949         struct net_device *netdev = priv->netdev;
2950         struct mlx5e_ptp *ptp_channel;
2951         int agg_count = 0;
2952         int i;
2953
2954         ptp_channel = priv->channels.ptp;
2955         if (ptp_channel && test_bit(MLX5E_PTP_STATE_TX, ptp_channel->state)) {
2956                 netdev_err(netdev,
2957                            "Cannot activate MQPRIO mode channel since it conflicts with TX port TS\n");
2958                 return -EINVAL;
2959         }
2960
2961         if (mqprio->qopt.offset[0] != 0 || mqprio->qopt.num_tc < 1 ||
2962             mqprio->qopt.num_tc > MLX5E_MAX_NUM_MQPRIO_CH_TC)
2963                 return -EINVAL;
2964
2965         for (i = 0; i < mqprio->qopt.num_tc; i++) {
2966                 if (!mqprio->qopt.count[i]) {
2967                         netdev_err(netdev, "Zero size for queue-group (%d) is not supported\n", i);
2968                         return -EINVAL;
2969                 }
2970                 if (mqprio->min_rate[i]) {
2971                         netdev_err(netdev, "Min tx rate is not supported\n");
2972                         return -EINVAL;
2973                 }
2974                 if (mqprio->max_rate[i]) {
2975                         netdev_err(netdev, "Max tx rate is not supported\n");
2976                         return -EINVAL;
2977                 }
2978
2979                 if (mqprio->qopt.offset[i] != agg_count) {
2980                         netdev_err(netdev, "Discontinuous queues config is not supported\n");
2981                         return -EINVAL;
2982                 }
2983                 agg_count += mqprio->qopt.count[i];
2984         }
2985
2986         if (priv->channels.params.num_channels < agg_count) {
2987                 netdev_err(netdev, "Num of queues (%d) exceeds available (%d)\n",
2988                            agg_count, priv->channels.params.num_channels);
2989                 return -EINVAL;
2990         }
2991
2992         return 0;
2993 }
2994
2995 static int mlx5e_setup_tc_mqprio_channel(struct mlx5e_priv *priv,
2996                                          struct tc_mqprio_qopt_offload *mqprio)
2997 {
2998         mlx5e_fp_preactivate preactivate;
2999         struct mlx5e_params new_params;
3000         bool nch_changed;
3001         int err;
3002
3003         err = mlx5e_mqprio_channel_validate(priv, mqprio);
3004         if (err)
3005                 return err;
3006
3007         new_params = priv->channels.params;
3008         mlx5e_params_mqprio_channel_set(&new_params, &mqprio->qopt);
3009
3010         nch_changed = mlx5e_get_dcb_num_tc(&priv->channels.params) > 1;
3011         preactivate = nch_changed ? mlx5e_num_channels_changed_ctx :
3012                 mlx5e_update_netdev_queues_ctx;
3013         return mlx5e_safe_switch_params(priv, &new_params, preactivate, NULL, true);
3014 }
3015
3016 static int mlx5e_setup_tc_mqprio(struct mlx5e_priv *priv,
3017                                  struct tc_mqprio_qopt_offload *mqprio)
3018 {
3019         /* MQPRIO is another toplevel qdisc that can't be attached
3020          * simultaneously with the offloaded HTB.
3021          */
3022         if (WARN_ON(priv->htb.maj_id))
3023                 return -EINVAL;
3024
3025         switch (mqprio->mode) {
3026         case TC_MQPRIO_MODE_DCB:
3027                 return mlx5e_setup_tc_mqprio_dcb(priv, &mqprio->qopt);
3028         case TC_MQPRIO_MODE_CHANNEL:
3029                 return mlx5e_setup_tc_mqprio_channel(priv, mqprio);
3030         default:
3031                 return -EOPNOTSUPP;
3032         }
3033 }
3034
3035 static int mlx5e_setup_tc_htb(struct mlx5e_priv *priv, struct tc_htb_qopt_offload *htb)
3036 {
3037         int res;
3038
3039         switch (htb->command) {
3040         case TC_HTB_CREATE:
3041                 return mlx5e_htb_root_add(priv, htb->parent_classid, htb->classid,
3042                                           htb->extack);
3043         case TC_HTB_DESTROY:
3044                 return mlx5e_htb_root_del(priv);
3045         case TC_HTB_LEAF_ALLOC_QUEUE:
3046                 res = mlx5e_htb_leaf_alloc_queue(priv, htb->classid, htb->parent_classid,
3047                                                  htb->rate, htb->ceil, htb->extack);
3048                 if (res < 0)
3049                         return res;
3050                 htb->qid = res;
3051                 return 0;
3052         case TC_HTB_LEAF_TO_INNER:
3053                 return mlx5e_htb_leaf_to_inner(priv, htb->parent_classid, htb->classid,
3054                                                htb->rate, htb->ceil, htb->extack);
3055         case TC_HTB_LEAF_DEL:
3056                 return mlx5e_htb_leaf_del(priv, &htb->classid, htb->extack);
3057         case TC_HTB_LEAF_DEL_LAST:
3058         case TC_HTB_LEAF_DEL_LAST_FORCE:
3059                 return mlx5e_htb_leaf_del_last(priv, htb->classid,
3060                                                htb->command == TC_HTB_LEAF_DEL_LAST_FORCE,
3061                                                htb->extack);
3062         case TC_HTB_NODE_MODIFY:
3063                 return mlx5e_htb_node_modify(priv, htb->classid, htb->rate, htb->ceil,
3064                                              htb->extack);
3065         case TC_HTB_LEAF_QUERY_QUEUE:
3066                 res = mlx5e_get_txq_by_classid(priv, htb->classid);
3067                 if (res < 0)
3068                         return res;
3069                 htb->qid = res;
3070                 return 0;
3071         default:
3072                 return -EOPNOTSUPP;
3073         }
3074 }
3075
3076 static LIST_HEAD(mlx5e_block_cb_list);
3077
3078 static int mlx5e_setup_tc(struct net_device *dev, enum tc_setup_type type,
3079                           void *type_data)
3080 {
3081         struct mlx5e_priv *priv = netdev_priv(dev);
3082         bool tc_unbind = false;
3083         int err;
3084
3085         if (type == TC_SETUP_BLOCK &&
3086             ((struct flow_block_offload *)type_data)->command == FLOW_BLOCK_UNBIND)
3087                 tc_unbind = true;
3088
3089         if (!netif_device_present(dev) && !tc_unbind)
3090                 return -ENODEV;
3091
3092         switch (type) {
3093         case TC_SETUP_BLOCK: {
3094                 struct flow_block_offload *f = type_data;
3095
3096                 f->unlocked_driver_cb = true;
3097                 return flow_block_cb_setup_simple(type_data,
3098                                                   &mlx5e_block_cb_list,
3099                                                   mlx5e_setup_tc_block_cb,
3100                                                   priv, priv, true);
3101         }
3102         case TC_SETUP_QDISC_MQPRIO:
3103                 mutex_lock(&priv->state_lock);
3104                 err = mlx5e_setup_tc_mqprio(priv, type_data);
3105                 mutex_unlock(&priv->state_lock);
3106                 return err;
3107         case TC_SETUP_QDISC_HTB:
3108                 mutex_lock(&priv->state_lock);
3109                 err = mlx5e_setup_tc_htb(priv, type_data);
3110                 mutex_unlock(&priv->state_lock);
3111                 return err;
3112         default:
3113                 return -EOPNOTSUPP;
3114         }
3115 }
3116
3117 void mlx5e_fold_sw_stats64(struct mlx5e_priv *priv, struct rtnl_link_stats64 *s)
3118 {
3119         int i;
3120
3121         for (i = 0; i < priv->stats_nch; i++) {
3122                 struct mlx5e_channel_stats *channel_stats = &priv->channel_stats[i];
3123                 struct mlx5e_rq_stats *xskrq_stats = &channel_stats->xskrq;
3124                 struct mlx5e_rq_stats *rq_stats = &channel_stats->rq;
3125                 int j;
3126
3127                 s->rx_packets   += rq_stats->packets + xskrq_stats->packets;
3128                 s->rx_bytes     += rq_stats->bytes + xskrq_stats->bytes;
3129                 s->multicast    += rq_stats->mcast_packets + xskrq_stats->mcast_packets;
3130
3131                 for (j = 0; j < priv->max_opened_tc; j++) {
3132                         struct mlx5e_sq_stats *sq_stats = &channel_stats->sq[j];
3133
3134                         s->tx_packets    += sq_stats->packets;
3135                         s->tx_bytes      += sq_stats->bytes;
3136                         s->tx_dropped    += sq_stats->dropped;
3137                 }
3138         }
3139         if (priv->tx_ptp_opened) {
3140                 for (i = 0; i < priv->max_opened_tc; i++) {
3141                         struct mlx5e_sq_stats *sq_stats = &priv->ptp_stats.sq[i];
3142
3143                         s->tx_packets    += sq_stats->packets;
3144                         s->tx_bytes      += sq_stats->bytes;
3145                         s->tx_dropped    += sq_stats->dropped;
3146                 }
3147         }
3148         if (priv->rx_ptp_opened) {
3149                 struct mlx5e_rq_stats *rq_stats = &priv->ptp_stats.rq;
3150
3151                 s->rx_packets   += rq_stats->packets;
3152                 s->rx_bytes     += rq_stats->bytes;
3153                 s->multicast    += rq_stats->mcast_packets;
3154         }
3155 }
3156
3157 void
3158 mlx5e_get_stats(struct net_device *dev, struct rtnl_link_stats64 *stats)
3159 {
3160         struct mlx5e_priv *priv = netdev_priv(dev);
3161         struct mlx5e_pport_stats *pstats = &priv->stats.pport;
3162
3163         if (!netif_device_present(dev))
3164                 return;
3165
3166         /* In switchdev mode, monitor counters doesn't monitor
3167          * rx/tx stats of 802_3. The update stats mechanism
3168          * should keep the 802_3 layout counters updated
3169          */
3170         if (!mlx5e_monitor_counter_supported(priv) ||
3171             mlx5e_is_uplink_rep(priv)) {
3172                 /* update HW stats in background for next time */
3173                 mlx5e_queue_update_stats(priv);
3174         }
3175
3176         if (mlx5e_is_uplink_rep(priv)) {
3177                 struct mlx5e_vport_stats *vstats = &priv->stats.vport;
3178
3179                 stats->rx_packets = PPORT_802_3_GET(pstats, a_frames_received_ok);
3180                 stats->rx_bytes   = PPORT_802_3_GET(pstats, a_octets_received_ok);
3181                 stats->tx_packets = PPORT_802_3_GET(pstats, a_frames_transmitted_ok);
3182                 stats->tx_bytes   = PPORT_802_3_GET(pstats, a_octets_transmitted_ok);
3183
3184                 /* vport multicast also counts packets that are dropped due to steering
3185                  * or rx out of buffer
3186                  */
3187                 stats->multicast = VPORT_COUNTER_GET(vstats, received_eth_multicast.packets);
3188         } else {
3189                 mlx5e_fold_sw_stats64(priv, stats);
3190         }
3191
3192         stats->rx_dropped = priv->stats.qcnt.rx_out_of_buffer;
3193
3194         stats->rx_length_errors =
3195                 PPORT_802_3_GET(pstats, a_in_range_length_errors) +
3196                 PPORT_802_3_GET(pstats, a_out_of_range_length_field) +
3197                 PPORT_802_3_GET(pstats, a_frame_too_long_errors);
3198         stats->rx_crc_errors =
3199                 PPORT_802_3_GET(pstats, a_frame_check_sequence_errors);
3200         stats->rx_frame_errors = PPORT_802_3_GET(pstats, a_alignment_errors);
3201         stats->tx_aborted_errors = PPORT_2863_GET(pstats, if_out_discards);
3202         stats->rx_errors = stats->rx_length_errors + stats->rx_crc_errors +
3203                            stats->rx_frame_errors;
3204         stats->tx_errors = stats->tx_aborted_errors + stats->tx_carrier_errors;
3205 }
3206
3207 static void mlx5e_nic_set_rx_mode(struct mlx5e_priv *priv)
3208 {
3209         if (mlx5e_is_uplink_rep(priv))
3210                 return; /* no rx mode for uplink rep */
3211
3212         queue_work(priv->wq, &priv->set_rx_mode_work);
3213 }
3214
3215 static void mlx5e_set_rx_mode(struct net_device *dev)
3216 {
3217         struct mlx5e_priv *priv = netdev_priv(dev);
3218
3219         mlx5e_nic_set_rx_mode(priv);
3220 }
3221
3222 static int mlx5e_set_mac(struct net_device *netdev, void *addr)
3223 {
3224         struct mlx5e_priv *priv = netdev_priv(netdev);
3225         struct sockaddr *saddr = addr;
3226
3227         if (!is_valid_ether_addr(saddr->sa_data))
3228                 return -EADDRNOTAVAIL;
3229
3230         netif_addr_lock_bh(netdev);
3231         eth_hw_addr_set(netdev, saddr->sa_data);
3232         netif_addr_unlock_bh(netdev);
3233
3234         mlx5e_nic_set_rx_mode(priv);
3235
3236         return 0;
3237 }
3238
3239 #define MLX5E_SET_FEATURE(features, feature, enable)    \
3240         do {                                            \
3241                 if (enable)                             \
3242                         *features |= feature;           \
3243                 else                                    \
3244                         *features &= ~feature;          \
3245         } while (0)
3246
3247 typedef int (*mlx5e_feature_handler)(struct net_device *netdev, bool enable);
3248
3249 static int set_feature_lro(struct net_device *netdev, bool enable)
3250 {
3251         struct mlx5e_priv *priv = netdev_priv(netdev);
3252         struct mlx5_core_dev *mdev = priv->mdev;
3253         struct mlx5e_params *cur_params;
3254         struct mlx5e_params new_params;
3255         bool reset = true;
3256         int err = 0;
3257
3258         mutex_lock(&priv->state_lock);
3259
3260         if (enable && priv->xsk.refcnt) {
3261                 netdev_warn(netdev, "LRO is incompatible with AF_XDP (%u XSKs are active)\n",
3262                             priv->xsk.refcnt);
3263                 err = -EINVAL;
3264                 goto out;
3265         }
3266
3267         cur_params = &priv->channels.params;
3268         if (enable && !MLX5E_GET_PFLAG(cur_params, MLX5E_PFLAG_RX_STRIDING_RQ)) {
3269                 netdev_warn(netdev, "can't set LRO with legacy RQ\n");
3270                 err = -EINVAL;
3271                 goto out;
3272         }
3273
3274         new_params = *cur_params;
3275         new_params.lro_en = enable;
3276
3277         if (cur_params->rq_wq_type == MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ) {
3278                 if (mlx5e_rx_mpwqe_is_linear_skb(mdev, cur_params, NULL) ==
3279                     mlx5e_rx_mpwqe_is_linear_skb(mdev, &new_params, NULL))
3280                         reset = false;
3281         }
3282
3283         err = mlx5e_safe_switch_params(priv, &new_params,
3284                                        mlx5e_modify_tirs_lro_ctx, NULL, reset);
3285 out:
3286         mutex_unlock(&priv->state_lock);
3287         return err;
3288 }
3289
3290 static int set_feature_cvlan_filter(struct net_device *netdev, bool enable)
3291 {
3292         struct mlx5e_priv *priv = netdev_priv(netdev);
3293
3294         if (enable)
3295                 mlx5e_enable_cvlan_filter(priv);
3296         else
3297                 mlx5e_disable_cvlan_filter(priv);
3298
3299         return 0;
3300 }
3301
3302 static int set_feature_hw_tc(struct net_device *netdev, bool enable)
3303 {
3304         struct mlx5e_priv *priv = netdev_priv(netdev);
3305
3306 #if IS_ENABLED(CONFIG_MLX5_CLS_ACT)
3307         if (!enable && mlx5e_tc_num_filters(priv, MLX5_TC_FLAG(NIC_OFFLOAD))) {
3308                 netdev_err(netdev,
3309                            "Active offloaded tc filters, can't turn hw_tc_offload off\n");
3310                 return -EINVAL;
3311         }
3312 #endif
3313
3314         if (!enable && priv->htb.maj_id) {
3315                 netdev_err(netdev, "Active HTB offload, can't turn hw_tc_offload off\n");
3316                 return -EINVAL;
3317         }
3318
3319         return 0;
3320 }
3321
3322 static int set_feature_rx_all(struct net_device *netdev, bool enable)
3323 {
3324         struct mlx5e_priv *priv = netdev_priv(netdev);
3325         struct mlx5_core_dev *mdev = priv->mdev;
3326
3327         return mlx5_set_port_fcs(mdev, !enable);
3328 }
3329
3330 static int set_feature_rx_fcs(struct net_device *netdev, bool enable)
3331 {
3332         struct mlx5e_priv *priv = netdev_priv(netdev);
3333         int err;
3334
3335         mutex_lock(&priv->state_lock);
3336
3337         priv->channels.params.scatter_fcs_en = enable;
3338         err = mlx5e_modify_channels_scatter_fcs(&priv->channels, enable);
3339         if (err)
3340                 priv->channels.params.scatter_fcs_en = !enable;
3341
3342         mutex_unlock(&priv->state_lock);
3343
3344         return err;
3345 }
3346
3347 static int set_feature_rx_vlan(struct net_device *netdev, bool enable)
3348 {
3349         struct mlx5e_priv *priv = netdev_priv(netdev);
3350         int err = 0;
3351
3352         mutex_lock(&priv->state_lock);
3353
3354         priv->channels.params.vlan_strip_disable = !enable;
3355         if (!test_bit(MLX5E_STATE_OPENED, &priv->state))
3356                 goto unlock;
3357
3358         err = mlx5e_modify_channels_vsd(&priv->channels, !enable);
3359         if (err)
3360                 priv->channels.params.vlan_strip_disable = enable;
3361
3362 unlock:
3363         mutex_unlock(&priv->state_lock);
3364
3365         return err;
3366 }
3367
3368 #ifdef CONFIG_MLX5_EN_ARFS
3369 static int set_feature_arfs(struct net_device *netdev, bool enable)
3370 {
3371         struct mlx5e_priv *priv = netdev_priv(netdev);
3372         int err;
3373
3374         if (enable)
3375                 err = mlx5e_arfs_enable(priv);
3376         else
3377                 err = mlx5e_arfs_disable(priv);
3378
3379         return err;
3380 }
3381 #endif
3382
3383 static int mlx5e_handle_feature(struct net_device *netdev,
3384                                 netdev_features_t *features,
3385                                 netdev_features_t wanted_features,
3386                                 netdev_features_t feature,
3387                                 mlx5e_feature_handler feature_handler)
3388 {
3389         netdev_features_t changes = wanted_features ^ netdev->features;
3390         bool enable = !!(wanted_features & feature);
3391         int err;
3392
3393         if (!(changes & feature))
3394                 return 0;
3395
3396         err = feature_handler(netdev, enable);
3397         if (err) {
3398                 netdev_err(netdev, "%s feature %pNF failed, err %d\n",
3399                            enable ? "Enable" : "Disable", &feature, err);
3400                 return err;
3401         }
3402
3403         MLX5E_SET_FEATURE(features, feature, enable);
3404         return 0;
3405 }
3406
3407 int mlx5e_set_features(struct net_device *netdev, netdev_features_t features)
3408 {
3409         netdev_features_t oper_features = netdev->features;
3410         int err = 0;
3411
3412 #define MLX5E_HANDLE_FEATURE(feature, handler) \
3413         mlx5e_handle_feature(netdev, &oper_features, features, feature, handler)
3414
3415         err |= MLX5E_HANDLE_FEATURE(NETIF_F_LRO, set_feature_lro);
3416         err |= MLX5E_HANDLE_FEATURE(NETIF_F_HW_VLAN_CTAG_FILTER,
3417                                     set_feature_cvlan_filter);
3418         err |= MLX5E_HANDLE_FEATURE(NETIF_F_HW_TC, set_feature_hw_tc);
3419         err |= MLX5E_HANDLE_FEATURE(NETIF_F_RXALL, set_feature_rx_all);
3420         err |= MLX5E_HANDLE_FEATURE(NETIF_F_RXFCS, set_feature_rx_fcs);
3421         err |= MLX5E_HANDLE_FEATURE(NETIF_F_HW_VLAN_CTAG_RX, set_feature_rx_vlan);
3422 #ifdef CONFIG_MLX5_EN_ARFS
3423         err |= MLX5E_HANDLE_FEATURE(NETIF_F_NTUPLE, set_feature_arfs);
3424 #endif
3425         err |= MLX5E_HANDLE_FEATURE(NETIF_F_HW_TLS_RX, mlx5e_ktls_set_feature_rx);
3426
3427         if (err) {
3428                 netdev->features = oper_features;
3429                 return -EINVAL;
3430         }
3431
3432         return 0;
3433 }
3434
3435 static netdev_features_t mlx5e_fix_uplink_rep_features(struct net_device *netdev,
3436                                                        netdev_features_t features)
3437 {
3438         features &= ~NETIF_F_HW_TLS_RX;
3439         if (netdev->features & NETIF_F_HW_TLS_RX)
3440                 netdev_warn(netdev, "Disabling hw_tls_rx, not supported in switchdev mode\n");
3441
3442         features &= ~NETIF_F_HW_TLS_TX;
3443         if (netdev->features & NETIF_F_HW_TLS_TX)
3444                 netdev_warn(netdev, "Disabling hw_tls_tx, not supported in switchdev mode\n");
3445
3446         features &= ~NETIF_F_NTUPLE;
3447         if (netdev->features & NETIF_F_NTUPLE)
3448                 netdev_warn(netdev, "Disabling ntuple, not supported in switchdev mode\n");
3449
3450         return features;
3451 }
3452
3453 static netdev_features_t mlx5e_fix_features(struct net_device *netdev,
3454                                             netdev_features_t features)
3455 {
3456         struct mlx5e_priv *priv = netdev_priv(netdev);
3457         struct mlx5e_params *params;
3458
3459         mutex_lock(&priv->state_lock);
3460         params = &priv->channels.params;
3461         if (!priv->fs.vlan ||
3462             !bitmap_empty(mlx5e_vlan_get_active_svlans(priv->fs.vlan), VLAN_N_VID)) {
3463                 /* HW strips the outer C-tag header, this is a problem
3464                  * for S-tag traffic.
3465                  */
3466                 features &= ~NETIF_F_HW_VLAN_CTAG_RX;
3467                 if (!params->vlan_strip_disable)
3468                         netdev_warn(netdev, "Dropping C-tag vlan stripping offload due to S-tag vlan\n");
3469         }
3470
3471         if (!MLX5E_GET_PFLAG(params, MLX5E_PFLAG_RX_STRIDING_RQ)) {
3472                 if (features & NETIF_F_LRO) {
3473                         netdev_warn(netdev, "Disabling LRO, not supported in legacy RQ\n");
3474                         features &= ~NETIF_F_LRO;
3475                 }
3476         }
3477
3478         if (MLX5E_GET_PFLAG(params, MLX5E_PFLAG_RX_CQE_COMPRESS)) {
3479                 features &= ~NETIF_F_RXHASH;
3480                 if (netdev->features & NETIF_F_RXHASH)
3481                         netdev_warn(netdev, "Disabling rxhash, not supported when CQE compress is active\n");
3482         }
3483
3484         if (mlx5e_is_uplink_rep(priv))
3485                 features = mlx5e_fix_uplink_rep_features(netdev, features);
3486
3487         mutex_unlock(&priv->state_lock);
3488
3489         return features;
3490 }
3491
3492 static bool mlx5e_xsk_validate_mtu(struct net_device *netdev,
3493                                    struct mlx5e_channels *chs,
3494                                    struct mlx5e_params *new_params,
3495                                    struct mlx5_core_dev *mdev)
3496 {
3497         u16 ix;
3498
3499         for (ix = 0; ix < chs->params.num_channels; ix++) {
3500                 struct xsk_buff_pool *xsk_pool =
3501                         mlx5e_xsk_get_pool(&chs->params, chs->params.xsk, ix);
3502                 struct mlx5e_xsk_param xsk;
3503
3504                 if (!xsk_pool)
3505                         continue;
3506
3507                 mlx5e_build_xsk_param(xsk_pool, &xsk);
3508
3509                 if (!mlx5e_validate_xsk_param(new_params, &xsk, mdev)) {
3510                         u32 hr = mlx5e_get_linear_rq_headroom(new_params, &xsk);
3511                         int max_mtu_frame, max_mtu_page, max_mtu;
3512
3513                         /* Two criteria must be met:
3514                          * 1. HW MTU + all headrooms <= XSK frame size.
3515                          * 2. Size of SKBs allocated on XDP_PASS <= PAGE_SIZE.
3516                          */
3517                         max_mtu_frame = MLX5E_HW2SW_MTU(new_params, xsk.chunk_size - hr);
3518                         max_mtu_page = mlx5e_xdp_max_mtu(new_params, &xsk);
3519                         max_mtu = min(max_mtu_frame, max_mtu_page);
3520
3521                         netdev_err(netdev, "MTU %d is too big for an XSK running on channel %u. Try MTU <= %d\n",
3522                                    new_params->sw_mtu, ix, max_mtu);
3523                         return false;
3524                 }
3525         }
3526
3527         return true;
3528 }
3529
3530 int mlx5e_change_mtu(struct net_device *netdev, int new_mtu,
3531                      mlx5e_fp_preactivate preactivate)
3532 {
3533         struct mlx5e_priv *priv = netdev_priv(netdev);
3534         struct mlx5e_params new_params;
3535         struct mlx5e_params *params;
3536         bool reset = true;
3537         int err = 0;
3538
3539         mutex_lock(&priv->state_lock);
3540
3541         params = &priv->channels.params;
3542
3543         new_params = *params;
3544         new_params.sw_mtu = new_mtu;
3545         err = mlx5e_validate_params(priv->mdev, &new_params);
3546         if (err)
3547                 goto out;
3548
3549         if (params->xdp_prog &&
3550             !mlx5e_rx_is_linear_skb(&new_params, NULL)) {
3551                 netdev_err(netdev, "MTU(%d) > %d is not allowed while XDP enabled\n",
3552                            new_mtu, mlx5e_xdp_max_mtu(params, NULL));
3553                 err = -EINVAL;
3554                 goto out;
3555         }
3556
3557         if (priv->xsk.refcnt &&
3558             !mlx5e_xsk_validate_mtu(netdev, &priv->channels,
3559                                     &new_params, priv->mdev)) {
3560                 err = -EINVAL;
3561                 goto out;
3562         }
3563
3564         if (params->lro_en)
3565                 reset = false;
3566
3567         if (params->rq_wq_type == MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ) {
3568                 bool is_linear_old = mlx5e_rx_mpwqe_is_linear_skb(priv->mdev, params, NULL);
3569                 bool is_linear_new = mlx5e_rx_mpwqe_is_linear_skb(priv->mdev,
3570                                                                   &new_params, NULL);
3571                 u8 ppw_old = mlx5e_mpwqe_log_pkts_per_wqe(params, NULL);
3572                 u8 ppw_new = mlx5e_mpwqe_log_pkts_per_wqe(&new_params, NULL);
3573
3574                 /* Always reset in linear mode - hw_mtu is used in data path.
3575                  * Check that the mode was non-linear and didn't change.
3576                  * If XSK is active, XSK RQs are linear.
3577                  */
3578                 if (!is_linear_old && !is_linear_new && !priv->xsk.refcnt &&
3579                     ppw_old == ppw_new)
3580                         reset = false;
3581         }
3582
3583         err = mlx5e_safe_switch_params(priv, &new_params, preactivate, NULL, reset);
3584
3585 out:
3586         netdev->mtu = params->sw_mtu;
3587         mutex_unlock(&priv->state_lock);
3588         return err;
3589 }
3590
3591 static int mlx5e_change_nic_mtu(struct net_device *netdev, int new_mtu)
3592 {
3593         return mlx5e_change_mtu(netdev, new_mtu, mlx5e_set_dev_port_mtu_ctx);
3594 }
3595
3596 int mlx5e_ptp_rx_manage_fs_ctx(struct mlx5e_priv *priv, void *ctx)
3597 {
3598         bool set  = *(bool *)ctx;
3599
3600         return mlx5e_ptp_rx_manage_fs(priv, set);
3601 }
3602
3603 static int mlx5e_hwstamp_config_no_ptp_rx(struct mlx5e_priv *priv, bool rx_filter)
3604 {
3605         bool rx_cqe_compress_def = priv->channels.params.rx_cqe_compress_def;
3606         int err;
3607
3608         if (!rx_filter)
3609                 /* Reset CQE compression to Admin default */
3610                 return mlx5e_modify_rx_cqe_compression_locked(priv, rx_cqe_compress_def, false);
3611
3612         if (!MLX5E_GET_PFLAG(&priv->channels.params, MLX5E_PFLAG_RX_CQE_COMPRESS))
3613                 return 0;
3614
3615         /* Disable CQE compression */
3616         netdev_warn(priv->netdev, "Disabling RX cqe compression\n");
3617         err = mlx5e_modify_rx_cqe_compression_locked(priv, false, true);
3618         if (err)
3619                 netdev_err(priv->netdev, "Failed disabling cqe compression err=%d\n", err);
3620
3621         return err;
3622 }
3623
3624 static int mlx5e_hwstamp_config_ptp_rx(struct mlx5e_priv *priv, bool ptp_rx)
3625 {
3626         struct mlx5e_params new_params;
3627
3628         if (ptp_rx == priv->channels.params.ptp_rx)
3629                 return 0;
3630
3631         new_params = priv->channels.params;
3632         new_params.ptp_rx = ptp_rx;
3633         return mlx5e_safe_switch_params(priv, &new_params, mlx5e_ptp_rx_manage_fs_ctx,
3634                                         &new_params.ptp_rx, true);
3635 }
3636
3637 int mlx5e_hwstamp_set(struct mlx5e_priv *priv, struct ifreq *ifr)
3638 {
3639         struct hwtstamp_config config;
3640         bool rx_cqe_compress_def;
3641         bool ptp_rx;
3642         int err;
3643
3644         if (!MLX5_CAP_GEN(priv->mdev, device_frequency_khz) ||
3645             (mlx5_clock_get_ptp_index(priv->mdev) == -1))
3646                 return -EOPNOTSUPP;
3647
3648         if (copy_from_user(&config, ifr->ifr_data, sizeof(config)))
3649                 return -EFAULT;
3650
3651         /* TX HW timestamp */
3652         switch (config.tx_type) {
3653         case HWTSTAMP_TX_OFF:
3654         case HWTSTAMP_TX_ON:
3655                 break;
3656         default:
3657                 return -ERANGE;
3658         }
3659
3660         mutex_lock(&priv->state_lock);
3661         rx_cqe_compress_def = priv->channels.params.rx_cqe_compress_def;
3662
3663         /* RX HW timestamp */
3664         switch (config.rx_filter) {
3665         case HWTSTAMP_FILTER_NONE:
3666                 ptp_rx = false;
3667                 break;
3668         case HWTSTAMP_FILTER_ALL:
3669         case HWTSTAMP_FILTER_SOME:
3670         case HWTSTAMP_FILTER_PTP_V1_L4_EVENT:
3671         case HWTSTAMP_FILTER_PTP_V1_L4_SYNC:
3672         case HWTSTAMP_FILTER_PTP_V1_L4_DELAY_REQ:
3673         case HWTSTAMP_FILTER_PTP_V2_L4_EVENT:
3674         case HWTSTAMP_FILTER_PTP_V2_L4_SYNC:
3675         case HWTSTAMP_FILTER_PTP_V2_L4_DELAY_REQ:
3676         case HWTSTAMP_FILTER_PTP_V2_L2_EVENT:
3677         case HWTSTAMP_FILTER_PTP_V2_L2_SYNC:
3678         case HWTSTAMP_FILTER_PTP_V2_L2_DELAY_REQ:
3679         case HWTSTAMP_FILTER_PTP_V2_EVENT:
3680         case HWTSTAMP_FILTER_PTP_V2_SYNC:
3681         case HWTSTAMP_FILTER_PTP_V2_DELAY_REQ:
3682         case HWTSTAMP_FILTER_NTP_ALL:
3683                 config.rx_filter = HWTSTAMP_FILTER_ALL;
3684                 /* ptp_rx is set if both HW TS is set and CQE
3685                  * compression is set
3686                  */
3687                 ptp_rx = rx_cqe_compress_def;
3688                 break;
3689         default:
3690                 err = -ERANGE;
3691                 goto err_unlock;
3692         }
3693
3694         if (!priv->profile->rx_ptp_support)
3695                 err = mlx5e_hwstamp_config_no_ptp_rx(priv,
3696                                                      config.rx_filter != HWTSTAMP_FILTER_NONE);
3697         else
3698                 err = mlx5e_hwstamp_config_ptp_rx(priv, ptp_rx);
3699         if (err)
3700                 goto err_unlock;
3701
3702         memcpy(&priv->tstamp, &config, sizeof(config));
3703         mutex_unlock(&priv->state_lock);
3704
3705         /* might need to fix some features */
3706         netdev_update_features(priv->netdev);
3707
3708         return copy_to_user(ifr->ifr_data, &config,
3709                             sizeof(config)) ? -EFAULT : 0;
3710 err_unlock:
3711         mutex_unlock(&priv->state_lock);
3712         return err;
3713 }
3714
3715 int mlx5e_hwstamp_get(struct mlx5e_priv *priv, struct ifreq *ifr)
3716 {
3717         struct hwtstamp_config *cfg = &priv->tstamp;
3718
3719         if (!MLX5_CAP_GEN(priv->mdev, device_frequency_khz))
3720                 return -EOPNOTSUPP;
3721
3722         return copy_to_user(ifr->ifr_data, cfg, sizeof(*cfg)) ? -EFAULT : 0;
3723 }
3724
3725 static int mlx5e_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
3726 {
3727         struct mlx5e_priv *priv = netdev_priv(dev);
3728
3729         switch (cmd) {
3730         case SIOCSHWTSTAMP:
3731                 return mlx5e_hwstamp_set(priv, ifr);
3732         case SIOCGHWTSTAMP:
3733                 return mlx5e_hwstamp_get(priv, ifr);
3734         default:
3735                 return -EOPNOTSUPP;
3736         }
3737 }
3738
3739 #ifdef CONFIG_MLX5_ESWITCH
3740 int mlx5e_set_vf_mac(struct net_device *dev, int vf, u8 *mac)
3741 {
3742         struct mlx5e_priv *priv = netdev_priv(dev);
3743         struct mlx5_core_dev *mdev = priv->mdev;
3744
3745         return mlx5_eswitch_set_vport_mac(mdev->priv.eswitch, vf + 1, mac);
3746 }
3747
3748 static int mlx5e_set_vf_vlan(struct net_device *dev, int vf, u16 vlan, u8 qos,
3749                              __be16 vlan_proto)
3750 {
3751         struct mlx5e_priv *priv = netdev_priv(dev);
3752         struct mlx5_core_dev *mdev = priv->mdev;
3753
3754         if (vlan_proto != htons(ETH_P_8021Q))
3755                 return -EPROTONOSUPPORT;
3756
3757         return mlx5_eswitch_set_vport_vlan(mdev->priv.eswitch, vf + 1,
3758                                            vlan, qos);
3759 }
3760
3761 static int mlx5e_set_vf_spoofchk(struct net_device *dev, int vf, bool setting)
3762 {
3763         struct mlx5e_priv *priv = netdev_priv(dev);
3764         struct mlx5_core_dev *mdev = priv->mdev;
3765
3766         return mlx5_eswitch_set_vport_spoofchk(mdev->priv.eswitch, vf + 1, setting);
3767 }
3768
3769 static int mlx5e_set_vf_trust(struct net_device *dev, int vf, bool setting)
3770 {
3771         struct mlx5e_priv *priv = netdev_priv(dev);
3772         struct mlx5_core_dev *mdev = priv->mdev;
3773
3774         return mlx5_eswitch_set_vport_trust(mdev->priv.eswitch, vf + 1, setting);
3775 }
3776
3777 int mlx5e_set_vf_rate(struct net_device *dev, int vf, int min_tx_rate,
3778                       int max_tx_rate)
3779 {
3780         struct mlx5e_priv *priv = netdev_priv(dev);
3781         struct mlx5_core_dev *mdev = priv->mdev;
3782
3783         return mlx5_eswitch_set_vport_rate(mdev->priv.eswitch, vf + 1,
3784                                            max_tx_rate, min_tx_rate);
3785 }
3786
3787 static int mlx5_vport_link2ifla(u8 esw_link)
3788 {
3789         switch (esw_link) {
3790         case MLX5_VPORT_ADMIN_STATE_DOWN:
3791                 return IFLA_VF_LINK_STATE_DISABLE;
3792         case MLX5_VPORT_ADMIN_STATE_UP:
3793                 return IFLA_VF_LINK_STATE_ENABLE;
3794         }
3795         return IFLA_VF_LINK_STATE_AUTO;
3796 }
3797
3798 static int mlx5_ifla_link2vport(u8 ifla_link)
3799 {
3800         switch (ifla_link) {
3801         case IFLA_VF_LINK_STATE_DISABLE:
3802                 return MLX5_VPORT_ADMIN_STATE_DOWN;
3803         case IFLA_VF_LINK_STATE_ENABLE:
3804                 return MLX5_VPORT_ADMIN_STATE_UP;
3805         }
3806         return MLX5_VPORT_ADMIN_STATE_AUTO;
3807 }
3808
3809 static int mlx5e_set_vf_link_state(struct net_device *dev, int vf,
3810                                    int link_state)
3811 {
3812         struct mlx5e_priv *priv = netdev_priv(dev);
3813         struct mlx5_core_dev *mdev = priv->mdev;
3814
3815         if (mlx5e_is_uplink_rep(priv))
3816                 return -EOPNOTSUPP;
3817
3818         return mlx5_eswitch_set_vport_state(mdev->priv.eswitch, vf + 1,
3819                                             mlx5_ifla_link2vport(link_state));
3820 }
3821
3822 int mlx5e_get_vf_config(struct net_device *dev,
3823                         int vf, struct ifla_vf_info *ivi)
3824 {
3825         struct mlx5e_priv *priv = netdev_priv(dev);
3826         struct mlx5_core_dev *mdev = priv->mdev;
3827         int err;
3828
3829         if (!netif_device_present(dev))
3830                 return -EOPNOTSUPP;
3831
3832         err = mlx5_eswitch_get_vport_config(mdev->priv.eswitch, vf + 1, ivi);
3833         if (err)
3834                 return err;
3835         ivi->linkstate = mlx5_vport_link2ifla(ivi->linkstate);
3836         return 0;
3837 }
3838
3839 int mlx5e_get_vf_stats(struct net_device *dev,
3840                        int vf, struct ifla_vf_stats *vf_stats)
3841 {
3842         struct mlx5e_priv *priv = netdev_priv(dev);
3843         struct mlx5_core_dev *mdev = priv->mdev;
3844
3845         return mlx5_eswitch_get_vport_stats(mdev->priv.eswitch, vf + 1,
3846                                             vf_stats);
3847 }
3848
3849 static bool
3850 mlx5e_has_offload_stats(const struct net_device *dev, int attr_id)
3851 {
3852         struct mlx5e_priv *priv = netdev_priv(dev);
3853
3854         if (!netif_device_present(dev))
3855                 return false;
3856
3857         if (!mlx5e_is_uplink_rep(priv))
3858                 return false;
3859
3860         return mlx5e_rep_has_offload_stats(dev, attr_id);
3861 }
3862
3863 static int
3864 mlx5e_get_offload_stats(int attr_id, const struct net_device *dev,
3865                         void *sp)
3866 {
3867         struct mlx5e_priv *priv = netdev_priv(dev);
3868
3869         if (!mlx5e_is_uplink_rep(priv))
3870                 return -EOPNOTSUPP;
3871
3872         return mlx5e_rep_get_offload_stats(attr_id, dev, sp);
3873 }
3874 #endif
3875
3876 static bool mlx5e_tunnel_proto_supported_tx(struct mlx5_core_dev *mdev, u8 proto_type)
3877 {
3878         switch (proto_type) {
3879         case IPPROTO_GRE:
3880                 return MLX5_CAP_ETH(mdev, tunnel_stateless_gre);
3881         case IPPROTO_IPIP:
3882         case IPPROTO_IPV6:
3883                 return (MLX5_CAP_ETH(mdev, tunnel_stateless_ip_over_ip) ||
3884                         MLX5_CAP_ETH(mdev, tunnel_stateless_ip_over_ip_tx));
3885         default:
3886                 return false;
3887         }
3888 }
3889
3890 static bool mlx5e_gre_tunnel_inner_proto_offload_supported(struct mlx5_core_dev *mdev,
3891                                                            struct sk_buff *skb)
3892 {
3893         switch (skb->inner_protocol) {
3894         case htons(ETH_P_IP):
3895         case htons(ETH_P_IPV6):
3896         case htons(ETH_P_TEB):
3897                 return true;
3898         case htons(ETH_P_MPLS_UC):
3899         case htons(ETH_P_MPLS_MC):
3900                 return MLX5_CAP_ETH(mdev, tunnel_stateless_mpls_over_gre);
3901         }
3902         return false;
3903 }
3904
3905 static netdev_features_t mlx5e_tunnel_features_check(struct mlx5e_priv *priv,
3906                                                      struct sk_buff *skb,
3907                                                      netdev_features_t features)
3908 {
3909         unsigned int offset = 0;
3910         struct udphdr *udph;
3911         u8 proto;
3912         u16 port;
3913
3914         switch (vlan_get_protocol(skb)) {
3915         case htons(ETH_P_IP):
3916                 proto = ip_hdr(skb)->protocol;
3917                 break;
3918         case htons(ETH_P_IPV6):
3919                 proto = ipv6_find_hdr(skb, &offset, -1, NULL, NULL);
3920                 break;
3921         default:
3922                 goto out;
3923         }
3924
3925         switch (proto) {
3926         case IPPROTO_GRE:
3927                 if (mlx5e_gre_tunnel_inner_proto_offload_supported(priv->mdev, skb))
3928                         return features;
3929                 break;
3930         case IPPROTO_IPIP:
3931         case IPPROTO_IPV6:
3932                 if (mlx5e_tunnel_proto_supported_tx(priv->mdev, IPPROTO_IPIP))
3933                         return features;
3934                 break;
3935         case IPPROTO_UDP:
3936                 udph = udp_hdr(skb);
3937                 port = be16_to_cpu(udph->dest);
3938
3939                 /* Verify if UDP port is being offloaded by HW */
3940                 if (mlx5_vxlan_lookup_port(priv->mdev->vxlan, port))
3941                         return features;
3942
3943 #if IS_ENABLED(CONFIG_GENEVE)
3944                 /* Support Geneve offload for default UDP port */
3945                 if (port == GENEVE_UDP_PORT && mlx5_geneve_tx_allowed(priv->mdev))
3946                         return features;
3947 #endif
3948                 break;
3949 #ifdef CONFIG_MLX5_EN_IPSEC
3950         case IPPROTO_ESP:
3951                 return mlx5e_ipsec_feature_check(skb, features);
3952 #endif
3953         }
3954
3955 out:
3956         /* Disable CSUM and GSO if the udp dport is not offloaded by HW */
3957         return features & ~(NETIF_F_CSUM_MASK | NETIF_F_GSO_MASK);
3958 }
3959
3960 netdev_features_t mlx5e_features_check(struct sk_buff *skb,
3961                                        struct net_device *netdev,
3962                                        netdev_features_t features)
3963 {
3964         struct mlx5e_priv *priv = netdev_priv(netdev);
3965
3966         features = vlan_features_check(skb, features);
3967         features = vxlan_features_check(skb, features);
3968
3969         /* Validate if the tunneled packet is being offloaded by HW */
3970         if (skb->encapsulation &&
3971             (features & NETIF_F_CSUM_MASK || features & NETIF_F_GSO_MASK))
3972                 return mlx5e_tunnel_features_check(priv, skb, features);
3973
3974         return features;
3975 }
3976
3977 static void mlx5e_tx_timeout_work(struct work_struct *work)
3978 {
3979         struct mlx5e_priv *priv = container_of(work, struct mlx5e_priv,
3980                                                tx_timeout_work);
3981         struct net_device *netdev = priv->netdev;
3982         int i;
3983
3984         rtnl_lock();
3985         mutex_lock(&priv->state_lock);
3986
3987         if (!test_bit(MLX5E_STATE_OPENED, &priv->state))
3988                 goto unlock;
3989
3990         for (i = 0; i < netdev->real_num_tx_queues; i++) {
3991                 struct netdev_queue *dev_queue =
3992                         netdev_get_tx_queue(netdev, i);
3993                 struct mlx5e_txqsq *sq = priv->txq2sq[i];
3994
3995                 if (!netif_xmit_stopped(dev_queue))
3996                         continue;
3997
3998                 if (mlx5e_reporter_tx_timeout(sq))
3999                 /* break if tried to reopened channels */
4000                         break;
4001         }
4002
4003 unlock:
4004         mutex_unlock(&priv->state_lock);
4005         rtnl_unlock();
4006 }
4007
4008 static void mlx5e_tx_timeout(struct net_device *dev, unsigned int txqueue)
4009 {
4010         struct mlx5e_priv *priv = netdev_priv(dev);
4011
4012         netdev_err(dev, "TX timeout detected\n");
4013         queue_work(priv->wq, &priv->tx_timeout_work);
4014 }
4015
4016 static int mlx5e_xdp_allowed(struct mlx5e_priv *priv, struct bpf_prog *prog)
4017 {
4018         struct net_device *netdev = priv->netdev;
4019         struct mlx5e_params new_params;
4020
4021         if (priv->channels.params.lro_en) {
4022                 netdev_warn(netdev, "can't set XDP while LRO is on, disable LRO first\n");
4023                 return -EINVAL;
4024         }
4025
4026         if (mlx5_fpga_is_ipsec_device(priv->mdev)) {
4027                 netdev_warn(netdev,
4028                             "XDP is not available on Innova cards with IPsec support\n");
4029                 return -EINVAL;
4030         }
4031
4032         new_params = priv->channels.params;
4033         new_params.xdp_prog = prog;
4034
4035         /* No XSK params: AF_XDP can't be enabled yet at the point of setting
4036          * the XDP program.
4037          */
4038         if (!mlx5e_rx_is_linear_skb(&new_params, NULL)) {
4039                 netdev_warn(netdev, "XDP is not allowed with MTU(%d) > %d\n",
4040                             new_params.sw_mtu,
4041                             mlx5e_xdp_max_mtu(&new_params, NULL));
4042                 return -EINVAL;
4043         }
4044
4045         return 0;
4046 }
4047
4048 static void mlx5e_rq_replace_xdp_prog(struct mlx5e_rq *rq, struct bpf_prog *prog)
4049 {
4050         struct bpf_prog *old_prog;
4051
4052         old_prog = rcu_replace_pointer(rq->xdp_prog, prog,
4053                                        lockdep_is_held(&rq->priv->state_lock));
4054         if (old_prog)
4055                 bpf_prog_put(old_prog);
4056 }
4057
4058 static int mlx5e_xdp_set(struct net_device *netdev, struct bpf_prog *prog)
4059 {
4060         struct mlx5e_priv *priv = netdev_priv(netdev);
4061         struct mlx5e_params new_params;
4062         struct bpf_prog *old_prog;
4063         int err = 0;
4064         bool reset;
4065         int i;
4066
4067         mutex_lock(&priv->state_lock);
4068
4069         if (prog) {
4070                 err = mlx5e_xdp_allowed(priv, prog);
4071                 if (err)
4072                         goto unlock;
4073         }
4074
4075         /* no need for full reset when exchanging programs */
4076         reset = (!priv->channels.params.xdp_prog || !prog);
4077
4078         new_params = priv->channels.params;
4079         new_params.xdp_prog = prog;
4080         if (reset)
4081                 mlx5e_set_rq_type(priv->mdev, &new_params);
4082         old_prog = priv->channels.params.xdp_prog;
4083
4084         err = mlx5e_safe_switch_params(priv, &new_params, NULL, NULL, reset);
4085         if (err)
4086                 goto unlock;
4087
4088         if (old_prog)
4089                 bpf_prog_put(old_prog);
4090
4091         if (!test_bit(MLX5E_STATE_OPENED, &priv->state) || reset)
4092                 goto unlock;
4093
4094         /* exchanging programs w/o reset, we update ref counts on behalf
4095          * of the channels RQs here.
4096          */
4097         bpf_prog_add(prog, priv->channels.num);
4098         for (i = 0; i < priv->channels.num; i++) {
4099                 struct mlx5e_channel *c = priv->channels.c[i];
4100
4101                 mlx5e_rq_replace_xdp_prog(&c->rq, prog);
4102                 if (test_bit(MLX5E_CHANNEL_STATE_XSK, c->state)) {
4103                         bpf_prog_inc(prog);
4104                         mlx5e_rq_replace_xdp_prog(&c->xskrq, prog);
4105                 }
4106         }
4107
4108 unlock:
4109         mutex_unlock(&priv->state_lock);
4110         return err;
4111 }
4112
4113 static int mlx5e_xdp(struct net_device *dev, struct netdev_bpf *xdp)
4114 {
4115         switch (xdp->command) {
4116         case XDP_SETUP_PROG:
4117                 return mlx5e_xdp_set(dev, xdp->prog);
4118         case XDP_SETUP_XSK_POOL:
4119                 return mlx5e_xsk_setup_pool(dev, xdp->xsk.pool,
4120                                             xdp->xsk.queue_id);
4121         default:
4122                 return -EINVAL;
4123         }
4124 }
4125
4126 #ifdef CONFIG_MLX5_ESWITCH
4127 static int mlx5e_bridge_getlink(struct sk_buff *skb, u32 pid, u32 seq,
4128                                 struct net_device *dev, u32 filter_mask,
4129                                 int nlflags)
4130 {
4131         struct mlx5e_priv *priv = netdev_priv(dev);
4132         struct mlx5_core_dev *mdev = priv->mdev;
4133         u8 mode, setting;
4134         int err;
4135
4136         err = mlx5_eswitch_get_vepa(mdev->priv.eswitch, &setting);
4137         if (err)
4138                 return err;
4139         mode = setting ? BRIDGE_MODE_VEPA : BRIDGE_MODE_VEB;
4140         return ndo_dflt_bridge_getlink(skb, pid, seq, dev,
4141                                        mode,
4142                                        0, 0, nlflags, filter_mask, NULL);
4143 }
4144
4145 static int mlx5e_bridge_setlink(struct net_device *dev, struct nlmsghdr *nlh,
4146                                 u16 flags, struct netlink_ext_ack *extack)
4147 {
4148         struct mlx5e_priv *priv = netdev_priv(dev);
4149         struct mlx5_core_dev *mdev = priv->mdev;
4150         struct nlattr *attr, *br_spec;
4151         u16 mode = BRIDGE_MODE_UNDEF;
4152         u8 setting;
4153         int rem;
4154
4155         br_spec = nlmsg_find_attr(nlh, sizeof(struct ifinfomsg), IFLA_AF_SPEC);
4156         if (!br_spec)
4157                 return -EINVAL;
4158
4159         nla_for_each_nested(attr, br_spec, rem) {
4160                 if (nla_type(attr) != IFLA_BRIDGE_MODE)
4161                         continue;
4162
4163                 if (nla_len(attr) < sizeof(mode))
4164                         return -EINVAL;
4165
4166                 mode = nla_get_u16(attr);
4167                 if (mode > BRIDGE_MODE_VEPA)
4168                         return -EINVAL;
4169
4170                 break;
4171         }
4172
4173         if (mode == BRIDGE_MODE_UNDEF)
4174                 return -EINVAL;
4175
4176         setting = (mode == BRIDGE_MODE_VEPA) ?  1 : 0;
4177         return mlx5_eswitch_set_vepa(mdev->priv.eswitch, setting);
4178 }
4179 #endif
4180
4181 const struct net_device_ops mlx5e_netdev_ops = {
4182         .ndo_open                = mlx5e_open,
4183         .ndo_stop                = mlx5e_close,
4184         .ndo_start_xmit          = mlx5e_xmit,
4185         .ndo_setup_tc            = mlx5e_setup_tc,
4186         .ndo_select_queue        = mlx5e_select_queue,
4187         .ndo_get_stats64         = mlx5e_get_stats,
4188         .ndo_set_rx_mode         = mlx5e_set_rx_mode,
4189         .ndo_set_mac_address     = mlx5e_set_mac,
4190         .ndo_vlan_rx_add_vid     = mlx5e_vlan_rx_add_vid,
4191         .ndo_vlan_rx_kill_vid    = mlx5e_vlan_rx_kill_vid,
4192         .ndo_set_features        = mlx5e_set_features,
4193         .ndo_fix_features        = mlx5e_fix_features,
4194         .ndo_change_mtu          = mlx5e_change_nic_mtu,
4195         .ndo_eth_ioctl            = mlx5e_ioctl,
4196         .ndo_set_tx_maxrate      = mlx5e_set_tx_maxrate,
4197         .ndo_features_check      = mlx5e_features_check,
4198         .ndo_tx_timeout          = mlx5e_tx_timeout,
4199         .ndo_bpf                 = mlx5e_xdp,
4200         .ndo_xdp_xmit            = mlx5e_xdp_xmit,
4201         .ndo_xsk_wakeup          = mlx5e_xsk_wakeup,
4202 #ifdef CONFIG_MLX5_EN_ARFS
4203         .ndo_rx_flow_steer       = mlx5e_rx_flow_steer,
4204 #endif
4205 #ifdef CONFIG_MLX5_ESWITCH
4206         .ndo_bridge_setlink      = mlx5e_bridge_setlink,
4207         .ndo_bridge_getlink      = mlx5e_bridge_getlink,
4208
4209         /* SRIOV E-Switch NDOs */
4210         .ndo_set_vf_mac          = mlx5e_set_vf_mac,
4211         .ndo_set_vf_vlan         = mlx5e_set_vf_vlan,
4212         .ndo_set_vf_spoofchk     = mlx5e_set_vf_spoofchk,
4213         .ndo_set_vf_trust        = mlx5e_set_vf_trust,
4214         .ndo_set_vf_rate         = mlx5e_set_vf_rate,
4215         .ndo_get_vf_config       = mlx5e_get_vf_config,
4216         .ndo_set_vf_link_state   = mlx5e_set_vf_link_state,
4217         .ndo_get_vf_stats        = mlx5e_get_vf_stats,
4218         .ndo_has_offload_stats   = mlx5e_has_offload_stats,
4219         .ndo_get_offload_stats   = mlx5e_get_offload_stats,
4220 #endif
4221         .ndo_get_devlink_port    = mlx5e_get_devlink_port,
4222 };
4223
4224 static u32 mlx5e_choose_lro_timeout(struct mlx5_core_dev *mdev, u32 wanted_timeout)
4225 {
4226         int i;
4227
4228         /* The supported periods are organized in ascending order */
4229         for (i = 0; i < MLX5E_LRO_TIMEOUT_ARR_SIZE - 1; i++)
4230                 if (MLX5_CAP_ETH(mdev, lro_timer_supported_periods[i]) >= wanted_timeout)
4231                         break;
4232
4233         return MLX5_CAP_ETH(mdev, lro_timer_supported_periods[i]);
4234 }
4235
4236 void mlx5e_build_nic_params(struct mlx5e_priv *priv, struct mlx5e_xsk *xsk, u16 mtu)
4237 {
4238         struct mlx5e_params *params = &priv->channels.params;
4239         struct mlx5_core_dev *mdev = priv->mdev;
4240         u8 rx_cq_period_mode;
4241
4242         params->sw_mtu = mtu;
4243         params->hard_mtu = MLX5E_ETH_HARD_MTU;
4244         params->num_channels = min_t(unsigned int, MLX5E_MAX_NUM_CHANNELS / 2,
4245                                      priv->max_nch);
4246         mlx5e_params_mqprio_reset(params);
4247
4248         /* Set an initial non-zero value, so that mlx5e_select_queue won't
4249          * divide by zero if called before first activating channels.
4250          */
4251         priv->num_tc_x_num_ch = params->num_channels * params->mqprio.num_tc;
4252
4253         /* SQ */
4254         params->log_sq_size = is_kdump_kernel() ?
4255                 MLX5E_PARAMS_MINIMUM_LOG_SQ_SIZE :
4256                 MLX5E_PARAMS_DEFAULT_LOG_SQ_SIZE;
4257         MLX5E_SET_PFLAG(params, MLX5E_PFLAG_SKB_TX_MPWQE, mlx5e_tx_mpwqe_supported(mdev));
4258
4259         /* XDP SQ */
4260         MLX5E_SET_PFLAG(params, MLX5E_PFLAG_XDP_TX_MPWQE, mlx5e_tx_mpwqe_supported(mdev));
4261
4262         /* set CQE compression */
4263         params->rx_cqe_compress_def = false;
4264         if (MLX5_CAP_GEN(mdev, cqe_compression) &&
4265             MLX5_CAP_GEN(mdev, vport_group_manager))
4266                 params->rx_cqe_compress_def = slow_pci_heuristic(mdev);
4267
4268         MLX5E_SET_PFLAG(params, MLX5E_PFLAG_RX_CQE_COMPRESS, params->rx_cqe_compress_def);
4269         MLX5E_SET_PFLAG(params, MLX5E_PFLAG_RX_NO_CSUM_COMPLETE, false);
4270
4271         /* RQ */
4272         mlx5e_build_rq_params(mdev, params);
4273
4274         /* HW LRO */
4275         if (MLX5_CAP_ETH(mdev, lro_cap) &&
4276             params->rq_wq_type == MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ) {
4277                 /* No XSK params: checking the availability of striding RQ in general. */
4278                 if (!mlx5e_rx_mpwqe_is_linear_skb(mdev, params, NULL))
4279                         params->lro_en = !slow_pci_heuristic(mdev);
4280         }
4281         params->lro_timeout = mlx5e_choose_lro_timeout(mdev, MLX5E_DEFAULT_LRO_TIMEOUT);
4282
4283         /* CQ moderation params */
4284         rx_cq_period_mode = MLX5_CAP_GEN(mdev, cq_period_start_from_cqe) ?
4285                         MLX5_CQ_PERIOD_MODE_START_FROM_CQE :
4286                         MLX5_CQ_PERIOD_MODE_START_FROM_EQE;
4287         params->rx_dim_enabled = MLX5_CAP_GEN(mdev, cq_moderation);
4288         params->tx_dim_enabled = MLX5_CAP_GEN(mdev, cq_moderation);
4289         mlx5e_set_rx_cq_mode_params(params, rx_cq_period_mode);
4290         mlx5e_set_tx_cq_mode_params(params, MLX5_CQ_PERIOD_MODE_START_FROM_EQE);
4291
4292         /* TX inline */
4293         mlx5_query_min_inline(mdev, &params->tx_min_inline_mode);
4294
4295         params->tunneled_offload_en = mlx5_tunnel_inner_ft_supported(mdev);
4296
4297         /* AF_XDP */
4298         params->xsk = xsk;
4299
4300         /* Do not update netdev->features directly in here
4301          * on mlx5e_attach_netdev() we will call mlx5e_update_features()
4302          * To update netdev->features please modify mlx5e_fix_features()
4303          */
4304 }
4305
4306 static void mlx5e_set_netdev_dev_addr(struct net_device *netdev)
4307 {
4308         struct mlx5e_priv *priv = netdev_priv(netdev);
4309
4310         mlx5_query_mac_address(priv->mdev, netdev->dev_addr);
4311         if (is_zero_ether_addr(netdev->dev_addr) &&
4312             !MLX5_CAP_GEN(priv->mdev, vport_group_manager)) {
4313                 eth_hw_addr_random(netdev);
4314                 mlx5_core_info(priv->mdev, "Assigned random MAC address %pM\n", netdev->dev_addr);
4315         }
4316 }
4317
4318 static int mlx5e_vxlan_set_port(struct net_device *netdev, unsigned int table,
4319                                 unsigned int entry, struct udp_tunnel_info *ti)
4320 {
4321         struct mlx5e_priv *priv = netdev_priv(netdev);
4322
4323         return mlx5_vxlan_add_port(priv->mdev->vxlan, ntohs(ti->port));
4324 }
4325
4326 static int mlx5e_vxlan_unset_port(struct net_device *netdev, unsigned int table,
4327                                   unsigned int entry, struct udp_tunnel_info *ti)
4328 {
4329         struct mlx5e_priv *priv = netdev_priv(netdev);
4330
4331         return mlx5_vxlan_del_port(priv->mdev->vxlan, ntohs(ti->port));
4332 }
4333
4334 void mlx5e_vxlan_set_netdev_info(struct mlx5e_priv *priv)
4335 {
4336         if (!mlx5_vxlan_allowed(priv->mdev->vxlan))
4337                 return;
4338
4339         priv->nic_info.set_port = mlx5e_vxlan_set_port;
4340         priv->nic_info.unset_port = mlx5e_vxlan_unset_port;
4341         priv->nic_info.flags = UDP_TUNNEL_NIC_INFO_MAY_SLEEP |
4342                                 UDP_TUNNEL_NIC_INFO_STATIC_IANA_VXLAN;
4343         priv->nic_info.tables[0].tunnel_types = UDP_TUNNEL_TYPE_VXLAN;
4344         /* Don't count the space hard-coded to the IANA port */
4345         priv->nic_info.tables[0].n_entries =
4346                 mlx5_vxlan_max_udp_ports(priv->mdev) - 1;
4347
4348         priv->netdev->udp_tunnel_nic_info = &priv->nic_info;
4349 }
4350
4351 static bool mlx5e_tunnel_any_tx_proto_supported(struct mlx5_core_dev *mdev)
4352 {
4353         int tt;
4354
4355         for (tt = 0; tt < MLX5_NUM_TUNNEL_TT; tt++) {
4356                 if (mlx5e_tunnel_proto_supported_tx(mdev, mlx5_get_proto_by_tunnel_type(tt)))
4357                         return true;
4358         }
4359         return (mlx5_vxlan_allowed(mdev->vxlan) || mlx5_geneve_tx_allowed(mdev));
4360 }
4361
4362 static void mlx5e_build_nic_netdev(struct net_device *netdev)
4363 {
4364         struct mlx5e_priv *priv = netdev_priv(netdev);
4365         struct mlx5_core_dev *mdev = priv->mdev;
4366         bool fcs_supported;
4367         bool fcs_enabled;
4368
4369         SET_NETDEV_DEV(netdev, mdev->device);
4370
4371         netdev->netdev_ops = &mlx5e_netdev_ops;
4372
4373         mlx5e_dcbnl_build_netdev(netdev);
4374
4375         netdev->watchdog_timeo    = 15 * HZ;
4376
4377         netdev->ethtool_ops       = &mlx5e_ethtool_ops;
4378
4379         netdev->vlan_features    |= NETIF_F_SG;
4380         netdev->vlan_features    |= NETIF_F_HW_CSUM;
4381         netdev->vlan_features    |= NETIF_F_GRO;
4382         netdev->vlan_features    |= NETIF_F_TSO;
4383         netdev->vlan_features    |= NETIF_F_TSO6;
4384         netdev->vlan_features    |= NETIF_F_RXCSUM;
4385         netdev->vlan_features    |= NETIF_F_RXHASH;
4386
4387         netdev->mpls_features    |= NETIF_F_SG;
4388         netdev->mpls_features    |= NETIF_F_HW_CSUM;
4389         netdev->mpls_features    |= NETIF_F_TSO;
4390         netdev->mpls_features    |= NETIF_F_TSO6;
4391
4392         netdev->hw_enc_features  |= NETIF_F_HW_VLAN_CTAG_TX;
4393         netdev->hw_enc_features  |= NETIF_F_HW_VLAN_CTAG_RX;
4394
4395         /* Tunneled LRO is not supported in the driver, and the same RQs are
4396          * shared between inner and outer TIRs, so the driver can't disable LRO
4397          * for inner TIRs while having it enabled for outer TIRs. Due to this,
4398          * block LRO altogether if the firmware declares tunneled LRO support.
4399          */
4400         if (!!MLX5_CAP_ETH(mdev, lro_cap) &&
4401             !MLX5_CAP_ETH(mdev, tunnel_lro_vxlan) &&
4402             !MLX5_CAP_ETH(mdev, tunnel_lro_gre) &&
4403             mlx5e_check_fragmented_striding_rq_cap(mdev))
4404                 netdev->vlan_features    |= NETIF_F_LRO;
4405
4406         netdev->hw_features       = netdev->vlan_features;
4407         netdev->hw_features      |= NETIF_F_HW_VLAN_CTAG_TX;
4408         netdev->hw_features      |= NETIF_F_HW_VLAN_CTAG_RX;
4409         netdev->hw_features      |= NETIF_F_HW_VLAN_CTAG_FILTER;
4410         netdev->hw_features      |= NETIF_F_HW_VLAN_STAG_TX;
4411
4412         if (mlx5e_tunnel_any_tx_proto_supported(mdev)) {
4413                 netdev->hw_enc_features |= NETIF_F_HW_CSUM;
4414                 netdev->hw_enc_features |= NETIF_F_TSO;
4415                 netdev->hw_enc_features |= NETIF_F_TSO6;
4416                 netdev->hw_enc_features |= NETIF_F_GSO_PARTIAL;
4417         }
4418
4419         if (mlx5_vxlan_allowed(mdev->vxlan) || mlx5_geneve_tx_allowed(mdev)) {
4420                 netdev->hw_features     |= NETIF_F_GSO_UDP_TUNNEL;
4421                 netdev->hw_enc_features |= NETIF_F_GSO_UDP_TUNNEL;
4422                 netdev->vlan_features |= NETIF_F_GSO_UDP_TUNNEL;
4423         }
4424
4425         if (mlx5e_tunnel_proto_supported_tx(mdev, IPPROTO_GRE)) {
4426                 netdev->hw_features     |= NETIF_F_GSO_GRE;
4427                 netdev->hw_enc_features |= NETIF_F_GSO_GRE;
4428                 netdev->gso_partial_features |= NETIF_F_GSO_GRE;
4429         }
4430
4431         if (mlx5e_tunnel_proto_supported_tx(mdev, IPPROTO_IPIP)) {
4432                 netdev->hw_features |= NETIF_F_GSO_IPXIP4 |
4433                                        NETIF_F_GSO_IPXIP6;
4434                 netdev->hw_enc_features |= NETIF_F_GSO_IPXIP4 |
4435                                            NETIF_F_GSO_IPXIP6;
4436                 netdev->gso_partial_features |= NETIF_F_GSO_IPXIP4 |
4437                                                 NETIF_F_GSO_IPXIP6;
4438         }
4439
4440         netdev->hw_features                      |= NETIF_F_GSO_PARTIAL;
4441         netdev->gso_partial_features             |= NETIF_F_GSO_UDP_L4;
4442         netdev->hw_features                      |= NETIF_F_GSO_UDP_L4;
4443         netdev->features                         |= NETIF_F_GSO_UDP_L4;
4444
4445         mlx5_query_port_fcs(mdev, &fcs_supported, &fcs_enabled);
4446
4447         if (fcs_supported)
4448                 netdev->hw_features |= NETIF_F_RXALL;
4449
4450         if (MLX5_CAP_ETH(mdev, scatter_fcs))
4451                 netdev->hw_features |= NETIF_F_RXFCS;
4452
4453         if (mlx5_qos_is_supported(mdev))
4454                 netdev->hw_features |= NETIF_F_HW_TC;
4455
4456         netdev->features          = netdev->hw_features;
4457
4458         /* Defaults */
4459         if (fcs_enabled)
4460                 netdev->features  &= ~NETIF_F_RXALL;
4461         netdev->features  &= ~NETIF_F_LRO;
4462         netdev->features  &= ~NETIF_F_RXFCS;
4463
4464 #define FT_CAP(f) MLX5_CAP_FLOWTABLE(mdev, flow_table_properties_nic_receive.f)
4465         if (FT_CAP(flow_modify_en) &&
4466             FT_CAP(modify_root) &&
4467             FT_CAP(identified_miss_table_mode) &&
4468             FT_CAP(flow_table_modify)) {
4469 #if IS_ENABLED(CONFIG_MLX5_CLS_ACT)
4470                 netdev->hw_features      |= NETIF_F_HW_TC;
4471 #endif
4472 #ifdef CONFIG_MLX5_EN_ARFS
4473                 netdev->hw_features      |= NETIF_F_NTUPLE;
4474 #endif
4475         }
4476
4477         netdev->features         |= NETIF_F_HIGHDMA;
4478         netdev->features         |= NETIF_F_HW_VLAN_STAG_FILTER;
4479
4480         netdev->priv_flags       |= IFF_UNICAST_FLT;
4481
4482         mlx5e_set_netdev_dev_addr(netdev);
4483         mlx5e_ipsec_build_netdev(priv);
4484         mlx5e_tls_build_netdev(priv);
4485 }
4486
4487 void mlx5e_create_q_counters(struct mlx5e_priv *priv)
4488 {
4489         u32 out[MLX5_ST_SZ_DW(alloc_q_counter_out)] = {};
4490         u32 in[MLX5_ST_SZ_DW(alloc_q_counter_in)] = {};
4491         struct mlx5_core_dev *mdev = priv->mdev;
4492         int err;
4493
4494         MLX5_SET(alloc_q_counter_in, in, opcode, MLX5_CMD_OP_ALLOC_Q_COUNTER);
4495         err = mlx5_cmd_exec_inout(mdev, alloc_q_counter, in, out);
4496         if (!err)
4497                 priv->q_counter =
4498                         MLX5_GET(alloc_q_counter_out, out, counter_set_id);
4499
4500         err = mlx5_cmd_exec_inout(mdev, alloc_q_counter, in, out);
4501         if (!err)
4502                 priv->drop_rq_q_counter =
4503                         MLX5_GET(alloc_q_counter_out, out, counter_set_id);
4504 }
4505
4506 void mlx5e_destroy_q_counters(struct mlx5e_priv *priv)
4507 {
4508         u32 in[MLX5_ST_SZ_DW(dealloc_q_counter_in)] = {};
4509
4510         MLX5_SET(dealloc_q_counter_in, in, opcode,
4511                  MLX5_CMD_OP_DEALLOC_Q_COUNTER);
4512         if (priv->q_counter) {
4513                 MLX5_SET(dealloc_q_counter_in, in, counter_set_id,
4514                          priv->q_counter);
4515                 mlx5_cmd_exec_in(priv->mdev, dealloc_q_counter, in);
4516         }
4517
4518         if (priv->drop_rq_q_counter) {
4519                 MLX5_SET(dealloc_q_counter_in, in, counter_set_id,
4520                          priv->drop_rq_q_counter);
4521                 mlx5_cmd_exec_in(priv->mdev, dealloc_q_counter, in);
4522         }
4523 }
4524
4525 static int mlx5e_nic_init(struct mlx5_core_dev *mdev,
4526                           struct net_device *netdev)
4527 {
4528         struct mlx5e_priv *priv = netdev_priv(netdev);
4529         int err;
4530
4531         mlx5e_build_nic_params(priv, &priv->xsk, netdev->mtu);
4532         mlx5e_vxlan_set_netdev_info(priv);
4533
4534         mlx5e_timestamp_init(priv);
4535
4536         err = mlx5e_ipsec_init(priv);
4537         if (err)
4538                 mlx5_core_err(mdev, "IPSec initialization failed, %d\n", err);
4539
4540         err = mlx5e_tls_init(priv);
4541         if (err)
4542                 mlx5_core_err(mdev, "TLS initialization failed, %d\n", err);
4543
4544         mlx5e_health_create_reporters(priv);
4545         return 0;
4546 }
4547
4548 static void mlx5e_nic_cleanup(struct mlx5e_priv *priv)
4549 {
4550         mlx5e_health_destroy_reporters(priv);
4551         mlx5e_tls_cleanup(priv);
4552         mlx5e_ipsec_cleanup(priv);
4553 }
4554
4555 static int mlx5e_init_nic_rx(struct mlx5e_priv *priv)
4556 {
4557         struct mlx5_core_dev *mdev = priv->mdev;
4558         enum mlx5e_rx_res_features features;
4559         struct mlx5e_lro_param lro_param;
4560         int err;
4561
4562         priv->rx_res = mlx5e_rx_res_alloc();
4563         if (!priv->rx_res)
4564                 return -ENOMEM;
4565
4566         mlx5e_create_q_counters(priv);
4567
4568         err = mlx5e_open_drop_rq(priv, &priv->drop_rq);
4569         if (err) {
4570                 mlx5_core_err(mdev, "open drop rq failed, %d\n", err);
4571                 goto err_destroy_q_counters;
4572         }
4573
4574         features = MLX5E_RX_RES_FEATURE_XSK | MLX5E_RX_RES_FEATURE_PTP;
4575         if (priv->channels.params.tunneled_offload_en)
4576                 features |= MLX5E_RX_RES_FEATURE_INNER_FT;
4577         lro_param = mlx5e_get_lro_param(&priv->channels.params);
4578         err = mlx5e_rx_res_init(priv->rx_res, priv->mdev, features,
4579                                 priv->max_nch, priv->drop_rq.rqn, &lro_param,
4580                                 priv->channels.params.num_channels);
4581         if (err)
4582                 goto err_close_drop_rq;
4583
4584         err = mlx5e_create_flow_steering(priv);
4585         if (err) {
4586                 mlx5_core_warn(mdev, "create flow steering failed, %d\n", err);
4587                 goto err_destroy_rx_res;
4588         }
4589
4590         err = mlx5e_tc_nic_init(priv);
4591         if (err)
4592                 goto err_destroy_flow_steering;
4593
4594         err = mlx5e_accel_init_rx(priv);
4595         if (err)
4596                 goto err_tc_nic_cleanup;
4597
4598 #ifdef CONFIG_MLX5_EN_ARFS
4599         priv->netdev->rx_cpu_rmap =  mlx5_eq_table_get_rmap(priv->mdev);
4600 #endif
4601
4602         return 0;
4603
4604 err_tc_nic_cleanup:
4605         mlx5e_tc_nic_cleanup(priv);
4606 err_destroy_flow_steering:
4607         mlx5e_destroy_flow_steering(priv);
4608 err_destroy_rx_res:
4609         mlx5e_rx_res_destroy(priv->rx_res);
4610 err_close_drop_rq:
4611         mlx5e_close_drop_rq(&priv->drop_rq);
4612 err_destroy_q_counters:
4613         mlx5e_destroy_q_counters(priv);
4614         mlx5e_rx_res_free(priv->rx_res);
4615         priv->rx_res = NULL;
4616         return err;
4617 }
4618
4619 static void mlx5e_cleanup_nic_rx(struct mlx5e_priv *priv)
4620 {
4621         mlx5e_accel_cleanup_rx(priv);
4622         mlx5e_tc_nic_cleanup(priv);
4623         mlx5e_destroy_flow_steering(priv);
4624         mlx5e_rx_res_destroy(priv->rx_res);
4625         mlx5e_close_drop_rq(&priv->drop_rq);
4626         mlx5e_destroy_q_counters(priv);
4627         mlx5e_rx_res_free(priv->rx_res);
4628         priv->rx_res = NULL;
4629 }
4630
4631 static int mlx5e_init_nic_tx(struct mlx5e_priv *priv)
4632 {
4633         int err;
4634
4635         err = mlx5e_create_tises(priv);
4636         if (err) {
4637                 mlx5_core_warn(priv->mdev, "create tises failed, %d\n", err);
4638                 return err;
4639         }
4640
4641         mlx5e_dcbnl_initialize(priv);
4642         return 0;
4643 }
4644
4645 static void mlx5e_nic_enable(struct mlx5e_priv *priv)
4646 {
4647         struct net_device *netdev = priv->netdev;
4648         struct mlx5_core_dev *mdev = priv->mdev;
4649
4650         mlx5e_init_l2_addr(priv);
4651
4652         /* Marking the link as currently not needed by the Driver */
4653         if (!netif_running(netdev))
4654                 mlx5e_modify_admin_state(mdev, MLX5_PORT_DOWN);
4655
4656         mlx5e_set_netdev_mtu_boundaries(priv);
4657         mlx5e_set_dev_port_mtu(priv);
4658
4659         mlx5_lag_add_netdev(mdev, netdev);
4660
4661         mlx5e_enable_async_events(priv);
4662         mlx5e_enable_blocking_events(priv);
4663         if (mlx5e_monitor_counter_supported(priv))
4664                 mlx5e_monitor_counter_init(priv);
4665
4666         mlx5e_hv_vhca_stats_create(priv);
4667         if (netdev->reg_state != NETREG_REGISTERED)
4668                 return;
4669         mlx5e_dcbnl_init_app(priv);
4670
4671         mlx5e_nic_set_rx_mode(priv);
4672
4673         rtnl_lock();
4674         if (netif_running(netdev))
4675                 mlx5e_open(netdev);
4676         udp_tunnel_nic_reset_ntf(priv->netdev);
4677         netif_device_attach(netdev);
4678         rtnl_unlock();
4679 }
4680
4681 static void mlx5e_nic_disable(struct mlx5e_priv *priv)
4682 {
4683         struct mlx5_core_dev *mdev = priv->mdev;
4684
4685         if (priv->netdev->reg_state == NETREG_REGISTERED)
4686                 mlx5e_dcbnl_delete_app(priv);
4687
4688         rtnl_lock();
4689         if (netif_running(priv->netdev))
4690                 mlx5e_close(priv->netdev);
4691         netif_device_detach(priv->netdev);
4692         rtnl_unlock();
4693
4694         mlx5e_nic_set_rx_mode(priv);
4695
4696         mlx5e_hv_vhca_stats_destroy(priv);
4697         if (mlx5e_monitor_counter_supported(priv))
4698                 mlx5e_monitor_counter_cleanup(priv);
4699
4700         mlx5e_disable_blocking_events(priv);
4701         if (priv->en_trap) {
4702                 mlx5e_deactivate_trap(priv);
4703                 mlx5e_close_trap(priv->en_trap);
4704                 priv->en_trap = NULL;
4705         }
4706         mlx5e_disable_async_events(priv);
4707         mlx5_lag_remove_netdev(mdev, priv->netdev);
4708         mlx5_vxlan_reset_to_default(mdev->vxlan);
4709 }
4710
4711 int mlx5e_update_nic_rx(struct mlx5e_priv *priv)
4712 {
4713         return mlx5e_refresh_tirs(priv, false, false);
4714 }
4715
4716 static const struct mlx5e_profile mlx5e_nic_profile = {
4717         .init              = mlx5e_nic_init,
4718         .cleanup           = mlx5e_nic_cleanup,
4719         .init_rx           = mlx5e_init_nic_rx,
4720         .cleanup_rx        = mlx5e_cleanup_nic_rx,
4721         .init_tx           = mlx5e_init_nic_tx,
4722         .cleanup_tx        = mlx5e_cleanup_nic_tx,
4723         .enable            = mlx5e_nic_enable,
4724         .disable           = mlx5e_nic_disable,
4725         .update_rx         = mlx5e_update_nic_rx,
4726         .update_stats      = mlx5e_stats_update_ndo_stats,
4727         .update_carrier    = mlx5e_update_carrier,
4728         .rx_handlers       = &mlx5e_rx_handlers_nic,
4729         .max_tc            = MLX5E_MAX_NUM_TC,
4730         .rq_groups         = MLX5E_NUM_RQ_GROUPS(XSK),
4731         .stats_grps        = mlx5e_nic_stats_grps,
4732         .stats_grps_num    = mlx5e_nic_stats_grps_num,
4733         .rx_ptp_support    = true,
4734 };
4735
4736 static unsigned int
4737 mlx5e_calc_max_nch(struct mlx5_core_dev *mdev, struct net_device *netdev,
4738                    const struct mlx5e_profile *profile)
4739
4740 {
4741         unsigned int max_nch, tmp;
4742
4743         /* core resources */
4744         max_nch = mlx5e_get_max_num_channels(mdev);
4745
4746         /* netdev rx queues */
4747         tmp = netdev->num_rx_queues / max_t(u8, profile->rq_groups, 1);
4748         max_nch = min_t(unsigned int, max_nch, tmp);
4749
4750         /* netdev tx queues */
4751         tmp = netdev->num_tx_queues;
4752         if (mlx5_qos_is_supported(mdev))
4753                 tmp -= mlx5e_qos_max_leaf_nodes(mdev);
4754         if (MLX5_CAP_GEN(mdev, ts_cqe_to_dest_cqn))
4755                 tmp -= profile->max_tc;
4756         tmp = tmp / profile->max_tc;
4757         max_nch = min_t(unsigned int, max_nch, tmp);
4758
4759         return max_nch;
4760 }
4761
4762 /* mlx5e generic netdev management API (move to en_common.c) */
4763 int mlx5e_priv_init(struct mlx5e_priv *priv,
4764                     const struct mlx5e_profile *profile,
4765                     struct net_device *netdev,
4766                     struct mlx5_core_dev *mdev)
4767 {
4768         /* priv init */
4769         priv->mdev        = mdev;
4770         priv->netdev      = netdev;
4771         priv->msglevel    = MLX5E_MSG_LEVEL;
4772         priv->max_nch     = mlx5e_calc_max_nch(mdev, netdev, profile);
4773         priv->stats_nch   = priv->max_nch;
4774         priv->max_opened_tc = 1;
4775
4776         if (!alloc_cpumask_var(&priv->scratchpad.cpumask, GFP_KERNEL))
4777                 return -ENOMEM;
4778
4779         mutex_init(&priv->state_lock);
4780         hash_init(priv->htb.qos_tc2node);
4781         INIT_WORK(&priv->update_carrier_work, mlx5e_update_carrier_work);
4782         INIT_WORK(&priv->set_rx_mode_work, mlx5e_set_rx_mode_work);
4783         INIT_WORK(&priv->tx_timeout_work, mlx5e_tx_timeout_work);
4784         INIT_WORK(&priv->update_stats_work, mlx5e_update_stats_work);
4785
4786         priv->wq = create_singlethread_workqueue("mlx5e");
4787         if (!priv->wq)
4788                 goto err_free_cpumask;
4789
4790         return 0;
4791
4792 err_free_cpumask:
4793         free_cpumask_var(priv->scratchpad.cpumask);
4794
4795         return -ENOMEM;
4796 }
4797
4798 void mlx5e_priv_cleanup(struct mlx5e_priv *priv)
4799 {
4800         int i;
4801
4802         /* bail if change profile failed and also rollback failed */
4803         if (!priv->mdev)
4804                 return;
4805
4806         destroy_workqueue(priv->wq);
4807         free_cpumask_var(priv->scratchpad.cpumask);
4808
4809         for (i = 0; i < priv->htb.max_qos_sqs; i++)
4810                 kfree(priv->htb.qos_sq_stats[i]);
4811         kvfree(priv->htb.qos_sq_stats);
4812
4813         memset(priv, 0, sizeof(*priv));
4814 }
4815
4816 struct net_device *
4817 mlx5e_create_netdev(struct mlx5_core_dev *mdev, const struct mlx5e_profile *profile,
4818                     unsigned int txqs, unsigned int rxqs)
4819 {
4820         struct net_device *netdev;
4821         int err;
4822
4823         netdev = alloc_etherdev_mqs(sizeof(struct mlx5e_priv), txqs, rxqs);
4824         if (!netdev) {
4825                 mlx5_core_err(mdev, "alloc_etherdev_mqs() failed\n");
4826                 return NULL;
4827         }
4828
4829         err = mlx5e_priv_init(netdev_priv(netdev), profile, netdev, mdev);
4830         if (err) {
4831                 mlx5_core_err(mdev, "mlx5e_priv_init failed, err=%d\n", err);
4832                 goto err_free_netdev;
4833         }
4834
4835         netif_carrier_off(netdev);
4836         dev_net_set(netdev, mlx5_core_net(mdev));
4837
4838         return netdev;
4839
4840 err_free_netdev:
4841         free_netdev(netdev);
4842
4843         return NULL;
4844 }
4845
4846 static void mlx5e_update_features(struct net_device *netdev)
4847 {
4848         if (netdev->reg_state != NETREG_REGISTERED)
4849                 return; /* features will be updated on netdev registration */
4850
4851         rtnl_lock();
4852         netdev_update_features(netdev);
4853         rtnl_unlock();
4854 }
4855
4856 static void mlx5e_reset_channels(struct net_device *netdev)
4857 {
4858         netdev_reset_tc(netdev);
4859 }
4860
4861 int mlx5e_attach_netdev(struct mlx5e_priv *priv)
4862 {
4863         const bool take_rtnl = priv->netdev->reg_state == NETREG_REGISTERED;
4864         const struct mlx5e_profile *profile = priv->profile;
4865         int max_nch;
4866         int err;
4867
4868         clear_bit(MLX5E_STATE_DESTROYING, &priv->state);
4869
4870         /* max number of channels may have changed */
4871         max_nch = mlx5e_calc_max_nch(priv->mdev, priv->netdev, profile);
4872         if (priv->channels.params.num_channels > max_nch) {
4873                 mlx5_core_warn(priv->mdev, "MLX5E: Reducing number of channels to %d\n", max_nch);
4874                 /* Reducing the number of channels - RXFH has to be reset, and
4875                  * mlx5e_num_channels_changed below will build the RQT.
4876                  */
4877                 priv->netdev->priv_flags &= ~IFF_RXFH_CONFIGURED;
4878                 priv->channels.params.num_channels = max_nch;
4879                 if (priv->channels.params.mqprio.mode == TC_MQPRIO_MODE_CHANNEL) {
4880                         mlx5_core_warn(priv->mdev, "MLX5E: Disabling MQPRIO channel mode\n");
4881                         mlx5e_params_mqprio_reset(&priv->channels.params);
4882                 }
4883         }
4884         if (max_nch != priv->max_nch) {
4885                 mlx5_core_warn(priv->mdev,
4886                                "MLX5E: Updating max number of channels from %u to %u\n",
4887                                priv->max_nch, max_nch);
4888                 priv->max_nch = max_nch;
4889         }
4890
4891         /* 1. Set the real number of queues in the kernel the first time.
4892          * 2. Set our default XPS cpumask.
4893          * 3. Build the RQT.
4894          *
4895          * rtnl_lock is required by netif_set_real_num_*_queues in case the
4896          * netdev has been registered by this point (if this function was called
4897          * in the reload or resume flow).
4898          */
4899         if (take_rtnl)
4900                 rtnl_lock();
4901         err = mlx5e_num_channels_changed(priv);
4902         if (take_rtnl)
4903                 rtnl_unlock();
4904         if (err)
4905                 goto out;
4906
4907         err = profile->init_tx(priv);
4908         if (err)
4909                 goto out;
4910
4911         err = profile->init_rx(priv);
4912         if (err)
4913                 goto err_cleanup_tx;
4914
4915         if (profile->enable)
4916                 profile->enable(priv);
4917
4918         mlx5e_update_features(priv->netdev);
4919
4920         return 0;
4921
4922 err_cleanup_tx:
4923         profile->cleanup_tx(priv);
4924
4925 out:
4926         mlx5e_reset_channels(priv->netdev);
4927         set_bit(MLX5E_STATE_DESTROYING, &priv->state);
4928         cancel_work_sync(&priv->update_stats_work);
4929         return err;
4930 }
4931
4932 void mlx5e_detach_netdev(struct mlx5e_priv *priv)
4933 {
4934         const struct mlx5e_profile *profile = priv->profile;
4935
4936         set_bit(MLX5E_STATE_DESTROYING, &priv->state);
4937
4938         if (profile->disable)
4939                 profile->disable(priv);
4940         flush_workqueue(priv->wq);
4941
4942         profile->cleanup_rx(priv);
4943         profile->cleanup_tx(priv);
4944         mlx5e_reset_channels(priv->netdev);
4945         cancel_work_sync(&priv->update_stats_work);
4946 }
4947
4948 static int
4949 mlx5e_netdev_attach_profile(struct net_device *netdev, struct mlx5_core_dev *mdev,
4950                             const struct mlx5e_profile *new_profile, void *new_ppriv)
4951 {
4952         struct mlx5e_priv *priv = netdev_priv(netdev);
4953         int err;
4954
4955         err = mlx5e_priv_init(priv, new_profile, netdev, mdev);
4956         if (err) {
4957                 mlx5_core_err(mdev, "mlx5e_priv_init failed, err=%d\n", err);
4958                 return err;
4959         }
4960         netif_carrier_off(netdev);
4961         priv->profile = new_profile;
4962         priv->ppriv = new_ppriv;
4963         err = new_profile->init(priv->mdev, priv->netdev);
4964         if (err)
4965                 goto priv_cleanup;
4966         err = mlx5e_attach_netdev(priv);
4967         if (err)
4968                 goto profile_cleanup;
4969         return err;
4970
4971 profile_cleanup:
4972         new_profile->cleanup(priv);
4973 priv_cleanup:
4974         mlx5e_priv_cleanup(priv);
4975         return err;
4976 }
4977
4978 int mlx5e_netdev_change_profile(struct mlx5e_priv *priv,
4979                                 const struct mlx5e_profile *new_profile, void *new_ppriv)
4980 {
4981         const struct mlx5e_profile *orig_profile = priv->profile;
4982         struct net_device *netdev = priv->netdev;
4983         struct mlx5_core_dev *mdev = priv->mdev;
4984         void *orig_ppriv = priv->ppriv;
4985         int err, rollback_err;
4986
4987         /* cleanup old profile */
4988         mlx5e_detach_netdev(priv);
4989         priv->profile->cleanup(priv);
4990         mlx5e_priv_cleanup(priv);
4991
4992         err = mlx5e_netdev_attach_profile(netdev, mdev, new_profile, new_ppriv);
4993         if (err) { /* roll back to original profile */
4994                 netdev_warn(netdev, "%s: new profile init failed, %d\n", __func__, err);
4995                 goto rollback;
4996         }
4997
4998         return 0;
4999
5000 rollback:
5001         rollback_err = mlx5e_netdev_attach_profile(netdev, mdev, orig_profile, orig_ppriv);
5002         if (rollback_err)
5003                 netdev_err(netdev, "%s: failed to rollback to orig profile, %d\n",
5004                            __func__, rollback_err);
5005         return err;
5006 }
5007
5008 void mlx5e_netdev_attach_nic_profile(struct mlx5e_priv *priv)
5009 {
5010         mlx5e_netdev_change_profile(priv, &mlx5e_nic_profile, NULL);
5011 }
5012
5013 void mlx5e_destroy_netdev(struct mlx5e_priv *priv)
5014 {
5015         struct net_device *netdev = priv->netdev;
5016
5017         mlx5e_priv_cleanup(priv);
5018         free_netdev(netdev);
5019 }
5020
5021 static int mlx5e_resume(struct auxiliary_device *adev)
5022 {
5023         struct mlx5_adev *edev = container_of(adev, struct mlx5_adev, adev);
5024         struct mlx5e_priv *priv = dev_get_drvdata(&adev->dev);
5025         struct net_device *netdev = priv->netdev;
5026         struct mlx5_core_dev *mdev = edev->mdev;
5027         int err;
5028
5029         if (netif_device_present(netdev))
5030                 return 0;
5031
5032         err = mlx5e_create_mdev_resources(mdev);
5033         if (err)
5034                 return err;
5035
5036         err = mlx5e_attach_netdev(priv);
5037         if (err) {
5038                 mlx5e_destroy_mdev_resources(mdev);
5039                 return err;
5040         }
5041
5042         return 0;
5043 }
5044
5045 static int mlx5e_suspend(struct auxiliary_device *adev, pm_message_t state)
5046 {
5047         struct mlx5e_priv *priv = dev_get_drvdata(&adev->dev);
5048         struct net_device *netdev = priv->netdev;
5049         struct mlx5_core_dev *mdev = priv->mdev;
5050
5051         if (!netif_device_present(netdev))
5052                 return -ENODEV;
5053
5054         mlx5e_detach_netdev(priv);
5055         mlx5e_destroy_mdev_resources(mdev);
5056         return 0;
5057 }
5058
5059 static int mlx5e_probe(struct auxiliary_device *adev,
5060                        const struct auxiliary_device_id *id)
5061 {
5062         struct mlx5_adev *edev = container_of(adev, struct mlx5_adev, adev);
5063         const struct mlx5e_profile *profile = &mlx5e_nic_profile;
5064         struct mlx5_core_dev *mdev = edev->mdev;
5065         struct net_device *netdev;
5066         pm_message_t state = {};
5067         unsigned int txqs, rxqs, ptp_txqs = 0;
5068         struct mlx5e_priv *priv;
5069         int qos_sqs = 0;
5070         int err;
5071         int nch;
5072
5073         if (MLX5_CAP_GEN(mdev, ts_cqe_to_dest_cqn))
5074                 ptp_txqs = profile->max_tc;
5075
5076         if (mlx5_qos_is_supported(mdev))
5077                 qos_sqs = mlx5e_qos_max_leaf_nodes(mdev);
5078
5079         nch = mlx5e_get_max_num_channels(mdev);
5080         txqs = nch * profile->max_tc + ptp_txqs + qos_sqs;
5081         rxqs = nch * profile->rq_groups;
5082         netdev = mlx5e_create_netdev(mdev, profile, txqs, rxqs);
5083         if (!netdev) {
5084                 mlx5_core_err(mdev, "mlx5e_create_netdev failed\n");
5085                 return -ENOMEM;
5086         }
5087
5088         mlx5e_build_nic_netdev(netdev);
5089
5090         priv = netdev_priv(netdev);
5091         dev_set_drvdata(&adev->dev, priv);
5092
5093         priv->profile = profile;
5094         priv->ppriv = NULL;
5095
5096         err = mlx5e_devlink_port_register(priv);
5097         if (err) {
5098                 mlx5_core_err(mdev, "mlx5e_devlink_port_register failed, %d\n", err);
5099                 goto err_destroy_netdev;
5100         }
5101
5102         err = profile->init(mdev, netdev);
5103         if (err) {
5104                 mlx5_core_err(mdev, "mlx5e_nic_profile init failed, %d\n", err);
5105                 goto err_devlink_cleanup;
5106         }
5107
5108         err = mlx5e_resume(adev);
5109         if (err) {
5110                 mlx5_core_err(mdev, "mlx5e_resume failed, %d\n", err);
5111                 goto err_profile_cleanup;
5112         }
5113
5114         err = register_netdev(netdev);
5115         if (err) {
5116                 mlx5_core_err(mdev, "register_netdev failed, %d\n", err);
5117                 goto err_resume;
5118         }
5119
5120         mlx5e_devlink_port_type_eth_set(priv);
5121
5122         mlx5e_dcbnl_init_app(priv);
5123         mlx5_uplink_netdev_set(mdev, netdev);
5124         return 0;
5125
5126 err_resume:
5127         mlx5e_suspend(adev, state);
5128 err_profile_cleanup:
5129         profile->cleanup(priv);
5130 err_devlink_cleanup:
5131         mlx5e_devlink_port_unregister(priv);
5132 err_destroy_netdev:
5133         mlx5e_destroy_netdev(priv);
5134         return err;
5135 }
5136
5137 static void mlx5e_remove(struct auxiliary_device *adev)
5138 {
5139         struct mlx5e_priv *priv = dev_get_drvdata(&adev->dev);
5140         pm_message_t state = {};
5141
5142         mlx5e_dcbnl_delete_app(priv);
5143         unregister_netdev(priv->netdev);
5144         mlx5e_suspend(adev, state);
5145         priv->profile->cleanup(priv);
5146         mlx5e_devlink_port_unregister(priv);
5147         mlx5e_destroy_netdev(priv);
5148 }
5149
5150 static const struct auxiliary_device_id mlx5e_id_table[] = {
5151         { .name = MLX5_ADEV_NAME ".eth", },
5152         {},
5153 };
5154
5155 MODULE_DEVICE_TABLE(auxiliary, mlx5e_id_table);
5156
5157 static struct auxiliary_driver mlx5e_driver = {
5158         .name = "eth",
5159         .probe = mlx5e_probe,
5160         .remove = mlx5e_remove,
5161         .suspend = mlx5e_suspend,
5162         .resume = mlx5e_resume,
5163         .id_table = mlx5e_id_table,
5164 };
5165
5166 int mlx5e_init(void)
5167 {
5168         int ret;
5169
5170         mlx5e_ipsec_build_inverse_table();
5171         mlx5e_build_ptys2ethtool_map();
5172         ret = auxiliary_driver_register(&mlx5e_driver);
5173         if (ret)
5174                 return ret;
5175
5176         ret = mlx5e_rep_init();
5177         if (ret)
5178                 auxiliary_driver_unregister(&mlx5e_driver);
5179         return ret;
5180 }
5181
5182 void mlx5e_cleanup(void)
5183 {
5184         mlx5e_rep_cleanup();
5185         auxiliary_driver_unregister(&mlx5e_driver);
5186 }