2 * Copyright (c) 2015, Mellanox Technologies. All rights reserved.
4 * This software is available to you under a choice of one of two
5 * licenses. You may choose to be licensed under the terms of the GNU
6 * General Public License (GPL) Version 2, available from the file
7 * COPYING in the main directory of this source tree, or the
8 * OpenIB.org BSD license below:
10 * Redistribution and use in source and binary forms, with or
11 * without modification, are permitted provided that the following
14 * - Redistributions of source code must retain the above
15 * copyright notice, this list of conditions and the following
18 * - Redistributions in binary form must reproduce the above
19 * copyright notice, this list of conditions and the following
20 * disclaimer in the documentation and/or other materials
21 * provided with the distribution.
23 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
24 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
25 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
26 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
27 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
28 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
29 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
35 #include "en/xsk/umem.h"
36 #include "lib/clock.h"
38 void mlx5e_ethtool_get_drvinfo(struct mlx5e_priv *priv,
39 struct ethtool_drvinfo *drvinfo)
41 struct mlx5_core_dev *mdev = priv->mdev;
43 strlcpy(drvinfo->driver, DRIVER_NAME, sizeof(drvinfo->driver));
44 strlcpy(drvinfo->version, DRIVER_VERSION,
45 sizeof(drvinfo->version));
46 snprintf(drvinfo->fw_version, sizeof(drvinfo->fw_version),
48 fw_rev_maj(mdev), fw_rev_min(mdev), fw_rev_sub(mdev),
50 strlcpy(drvinfo->bus_info, dev_name(mdev->device),
51 sizeof(drvinfo->bus_info));
54 static void mlx5e_get_drvinfo(struct net_device *dev,
55 struct ethtool_drvinfo *drvinfo)
57 struct mlx5e_priv *priv = netdev_priv(dev);
59 mlx5e_ethtool_get_drvinfo(priv, drvinfo);
62 struct ptys2ethtool_config {
63 __ETHTOOL_DECLARE_LINK_MODE_MASK(supported);
64 __ETHTOOL_DECLARE_LINK_MODE_MASK(advertised);
68 struct ptys2ethtool_config ptys2legacy_ethtool_table[MLX5E_LINK_MODES_NUMBER];
70 struct ptys2ethtool_config ptys2ext_ethtool_table[MLX5E_EXT_LINK_MODES_NUMBER];
72 #define MLX5_BUILD_PTYS2ETHTOOL_CONFIG(reg_, table, ...) \
74 struct ptys2ethtool_config *cfg; \
75 const unsigned int modes[] = { __VA_ARGS__ }; \
76 unsigned int i, bit, idx; \
77 cfg = &ptys2##table##_ethtool_table[reg_]; \
78 bitmap_zero(cfg->supported, \
79 __ETHTOOL_LINK_MODE_MASK_NBITS); \
80 bitmap_zero(cfg->advertised, \
81 __ETHTOOL_LINK_MODE_MASK_NBITS); \
82 for (i = 0 ; i < ARRAY_SIZE(modes) ; ++i) { \
83 bit = modes[i] % 64; \
84 idx = modes[i] / 64; \
85 __set_bit(bit, &cfg->supported[idx]); \
86 __set_bit(bit, &cfg->advertised[idx]); \
90 void mlx5e_build_ptys2ethtool_map(void)
92 memset(ptys2legacy_ethtool_table, 0, sizeof(ptys2legacy_ethtool_table));
93 memset(ptys2ext_ethtool_table, 0, sizeof(ptys2ext_ethtool_table));
94 MLX5_BUILD_PTYS2ETHTOOL_CONFIG(MLX5E_1000BASE_CX_SGMII, legacy,
95 ETHTOOL_LINK_MODE_1000baseKX_Full_BIT);
96 MLX5_BUILD_PTYS2ETHTOOL_CONFIG(MLX5E_1000BASE_KX, legacy,
97 ETHTOOL_LINK_MODE_1000baseKX_Full_BIT);
98 MLX5_BUILD_PTYS2ETHTOOL_CONFIG(MLX5E_10GBASE_CX4, legacy,
99 ETHTOOL_LINK_MODE_10000baseKX4_Full_BIT);
100 MLX5_BUILD_PTYS2ETHTOOL_CONFIG(MLX5E_10GBASE_KX4, legacy,
101 ETHTOOL_LINK_MODE_10000baseKX4_Full_BIT);
102 MLX5_BUILD_PTYS2ETHTOOL_CONFIG(MLX5E_10GBASE_KR, legacy,
103 ETHTOOL_LINK_MODE_10000baseKR_Full_BIT);
104 MLX5_BUILD_PTYS2ETHTOOL_CONFIG(MLX5E_20GBASE_KR2, legacy,
105 ETHTOOL_LINK_MODE_20000baseKR2_Full_BIT);
106 MLX5_BUILD_PTYS2ETHTOOL_CONFIG(MLX5E_40GBASE_CR4, legacy,
107 ETHTOOL_LINK_MODE_40000baseCR4_Full_BIT);
108 MLX5_BUILD_PTYS2ETHTOOL_CONFIG(MLX5E_40GBASE_KR4, legacy,
109 ETHTOOL_LINK_MODE_40000baseKR4_Full_BIT);
110 MLX5_BUILD_PTYS2ETHTOOL_CONFIG(MLX5E_56GBASE_R4, legacy,
111 ETHTOOL_LINK_MODE_56000baseKR4_Full_BIT);
112 MLX5_BUILD_PTYS2ETHTOOL_CONFIG(MLX5E_10GBASE_CR, legacy,
113 ETHTOOL_LINK_MODE_10000baseKR_Full_BIT);
114 MLX5_BUILD_PTYS2ETHTOOL_CONFIG(MLX5E_10GBASE_SR, legacy,
115 ETHTOOL_LINK_MODE_10000baseKR_Full_BIT);
116 MLX5_BUILD_PTYS2ETHTOOL_CONFIG(MLX5E_10GBASE_ER, legacy,
117 ETHTOOL_LINK_MODE_10000baseKR_Full_BIT);
118 MLX5_BUILD_PTYS2ETHTOOL_CONFIG(MLX5E_40GBASE_SR4, legacy,
119 ETHTOOL_LINK_MODE_40000baseSR4_Full_BIT);
120 MLX5_BUILD_PTYS2ETHTOOL_CONFIG(MLX5E_40GBASE_LR4, legacy,
121 ETHTOOL_LINK_MODE_40000baseLR4_Full_BIT);
122 MLX5_BUILD_PTYS2ETHTOOL_CONFIG(MLX5E_50GBASE_SR2, legacy,
123 ETHTOOL_LINK_MODE_50000baseSR2_Full_BIT);
124 MLX5_BUILD_PTYS2ETHTOOL_CONFIG(MLX5E_100GBASE_CR4, legacy,
125 ETHTOOL_LINK_MODE_100000baseCR4_Full_BIT);
126 MLX5_BUILD_PTYS2ETHTOOL_CONFIG(MLX5E_100GBASE_SR4, legacy,
127 ETHTOOL_LINK_MODE_100000baseSR4_Full_BIT);
128 MLX5_BUILD_PTYS2ETHTOOL_CONFIG(MLX5E_100GBASE_KR4, legacy,
129 ETHTOOL_LINK_MODE_100000baseKR4_Full_BIT);
130 MLX5_BUILD_PTYS2ETHTOOL_CONFIG(MLX5E_100GBASE_LR4, legacy,
131 ETHTOOL_LINK_MODE_100000baseLR4_ER4_Full_BIT);
132 MLX5_BUILD_PTYS2ETHTOOL_CONFIG(MLX5E_10GBASE_T, legacy,
133 ETHTOOL_LINK_MODE_10000baseT_Full_BIT);
134 MLX5_BUILD_PTYS2ETHTOOL_CONFIG(MLX5E_25GBASE_CR, legacy,
135 ETHTOOL_LINK_MODE_25000baseCR_Full_BIT);
136 MLX5_BUILD_PTYS2ETHTOOL_CONFIG(MLX5E_25GBASE_KR, legacy,
137 ETHTOOL_LINK_MODE_25000baseKR_Full_BIT);
138 MLX5_BUILD_PTYS2ETHTOOL_CONFIG(MLX5E_25GBASE_SR, legacy,
139 ETHTOOL_LINK_MODE_25000baseSR_Full_BIT);
140 MLX5_BUILD_PTYS2ETHTOOL_CONFIG(MLX5E_50GBASE_CR2, legacy,
141 ETHTOOL_LINK_MODE_50000baseCR2_Full_BIT);
142 MLX5_BUILD_PTYS2ETHTOOL_CONFIG(MLX5E_50GBASE_KR2, legacy,
143 ETHTOOL_LINK_MODE_50000baseKR2_Full_BIT);
144 MLX5_BUILD_PTYS2ETHTOOL_CONFIG(MLX5E_SGMII_100M, ext,
145 ETHTOOL_LINK_MODE_100baseT_Full_BIT);
146 MLX5_BUILD_PTYS2ETHTOOL_CONFIG(MLX5E_1000BASE_X_SGMII, ext,
147 ETHTOOL_LINK_MODE_1000baseT_Full_BIT,
148 ETHTOOL_LINK_MODE_1000baseKX_Full_BIT,
149 ETHTOOL_LINK_MODE_1000baseX_Full_BIT);
150 MLX5_BUILD_PTYS2ETHTOOL_CONFIG(MLX5E_5GBASE_R, ext,
151 ETHTOOL_LINK_MODE_5000baseT_Full_BIT);
152 MLX5_BUILD_PTYS2ETHTOOL_CONFIG(MLX5E_10GBASE_XFI_XAUI_1, ext,
153 ETHTOOL_LINK_MODE_10000baseT_Full_BIT,
154 ETHTOOL_LINK_MODE_10000baseKR_Full_BIT,
155 ETHTOOL_LINK_MODE_10000baseR_FEC_BIT,
156 ETHTOOL_LINK_MODE_10000baseCR_Full_BIT,
157 ETHTOOL_LINK_MODE_10000baseSR_Full_BIT,
158 ETHTOOL_LINK_MODE_10000baseLR_Full_BIT,
159 ETHTOOL_LINK_MODE_10000baseER_Full_BIT);
160 MLX5_BUILD_PTYS2ETHTOOL_CONFIG(MLX5E_40GBASE_XLAUI_4_XLPPI_4, ext,
161 ETHTOOL_LINK_MODE_40000baseKR4_Full_BIT,
162 ETHTOOL_LINK_MODE_40000baseCR4_Full_BIT,
163 ETHTOOL_LINK_MODE_40000baseSR4_Full_BIT,
164 ETHTOOL_LINK_MODE_40000baseLR4_Full_BIT);
165 MLX5_BUILD_PTYS2ETHTOOL_CONFIG(MLX5E_25GAUI_1_25GBASE_CR_KR, ext,
166 ETHTOOL_LINK_MODE_25000baseCR_Full_BIT,
167 ETHTOOL_LINK_MODE_25000baseKR_Full_BIT,
168 ETHTOOL_LINK_MODE_25000baseSR_Full_BIT);
169 MLX5_BUILD_PTYS2ETHTOOL_CONFIG(MLX5E_50GAUI_2_LAUI_2_50GBASE_CR2_KR2,
171 ETHTOOL_LINK_MODE_50000baseCR2_Full_BIT,
172 ETHTOOL_LINK_MODE_50000baseKR2_Full_BIT,
173 ETHTOOL_LINK_MODE_50000baseSR2_Full_BIT);
174 MLX5_BUILD_PTYS2ETHTOOL_CONFIG(MLX5E_50GAUI_1_LAUI_1_50GBASE_CR_KR, ext,
175 ETHTOOL_LINK_MODE_50000baseKR_Full_BIT,
176 ETHTOOL_LINK_MODE_50000baseSR_Full_BIT,
177 ETHTOOL_LINK_MODE_50000baseCR_Full_BIT,
178 ETHTOOL_LINK_MODE_50000baseLR_ER_FR_Full_BIT,
179 ETHTOOL_LINK_MODE_50000baseDR_Full_BIT);
180 MLX5_BUILD_PTYS2ETHTOOL_CONFIG(MLX5E_CAUI_4_100GBASE_CR4_KR4, ext,
181 ETHTOOL_LINK_MODE_100000baseKR4_Full_BIT,
182 ETHTOOL_LINK_MODE_100000baseSR4_Full_BIT,
183 ETHTOOL_LINK_MODE_100000baseCR4_Full_BIT,
184 ETHTOOL_LINK_MODE_100000baseLR4_ER4_Full_BIT);
185 MLX5_BUILD_PTYS2ETHTOOL_CONFIG(MLX5E_100GAUI_2_100GBASE_CR2_KR2, ext,
186 ETHTOOL_LINK_MODE_100000baseKR2_Full_BIT,
187 ETHTOOL_LINK_MODE_100000baseSR2_Full_BIT,
188 ETHTOOL_LINK_MODE_100000baseCR2_Full_BIT,
189 ETHTOOL_LINK_MODE_100000baseLR2_ER2_FR2_Full_BIT,
190 ETHTOOL_LINK_MODE_100000baseDR2_Full_BIT);
191 MLX5_BUILD_PTYS2ETHTOOL_CONFIG(MLX5E_200GAUI_4_200GBASE_CR4_KR4, ext,
192 ETHTOOL_LINK_MODE_200000baseKR4_Full_BIT,
193 ETHTOOL_LINK_MODE_200000baseSR4_Full_BIT,
194 ETHTOOL_LINK_MODE_200000baseLR4_ER4_FR4_Full_BIT,
195 ETHTOOL_LINK_MODE_200000baseDR4_Full_BIT,
196 ETHTOOL_LINK_MODE_200000baseCR4_Full_BIT);
199 static void mlx5e_ethtool_get_speed_arr(struct mlx5_core_dev *mdev,
200 struct ptys2ethtool_config **arr,
203 bool ext = MLX5_CAP_PCAM_FEATURE(mdev, ptys_extended_ethernet);
205 *arr = ext ? ptys2ext_ethtool_table : ptys2legacy_ethtool_table;
206 *size = ext ? ARRAY_SIZE(ptys2ext_ethtool_table) :
207 ARRAY_SIZE(ptys2legacy_ethtool_table);
210 typedef int (*mlx5e_pflag_handler)(struct net_device *netdev, bool enable);
213 char name[ETH_GSTRING_LEN];
214 mlx5e_pflag_handler handler;
217 static const struct pflag_desc mlx5e_priv_flags[MLX5E_NUM_PFLAGS];
219 int mlx5e_ethtool_get_sset_count(struct mlx5e_priv *priv, int sset)
223 return mlx5e_stats_total_num(priv);
224 case ETH_SS_PRIV_FLAGS:
225 return MLX5E_NUM_PFLAGS;
227 return mlx5e_self_test_num(priv);
234 static int mlx5e_get_sset_count(struct net_device *dev, int sset)
236 struct mlx5e_priv *priv = netdev_priv(dev);
238 return mlx5e_ethtool_get_sset_count(priv, sset);
241 void mlx5e_ethtool_get_strings(struct mlx5e_priv *priv, u32 stringset, u8 *data)
246 case ETH_SS_PRIV_FLAGS:
247 for (i = 0; i < MLX5E_NUM_PFLAGS; i++)
248 strcpy(data + i * ETH_GSTRING_LEN,
249 mlx5e_priv_flags[i].name);
253 for (i = 0; i < mlx5e_self_test_num(priv); i++)
254 strcpy(data + i * ETH_GSTRING_LEN,
255 mlx5e_self_tests[i]);
259 mlx5e_stats_fill_strings(priv, data);
264 static void mlx5e_get_strings(struct net_device *dev, u32 stringset, u8 *data)
266 struct mlx5e_priv *priv = netdev_priv(dev);
268 mlx5e_ethtool_get_strings(priv, stringset, data);
271 void mlx5e_ethtool_get_ethtool_stats(struct mlx5e_priv *priv,
272 struct ethtool_stats *stats, u64 *data)
276 mutex_lock(&priv->state_lock);
277 mlx5e_stats_update(priv);
278 mutex_unlock(&priv->state_lock);
280 mlx5e_stats_fill(priv, data, idx);
283 static void mlx5e_get_ethtool_stats(struct net_device *dev,
284 struct ethtool_stats *stats,
287 struct mlx5e_priv *priv = netdev_priv(dev);
289 mlx5e_ethtool_get_ethtool_stats(priv, stats, data);
292 void mlx5e_ethtool_get_ringparam(struct mlx5e_priv *priv,
293 struct ethtool_ringparam *param)
295 param->rx_max_pending = 1 << MLX5E_PARAMS_MAXIMUM_LOG_RQ_SIZE;
296 param->tx_max_pending = 1 << MLX5E_PARAMS_MAXIMUM_LOG_SQ_SIZE;
297 param->rx_pending = 1 << priv->channels.params.log_rq_mtu_frames;
298 param->tx_pending = 1 << priv->channels.params.log_sq_size;
301 static void mlx5e_get_ringparam(struct net_device *dev,
302 struct ethtool_ringparam *param)
304 struct mlx5e_priv *priv = netdev_priv(dev);
306 mlx5e_ethtool_get_ringparam(priv, param);
309 int mlx5e_ethtool_set_ringparam(struct mlx5e_priv *priv,
310 struct ethtool_ringparam *param)
312 struct mlx5e_channels new_channels = {};
317 if (param->rx_jumbo_pending) {
318 netdev_info(priv->netdev, "%s: rx_jumbo_pending not supported\n",
322 if (param->rx_mini_pending) {
323 netdev_info(priv->netdev, "%s: rx_mini_pending not supported\n",
328 if (param->rx_pending < (1 << MLX5E_PARAMS_MINIMUM_LOG_RQ_SIZE)) {
329 netdev_info(priv->netdev, "%s: rx_pending (%d) < min (%d)\n",
330 __func__, param->rx_pending,
331 1 << MLX5E_PARAMS_MINIMUM_LOG_RQ_SIZE);
335 if (param->tx_pending < (1 << MLX5E_PARAMS_MINIMUM_LOG_SQ_SIZE)) {
336 netdev_info(priv->netdev, "%s: tx_pending (%d) < min (%d)\n",
337 __func__, param->tx_pending,
338 1 << MLX5E_PARAMS_MINIMUM_LOG_SQ_SIZE);
342 log_rq_size = order_base_2(param->rx_pending);
343 log_sq_size = order_base_2(param->tx_pending);
345 if (log_rq_size == priv->channels.params.log_rq_mtu_frames &&
346 log_sq_size == priv->channels.params.log_sq_size)
349 mutex_lock(&priv->state_lock);
351 new_channels.params = priv->channels.params;
352 new_channels.params.log_rq_mtu_frames = log_rq_size;
353 new_channels.params.log_sq_size = log_sq_size;
355 if (!test_bit(MLX5E_STATE_OPENED, &priv->state)) {
356 priv->channels.params = new_channels.params;
360 err = mlx5e_safe_switch_channels(priv, &new_channels, NULL);
363 mutex_unlock(&priv->state_lock);
368 static int mlx5e_set_ringparam(struct net_device *dev,
369 struct ethtool_ringparam *param)
371 struct mlx5e_priv *priv = netdev_priv(dev);
373 return mlx5e_ethtool_set_ringparam(priv, param);
376 void mlx5e_ethtool_get_channels(struct mlx5e_priv *priv,
377 struct ethtool_channels *ch)
379 mutex_lock(&priv->state_lock);
381 ch->max_combined = priv->max_nch;
382 ch->combined_count = priv->channels.params.num_channels;
383 if (priv->xsk.refcnt) {
384 /* The upper half are XSK queues. */
385 ch->max_combined *= 2;
386 ch->combined_count *= 2;
389 mutex_unlock(&priv->state_lock);
392 static void mlx5e_get_channels(struct net_device *dev,
393 struct ethtool_channels *ch)
395 struct mlx5e_priv *priv = netdev_priv(dev);
397 mlx5e_ethtool_get_channels(priv, ch);
400 int mlx5e_ethtool_set_channels(struct mlx5e_priv *priv,
401 struct ethtool_channels *ch)
403 struct mlx5e_params *cur_params = &priv->channels.params;
404 unsigned int count = ch->combined_count;
405 struct mlx5e_channels new_channels = {};
410 netdev_info(priv->netdev, "%s: combined_count=0 not supported\n",
415 if (cur_params->num_channels == count)
418 mutex_lock(&priv->state_lock);
420 /* Don't allow changing the number of channels if there is an active
421 * XSK, because the numeration of the XSK and regular RQs will change.
423 if (priv->xsk.refcnt) {
425 netdev_err(priv->netdev, "%s: AF_XDP is active, cannot change the number of channels\n",
430 new_channels.params = priv->channels.params;
431 new_channels.params.num_channels = count;
433 if (!test_bit(MLX5E_STATE_OPENED, &priv->state)) {
434 *cur_params = new_channels.params;
435 if (!netif_is_rxfh_configured(priv->netdev))
436 mlx5e_build_default_indir_rqt(priv->rss_params.indirection_rqt,
437 MLX5E_INDIR_RQT_SIZE, count);
441 arfs_enabled = priv->netdev->features & NETIF_F_NTUPLE;
443 mlx5e_arfs_disable(priv);
445 if (!netif_is_rxfh_configured(priv->netdev))
446 mlx5e_build_default_indir_rqt(priv->rss_params.indirection_rqt,
447 MLX5E_INDIR_RQT_SIZE, count);
449 /* Switch to new channels, set new parameters and close old ones */
450 err = mlx5e_safe_switch_channels(priv, &new_channels, NULL);
453 int err2 = mlx5e_arfs_enable(priv);
456 netdev_err(priv->netdev, "%s: mlx5e_arfs_enable failed: %d\n",
461 mutex_unlock(&priv->state_lock);
466 static int mlx5e_set_channels(struct net_device *dev,
467 struct ethtool_channels *ch)
469 struct mlx5e_priv *priv = netdev_priv(dev);
471 return mlx5e_ethtool_set_channels(priv, ch);
474 int mlx5e_ethtool_get_coalesce(struct mlx5e_priv *priv,
475 struct ethtool_coalesce *coal)
477 struct dim_cq_moder *rx_moder, *tx_moder;
479 if (!MLX5_CAP_GEN(priv->mdev, cq_moderation))
482 rx_moder = &priv->channels.params.rx_cq_moderation;
483 coal->rx_coalesce_usecs = rx_moder->usec;
484 coal->rx_max_coalesced_frames = rx_moder->pkts;
485 coal->use_adaptive_rx_coalesce = priv->channels.params.rx_dim_enabled;
487 tx_moder = &priv->channels.params.tx_cq_moderation;
488 coal->tx_coalesce_usecs = tx_moder->usec;
489 coal->tx_max_coalesced_frames = tx_moder->pkts;
490 coal->use_adaptive_tx_coalesce = priv->channels.params.tx_dim_enabled;
495 static int mlx5e_get_coalesce(struct net_device *netdev,
496 struct ethtool_coalesce *coal)
498 struct mlx5e_priv *priv = netdev_priv(netdev);
500 return mlx5e_ethtool_get_coalesce(priv, coal);
503 #define MLX5E_MAX_COAL_TIME MLX5_MAX_CQ_PERIOD
504 #define MLX5E_MAX_COAL_FRAMES MLX5_MAX_CQ_COUNT
507 mlx5e_set_priv_channels_coalesce(struct mlx5e_priv *priv, struct ethtool_coalesce *coal)
509 struct mlx5_core_dev *mdev = priv->mdev;
513 for (i = 0; i < priv->channels.num; ++i) {
514 struct mlx5e_channel *c = priv->channels.c[i];
516 for (tc = 0; tc < c->num_tc; tc++) {
517 mlx5_core_modify_cq_moderation(mdev,
519 coal->tx_coalesce_usecs,
520 coal->tx_max_coalesced_frames);
523 mlx5_core_modify_cq_moderation(mdev, &c->rq.cq.mcq,
524 coal->rx_coalesce_usecs,
525 coal->rx_max_coalesced_frames);
529 int mlx5e_ethtool_set_coalesce(struct mlx5e_priv *priv,
530 struct ethtool_coalesce *coal)
532 struct dim_cq_moder *rx_moder, *tx_moder;
533 struct mlx5_core_dev *mdev = priv->mdev;
534 struct mlx5e_channels new_channels = {};
538 if (!MLX5_CAP_GEN(mdev, cq_moderation))
541 if (coal->tx_coalesce_usecs > MLX5E_MAX_COAL_TIME ||
542 coal->rx_coalesce_usecs > MLX5E_MAX_COAL_TIME) {
543 netdev_info(priv->netdev, "%s: maximum coalesce time supported is %lu usecs\n",
544 __func__, MLX5E_MAX_COAL_TIME);
548 if (coal->tx_max_coalesced_frames > MLX5E_MAX_COAL_FRAMES ||
549 coal->rx_max_coalesced_frames > MLX5E_MAX_COAL_FRAMES) {
550 netdev_info(priv->netdev, "%s: maximum coalesced frames supported is %lu\n",
551 __func__, MLX5E_MAX_COAL_FRAMES);
555 mutex_lock(&priv->state_lock);
556 new_channels.params = priv->channels.params;
558 rx_moder = &new_channels.params.rx_cq_moderation;
559 rx_moder->usec = coal->rx_coalesce_usecs;
560 rx_moder->pkts = coal->rx_max_coalesced_frames;
561 new_channels.params.rx_dim_enabled = !!coal->use_adaptive_rx_coalesce;
563 tx_moder = &new_channels.params.tx_cq_moderation;
564 tx_moder->usec = coal->tx_coalesce_usecs;
565 tx_moder->pkts = coal->tx_max_coalesced_frames;
566 new_channels.params.tx_dim_enabled = !!coal->use_adaptive_tx_coalesce;
568 if (!test_bit(MLX5E_STATE_OPENED, &priv->state)) {
569 priv->channels.params = new_channels.params;
574 reset = (!!coal->use_adaptive_rx_coalesce != priv->channels.params.rx_dim_enabled) ||
575 (!!coal->use_adaptive_tx_coalesce != priv->channels.params.tx_dim_enabled);
578 mlx5e_set_priv_channels_coalesce(priv, coal);
579 priv->channels.params = new_channels.params;
583 err = mlx5e_safe_switch_channels(priv, &new_channels, NULL);
586 mutex_unlock(&priv->state_lock);
590 static int mlx5e_set_coalesce(struct net_device *netdev,
591 struct ethtool_coalesce *coal)
593 struct mlx5e_priv *priv = netdev_priv(netdev);
595 return mlx5e_ethtool_set_coalesce(priv, coal);
598 static void ptys2ethtool_supported_link(struct mlx5_core_dev *mdev,
599 unsigned long *supported_modes,
602 unsigned long proto_cap = eth_proto_cap;
603 struct ptys2ethtool_config *table;
607 mlx5e_ethtool_get_speed_arr(mdev, &table, &max_size);
608 for_each_set_bit(proto, &proto_cap, max_size)
609 bitmap_or(supported_modes, supported_modes,
610 table[proto].supported,
611 __ETHTOOL_LINK_MODE_MASK_NBITS);
614 static void ptys2ethtool_adver_link(unsigned long *advertising_modes,
615 u32 eth_proto_cap, bool ext)
617 unsigned long proto_cap = eth_proto_cap;
618 struct ptys2ethtool_config *table;
622 table = ext ? ptys2ext_ethtool_table : ptys2legacy_ethtool_table;
623 max_size = ext ? ARRAY_SIZE(ptys2ext_ethtool_table) :
624 ARRAY_SIZE(ptys2legacy_ethtool_table);
626 for_each_set_bit(proto, &proto_cap, max_size)
627 bitmap_or(advertising_modes, advertising_modes,
628 table[proto].advertised,
629 __ETHTOOL_LINK_MODE_MASK_NBITS);
632 static const u32 pplm_fec_2_ethtool[] = {
633 [MLX5E_FEC_NOFEC] = ETHTOOL_FEC_OFF,
634 [MLX5E_FEC_FIRECODE] = ETHTOOL_FEC_BASER,
635 [MLX5E_FEC_RS_528_514] = ETHTOOL_FEC_RS,
636 [MLX5E_FEC_RS_544_514] = ETHTOOL_FEC_RS,
637 [MLX5E_FEC_LLRS_272_257_1] = ETHTOOL_FEC_LLRS,
640 static u32 pplm2ethtool_fec(u_long fec_mode, unsigned long size)
645 return ETHTOOL_FEC_AUTO;
647 mode = find_first_bit(&fec_mode, size);
649 if (mode < ARRAY_SIZE(pplm_fec_2_ethtool))
650 return pplm_fec_2_ethtool[mode];
655 #define MLX5E_ADVERTISE_SUPPORTED_FEC(mlx5_fec, ethtool_fec) \
657 if (mlx5e_fec_in_caps(dev, 1 << (mlx5_fec))) \
658 __set_bit(ethtool_fec, \
659 link_ksettings->link_modes.supported);\
662 static const u32 pplm_fec_2_ethtool_linkmodes[] = {
663 [MLX5E_FEC_NOFEC] = ETHTOOL_LINK_MODE_FEC_NONE_BIT,
664 [MLX5E_FEC_FIRECODE] = ETHTOOL_LINK_MODE_FEC_BASER_BIT,
665 [MLX5E_FEC_RS_528_514] = ETHTOOL_LINK_MODE_FEC_RS_BIT,
666 [MLX5E_FEC_RS_544_514] = ETHTOOL_LINK_MODE_FEC_RS_BIT,
667 [MLX5E_FEC_LLRS_272_257_1] = ETHTOOL_LINK_MODE_FEC_LLRS_BIT,
670 static int get_fec_supported_advertised(struct mlx5_core_dev *dev,
671 struct ethtool_link_ksettings *link_ksettings)
673 u_long active_fec = 0;
677 err = mlx5e_get_fec_mode(dev, (u32 *)&active_fec, NULL);
679 return (err == -EOPNOTSUPP) ? 0 : err;
681 MLX5E_ADVERTISE_SUPPORTED_FEC(MLX5E_FEC_NOFEC,
682 ETHTOOL_LINK_MODE_FEC_NONE_BIT);
683 MLX5E_ADVERTISE_SUPPORTED_FEC(MLX5E_FEC_FIRECODE,
684 ETHTOOL_LINK_MODE_FEC_BASER_BIT);
685 MLX5E_ADVERTISE_SUPPORTED_FEC(MLX5E_FEC_RS_528_514,
686 ETHTOOL_LINK_MODE_FEC_RS_BIT);
687 MLX5E_ADVERTISE_SUPPORTED_FEC(MLX5E_FEC_LLRS_272_257_1,
688 ETHTOOL_LINK_MODE_FEC_LLRS_BIT);
690 /* active fec is a bit set, find out which bit is set and
691 * advertise the corresponding ethtool bit
693 bitn = find_first_bit(&active_fec, sizeof(u32) * BITS_PER_BYTE);
694 if (bitn < ARRAY_SIZE(pplm_fec_2_ethtool_linkmodes))
695 __set_bit(pplm_fec_2_ethtool_linkmodes[bitn],
696 link_ksettings->link_modes.advertising);
701 static void ptys2ethtool_supported_advertised_port(struct ethtool_link_ksettings *link_ksettings,
703 u8 connector_type, bool ext)
705 if ((!connector_type && !ext) || connector_type >= MLX5E_CONNECTOR_TYPE_NUMBER) {
706 if (eth_proto_cap & (MLX5E_PROT_MASK(MLX5E_10GBASE_CR)
707 | MLX5E_PROT_MASK(MLX5E_10GBASE_SR)
708 | MLX5E_PROT_MASK(MLX5E_40GBASE_CR4)
709 | MLX5E_PROT_MASK(MLX5E_40GBASE_SR4)
710 | MLX5E_PROT_MASK(MLX5E_100GBASE_SR4)
711 | MLX5E_PROT_MASK(MLX5E_1000BASE_CX_SGMII))) {
712 ethtool_link_ksettings_add_link_mode(link_ksettings,
715 ethtool_link_ksettings_add_link_mode(link_ksettings,
720 if (eth_proto_cap & (MLX5E_PROT_MASK(MLX5E_100GBASE_KR4)
721 | MLX5E_PROT_MASK(MLX5E_40GBASE_KR4)
722 | MLX5E_PROT_MASK(MLX5E_10GBASE_KR)
723 | MLX5E_PROT_MASK(MLX5E_10GBASE_KX4)
724 | MLX5E_PROT_MASK(MLX5E_1000BASE_KX))) {
725 ethtool_link_ksettings_add_link_mode(link_ksettings,
728 ethtool_link_ksettings_add_link_mode(link_ksettings,
735 switch (connector_type) {
737 ethtool_link_ksettings_add_link_mode(link_ksettings,
739 ethtool_link_ksettings_add_link_mode(link_ksettings,
743 ethtool_link_ksettings_add_link_mode(link_ksettings,
745 ethtool_link_ksettings_add_link_mode(link_ksettings,
749 ethtool_link_ksettings_add_link_mode(link_ksettings,
751 ethtool_link_ksettings_add_link_mode(link_ksettings,
755 ethtool_link_ksettings_add_link_mode(link_ksettings,
757 ethtool_link_ksettings_add_link_mode(link_ksettings,
760 case MLX5E_PORT_FIBRE:
761 ethtool_link_ksettings_add_link_mode(link_ksettings,
763 ethtool_link_ksettings_add_link_mode(link_ksettings,
767 ethtool_link_ksettings_add_link_mode(link_ksettings,
768 supported, Backplane);
769 ethtool_link_ksettings_add_link_mode(link_ksettings,
770 advertising, Backplane);
772 case MLX5E_PORT_NONE:
773 case MLX5E_PORT_OTHER:
779 static void get_speed_duplex(struct net_device *netdev,
780 u32 eth_proto_oper, bool force_legacy,
781 struct ethtool_link_ksettings *link_ksettings)
783 struct mlx5e_priv *priv = netdev_priv(netdev);
784 u32 speed = SPEED_UNKNOWN;
785 u8 duplex = DUPLEX_UNKNOWN;
787 if (!netif_carrier_ok(netdev))
790 speed = mlx5e_port_ptys2speed(priv->mdev, eth_proto_oper, force_legacy);
792 speed = SPEED_UNKNOWN;
796 duplex = DUPLEX_FULL;
799 link_ksettings->base.speed = speed;
800 link_ksettings->base.duplex = duplex;
803 static void get_supported(struct mlx5_core_dev *mdev, u32 eth_proto_cap,
804 struct ethtool_link_ksettings *link_ksettings)
806 unsigned long *supported = link_ksettings->link_modes.supported;
807 ptys2ethtool_supported_link(mdev, supported, eth_proto_cap);
809 ethtool_link_ksettings_add_link_mode(link_ksettings, supported, Pause);
812 static void get_advertising(u32 eth_proto_cap, u8 tx_pause, u8 rx_pause,
813 struct ethtool_link_ksettings *link_ksettings,
816 unsigned long *advertising = link_ksettings->link_modes.advertising;
817 ptys2ethtool_adver_link(advertising, eth_proto_cap, ext);
820 ethtool_link_ksettings_add_link_mode(link_ksettings, advertising, Pause);
821 if (tx_pause ^ rx_pause)
822 ethtool_link_ksettings_add_link_mode(link_ksettings, advertising, Asym_Pause);
825 static int ptys2connector_type[MLX5E_CONNECTOR_TYPE_NUMBER] = {
826 [MLX5E_PORT_UNKNOWN] = PORT_OTHER,
827 [MLX5E_PORT_NONE] = PORT_NONE,
828 [MLX5E_PORT_TP] = PORT_TP,
829 [MLX5E_PORT_AUI] = PORT_AUI,
830 [MLX5E_PORT_BNC] = PORT_BNC,
831 [MLX5E_PORT_MII] = PORT_MII,
832 [MLX5E_PORT_FIBRE] = PORT_FIBRE,
833 [MLX5E_PORT_DA] = PORT_DA,
834 [MLX5E_PORT_OTHER] = PORT_OTHER,
837 static u8 get_connector_port(u32 eth_proto, u8 connector_type, bool ext)
839 if ((connector_type || ext) && connector_type < MLX5E_CONNECTOR_TYPE_NUMBER)
840 return ptys2connector_type[connector_type];
843 (MLX5E_PROT_MASK(MLX5E_10GBASE_SR) |
844 MLX5E_PROT_MASK(MLX5E_40GBASE_SR4) |
845 MLX5E_PROT_MASK(MLX5E_100GBASE_SR4) |
846 MLX5E_PROT_MASK(MLX5E_1000BASE_CX_SGMII))) {
851 (MLX5E_PROT_MASK(MLX5E_40GBASE_CR4) |
852 MLX5E_PROT_MASK(MLX5E_10GBASE_CR) |
853 MLX5E_PROT_MASK(MLX5E_100GBASE_CR4))) {
858 (MLX5E_PROT_MASK(MLX5E_10GBASE_KX4) |
859 MLX5E_PROT_MASK(MLX5E_10GBASE_KR) |
860 MLX5E_PROT_MASK(MLX5E_40GBASE_KR4) |
861 MLX5E_PROT_MASK(MLX5E_100GBASE_KR4))) {
868 static void get_lp_advertising(struct mlx5_core_dev *mdev, u32 eth_proto_lp,
869 struct ethtool_link_ksettings *link_ksettings)
871 unsigned long *lp_advertising = link_ksettings->link_modes.lp_advertising;
872 bool ext = MLX5_CAP_PCAM_FEATURE(mdev, ptys_extended_ethernet);
874 ptys2ethtool_adver_link(lp_advertising, eth_proto_lp, ext);
877 int mlx5e_ethtool_get_link_ksettings(struct mlx5e_priv *priv,
878 struct ethtool_link_ksettings *link_ksettings)
880 struct mlx5_core_dev *mdev = priv->mdev;
881 u32 out[MLX5_ST_SZ_DW(ptys_reg)] = {0};
895 err = mlx5_query_port_ptys(mdev, out, sizeof(out), MLX5_PTYS_EN, 1);
897 netdev_err(priv->netdev, "%s: query port ptys failed: %d\n",
901 ext = MLX5_CAP_PCAM_FEATURE(mdev, ptys_extended_ethernet);
902 eth_proto_cap = MLX5_GET_ETH_PROTO(ptys_reg, out, ext,
903 eth_proto_capability);
904 eth_proto_admin = MLX5_GET_ETH_PROTO(ptys_reg, out, ext,
906 /* Fields: eth_proto_admin and ext_eth_proto_admin are
907 * mutually exclusive. Hence try reading legacy advertising
908 * when extended advertising is zero.
909 * admin_ext indicates which proto_admin (ext vs. legacy)
910 * should be read and interpreted
913 if (ext && !eth_proto_admin) {
914 eth_proto_admin = MLX5_GET_ETH_PROTO(ptys_reg, out, false,
919 eth_proto_oper = MLX5_GET_ETH_PROTO(ptys_reg, out, admin_ext,
921 eth_proto_lp = MLX5_GET(ptys_reg, out, eth_proto_lp_advertise);
922 an_disable_admin = MLX5_GET(ptys_reg, out, an_disable_admin);
923 an_status = MLX5_GET(ptys_reg, out, an_status);
924 connector_type = MLX5_GET(ptys_reg, out, connector_type);
926 mlx5_query_port_pause(mdev, &rx_pause, &tx_pause);
928 ethtool_link_ksettings_zero_link_mode(link_ksettings, supported);
929 ethtool_link_ksettings_zero_link_mode(link_ksettings, advertising);
931 get_supported(mdev, eth_proto_cap, link_ksettings);
932 get_advertising(eth_proto_admin, tx_pause, rx_pause, link_ksettings,
934 get_speed_duplex(priv->netdev, eth_proto_oper, !admin_ext,
937 eth_proto_oper = eth_proto_oper ? eth_proto_oper : eth_proto_cap;
939 link_ksettings->base.port = get_connector_port(eth_proto_oper,
940 connector_type, ext);
941 ptys2ethtool_supported_advertised_port(link_ksettings, eth_proto_admin,
942 connector_type, ext);
943 get_lp_advertising(mdev, eth_proto_lp, link_ksettings);
945 if (an_status == MLX5_AN_COMPLETE)
946 ethtool_link_ksettings_add_link_mode(link_ksettings,
947 lp_advertising, Autoneg);
949 link_ksettings->base.autoneg = an_disable_admin ? AUTONEG_DISABLE :
951 ethtool_link_ksettings_add_link_mode(link_ksettings, supported,
954 err = get_fec_supported_advertised(mdev, link_ksettings);
956 netdev_dbg(priv->netdev, "%s: FEC caps query failed: %d\n",
958 err = 0; /* don't fail caps query because of FEC error */
961 if (!an_disable_admin)
962 ethtool_link_ksettings_add_link_mode(link_ksettings,
963 advertising, Autoneg);
969 static int mlx5e_get_link_ksettings(struct net_device *netdev,
970 struct ethtool_link_ksettings *link_ksettings)
972 struct mlx5e_priv *priv = netdev_priv(netdev);
974 return mlx5e_ethtool_get_link_ksettings(priv, link_ksettings);
977 static u32 mlx5e_ethtool2ptys_adver_link(const unsigned long *link_modes)
979 u32 i, ptys_modes = 0;
981 for (i = 0; i < MLX5E_LINK_MODES_NUMBER; ++i) {
982 if (*ptys2legacy_ethtool_table[i].advertised == 0)
984 if (bitmap_intersects(ptys2legacy_ethtool_table[i].advertised,
986 __ETHTOOL_LINK_MODE_MASK_NBITS))
987 ptys_modes |= MLX5E_PROT_MASK(i);
993 static u32 mlx5e_ethtool2ptys_ext_adver_link(const unsigned long *link_modes)
995 u32 i, ptys_modes = 0;
996 unsigned long modes[2];
998 for (i = 0; i < MLX5E_EXT_LINK_MODES_NUMBER; ++i) {
999 if (*ptys2ext_ethtool_table[i].advertised == 0)
1001 memset(modes, 0, sizeof(modes));
1002 bitmap_and(modes, ptys2ext_ethtool_table[i].advertised,
1003 link_modes, __ETHTOOL_LINK_MODE_MASK_NBITS);
1005 if (modes[0] == ptys2ext_ethtool_table[i].advertised[0] &&
1006 modes[1] == ptys2ext_ethtool_table[i].advertised[1])
1007 ptys_modes |= MLX5E_PROT_MASK(i);
1012 static bool ext_link_mode_requested(const unsigned long *adver)
1014 #define MLX5E_MIN_PTYS_EXT_LINK_MODE_BIT ETHTOOL_LINK_MODE_50000baseKR_Full_BIT
1015 int size = __ETHTOOL_LINK_MODE_MASK_NBITS - MLX5E_MIN_PTYS_EXT_LINK_MODE_BIT;
1016 __ETHTOOL_DECLARE_LINK_MODE_MASK(modes) = {0,};
1018 bitmap_set(modes, MLX5E_MIN_PTYS_EXT_LINK_MODE_BIT, size);
1019 return bitmap_intersects(modes, adver, __ETHTOOL_LINK_MODE_MASK_NBITS);
1022 static bool ext_requested(u8 autoneg, const unsigned long *adver, bool ext_supported)
1024 bool ext_link_mode = ext_link_mode_requested(adver);
1026 return autoneg == AUTONEG_ENABLE ? ext_link_mode : ext_supported;
1029 int mlx5e_ethtool_set_link_ksettings(struct mlx5e_priv *priv,
1030 const struct ethtool_link_ksettings *link_ksettings)
1032 struct mlx5_core_dev *mdev = priv->mdev;
1033 struct mlx5e_port_eth_proto eproto;
1034 const unsigned long *adver;
1035 bool an_changes = false;
1036 u8 an_disable_admin;
1047 u32 (*ethtool2ptys_adver_func)(const unsigned long *adver);
1049 adver = link_ksettings->link_modes.advertising;
1050 autoneg = link_ksettings->base.autoneg;
1051 speed = link_ksettings->base.speed;
1053 ext_supported = MLX5_CAP_PCAM_FEATURE(mdev, ptys_extended_ethernet);
1054 ext = ext_requested(autoneg, adver, ext_supported);
1055 if (!ext_supported && ext)
1058 ethtool2ptys_adver_func = ext ? mlx5e_ethtool2ptys_ext_adver_link :
1059 mlx5e_ethtool2ptys_adver_link;
1060 err = mlx5_port_query_eth_proto(mdev, 1, ext, &eproto);
1062 netdev_err(priv->netdev, "%s: query port eth proto failed: %d\n",
1066 link_modes = autoneg == AUTONEG_ENABLE ? ethtool2ptys_adver_func(adver) :
1067 mlx5e_port_speed2linkmodes(mdev, speed, !ext);
1069 if ((link_modes & MLX5E_PROT_MASK(MLX5E_56GBASE_R4)) &&
1070 autoneg != AUTONEG_ENABLE) {
1071 netdev_err(priv->netdev, "%s: 56G link speed requires autoneg enabled\n",
1077 link_modes = link_modes & eproto.cap;
1079 netdev_err(priv->netdev, "%s: Not supported link mode(s) requested",
1085 mlx5_port_query_eth_autoneg(mdev, &an_status, &an_disable_cap,
1088 an_disable = autoneg == AUTONEG_DISABLE;
1089 an_changes = ((!an_disable && an_disable_admin) ||
1090 (an_disable && !an_disable_admin));
1092 if (!an_changes && link_modes == eproto.admin)
1095 mlx5_port_set_eth_ptys(mdev, an_disable, link_modes, ext);
1096 mlx5_toggle_port_link(mdev);
1102 static int mlx5e_set_link_ksettings(struct net_device *netdev,
1103 const struct ethtool_link_ksettings *link_ksettings)
1105 struct mlx5e_priv *priv = netdev_priv(netdev);
1107 return mlx5e_ethtool_set_link_ksettings(priv, link_ksettings);
1110 u32 mlx5e_ethtool_get_rxfh_key_size(struct mlx5e_priv *priv)
1112 return sizeof(priv->rss_params.toeplitz_hash_key);
1115 static u32 mlx5e_get_rxfh_key_size(struct net_device *netdev)
1117 struct mlx5e_priv *priv = netdev_priv(netdev);
1119 return mlx5e_ethtool_get_rxfh_key_size(priv);
1122 u32 mlx5e_ethtool_get_rxfh_indir_size(struct mlx5e_priv *priv)
1124 return MLX5E_INDIR_RQT_SIZE;
1127 static u32 mlx5e_get_rxfh_indir_size(struct net_device *netdev)
1129 struct mlx5e_priv *priv = netdev_priv(netdev);
1131 return mlx5e_ethtool_get_rxfh_indir_size(priv);
1134 static int mlx5e_get_rxfh(struct net_device *netdev, u32 *indir, u8 *key,
1137 struct mlx5e_priv *priv = netdev_priv(netdev);
1138 struct mlx5e_rss_params *rss = &priv->rss_params;
1141 memcpy(indir, rss->indirection_rqt,
1142 sizeof(rss->indirection_rqt));
1145 memcpy(key, rss->toeplitz_hash_key,
1146 sizeof(rss->toeplitz_hash_key));
1149 *hfunc = rss->hfunc;
1154 static int mlx5e_set_rxfh(struct net_device *dev, const u32 *indir,
1155 const u8 *key, const u8 hfunc)
1157 struct mlx5e_priv *priv = netdev_priv(dev);
1158 struct mlx5e_rss_params *rss = &priv->rss_params;
1159 int inlen = MLX5_ST_SZ_BYTES(modify_tir_in);
1160 bool hash_changed = false;
1163 if ((hfunc != ETH_RSS_HASH_NO_CHANGE) &&
1164 (hfunc != ETH_RSS_HASH_XOR) &&
1165 (hfunc != ETH_RSS_HASH_TOP))
1168 in = kvzalloc(inlen, GFP_KERNEL);
1172 mutex_lock(&priv->state_lock);
1174 if (hfunc != ETH_RSS_HASH_NO_CHANGE && hfunc != rss->hfunc) {
1176 hash_changed = true;
1180 memcpy(rss->indirection_rqt, indir,
1181 sizeof(rss->indirection_rqt));
1183 if (test_bit(MLX5E_STATE_OPENED, &priv->state)) {
1184 u32 rqtn = priv->indir_rqt.rqtn;
1185 struct mlx5e_redirect_rqt_param rrp = {
1189 .hfunc = rss->hfunc,
1190 .channels = &priv->channels,
1195 mlx5e_redirect_rqt(priv, rqtn, MLX5E_INDIR_RQT_SIZE, rrp);
1200 memcpy(rss->toeplitz_hash_key, key,
1201 sizeof(rss->toeplitz_hash_key));
1202 hash_changed = hash_changed || rss->hfunc == ETH_RSS_HASH_TOP;
1206 mlx5e_modify_tirs_hash(priv, in, inlen);
1208 mutex_unlock(&priv->state_lock);
1215 #define MLX5E_PFC_PREVEN_AUTO_TOUT_MSEC 100
1216 #define MLX5E_PFC_PREVEN_TOUT_MAX_MSEC 8000
1217 #define MLX5E_PFC_PREVEN_MINOR_PRECENT 85
1218 #define MLX5E_PFC_PREVEN_TOUT_MIN_MSEC 80
1219 #define MLX5E_DEVICE_STALL_MINOR_WATERMARK(critical_tout) \
1220 max_t(u16, MLX5E_PFC_PREVEN_TOUT_MIN_MSEC, \
1221 (critical_tout * MLX5E_PFC_PREVEN_MINOR_PRECENT) / 100)
1223 static int mlx5e_get_pfc_prevention_tout(struct net_device *netdev,
1224 u16 *pfc_prevention_tout)
1226 struct mlx5e_priv *priv = netdev_priv(netdev);
1227 struct mlx5_core_dev *mdev = priv->mdev;
1229 if (!MLX5_CAP_PCAM_FEATURE((priv)->mdev, pfcc_mask) ||
1230 !MLX5_CAP_DEBUG((priv)->mdev, stall_detect))
1233 return mlx5_query_port_stall_watermark(mdev, pfc_prevention_tout, NULL);
1236 static int mlx5e_set_pfc_prevention_tout(struct net_device *netdev,
1239 struct mlx5e_priv *priv = netdev_priv(netdev);
1240 struct mlx5_core_dev *mdev = priv->mdev;
1244 if (!MLX5_CAP_PCAM_FEATURE((priv)->mdev, pfcc_mask) ||
1245 !MLX5_CAP_DEBUG((priv)->mdev, stall_detect))
1248 critical_tout = (pfc_preven == PFC_STORM_PREVENTION_AUTO) ?
1249 MLX5E_PFC_PREVEN_AUTO_TOUT_MSEC :
1252 if (critical_tout != PFC_STORM_PREVENTION_DISABLE &&
1253 (critical_tout > MLX5E_PFC_PREVEN_TOUT_MAX_MSEC ||
1254 critical_tout < MLX5E_PFC_PREVEN_TOUT_MIN_MSEC)) {
1255 netdev_info(netdev, "%s: pfc prevention tout not in range (%d-%d)\n",
1256 __func__, MLX5E_PFC_PREVEN_TOUT_MIN_MSEC,
1257 MLX5E_PFC_PREVEN_TOUT_MAX_MSEC);
1261 minor = MLX5E_DEVICE_STALL_MINOR_WATERMARK(critical_tout);
1262 return mlx5_set_port_stall_watermark(mdev, critical_tout,
1266 static int mlx5e_get_tunable(struct net_device *dev,
1267 const struct ethtool_tunable *tuna,
1273 case ETHTOOL_PFC_PREVENTION_TOUT:
1274 err = mlx5e_get_pfc_prevention_tout(dev, data);
1284 static int mlx5e_set_tunable(struct net_device *dev,
1285 const struct ethtool_tunable *tuna,
1288 struct mlx5e_priv *priv = netdev_priv(dev);
1291 mutex_lock(&priv->state_lock);
1294 case ETHTOOL_PFC_PREVENTION_TOUT:
1295 err = mlx5e_set_pfc_prevention_tout(dev, *(u16 *)data);
1302 mutex_unlock(&priv->state_lock);
1306 void mlx5e_ethtool_get_pauseparam(struct mlx5e_priv *priv,
1307 struct ethtool_pauseparam *pauseparam)
1309 struct mlx5_core_dev *mdev = priv->mdev;
1312 err = mlx5_query_port_pause(mdev, &pauseparam->rx_pause,
1313 &pauseparam->tx_pause);
1315 netdev_err(priv->netdev, "%s: mlx5_query_port_pause failed:0x%x\n",
1320 static void mlx5e_get_pauseparam(struct net_device *netdev,
1321 struct ethtool_pauseparam *pauseparam)
1323 struct mlx5e_priv *priv = netdev_priv(netdev);
1325 mlx5e_ethtool_get_pauseparam(priv, pauseparam);
1328 int mlx5e_ethtool_set_pauseparam(struct mlx5e_priv *priv,
1329 struct ethtool_pauseparam *pauseparam)
1331 struct mlx5_core_dev *mdev = priv->mdev;
1334 if (!MLX5_CAP_GEN(mdev, vport_group_manager))
1337 if (pauseparam->autoneg)
1340 err = mlx5_set_port_pause(mdev,
1341 pauseparam->rx_pause ? 1 : 0,
1342 pauseparam->tx_pause ? 1 : 0);
1344 netdev_err(priv->netdev, "%s: mlx5_set_port_pause failed:0x%x\n",
1351 static int mlx5e_set_pauseparam(struct net_device *netdev,
1352 struct ethtool_pauseparam *pauseparam)
1354 struct mlx5e_priv *priv = netdev_priv(netdev);
1356 return mlx5e_ethtool_set_pauseparam(priv, pauseparam);
1359 int mlx5e_ethtool_get_ts_info(struct mlx5e_priv *priv,
1360 struct ethtool_ts_info *info)
1362 struct mlx5_core_dev *mdev = priv->mdev;
1364 info->phc_index = mlx5_clock_get_ptp_index(mdev);
1366 if (!MLX5_CAP_GEN(priv->mdev, device_frequency_khz) ||
1367 info->phc_index == -1)
1370 info->so_timestamping = SOF_TIMESTAMPING_TX_HARDWARE |
1371 SOF_TIMESTAMPING_RX_HARDWARE |
1372 SOF_TIMESTAMPING_RAW_HARDWARE;
1374 info->tx_types = BIT(HWTSTAMP_TX_OFF) |
1375 BIT(HWTSTAMP_TX_ON);
1377 info->rx_filters = BIT(HWTSTAMP_FILTER_NONE) |
1378 BIT(HWTSTAMP_FILTER_ALL);
1383 static int mlx5e_get_ts_info(struct net_device *dev,
1384 struct ethtool_ts_info *info)
1386 struct mlx5e_priv *priv = netdev_priv(dev);
1388 return mlx5e_ethtool_get_ts_info(priv, info);
1391 static __u32 mlx5e_get_wol_supported(struct mlx5_core_dev *mdev)
1395 if (MLX5_CAP_GEN(mdev, wol_g))
1398 if (MLX5_CAP_GEN(mdev, wol_s))
1399 ret |= WAKE_MAGICSECURE;
1401 if (MLX5_CAP_GEN(mdev, wol_a))
1404 if (MLX5_CAP_GEN(mdev, wol_b))
1407 if (MLX5_CAP_GEN(mdev, wol_m))
1410 if (MLX5_CAP_GEN(mdev, wol_u))
1413 if (MLX5_CAP_GEN(mdev, wol_p))
1419 static __u32 mlx5e_reformat_wol_mode_mlx5_to_linux(u8 mode)
1423 if (mode & MLX5_WOL_MAGIC)
1426 if (mode & MLX5_WOL_SECURED_MAGIC)
1427 ret |= WAKE_MAGICSECURE;
1429 if (mode & MLX5_WOL_ARP)
1432 if (mode & MLX5_WOL_BROADCAST)
1435 if (mode & MLX5_WOL_MULTICAST)
1438 if (mode & MLX5_WOL_UNICAST)
1441 if (mode & MLX5_WOL_PHY_ACTIVITY)
1447 static u8 mlx5e_reformat_wol_mode_linux_to_mlx5(__u32 mode)
1451 if (mode & WAKE_MAGIC)
1452 ret |= MLX5_WOL_MAGIC;
1454 if (mode & WAKE_MAGICSECURE)
1455 ret |= MLX5_WOL_SECURED_MAGIC;
1457 if (mode & WAKE_ARP)
1458 ret |= MLX5_WOL_ARP;
1460 if (mode & WAKE_BCAST)
1461 ret |= MLX5_WOL_BROADCAST;
1463 if (mode & WAKE_MCAST)
1464 ret |= MLX5_WOL_MULTICAST;
1466 if (mode & WAKE_UCAST)
1467 ret |= MLX5_WOL_UNICAST;
1469 if (mode & WAKE_PHY)
1470 ret |= MLX5_WOL_PHY_ACTIVITY;
1475 static void mlx5e_get_wol(struct net_device *netdev,
1476 struct ethtool_wolinfo *wol)
1478 struct mlx5e_priv *priv = netdev_priv(netdev);
1479 struct mlx5_core_dev *mdev = priv->mdev;
1483 memset(wol, 0, sizeof(*wol));
1485 wol->supported = mlx5e_get_wol_supported(mdev);
1486 if (!wol->supported)
1489 err = mlx5_query_port_wol(mdev, &mlx5_wol_mode);
1493 wol->wolopts = mlx5e_reformat_wol_mode_mlx5_to_linux(mlx5_wol_mode);
1496 static int mlx5e_set_wol(struct net_device *netdev, struct ethtool_wolinfo *wol)
1498 struct mlx5e_priv *priv = netdev_priv(netdev);
1499 struct mlx5_core_dev *mdev = priv->mdev;
1500 __u32 wol_supported = mlx5e_get_wol_supported(mdev);
1506 if (wol->wolopts & ~wol_supported)
1509 mlx5_wol_mode = mlx5e_reformat_wol_mode_linux_to_mlx5(wol->wolopts);
1511 return mlx5_set_port_wol(mdev, mlx5_wol_mode);
1514 static int mlx5e_get_fecparam(struct net_device *netdev,
1515 struct ethtool_fecparam *fecparam)
1517 struct mlx5e_priv *priv = netdev_priv(netdev);
1518 struct mlx5_core_dev *mdev = priv->mdev;
1519 u16 fec_configured = 0;
1523 err = mlx5e_get_fec_mode(mdev, &fec_active, &fec_configured);
1528 fecparam->active_fec = pplm2ethtool_fec((u_long)fec_active,
1529 sizeof(u32) * BITS_PER_BYTE);
1531 if (!fecparam->active_fec)
1534 fecparam->fec = pplm2ethtool_fec((u_long)fec_configured,
1535 sizeof(u16) * BITS_PER_BYTE);
1540 static int mlx5e_set_fecparam(struct net_device *netdev,
1541 struct ethtool_fecparam *fecparam)
1543 struct mlx5e_priv *priv = netdev_priv(netdev);
1544 struct mlx5_core_dev *mdev = priv->mdev;
1549 if (bitmap_weight((unsigned long *)&fecparam->fec,
1550 ETHTOOL_FEC_LLRS_BIT + 1) > 1)
1553 for (mode = 0; mode < ARRAY_SIZE(pplm_fec_2_ethtool); mode++) {
1554 if (!(pplm_fec_2_ethtool[mode] & fecparam->fec))
1556 fec_policy |= (1 << mode);
1560 err = mlx5e_set_fec_mode(mdev, fec_policy);
1565 mlx5_toggle_port_link(mdev);
1570 static u32 mlx5e_get_msglevel(struct net_device *dev)
1572 return ((struct mlx5e_priv *)netdev_priv(dev))->msglevel;
1575 static void mlx5e_set_msglevel(struct net_device *dev, u32 val)
1577 ((struct mlx5e_priv *)netdev_priv(dev))->msglevel = val;
1580 static int mlx5e_set_phys_id(struct net_device *dev,
1581 enum ethtool_phys_id_state state)
1583 struct mlx5e_priv *priv = netdev_priv(dev);
1584 struct mlx5_core_dev *mdev = priv->mdev;
1585 u16 beacon_duration;
1587 if (!MLX5_CAP_GEN(mdev, beacon_led))
1591 case ETHTOOL_ID_ACTIVE:
1592 beacon_duration = MLX5_BEACON_DURATION_INF;
1594 case ETHTOOL_ID_INACTIVE:
1595 beacon_duration = MLX5_BEACON_DURATION_OFF;
1601 return mlx5_set_port_beacon(mdev, beacon_duration);
1604 static int mlx5e_get_module_info(struct net_device *netdev,
1605 struct ethtool_modinfo *modinfo)
1607 struct mlx5e_priv *priv = netdev_priv(netdev);
1608 struct mlx5_core_dev *dev = priv->mdev;
1612 size_read = mlx5_query_module_eeprom(dev, 0, 2, data);
1616 /* data[0] = identifier byte */
1618 case MLX5_MODULE_ID_QSFP:
1619 modinfo->type = ETH_MODULE_SFF_8436;
1620 modinfo->eeprom_len = ETH_MODULE_SFF_8436_MAX_LEN;
1622 case MLX5_MODULE_ID_QSFP_PLUS:
1623 case MLX5_MODULE_ID_QSFP28:
1624 /* data[1] = revision id */
1625 if (data[0] == MLX5_MODULE_ID_QSFP28 || data[1] >= 0x3) {
1626 modinfo->type = ETH_MODULE_SFF_8636;
1627 modinfo->eeprom_len = ETH_MODULE_SFF_8636_MAX_LEN;
1629 modinfo->type = ETH_MODULE_SFF_8436;
1630 modinfo->eeprom_len = ETH_MODULE_SFF_8436_MAX_LEN;
1633 case MLX5_MODULE_ID_SFP:
1634 modinfo->type = ETH_MODULE_SFF_8472;
1635 modinfo->eeprom_len = ETH_MODULE_SFF_8472_LEN;
1638 netdev_err(priv->netdev, "%s: cable type not recognized:0x%x\n",
1646 static int mlx5e_get_module_eeprom(struct net_device *netdev,
1647 struct ethtool_eeprom *ee,
1650 struct mlx5e_priv *priv = netdev_priv(netdev);
1651 struct mlx5_core_dev *mdev = priv->mdev;
1652 int offset = ee->offset;
1659 memset(data, 0, ee->len);
1661 while (i < ee->len) {
1662 size_read = mlx5_query_module_eeprom(mdev, offset, ee->len - i,
1669 if (size_read < 0) {
1670 netdev_err(priv->netdev, "%s: mlx5_query_eeprom failed:0x%x\n",
1671 __func__, size_read);
1676 offset += size_read;
1682 int mlx5e_ethtool_flash_device(struct mlx5e_priv *priv,
1683 struct ethtool_flash *flash)
1685 struct mlx5_core_dev *mdev = priv->mdev;
1686 struct net_device *dev = priv->netdev;
1687 const struct firmware *fw;
1690 if (flash->region != ETHTOOL_FLASH_ALL_REGIONS)
1693 err = request_firmware_direct(&fw, flash->data, &dev->dev);
1700 err = mlx5_firmware_flash(mdev, fw, NULL);
1701 release_firmware(fw);
1708 static int mlx5e_flash_device(struct net_device *dev,
1709 struct ethtool_flash *flash)
1711 struct mlx5e_priv *priv = netdev_priv(dev);
1713 return mlx5e_ethtool_flash_device(priv, flash);
1716 static int set_pflag_cqe_based_moder(struct net_device *netdev, bool enable,
1719 struct mlx5e_priv *priv = netdev_priv(netdev);
1720 struct mlx5_core_dev *mdev = priv->mdev;
1721 struct mlx5e_channels new_channels = {};
1723 u8 cq_period_mode, current_cq_period_mode;
1725 cq_period_mode = enable ?
1726 MLX5_CQ_PERIOD_MODE_START_FROM_CQE :
1727 MLX5_CQ_PERIOD_MODE_START_FROM_EQE;
1728 current_cq_period_mode = is_rx_cq ?
1729 priv->channels.params.rx_cq_moderation.cq_period_mode :
1730 priv->channels.params.tx_cq_moderation.cq_period_mode;
1731 mode_changed = cq_period_mode != current_cq_period_mode;
1733 if (cq_period_mode == MLX5_CQ_PERIOD_MODE_START_FROM_CQE &&
1734 !MLX5_CAP_GEN(mdev, cq_period_start_from_cqe))
1740 new_channels.params = priv->channels.params;
1742 mlx5e_set_rx_cq_mode_params(&new_channels.params, cq_period_mode);
1744 mlx5e_set_tx_cq_mode_params(&new_channels.params, cq_period_mode);
1746 if (!test_bit(MLX5E_STATE_OPENED, &priv->state)) {
1747 priv->channels.params = new_channels.params;
1751 return mlx5e_safe_switch_channels(priv, &new_channels, NULL);
1754 static int set_pflag_tx_cqe_based_moder(struct net_device *netdev, bool enable)
1756 return set_pflag_cqe_based_moder(netdev, enable, false);
1759 static int set_pflag_rx_cqe_based_moder(struct net_device *netdev, bool enable)
1761 return set_pflag_cqe_based_moder(netdev, enable, true);
1764 int mlx5e_modify_rx_cqe_compression_locked(struct mlx5e_priv *priv, bool new_val)
1766 bool curr_val = MLX5E_GET_PFLAG(&priv->channels.params, MLX5E_PFLAG_RX_CQE_COMPRESS);
1767 struct mlx5e_channels new_channels = {};
1770 if (!MLX5_CAP_GEN(priv->mdev, cqe_compression))
1771 return new_val ? -EOPNOTSUPP : 0;
1773 if (curr_val == new_val)
1776 new_channels.params = priv->channels.params;
1777 MLX5E_SET_PFLAG(&new_channels.params, MLX5E_PFLAG_RX_CQE_COMPRESS, new_val);
1779 if (!test_bit(MLX5E_STATE_OPENED, &priv->state)) {
1780 priv->channels.params = new_channels.params;
1784 err = mlx5e_safe_switch_channels(priv, &new_channels, NULL);
1788 mlx5e_dbg(DRV, priv, "MLX5E: RxCqeCmprss was turned %s\n",
1789 MLX5E_GET_PFLAG(&priv->channels.params,
1790 MLX5E_PFLAG_RX_CQE_COMPRESS) ? "ON" : "OFF");
1795 static int set_pflag_rx_cqe_compress(struct net_device *netdev,
1798 struct mlx5e_priv *priv = netdev_priv(netdev);
1799 struct mlx5_core_dev *mdev = priv->mdev;
1801 if (!MLX5_CAP_GEN(mdev, cqe_compression))
1804 if (enable && priv->tstamp.rx_filter != HWTSTAMP_FILTER_NONE) {
1805 netdev_err(netdev, "Can't enable cqe compression while timestamping is enabled.\n");
1809 mlx5e_modify_rx_cqe_compression_locked(priv, enable);
1810 priv->channels.params.rx_cqe_compress_def = enable;
1815 static int set_pflag_rx_striding_rq(struct net_device *netdev, bool enable)
1817 struct mlx5e_priv *priv = netdev_priv(netdev);
1818 struct mlx5_core_dev *mdev = priv->mdev;
1819 struct mlx5e_channels new_channels = {};
1822 if (!mlx5e_check_fragmented_striding_rq_cap(mdev))
1824 if (!mlx5e_striding_rq_possible(mdev, &priv->channels.params))
1826 } else if (priv->channels.params.lro_en) {
1827 netdev_warn(netdev, "Can't set legacy RQ with LRO, disable LRO first\n");
1831 new_channels.params = priv->channels.params;
1833 MLX5E_SET_PFLAG(&new_channels.params, MLX5E_PFLAG_RX_STRIDING_RQ, enable);
1834 mlx5e_set_rq_type(mdev, &new_channels.params);
1836 if (!test_bit(MLX5E_STATE_OPENED, &priv->state)) {
1837 priv->channels.params = new_channels.params;
1841 return mlx5e_safe_switch_channels(priv, &new_channels, NULL);
1844 static int set_pflag_rx_no_csum_complete(struct net_device *netdev, bool enable)
1846 struct mlx5e_priv *priv = netdev_priv(netdev);
1847 struct mlx5e_channels *channels = &priv->channels;
1848 struct mlx5e_channel *c;
1851 if (!test_bit(MLX5E_STATE_OPENED, &priv->state) ||
1852 priv->channels.params.xdp_prog)
1855 for (i = 0; i < channels->num; i++) {
1858 __set_bit(MLX5E_RQ_STATE_NO_CSUM_COMPLETE, &c->rq.state);
1860 __clear_bit(MLX5E_RQ_STATE_NO_CSUM_COMPLETE, &c->rq.state);
1866 static int set_pflag_xdp_tx_mpwqe(struct net_device *netdev, bool enable)
1868 struct mlx5e_priv *priv = netdev_priv(netdev);
1869 struct mlx5_core_dev *mdev = priv->mdev;
1870 struct mlx5e_channels new_channels = {};
1873 if (enable && !MLX5_CAP_ETH(mdev, enhanced_multi_pkt_send_wqe))
1876 new_channels.params = priv->channels.params;
1878 MLX5E_SET_PFLAG(&new_channels.params, MLX5E_PFLAG_XDP_TX_MPWQE, enable);
1880 if (!test_bit(MLX5E_STATE_OPENED, &priv->state)) {
1881 priv->channels.params = new_channels.params;
1885 err = mlx5e_safe_switch_channels(priv, &new_channels, NULL);
1889 static const struct pflag_desc mlx5e_priv_flags[MLX5E_NUM_PFLAGS] = {
1890 { "rx_cqe_moder", set_pflag_rx_cqe_based_moder },
1891 { "tx_cqe_moder", set_pflag_tx_cqe_based_moder },
1892 { "rx_cqe_compress", set_pflag_rx_cqe_compress },
1893 { "rx_striding_rq", set_pflag_rx_striding_rq },
1894 { "rx_no_csum_complete", set_pflag_rx_no_csum_complete },
1895 { "xdp_tx_mpwqe", set_pflag_xdp_tx_mpwqe },
1898 static int mlx5e_handle_pflag(struct net_device *netdev,
1900 enum mlx5e_priv_flag flag)
1902 struct mlx5e_priv *priv = netdev_priv(netdev);
1903 bool enable = !!(wanted_flags & BIT(flag));
1904 u32 changes = wanted_flags ^ priv->channels.params.pflags;
1907 if (!(changes & BIT(flag)))
1910 err = mlx5e_priv_flags[flag].handler(netdev, enable);
1912 netdev_err(netdev, "%s private flag '%s' failed err %d\n",
1913 enable ? "Enable" : "Disable", mlx5e_priv_flags[flag].name, err);
1917 MLX5E_SET_PFLAG(&priv->channels.params, flag, enable);
1921 static int mlx5e_set_priv_flags(struct net_device *netdev, u32 pflags)
1923 struct mlx5e_priv *priv = netdev_priv(netdev);
1924 enum mlx5e_priv_flag pflag;
1927 mutex_lock(&priv->state_lock);
1929 for (pflag = 0; pflag < MLX5E_NUM_PFLAGS; pflag++) {
1930 err = mlx5e_handle_pflag(netdev, pflags, pflag);
1935 mutex_unlock(&priv->state_lock);
1937 /* Need to fix some features.. */
1938 netdev_update_features(netdev);
1943 static u32 mlx5e_get_priv_flags(struct net_device *netdev)
1945 struct mlx5e_priv *priv = netdev_priv(netdev);
1947 return priv->channels.params.pflags;
1950 static int mlx5e_get_rxnfc(struct net_device *dev, struct ethtool_rxnfc *info, u32 *rule_locs)
1952 struct mlx5e_priv *priv = netdev_priv(dev);
1954 /* ETHTOOL_GRXRINGS is needed by ethtool -x which is not part
1955 * of rxnfc. We keep this logic out of mlx5e_ethtool_get_rxnfc,
1956 * to avoid breaking "ethtool -x" when mlx5e_ethtool_get_rxnfc
1957 * is compiled out via CONFIG_MLX5_EN_RXNFC=n.
1959 if (info->cmd == ETHTOOL_GRXRINGS) {
1960 info->data = priv->channels.params.num_channels;
1964 return mlx5e_ethtool_get_rxnfc(dev, info, rule_locs);
1967 static int mlx5e_set_rxnfc(struct net_device *dev, struct ethtool_rxnfc *cmd)
1969 return mlx5e_ethtool_set_rxnfc(dev, cmd);
1972 const struct ethtool_ops mlx5e_ethtool_ops = {
1973 .get_drvinfo = mlx5e_get_drvinfo,
1974 .get_link = ethtool_op_get_link,
1975 .get_strings = mlx5e_get_strings,
1976 .get_sset_count = mlx5e_get_sset_count,
1977 .get_ethtool_stats = mlx5e_get_ethtool_stats,
1978 .get_ringparam = mlx5e_get_ringparam,
1979 .set_ringparam = mlx5e_set_ringparam,
1980 .get_channels = mlx5e_get_channels,
1981 .set_channels = mlx5e_set_channels,
1982 .get_coalesce = mlx5e_get_coalesce,
1983 .set_coalesce = mlx5e_set_coalesce,
1984 .get_link_ksettings = mlx5e_get_link_ksettings,
1985 .set_link_ksettings = mlx5e_set_link_ksettings,
1986 .get_rxfh_key_size = mlx5e_get_rxfh_key_size,
1987 .get_rxfh_indir_size = mlx5e_get_rxfh_indir_size,
1988 .get_rxfh = mlx5e_get_rxfh,
1989 .set_rxfh = mlx5e_set_rxfh,
1990 .get_rxnfc = mlx5e_get_rxnfc,
1991 .set_rxnfc = mlx5e_set_rxnfc,
1992 .get_tunable = mlx5e_get_tunable,
1993 .set_tunable = mlx5e_set_tunable,
1994 .get_pauseparam = mlx5e_get_pauseparam,
1995 .set_pauseparam = mlx5e_set_pauseparam,
1996 .get_ts_info = mlx5e_get_ts_info,
1997 .set_phys_id = mlx5e_set_phys_id,
1998 .get_wol = mlx5e_get_wol,
1999 .set_wol = mlx5e_set_wol,
2000 .get_module_info = mlx5e_get_module_info,
2001 .get_module_eeprom = mlx5e_get_module_eeprom,
2002 .flash_device = mlx5e_flash_device,
2003 .get_priv_flags = mlx5e_get_priv_flags,
2004 .set_priv_flags = mlx5e_set_priv_flags,
2005 .self_test = mlx5e_self_test,
2006 .get_msglevel = mlx5e_get_msglevel,
2007 .set_msglevel = mlx5e_set_msglevel,
2008 .get_fecparam = mlx5e_get_fecparam,
2009 .set_fecparam = mlx5e_set_fecparam,