2 * Copyright (c) 2015, Mellanox Technologies. All rights reserved.
4 * This software is available to you under a choice of one of two
5 * licenses. You may choose to be licensed under the terms of the GNU
6 * General Public License (GPL) Version 2, available from the file
7 * COPYING in the main directory of this source tree, or the
8 * OpenIB.org BSD license below:
10 * Redistribution and use in source and binary forms, with or
11 * without modification, are permitted provided that the following
14 * - Redistributions of source code must retain the above
15 * copyright notice, this list of conditions and the following
18 * - Redistributions in binary form must reproduce the above
19 * copyright notice, this list of conditions and the following
20 * disclaimer in the documentation and/or other materials
21 * provided with the distribution.
23 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
24 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
25 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
26 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
27 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
28 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
29 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
35 #include "en/xsk/umem.h"
36 #include "lib/clock.h"
38 void mlx5e_ethtool_get_drvinfo(struct mlx5e_priv *priv,
39 struct ethtool_drvinfo *drvinfo)
41 struct mlx5_core_dev *mdev = priv->mdev;
43 strlcpy(drvinfo->driver, DRIVER_NAME, sizeof(drvinfo->driver));
44 strlcpy(drvinfo->version, DRIVER_VERSION,
45 sizeof(drvinfo->version));
46 snprintf(drvinfo->fw_version, sizeof(drvinfo->fw_version),
48 fw_rev_maj(mdev), fw_rev_min(mdev), fw_rev_sub(mdev),
50 strlcpy(drvinfo->bus_info, dev_name(mdev->device),
51 sizeof(drvinfo->bus_info));
54 static void mlx5e_get_drvinfo(struct net_device *dev,
55 struct ethtool_drvinfo *drvinfo)
57 struct mlx5e_priv *priv = netdev_priv(dev);
59 mlx5e_ethtool_get_drvinfo(priv, drvinfo);
62 struct ptys2ethtool_config {
63 __ETHTOOL_DECLARE_LINK_MODE_MASK(supported);
64 __ETHTOOL_DECLARE_LINK_MODE_MASK(advertised);
68 struct ptys2ethtool_config ptys2legacy_ethtool_table[MLX5E_LINK_MODES_NUMBER];
70 struct ptys2ethtool_config ptys2ext_ethtool_table[MLX5E_EXT_LINK_MODES_NUMBER];
72 #define MLX5_BUILD_PTYS2ETHTOOL_CONFIG(reg_, table, ...) \
74 struct ptys2ethtool_config *cfg; \
75 const unsigned int modes[] = { __VA_ARGS__ }; \
76 unsigned int i, bit, idx; \
77 cfg = &ptys2##table##_ethtool_table[reg_]; \
78 bitmap_zero(cfg->supported, \
79 __ETHTOOL_LINK_MODE_MASK_NBITS); \
80 bitmap_zero(cfg->advertised, \
81 __ETHTOOL_LINK_MODE_MASK_NBITS); \
82 for (i = 0 ; i < ARRAY_SIZE(modes) ; ++i) { \
83 bit = modes[i] % 64; \
84 idx = modes[i] / 64; \
85 __set_bit(bit, &cfg->supported[idx]); \
86 __set_bit(bit, &cfg->advertised[idx]); \
90 void mlx5e_build_ptys2ethtool_map(void)
92 memset(ptys2legacy_ethtool_table, 0, sizeof(ptys2legacy_ethtool_table));
93 memset(ptys2ext_ethtool_table, 0, sizeof(ptys2ext_ethtool_table));
94 MLX5_BUILD_PTYS2ETHTOOL_CONFIG(MLX5E_1000BASE_CX_SGMII, legacy,
95 ETHTOOL_LINK_MODE_1000baseKX_Full_BIT);
96 MLX5_BUILD_PTYS2ETHTOOL_CONFIG(MLX5E_1000BASE_KX, legacy,
97 ETHTOOL_LINK_MODE_1000baseKX_Full_BIT);
98 MLX5_BUILD_PTYS2ETHTOOL_CONFIG(MLX5E_10GBASE_CX4, legacy,
99 ETHTOOL_LINK_MODE_10000baseKX4_Full_BIT);
100 MLX5_BUILD_PTYS2ETHTOOL_CONFIG(MLX5E_10GBASE_KX4, legacy,
101 ETHTOOL_LINK_MODE_10000baseKX4_Full_BIT);
102 MLX5_BUILD_PTYS2ETHTOOL_CONFIG(MLX5E_10GBASE_KR, legacy,
103 ETHTOOL_LINK_MODE_10000baseKR_Full_BIT);
104 MLX5_BUILD_PTYS2ETHTOOL_CONFIG(MLX5E_20GBASE_KR2, legacy,
105 ETHTOOL_LINK_MODE_20000baseKR2_Full_BIT);
106 MLX5_BUILD_PTYS2ETHTOOL_CONFIG(MLX5E_40GBASE_CR4, legacy,
107 ETHTOOL_LINK_MODE_40000baseCR4_Full_BIT);
108 MLX5_BUILD_PTYS2ETHTOOL_CONFIG(MLX5E_40GBASE_KR4, legacy,
109 ETHTOOL_LINK_MODE_40000baseKR4_Full_BIT);
110 MLX5_BUILD_PTYS2ETHTOOL_CONFIG(MLX5E_56GBASE_R4, legacy,
111 ETHTOOL_LINK_MODE_56000baseKR4_Full_BIT);
112 MLX5_BUILD_PTYS2ETHTOOL_CONFIG(MLX5E_10GBASE_CR, legacy,
113 ETHTOOL_LINK_MODE_10000baseKR_Full_BIT);
114 MLX5_BUILD_PTYS2ETHTOOL_CONFIG(MLX5E_10GBASE_SR, legacy,
115 ETHTOOL_LINK_MODE_10000baseKR_Full_BIT);
116 MLX5_BUILD_PTYS2ETHTOOL_CONFIG(MLX5E_10GBASE_ER, legacy,
117 ETHTOOL_LINK_MODE_10000baseKR_Full_BIT);
118 MLX5_BUILD_PTYS2ETHTOOL_CONFIG(MLX5E_40GBASE_SR4, legacy,
119 ETHTOOL_LINK_MODE_40000baseSR4_Full_BIT);
120 MLX5_BUILD_PTYS2ETHTOOL_CONFIG(MLX5E_40GBASE_LR4, legacy,
121 ETHTOOL_LINK_MODE_40000baseLR4_Full_BIT);
122 MLX5_BUILD_PTYS2ETHTOOL_CONFIG(MLX5E_50GBASE_SR2, legacy,
123 ETHTOOL_LINK_MODE_50000baseSR2_Full_BIT);
124 MLX5_BUILD_PTYS2ETHTOOL_CONFIG(MLX5E_100GBASE_CR4, legacy,
125 ETHTOOL_LINK_MODE_100000baseCR4_Full_BIT);
126 MLX5_BUILD_PTYS2ETHTOOL_CONFIG(MLX5E_100GBASE_SR4, legacy,
127 ETHTOOL_LINK_MODE_100000baseSR4_Full_BIT);
128 MLX5_BUILD_PTYS2ETHTOOL_CONFIG(MLX5E_100GBASE_KR4, legacy,
129 ETHTOOL_LINK_MODE_100000baseKR4_Full_BIT);
130 MLX5_BUILD_PTYS2ETHTOOL_CONFIG(MLX5E_100GBASE_LR4, legacy,
131 ETHTOOL_LINK_MODE_100000baseLR4_ER4_Full_BIT);
132 MLX5_BUILD_PTYS2ETHTOOL_CONFIG(MLX5E_10GBASE_T, legacy,
133 ETHTOOL_LINK_MODE_10000baseT_Full_BIT);
134 MLX5_BUILD_PTYS2ETHTOOL_CONFIG(MLX5E_25GBASE_CR, legacy,
135 ETHTOOL_LINK_MODE_25000baseCR_Full_BIT);
136 MLX5_BUILD_PTYS2ETHTOOL_CONFIG(MLX5E_25GBASE_KR, legacy,
137 ETHTOOL_LINK_MODE_25000baseKR_Full_BIT);
138 MLX5_BUILD_PTYS2ETHTOOL_CONFIG(MLX5E_25GBASE_SR, legacy,
139 ETHTOOL_LINK_MODE_25000baseSR_Full_BIT);
140 MLX5_BUILD_PTYS2ETHTOOL_CONFIG(MLX5E_50GBASE_CR2, legacy,
141 ETHTOOL_LINK_MODE_50000baseCR2_Full_BIT);
142 MLX5_BUILD_PTYS2ETHTOOL_CONFIG(MLX5E_50GBASE_KR2, legacy,
143 ETHTOOL_LINK_MODE_50000baseKR2_Full_BIT);
144 MLX5_BUILD_PTYS2ETHTOOL_CONFIG(MLX5E_SGMII_100M, ext,
145 ETHTOOL_LINK_MODE_100baseT_Full_BIT);
146 MLX5_BUILD_PTYS2ETHTOOL_CONFIG(MLX5E_1000BASE_X_SGMII, ext,
147 ETHTOOL_LINK_MODE_1000baseT_Full_BIT,
148 ETHTOOL_LINK_MODE_1000baseKX_Full_BIT,
149 ETHTOOL_LINK_MODE_1000baseX_Full_BIT);
150 MLX5_BUILD_PTYS2ETHTOOL_CONFIG(MLX5E_5GBASE_R, ext,
151 ETHTOOL_LINK_MODE_5000baseT_Full_BIT);
152 MLX5_BUILD_PTYS2ETHTOOL_CONFIG(MLX5E_10GBASE_XFI_XAUI_1, ext,
153 ETHTOOL_LINK_MODE_10000baseT_Full_BIT,
154 ETHTOOL_LINK_MODE_10000baseKR_Full_BIT,
155 ETHTOOL_LINK_MODE_10000baseR_FEC_BIT,
156 ETHTOOL_LINK_MODE_10000baseCR_Full_BIT,
157 ETHTOOL_LINK_MODE_10000baseSR_Full_BIT,
158 ETHTOOL_LINK_MODE_10000baseLR_Full_BIT,
159 ETHTOOL_LINK_MODE_10000baseER_Full_BIT);
160 MLX5_BUILD_PTYS2ETHTOOL_CONFIG(MLX5E_40GBASE_XLAUI_4_XLPPI_4, ext,
161 ETHTOOL_LINK_MODE_40000baseKR4_Full_BIT,
162 ETHTOOL_LINK_MODE_40000baseCR4_Full_BIT,
163 ETHTOOL_LINK_MODE_40000baseSR4_Full_BIT,
164 ETHTOOL_LINK_MODE_40000baseLR4_Full_BIT);
165 MLX5_BUILD_PTYS2ETHTOOL_CONFIG(MLX5E_25GAUI_1_25GBASE_CR_KR, ext,
166 ETHTOOL_LINK_MODE_25000baseCR_Full_BIT,
167 ETHTOOL_LINK_MODE_25000baseKR_Full_BIT,
168 ETHTOOL_LINK_MODE_25000baseSR_Full_BIT);
169 MLX5_BUILD_PTYS2ETHTOOL_CONFIG(MLX5E_50GAUI_2_LAUI_2_50GBASE_CR2_KR2,
171 ETHTOOL_LINK_MODE_50000baseCR2_Full_BIT,
172 ETHTOOL_LINK_MODE_50000baseKR2_Full_BIT,
173 ETHTOOL_LINK_MODE_50000baseSR2_Full_BIT);
174 MLX5_BUILD_PTYS2ETHTOOL_CONFIG(MLX5E_50GAUI_1_LAUI_1_50GBASE_CR_KR, ext,
175 ETHTOOL_LINK_MODE_50000baseKR_Full_BIT,
176 ETHTOOL_LINK_MODE_50000baseSR_Full_BIT,
177 ETHTOOL_LINK_MODE_50000baseCR_Full_BIT,
178 ETHTOOL_LINK_MODE_50000baseLR_ER_FR_Full_BIT,
179 ETHTOOL_LINK_MODE_50000baseDR_Full_BIT);
180 MLX5_BUILD_PTYS2ETHTOOL_CONFIG(MLX5E_CAUI_4_100GBASE_CR4_KR4, ext,
181 ETHTOOL_LINK_MODE_100000baseKR4_Full_BIT,
182 ETHTOOL_LINK_MODE_100000baseSR4_Full_BIT,
183 ETHTOOL_LINK_MODE_100000baseCR4_Full_BIT,
184 ETHTOOL_LINK_MODE_100000baseLR4_ER4_Full_BIT);
185 MLX5_BUILD_PTYS2ETHTOOL_CONFIG(MLX5E_100GAUI_2_100GBASE_CR2_KR2, ext,
186 ETHTOOL_LINK_MODE_100000baseKR2_Full_BIT,
187 ETHTOOL_LINK_MODE_100000baseSR2_Full_BIT,
188 ETHTOOL_LINK_MODE_100000baseCR2_Full_BIT,
189 ETHTOOL_LINK_MODE_100000baseLR2_ER2_FR2_Full_BIT,
190 ETHTOOL_LINK_MODE_100000baseDR2_Full_BIT);
191 MLX5_BUILD_PTYS2ETHTOOL_CONFIG(MLX5E_200GAUI_4_200GBASE_CR4_KR4, ext,
192 ETHTOOL_LINK_MODE_200000baseKR4_Full_BIT,
193 ETHTOOL_LINK_MODE_200000baseSR4_Full_BIT,
194 ETHTOOL_LINK_MODE_200000baseLR4_ER4_FR4_Full_BIT,
195 ETHTOOL_LINK_MODE_200000baseDR4_Full_BIT,
196 ETHTOOL_LINK_MODE_200000baseCR4_Full_BIT);
199 static void mlx5e_ethtool_get_speed_arr(struct mlx5_core_dev *mdev,
200 struct ptys2ethtool_config **arr,
203 bool ext = MLX5_CAP_PCAM_FEATURE(mdev, ptys_extended_ethernet);
205 *arr = ext ? ptys2ext_ethtool_table : ptys2legacy_ethtool_table;
206 *size = ext ? ARRAY_SIZE(ptys2ext_ethtool_table) :
207 ARRAY_SIZE(ptys2legacy_ethtool_table);
210 typedef int (*mlx5e_pflag_handler)(struct net_device *netdev, bool enable);
213 char name[ETH_GSTRING_LEN];
214 mlx5e_pflag_handler handler;
217 static const struct pflag_desc mlx5e_priv_flags[MLX5E_NUM_PFLAGS];
219 int mlx5e_ethtool_get_sset_count(struct mlx5e_priv *priv, int sset)
223 return mlx5e_stats_total_num(priv);
224 case ETH_SS_PRIV_FLAGS:
225 return MLX5E_NUM_PFLAGS;
227 return mlx5e_self_test_num(priv);
234 static int mlx5e_get_sset_count(struct net_device *dev, int sset)
236 struct mlx5e_priv *priv = netdev_priv(dev);
238 return mlx5e_ethtool_get_sset_count(priv, sset);
241 void mlx5e_ethtool_get_strings(struct mlx5e_priv *priv, u32 stringset, u8 *data)
246 case ETH_SS_PRIV_FLAGS:
247 for (i = 0; i < MLX5E_NUM_PFLAGS; i++)
248 strcpy(data + i * ETH_GSTRING_LEN,
249 mlx5e_priv_flags[i].name);
253 for (i = 0; i < mlx5e_self_test_num(priv); i++)
254 strcpy(data + i * ETH_GSTRING_LEN,
255 mlx5e_self_tests[i]);
259 mlx5e_stats_fill_strings(priv, data);
264 static void mlx5e_get_strings(struct net_device *dev, u32 stringset, u8 *data)
266 struct mlx5e_priv *priv = netdev_priv(dev);
268 mlx5e_ethtool_get_strings(priv, stringset, data);
271 void mlx5e_ethtool_get_ethtool_stats(struct mlx5e_priv *priv,
272 struct ethtool_stats *stats, u64 *data)
276 mutex_lock(&priv->state_lock);
277 mlx5e_stats_update(priv);
278 mutex_unlock(&priv->state_lock);
280 mlx5e_stats_fill(priv, data, idx);
283 static void mlx5e_get_ethtool_stats(struct net_device *dev,
284 struct ethtool_stats *stats,
287 struct mlx5e_priv *priv = netdev_priv(dev);
289 mlx5e_ethtool_get_ethtool_stats(priv, stats, data);
292 void mlx5e_ethtool_get_ringparam(struct mlx5e_priv *priv,
293 struct ethtool_ringparam *param)
295 param->rx_max_pending = 1 << MLX5E_PARAMS_MAXIMUM_LOG_RQ_SIZE;
296 param->tx_max_pending = 1 << MLX5E_PARAMS_MAXIMUM_LOG_SQ_SIZE;
297 param->rx_pending = 1 << priv->channels.params.log_rq_mtu_frames;
298 param->tx_pending = 1 << priv->channels.params.log_sq_size;
301 static void mlx5e_get_ringparam(struct net_device *dev,
302 struct ethtool_ringparam *param)
304 struct mlx5e_priv *priv = netdev_priv(dev);
306 mlx5e_ethtool_get_ringparam(priv, param);
309 int mlx5e_ethtool_set_ringparam(struct mlx5e_priv *priv,
310 struct ethtool_ringparam *param)
312 struct mlx5e_channels new_channels = {};
317 if (param->rx_jumbo_pending) {
318 netdev_info(priv->netdev, "%s: rx_jumbo_pending not supported\n",
322 if (param->rx_mini_pending) {
323 netdev_info(priv->netdev, "%s: rx_mini_pending not supported\n",
328 if (param->rx_pending < (1 << MLX5E_PARAMS_MINIMUM_LOG_RQ_SIZE)) {
329 netdev_info(priv->netdev, "%s: rx_pending (%d) < min (%d)\n",
330 __func__, param->rx_pending,
331 1 << MLX5E_PARAMS_MINIMUM_LOG_RQ_SIZE);
335 if (param->tx_pending < (1 << MLX5E_PARAMS_MINIMUM_LOG_SQ_SIZE)) {
336 netdev_info(priv->netdev, "%s: tx_pending (%d) < min (%d)\n",
337 __func__, param->tx_pending,
338 1 << MLX5E_PARAMS_MINIMUM_LOG_SQ_SIZE);
342 log_rq_size = order_base_2(param->rx_pending);
343 log_sq_size = order_base_2(param->tx_pending);
345 if (log_rq_size == priv->channels.params.log_rq_mtu_frames &&
346 log_sq_size == priv->channels.params.log_sq_size)
349 mutex_lock(&priv->state_lock);
351 new_channels.params = priv->channels.params;
352 new_channels.params.log_rq_mtu_frames = log_rq_size;
353 new_channels.params.log_sq_size = log_sq_size;
355 if (!test_bit(MLX5E_STATE_OPENED, &priv->state)) {
356 priv->channels.params = new_channels.params;
360 err = mlx5e_safe_switch_channels(priv, &new_channels, NULL, NULL);
363 mutex_unlock(&priv->state_lock);
368 static int mlx5e_set_ringparam(struct net_device *dev,
369 struct ethtool_ringparam *param)
371 struct mlx5e_priv *priv = netdev_priv(dev);
373 return mlx5e_ethtool_set_ringparam(priv, param);
376 void mlx5e_ethtool_get_channels(struct mlx5e_priv *priv,
377 struct ethtool_channels *ch)
379 mutex_lock(&priv->state_lock);
381 ch->max_combined = priv->max_nch;
382 ch->combined_count = priv->channels.params.num_channels;
383 if (priv->xsk.refcnt) {
384 /* The upper half are XSK queues. */
385 ch->max_combined *= 2;
386 ch->combined_count *= 2;
389 mutex_unlock(&priv->state_lock);
392 static void mlx5e_get_channels(struct net_device *dev,
393 struct ethtool_channels *ch)
395 struct mlx5e_priv *priv = netdev_priv(dev);
397 mlx5e_ethtool_get_channels(priv, ch);
400 int mlx5e_ethtool_set_channels(struct mlx5e_priv *priv,
401 struct ethtool_channels *ch)
403 struct mlx5e_params *cur_params = &priv->channels.params;
404 unsigned int count = ch->combined_count;
405 struct mlx5e_channels new_channels = {};
410 netdev_info(priv->netdev, "%s: combined_count=0 not supported\n",
415 if (cur_params->num_channels == count)
418 mutex_lock(&priv->state_lock);
420 /* Don't allow changing the number of channels if there is an active
421 * XSK, because the numeration of the XSK and regular RQs will change.
423 if (priv->xsk.refcnt) {
425 netdev_err(priv->netdev, "%s: AF_XDP is active, cannot change the number of channels\n",
430 new_channels.params = priv->channels.params;
431 new_channels.params.num_channels = count;
433 if (!test_bit(MLX5E_STATE_OPENED, &priv->state)) {
434 *cur_params = new_channels.params;
435 mlx5e_num_channels_changed(priv);
439 arfs_enabled = priv->netdev->features & NETIF_F_NTUPLE;
441 mlx5e_arfs_disable(priv);
443 /* Switch to new channels, set new parameters and close old ones */
444 err = mlx5e_safe_switch_channels(priv, &new_channels,
445 mlx5e_num_channels_changed_ctx, NULL);
448 int err2 = mlx5e_arfs_enable(priv);
451 netdev_err(priv->netdev, "%s: mlx5e_arfs_enable failed: %d\n",
456 mutex_unlock(&priv->state_lock);
461 static int mlx5e_set_channels(struct net_device *dev,
462 struct ethtool_channels *ch)
464 struct mlx5e_priv *priv = netdev_priv(dev);
466 return mlx5e_ethtool_set_channels(priv, ch);
469 int mlx5e_ethtool_get_coalesce(struct mlx5e_priv *priv,
470 struct ethtool_coalesce *coal)
472 struct dim_cq_moder *rx_moder, *tx_moder;
474 if (!MLX5_CAP_GEN(priv->mdev, cq_moderation))
477 rx_moder = &priv->channels.params.rx_cq_moderation;
478 coal->rx_coalesce_usecs = rx_moder->usec;
479 coal->rx_max_coalesced_frames = rx_moder->pkts;
480 coal->use_adaptive_rx_coalesce = priv->channels.params.rx_dim_enabled;
482 tx_moder = &priv->channels.params.tx_cq_moderation;
483 coal->tx_coalesce_usecs = tx_moder->usec;
484 coal->tx_max_coalesced_frames = tx_moder->pkts;
485 coal->use_adaptive_tx_coalesce = priv->channels.params.tx_dim_enabled;
490 static int mlx5e_get_coalesce(struct net_device *netdev,
491 struct ethtool_coalesce *coal)
493 struct mlx5e_priv *priv = netdev_priv(netdev);
495 return mlx5e_ethtool_get_coalesce(priv, coal);
498 #define MLX5E_MAX_COAL_TIME MLX5_MAX_CQ_PERIOD
499 #define MLX5E_MAX_COAL_FRAMES MLX5_MAX_CQ_COUNT
502 mlx5e_set_priv_channels_coalesce(struct mlx5e_priv *priv, struct ethtool_coalesce *coal)
504 struct mlx5_core_dev *mdev = priv->mdev;
508 for (i = 0; i < priv->channels.num; ++i) {
509 struct mlx5e_channel *c = priv->channels.c[i];
511 for (tc = 0; tc < c->num_tc; tc++) {
512 mlx5_core_modify_cq_moderation(mdev,
514 coal->tx_coalesce_usecs,
515 coal->tx_max_coalesced_frames);
518 mlx5_core_modify_cq_moderation(mdev, &c->rq.cq.mcq,
519 coal->rx_coalesce_usecs,
520 coal->rx_max_coalesced_frames);
524 int mlx5e_ethtool_set_coalesce(struct mlx5e_priv *priv,
525 struct ethtool_coalesce *coal)
527 struct dim_cq_moder *rx_moder, *tx_moder;
528 struct mlx5_core_dev *mdev = priv->mdev;
529 struct mlx5e_channels new_channels = {};
533 if (!MLX5_CAP_GEN(mdev, cq_moderation))
536 if (coal->tx_coalesce_usecs > MLX5E_MAX_COAL_TIME ||
537 coal->rx_coalesce_usecs > MLX5E_MAX_COAL_TIME) {
538 netdev_info(priv->netdev, "%s: maximum coalesce time supported is %lu usecs\n",
539 __func__, MLX5E_MAX_COAL_TIME);
543 if (coal->tx_max_coalesced_frames > MLX5E_MAX_COAL_FRAMES ||
544 coal->rx_max_coalesced_frames > MLX5E_MAX_COAL_FRAMES) {
545 netdev_info(priv->netdev, "%s: maximum coalesced frames supported is %lu\n",
546 __func__, MLX5E_MAX_COAL_FRAMES);
550 mutex_lock(&priv->state_lock);
551 new_channels.params = priv->channels.params;
553 rx_moder = &new_channels.params.rx_cq_moderation;
554 rx_moder->usec = coal->rx_coalesce_usecs;
555 rx_moder->pkts = coal->rx_max_coalesced_frames;
556 new_channels.params.rx_dim_enabled = !!coal->use_adaptive_rx_coalesce;
558 tx_moder = &new_channels.params.tx_cq_moderation;
559 tx_moder->usec = coal->tx_coalesce_usecs;
560 tx_moder->pkts = coal->tx_max_coalesced_frames;
561 new_channels.params.tx_dim_enabled = !!coal->use_adaptive_tx_coalesce;
563 if (!test_bit(MLX5E_STATE_OPENED, &priv->state)) {
564 priv->channels.params = new_channels.params;
569 reset = (!!coal->use_adaptive_rx_coalesce != priv->channels.params.rx_dim_enabled) ||
570 (!!coal->use_adaptive_tx_coalesce != priv->channels.params.tx_dim_enabled);
573 mlx5e_set_priv_channels_coalesce(priv, coal);
574 priv->channels.params = new_channels.params;
578 err = mlx5e_safe_switch_channels(priv, &new_channels, NULL, NULL);
581 mutex_unlock(&priv->state_lock);
585 static int mlx5e_set_coalesce(struct net_device *netdev,
586 struct ethtool_coalesce *coal)
588 struct mlx5e_priv *priv = netdev_priv(netdev);
590 return mlx5e_ethtool_set_coalesce(priv, coal);
593 static void ptys2ethtool_supported_link(struct mlx5_core_dev *mdev,
594 unsigned long *supported_modes,
597 unsigned long proto_cap = eth_proto_cap;
598 struct ptys2ethtool_config *table;
602 mlx5e_ethtool_get_speed_arr(mdev, &table, &max_size);
603 for_each_set_bit(proto, &proto_cap, max_size)
604 bitmap_or(supported_modes, supported_modes,
605 table[proto].supported,
606 __ETHTOOL_LINK_MODE_MASK_NBITS);
609 static void ptys2ethtool_adver_link(unsigned long *advertising_modes,
610 u32 eth_proto_cap, bool ext)
612 unsigned long proto_cap = eth_proto_cap;
613 struct ptys2ethtool_config *table;
617 table = ext ? ptys2ext_ethtool_table : ptys2legacy_ethtool_table;
618 max_size = ext ? ARRAY_SIZE(ptys2ext_ethtool_table) :
619 ARRAY_SIZE(ptys2legacy_ethtool_table);
621 for_each_set_bit(proto, &proto_cap, max_size)
622 bitmap_or(advertising_modes, advertising_modes,
623 table[proto].advertised,
624 __ETHTOOL_LINK_MODE_MASK_NBITS);
627 static const u32 pplm_fec_2_ethtool[] = {
628 [MLX5E_FEC_NOFEC] = ETHTOOL_FEC_OFF,
629 [MLX5E_FEC_FIRECODE] = ETHTOOL_FEC_BASER,
630 [MLX5E_FEC_RS_528_514] = ETHTOOL_FEC_RS,
631 [MLX5E_FEC_RS_544_514] = ETHTOOL_FEC_RS,
632 [MLX5E_FEC_LLRS_272_257_1] = ETHTOOL_FEC_LLRS,
635 static u32 pplm2ethtool_fec(u_long fec_mode, unsigned long size)
640 return ETHTOOL_FEC_AUTO;
642 mode = find_first_bit(&fec_mode, size);
644 if (mode < ARRAY_SIZE(pplm_fec_2_ethtool))
645 return pplm_fec_2_ethtool[mode];
650 #define MLX5E_ADVERTISE_SUPPORTED_FEC(mlx5_fec, ethtool_fec) \
652 if (mlx5e_fec_in_caps(dev, 1 << (mlx5_fec))) \
653 __set_bit(ethtool_fec, \
654 link_ksettings->link_modes.supported);\
657 static const u32 pplm_fec_2_ethtool_linkmodes[] = {
658 [MLX5E_FEC_NOFEC] = ETHTOOL_LINK_MODE_FEC_NONE_BIT,
659 [MLX5E_FEC_FIRECODE] = ETHTOOL_LINK_MODE_FEC_BASER_BIT,
660 [MLX5E_FEC_RS_528_514] = ETHTOOL_LINK_MODE_FEC_RS_BIT,
661 [MLX5E_FEC_RS_544_514] = ETHTOOL_LINK_MODE_FEC_RS_BIT,
662 [MLX5E_FEC_LLRS_272_257_1] = ETHTOOL_LINK_MODE_FEC_LLRS_BIT,
665 static int get_fec_supported_advertised(struct mlx5_core_dev *dev,
666 struct ethtool_link_ksettings *link_ksettings)
668 u_long active_fec = 0;
672 err = mlx5e_get_fec_mode(dev, (u32 *)&active_fec, NULL);
674 return (err == -EOPNOTSUPP) ? 0 : err;
676 MLX5E_ADVERTISE_SUPPORTED_FEC(MLX5E_FEC_NOFEC,
677 ETHTOOL_LINK_MODE_FEC_NONE_BIT);
678 MLX5E_ADVERTISE_SUPPORTED_FEC(MLX5E_FEC_FIRECODE,
679 ETHTOOL_LINK_MODE_FEC_BASER_BIT);
680 MLX5E_ADVERTISE_SUPPORTED_FEC(MLX5E_FEC_RS_528_514,
681 ETHTOOL_LINK_MODE_FEC_RS_BIT);
682 MLX5E_ADVERTISE_SUPPORTED_FEC(MLX5E_FEC_LLRS_272_257_1,
683 ETHTOOL_LINK_MODE_FEC_LLRS_BIT);
685 /* active fec is a bit set, find out which bit is set and
686 * advertise the corresponding ethtool bit
688 bitn = find_first_bit(&active_fec, sizeof(u32) * BITS_PER_BYTE);
689 if (bitn < ARRAY_SIZE(pplm_fec_2_ethtool_linkmodes))
690 __set_bit(pplm_fec_2_ethtool_linkmodes[bitn],
691 link_ksettings->link_modes.advertising);
696 static void ptys2ethtool_supported_advertised_port(struct ethtool_link_ksettings *link_ksettings,
698 u8 connector_type, bool ext)
700 if ((!connector_type && !ext) || connector_type >= MLX5E_CONNECTOR_TYPE_NUMBER) {
701 if (eth_proto_cap & (MLX5E_PROT_MASK(MLX5E_10GBASE_CR)
702 | MLX5E_PROT_MASK(MLX5E_10GBASE_SR)
703 | MLX5E_PROT_MASK(MLX5E_40GBASE_CR4)
704 | MLX5E_PROT_MASK(MLX5E_40GBASE_SR4)
705 | MLX5E_PROT_MASK(MLX5E_100GBASE_SR4)
706 | MLX5E_PROT_MASK(MLX5E_1000BASE_CX_SGMII))) {
707 ethtool_link_ksettings_add_link_mode(link_ksettings,
710 ethtool_link_ksettings_add_link_mode(link_ksettings,
715 if (eth_proto_cap & (MLX5E_PROT_MASK(MLX5E_100GBASE_KR4)
716 | MLX5E_PROT_MASK(MLX5E_40GBASE_KR4)
717 | MLX5E_PROT_MASK(MLX5E_10GBASE_KR)
718 | MLX5E_PROT_MASK(MLX5E_10GBASE_KX4)
719 | MLX5E_PROT_MASK(MLX5E_1000BASE_KX))) {
720 ethtool_link_ksettings_add_link_mode(link_ksettings,
723 ethtool_link_ksettings_add_link_mode(link_ksettings,
730 switch (connector_type) {
732 ethtool_link_ksettings_add_link_mode(link_ksettings,
734 ethtool_link_ksettings_add_link_mode(link_ksettings,
738 ethtool_link_ksettings_add_link_mode(link_ksettings,
740 ethtool_link_ksettings_add_link_mode(link_ksettings,
744 ethtool_link_ksettings_add_link_mode(link_ksettings,
746 ethtool_link_ksettings_add_link_mode(link_ksettings,
750 ethtool_link_ksettings_add_link_mode(link_ksettings,
752 ethtool_link_ksettings_add_link_mode(link_ksettings,
755 case MLX5E_PORT_FIBRE:
756 ethtool_link_ksettings_add_link_mode(link_ksettings,
758 ethtool_link_ksettings_add_link_mode(link_ksettings,
762 ethtool_link_ksettings_add_link_mode(link_ksettings,
763 supported, Backplane);
764 ethtool_link_ksettings_add_link_mode(link_ksettings,
765 advertising, Backplane);
767 case MLX5E_PORT_NONE:
768 case MLX5E_PORT_OTHER:
774 static void get_speed_duplex(struct net_device *netdev,
775 u32 eth_proto_oper, bool force_legacy,
777 struct ethtool_link_ksettings *link_ksettings)
779 struct mlx5e_priv *priv = netdev_priv(netdev);
780 u32 speed = SPEED_UNKNOWN;
781 u8 duplex = DUPLEX_UNKNOWN;
783 if (!netif_carrier_ok(netdev))
786 speed = mlx5e_port_ptys2speed(priv->mdev, eth_proto_oper, force_legacy);
789 speed = 100 * data_rate_oper;
791 speed = SPEED_UNKNOWN;
795 duplex = DUPLEX_FULL;
798 link_ksettings->base.speed = speed;
799 link_ksettings->base.duplex = duplex;
802 static void get_supported(struct mlx5_core_dev *mdev, u32 eth_proto_cap,
803 struct ethtool_link_ksettings *link_ksettings)
805 unsigned long *supported = link_ksettings->link_modes.supported;
806 ptys2ethtool_supported_link(mdev, supported, eth_proto_cap);
808 ethtool_link_ksettings_add_link_mode(link_ksettings, supported, Pause);
811 static void get_advertising(u32 eth_proto_cap, u8 tx_pause, u8 rx_pause,
812 struct ethtool_link_ksettings *link_ksettings,
815 unsigned long *advertising = link_ksettings->link_modes.advertising;
816 ptys2ethtool_adver_link(advertising, eth_proto_cap, ext);
819 ethtool_link_ksettings_add_link_mode(link_ksettings, advertising, Pause);
820 if (tx_pause ^ rx_pause)
821 ethtool_link_ksettings_add_link_mode(link_ksettings, advertising, Asym_Pause);
824 static int ptys2connector_type[MLX5E_CONNECTOR_TYPE_NUMBER] = {
825 [MLX5E_PORT_UNKNOWN] = PORT_OTHER,
826 [MLX5E_PORT_NONE] = PORT_NONE,
827 [MLX5E_PORT_TP] = PORT_TP,
828 [MLX5E_PORT_AUI] = PORT_AUI,
829 [MLX5E_PORT_BNC] = PORT_BNC,
830 [MLX5E_PORT_MII] = PORT_MII,
831 [MLX5E_PORT_FIBRE] = PORT_FIBRE,
832 [MLX5E_PORT_DA] = PORT_DA,
833 [MLX5E_PORT_OTHER] = PORT_OTHER,
836 static u8 get_connector_port(u32 eth_proto, u8 connector_type, bool ext)
838 if ((connector_type || ext) && connector_type < MLX5E_CONNECTOR_TYPE_NUMBER)
839 return ptys2connector_type[connector_type];
842 (MLX5E_PROT_MASK(MLX5E_10GBASE_SR) |
843 MLX5E_PROT_MASK(MLX5E_40GBASE_SR4) |
844 MLX5E_PROT_MASK(MLX5E_100GBASE_SR4) |
845 MLX5E_PROT_MASK(MLX5E_1000BASE_CX_SGMII))) {
850 (MLX5E_PROT_MASK(MLX5E_40GBASE_CR4) |
851 MLX5E_PROT_MASK(MLX5E_10GBASE_CR) |
852 MLX5E_PROT_MASK(MLX5E_100GBASE_CR4))) {
857 (MLX5E_PROT_MASK(MLX5E_10GBASE_KX4) |
858 MLX5E_PROT_MASK(MLX5E_10GBASE_KR) |
859 MLX5E_PROT_MASK(MLX5E_40GBASE_KR4) |
860 MLX5E_PROT_MASK(MLX5E_100GBASE_KR4))) {
867 static void get_lp_advertising(struct mlx5_core_dev *mdev, u32 eth_proto_lp,
868 struct ethtool_link_ksettings *link_ksettings)
870 unsigned long *lp_advertising = link_ksettings->link_modes.lp_advertising;
871 bool ext = MLX5_CAP_PCAM_FEATURE(mdev, ptys_extended_ethernet);
873 ptys2ethtool_adver_link(lp_advertising, eth_proto_lp, ext);
876 int mlx5e_ethtool_get_link_ksettings(struct mlx5e_priv *priv,
877 struct ethtool_link_ksettings *link_ksettings)
879 struct mlx5_core_dev *mdev = priv->mdev;
880 u32 out[MLX5_ST_SZ_DW(ptys_reg)] = {};
895 err = mlx5_query_port_ptys(mdev, out, sizeof(out), MLX5_PTYS_EN, 1);
897 netdev_err(priv->netdev, "%s: query port ptys failed: %d\n",
901 ext = MLX5_CAP_PCAM_FEATURE(mdev, ptys_extended_ethernet);
902 eth_proto_cap = MLX5_GET_ETH_PROTO(ptys_reg, out, ext,
903 eth_proto_capability);
904 eth_proto_admin = MLX5_GET_ETH_PROTO(ptys_reg, out, ext,
906 /* Fields: eth_proto_admin and ext_eth_proto_admin are
907 * mutually exclusive. Hence try reading legacy advertising
908 * when extended advertising is zero.
909 * admin_ext indicates which proto_admin (ext vs. legacy)
910 * should be read and interpreted
913 if (ext && !eth_proto_admin) {
914 eth_proto_admin = MLX5_GET_ETH_PROTO(ptys_reg, out, false,
919 eth_proto_oper = MLX5_GET_ETH_PROTO(ptys_reg, out, admin_ext,
921 eth_proto_lp = MLX5_GET(ptys_reg, out, eth_proto_lp_advertise);
922 an_disable_admin = MLX5_GET(ptys_reg, out, an_disable_admin);
923 an_status = MLX5_GET(ptys_reg, out, an_status);
924 connector_type = MLX5_GET(ptys_reg, out, connector_type);
925 data_rate_oper = MLX5_GET(ptys_reg, out, data_rate_oper);
927 mlx5_query_port_pause(mdev, &rx_pause, &tx_pause);
929 ethtool_link_ksettings_zero_link_mode(link_ksettings, supported);
930 ethtool_link_ksettings_zero_link_mode(link_ksettings, advertising);
932 get_supported(mdev, eth_proto_cap, link_ksettings);
933 get_advertising(eth_proto_admin, tx_pause, rx_pause, link_ksettings,
935 get_speed_duplex(priv->netdev, eth_proto_oper, !admin_ext,
936 data_rate_oper, link_ksettings);
938 eth_proto_oper = eth_proto_oper ? eth_proto_oper : eth_proto_cap;
940 link_ksettings->base.port = get_connector_port(eth_proto_oper,
941 connector_type, ext);
942 ptys2ethtool_supported_advertised_port(link_ksettings, eth_proto_admin,
943 connector_type, ext);
944 get_lp_advertising(mdev, eth_proto_lp, link_ksettings);
946 if (an_status == MLX5_AN_COMPLETE)
947 ethtool_link_ksettings_add_link_mode(link_ksettings,
948 lp_advertising, Autoneg);
950 link_ksettings->base.autoneg = an_disable_admin ? AUTONEG_DISABLE :
952 ethtool_link_ksettings_add_link_mode(link_ksettings, supported,
955 err = get_fec_supported_advertised(mdev, link_ksettings);
957 netdev_dbg(priv->netdev, "%s: FEC caps query failed: %d\n",
959 err = 0; /* don't fail caps query because of FEC error */
962 if (!an_disable_admin)
963 ethtool_link_ksettings_add_link_mode(link_ksettings,
964 advertising, Autoneg);
970 static int mlx5e_get_link_ksettings(struct net_device *netdev,
971 struct ethtool_link_ksettings *link_ksettings)
973 struct mlx5e_priv *priv = netdev_priv(netdev);
975 return mlx5e_ethtool_get_link_ksettings(priv, link_ksettings);
978 static u32 mlx5e_ethtool2ptys_adver_link(const unsigned long *link_modes)
980 u32 i, ptys_modes = 0;
982 for (i = 0; i < MLX5E_LINK_MODES_NUMBER; ++i) {
983 if (*ptys2legacy_ethtool_table[i].advertised == 0)
985 if (bitmap_intersects(ptys2legacy_ethtool_table[i].advertised,
987 __ETHTOOL_LINK_MODE_MASK_NBITS))
988 ptys_modes |= MLX5E_PROT_MASK(i);
994 static u32 mlx5e_ethtool2ptys_ext_adver_link(const unsigned long *link_modes)
996 u32 i, ptys_modes = 0;
997 unsigned long modes[2];
999 for (i = 0; i < MLX5E_EXT_LINK_MODES_NUMBER; ++i) {
1000 if (*ptys2ext_ethtool_table[i].advertised == 0)
1002 memset(modes, 0, sizeof(modes));
1003 bitmap_and(modes, ptys2ext_ethtool_table[i].advertised,
1004 link_modes, __ETHTOOL_LINK_MODE_MASK_NBITS);
1006 if (modes[0] == ptys2ext_ethtool_table[i].advertised[0] &&
1007 modes[1] == ptys2ext_ethtool_table[i].advertised[1])
1008 ptys_modes |= MLX5E_PROT_MASK(i);
1013 static bool ext_link_mode_requested(const unsigned long *adver)
1015 #define MLX5E_MIN_PTYS_EXT_LINK_MODE_BIT ETHTOOL_LINK_MODE_50000baseKR_Full_BIT
1016 int size = __ETHTOOL_LINK_MODE_MASK_NBITS - MLX5E_MIN_PTYS_EXT_LINK_MODE_BIT;
1017 __ETHTOOL_DECLARE_LINK_MODE_MASK(modes) = {0,};
1019 bitmap_set(modes, MLX5E_MIN_PTYS_EXT_LINK_MODE_BIT, size);
1020 return bitmap_intersects(modes, adver, __ETHTOOL_LINK_MODE_MASK_NBITS);
1023 static bool ext_requested(u8 autoneg, const unsigned long *adver, bool ext_supported)
1025 bool ext_link_mode = ext_link_mode_requested(adver);
1027 return autoneg == AUTONEG_ENABLE ? ext_link_mode : ext_supported;
1030 int mlx5e_ethtool_set_link_ksettings(struct mlx5e_priv *priv,
1031 const struct ethtool_link_ksettings *link_ksettings)
1033 struct mlx5_core_dev *mdev = priv->mdev;
1034 struct mlx5e_port_eth_proto eproto;
1035 const unsigned long *adver;
1036 bool an_changes = false;
1037 u8 an_disable_admin;
1048 u32 (*ethtool2ptys_adver_func)(const unsigned long *adver);
1050 adver = link_ksettings->link_modes.advertising;
1051 autoneg = link_ksettings->base.autoneg;
1052 speed = link_ksettings->base.speed;
1054 ext_supported = MLX5_CAP_PCAM_FEATURE(mdev, ptys_extended_ethernet);
1055 ext = ext_requested(autoneg, adver, ext_supported);
1056 if (!ext_supported && ext)
1059 ethtool2ptys_adver_func = ext ? mlx5e_ethtool2ptys_ext_adver_link :
1060 mlx5e_ethtool2ptys_adver_link;
1061 err = mlx5_port_query_eth_proto(mdev, 1, ext, &eproto);
1063 netdev_err(priv->netdev, "%s: query port eth proto failed: %d\n",
1067 link_modes = autoneg == AUTONEG_ENABLE ? ethtool2ptys_adver_func(adver) :
1068 mlx5e_port_speed2linkmodes(mdev, speed, !ext);
1070 if ((link_modes & MLX5E_PROT_MASK(MLX5E_56GBASE_R4)) &&
1071 autoneg != AUTONEG_ENABLE) {
1072 netdev_err(priv->netdev, "%s: 56G link speed requires autoneg enabled\n",
1078 link_modes = link_modes & eproto.cap;
1080 netdev_err(priv->netdev, "%s: Not supported link mode(s) requested",
1086 mlx5_port_query_eth_autoneg(mdev, &an_status, &an_disable_cap,
1089 an_disable = autoneg == AUTONEG_DISABLE;
1090 an_changes = ((!an_disable && an_disable_admin) ||
1091 (an_disable && !an_disable_admin));
1093 if (!an_changes && link_modes == eproto.admin)
1096 mlx5_port_set_eth_ptys(mdev, an_disable, link_modes, ext);
1097 mlx5_toggle_port_link(mdev);
1103 static int mlx5e_set_link_ksettings(struct net_device *netdev,
1104 const struct ethtool_link_ksettings *link_ksettings)
1106 struct mlx5e_priv *priv = netdev_priv(netdev);
1108 return mlx5e_ethtool_set_link_ksettings(priv, link_ksettings);
1111 u32 mlx5e_ethtool_get_rxfh_key_size(struct mlx5e_priv *priv)
1113 return sizeof(priv->rss_params.toeplitz_hash_key);
1116 static u32 mlx5e_get_rxfh_key_size(struct net_device *netdev)
1118 struct mlx5e_priv *priv = netdev_priv(netdev);
1120 return mlx5e_ethtool_get_rxfh_key_size(priv);
1123 u32 mlx5e_ethtool_get_rxfh_indir_size(struct mlx5e_priv *priv)
1125 return MLX5E_INDIR_RQT_SIZE;
1128 static u32 mlx5e_get_rxfh_indir_size(struct net_device *netdev)
1130 struct mlx5e_priv *priv = netdev_priv(netdev);
1132 return mlx5e_ethtool_get_rxfh_indir_size(priv);
1135 int mlx5e_get_rxfh(struct net_device *netdev, u32 *indir, u8 *key,
1138 struct mlx5e_priv *priv = netdev_priv(netdev);
1139 struct mlx5e_rss_params *rss = &priv->rss_params;
1142 memcpy(indir, rss->indirection_rqt,
1143 sizeof(rss->indirection_rqt));
1146 memcpy(key, rss->toeplitz_hash_key,
1147 sizeof(rss->toeplitz_hash_key));
1150 *hfunc = rss->hfunc;
1155 int mlx5e_set_rxfh(struct net_device *dev, const u32 *indir,
1156 const u8 *key, const u8 hfunc)
1158 struct mlx5e_priv *priv = netdev_priv(dev);
1159 struct mlx5e_rss_params *rss = &priv->rss_params;
1160 int inlen = MLX5_ST_SZ_BYTES(modify_tir_in);
1161 bool hash_changed = false;
1164 if ((hfunc != ETH_RSS_HASH_NO_CHANGE) &&
1165 (hfunc != ETH_RSS_HASH_XOR) &&
1166 (hfunc != ETH_RSS_HASH_TOP))
1169 in = kvzalloc(inlen, GFP_KERNEL);
1173 mutex_lock(&priv->state_lock);
1175 if (hfunc != ETH_RSS_HASH_NO_CHANGE && hfunc != rss->hfunc) {
1177 hash_changed = true;
1181 memcpy(rss->indirection_rqt, indir,
1182 sizeof(rss->indirection_rqt));
1184 if (test_bit(MLX5E_STATE_OPENED, &priv->state)) {
1185 u32 rqtn = priv->indir_rqt.rqtn;
1186 struct mlx5e_redirect_rqt_param rrp = {
1190 .hfunc = rss->hfunc,
1191 .channels = &priv->channels,
1196 mlx5e_redirect_rqt(priv, rqtn, MLX5E_INDIR_RQT_SIZE, rrp);
1201 memcpy(rss->toeplitz_hash_key, key,
1202 sizeof(rss->toeplitz_hash_key));
1203 hash_changed = hash_changed || rss->hfunc == ETH_RSS_HASH_TOP;
1207 mlx5e_modify_tirs_hash(priv, in, inlen);
1209 mutex_unlock(&priv->state_lock);
1216 #define MLX5E_PFC_PREVEN_AUTO_TOUT_MSEC 100
1217 #define MLX5E_PFC_PREVEN_TOUT_MAX_MSEC 8000
1218 #define MLX5E_PFC_PREVEN_MINOR_PRECENT 85
1219 #define MLX5E_PFC_PREVEN_TOUT_MIN_MSEC 80
1220 #define MLX5E_DEVICE_STALL_MINOR_WATERMARK(critical_tout) \
1221 max_t(u16, MLX5E_PFC_PREVEN_TOUT_MIN_MSEC, \
1222 (critical_tout * MLX5E_PFC_PREVEN_MINOR_PRECENT) / 100)
1224 static int mlx5e_get_pfc_prevention_tout(struct net_device *netdev,
1225 u16 *pfc_prevention_tout)
1227 struct mlx5e_priv *priv = netdev_priv(netdev);
1228 struct mlx5_core_dev *mdev = priv->mdev;
1230 if (!MLX5_CAP_PCAM_FEATURE((priv)->mdev, pfcc_mask) ||
1231 !MLX5_CAP_DEBUG((priv)->mdev, stall_detect))
1234 return mlx5_query_port_stall_watermark(mdev, pfc_prevention_tout, NULL);
1237 static int mlx5e_set_pfc_prevention_tout(struct net_device *netdev,
1240 struct mlx5e_priv *priv = netdev_priv(netdev);
1241 struct mlx5_core_dev *mdev = priv->mdev;
1245 if (!MLX5_CAP_PCAM_FEATURE((priv)->mdev, pfcc_mask) ||
1246 !MLX5_CAP_DEBUG((priv)->mdev, stall_detect))
1249 critical_tout = (pfc_preven == PFC_STORM_PREVENTION_AUTO) ?
1250 MLX5E_PFC_PREVEN_AUTO_TOUT_MSEC :
1253 if (critical_tout != PFC_STORM_PREVENTION_DISABLE &&
1254 (critical_tout > MLX5E_PFC_PREVEN_TOUT_MAX_MSEC ||
1255 critical_tout < MLX5E_PFC_PREVEN_TOUT_MIN_MSEC)) {
1256 netdev_info(netdev, "%s: pfc prevention tout not in range (%d-%d)\n",
1257 __func__, MLX5E_PFC_PREVEN_TOUT_MIN_MSEC,
1258 MLX5E_PFC_PREVEN_TOUT_MAX_MSEC);
1262 minor = MLX5E_DEVICE_STALL_MINOR_WATERMARK(critical_tout);
1263 return mlx5_set_port_stall_watermark(mdev, critical_tout,
1267 static int mlx5e_get_tunable(struct net_device *dev,
1268 const struct ethtool_tunable *tuna,
1274 case ETHTOOL_PFC_PREVENTION_TOUT:
1275 err = mlx5e_get_pfc_prevention_tout(dev, data);
1285 static int mlx5e_set_tunable(struct net_device *dev,
1286 const struct ethtool_tunable *tuna,
1289 struct mlx5e_priv *priv = netdev_priv(dev);
1292 mutex_lock(&priv->state_lock);
1295 case ETHTOOL_PFC_PREVENTION_TOUT:
1296 err = mlx5e_set_pfc_prevention_tout(dev, *(u16 *)data);
1303 mutex_unlock(&priv->state_lock);
1307 void mlx5e_ethtool_get_pauseparam(struct mlx5e_priv *priv,
1308 struct ethtool_pauseparam *pauseparam)
1310 struct mlx5_core_dev *mdev = priv->mdev;
1313 err = mlx5_query_port_pause(mdev, &pauseparam->rx_pause,
1314 &pauseparam->tx_pause);
1316 netdev_err(priv->netdev, "%s: mlx5_query_port_pause failed:0x%x\n",
1321 static void mlx5e_get_pauseparam(struct net_device *netdev,
1322 struct ethtool_pauseparam *pauseparam)
1324 struct mlx5e_priv *priv = netdev_priv(netdev);
1326 mlx5e_ethtool_get_pauseparam(priv, pauseparam);
1329 int mlx5e_ethtool_set_pauseparam(struct mlx5e_priv *priv,
1330 struct ethtool_pauseparam *pauseparam)
1332 struct mlx5_core_dev *mdev = priv->mdev;
1335 if (!MLX5_CAP_GEN(mdev, vport_group_manager))
1338 if (pauseparam->autoneg)
1341 err = mlx5_set_port_pause(mdev,
1342 pauseparam->rx_pause ? 1 : 0,
1343 pauseparam->tx_pause ? 1 : 0);
1345 netdev_err(priv->netdev, "%s: mlx5_set_port_pause failed:0x%x\n",
1352 static int mlx5e_set_pauseparam(struct net_device *netdev,
1353 struct ethtool_pauseparam *pauseparam)
1355 struct mlx5e_priv *priv = netdev_priv(netdev);
1357 return mlx5e_ethtool_set_pauseparam(priv, pauseparam);
1360 int mlx5e_ethtool_get_ts_info(struct mlx5e_priv *priv,
1361 struct ethtool_ts_info *info)
1363 struct mlx5_core_dev *mdev = priv->mdev;
1365 info->phc_index = mlx5_clock_get_ptp_index(mdev);
1367 if (!MLX5_CAP_GEN(priv->mdev, device_frequency_khz) ||
1368 info->phc_index == -1)
1371 info->so_timestamping = SOF_TIMESTAMPING_TX_HARDWARE |
1372 SOF_TIMESTAMPING_RX_HARDWARE |
1373 SOF_TIMESTAMPING_RAW_HARDWARE;
1375 info->tx_types = BIT(HWTSTAMP_TX_OFF) |
1376 BIT(HWTSTAMP_TX_ON);
1378 info->rx_filters = BIT(HWTSTAMP_FILTER_NONE) |
1379 BIT(HWTSTAMP_FILTER_ALL);
1384 static int mlx5e_get_ts_info(struct net_device *dev,
1385 struct ethtool_ts_info *info)
1387 struct mlx5e_priv *priv = netdev_priv(dev);
1389 return mlx5e_ethtool_get_ts_info(priv, info);
1392 static __u32 mlx5e_get_wol_supported(struct mlx5_core_dev *mdev)
1396 if (MLX5_CAP_GEN(mdev, wol_g))
1399 if (MLX5_CAP_GEN(mdev, wol_s))
1400 ret |= WAKE_MAGICSECURE;
1402 if (MLX5_CAP_GEN(mdev, wol_a))
1405 if (MLX5_CAP_GEN(mdev, wol_b))
1408 if (MLX5_CAP_GEN(mdev, wol_m))
1411 if (MLX5_CAP_GEN(mdev, wol_u))
1414 if (MLX5_CAP_GEN(mdev, wol_p))
1420 static __u32 mlx5e_reformat_wol_mode_mlx5_to_linux(u8 mode)
1424 if (mode & MLX5_WOL_MAGIC)
1427 if (mode & MLX5_WOL_SECURED_MAGIC)
1428 ret |= WAKE_MAGICSECURE;
1430 if (mode & MLX5_WOL_ARP)
1433 if (mode & MLX5_WOL_BROADCAST)
1436 if (mode & MLX5_WOL_MULTICAST)
1439 if (mode & MLX5_WOL_UNICAST)
1442 if (mode & MLX5_WOL_PHY_ACTIVITY)
1448 static u8 mlx5e_reformat_wol_mode_linux_to_mlx5(__u32 mode)
1452 if (mode & WAKE_MAGIC)
1453 ret |= MLX5_WOL_MAGIC;
1455 if (mode & WAKE_MAGICSECURE)
1456 ret |= MLX5_WOL_SECURED_MAGIC;
1458 if (mode & WAKE_ARP)
1459 ret |= MLX5_WOL_ARP;
1461 if (mode & WAKE_BCAST)
1462 ret |= MLX5_WOL_BROADCAST;
1464 if (mode & WAKE_MCAST)
1465 ret |= MLX5_WOL_MULTICAST;
1467 if (mode & WAKE_UCAST)
1468 ret |= MLX5_WOL_UNICAST;
1470 if (mode & WAKE_PHY)
1471 ret |= MLX5_WOL_PHY_ACTIVITY;
1476 static void mlx5e_get_wol(struct net_device *netdev,
1477 struct ethtool_wolinfo *wol)
1479 struct mlx5e_priv *priv = netdev_priv(netdev);
1480 struct mlx5_core_dev *mdev = priv->mdev;
1484 memset(wol, 0, sizeof(*wol));
1486 wol->supported = mlx5e_get_wol_supported(mdev);
1487 if (!wol->supported)
1490 err = mlx5_query_port_wol(mdev, &mlx5_wol_mode);
1494 wol->wolopts = mlx5e_reformat_wol_mode_mlx5_to_linux(mlx5_wol_mode);
1497 static int mlx5e_set_wol(struct net_device *netdev, struct ethtool_wolinfo *wol)
1499 struct mlx5e_priv *priv = netdev_priv(netdev);
1500 struct mlx5_core_dev *mdev = priv->mdev;
1501 __u32 wol_supported = mlx5e_get_wol_supported(mdev);
1507 if (wol->wolopts & ~wol_supported)
1510 mlx5_wol_mode = mlx5e_reformat_wol_mode_linux_to_mlx5(wol->wolopts);
1512 return mlx5_set_port_wol(mdev, mlx5_wol_mode);
1515 static int mlx5e_get_fecparam(struct net_device *netdev,
1516 struct ethtool_fecparam *fecparam)
1518 struct mlx5e_priv *priv = netdev_priv(netdev);
1519 struct mlx5_core_dev *mdev = priv->mdev;
1520 u16 fec_configured = 0;
1524 err = mlx5e_get_fec_mode(mdev, &fec_active, &fec_configured);
1529 fecparam->active_fec = pplm2ethtool_fec((u_long)fec_active,
1530 sizeof(u32) * BITS_PER_BYTE);
1532 if (!fecparam->active_fec)
1535 fecparam->fec = pplm2ethtool_fec((u_long)fec_configured,
1536 sizeof(u16) * BITS_PER_BYTE);
1541 static int mlx5e_set_fecparam(struct net_device *netdev,
1542 struct ethtool_fecparam *fecparam)
1544 struct mlx5e_priv *priv = netdev_priv(netdev);
1545 struct mlx5_core_dev *mdev = priv->mdev;
1550 if (bitmap_weight((unsigned long *)&fecparam->fec,
1551 ETHTOOL_FEC_LLRS_BIT + 1) > 1)
1554 for (mode = 0; mode < ARRAY_SIZE(pplm_fec_2_ethtool); mode++) {
1555 if (!(pplm_fec_2_ethtool[mode] & fecparam->fec))
1557 fec_policy |= (1 << mode);
1561 err = mlx5e_set_fec_mode(mdev, fec_policy);
1566 mlx5_toggle_port_link(mdev);
1571 static u32 mlx5e_get_msglevel(struct net_device *dev)
1573 return ((struct mlx5e_priv *)netdev_priv(dev))->msglevel;
1576 static void mlx5e_set_msglevel(struct net_device *dev, u32 val)
1578 ((struct mlx5e_priv *)netdev_priv(dev))->msglevel = val;
1581 static int mlx5e_set_phys_id(struct net_device *dev,
1582 enum ethtool_phys_id_state state)
1584 struct mlx5e_priv *priv = netdev_priv(dev);
1585 struct mlx5_core_dev *mdev = priv->mdev;
1586 u16 beacon_duration;
1588 if (!MLX5_CAP_GEN(mdev, beacon_led))
1592 case ETHTOOL_ID_ACTIVE:
1593 beacon_duration = MLX5_BEACON_DURATION_INF;
1595 case ETHTOOL_ID_INACTIVE:
1596 beacon_duration = MLX5_BEACON_DURATION_OFF;
1602 return mlx5_set_port_beacon(mdev, beacon_duration);
1605 static int mlx5e_get_module_info(struct net_device *netdev,
1606 struct ethtool_modinfo *modinfo)
1608 struct mlx5e_priv *priv = netdev_priv(netdev);
1609 struct mlx5_core_dev *dev = priv->mdev;
1613 size_read = mlx5_query_module_eeprom(dev, 0, 2, data);
1617 /* data[0] = identifier byte */
1619 case MLX5_MODULE_ID_QSFP:
1620 modinfo->type = ETH_MODULE_SFF_8436;
1621 modinfo->eeprom_len = ETH_MODULE_SFF_8436_MAX_LEN;
1623 case MLX5_MODULE_ID_QSFP_PLUS:
1624 case MLX5_MODULE_ID_QSFP28:
1625 /* data[1] = revision id */
1626 if (data[0] == MLX5_MODULE_ID_QSFP28 || data[1] >= 0x3) {
1627 modinfo->type = ETH_MODULE_SFF_8636;
1628 modinfo->eeprom_len = ETH_MODULE_SFF_8636_MAX_LEN;
1630 modinfo->type = ETH_MODULE_SFF_8436;
1631 modinfo->eeprom_len = ETH_MODULE_SFF_8436_MAX_LEN;
1634 case MLX5_MODULE_ID_SFP:
1635 modinfo->type = ETH_MODULE_SFF_8472;
1636 modinfo->eeprom_len = ETH_MODULE_SFF_8472_LEN;
1639 netdev_err(priv->netdev, "%s: cable type not recognized:0x%x\n",
1647 static int mlx5e_get_module_eeprom(struct net_device *netdev,
1648 struct ethtool_eeprom *ee,
1651 struct mlx5e_priv *priv = netdev_priv(netdev);
1652 struct mlx5_core_dev *mdev = priv->mdev;
1653 int offset = ee->offset;
1660 memset(data, 0, ee->len);
1662 while (i < ee->len) {
1663 size_read = mlx5_query_module_eeprom(mdev, offset, ee->len - i,
1670 if (size_read < 0) {
1671 netdev_err(priv->netdev, "%s: mlx5_query_eeprom failed:0x%x\n",
1672 __func__, size_read);
1677 offset += size_read;
1683 int mlx5e_ethtool_flash_device(struct mlx5e_priv *priv,
1684 struct ethtool_flash *flash)
1686 struct mlx5_core_dev *mdev = priv->mdev;
1687 struct net_device *dev = priv->netdev;
1688 const struct firmware *fw;
1691 if (flash->region != ETHTOOL_FLASH_ALL_REGIONS)
1694 err = request_firmware_direct(&fw, flash->data, &dev->dev);
1701 err = mlx5_firmware_flash(mdev, fw, NULL);
1702 release_firmware(fw);
1709 static int mlx5e_flash_device(struct net_device *dev,
1710 struct ethtool_flash *flash)
1712 struct mlx5e_priv *priv = netdev_priv(dev);
1714 return mlx5e_ethtool_flash_device(priv, flash);
1717 static int set_pflag_cqe_based_moder(struct net_device *netdev, bool enable,
1720 struct mlx5e_priv *priv = netdev_priv(netdev);
1721 struct mlx5_core_dev *mdev = priv->mdev;
1722 struct mlx5e_channels new_channels = {};
1724 u8 cq_period_mode, current_cq_period_mode;
1726 cq_period_mode = enable ?
1727 MLX5_CQ_PERIOD_MODE_START_FROM_CQE :
1728 MLX5_CQ_PERIOD_MODE_START_FROM_EQE;
1729 current_cq_period_mode = is_rx_cq ?
1730 priv->channels.params.rx_cq_moderation.cq_period_mode :
1731 priv->channels.params.tx_cq_moderation.cq_period_mode;
1732 mode_changed = cq_period_mode != current_cq_period_mode;
1734 if (cq_period_mode == MLX5_CQ_PERIOD_MODE_START_FROM_CQE &&
1735 !MLX5_CAP_GEN(mdev, cq_period_start_from_cqe))
1741 new_channels.params = priv->channels.params;
1743 mlx5e_set_rx_cq_mode_params(&new_channels.params, cq_period_mode);
1745 mlx5e_set_tx_cq_mode_params(&new_channels.params, cq_period_mode);
1747 if (!test_bit(MLX5E_STATE_OPENED, &priv->state)) {
1748 priv->channels.params = new_channels.params;
1752 return mlx5e_safe_switch_channels(priv, &new_channels, NULL, NULL);
1755 static int set_pflag_tx_cqe_based_moder(struct net_device *netdev, bool enable)
1757 return set_pflag_cqe_based_moder(netdev, enable, false);
1760 static int set_pflag_rx_cqe_based_moder(struct net_device *netdev, bool enable)
1762 return set_pflag_cqe_based_moder(netdev, enable, true);
1765 int mlx5e_modify_rx_cqe_compression_locked(struct mlx5e_priv *priv, bool new_val)
1767 bool curr_val = MLX5E_GET_PFLAG(&priv->channels.params, MLX5E_PFLAG_RX_CQE_COMPRESS);
1768 struct mlx5e_channels new_channels = {};
1771 if (!MLX5_CAP_GEN(priv->mdev, cqe_compression))
1772 return new_val ? -EOPNOTSUPP : 0;
1774 if (curr_val == new_val)
1777 new_channels.params = priv->channels.params;
1778 MLX5E_SET_PFLAG(&new_channels.params, MLX5E_PFLAG_RX_CQE_COMPRESS, new_val);
1780 if (!test_bit(MLX5E_STATE_OPENED, &priv->state)) {
1781 priv->channels.params = new_channels.params;
1785 err = mlx5e_safe_switch_channels(priv, &new_channels, NULL, NULL);
1789 mlx5e_dbg(DRV, priv, "MLX5E: RxCqeCmprss was turned %s\n",
1790 MLX5E_GET_PFLAG(&priv->channels.params,
1791 MLX5E_PFLAG_RX_CQE_COMPRESS) ? "ON" : "OFF");
1796 static int set_pflag_rx_cqe_compress(struct net_device *netdev,
1799 struct mlx5e_priv *priv = netdev_priv(netdev);
1800 struct mlx5_core_dev *mdev = priv->mdev;
1802 if (!MLX5_CAP_GEN(mdev, cqe_compression))
1805 if (enable && priv->tstamp.rx_filter != HWTSTAMP_FILTER_NONE) {
1806 netdev_err(netdev, "Can't enable cqe compression while timestamping is enabled.\n");
1810 mlx5e_modify_rx_cqe_compression_locked(priv, enable);
1811 priv->channels.params.rx_cqe_compress_def = enable;
1816 static int set_pflag_rx_striding_rq(struct net_device *netdev, bool enable)
1818 struct mlx5e_priv *priv = netdev_priv(netdev);
1819 struct mlx5_core_dev *mdev = priv->mdev;
1820 struct mlx5e_channels new_channels = {};
1823 if (!mlx5e_check_fragmented_striding_rq_cap(mdev))
1825 if (!mlx5e_striding_rq_possible(mdev, &priv->channels.params))
1827 } else if (priv->channels.params.lro_en) {
1828 netdev_warn(netdev, "Can't set legacy RQ with LRO, disable LRO first\n");
1832 new_channels.params = priv->channels.params;
1834 MLX5E_SET_PFLAG(&new_channels.params, MLX5E_PFLAG_RX_STRIDING_RQ, enable);
1835 mlx5e_set_rq_type(mdev, &new_channels.params);
1837 if (!test_bit(MLX5E_STATE_OPENED, &priv->state)) {
1838 priv->channels.params = new_channels.params;
1842 return mlx5e_safe_switch_channels(priv, &new_channels, NULL, NULL);
1845 static int set_pflag_rx_no_csum_complete(struct net_device *netdev, bool enable)
1847 struct mlx5e_priv *priv = netdev_priv(netdev);
1848 struct mlx5e_channels *channels = &priv->channels;
1849 struct mlx5e_channel *c;
1852 if (!test_bit(MLX5E_STATE_OPENED, &priv->state) ||
1853 priv->channels.params.xdp_prog)
1856 for (i = 0; i < channels->num; i++) {
1859 __set_bit(MLX5E_RQ_STATE_NO_CSUM_COMPLETE, &c->rq.state);
1861 __clear_bit(MLX5E_RQ_STATE_NO_CSUM_COMPLETE, &c->rq.state);
1867 static int set_pflag_xdp_tx_mpwqe(struct net_device *netdev, bool enable)
1869 struct mlx5e_priv *priv = netdev_priv(netdev);
1870 struct mlx5_core_dev *mdev = priv->mdev;
1871 struct mlx5e_channels new_channels = {};
1874 if (enable && !MLX5_CAP_ETH(mdev, enhanced_multi_pkt_send_wqe))
1877 new_channels.params = priv->channels.params;
1879 MLX5E_SET_PFLAG(&new_channels.params, MLX5E_PFLAG_XDP_TX_MPWQE, enable);
1881 if (!test_bit(MLX5E_STATE_OPENED, &priv->state)) {
1882 priv->channels.params = new_channels.params;
1886 err = mlx5e_safe_switch_channels(priv, &new_channels, NULL, NULL);
1890 static const struct pflag_desc mlx5e_priv_flags[MLX5E_NUM_PFLAGS] = {
1891 { "rx_cqe_moder", set_pflag_rx_cqe_based_moder },
1892 { "tx_cqe_moder", set_pflag_tx_cqe_based_moder },
1893 { "rx_cqe_compress", set_pflag_rx_cqe_compress },
1894 { "rx_striding_rq", set_pflag_rx_striding_rq },
1895 { "rx_no_csum_complete", set_pflag_rx_no_csum_complete },
1896 { "xdp_tx_mpwqe", set_pflag_xdp_tx_mpwqe },
1899 static int mlx5e_handle_pflag(struct net_device *netdev,
1901 enum mlx5e_priv_flag flag)
1903 struct mlx5e_priv *priv = netdev_priv(netdev);
1904 bool enable = !!(wanted_flags & BIT(flag));
1905 u32 changes = wanted_flags ^ priv->channels.params.pflags;
1908 if (!(changes & BIT(flag)))
1911 err = mlx5e_priv_flags[flag].handler(netdev, enable);
1913 netdev_err(netdev, "%s private flag '%s' failed err %d\n",
1914 enable ? "Enable" : "Disable", mlx5e_priv_flags[flag].name, err);
1918 MLX5E_SET_PFLAG(&priv->channels.params, flag, enable);
1922 static int mlx5e_set_priv_flags(struct net_device *netdev, u32 pflags)
1924 struct mlx5e_priv *priv = netdev_priv(netdev);
1925 enum mlx5e_priv_flag pflag;
1928 mutex_lock(&priv->state_lock);
1930 for (pflag = 0; pflag < MLX5E_NUM_PFLAGS; pflag++) {
1931 err = mlx5e_handle_pflag(netdev, pflags, pflag);
1936 mutex_unlock(&priv->state_lock);
1938 /* Need to fix some features.. */
1939 netdev_update_features(netdev);
1944 static u32 mlx5e_get_priv_flags(struct net_device *netdev)
1946 struct mlx5e_priv *priv = netdev_priv(netdev);
1948 return priv->channels.params.pflags;
1951 int mlx5e_get_rxnfc(struct net_device *dev, struct ethtool_rxnfc *info,
1954 struct mlx5e_priv *priv = netdev_priv(dev);
1956 /* ETHTOOL_GRXRINGS is needed by ethtool -x which is not part
1957 * of rxnfc. We keep this logic out of mlx5e_ethtool_get_rxnfc,
1958 * to avoid breaking "ethtool -x" when mlx5e_ethtool_get_rxnfc
1959 * is compiled out via CONFIG_MLX5_EN_RXNFC=n.
1961 if (info->cmd == ETHTOOL_GRXRINGS) {
1962 info->data = priv->channels.params.num_channels;
1966 return mlx5e_ethtool_get_rxnfc(dev, info, rule_locs);
1969 int mlx5e_set_rxnfc(struct net_device *dev, struct ethtool_rxnfc *cmd)
1971 return mlx5e_ethtool_set_rxnfc(dev, cmd);
1974 const struct ethtool_ops mlx5e_ethtool_ops = {
1975 .supported_coalesce_params = ETHTOOL_COALESCE_USECS |
1976 ETHTOOL_COALESCE_MAX_FRAMES |
1977 ETHTOOL_COALESCE_USE_ADAPTIVE,
1978 .get_drvinfo = mlx5e_get_drvinfo,
1979 .get_link = ethtool_op_get_link,
1980 .get_strings = mlx5e_get_strings,
1981 .get_sset_count = mlx5e_get_sset_count,
1982 .get_ethtool_stats = mlx5e_get_ethtool_stats,
1983 .get_ringparam = mlx5e_get_ringparam,
1984 .set_ringparam = mlx5e_set_ringparam,
1985 .get_channels = mlx5e_get_channels,
1986 .set_channels = mlx5e_set_channels,
1987 .get_coalesce = mlx5e_get_coalesce,
1988 .set_coalesce = mlx5e_set_coalesce,
1989 .get_link_ksettings = mlx5e_get_link_ksettings,
1990 .set_link_ksettings = mlx5e_set_link_ksettings,
1991 .get_rxfh_key_size = mlx5e_get_rxfh_key_size,
1992 .get_rxfh_indir_size = mlx5e_get_rxfh_indir_size,
1993 .get_rxfh = mlx5e_get_rxfh,
1994 .set_rxfh = mlx5e_set_rxfh,
1995 .get_rxnfc = mlx5e_get_rxnfc,
1996 .set_rxnfc = mlx5e_set_rxnfc,
1997 .get_tunable = mlx5e_get_tunable,
1998 .set_tunable = mlx5e_set_tunable,
1999 .get_pauseparam = mlx5e_get_pauseparam,
2000 .set_pauseparam = mlx5e_set_pauseparam,
2001 .get_ts_info = mlx5e_get_ts_info,
2002 .set_phys_id = mlx5e_set_phys_id,
2003 .get_wol = mlx5e_get_wol,
2004 .set_wol = mlx5e_set_wol,
2005 .get_module_info = mlx5e_get_module_info,
2006 .get_module_eeprom = mlx5e_get_module_eeprom,
2007 .flash_device = mlx5e_flash_device,
2008 .get_priv_flags = mlx5e_get_priv_flags,
2009 .set_priv_flags = mlx5e_set_priv_flags,
2010 .self_test = mlx5e_self_test,
2011 .get_msglevel = mlx5e_get_msglevel,
2012 .set_msglevel = mlx5e_set_msglevel,
2013 .get_fecparam = mlx5e_get_fecparam,
2014 .set_fecparam = mlx5e_set_fecparam,