drivers/net/ethernet/mellanox/mlx5/core/en_ethtool.c

   1 /*
   2  * Copyright (c) 2015, Mellanox Technologies. All rights reserved.
   3  *
   4  * This software is available to you under a choice of one of two
   5  * licenses.  You may choose to be licensed under the terms of the GNU
   6  * General Public License (GPL) Version 2, available from the file
   7  * COPYING in the main directory of this source tree, or the
   8  * OpenIB.org BSD license below:
   9  *
  10  *     Redistribution and use in source and binary forms, with or
  11  *     without modification, are permitted provided that the following
  12  *     conditions are met:
  13  *
  14  *      - Redistributions of source code must retain the above
  15  *        copyright notice, this list of conditions and the following
  16  *        disclaimer.
  17  *
  18  *      - Redistributions in binary form must reproduce the above
  19  *        copyright notice, this list of conditions and the following
  20  *        disclaimer in the documentation and/or other materials
  21  *        provided with the distribution.
  22  *
  23  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  24  * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  25  * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
  26  * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
  27  * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
  28  * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
  29  * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
  30  * SOFTWARE.
  31  */
  32
  33 #include "en.h"
  34 #include "en/port.h"
  35 #include "en/params.h"
  36 #include "en/xsk/pool.h"
  37 #include "lib/clock.h"
  38
  39 void mlx5e_ethtool_get_drvinfo(struct mlx5e_priv *priv,
  40                                struct ethtool_drvinfo *drvinfo)
  41 {
  42         struct mlx5_core_dev *mdev = priv->mdev;
  43
  44         strlcpy(drvinfo->driver, KBUILD_MODNAME, sizeof(drvinfo->driver));
  45         snprintf(drvinfo->fw_version, sizeof(drvinfo->fw_version),
  46                  "%d.%d.%04d (%.16s)",
  47                  fw_rev_maj(mdev), fw_rev_min(mdev), fw_rev_sub(mdev),
  48                  mdev->board_id);
  49         strlcpy(drvinfo->bus_info, dev_name(mdev->device),
  50                 sizeof(drvinfo->bus_info));
  51 }
  52
  53 static void mlx5e_get_drvinfo(struct net_device *dev,
  54                               struct ethtool_drvinfo *drvinfo)
  55 {
  56         struct mlx5e_priv *priv = netdev_priv(dev);
  57
  58         mlx5e_ethtool_get_drvinfo(priv, drvinfo);
  59 }
  60
  61 struct ptys2ethtool_config {
  62         __ETHTOOL_DECLARE_LINK_MODE_MASK(supported);
  63         __ETHTOOL_DECLARE_LINK_MODE_MASK(advertised);
  64 };
  65
  66 static
  67 struct ptys2ethtool_config ptys2legacy_ethtool_table[MLX5E_LINK_MODES_NUMBER];
  68 static
  69 struct ptys2ethtool_config ptys2ext_ethtool_table[MLX5E_EXT_LINK_MODES_NUMBER];
  70
  71 #define MLX5_BUILD_PTYS2ETHTOOL_CONFIG(reg_, table, ...)                  \
  72         ({                                                              \
  73                 struct ptys2ethtool_config *cfg;                        \
  74                 const unsigned int modes[] = { __VA_ARGS__ };           \
  75                 unsigned int i, bit, idx;                               \
  76                 cfg = &ptys2##table##_ethtool_table[reg_];              \
  77                 bitmap_zero(cfg->supported,                             \
  78                             __ETHTOOL_LINK_MODE_MASK_NBITS);            \
  79                 bitmap_zero(cfg->advertised,                            \
  80                             __ETHTOOL_LINK_MODE_MASK_NBITS);            \
  81                 for (i = 0 ; i < ARRAY_SIZE(modes) ; ++i) {             \
  82                         bit = modes[i] % 64;                            \
  83                         idx = modes[i] / 64;                            \
  84                         __set_bit(bit, &cfg->supported[idx]);           \
  85                         __set_bit(bit, &cfg->advertised[idx]);          \
  86                 }                                                       \
  87         })
  88
  89 void mlx5e_build_ptys2ethtool_map(void)
  90 {
  91         memset(ptys2legacy_ethtool_table, 0, sizeof(ptys2legacy_ethtool_table));
  92         memset(ptys2ext_ethtool_table, 0, sizeof(ptys2ext_ethtool_table));
  93         MLX5_BUILD_PTYS2ETHTOOL_CONFIG(MLX5E_1000BASE_CX_SGMII, legacy,
  94                                        ETHTOOL_LINK_MODE_1000baseKX_Full_BIT);
  95         MLX5_BUILD_PTYS2ETHTOOL_CONFIG(MLX5E_1000BASE_KX, legacy,
  96                                        ETHTOOL_LINK_MODE_1000baseKX_Full_BIT);
  97         MLX5_BUILD_PTYS2ETHTOOL_CONFIG(MLX5E_10GBASE_CX4, legacy,
  98                                        ETHTOOL_LINK_MODE_10000baseKX4_Full_BIT);
  99         MLX5_BUILD_PTYS2ETHTOOL_CONFIG(MLX5E_10GBASE_KX4, legacy,
 100                                        ETHTOOL_LINK_MODE_10000baseKX4_Full_BIT);
 101         MLX5_BUILD_PTYS2ETHTOOL_CONFIG(MLX5E_10GBASE_KR, legacy,
 102                                        ETHTOOL_LINK_MODE_10000baseKR_Full_BIT);
 103         MLX5_BUILD_PTYS2ETHTOOL_CONFIG(MLX5E_20GBASE_KR2, legacy,
 104                                        ETHTOOL_LINK_MODE_20000baseKR2_Full_BIT);
 105         MLX5_BUILD_PTYS2ETHTOOL_CONFIG(MLX5E_40GBASE_CR4, legacy,
 106                                        ETHTOOL_LINK_MODE_40000baseCR4_Full_BIT);
 107         MLX5_BUILD_PTYS2ETHTOOL_CONFIG(MLX5E_40GBASE_KR4, legacy,
 108                                        ETHTOOL_LINK_MODE_40000baseKR4_Full_BIT);
 109         MLX5_BUILD_PTYS2ETHTOOL_CONFIG(MLX5E_56GBASE_R4, legacy,
 110                                        ETHTOOL_LINK_MODE_56000baseKR4_Full_BIT);
 111         MLX5_BUILD_PTYS2ETHTOOL_CONFIG(MLX5E_10GBASE_CR, legacy,
 112                                        ETHTOOL_LINK_MODE_10000baseKR_Full_BIT);
 113         MLX5_BUILD_PTYS2ETHTOOL_CONFIG(MLX5E_10GBASE_SR, legacy,
 114                                        ETHTOOL_LINK_MODE_10000baseKR_Full_BIT);
 115         MLX5_BUILD_PTYS2ETHTOOL_CONFIG(MLX5E_10GBASE_ER, legacy,
 116                                        ETHTOOL_LINK_MODE_10000baseKR_Full_BIT);
 117         MLX5_BUILD_PTYS2ETHTOOL_CONFIG(MLX5E_40GBASE_SR4, legacy,
 118                                        ETHTOOL_LINK_MODE_40000baseSR4_Full_BIT);
 119         MLX5_BUILD_PTYS2ETHTOOL_CONFIG(MLX5E_40GBASE_LR4, legacy,
 120                                        ETHTOOL_LINK_MODE_40000baseLR4_Full_BIT);
 121         MLX5_BUILD_PTYS2ETHTOOL_CONFIG(MLX5E_50GBASE_SR2, legacy,
 122                                        ETHTOOL_LINK_MODE_50000baseSR2_Full_BIT);
 123         MLX5_BUILD_PTYS2ETHTOOL_CONFIG(MLX5E_100GBASE_CR4, legacy,
 124                                        ETHTOOL_LINK_MODE_100000baseCR4_Full_BIT);
 125         MLX5_BUILD_PTYS2ETHTOOL_CONFIG(MLX5E_100GBASE_SR4, legacy,
 126                                        ETHTOOL_LINK_MODE_100000baseSR4_Full_BIT);
 127         MLX5_BUILD_PTYS2ETHTOOL_CONFIG(MLX5E_100GBASE_KR4, legacy,
 128                                        ETHTOOL_LINK_MODE_100000baseKR4_Full_BIT);
 129         MLX5_BUILD_PTYS2ETHTOOL_CONFIG(MLX5E_100GBASE_LR4, legacy,
 130                                        ETHTOOL_LINK_MODE_100000baseLR4_ER4_Full_BIT);
 131         MLX5_BUILD_PTYS2ETHTOOL_CONFIG(MLX5E_10GBASE_T, legacy,
 132                                        ETHTOOL_LINK_MODE_10000baseT_Full_BIT);
 133         MLX5_BUILD_PTYS2ETHTOOL_CONFIG(MLX5E_25GBASE_CR, legacy,
 134                                        ETHTOOL_LINK_MODE_25000baseCR_Full_BIT);
 135         MLX5_BUILD_PTYS2ETHTOOL_CONFIG(MLX5E_25GBASE_KR, legacy,
 136                                        ETHTOOL_LINK_MODE_25000baseKR_Full_BIT);
 137         MLX5_BUILD_PTYS2ETHTOOL_CONFIG(MLX5E_25GBASE_SR, legacy,
 138                                        ETHTOOL_LINK_MODE_25000baseSR_Full_BIT);
 139         MLX5_BUILD_PTYS2ETHTOOL_CONFIG(MLX5E_50GBASE_CR2, legacy,
 140                                        ETHTOOL_LINK_MODE_50000baseCR2_Full_BIT);
 141         MLX5_BUILD_PTYS2ETHTOOL_CONFIG(MLX5E_50GBASE_KR2, legacy,
 142                                        ETHTOOL_LINK_MODE_50000baseKR2_Full_BIT);
 143         MLX5_BUILD_PTYS2ETHTOOL_CONFIG(MLX5E_SGMII_100M, ext,
 144                                        ETHTOOL_LINK_MODE_100baseT_Full_BIT);
 145         MLX5_BUILD_PTYS2ETHTOOL_CONFIG(MLX5E_1000BASE_X_SGMII, ext,
 146                                        ETHTOOL_LINK_MODE_1000baseT_Full_BIT,
 147                                        ETHTOOL_LINK_MODE_1000baseKX_Full_BIT,
 148                                        ETHTOOL_LINK_MODE_1000baseX_Full_BIT);
 149         MLX5_BUILD_PTYS2ETHTOOL_CONFIG(MLX5E_5GBASE_R, ext,
 150                                        ETHTOOL_LINK_MODE_5000baseT_Full_BIT);
 151         MLX5_BUILD_PTYS2ETHTOOL_CONFIG(MLX5E_10GBASE_XFI_XAUI_1, ext,
 152                                        ETHTOOL_LINK_MODE_10000baseT_Full_BIT,
 153                                        ETHTOOL_LINK_MODE_10000baseKR_Full_BIT,
 154                                        ETHTOOL_LINK_MODE_10000baseR_FEC_BIT,
 155                                        ETHTOOL_LINK_MODE_10000baseCR_Full_BIT,
 156                                        ETHTOOL_LINK_MODE_10000baseSR_Full_BIT,
 157                                        ETHTOOL_LINK_MODE_10000baseLR_Full_BIT,
 158                                        ETHTOOL_LINK_MODE_10000baseER_Full_BIT);
 159         MLX5_BUILD_PTYS2ETHTOOL_CONFIG(MLX5E_40GBASE_XLAUI_4_XLPPI_4, ext,
 160                                        ETHTOOL_LINK_MODE_40000baseKR4_Full_BIT,
 161                                        ETHTOOL_LINK_MODE_40000baseCR4_Full_BIT,
 162                                        ETHTOOL_LINK_MODE_40000baseSR4_Full_BIT,
 163                                        ETHTOOL_LINK_MODE_40000baseLR4_Full_BIT);
 164         MLX5_BUILD_PTYS2ETHTOOL_CONFIG(MLX5E_25GAUI_1_25GBASE_CR_KR, ext,
 165                                        ETHTOOL_LINK_MODE_25000baseCR_Full_BIT,
 166                                        ETHTOOL_LINK_MODE_25000baseKR_Full_BIT,
 167                                        ETHTOOL_LINK_MODE_25000baseSR_Full_BIT);
 168         MLX5_BUILD_PTYS2ETHTOOL_CONFIG(MLX5E_50GAUI_2_LAUI_2_50GBASE_CR2_KR2,
 169                                        ext,
 170                                        ETHTOOL_LINK_MODE_50000baseCR2_Full_BIT,
 171                                        ETHTOOL_LINK_MODE_50000baseKR2_Full_BIT,
 172                                        ETHTOOL_LINK_MODE_50000baseSR2_Full_BIT);
 173         MLX5_BUILD_PTYS2ETHTOOL_CONFIG(MLX5E_50GAUI_1_LAUI_1_50GBASE_CR_KR, ext,
 174                                        ETHTOOL_LINK_MODE_50000baseKR_Full_BIT,
 175                                        ETHTOOL_LINK_MODE_50000baseSR_Full_BIT,
 176                                        ETHTOOL_LINK_MODE_50000baseCR_Full_BIT,
 177                                        ETHTOOL_LINK_MODE_50000baseLR_ER_FR_Full_BIT,
 178                                        ETHTOOL_LINK_MODE_50000baseDR_Full_BIT);
 179         MLX5_BUILD_PTYS2ETHTOOL_CONFIG(MLX5E_CAUI_4_100GBASE_CR4_KR4, ext,
 180                                        ETHTOOL_LINK_MODE_100000baseKR4_Full_BIT,
 181                                        ETHTOOL_LINK_MODE_100000baseSR4_Full_BIT,
 182                                        ETHTOOL_LINK_MODE_100000baseCR4_Full_BIT,
 183                                        ETHTOOL_LINK_MODE_100000baseLR4_ER4_Full_BIT);
 184         MLX5_BUILD_PTYS2ETHTOOL_CONFIG(MLX5E_100GAUI_2_100GBASE_CR2_KR2, ext,
 185                                        ETHTOOL_LINK_MODE_100000baseKR2_Full_BIT,
 186                                        ETHTOOL_LINK_MODE_100000baseSR2_Full_BIT,
 187                                        ETHTOOL_LINK_MODE_100000baseCR2_Full_BIT,
 188                                        ETHTOOL_LINK_MODE_100000baseLR2_ER2_FR2_Full_BIT,
 189                                        ETHTOOL_LINK_MODE_100000baseDR2_Full_BIT);
 190         MLX5_BUILD_PTYS2ETHTOOL_CONFIG(MLX5E_200GAUI_4_200GBASE_CR4_KR4, ext,
 191                                        ETHTOOL_LINK_MODE_200000baseKR4_Full_BIT,
 192                                        ETHTOOL_LINK_MODE_200000baseSR4_Full_BIT,
 193                                        ETHTOOL_LINK_MODE_200000baseLR4_ER4_FR4_Full_BIT,
 194                                        ETHTOOL_LINK_MODE_200000baseDR4_Full_BIT,
 195                                        ETHTOOL_LINK_MODE_200000baseCR4_Full_BIT);
 196         MLX5_BUILD_PTYS2ETHTOOL_CONFIG(MLX5E_100GAUI_1_100GBASE_CR_KR, ext,
 197                                        ETHTOOL_LINK_MODE_100000baseKR_Full_BIT,
 198                                        ETHTOOL_LINK_MODE_100000baseSR_Full_BIT,
 199                                        ETHTOOL_LINK_MODE_100000baseLR_ER_FR_Full_BIT,
 200                                        ETHTOOL_LINK_MODE_100000baseDR_Full_BIT,
 201                                        ETHTOOL_LINK_MODE_100000baseCR_Full_BIT);
 202         MLX5_BUILD_PTYS2ETHTOOL_CONFIG(MLX5E_200GAUI_2_200GBASE_CR2_KR2, ext,
 203                                        ETHTOOL_LINK_MODE_200000baseKR2_Full_BIT,
 204                                        ETHTOOL_LINK_MODE_200000baseSR2_Full_BIT,
 205                                        ETHTOOL_LINK_MODE_200000baseLR2_ER2_FR2_Full_BIT,
 206                                        ETHTOOL_LINK_MODE_200000baseDR2_Full_BIT,
 207                                        ETHTOOL_LINK_MODE_200000baseCR2_Full_BIT);
 208         MLX5_BUILD_PTYS2ETHTOOL_CONFIG(MLX5E_400GAUI_4_400GBASE_CR4_KR4, ext,
 209                                        ETHTOOL_LINK_MODE_400000baseKR4_Full_BIT,
 210                                        ETHTOOL_LINK_MODE_400000baseSR4_Full_BIT,
 211                                        ETHTOOL_LINK_MODE_400000baseLR4_ER4_FR4_Full_BIT,
 212                                        ETHTOOL_LINK_MODE_400000baseDR4_Full_BIT,
 213                                        ETHTOOL_LINK_MODE_400000baseCR4_Full_BIT);
 214 }
 215
 216 static void mlx5e_ethtool_get_speed_arr(struct mlx5_core_dev *mdev,
 217                                         struct ptys2ethtool_config **arr,
 218                                         u32 *size)
 219 {
 220         bool ext = mlx5e_ptys_ext_supported(mdev);
 221
 222         *arr = ext ? ptys2ext_ethtool_table : ptys2legacy_ethtool_table;
 223         *size = ext ? ARRAY_SIZE(ptys2ext_ethtool_table) :
 224                       ARRAY_SIZE(ptys2legacy_ethtool_table);
 225 }
 226
 227 typedef int (*mlx5e_pflag_handler)(struct net_device *netdev, bool enable);
 228
 229 struct pflag_desc {
 230         char name[ETH_GSTRING_LEN];
 231         mlx5e_pflag_handler handler;
 232 };
 233
 234 static const struct pflag_desc mlx5e_priv_flags[MLX5E_NUM_PFLAGS];
 235
 236 int mlx5e_ethtool_get_sset_count(struct mlx5e_priv *priv, int sset)
 237 {
 238         switch (sset) {
 239         case ETH_SS_STATS:
 240                 return mlx5e_stats_total_num(priv);
 241         case ETH_SS_PRIV_FLAGS:
 242                 return MLX5E_NUM_PFLAGS;
 243         case ETH_SS_TEST:
 244                 return mlx5e_self_test_num(priv);
 245         default:
 246                 return -EOPNOTSUPP;
 247         }
 248 }
 249
 250 static int mlx5e_get_sset_count(struct net_device *dev, int sset)
 251 {
 252         struct mlx5e_priv *priv = netdev_priv(dev);
 253
 254         return mlx5e_ethtool_get_sset_count(priv, sset);
 255 }
 256
 257 void mlx5e_ethtool_get_strings(struct mlx5e_priv *priv, u32 stringset, u8 *data)
 258 {
 259         int i;
 260
 261         switch (stringset) {
 262         case ETH_SS_PRIV_FLAGS:
 263                 for (i = 0; i < MLX5E_NUM_PFLAGS; i++)
 264                         strcpy(data + i * ETH_GSTRING_LEN,
 265                                mlx5e_priv_flags[i].name);
 266                 break;
 267
 268         case ETH_SS_TEST:
 269                 for (i = 0; i < mlx5e_self_test_num(priv); i++)
 270                         strcpy(data + i * ETH_GSTRING_LEN,
 271                                mlx5e_self_tests[i]);
 272                 break;
 273
 274         case ETH_SS_STATS:
 275                 mlx5e_stats_fill_strings(priv, data);
 276                 break;
 277         }
 278 }
 279
 280 static void mlx5e_get_strings(struct net_device *dev, u32 stringset, u8 *data)
 281 {
 282         struct mlx5e_priv *priv = netdev_priv(dev);
 283
 284         mlx5e_ethtool_get_strings(priv, stringset, data);
 285 }
 286
 287 void mlx5e_ethtool_get_ethtool_stats(struct mlx5e_priv *priv,
 288                                      struct ethtool_stats *stats, u64 *data)
 289 {
 290         int idx = 0;
 291
 292         mutex_lock(&priv->state_lock);
 293         mlx5e_stats_update(priv);
 294         mutex_unlock(&priv->state_lock);
 295
 296         mlx5e_stats_fill(priv, data, idx);
 297 }
 298
 299 static void mlx5e_get_ethtool_stats(struct net_device *dev,
 300                                     struct ethtool_stats *stats,
 301                                     u64 *data)
 302 {
 303         struct mlx5e_priv *priv = netdev_priv(dev);
 304
 305         mlx5e_ethtool_get_ethtool_stats(priv, stats, data);
 306 }
 307
 308 void mlx5e_ethtool_get_ringparam(struct mlx5e_priv *priv,
 309                                  struct ethtool_ringparam *param)
 310 {
 311         param->rx_max_pending = 1 << MLX5E_PARAMS_MAXIMUM_LOG_RQ_SIZE;
 312         param->tx_max_pending = 1 << MLX5E_PARAMS_MAXIMUM_LOG_SQ_SIZE;
 313         param->rx_pending     = 1 << priv->channels.params.log_rq_mtu_frames;
 314         param->tx_pending     = 1 << priv->channels.params.log_sq_size;
 315 }
 316
 317 static void mlx5e_get_ringparam(struct net_device *dev,
 318                                 struct ethtool_ringparam *param)
 319 {
 320         struct mlx5e_priv *priv = netdev_priv(dev);
 321
 322         mlx5e_ethtool_get_ringparam(priv, param);
 323 }
 324
 325 int mlx5e_ethtool_set_ringparam(struct mlx5e_priv *priv,
 326                                 struct ethtool_ringparam *param)
 327 {
 328         struct mlx5e_channels new_channels = {};
 329         u8 log_rq_size;
 330         u8 log_sq_size;
 331         int err = 0;
 332
 333         if (param->rx_jumbo_pending) {
 334                 netdev_info(priv->netdev, "%s: rx_jumbo_pending not supported\n",
 335                             __func__);
 336                 return -EINVAL;
 337         }
 338         if (param->rx_mini_pending) {
 339                 netdev_info(priv->netdev, "%s: rx_mini_pending not supported\n",
 340                             __func__);
 341                 return -EINVAL;
 342         }
 343
 344         if (param->rx_pending < (1 << MLX5E_PARAMS_MINIMUM_LOG_RQ_SIZE)) {
 345                 netdev_info(priv->netdev, "%s: rx_pending (%d) < min (%d)\n",
 346                             __func__, param->rx_pending,
 347                             1 << MLX5E_PARAMS_MINIMUM_LOG_RQ_SIZE);
 348                 return -EINVAL;
 349         }
 350
 351         if (param->tx_pending < (1 << MLX5E_PARAMS_MINIMUM_LOG_SQ_SIZE)) {
 352                 netdev_info(priv->netdev, "%s: tx_pending (%d) < min (%d)\n",
 353                             __func__, param->tx_pending,
 354                             1 << MLX5E_PARAMS_MINIMUM_LOG_SQ_SIZE);
 355                 return -EINVAL;
 356         }
 357
 358         log_rq_size = order_base_2(param->rx_pending);
 359         log_sq_size = order_base_2(param->tx_pending);
 360
 361         if (log_rq_size == priv->channels.params.log_rq_mtu_frames &&
 362             log_sq_size == priv->channels.params.log_sq_size)
 363                 return 0;
 364
 365         mutex_lock(&priv->state_lock);
 366
 367         new_channels.params = priv->channels.params;
 368         new_channels.params.log_rq_mtu_frames = log_rq_size;
 369         new_channels.params.log_sq_size = log_sq_size;
 370
 371         err = mlx5e_validate_params(priv, &new_channels.params);
 372         if (err)
 373                 goto unlock;
 374
 375         if (!test_bit(MLX5E_STATE_OPENED, &priv->state)) {
 376                 priv->channels.params = new_channels.params;
 377                 goto unlock;
 378         }
 379
 380         err = mlx5e_safe_switch_channels(priv, &new_channels, NULL, NULL);
 381
 382 unlock:
 383         mutex_unlock(&priv->state_lock);
 384
 385         return err;
 386 }
 387
 388 static int mlx5e_set_ringparam(struct net_device *dev,
 389                                struct ethtool_ringparam *param)
 390 {
 391         struct mlx5e_priv *priv = netdev_priv(dev);
 392
 393         return mlx5e_ethtool_set_ringparam(priv, param);
 394 }
 395
 396 void mlx5e_ethtool_get_channels(struct mlx5e_priv *priv,
 397                                 struct ethtool_channels *ch)
 398 {
 399         mutex_lock(&priv->state_lock);
 400
 401         ch->max_combined   = priv->max_nch;
 402         ch->combined_count = priv->channels.params.num_channels;
 403         if (priv->xsk.refcnt) {
 404                 /* The upper half are XSK queues. */
 405                 ch->max_combined *= 2;
 406                 ch->combined_count *= 2;
 407         }
 408
 409         mutex_unlock(&priv->state_lock);
 410 }
 411
 412 static void mlx5e_get_channels(struct net_device *dev,
 413                                struct ethtool_channels *ch)
 414 {
 415         struct mlx5e_priv *priv = netdev_priv(dev);
 416
 417         mlx5e_ethtool_get_channels(priv, ch);
 418 }
 419
 420 int mlx5e_ethtool_set_channels(struct mlx5e_priv *priv,
 421                                struct ethtool_channels *ch)
 422 {
 423         struct mlx5e_params *cur_params = &priv->channels.params;
 424         unsigned int count = ch->combined_count;
 425         struct mlx5e_channels new_channels = {};
 426         bool arfs_enabled;
 427         int err = 0;
 428
 429         if (!count) {
 430                 netdev_info(priv->netdev, "%s: combined_count=0 not supported\n",
 431                             __func__);
 432                 return -EINVAL;
 433         }
 434
 435         if (cur_params->num_channels == count)
 436                 return 0;
 437
 438         mutex_lock(&priv->state_lock);
 439
 440         /* Don't allow changing the number of channels if there is an active
 441          * XSK, because the numeration of the XSK and regular RQs will change.
 442          */
 443         if (priv->xsk.refcnt) {
 444                 err = -EINVAL;
 445                 netdev_err(priv->netdev, "%s: AF_XDP is active, cannot change the number of channels\n",
 446                            __func__);
 447                 goto out;
 448         }
 449
 450         /* Don't allow changing the number of channels if HTB offload is active,
 451          * because the numeration of the QoS SQs will change, while per-queue
 452          * qdiscs are attached.
 453          */
 454         if (priv->htb.maj_id) {
 455                 err = -EINVAL;
 456                 netdev_err(priv->netdev, "%s: HTB offload is active, cannot change the number of channels\n",
 457                            __func__);
 458                 goto out;
 459         }
 460
 461         new_channels.params = *cur_params;
 462         new_channels.params.num_channels = count;
 463
 464         if (!test_bit(MLX5E_STATE_OPENED, &priv->state)) {
 465                 struct mlx5e_params old_params;
 466
 467                 old_params = *cur_params;
 468                 *cur_params = new_channels.params;
 469                 err = mlx5e_num_channels_changed(priv);
 470                 if (err)
 471                         *cur_params = old_params;
 472
 473                 goto out;
 474         }
 475
 476         arfs_enabled = priv->netdev->features & NETIF_F_NTUPLE;
 477         if (arfs_enabled)
 478                 mlx5e_arfs_disable(priv);
 479
 480         /* Switch to new channels, set new parameters and close old ones */
 481         err = mlx5e_safe_switch_channels(priv, &new_channels,
 482                                          mlx5e_num_channels_changed_ctx, NULL);
 483
 484         if (arfs_enabled) {
 485                 int err2 = mlx5e_arfs_enable(priv);
 486
 487                 if (err2)
 488                         netdev_err(priv->netdev, "%s: mlx5e_arfs_enable failed: %d\n",
 489                                    __func__, err2);
 490         }
 491
 492 out:
 493         mutex_unlock(&priv->state_lock);
 494
 495         return err;
 496 }
 497
 498 static int mlx5e_set_channels(struct net_device *dev,
 499                               struct ethtool_channels *ch)
 500 {
 501         struct mlx5e_priv *priv = netdev_priv(dev);
 502
 503         return mlx5e_ethtool_set_channels(priv, ch);
 504 }
 505
 506 int mlx5e_ethtool_get_coalesce(struct mlx5e_priv *priv,
 507                                struct ethtool_coalesce *coal)
 508 {
 509         struct dim_cq_moder *rx_moder, *tx_moder;
 510
 511         if (!MLX5_CAP_GEN(priv->mdev, cq_moderation))
 512                 return -EOPNOTSUPP;
 513
 514         rx_moder = &priv->channels.params.rx_cq_moderation;
 515         coal->rx_coalesce_usecs         = rx_moder->usec;
 516         coal->rx_max_coalesced_frames   = rx_moder->pkts;
 517         coal->use_adaptive_rx_coalesce  = priv->channels.params.rx_dim_enabled;
 518
 519         tx_moder = &priv->channels.params.tx_cq_moderation;
 520         coal->tx_coalesce_usecs         = tx_moder->usec;
 521         coal->tx_max_coalesced_frames   = tx_moder->pkts;
 522         coal->use_adaptive_tx_coalesce  = priv->channels.params.tx_dim_enabled;
 523
 524         return 0;
 525 }
 526
 527 static int mlx5e_get_coalesce(struct net_device *netdev,
 528                               struct ethtool_coalesce *coal)
 529 {
 530         struct mlx5e_priv *priv = netdev_priv(netdev);
 531
 532         return mlx5e_ethtool_get_coalesce(priv, coal);
 533 }
 534
 535 #define MLX5E_MAX_COAL_TIME             MLX5_MAX_CQ_PERIOD
 536 #define MLX5E_MAX_COAL_FRAMES           MLX5_MAX_CQ_COUNT
 537
 538 static void
 539 mlx5e_set_priv_channels_coalesce(struct mlx5e_priv *priv, struct ethtool_coalesce *coal)
 540 {
 541         struct mlx5_core_dev *mdev = priv->mdev;
 542         int tc;
 543         int i;
 544
 545         for (i = 0; i < priv->channels.num; ++i) {
 546                 struct mlx5e_channel *c = priv->channels.c[i];
 547
 548                 for (tc = 0; tc < c->num_tc; tc++) {
 549                         mlx5_core_modify_cq_moderation(mdev,
 550                                                 &c->sq[tc].cq.mcq,
 551                                                 coal->tx_coalesce_usecs,
 552                                                 coal->tx_max_coalesced_frames);
 553                 }
 554
 555                 mlx5_core_modify_cq_moderation(mdev, &c->rq.cq.mcq,
 556                                                coal->rx_coalesce_usecs,
 557                                                coal->rx_max_coalesced_frames);
 558         }
 559 }
 560
 561 int mlx5e_ethtool_set_coalesce(struct mlx5e_priv *priv,
 562                                struct ethtool_coalesce *coal)
 563 {
 564         struct dim_cq_moder *rx_moder, *tx_moder;
 565         struct mlx5_core_dev *mdev = priv->mdev;
 566         struct mlx5e_channels new_channels = {};
 567         bool reset_rx, reset_tx;
 568         int err = 0;
 569
 570         if (!MLX5_CAP_GEN(mdev, cq_moderation))
 571                 return -EOPNOTSUPP;
 572
 573         if (coal->tx_coalesce_usecs > MLX5E_MAX_COAL_TIME ||
 574             coal->rx_coalesce_usecs > MLX5E_MAX_COAL_TIME) {
 575                 netdev_info(priv->netdev, "%s: maximum coalesce time supported is %lu usecs\n",
 576                             __func__, MLX5E_MAX_COAL_TIME);
 577                 return -ERANGE;
 578         }
 579
 580         if (coal->tx_max_coalesced_frames > MLX5E_MAX_COAL_FRAMES ||
 581             coal->rx_max_coalesced_frames > MLX5E_MAX_COAL_FRAMES) {
 582                 netdev_info(priv->netdev, "%s: maximum coalesced frames supported is %lu\n",
 583                             __func__, MLX5E_MAX_COAL_FRAMES);
 584                 return -ERANGE;
 585         }
 586
 587         mutex_lock(&priv->state_lock);
 588         new_channels.params = priv->channels.params;
 589
 590         rx_moder          = &new_channels.params.rx_cq_moderation;
 591         rx_moder->usec    = coal->rx_coalesce_usecs;
 592         rx_moder->pkts    = coal->rx_max_coalesced_frames;
 593         new_channels.params.rx_dim_enabled = !!coal->use_adaptive_rx_coalesce;
 594
 595         tx_moder          = &new_channels.params.tx_cq_moderation;
 596         tx_moder->usec    = coal->tx_coalesce_usecs;
 597         tx_moder->pkts    = coal->tx_max_coalesced_frames;
 598         new_channels.params.tx_dim_enabled = !!coal->use_adaptive_tx_coalesce;
 599
 600         if (!test_bit(MLX5E_STATE_OPENED, &priv->state)) {
 601                 priv->channels.params = new_channels.params;
 602                 goto out;
 603         }
 604         /* we are opened */
 605
 606         reset_rx = !!coal->use_adaptive_rx_coalesce != priv->channels.params.rx_dim_enabled;
 607         reset_tx = !!coal->use_adaptive_tx_coalesce != priv->channels.params.tx_dim_enabled;
 608
 609         if (!reset_rx && !reset_tx) {
 610                 mlx5e_set_priv_channels_coalesce(priv, coal);
 611                 priv->channels.params = new_channels.params;
 612                 goto out;
 613         }
 614
 615         if (reset_rx) {
 616                 u8 mode = MLX5E_GET_PFLAG(&new_channels.params,
 617                                           MLX5E_PFLAG_RX_CQE_BASED_MODER);
 618
 619                 mlx5e_reset_rx_moderation(&new_channels.params, mode);
 620         }
 621         if (reset_tx) {
 622                 u8 mode = MLX5E_GET_PFLAG(&new_channels.params,
 623                                           MLX5E_PFLAG_TX_CQE_BASED_MODER);
 624
 625                 mlx5e_reset_tx_moderation(&new_channels.params, mode);
 626         }
 627
 628         err = mlx5e_safe_switch_channels(priv, &new_channels, NULL, NULL);
 629
 630 out:
 631         mutex_unlock(&priv->state_lock);
 632         return err;
 633 }
 634
 635 static int mlx5e_set_coalesce(struct net_device *netdev,
 636                               struct ethtool_coalesce *coal)
 637 {
 638         struct mlx5e_priv *priv    = netdev_priv(netdev);
 639
 640         return mlx5e_ethtool_set_coalesce(priv, coal);
 641 }
 642
 643 static void ptys2ethtool_supported_link(struct mlx5_core_dev *mdev,
 644                                         unsigned long *supported_modes,
 645                                         u32 eth_proto_cap)
 646 {
 647         unsigned long proto_cap = eth_proto_cap;
 648         struct ptys2ethtool_config *table;
 649         u32 max_size;
 650         int proto;
 651
 652         mlx5e_ethtool_get_speed_arr(mdev, &table, &max_size);
 653         for_each_set_bit(proto, &proto_cap, max_size)
 654                 bitmap_or(supported_modes, supported_modes,
 655                           table[proto].supported,
 656                           __ETHTOOL_LINK_MODE_MASK_NBITS);
 657 }
 658
 659 static void ptys2ethtool_adver_link(unsigned long *advertising_modes,
 660                                     u32 eth_proto_cap, bool ext)
 661 {
 662         unsigned long proto_cap = eth_proto_cap;
 663         struct ptys2ethtool_config *table;
 664         u32 max_size;
 665         int proto;
 666
 667         table = ext ? ptys2ext_ethtool_table : ptys2legacy_ethtool_table;
 668         max_size = ext ? ARRAY_SIZE(ptys2ext_ethtool_table) :
 669                          ARRAY_SIZE(ptys2legacy_ethtool_table);
 670
 671         for_each_set_bit(proto, &proto_cap, max_size)
 672                 bitmap_or(advertising_modes, advertising_modes,
 673                           table[proto].advertised,
 674                           __ETHTOOL_LINK_MODE_MASK_NBITS);
 675 }
 676
 677 static const u32 pplm_fec_2_ethtool[] = {
 678         [MLX5E_FEC_NOFEC] = ETHTOOL_FEC_OFF,
 679         [MLX5E_FEC_FIRECODE] = ETHTOOL_FEC_BASER,
 680         [MLX5E_FEC_RS_528_514] = ETHTOOL_FEC_RS,
 681         [MLX5E_FEC_RS_544_514] = ETHTOOL_FEC_RS,
 682         [MLX5E_FEC_LLRS_272_257_1] = ETHTOOL_FEC_LLRS,
 683 };
 684
 685 static u32 pplm2ethtool_fec(u_long fec_mode, unsigned long size)
 686 {
 687         int mode = 0;
 688
 689         if (!fec_mode)
 690                 return ETHTOOL_FEC_AUTO;
 691
 692         mode = find_first_bit(&fec_mode, size);
 693
 694         if (mode < ARRAY_SIZE(pplm_fec_2_ethtool))
 695                 return pplm_fec_2_ethtool[mode];
 696
 697         return 0;
 698 }
 699
 700 #define MLX5E_ADVERTISE_SUPPORTED_FEC(mlx5_fec, ethtool_fec)            \
 701         do {                                                            \
 702                 if (mlx5e_fec_in_caps(dev, 1 << (mlx5_fec)))            \
 703                         __set_bit(ethtool_fec,                          \
 704                                   link_ksettings->link_modes.supported);\
 705         } while (0)
 706
 707 static const u32 pplm_fec_2_ethtool_linkmodes[] = {
 708         [MLX5E_FEC_NOFEC] = ETHTOOL_LINK_MODE_FEC_NONE_BIT,
 709         [MLX5E_FEC_FIRECODE] = ETHTOOL_LINK_MODE_FEC_BASER_BIT,
 710         [MLX5E_FEC_RS_528_514] = ETHTOOL_LINK_MODE_FEC_RS_BIT,
 711         [MLX5E_FEC_RS_544_514] = ETHTOOL_LINK_MODE_FEC_RS_BIT,
 712         [MLX5E_FEC_LLRS_272_257_1] = ETHTOOL_LINK_MODE_FEC_LLRS_BIT,
 713 };
 714
 715 static int get_fec_supported_advertised(struct mlx5_core_dev *dev,
 716                                         struct ethtool_link_ksettings *link_ksettings)
 717 {
 718         unsigned long active_fec_long;
 719         u32 active_fec;
 720         u32 bitn;
 721         int err;
 722
 723         err = mlx5e_get_fec_mode(dev, &active_fec, NULL);
 724         if (err)
 725                 return (err == -EOPNOTSUPP) ? 0 : err;
 726
 727         MLX5E_ADVERTISE_SUPPORTED_FEC(MLX5E_FEC_NOFEC,
 728                                       ETHTOOL_LINK_MODE_FEC_NONE_BIT);
 729         MLX5E_ADVERTISE_SUPPORTED_FEC(MLX5E_FEC_FIRECODE,
 730                                       ETHTOOL_LINK_MODE_FEC_BASER_BIT);
 731         MLX5E_ADVERTISE_SUPPORTED_FEC(MLX5E_FEC_RS_528_514,
 732                                       ETHTOOL_LINK_MODE_FEC_RS_BIT);
 733         MLX5E_ADVERTISE_SUPPORTED_FEC(MLX5E_FEC_LLRS_272_257_1,
 734                                       ETHTOOL_LINK_MODE_FEC_LLRS_BIT);
 735
 736         active_fec_long = active_fec;
 737         /* active fec is a bit set, find out which bit is set and
 738          * advertise the corresponding ethtool bit
 739          */
 740         bitn = find_first_bit(&active_fec_long, sizeof(active_fec_long) * BITS_PER_BYTE);
 741         if (bitn < ARRAY_SIZE(pplm_fec_2_ethtool_linkmodes))
 742                 __set_bit(pplm_fec_2_ethtool_linkmodes[bitn],
 743                           link_ksettings->link_modes.advertising);
 744
 745         return 0;
 746 }
 747
 748 static void ptys2ethtool_supported_advertised_port(struct ethtool_link_ksettings *link_ksettings,
 749                                                    u32 eth_proto_cap,
 750                                                    u8 connector_type, bool ext)
 751 {
 752         if ((!connector_type && !ext) || connector_type >= MLX5E_CONNECTOR_TYPE_NUMBER) {
 753                 if (eth_proto_cap & (MLX5E_PROT_MASK(MLX5E_10GBASE_CR)
 754                                    | MLX5E_PROT_MASK(MLX5E_10GBASE_SR)
 755                                    | MLX5E_PROT_MASK(MLX5E_40GBASE_CR4)
 756                                    | MLX5E_PROT_MASK(MLX5E_40GBASE_SR4)
 757                                    | MLX5E_PROT_MASK(MLX5E_100GBASE_SR4)
 758                                    | MLX5E_PROT_MASK(MLX5E_1000BASE_CX_SGMII))) {
 759                         ethtool_link_ksettings_add_link_mode(link_ksettings,
 760                                                              supported,
 761                                                              FIBRE);
 762                         ethtool_link_ksettings_add_link_mode(link_ksettings,
 763                                                              advertising,
 764                                                              FIBRE);
 765                 }
 766
 767                 if (eth_proto_cap & (MLX5E_PROT_MASK(MLX5E_100GBASE_KR4)
 768                                    | MLX5E_PROT_MASK(MLX5E_40GBASE_KR4)
 769                                    | MLX5E_PROT_MASK(MLX5E_10GBASE_KR)
 770                                    | MLX5E_PROT_MASK(MLX5E_10GBASE_KX4)
 771                                    | MLX5E_PROT_MASK(MLX5E_1000BASE_KX))) {
 772                         ethtool_link_ksettings_add_link_mode(link_ksettings,
 773                                                              supported,
 774                                                              Backplane);
 775                         ethtool_link_ksettings_add_link_mode(link_ksettings,
 776                                                              advertising,
 777                                                              Backplane);
 778                 }
 779                 return;
 780         }
 781
 782         switch (connector_type) {
 783         case MLX5E_PORT_TP:
 784                 ethtool_link_ksettings_add_link_mode(link_ksettings,
 785                                                      supported, TP);
 786                 ethtool_link_ksettings_add_link_mode(link_ksettings,
 787                                                      advertising, TP);
 788                 break;
 789         case MLX5E_PORT_AUI:
 790                 ethtool_link_ksettings_add_link_mode(link_ksettings,
 791                                                      supported, AUI);
 792                 ethtool_link_ksettings_add_link_mode(link_ksettings,
 793                                                      advertising, AUI);
 794                 break;
 795         case MLX5E_PORT_BNC:
 796                 ethtool_link_ksettings_add_link_mode(link_ksettings,
 797                                                      supported, BNC);
 798                 ethtool_link_ksettings_add_link_mode(link_ksettings,
 799                                                      advertising, BNC);
 800                 break;
 801         case MLX5E_PORT_MII:
 802                 ethtool_link_ksettings_add_link_mode(link_ksettings,
 803                                                      supported, MII);
 804                 ethtool_link_ksettings_add_link_mode(link_ksettings,
 805                                                      advertising, MII);
 806                 break;
 807         case MLX5E_PORT_FIBRE:
 808                 ethtool_link_ksettings_add_link_mode(link_ksettings,
 809                                                      supported, FIBRE);
 810                 ethtool_link_ksettings_add_link_mode(link_ksettings,
 811                                                      advertising, FIBRE);
 812                 break;
 813         case MLX5E_PORT_DA:
 814                 ethtool_link_ksettings_add_link_mode(link_ksettings,
 815                                                      supported, Backplane);
 816                 ethtool_link_ksettings_add_link_mode(link_ksettings,
 817                                                      advertising, Backplane);
 818                 break;
 819         case MLX5E_PORT_NONE:
 820         case MLX5E_PORT_OTHER:
 821         default:
 822                 break;
 823         }
 824 }
 825
 826 static void get_speed_duplex(struct net_device *netdev,
 827                              u32 eth_proto_oper, bool force_legacy,
 828                              u16 data_rate_oper,
 829                              struct ethtool_link_ksettings *link_ksettings)
 830 {
 831         struct mlx5e_priv *priv = netdev_priv(netdev);
 832         u32 speed = SPEED_UNKNOWN;
 833         u8 duplex = DUPLEX_UNKNOWN;
 834
 835         if (!netif_carrier_ok(netdev))
 836                 goto out;
 837
 838         speed = mlx5e_port_ptys2speed(priv->mdev, eth_proto_oper, force_legacy);
 839         if (!speed) {
 840                 if (data_rate_oper)
 841                         speed = 100 * data_rate_oper;
 842                 else
 843                         speed = SPEED_UNKNOWN;
 844                 goto out;
 845         }
 846
 847         duplex = DUPLEX_FULL;
 848
 849 out:
 850         link_ksettings->base.speed = speed;
 851         link_ksettings->base.duplex = duplex;
 852 }
 853
 854 static void get_supported(struct mlx5_core_dev *mdev, u32 eth_proto_cap,
 855                           struct ethtool_link_ksettings *link_ksettings)
 856 {
 857         unsigned long *supported = link_ksettings->link_modes.supported;
 858         ptys2ethtool_supported_link(mdev, supported, eth_proto_cap);
 859
 860         ethtool_link_ksettings_add_link_mode(link_ksettings, supported, Pause);
 861 }
 862
 863 static void get_advertising(u32 eth_proto_cap, u8 tx_pause, u8 rx_pause,
 864                             struct ethtool_link_ksettings *link_ksettings,
 865                             bool ext)
 866 {
 867         unsigned long *advertising = link_ksettings->link_modes.advertising;
 868         ptys2ethtool_adver_link(advertising, eth_proto_cap, ext);
 869
 870         if (rx_pause)
 871                 ethtool_link_ksettings_add_link_mode(link_ksettings, advertising, Pause);
 872         if (tx_pause ^ rx_pause)
 873                 ethtool_link_ksettings_add_link_mode(link_ksettings, advertising, Asym_Pause);
 874 }
 875
 876 static int ptys2connector_type[MLX5E_CONNECTOR_TYPE_NUMBER] = {
 877                 [MLX5E_PORT_UNKNOWN]            = PORT_OTHER,
 878                 [MLX5E_PORT_NONE]               = PORT_NONE,
 879                 [MLX5E_PORT_TP]                 = PORT_TP,
 880                 [MLX5E_PORT_AUI]                = PORT_AUI,
 881                 [MLX5E_PORT_BNC]                = PORT_BNC,
 882                 [MLX5E_PORT_MII]                = PORT_MII,
 883                 [MLX5E_PORT_FIBRE]              = PORT_FIBRE,
 884                 [MLX5E_PORT_DA]                 = PORT_DA,
 885                 [MLX5E_PORT_OTHER]              = PORT_OTHER,
 886         };
 887
 888 static u8 get_connector_port(u32 eth_proto, u8 connector_type, bool ext)
 889 {
 890         if ((connector_type || ext) && connector_type < MLX5E_CONNECTOR_TYPE_NUMBER)
 891                 return ptys2connector_type[connector_type];
 892
 893         if (eth_proto &
 894             (MLX5E_PROT_MASK(MLX5E_10GBASE_SR)   |
 895              MLX5E_PROT_MASK(MLX5E_40GBASE_SR4)  |
 896              MLX5E_PROT_MASK(MLX5E_100GBASE_SR4) |
 897              MLX5E_PROT_MASK(MLX5E_1000BASE_CX_SGMII))) {
 898                 return PORT_FIBRE;
 899         }
 900
 901         if (eth_proto &
 902             (MLX5E_PROT_MASK(MLX5E_40GBASE_CR4) |
 903              MLX5E_PROT_MASK(MLX5E_10GBASE_CR)  |
 904              MLX5E_PROT_MASK(MLX5E_100GBASE_CR4))) {
 905                 return PORT_DA;
 906         }
 907
 908         if (eth_proto &
 909             (MLX5E_PROT_MASK(MLX5E_10GBASE_KX4) |
 910              MLX5E_PROT_MASK(MLX5E_10GBASE_KR)  |
 911              MLX5E_PROT_MASK(MLX5E_40GBASE_KR4) |
 912              MLX5E_PROT_MASK(MLX5E_100GBASE_KR4))) {
 913                 return PORT_NONE;
 914         }
 915
 916         return PORT_OTHER;
 917 }
 918
 919 static void get_lp_advertising(struct mlx5_core_dev *mdev, u32 eth_proto_lp,
 920                                struct ethtool_link_ksettings *link_ksettings)
 921 {
 922         unsigned long *lp_advertising = link_ksettings->link_modes.lp_advertising;
 923         bool ext = mlx5e_ptys_ext_supported(mdev);
 924
 925         ptys2ethtool_adver_link(lp_advertising, eth_proto_lp, ext);
 926 }
 927
 928 int mlx5e_ethtool_get_link_ksettings(struct mlx5e_priv *priv,
 929                                      struct ethtool_link_ksettings *link_ksettings)
 930 {
 931         struct mlx5_core_dev *mdev = priv->mdev;
 932         u32 out[MLX5_ST_SZ_DW(ptys_reg)] = {};
 933         u32 eth_proto_admin;
 934         u8 an_disable_admin;
 935         u16 data_rate_oper;
 936         u32 eth_proto_oper;
 937         u32 eth_proto_cap;
 938         u8 connector_type;
 939         u32 rx_pause = 0;
 940         u32 tx_pause = 0;
 941         u32 eth_proto_lp;
 942         bool admin_ext;
 943         u8 an_status;
 944         bool ext;
 945         int err;
 946
 947         err = mlx5_query_port_ptys(mdev, out, sizeof(out), MLX5_PTYS_EN, 1);
 948         if (err) {
 949                 netdev_err(priv->netdev, "%s: query port ptys failed: %d\n",
 950                            __func__, err);
 951                 goto err_query_regs;
 952         }
 953         ext = !!MLX5_GET_ETH_PROTO(ptys_reg, out, true, eth_proto_capability);
 954         eth_proto_cap    = MLX5_GET_ETH_PROTO(ptys_reg, out, ext,
 955                                               eth_proto_capability);
 956         eth_proto_admin  = MLX5_GET_ETH_PROTO(ptys_reg, out, ext,
 957                                               eth_proto_admin);
 958         /* Fields: eth_proto_admin and ext_eth_proto_admin  are
 959          * mutually exclusive. Hence try reading legacy advertising
 960          * when extended advertising is zero.
 961          * admin_ext indicates which proto_admin (ext vs. legacy)
 962          * should be read and interpreted
 963          */
 964         admin_ext = ext;
 965         if (ext && !eth_proto_admin) {
 966                 eth_proto_admin  = MLX5_GET_ETH_PROTO(ptys_reg, out, false,
 967                                                       eth_proto_admin);
 968                 admin_ext = false;
 969         }
 970
 971         eth_proto_oper   = MLX5_GET_ETH_PROTO(ptys_reg, out, admin_ext,
 972                                               eth_proto_oper);
 973         eth_proto_lp        = MLX5_GET(ptys_reg, out, eth_proto_lp_advertise);
 974         an_disable_admin    = MLX5_GET(ptys_reg, out, an_disable_admin);
 975         an_status           = MLX5_GET(ptys_reg, out, an_status);
 976         connector_type      = MLX5_GET(ptys_reg, out, connector_type);
 977         data_rate_oper      = MLX5_GET(ptys_reg, out, data_rate_oper);
 978
 979         mlx5_query_port_pause(mdev, &rx_pause, &tx_pause);
 980
 981         ethtool_link_ksettings_zero_link_mode(link_ksettings, supported);
 982         ethtool_link_ksettings_zero_link_mode(link_ksettings, advertising);
 983
 984         get_supported(mdev, eth_proto_cap, link_ksettings);
 985         get_advertising(eth_proto_admin, tx_pause, rx_pause, link_ksettings,
 986                         admin_ext);
 987         get_speed_duplex(priv->netdev, eth_proto_oper, !admin_ext,
 988                          data_rate_oper, link_ksettings);
 989
 990         eth_proto_oper = eth_proto_oper ? eth_proto_oper : eth_proto_cap;
 991
 992         link_ksettings->base.port = get_connector_port(eth_proto_oper,
 993                                                        connector_type, ext);
 994         ptys2ethtool_supported_advertised_port(link_ksettings, eth_proto_admin,
 995                                                connector_type, ext);
 996         get_lp_advertising(mdev, eth_proto_lp, link_ksettings);
 997
 998         if (an_status == MLX5_AN_COMPLETE)
 999                 ethtool_link_ksettings_add_link_mode(link_ksettings,
1000                                                      lp_advertising, Autoneg);
1001
1002         link_ksettings->base.autoneg = an_disable_admin ? AUTONEG_DISABLE :
1003                                                           AUTONEG_ENABLE;
1004         ethtool_link_ksettings_add_link_mode(link_ksettings, supported,
1005                                              Autoneg);
1006
1007         err = get_fec_supported_advertised(mdev, link_ksettings);
1008         if (err) {
1009                 netdev_dbg(priv->netdev, "%s: FEC caps query failed: %d\n",
1010                            __func__, err);
1011                 err = 0; /* don't fail caps query because of FEC error */
1012         }
1013
1014         if (!an_disable_admin)
1015                 ethtool_link_ksettings_add_link_mode(link_ksettings,
1016                                                      advertising, Autoneg);
1017
1018 err_query_regs:
1019         return err;
1020 }
1021
1022 static int mlx5e_get_link_ksettings(struct net_device *netdev,
1023                                     struct ethtool_link_ksettings *link_ksettings)
1024 {
1025         struct mlx5e_priv *priv = netdev_priv(netdev);
1026
1027         return mlx5e_ethtool_get_link_ksettings(priv, link_ksettings);
1028 }
1029
1030 static int mlx5e_speed_validate(struct net_device *netdev, bool ext,
1031                                 const unsigned long link_modes, u8 autoneg)
1032 {
1033         /* Extended link-mode has no speed limitations. */
1034         if (ext)
1035                 return 0;
1036
1037         if ((link_modes & MLX5E_PROT_MASK(MLX5E_56GBASE_R4)) &&
1038             autoneg != AUTONEG_ENABLE) {
1039                 netdev_err(netdev, "%s: 56G link speed requires autoneg enabled\n",
1040                            __func__);
1041                 return -EINVAL;
1042         }
1043         return 0;
1044 }
1045
1046 static u32 mlx5e_ethtool2ptys_adver_link(const unsigned long *link_modes)
1047 {
1048         u32 i, ptys_modes = 0;
1049
1050         for (i = 0; i < MLX5E_LINK_MODES_NUMBER; ++i) {
1051                 if (*ptys2legacy_ethtool_table[i].advertised == 0)
1052                         continue;
1053                 if (bitmap_intersects(ptys2legacy_ethtool_table[i].advertised,
1054                                       link_modes,
1055                                       __ETHTOOL_LINK_MODE_MASK_NBITS))
1056                         ptys_modes |= MLX5E_PROT_MASK(i);
1057         }
1058
1059         return ptys_modes;
1060 }
1061
1062 static u32 mlx5e_ethtool2ptys_ext_adver_link(const unsigned long *link_modes)
1063 {
1064         u32 i, ptys_modes = 0;
1065         unsigned long modes[2];
1066
1067         for (i = 0; i < MLX5E_EXT_LINK_MODES_NUMBER; ++i) {
1068                 if (ptys2ext_ethtool_table[i].advertised[0] == 0 &&
1069                     ptys2ext_ethtool_table[i].advertised[1] == 0)
1070                         continue;
1071                 memset(modes, 0, sizeof(modes));
1072                 bitmap_and(modes, ptys2ext_ethtool_table[i].advertised,
1073                            link_modes, __ETHTOOL_LINK_MODE_MASK_NBITS);
1074
1075                 if (modes[0] == ptys2ext_ethtool_table[i].advertised[0] &&
1076                     modes[1] == ptys2ext_ethtool_table[i].advertised[1])
1077                         ptys_modes |= MLX5E_PROT_MASK(i);
1078         }
1079         return ptys_modes;
1080 }
1081
1082 static bool ext_link_mode_requested(const unsigned long *adver)
1083 {
1084 #define MLX5E_MIN_PTYS_EXT_LINK_MODE_BIT ETHTOOL_LINK_MODE_50000baseKR_Full_BIT
1085         int size = __ETHTOOL_LINK_MODE_MASK_NBITS - MLX5E_MIN_PTYS_EXT_LINK_MODE_BIT;
1086         __ETHTOOL_DECLARE_LINK_MODE_MASK(modes) = {0,};
1087
1088         bitmap_set(modes, MLX5E_MIN_PTYS_EXT_LINK_MODE_BIT, size);
1089         return bitmap_intersects(modes, adver, __ETHTOOL_LINK_MODE_MASK_NBITS);
1090 }
1091
1092 static bool ext_requested(u8 autoneg, const unsigned long *adver, bool ext_supported)
1093 {
1094         bool ext_link_mode = ext_link_mode_requested(adver);
1095
1096         return  autoneg == AUTONEG_ENABLE ? ext_link_mode : ext_supported;
1097 }
1098
1099 int mlx5e_ethtool_set_link_ksettings(struct mlx5e_priv *priv,
1100                                      const struct ethtool_link_ksettings *link_ksettings)
1101 {
1102         struct mlx5_core_dev *mdev = priv->mdev;
1103         struct mlx5e_port_eth_proto eproto;
1104         const unsigned long *adver;
1105         bool an_changes = false;
1106         u8 an_disable_admin;
1107         bool ext_supported;
1108         u8 an_disable_cap;
1109         bool an_disable;
1110         u32 link_modes;
1111         u8 an_status;
1112         u8 autoneg;
1113         u32 speed;
1114         bool ext;
1115         int err;
1116
1117         u32 (*ethtool2ptys_adver_func)(const unsigned long *adver);
1118
1119         adver = link_ksettings->link_modes.advertising;
1120         autoneg = link_ksettings->base.autoneg;
1121         speed = link_ksettings->base.speed;
1122
1123         ext_supported = mlx5e_ptys_ext_supported(mdev);
1124         ext = ext_requested(autoneg, adver, ext_supported);
1125         if (!ext_supported && ext)
1126                 return -EOPNOTSUPP;
1127
1128         ethtool2ptys_adver_func = ext ? mlx5e_ethtool2ptys_ext_adver_link :
1129                                   mlx5e_ethtool2ptys_adver_link;
1130         err = mlx5_port_query_eth_proto(mdev, 1, ext, &eproto);
1131         if (err) {
1132                 netdev_err(priv->netdev, "%s: query port eth proto failed: %d\n",
1133                            __func__, err);
1134                 goto out;
1135         }
1136         link_modes = autoneg == AUTONEG_ENABLE ? ethtool2ptys_adver_func(adver) :
1137                 mlx5e_port_speed2linkmodes(mdev, speed, !ext);
1138
1139         err = mlx5e_speed_validate(priv->netdev, ext, link_modes, autoneg);
1140         if (err)
1141                 goto out;
1142
1143         link_modes = link_modes & eproto.cap;
1144         if (!link_modes) {
1145                 netdev_err(priv->netdev, "%s: Not supported link mode(s) requested",
1146                            __func__);
1147                 err = -EINVAL;
1148                 goto out;
1149         }
1150
1151         mlx5_port_query_eth_autoneg(mdev, &an_status, &an_disable_cap,
1152                                     &an_disable_admin);
1153
1154         an_disable = autoneg == AUTONEG_DISABLE;
1155         an_changes = ((!an_disable && an_disable_admin) ||
1156                       (an_disable && !an_disable_admin));
1157
1158         if (!an_changes && link_modes == eproto.admin)
1159                 goto out;
1160
1161         mlx5_port_set_eth_ptys(mdev, an_disable, link_modes, ext);
1162         mlx5_toggle_port_link(mdev);
1163
1164 out:
1165         return err;
1166 }
1167
1168 static int mlx5e_set_link_ksettings(struct net_device *netdev,
1169                                     const struct ethtool_link_ksettings *link_ksettings)
1170 {
1171         struct mlx5e_priv *priv = netdev_priv(netdev);
1172
1173         return mlx5e_ethtool_set_link_ksettings(priv, link_ksettings);
1174 }
1175
1176 u32 mlx5e_ethtool_get_rxfh_key_size(struct mlx5e_priv *priv)
1177 {
1178         return sizeof(priv->rss_params.toeplitz_hash_key);
1179 }
1180
1181 static u32 mlx5e_get_rxfh_key_size(struct net_device *netdev)
1182 {
1183         struct mlx5e_priv *priv = netdev_priv(netdev);
1184
1185         return mlx5e_ethtool_get_rxfh_key_size(priv);
1186 }
1187
1188 u32 mlx5e_ethtool_get_rxfh_indir_size(struct mlx5e_priv *priv)
1189 {
1190         return MLX5E_INDIR_RQT_SIZE;
1191 }
1192
1193 static u32 mlx5e_get_rxfh_indir_size(struct net_device *netdev)
1194 {
1195         struct mlx5e_priv *priv = netdev_priv(netdev);
1196
1197         return mlx5e_ethtool_get_rxfh_indir_size(priv);
1198 }
1199
1200 int mlx5e_get_rxfh(struct net_device *netdev, u32 *indir, u8 *key,
1201                    u8 *hfunc)
1202 {
1203         struct mlx5e_priv *priv = netdev_priv(netdev);
1204         struct mlx5e_rss_params *rss = &priv->rss_params;
1205
1206         if (indir)
1207                 memcpy(indir, rss->indirection_rqt,
1208                        sizeof(rss->indirection_rqt));
1209
1210         if (key)
1211                 memcpy(key, rss->toeplitz_hash_key,
1212                        sizeof(rss->toeplitz_hash_key));
1213
1214         if (hfunc)
1215                 *hfunc = rss->hfunc;
1216
1217         return 0;
1218 }
1219
1220 int mlx5e_set_rxfh(struct net_device *dev, const u32 *indir,
1221                    const u8 *key, const u8 hfunc)
1222 {
1223         struct mlx5e_priv *priv = netdev_priv(dev);
1224         struct mlx5e_rss_params *rss = &priv->rss_params;
1225         int inlen = MLX5_ST_SZ_BYTES(modify_tir_in);
1226         bool refresh_tirs = false;
1227         bool refresh_rqt = false;
1228         void *in;
1229
1230         if ((hfunc != ETH_RSS_HASH_NO_CHANGE) &&
1231             (hfunc != ETH_RSS_HASH_XOR) &&
1232             (hfunc != ETH_RSS_HASH_TOP))
1233                 return -EINVAL;
1234
1235         in = kvzalloc(inlen, GFP_KERNEL);
1236         if (!in)
1237                 return -ENOMEM;
1238
1239         mutex_lock(&priv->state_lock);
1240
1241         if (hfunc != ETH_RSS_HASH_NO_CHANGE && hfunc != rss->hfunc) {
1242                 rss->hfunc = hfunc;
1243                 refresh_rqt = true;
1244                 refresh_tirs = true;
1245         }
1246
1247         if (indir) {
1248                 memcpy(rss->indirection_rqt, indir,
1249                        sizeof(rss->indirection_rqt));
1250                 refresh_rqt = true;
1251         }
1252
1253         if (key) {
1254                 memcpy(rss->toeplitz_hash_key, key,
1255                        sizeof(rss->toeplitz_hash_key));
1256                 refresh_tirs = refresh_tirs || rss->hfunc == ETH_RSS_HASH_TOP;
1257         }
1258
1259         if (refresh_rqt && test_bit(MLX5E_STATE_OPENED, &priv->state)) {
1260                 struct mlx5e_redirect_rqt_param rrp = {
1261                         .is_rss = true,
1262                         {
1263                                 .rss = {
1264                                         .hfunc = rss->hfunc,
1265                                         .channels  = &priv->channels,
1266                                 },
1267                         },
1268                 };
1269                 u32 rqtn = priv->indir_rqt.rqtn;
1270
1271                 mlx5e_redirect_rqt(priv, rqtn, MLX5E_INDIR_RQT_SIZE, rrp);
1272         }
1273
1274         if (refresh_tirs)
1275                 mlx5e_modify_tirs_hash(priv, in);
1276
1277         mutex_unlock(&priv->state_lock);
1278
1279         kvfree(in);
1280
1281         return 0;
1282 }
1283
1284 #define MLX5E_PFC_PREVEN_AUTO_TOUT_MSEC         100
1285 #define MLX5E_PFC_PREVEN_TOUT_MAX_MSEC          8000
1286 #define MLX5E_PFC_PREVEN_MINOR_PRECENT          85
1287 #define MLX5E_PFC_PREVEN_TOUT_MIN_MSEC          80
1288 #define MLX5E_DEVICE_STALL_MINOR_WATERMARK(critical_tout) \
1289         max_t(u16, MLX5E_PFC_PREVEN_TOUT_MIN_MSEC, \
1290               (critical_tout * MLX5E_PFC_PREVEN_MINOR_PRECENT) / 100)
1291
1292 static int mlx5e_get_pfc_prevention_tout(struct net_device *netdev,
1293                                          u16 *pfc_prevention_tout)
1294 {
1295         struct mlx5e_priv *priv    = netdev_priv(netdev);
1296         struct mlx5_core_dev *mdev = priv->mdev;
1297
1298         if (!MLX5_CAP_PCAM_FEATURE((priv)->mdev, pfcc_mask) ||
1299             !MLX5_CAP_DEBUG((priv)->mdev, stall_detect))
1300                 return -EOPNOTSUPP;
1301
1302         return mlx5_query_port_stall_watermark(mdev, pfc_prevention_tout, NULL);
1303 }
1304
1305 static int mlx5e_set_pfc_prevention_tout(struct net_device *netdev,
1306                                          u16 pfc_preven)
1307 {
1308         struct mlx5e_priv *priv = netdev_priv(netdev);
1309         struct mlx5_core_dev *mdev = priv->mdev;
1310         u16 critical_tout;
1311         u16 minor;
1312
1313         if (!MLX5_CAP_PCAM_FEATURE((priv)->mdev, pfcc_mask) ||
1314             !MLX5_CAP_DEBUG((priv)->mdev, stall_detect))
1315                 return -EOPNOTSUPP;
1316
1317         critical_tout = (pfc_preven == PFC_STORM_PREVENTION_AUTO) ?
1318                         MLX5E_PFC_PREVEN_AUTO_TOUT_MSEC :
1319                         pfc_preven;
1320
1321         if (critical_tout != PFC_STORM_PREVENTION_DISABLE &&
1322             (critical_tout > MLX5E_PFC_PREVEN_TOUT_MAX_MSEC ||
1323              critical_tout < MLX5E_PFC_PREVEN_TOUT_MIN_MSEC)) {
1324                 netdev_info(netdev, "%s: pfc prevention tout not in range (%d-%d)\n",
1325                             __func__, MLX5E_PFC_PREVEN_TOUT_MIN_MSEC,
1326                             MLX5E_PFC_PREVEN_TOUT_MAX_MSEC);
1327                 return -EINVAL;
1328         }
1329
1330         minor = MLX5E_DEVICE_STALL_MINOR_WATERMARK(critical_tout);
1331         return mlx5_set_port_stall_watermark(mdev, critical_tout,
1332                                              minor);
1333 }
1334
1335 static int mlx5e_get_tunable(struct net_device *dev,
1336                              const struct ethtool_tunable *tuna,
1337                              void *data)
1338 {
1339         int err;
1340
1341         switch (tuna->id) {
1342         case ETHTOOL_PFC_PREVENTION_TOUT:
1343                 err = mlx5e_get_pfc_prevention_tout(dev, data);
1344                 break;
1345         default:
1346                 err = -EINVAL;
1347                 break;
1348         }
1349
1350         return err;
1351 }
1352
1353 static int mlx5e_set_tunable(struct net_device *dev,
1354                              const struct ethtool_tunable *tuna,
1355                              const void *data)
1356 {
1357         struct mlx5e_priv *priv = netdev_priv(dev);
1358         int err;
1359
1360         mutex_lock(&priv->state_lock);
1361
1362         switch (tuna->id) {
1363         case ETHTOOL_PFC_PREVENTION_TOUT:
1364                 err = mlx5e_set_pfc_prevention_tout(dev, *(u16 *)data);
1365                 break;
1366         default:
1367                 err = -EINVAL;
1368                 break;
1369         }
1370
1371         mutex_unlock(&priv->state_lock);
1372         return err;
1373 }
1374
1375 static void mlx5e_get_pause_stats(struct net_device *netdev,
1376                                   struct ethtool_pause_stats *pause_stats)
1377 {
1378         struct mlx5e_priv *priv = netdev_priv(netdev);
1379
1380         mlx5e_stats_pause_get(priv, pause_stats);
1381 }
1382
1383 void mlx5e_ethtool_get_pauseparam(struct mlx5e_priv *priv,
1384                                   struct ethtool_pauseparam *pauseparam)
1385 {
1386         struct mlx5_core_dev *mdev = priv->mdev;
1387         int err;
1388
1389         err = mlx5_query_port_pause(mdev, &pauseparam->rx_pause,
1390                                     &pauseparam->tx_pause);
1391         if (err) {
1392                 netdev_err(priv->netdev, "%s: mlx5_query_port_pause failed:0x%x\n",
1393                            __func__, err);
1394         }
1395 }
1396
1397 static void mlx5e_get_pauseparam(struct net_device *netdev,
1398                                  struct ethtool_pauseparam *pauseparam)
1399 {
1400         struct mlx5e_priv *priv = netdev_priv(netdev);
1401
1402         mlx5e_ethtool_get_pauseparam(priv, pauseparam);
1403 }
1404
1405 int mlx5e_ethtool_set_pauseparam(struct mlx5e_priv *priv,
1406                                  struct ethtool_pauseparam *pauseparam)
1407 {
1408         struct mlx5_core_dev *mdev = priv->mdev;
1409         int err;
1410
1411         if (!MLX5_CAP_GEN(mdev, vport_group_manager))
1412                 return -EOPNOTSUPP;
1413
1414         if (pauseparam->autoneg)
1415                 return -EINVAL;
1416
1417         err = mlx5_set_port_pause(mdev,
1418                                   pauseparam->rx_pause ? 1 : 0,
1419                                   pauseparam->tx_pause ? 1 : 0);
1420         if (err) {
1421                 netdev_err(priv->netdev, "%s: mlx5_set_port_pause failed:0x%x\n",
1422                            __func__, err);
1423         }
1424
1425         return err;
1426 }
1427
1428 static int mlx5e_set_pauseparam(struct net_device *netdev,
1429                                 struct ethtool_pauseparam *pauseparam)
1430 {
1431         struct mlx5e_priv *priv = netdev_priv(netdev);
1432
1433         return mlx5e_ethtool_set_pauseparam(priv, pauseparam);
1434 }
1435
1436 int mlx5e_ethtool_get_ts_info(struct mlx5e_priv *priv,
1437                               struct ethtool_ts_info *info)
1438 {
1439         struct mlx5_core_dev *mdev = priv->mdev;
1440
1441         info->phc_index = mlx5_clock_get_ptp_index(mdev);
1442
1443         if (!MLX5_CAP_GEN(priv->mdev, device_frequency_khz) ||
1444             info->phc_index == -1)
1445                 return 0;
1446
1447         info->so_timestamping = SOF_TIMESTAMPING_TX_HARDWARE |
1448                                 SOF_TIMESTAMPING_RX_HARDWARE |
1449                                 SOF_TIMESTAMPING_RAW_HARDWARE;
1450
1451         info->tx_types = BIT(HWTSTAMP_TX_OFF) |
1452                          BIT(HWTSTAMP_TX_ON);
1453
1454         info->rx_filters = BIT(HWTSTAMP_FILTER_NONE) |
1455                            BIT(HWTSTAMP_FILTER_ALL);
1456
1457         return 0;
1458 }
1459
1460 static int mlx5e_get_ts_info(struct net_device *dev,
1461                              struct ethtool_ts_info *info)
1462 {
1463         struct mlx5e_priv *priv = netdev_priv(dev);
1464
1465         return mlx5e_ethtool_get_ts_info(priv, info);
1466 }
1467
1468 static __u32 mlx5e_get_wol_supported(struct mlx5_core_dev *mdev)
1469 {
1470         __u32 ret = 0;
1471
1472         if (MLX5_CAP_GEN(mdev, wol_g))
1473                 ret |= WAKE_MAGIC;
1474
1475         if (MLX5_CAP_GEN(mdev, wol_s))
1476                 ret |= WAKE_MAGICSECURE;
1477
1478         if (MLX5_CAP_GEN(mdev, wol_a))
1479                 ret |= WAKE_ARP;
1480
1481         if (MLX5_CAP_GEN(mdev, wol_b))
1482                 ret |= WAKE_BCAST;
1483
1484         if (MLX5_CAP_GEN(mdev, wol_m))
1485                 ret |= WAKE_MCAST;
1486
1487         if (MLX5_CAP_GEN(mdev, wol_u))
1488                 ret |= WAKE_UCAST;
1489
1490         if (MLX5_CAP_GEN(mdev, wol_p))
1491                 ret |= WAKE_PHY;
1492
1493         return ret;
1494 }
1495
1496 static __u32 mlx5e_reformat_wol_mode_mlx5_to_linux(u8 mode)
1497 {
1498         __u32 ret = 0;
1499
1500         if (mode & MLX5_WOL_MAGIC)
1501                 ret |= WAKE_MAGIC;
1502
1503         if (mode & MLX5_WOL_SECURED_MAGIC)
1504                 ret |= WAKE_MAGICSECURE;
1505
1506         if (mode & MLX5_WOL_ARP)
1507                 ret |= WAKE_ARP;
1508
1509         if (mode & MLX5_WOL_BROADCAST)
1510                 ret |= WAKE_BCAST;
1511
1512         if (mode & MLX5_WOL_MULTICAST)
1513                 ret |= WAKE_MCAST;
1514
1515         if (mode & MLX5_WOL_UNICAST)
1516                 ret |= WAKE_UCAST;
1517
1518         if (mode & MLX5_WOL_PHY_ACTIVITY)
1519                 ret |= WAKE_PHY;
1520
1521         return ret;
1522 }
1523
1524 static u8 mlx5e_reformat_wol_mode_linux_to_mlx5(__u32 mode)
1525 {
1526         u8 ret = 0;
1527
1528         if (mode & WAKE_MAGIC)
1529                 ret |= MLX5_WOL_MAGIC;
1530
1531         if (mode & WAKE_MAGICSECURE)
1532                 ret |= MLX5_WOL_SECURED_MAGIC;
1533
1534         if (mode & WAKE_ARP)
1535                 ret |= MLX5_WOL_ARP;
1536
1537         if (mode & WAKE_BCAST)
1538                 ret |= MLX5_WOL_BROADCAST;
1539
1540         if (mode & WAKE_MCAST)
1541                 ret |= MLX5_WOL_MULTICAST;
1542
1543         if (mode & WAKE_UCAST)
1544                 ret |= MLX5_WOL_UNICAST;
1545
1546         if (mode & WAKE_PHY)
1547                 ret |= MLX5_WOL_PHY_ACTIVITY;
1548
1549         return ret;
1550 }
1551
1552 static void mlx5e_get_wol(struct net_device *netdev,
1553                           struct ethtool_wolinfo *wol)
1554 {
1555         struct mlx5e_priv *priv = netdev_priv(netdev);
1556         struct mlx5_core_dev *mdev = priv->mdev;
1557         u8 mlx5_wol_mode;
1558         int err;
1559
1560         memset(wol, 0, sizeof(*wol));
1561
1562         wol->supported = mlx5e_get_wol_supported(mdev);
1563         if (!wol->supported)
1564                 return;
1565
1566         err = mlx5_query_port_wol(mdev, &mlx5_wol_mode);
1567         if (err)
1568                 return;
1569
1570         wol->wolopts = mlx5e_reformat_wol_mode_mlx5_to_linux(mlx5_wol_mode);
1571 }
1572
1573 static int mlx5e_set_wol(struct net_device *netdev, struct ethtool_wolinfo *wol)
1574 {
1575         struct mlx5e_priv *priv = netdev_priv(netdev);
1576         struct mlx5_core_dev *mdev = priv->mdev;
1577         __u32 wol_supported = mlx5e_get_wol_supported(mdev);
1578         u32 mlx5_wol_mode;
1579
1580         if (!wol_supported)
1581                 return -EOPNOTSUPP;
1582
1583         if (wol->wolopts & ~wol_supported)
1584                 return -EINVAL;
1585
1586         mlx5_wol_mode = mlx5e_reformat_wol_mode_linux_to_mlx5(wol->wolopts);
1587
1588         return mlx5_set_port_wol(mdev, mlx5_wol_mode);
1589 }
1590
1591 static int mlx5e_get_fecparam(struct net_device *netdev,
1592                               struct ethtool_fecparam *fecparam)
1593 {
1594         struct mlx5e_priv *priv = netdev_priv(netdev);
1595         struct mlx5_core_dev *mdev = priv->mdev;
1596         u16 fec_configured;
1597         u32 fec_active;
1598         int err;
1599
1600         err = mlx5e_get_fec_mode(mdev, &fec_active, &fec_configured);
1601
1602         if (err)
1603                 return err;
1604
1605         fecparam->active_fec = pplm2ethtool_fec((unsigned long)fec_active,
1606                                                 sizeof(unsigned long) * BITS_PER_BYTE);
1607
1608         if (!fecparam->active_fec)
1609                 return -EOPNOTSUPP;
1610
1611         fecparam->fec = pplm2ethtool_fec((unsigned long)fec_configured,
1612                                          sizeof(unsigned long) * BITS_PER_BYTE);
1613
1614         return 0;
1615 }
1616
1617 static int mlx5e_set_fecparam(struct net_device *netdev,
1618                               struct ethtool_fecparam *fecparam)
1619 {
1620         struct mlx5e_priv *priv = netdev_priv(netdev);
1621         struct mlx5_core_dev *mdev = priv->mdev;
1622         u16 fec_policy = 0;
1623         int mode;
1624         int err;
1625
1626         if (bitmap_weight((unsigned long *)&fecparam->fec,
1627                           ETHTOOL_FEC_LLRS_BIT + 1) > 1)
1628                 return -EOPNOTSUPP;
1629
1630         for (mode = 0; mode < ARRAY_SIZE(pplm_fec_2_ethtool); mode++) {
1631                 if (!(pplm_fec_2_ethtool[mode] & fecparam->fec))
1632                         continue;
1633                 fec_policy |= (1 << mode);
1634                 break;
1635         }
1636
1637         err = mlx5e_set_fec_mode(mdev, fec_policy);
1638
1639         if (err)
1640                 return err;
1641
1642         mlx5_toggle_port_link(mdev);
1643
1644         return 0;
1645 }
1646
1647 static u32 mlx5e_get_msglevel(struct net_device *dev)
1648 {
1649         return ((struct mlx5e_priv *)netdev_priv(dev))->msglevel;
1650 }
1651
1652 static void mlx5e_set_msglevel(struct net_device *dev, u32 val)
1653 {
1654         ((struct mlx5e_priv *)netdev_priv(dev))->msglevel = val;
1655 }
1656
1657 static int mlx5e_set_phys_id(struct net_device *dev,
1658                              enum ethtool_phys_id_state state)
1659 {
1660         struct mlx5e_priv *priv = netdev_priv(dev);
1661         struct mlx5_core_dev *mdev = priv->mdev;
1662         u16 beacon_duration;
1663
1664         if (!MLX5_CAP_GEN(mdev, beacon_led))
1665                 return -EOPNOTSUPP;
1666
1667         switch (state) {
1668         case ETHTOOL_ID_ACTIVE:
1669                 beacon_duration = MLX5_BEACON_DURATION_INF;
1670                 break;
1671         case ETHTOOL_ID_INACTIVE:
1672                 beacon_duration = MLX5_BEACON_DURATION_OFF;
1673                 break;
1674         default:
1675                 return -EOPNOTSUPP;
1676         }
1677
1678         return mlx5_set_port_beacon(mdev, beacon_duration);
1679 }
1680
1681 static int mlx5e_get_module_info(struct net_device *netdev,
1682                                  struct ethtool_modinfo *modinfo)
1683 {
1684         struct mlx5e_priv *priv = netdev_priv(netdev);
1685         struct mlx5_core_dev *dev = priv->mdev;
1686         int size_read = 0;
1687         u8 data[4] = {0};
1688
1689         size_read = mlx5_query_module_eeprom(dev, 0, 2, data);
1690         if (size_read < 2)
1691                 return -EIO;
1692
1693         /* data[0] = identifier byte */
1694         switch (data[0]) {
1695         case MLX5_MODULE_ID_QSFP:
1696                 modinfo->type       = ETH_MODULE_SFF_8436;
1697                 modinfo->eeprom_len = ETH_MODULE_SFF_8436_MAX_LEN;
1698                 break;
1699         case MLX5_MODULE_ID_QSFP_PLUS:
1700         case MLX5_MODULE_ID_QSFP28:
1701                 /* data[1] = revision id */
1702                 if (data[0] == MLX5_MODULE_ID_QSFP28 || data[1] >= 0x3) {
1703                         modinfo->type       = ETH_MODULE_SFF_8636;
1704                         modinfo->eeprom_len = ETH_MODULE_SFF_8636_MAX_LEN;
1705                 } else {
1706                         modinfo->type       = ETH_MODULE_SFF_8436;
1707                         modinfo->eeprom_len = ETH_MODULE_SFF_8436_MAX_LEN;
1708                 }
1709                 break;
1710         case MLX5_MODULE_ID_SFP:
1711                 modinfo->type       = ETH_MODULE_SFF_8472;
1712                 modinfo->eeprom_len = ETH_MODULE_SFF_8472_LEN;
1713                 break;
1714         default:
1715                 netdev_err(priv->netdev, "%s: cable type not recognized:0x%x\n",
1716                            __func__, data[0]);
1717                 return -EINVAL;
1718         }
1719
1720         return 0;
1721 }
1722
1723 static int mlx5e_get_module_eeprom(struct net_device *netdev,
1724                                    struct ethtool_eeprom *ee,
1725                                    u8 *data)
1726 {
1727         struct mlx5e_priv *priv = netdev_priv(netdev);
1728         struct mlx5_core_dev *mdev = priv->mdev;
1729         int offset = ee->offset;
1730         int size_read;
1731         int i = 0;
1732
1733         if (!ee->len)
1734                 return -EINVAL;
1735
1736         memset(data, 0, ee->len);
1737
1738         while (i < ee->len) {
1739                 size_read = mlx5_query_module_eeprom(mdev, offset, ee->len - i,
1740                                                      data + i);
1741
1742                 if (!size_read)
1743                         /* Done reading */
1744                         return 0;
1745
1746                 if (size_read < 0) {
1747                         netdev_err(priv->netdev, "%s: mlx5_query_eeprom failed:0x%x\n",
1748                                    __func__, size_read);
1749                         return 0;
1750                 }
1751
1752                 i += size_read;
1753                 offset += size_read;
1754         }
1755
1756         return 0;
1757 }
1758
1759 int mlx5e_ethtool_flash_device(struct mlx5e_priv *priv,
1760                                struct ethtool_flash *flash)
1761 {
1762         struct mlx5_core_dev *mdev = priv->mdev;
1763         struct net_device *dev = priv->netdev;
1764         const struct firmware *fw;
1765         int err;
1766
1767         if (flash->region != ETHTOOL_FLASH_ALL_REGIONS)
1768                 return -EOPNOTSUPP;
1769
1770         err = request_firmware_direct(&fw, flash->data, &dev->dev);
1771         if (err)
1772                 return err;
1773
1774         dev_hold(dev);
1775         rtnl_unlock();
1776
1777         err = mlx5_firmware_flash(mdev, fw, NULL);
1778         release_firmware(fw);
1779
1780         rtnl_lock();
1781         dev_put(dev);
1782         return err;
1783 }
1784
1785 static int mlx5e_flash_device(struct net_device *dev,
1786                               struct ethtool_flash *flash)
1787 {
1788         struct mlx5e_priv *priv = netdev_priv(dev);
1789
1790         return mlx5e_ethtool_flash_device(priv, flash);
1791 }
1792
1793 static int set_pflag_cqe_based_moder(struct net_device *netdev, bool enable,
1794                                      bool is_rx_cq)
1795 {
1796         struct mlx5e_priv *priv = netdev_priv(netdev);
1797         struct mlx5_core_dev *mdev = priv->mdev;
1798         struct mlx5e_channels new_channels = {};
1799         bool mode_changed;
1800         u8 cq_period_mode, current_cq_period_mode;
1801
1802         cq_period_mode = enable ?
1803                 MLX5_CQ_PERIOD_MODE_START_FROM_CQE :
1804                 MLX5_CQ_PERIOD_MODE_START_FROM_EQE;
1805         current_cq_period_mode = is_rx_cq ?
1806                 priv->channels.params.rx_cq_moderation.cq_period_mode :
1807                 priv->channels.params.tx_cq_moderation.cq_period_mode;
1808         mode_changed = cq_period_mode != current_cq_period_mode;
1809
1810         if (cq_period_mode == MLX5_CQ_PERIOD_MODE_START_FROM_CQE &&
1811             !MLX5_CAP_GEN(mdev, cq_period_start_from_cqe))
1812                 return -EOPNOTSUPP;
1813
1814         if (!mode_changed)
1815                 return 0;
1816
1817         new_channels.params = priv->channels.params;
1818         if (is_rx_cq)
1819                 mlx5e_set_rx_cq_mode_params(&new_channels.params, cq_period_mode);
1820         else
1821                 mlx5e_set_tx_cq_mode_params(&new_channels.params, cq_period_mode);
1822
1823         if (!test_bit(MLX5E_STATE_OPENED, &priv->state)) {
1824                 priv->channels.params = new_channels.params;
1825                 return 0;
1826         }
1827
1828         return mlx5e_safe_switch_channels(priv, &new_channels, NULL, NULL);
1829 }
1830
1831 static int set_pflag_tx_cqe_based_moder(struct net_device *netdev, bool enable)
1832 {
1833         return set_pflag_cqe_based_moder(netdev, enable, false);
1834 }
1835
1836 static int set_pflag_rx_cqe_based_moder(struct net_device *netdev, bool enable)
1837 {
1838         return set_pflag_cqe_based_moder(netdev, enable, true);
1839 }
1840
1841 int mlx5e_modify_rx_cqe_compression_locked(struct mlx5e_priv *priv, bool new_val)
1842 {
1843         bool curr_val = MLX5E_GET_PFLAG(&priv->channels.params, MLX5E_PFLAG_RX_CQE_COMPRESS);
1844         struct mlx5e_channels new_channels = {};
1845         int err = 0;
1846
1847         if (!MLX5_CAP_GEN(priv->mdev, cqe_compression))
1848                 return new_val ? -EOPNOTSUPP : 0;
1849
1850         if (curr_val == new_val)
1851                 return 0;
1852
1853         new_channels.params = priv->channels.params;
1854         MLX5E_SET_PFLAG(&new_channels.params, MLX5E_PFLAG_RX_CQE_COMPRESS, new_val);
1855
1856         if (!test_bit(MLX5E_STATE_OPENED, &priv->state)) {
1857                 priv->channels.params = new_channels.params;
1858                 return 0;
1859         }
1860
1861         err = mlx5e_safe_switch_channels(priv, &new_channels, NULL, NULL);
1862         if (err)
1863                 return err;
1864
1865         mlx5e_dbg(DRV, priv, "MLX5E: RxCqeCmprss was turned %s\n",
1866                   MLX5E_GET_PFLAG(&priv->channels.params,
1867                                   MLX5E_PFLAG_RX_CQE_COMPRESS) ? "ON" : "OFF");
1868
1869         return 0;
1870 }
1871
1872 static int set_pflag_rx_cqe_compress(struct net_device *netdev,
1873                                      bool enable)
1874 {
1875         struct mlx5e_priv *priv = netdev_priv(netdev);
1876         struct mlx5_core_dev *mdev = priv->mdev;
1877
1878         if (!MLX5_CAP_GEN(mdev, cqe_compression))
1879                 return -EOPNOTSUPP;
1880
1881         if (enable && priv->tstamp.rx_filter != HWTSTAMP_FILTER_NONE) {
1882                 netdev_err(netdev, "Can't enable cqe compression while timestamping is enabled.\n");
1883                 return -EINVAL;
1884         }
1885
1886         mlx5e_modify_rx_cqe_compression_locked(priv, enable);
1887         priv->channels.params.rx_cqe_compress_def = enable;
1888
1889         return 0;
1890 }
1891
1892 static int set_pflag_rx_striding_rq(struct net_device *netdev, bool enable)
1893 {
1894         struct mlx5e_priv *priv = netdev_priv(netdev);
1895         struct mlx5_core_dev *mdev = priv->mdev;
1896         struct mlx5e_channels new_channels = {};
1897
1898         if (enable) {
1899                 if (!mlx5e_check_fragmented_striding_rq_cap(mdev))
1900                         return -EOPNOTSUPP;
1901                 if (!mlx5e_striding_rq_possible(mdev, &priv->channels.params))
1902                         return -EINVAL;
1903         } else if (priv->channels.params.lro_en) {
1904                 netdev_warn(netdev, "Can't set legacy RQ with LRO, disable LRO first\n");
1905                 return -EINVAL;
1906         }
1907
1908         new_channels.params = priv->channels.params;
1909
1910         MLX5E_SET_PFLAG(&new_channels.params, MLX5E_PFLAG_RX_STRIDING_RQ, enable);
1911         mlx5e_set_rq_type(mdev, &new_channels.params);
1912
1913         if (!test_bit(MLX5E_STATE_OPENED, &priv->state)) {
1914                 priv->channels.params = new_channels.params;
1915                 return 0;
1916         }
1917
1918         return mlx5e_safe_switch_channels(priv, &new_channels, NULL, NULL);
1919 }
1920
1921 static int set_pflag_rx_no_csum_complete(struct net_device *netdev, bool enable)
1922 {
1923         struct mlx5e_priv *priv = netdev_priv(netdev);
1924         struct mlx5e_channels *channels = &priv->channels;
1925         struct mlx5e_channel *c;
1926         int i;
1927
1928         if (!test_bit(MLX5E_STATE_OPENED, &priv->state) ||
1929             priv->channels.params.xdp_prog)
1930                 return 0;
1931
1932         for (i = 0; i < channels->num; i++) {
1933                 c = channels->c[i];
1934                 if (enable)
1935                         __set_bit(MLX5E_RQ_STATE_NO_CSUM_COMPLETE, &c->rq.state);
1936                 else
1937                         __clear_bit(MLX5E_RQ_STATE_NO_CSUM_COMPLETE, &c->rq.state);
1938         }
1939
1940         return 0;
1941 }
1942
1943 static int set_pflag_tx_mpwqe_common(struct net_device *netdev, u32 flag, bool enable)
1944 {
1945         struct mlx5e_priv *priv = netdev_priv(netdev);
1946         struct mlx5_core_dev *mdev = priv->mdev;
1947         struct mlx5e_channels new_channels = {};
1948         int err;
1949
1950         if (enable && !MLX5_CAP_ETH(mdev, enhanced_multi_pkt_send_wqe))
1951                 return -EOPNOTSUPP;
1952
1953         new_channels.params = priv->channels.params;
1954
1955         MLX5E_SET_PFLAG(&new_channels.params, flag, enable);
1956
1957         if (!test_bit(MLX5E_STATE_OPENED, &priv->state)) {
1958                 priv->channels.params = new_channels.params;
1959                 return 0;
1960         }
1961
1962         err = mlx5e_safe_switch_channels(priv, &new_channels, NULL, NULL);
1963         return err;
1964 }
1965
1966 static int set_pflag_xdp_tx_mpwqe(struct net_device *netdev, bool enable)
1967 {
1968         return set_pflag_tx_mpwqe_common(netdev, MLX5E_PFLAG_XDP_TX_MPWQE, enable);
1969 }
1970
1971 static int set_pflag_skb_tx_mpwqe(struct net_device *netdev, bool enable)
1972 {
1973         return set_pflag_tx_mpwqe_common(netdev, MLX5E_PFLAG_SKB_TX_MPWQE, enable);
1974 }
1975
1976 static int set_pflag_tx_port_ts(struct net_device *netdev, bool enable)
1977 {
1978         struct mlx5e_priv *priv = netdev_priv(netdev);
1979         struct mlx5_core_dev *mdev = priv->mdev;
1980         struct mlx5e_channels new_channels = {};
1981         int err;
1982
1983         if (!MLX5_CAP_GEN(mdev, ts_cqe_to_dest_cqn))
1984                 return -EOPNOTSUPP;
1985
1986         /* Don't allow changing the PTP state if HTB offload is active, because
1987          * the numeration of the QoS SQs will change, while per-queue qdiscs are
1988          * attached.
1989          */
1990         if (priv->htb.maj_id) {
1991                 netdev_err(priv->netdev, "%s: HTB offload is active, cannot change the PTP state\n",
1992                            __func__);
1993                 return -EINVAL;
1994         }
1995
1996         new_channels.params = priv->channels.params;
1997         MLX5E_SET_PFLAG(&new_channels.params, MLX5E_PFLAG_TX_PORT_TS, enable);
1998         /* No need to verify SQ stop room as
1999          * ptpsq.txqsq.stop_room <= generic_sq->stop_room, and both
2000          * has the same log_sq_size.
2001          */
2002
2003         if (!test_bit(MLX5E_STATE_OPENED, &priv->state)) {
2004                 priv->channels.params = new_channels.params;
2005                 err = mlx5e_num_channels_changed(priv);
2006                 goto out;
2007         }
2008
2009         err = mlx5e_safe_switch_channels(priv, &new_channels,
2010                                          mlx5e_num_channels_changed_ctx, NULL);
2011 out:
2012         if (!err)
2013                 priv->port_ptp_opened = true;
2014
2015         return err;
2016 }
2017
2018 static const struct pflag_desc mlx5e_priv_flags[MLX5E_NUM_PFLAGS] = {
2019         { "rx_cqe_moder",        set_pflag_rx_cqe_based_moder },
2020         { "tx_cqe_moder",        set_pflag_tx_cqe_based_moder },
2021         { "rx_cqe_compress",     set_pflag_rx_cqe_compress },
2022         { "rx_striding_rq",      set_pflag_rx_striding_rq },
2023         { "rx_no_csum_complete", set_pflag_rx_no_csum_complete },
2024         { "xdp_tx_mpwqe",        set_pflag_xdp_tx_mpwqe },
2025         { "skb_tx_mpwqe",        set_pflag_skb_tx_mpwqe },
2026         { "tx_port_ts",          set_pflag_tx_port_ts },
2027 };
2028
2029 static int mlx5e_handle_pflag(struct net_device *netdev,
2030                               u32 wanted_flags,
2031                               enum mlx5e_priv_flag flag)
2032 {
2033         struct mlx5e_priv *priv = netdev_priv(netdev);
2034         bool enable = !!(wanted_flags & BIT(flag));
2035         u32 changes = wanted_flags ^ priv->channels.params.pflags;
2036         int err;
2037
2038         if (!(changes & BIT(flag)))
2039                 return 0;
2040
2041         err = mlx5e_priv_flags[flag].handler(netdev, enable);
2042         if (err) {
2043                 netdev_err(netdev, "%s private flag '%s' failed err %d\n",
2044                            enable ? "Enable" : "Disable", mlx5e_priv_flags[flag].name, err);
2045                 return err;
2046         }
2047
2048         MLX5E_SET_PFLAG(&priv->channels.params, flag, enable);
2049         return 0;
2050 }
2051
2052 static int mlx5e_set_priv_flags(struct net_device *netdev, u32 pflags)
2053 {
2054         struct mlx5e_priv *priv = netdev_priv(netdev);
2055         enum mlx5e_priv_flag pflag;
2056         int err;
2057
2058         mutex_lock(&priv->state_lock);
2059
2060         for (pflag = 0; pflag < MLX5E_NUM_PFLAGS; pflag++) {
2061                 err = mlx5e_handle_pflag(netdev, pflags, pflag);
2062                 if (err)
2063                         break;
2064         }
2065
2066         mutex_unlock(&priv->state_lock);
2067
2068         /* Need to fix some features.. */
2069         netdev_update_features(netdev);
2070
2071         return err;
2072 }
2073
2074 static u32 mlx5e_get_priv_flags(struct net_device *netdev)
2075 {
2076         struct mlx5e_priv *priv = netdev_priv(netdev);
2077
2078         return priv->channels.params.pflags;
2079 }
2080
2081 int mlx5e_get_rxnfc(struct net_device *dev, struct ethtool_rxnfc *info,
2082                     u32 *rule_locs)
2083 {
2084         struct mlx5e_priv *priv = netdev_priv(dev);
2085
2086         /* ETHTOOL_GRXRINGS is needed by ethtool -x which is not part
2087          * of rxnfc. We keep this logic out of mlx5e_ethtool_get_rxnfc,
2088          * to avoid breaking "ethtool -x" when mlx5e_ethtool_get_rxnfc
2089          * is compiled out via CONFIG_MLX5_EN_RXNFC=n.
2090          */
2091         if (info->cmd == ETHTOOL_GRXRINGS) {
2092                 info->data = priv->channels.params.num_channels;
2093                 return 0;
2094         }
2095
2096         return mlx5e_ethtool_get_rxnfc(dev, info, rule_locs);
2097 }
2098
2099 int mlx5e_set_rxnfc(struct net_device *dev, struct ethtool_rxnfc *cmd)
2100 {
2101         return mlx5e_ethtool_set_rxnfc(dev, cmd);
2102 }
2103
2104 const struct ethtool_ops mlx5e_ethtool_ops = {
2105         .supported_coalesce_params = ETHTOOL_COALESCE_USECS |
2106                                      ETHTOOL_COALESCE_MAX_FRAMES |
2107                                      ETHTOOL_COALESCE_USE_ADAPTIVE,
2108         .get_drvinfo       = mlx5e_get_drvinfo,
2109         .get_link          = ethtool_op_get_link,
2110         .get_strings       = mlx5e_get_strings,
2111         .get_sset_count    = mlx5e_get_sset_count,
2112         .get_ethtool_stats = mlx5e_get_ethtool_stats,
2113         .get_ringparam     = mlx5e_get_ringparam,
2114         .set_ringparam     = mlx5e_set_ringparam,
2115         .get_channels      = mlx5e_get_channels,
2116         .set_channels      = mlx5e_set_channels,
2117         .get_coalesce      = mlx5e_get_coalesce,
2118         .set_coalesce      = mlx5e_set_coalesce,
2119         .get_link_ksettings  = mlx5e_get_link_ksettings,
2120         .set_link_ksettings  = mlx5e_set_link_ksettings,
2121         .get_rxfh_key_size   = mlx5e_get_rxfh_key_size,
2122         .get_rxfh_indir_size = mlx5e_get_rxfh_indir_size,
2123         .get_rxfh          = mlx5e_get_rxfh,
2124         .set_rxfh          = mlx5e_set_rxfh,
2125         .get_rxnfc         = mlx5e_get_rxnfc,
2126         .set_rxnfc         = mlx5e_set_rxnfc,
2127         .get_tunable       = mlx5e_get_tunable,
2128         .set_tunable       = mlx5e_set_tunable,
2129         .get_pause_stats   = mlx5e_get_pause_stats,
2130         .get_pauseparam    = mlx5e_get_pauseparam,
2131         .set_pauseparam    = mlx5e_set_pauseparam,
2132         .get_ts_info       = mlx5e_get_ts_info,
2133         .set_phys_id       = mlx5e_set_phys_id,
2134         .get_wol           = mlx5e_get_wol,
2135         .set_wol           = mlx5e_set_wol,
2136         .get_module_info   = mlx5e_get_module_info,
2137         .get_module_eeprom = mlx5e_get_module_eeprom,
2138         .flash_device      = mlx5e_flash_device,
2139         .get_priv_flags    = mlx5e_get_priv_flags,
2140         .set_priv_flags    = mlx5e_set_priv_flags,
2141         .self_test         = mlx5e_self_test,
2142         .get_msglevel      = mlx5e_get_msglevel,
2143         .set_msglevel      = mlx5e_set_msglevel,
2144         .get_fecparam      = mlx5e_get_fecparam,
2145         .set_fecparam      = mlx5e_set_fecparam,
2146 };