2 * Copyright (c) 2016, Mellanox Technologies. All rights reserved.
4 * This software is available to you under a choice of one of two
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6 * General Public License (GPL) Version 2, available from the file
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8 * OpenIB.org BSD license below:
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11 * without modification, are permitted provided that the following
14 * - Redistributions of source code must retain the above
15 * copyright notice, this list of conditions and the following
18 * - Redistributions in binary form must reproduce the above
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21 * provided with the distribution.
23 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
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29 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
34 #include "lib/crypto.h"
36 /* mlx5e global resources should be placed in this file.
37 * Global resources are common to all the netdevices created on the same nic.
40 void mlx5e_mkey_set_relaxed_ordering(struct mlx5_core_dev *mdev, void *mkc)
42 bool ro_write = MLX5_CAP_GEN(mdev, relaxed_ordering_write);
43 bool ro_read = MLX5_CAP_GEN(mdev, relaxed_ordering_read) ||
44 (pcie_relaxed_ordering_enabled(mdev->pdev) &&
45 MLX5_CAP_GEN(mdev, relaxed_ordering_read_pci_enabled));
47 MLX5_SET(mkc, mkc, relaxed_ordering_read, ro_read);
48 MLX5_SET(mkc, mkc, relaxed_ordering_write, ro_write);
51 int mlx5e_create_mkey(struct mlx5_core_dev *mdev, u32 pdn, u32 *mkey)
53 int inlen = MLX5_ST_SZ_BYTES(create_mkey_in);
58 in = kvzalloc(inlen, GFP_KERNEL);
62 mkc = MLX5_ADDR_OF(create_mkey_in, in, memory_key_mkey_entry);
63 MLX5_SET(mkc, mkc, access_mode_1_0, MLX5_MKC_ACCESS_MODE_PA);
64 MLX5_SET(mkc, mkc, lw, 1);
65 MLX5_SET(mkc, mkc, lr, 1);
66 mlx5e_mkey_set_relaxed_ordering(mdev, mkc);
67 MLX5_SET(mkc, mkc, pd, pdn);
68 MLX5_SET(mkc, mkc, length64, 1);
69 MLX5_SET(mkc, mkc, qpn, 0xffffff);
71 err = mlx5_core_create_mkey(mdev, mkey, in, inlen);
77 int mlx5e_create_tis(struct mlx5_core_dev *mdev, void *in, u32 *tisn)
79 void *tisc = MLX5_ADDR_OF(create_tis_in, in, ctx);
81 MLX5_SET(tisc, tisc, transport_domain, mdev->mlx5e_res.hw_objs.td.tdn);
83 if (mlx5_lag_is_lacp_owner(mdev))
84 MLX5_SET(tisc, tisc, strict_lag_tx_port_affinity, 1);
86 return mlx5_core_create_tis(mdev, in, tisn);
89 void mlx5e_destroy_tis(struct mlx5_core_dev *mdev, u32 tisn)
91 mlx5_core_destroy_tis(mdev, tisn);
94 static void mlx5e_destroy_tises(struct mlx5_core_dev *mdev, u32 tisn[MLX5_MAX_PORTS][MLX5_MAX_NUM_TC])
98 for (i = 0; i < MLX5_MAX_PORTS; i++)
99 for (tc = 0; tc < MLX5_MAX_NUM_TC; tc++)
100 mlx5e_destroy_tis(mdev, tisn[i][tc]);
103 static bool mlx5_lag_should_assign_affinity(struct mlx5_core_dev *mdev)
105 return MLX5_CAP_GEN(mdev, lag_tx_port_affinity) && mlx5e_get_num_lag_ports(mdev) > 1;
108 static int mlx5e_create_tises(struct mlx5_core_dev *mdev, u32 tisn[MLX5_MAX_PORTS][MLX5_MAX_NUM_TC])
113 for (i = 0; i < MLX5_MAX_PORTS; i++) {
114 for (tc = 0; tc < MLX5_MAX_NUM_TC; tc++) {
115 u32 in[MLX5_ST_SZ_DW(create_tis_in)] = {};
118 tisc = MLX5_ADDR_OF(create_tis_in, in, ctx);
120 MLX5_SET(tisc, tisc, prio, tc << 1);
122 if (mlx5_lag_should_assign_affinity(mdev))
123 MLX5_SET(tisc, tisc, lag_tx_port_affinity, i + 1);
125 err = mlx5e_create_tis(mdev, in, &tisn[i][tc]);
127 goto err_close_tises;
134 for (; i >= 0; i--) {
135 for (tc--; tc >= 0; tc--)
136 mlx5e_destroy_tis(mdev, tisn[i][tc]);
137 tc = MLX5_MAX_NUM_TC;
143 int mlx5e_create_mdev_resources(struct mlx5_core_dev *mdev)
145 struct mlx5e_hw_objs *res = &mdev->mlx5e_res.hw_objs;
148 err = mlx5_core_alloc_pd(mdev, &res->pdn);
150 mlx5_core_err(mdev, "alloc pd failed, %d\n", err);
154 err = mlx5_core_alloc_transport_domain(mdev, &res->td.tdn);
156 mlx5_core_err(mdev, "alloc td failed, %d\n", err);
160 err = mlx5e_create_mkey(mdev, res->pdn, &res->mkey);
162 mlx5_core_err(mdev, "create mkey failed, %d\n", err);
163 goto err_dealloc_transport_domain;
166 err = mlx5_alloc_bfreg(mdev, &res->bfreg, false, false);
168 mlx5_core_err(mdev, "alloc bfreg failed, %d\n", err);
169 goto err_destroy_mkey;
172 err = mlx5e_create_tises(mdev, res->tisn);
174 mlx5_core_err(mdev, "alloc tises failed, %d\n", err);
175 goto err_destroy_bfreg;
177 INIT_LIST_HEAD(&res->td.tirs_list);
178 mutex_init(&res->td.list_lock);
180 mdev->mlx5e_res.dek_priv = mlx5_crypto_dek_init(mdev);
181 if (IS_ERR(mdev->mlx5e_res.dek_priv)) {
182 mlx5_core_err(mdev, "crypto dek init failed, %ld\n",
183 PTR_ERR(mdev->mlx5e_res.dek_priv));
184 mdev->mlx5e_res.dek_priv = NULL;
190 mlx5_free_bfreg(mdev, &res->bfreg);
192 mlx5_core_destroy_mkey(mdev, res->mkey);
193 err_dealloc_transport_domain:
194 mlx5_core_dealloc_transport_domain(mdev, res->td.tdn);
196 mlx5_core_dealloc_pd(mdev, res->pdn);
200 void mlx5e_destroy_mdev_resources(struct mlx5_core_dev *mdev)
202 struct mlx5e_hw_objs *res = &mdev->mlx5e_res.hw_objs;
204 mlx5_crypto_dek_cleanup(mdev->mlx5e_res.dek_priv);
205 mdev->mlx5e_res.dek_priv = NULL;
206 mlx5e_destroy_tises(mdev, res->tisn);
207 mlx5_free_bfreg(mdev, &res->bfreg);
208 mlx5_core_destroy_mkey(mdev, res->mkey);
209 mlx5_core_dealloc_transport_domain(mdev, res->td.tdn);
210 mlx5_core_dealloc_pd(mdev, res->pdn);
211 memset(res, 0, sizeof(*res));
214 int mlx5e_refresh_tirs(struct mlx5e_priv *priv, bool enable_uc_lb,
217 struct mlx5_core_dev *mdev = priv->mdev;
218 struct mlx5e_tir *tir;
225 inlen = MLX5_ST_SZ_BYTES(modify_tir_in);
226 in = kvzalloc(inlen, GFP_KERNEL);
231 lb_flags = MLX5_TIRC_SELF_LB_BLOCK_BLOCK_UNICAST;
234 lb_flags |= MLX5_TIRC_SELF_LB_BLOCK_BLOCK_MULTICAST;
237 MLX5_SET(modify_tir_in, in, ctx.self_lb_block, lb_flags);
239 MLX5_SET(modify_tir_in, in, bitmask.self_lb_en, 1);
241 mutex_lock(&mdev->mlx5e_res.hw_objs.td.list_lock);
242 list_for_each_entry(tir, &mdev->mlx5e_res.hw_objs.td.tirs_list, list) {
244 err = mlx5_core_modify_tir(mdev, tirn, in);
248 mutex_unlock(&mdev->mlx5e_res.hw_objs.td.list_lock);
252 netdev_err(priv->netdev, "refresh tir(0x%x) failed, %d\n", tirn, err);