2 * Copyright (c) 2015-2016, Mellanox Technologies. All rights reserved.
4 * This software is available to you under a choice of one of two
5 * licenses. You may choose to be licensed under the terms of the GNU
6 * General Public License (GPL) Version 2, available from the file
7 * COPYING in the main directory of this source tree, or the
8 * OpenIB.org BSD license below:
10 * Redistribution and use in source and binary forms, with or
11 * without modification, are permitted provided that the following
14 * - Redistributions of source code must retain the above
15 * copyright notice, this list of conditions and the following
18 * - Redistributions in binary form must reproduce the above
19 * copyright notice, this list of conditions and the following
20 * disclaimer in the documentation and/or other materials
21 * provided with the distribution.
23 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
24 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
25 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
26 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
27 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
28 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
29 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
35 #include <linux/if_vlan.h>
36 #include <linux/etherdevice.h>
37 #include <linux/timecounter.h>
38 #include <linux/net_tstamp.h>
39 #include <linux/crash_dump.h>
40 #include <linux/mlx5/driver.h>
41 #include <linux/mlx5/qp.h>
42 #include <linux/mlx5/cq.h>
43 #include <linux/mlx5/port.h>
44 #include <linux/mlx5/vport.h>
45 #include <linux/mlx5/transobj.h>
46 #include <linux/mlx5/fs.h>
47 #include <linux/rhashtable.h>
48 #include <net/udp_tunnel.h>
49 #include <net/switchdev.h>
51 #include <linux/dim.h>
52 #include <linux/bits.h>
54 #include "mlx5_core.h"
59 #include "lib/hv_vhca.h"
60 #include "lib/clock.h"
61 #include "en/rx_res.h"
64 extern const struct net_device_ops mlx5e_netdev_ops;
67 #define MLX5E_METADATA_ETHER_TYPE (0x8CE4)
68 #define MLX5E_METADATA_ETHER_LEN 8
70 #define MLX5E_ETH_HARD_MTU (ETH_HLEN + VLAN_HLEN + ETH_FCS_LEN)
72 #define MLX5E_HW2SW_MTU(params, hwmtu) ((hwmtu) - ((params)->hard_mtu))
73 #define MLX5E_SW2HW_MTU(params, swmtu) ((swmtu) + ((params)->hard_mtu))
75 #define MLX5E_MAX_NUM_TC 8
76 #define MLX5E_MAX_NUM_MQPRIO_CH_TC TC_QOPT_MAX_QUEUE
78 #define MLX5_RX_HEADROOM NET_SKB_PAD
79 #define MLX5_SKB_FRAG_SZ(len) (SKB_DATA_ALIGN(len) + \
80 SKB_DATA_ALIGN(sizeof(struct skb_shared_info)))
82 #define MLX5E_RX_MAX_HEAD (256)
83 #define MLX5E_SHAMPO_LOG_MAX_HEADER_ENTRY_SIZE (9)
84 #define MLX5E_SHAMPO_WQ_HEADER_PER_PAGE (PAGE_SIZE >> MLX5E_SHAMPO_LOG_MAX_HEADER_ENTRY_SIZE)
85 #define MLX5E_SHAMPO_WQ_BASE_HEAD_ENTRY_SIZE (64)
86 #define MLX5E_SHAMPO_WQ_RESRV_SIZE (64 * 1024)
87 #define MLX5E_SHAMPO_WQ_BASE_RESRV_SIZE (4096)
89 #define MLX5_MPWRQ_MIN_LOG_STRIDE_SZ(mdev) \
90 (6 + MLX5_CAP_GEN(mdev, cache_line_128byte)) /* HW restriction */
91 #define MLX5_MPWRQ_LOG_STRIDE_SZ(mdev, req) \
92 max_t(u32, MLX5_MPWRQ_MIN_LOG_STRIDE_SZ(mdev), req)
93 #define MLX5_MPWRQ_DEF_LOG_STRIDE_SZ(mdev) \
94 MLX5_MPWRQ_LOG_STRIDE_SZ(mdev, order_base_2(MLX5E_RX_MAX_HEAD))
96 #define MLX5_MPWRQ_LOG_WQE_SZ 18
97 #define MLX5_MPWRQ_WQE_PAGE_ORDER (MLX5_MPWRQ_LOG_WQE_SZ - PAGE_SHIFT > 0 ? \
98 MLX5_MPWRQ_LOG_WQE_SZ - PAGE_SHIFT : 0)
99 #define MLX5_MPWRQ_PAGES_PER_WQE BIT(MLX5_MPWRQ_WQE_PAGE_ORDER)
101 #define MLX5_ALIGN_MTTS(mtts) (ALIGN(mtts, 8))
102 #define MLX5_ALIGNED_MTTS_OCTW(mtts) ((mtts) / 2)
103 #define MLX5_MTT_OCTW(mtts) (MLX5_ALIGNED_MTTS_OCTW(MLX5_ALIGN_MTTS(mtts)))
104 /* Add another page to MLX5E_REQUIRED_WQE_MTTS as a buffer between
105 * WQEs, This page will absorb write overflow by the hardware, when
106 * receiving packets larger than MTU. These oversize packets are
107 * dropped by the driver at a later stage.
109 #define MLX5E_REQUIRED_WQE_MTTS (MLX5_ALIGN_MTTS(MLX5_MPWRQ_PAGES_PER_WQE + 1))
110 #define MLX5E_REQUIRED_MTTS(wqes) (wqes * MLX5E_REQUIRED_WQE_MTTS)
111 #define MLX5E_MAX_RQ_NUM_MTTS \
112 ((1 << 16) * 2) /* So that MLX5_MTT_OCTW(num_mtts) fits into u16 */
113 #define MLX5E_ORDER2_MAX_PACKET_MTU (order_base_2(10 * 1024))
114 #define MLX5E_PARAMS_MAXIMUM_LOG_RQ_SIZE_MPW \
115 (ilog2(MLX5E_MAX_RQ_NUM_MTTS / MLX5E_REQUIRED_WQE_MTTS))
116 #define MLX5E_LOG_MAX_RQ_NUM_PACKETS_MPW \
117 (MLX5E_PARAMS_MAXIMUM_LOG_RQ_SIZE_MPW + \
118 (MLX5_MPWRQ_LOG_WQE_SZ - MLX5E_ORDER2_MAX_PACKET_MTU))
120 #define MLX5E_MIN_SKB_FRAG_SZ (MLX5_SKB_FRAG_SZ(MLX5_RX_HEADROOM))
121 #define MLX5E_LOG_MAX_RX_WQE_BULK \
122 (ilog2(PAGE_SIZE / roundup_pow_of_two(MLX5E_MIN_SKB_FRAG_SZ)))
124 #define MLX5E_PARAMS_MINIMUM_LOG_SQ_SIZE 0x6
125 #define MLX5E_PARAMS_DEFAULT_LOG_SQ_SIZE 0xa
126 #define MLX5E_PARAMS_MAXIMUM_LOG_SQ_SIZE 0xd
128 #define MLX5E_PARAMS_MINIMUM_LOG_RQ_SIZE (1 + MLX5E_LOG_MAX_RX_WQE_BULK)
129 #define MLX5E_PARAMS_DEFAULT_LOG_RQ_SIZE 0xa
130 #define MLX5E_PARAMS_MAXIMUM_LOG_RQ_SIZE min_t(u8, 0xd, \
131 MLX5E_LOG_MAX_RQ_NUM_PACKETS_MPW)
133 #define MLX5E_PARAMS_MINIMUM_LOG_RQ_SIZE_MPW 0x2
135 #define MLX5E_DEFAULT_LRO_TIMEOUT 32
136 #define MLX5E_LRO_TIMEOUT_ARR_SIZE 4
138 #define MLX5E_PARAMS_DEFAULT_RX_CQ_MODERATION_USEC 0x10
139 #define MLX5E_PARAMS_DEFAULT_RX_CQ_MODERATION_USEC_FROM_CQE 0x3
140 #define MLX5E_PARAMS_DEFAULT_RX_CQ_MODERATION_PKTS 0x20
141 #define MLX5E_PARAMS_DEFAULT_TX_CQ_MODERATION_USEC 0x10
142 #define MLX5E_PARAMS_DEFAULT_TX_CQ_MODERATION_USEC_FROM_CQE 0x10
143 #define MLX5E_PARAMS_DEFAULT_TX_CQ_MODERATION_PKTS 0x20
144 #define MLX5E_PARAMS_DEFAULT_MIN_RX_WQES 0x80
145 #define MLX5E_PARAMS_DEFAULT_MIN_RX_WQES_MPW 0x2
147 #define MLX5E_MIN_NUM_CHANNELS 0x1
148 #define MLX5E_MAX_NUM_CHANNELS (MLX5E_INDIR_RQT_SIZE / 2)
149 #define MLX5E_TX_CQ_POLL_BUDGET 128
150 #define MLX5E_TX_XSK_POLL_BUDGET 64
151 #define MLX5E_SQ_RECOVER_MIN_INTERVAL 500 /* msecs */
153 #define MLX5E_UMR_WQE_INLINE_SZ \
154 (sizeof(struct mlx5e_umr_wqe) + \
155 ALIGN(MLX5_MPWRQ_PAGES_PER_WQE * sizeof(struct mlx5_mtt), \
156 MLX5_UMR_MTT_ALIGNMENT))
157 #define MLX5E_UMR_WQEBBS \
158 (DIV_ROUND_UP(MLX5E_UMR_WQE_INLINE_SZ, MLX5_SEND_WQE_BB))
160 #define MLX5E_KLM_UMR_WQE_SZ(sgl_len)\
161 (sizeof(struct mlx5e_umr_wqe) +\
162 (sizeof(struct mlx5_klm) * (sgl_len)))
164 #define MLX5E_KLM_UMR_WQEBBS(klm_entries) \
165 (DIV_ROUND_UP(MLX5E_KLM_UMR_WQE_SZ(klm_entries), MLX5_SEND_WQE_BB))
167 #define MLX5E_KLM_UMR_DS_CNT(klm_entries)\
168 (DIV_ROUND_UP(MLX5E_KLM_UMR_WQE_SZ(klm_entries), MLX5_SEND_WQE_DS))
170 #define MLX5E_KLM_MAX_ENTRIES_PER_WQE(wqe_size)\
171 (((wqe_size) - sizeof(struct mlx5e_umr_wqe)) / sizeof(struct mlx5_klm))
173 #define MLX5E_KLM_ENTRIES_PER_WQE(wqe_size)\
174 ALIGN_DOWN(MLX5E_KLM_MAX_ENTRIES_PER_WQE(wqe_size), MLX5_UMR_KLM_ALIGNMENT)
176 #define MLX5E_MAX_KLM_PER_WQE(mdev) \
177 MLX5E_KLM_ENTRIES_PER_WQE(mlx5e_get_sw_max_sq_mpw_wqebbs(mlx5e_get_max_sq_wqebbs(mdev)) \
178 << MLX5_MKEY_BSF_OCTO_SIZE)
180 #define MLX5E_MSG_LEVEL NETIF_MSG_LINK
182 #define mlx5e_dbg(mlevel, priv, format, ...) \
184 if (NETIF_MSG_##mlevel & (priv)->msglevel) \
185 netdev_warn(priv->netdev, format, \
189 #define mlx5e_state_dereference(priv, p) \
190 rcu_dereference_protected((p), lockdep_is_held(&(priv)->state_lock))
192 enum mlx5e_rq_group {
193 MLX5E_RQ_GROUP_REGULAR,
195 #define MLX5E_NUM_RQ_GROUPS(g) (1 + MLX5E_RQ_GROUP_##g)
198 static inline u8 mlx5e_get_num_lag_ports(struct mlx5_core_dev *mdev)
200 if (mlx5_lag_is_lacp_owner(mdev))
203 return clamp_t(u8, MLX5_CAP_GEN(mdev, num_lag_ports), 1, MLX5_MAX_PORTS);
206 static inline u16 mlx5_min_rx_wqes(int wq_type, u32 wq_size)
209 case MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ:
210 return min_t(u16, MLX5E_PARAMS_DEFAULT_MIN_RX_WQES_MPW,
213 return min_t(u16, MLX5E_PARAMS_DEFAULT_MIN_RX_WQES,
218 /* Use this function to get max num channels (rxqs/txqs) only to create netdev */
219 static inline int mlx5e_get_max_num_channels(struct mlx5_core_dev *mdev)
221 return is_kdump_kernel() ?
222 MLX5E_MIN_NUM_CHANNELS :
223 min_t(int, mlx5_comp_vectors_count(mdev), MLX5E_MAX_NUM_CHANNELS);
226 /* The maximum WQE size can be retrieved by max_wqe_sz_sq in
227 * bytes units. Driver hardens the limitation to 1KB (16
228 * WQEBBs), unless firmware capability is stricter.
230 static inline u16 mlx5e_get_max_sq_wqebbs(struct mlx5_core_dev *mdev)
232 return min_t(u16, MLX5_SEND_WQE_MAX_WQEBBS,
233 MLX5_CAP_GEN(mdev, max_wqe_sz_sq) / MLX5_SEND_WQE_BB);
236 static inline u16 mlx5e_get_sw_max_sq_mpw_wqebbs(u16 max_sq_wqebbs)
238 /* The return value will be multiplied by MLX5_SEND_WQEBB_NUM_DS.
239 * Since max_sq_wqebbs may be up to MLX5_SEND_WQE_MAX_WQEBBS == 16,
240 * see mlx5e_get_max_sq_wqebbs(), the multiplication (16 * 4 == 64)
241 * overflows the 6-bit DS field of Ctrl Segment. Use a bound lower
242 * than MLX5_SEND_WQE_MAX_WQEBBS to let a full-session WQE be
245 #if L1_CACHE_BYTES < 128
246 return min_t(u16, max_sq_wqebbs, MLX5_SEND_WQE_MAX_WQEBBS - 1);
248 return min_t(u16, max_sq_wqebbs, MLX5_SEND_WQE_MAX_WQEBBS - 2);
252 struct mlx5e_tx_wqe {
253 struct mlx5_wqe_ctrl_seg ctrl;
254 struct mlx5_wqe_eth_seg eth;
255 struct mlx5_wqe_data_seg data[];
258 struct mlx5e_rx_wqe_ll {
259 struct mlx5_wqe_srq_next_seg next;
260 struct mlx5_wqe_data_seg data[];
263 struct mlx5e_rx_wqe_cyc {
264 struct mlx5_wqe_data_seg data[0];
267 struct mlx5e_umr_wqe {
268 struct mlx5_wqe_ctrl_seg ctrl;
269 struct mlx5_wqe_umr_ctrl_seg uctrl;
270 struct mlx5_mkey_seg mkc;
272 DECLARE_FLEX_ARRAY(struct mlx5_mtt, inline_mtts);
273 DECLARE_FLEX_ARRAY(struct mlx5_klm, inline_klms);
277 enum mlx5e_priv_flag {
278 MLX5E_PFLAG_RX_CQE_BASED_MODER,
279 MLX5E_PFLAG_TX_CQE_BASED_MODER,
280 MLX5E_PFLAG_RX_CQE_COMPRESS,
281 MLX5E_PFLAG_RX_STRIDING_RQ,
282 MLX5E_PFLAG_RX_NO_CSUM_COMPLETE,
283 MLX5E_PFLAG_XDP_TX_MPWQE,
284 MLX5E_PFLAG_SKB_TX_MPWQE,
285 MLX5E_PFLAG_TX_PORT_TS,
286 MLX5E_NUM_PFLAGS, /* Keep last */
289 #define MLX5E_SET_PFLAG(params, pflag, enable) \
292 (params)->pflags |= BIT(pflag); \
294 (params)->pflags &= ~(BIT(pflag)); \
297 #define MLX5E_GET_PFLAG(params, pflag) (!!((params)->pflags & (BIT(pflag))))
300 MLX5E_PACKET_MERGE_NONE,
301 MLX5E_PACKET_MERGE_LRO,
302 MLX5E_PACKET_MERGE_SHAMPO,
305 struct mlx5e_packet_merge_param {
306 enum packet_merge type;
309 u8 match_criteria_type;
310 u8 alignment_granularity;
314 struct mlx5e_params {
317 u8 log_rq_mtu_frames;
322 struct netdev_tc_txq tc_to_txq[TC_MAX_QUEUE];
324 u64 max_rate[TC_MAX_QUEUE];
325 u32 hw_id[TC_MAX_QUEUE];
328 bool rx_cqe_compress_def;
329 bool tunneled_offload_en;
330 struct dim_cq_moder rx_cq_moderation;
331 struct dim_cq_moder tx_cq_moderation;
332 struct mlx5e_packet_merge_param packet_merge;
333 u8 tx_min_inline_mode;
334 bool vlan_strip_disable;
339 struct bpf_prog *xdp_prog;
340 struct mlx5e_xsk *xsk;
346 static inline u8 mlx5e_get_dcb_num_tc(struct mlx5e_params *params)
348 return params->mqprio.mode == TC_MQPRIO_MODE_DCB ?
349 params->mqprio.num_tc : 1;
353 MLX5E_RQ_STATE_ENABLED,
354 MLX5E_RQ_STATE_RECOVERING,
356 MLX5E_RQ_STATE_NO_CSUM_COMPLETE,
357 MLX5E_RQ_STATE_CSUM_FULL, /* cqe_csum_full hw bit is set */
358 MLX5E_RQ_STATE_MINI_CQE_HW_STRIDX, /* set when mini_cqe_resp_stride_index cap is used */
359 MLX5E_RQ_STATE_SHAMPO, /* set when SHAMPO cap is used */
363 /* data path - accessed per cqe */
366 /* data path - accessed per napi poll */
368 struct napi_struct *napi;
369 struct mlx5_core_cq mcq;
370 struct mlx5e_ch_stats *ch_stats;
373 struct net_device *netdev;
374 struct mlx5_core_dev *mdev;
375 struct mlx5e_priv *priv;
376 struct mlx5_wq_ctrl wq_ctrl;
377 } ____cacheline_aligned_in_smp;
379 struct mlx5e_cq_decomp {
380 /* cqe decompression */
381 struct mlx5_cqe64 title;
382 struct mlx5_mini_cqe8 mini_arr[MLX5_MINI_CQE_ARRAY_SIZE];
386 } ____cacheline_aligned_in_smp;
388 enum mlx5e_dma_map_type {
389 MLX5E_DMA_MAP_SINGLE,
393 struct mlx5e_sq_dma {
396 enum mlx5e_dma_map_type type;
400 MLX5E_SQ_STATE_ENABLED,
401 MLX5E_SQ_STATE_MPWQE,
402 MLX5E_SQ_STATE_RECOVERING,
403 MLX5E_SQ_STATE_IPSEC,
405 MLX5E_SQ_STATE_VLAN_NEED_L2_INLINE,
406 MLX5E_SQ_STATE_PENDING_XSK_TX,
407 MLX5E_SQ_STATE_PENDING_TLS_RX_RESYNC,
408 MLX5E_SQ_STATE_XDP_MULTIBUF,
411 struct mlx5e_tx_mpwqe {
412 /* Current MPWQE session */
413 struct mlx5e_tx_wqe *wqe;
420 struct mlx5e_skb_fifo {
421 struct sk_buff **fifo;
432 /* dirtied @completion */
436 struct dim dim; /* Adaptive Moderation */
439 u16 pc ____cacheline_aligned_in_smp;
442 struct mlx5e_tx_mpwqe mpwqe;
447 struct mlx5_wq_cyc wq;
449 struct mlx5e_sq_stats *stats;
451 struct mlx5e_sq_dma *dma_fifo;
452 struct mlx5e_skb_fifo skb_fifo;
453 struct mlx5e_tx_wqe_info *wqe_info;
455 void __iomem *uar_map;
456 struct netdev_queue *txq;
459 u16 max_sq_mpw_wqebbs;
465 struct mlx5_clock *clock;
466 struct net_device *netdev;
467 struct mlx5_core_dev *mdev;
468 struct mlx5e_priv *priv;
471 struct mlx5_wq_ctrl wq_ctrl;
475 struct work_struct recover_work;
476 struct mlx5e_ptpsq *ptpsq;
477 cqe_ts_to_ns ptp_cyc2time;
479 } ____cacheline_aligned_in_smp;
481 struct mlx5e_dma_info {
485 struct xdp_buff *xsk;
489 /* XDP packets can be transmitted in different ways. On completion, we need to
490 * distinguish between them to clean up things in a proper way.
492 enum mlx5e_xdp_xmit_mode {
493 /* An xdp_frame was transmitted due to either XDP_REDIRECT from another
494 * device or XDP_TX from an XSK RQ. The frame has to be unmapped and
497 MLX5E_XDP_XMIT_MODE_FRAME,
499 /* The xdp_frame was created in place as a result of XDP_TX from a
500 * regular RQ. No DMA remapping happened, and the page belongs to us.
502 MLX5E_XDP_XMIT_MODE_PAGE,
504 /* No xdp_frame was created at all, the transmit happened from a UMEM
505 * page. The UMEM Completion Ring producer pointer has to be increased.
507 MLX5E_XDP_XMIT_MODE_XSK,
510 struct mlx5e_xdp_info {
511 enum mlx5e_xdp_xmit_mode mode;
514 struct xdp_frame *xdpf;
524 struct mlx5e_xmit_data {
530 struct mlx5e_xdp_info_fifo {
531 struct mlx5e_xdp_info *xi;
538 typedef int (*mlx5e_fp_xmit_xdp_frame_check)(struct mlx5e_xdpsq *);
539 typedef bool (*mlx5e_fp_xmit_xdp_frame)(struct mlx5e_xdpsq *,
540 struct mlx5e_xmit_data *,
541 struct skb_shared_info *,
547 /* dirtied @completion */
552 u32 xdpi_fifo_pc ____cacheline_aligned_in_smp;
554 struct mlx5_wqe_ctrl_seg *doorbell_cseg;
555 struct mlx5e_tx_mpwqe mpwqe;
560 struct xsk_buff_pool *xsk_pool;
561 struct mlx5_wq_cyc wq;
562 struct mlx5e_xdpsq_stats *stats;
563 mlx5e_fp_xmit_xdp_frame_check xmit_xdp_frame_check;
564 mlx5e_fp_xmit_xdp_frame xmit_xdp_frame;
566 struct mlx5e_xdp_wqe_info *wqe_info;
567 struct mlx5e_xdp_info_fifo xdpi_fifo;
569 void __iomem *uar_map;
574 u16 max_sq_mpw_wqebbs;
580 struct mlx5_wq_ctrl wq_ctrl;
581 struct mlx5e_channel *channel;
583 } ____cacheline_aligned_in_smp;
585 struct mlx5e_ktls_resync_resp;
592 struct mlx5_wqe_ctrl_seg *doorbell_cseg;
595 /* write@xmit, read@completion */
597 struct mlx5e_icosq_wqe_info *wqe_info;
601 struct mlx5_wq_cyc wq;
602 void __iomem *uar_map;
606 struct mlx5e_ktls_resync_resp *ktls_resync;
609 struct mlx5_wq_ctrl wq_ctrl;
610 struct mlx5e_channel *channel;
613 struct work_struct recover_work;
614 } ____cacheline_aligned_in_smp;
616 struct mlx5e_wqe_frag_info {
617 struct mlx5e_dma_info *di;
622 struct mlx5e_umr_dma_info {
623 struct mlx5e_dma_info dma_info[MLX5_MPWRQ_PAGES_PER_WQE];
626 struct mlx5e_mpw_info {
627 struct mlx5e_umr_dma_info umr;
628 u16 consumed_strides;
629 DECLARE_BITMAP(xdp_xmit_bitmap, MLX5_MPWRQ_PAGES_PER_WQE);
632 #define MLX5E_MAX_RX_FRAGS 4
634 /* a single cache unit is capable to serve one napi call (for non-striding rq)
635 * or a MPWQE (for striding rq).
637 #define MLX5E_CACHE_UNIT (MLX5_MPWRQ_PAGES_PER_WQE > NAPI_POLL_WEIGHT ? \
638 MLX5_MPWRQ_PAGES_PER_WQE : NAPI_POLL_WEIGHT)
639 #define MLX5E_CACHE_SIZE (4 * roundup_pow_of_two(MLX5E_CACHE_UNIT))
640 struct mlx5e_page_cache {
643 struct mlx5e_dma_info page_cache[MLX5E_CACHE_SIZE];
647 typedef void (*mlx5e_fp_handle_rx_cqe)(struct mlx5e_rq*, struct mlx5_cqe64*);
648 typedef struct sk_buff *
649 (*mlx5e_fp_skb_from_cqe_mpwrq)(struct mlx5e_rq *rq, struct mlx5e_mpw_info *wi,
650 u16 cqe_bcnt, u32 head_offset, u32 page_idx);
651 typedef struct sk_buff *
652 (*mlx5e_fp_skb_from_cqe)(struct mlx5e_rq *rq, struct mlx5e_wqe_frag_info *wi,
654 typedef bool (*mlx5e_fp_post_rx_wqes)(struct mlx5e_rq *rq);
655 typedef void (*mlx5e_fp_dealloc_wqe)(struct mlx5e_rq*, u16);
656 typedef void (*mlx5e_fp_shampo_dealloc_hd)(struct mlx5e_rq*, u16, u16, bool);
658 int mlx5e_rq_set_handlers(struct mlx5e_rq *rq, struct mlx5e_params *params, bool xsk);
659 void mlx5e_rq_set_trap_handlers(struct mlx5e_rq *rq, struct mlx5e_params *params);
662 MLX5E_RQ_FLAG_XDP_XMIT,
663 MLX5E_RQ_FLAG_XDP_REDIRECT,
666 struct mlx5e_rq_frag_info {
671 struct mlx5e_rq_frags_info {
672 struct mlx5e_rq_frag_info arr[MLX5E_MAX_RX_FRAGS];
678 struct mlx5e_shampo_hd {
680 struct mlx5e_dma_info *info;
681 struct page *last_page;
684 unsigned long *bitmap;
691 struct mlx5e_hw_gro_data {
701 struct mlx5_wq_cyc wq;
702 struct mlx5e_wqe_frag_info *frags;
703 struct mlx5e_dma_info *di;
704 struct mlx5e_rq_frags_info info;
705 mlx5e_fp_skb_from_cqe skb_from_cqe;
708 struct mlx5_wq_ll wq;
709 struct mlx5e_umr_wqe umr_wqe;
710 struct mlx5e_mpw_info *info;
711 mlx5e_fp_skb_from_cqe_mpwrq skb_from_cqe_mpwrq;
719 struct mlx5e_shampo_hd *shampo;
725 u8 map_dir; /* dma map direction */
729 struct net_device *netdev;
730 struct mlx5e_rq_stats *stats;
732 struct mlx5e_cq_decomp cqd;
733 struct mlx5e_page_cache page_cache;
734 struct hwtstamp_config *tstamp;
735 struct mlx5_clock *clock;
736 struct mlx5e_icosq *icosq;
737 struct mlx5e_priv *priv;
739 struct mlx5e_hw_gro_data *hw_gro_data;
741 mlx5e_fp_handle_rx_cqe handle_rx_cqe;
742 mlx5e_fp_post_rx_wqes post_wqes;
743 mlx5e_fp_dealloc_wqe dealloc_wqe;
749 struct dim dim; /* Dynamic Interrupt Moderation */
752 struct bpf_prog __rcu *xdp_prog;
753 struct mlx5e_xdpsq *xdpsq;
754 DECLARE_BITMAP(flags, 8);
755 struct page_pool *page_pool;
757 /* AF_XDP zero-copy */
758 struct xsk_buff_pool *xsk_pool;
760 struct work_struct recover_work;
763 struct mlx5_wq_ctrl wq_ctrl;
767 struct mlx5_core_dev *mdev;
768 struct mlx5e_channel *channel;
770 struct mlx5e_dma_info wqe_overflow;
772 /* XDP read-mostly */
773 struct xdp_rxq_info xdp_rxq;
774 cqe_ts_to_ns ptp_cyc2time;
775 } ____cacheline_aligned_in_smp;
777 enum mlx5e_channel_state {
778 MLX5E_CHANNEL_STATE_XSK,
779 MLX5E_CHANNEL_NUM_STATES
782 struct mlx5e_channel {
785 struct mlx5e_xdpsq rq_xdpsq;
786 struct mlx5e_txqsq sq[MLX5E_MAX_NUM_TC];
787 struct mlx5e_icosq icosq; /* internal control operations */
788 struct mlx5e_txqsq __rcu * __rcu *qos_sqs;
790 struct napi_struct napi;
792 struct net_device *netdev;
799 struct mlx5e_xdpsq xdpsq;
801 /* AF_XDP zero-copy */
802 struct mlx5e_rq xskrq;
803 struct mlx5e_xdpsq xsksq;
806 struct mlx5e_icosq async_icosq;
807 /* async_icosq can be accessed from any CPU - the spinlock protects it. */
808 spinlock_t async_icosq_lock;
810 /* data path - accessed per napi poll */
811 const struct cpumask *aff_mask;
812 struct mlx5e_ch_stats *stats;
815 struct mlx5e_priv *priv;
816 struct mlx5_core_dev *mdev;
817 struct hwtstamp_config *tstamp;
818 DECLARE_BITMAP(state, MLX5E_CHANNEL_NUM_STATES);
821 /* Sync between icosq recovery and XSK enable/disable. */
822 struct mutex icosq_recovery_lock;
827 struct mlx5e_channels {
828 struct mlx5e_channel **c;
829 struct mlx5e_ptp *ptp;
831 struct mlx5e_params params;
834 struct mlx5e_channel_stats {
835 struct mlx5e_ch_stats ch;
836 struct mlx5e_sq_stats sq[MLX5E_MAX_NUM_TC];
837 struct mlx5e_rq_stats rq;
838 struct mlx5e_rq_stats xskrq;
839 struct mlx5e_xdpsq_stats rq_xdpsq;
840 struct mlx5e_xdpsq_stats xdpsq;
841 struct mlx5e_xdpsq_stats xsksq;
842 } ____cacheline_aligned_in_smp;
844 struct mlx5e_ptp_stats {
845 struct mlx5e_ch_stats ch;
846 struct mlx5e_sq_stats sq[MLX5E_MAX_NUM_TC];
847 struct mlx5e_ptp_cq_stats cq[MLX5E_MAX_NUM_TC];
848 struct mlx5e_rq_stats rq;
849 } ____cacheline_aligned_in_smp;
853 MLX5E_STATE_DESTROYING,
854 MLX5E_STATE_XDP_TX_ENABLED,
855 MLX5E_STATE_XDP_ACTIVE,
863 struct mlx5e_modify_sq_param {
869 u16 qos_queue_group_id;
872 #if IS_ENABLED(CONFIG_PCI_HYPERV_INTERFACE)
873 struct mlx5e_hv_vhca_stats_agent {
874 struct mlx5_hv_vhca_agent *agent;
875 struct delayed_work work;
882 /* XSK buffer pools are stored separately from channels,
883 * because we don't want to lose them when channels are
884 * recreated. The kernel also stores buffer pool, but it doesn't
885 * distinguish between zero-copy and non-zero-copy UMEMs, so
886 * rely on our mechanism.
888 struct xsk_buff_pool **pools;
893 /* Temporary storage for variables that are allocated when struct mlx5e_priv is
894 * initialized, and used where we can't allocate them because that functions
895 * must not fail. Use with care and make sure the same variable is not used
896 * simultaneously by multiple users.
898 struct mlx5e_scratchpad {
899 cpumask_var_t cpumask;
906 /* priv data path fields - start */
907 struct mlx5e_selq selq;
908 struct mlx5e_txqsq **txq2sq;
909 #ifdef CONFIG_MLX5_CORE_EN_DCB
910 struct mlx5e_dcbx_dp dcbx_dp;
912 /* priv data path fields - end */
916 struct mutex state_lock; /* Protects Interface state */
917 struct mlx5e_rq drop_rq;
919 struct mlx5e_channels channels;
920 u32 tisn[MLX5_MAX_PORTS][MLX5E_MAX_NUM_TC];
921 struct mlx5e_rx_res *rx_res;
924 struct mlx5e_flow_steering fs;
926 struct workqueue_struct *wq;
927 struct work_struct update_carrier_work;
928 struct work_struct set_rx_mode_work;
929 struct work_struct tx_timeout_work;
930 struct work_struct update_stats_work;
931 struct work_struct monitor_counters_work;
932 struct mlx5_nb monitor_counters_nb;
934 struct mlx5_core_dev *mdev;
935 struct net_device *netdev;
936 struct mlx5e_trap *en_trap;
937 struct mlx5e_stats stats;
938 struct mlx5e_channel_stats **channel_stats;
939 struct mlx5e_channel_stats trap_stats;
940 struct mlx5e_ptp_stats ptp_stats;
941 struct mlx5e_sq_stats **htb_qos_sq_stats;
948 struct hwtstamp_config tstamp;
950 u16 drop_rq_q_counter;
951 struct notifier_block events_nb;
952 struct notifier_block blocking_events_nb;
954 struct udp_tunnel_nic_info nic_info;
955 #ifdef CONFIG_MLX5_CORE_EN_DCB
956 struct mlx5e_dcbx dcbx;
959 const struct mlx5e_profile *profile;
961 #ifdef CONFIG_MLX5_EN_IPSEC
962 struct mlx5e_ipsec *ipsec;
964 #ifdef CONFIG_MLX5_EN_TLS
965 struct mlx5e_tls *tls;
967 struct devlink_health_reporter *tx_reporter;
968 struct devlink_health_reporter *rx_reporter;
969 struct mlx5e_xsk xsk;
970 #if IS_ENABLED(CONFIG_PCI_HYPERV_INTERFACE)
971 struct mlx5e_hv_vhca_stats_agent stats_agent;
973 struct mlx5e_scratchpad scratchpad;
974 struct mlx5e_htb *htb;
975 struct mlx5e_mqprio_rl *mqprio_rl;
978 struct mlx5e_rx_handlers {
979 mlx5e_fp_handle_rx_cqe handle_rx_cqe;
980 mlx5e_fp_handle_rx_cqe handle_rx_cqe_mpwqe;
981 mlx5e_fp_handle_rx_cqe handle_rx_cqe_mpwqe_shampo;
984 extern const struct mlx5e_rx_handlers mlx5e_rx_handlers_nic;
986 enum mlx5e_profile_feature {
987 MLX5E_PROFILE_FEATURE_PTP_RX,
988 MLX5E_PROFILE_FEATURE_PTP_TX,
989 MLX5E_PROFILE_FEATURE_QOS_HTB,
992 struct mlx5e_profile {
993 int (*init)(struct mlx5_core_dev *mdev,
994 struct net_device *netdev);
995 void (*cleanup)(struct mlx5e_priv *priv);
996 int (*init_rx)(struct mlx5e_priv *priv);
997 void (*cleanup_rx)(struct mlx5e_priv *priv);
998 int (*init_tx)(struct mlx5e_priv *priv);
999 void (*cleanup_tx)(struct mlx5e_priv *priv);
1000 void (*enable)(struct mlx5e_priv *priv);
1001 void (*disable)(struct mlx5e_priv *priv);
1002 int (*update_rx)(struct mlx5e_priv *priv);
1003 void (*update_stats)(struct mlx5e_priv *priv);
1004 void (*update_carrier)(struct mlx5e_priv *priv);
1005 int (*max_nch_limit)(struct mlx5_core_dev *mdev);
1006 unsigned int (*stats_grps_num)(struct mlx5e_priv *priv);
1007 mlx5e_stats_grp_t *stats_grps;
1008 const struct mlx5e_rx_handlers *rx_handlers;
1014 #define mlx5e_profile_feature_cap(profile, feature) \
1015 ((profile)->features & BIT(MLX5E_PROFILE_FEATURE_##feature))
1017 void mlx5e_build_ptys2ethtool_map(void);
1019 bool mlx5e_check_fragmented_striding_rq_cap(struct mlx5_core_dev *mdev);
1021 void mlx5e_shampo_dealloc_hd(struct mlx5e_rq *rq, u16 len, u16 start, bool close);
1022 void mlx5e_get_stats(struct net_device *dev, struct rtnl_link_stats64 *stats);
1023 void mlx5e_fold_sw_stats64(struct mlx5e_priv *priv, struct rtnl_link_stats64 *s);
1025 void mlx5e_init_l2_addr(struct mlx5e_priv *priv);
1026 int mlx5e_self_test_num(struct mlx5e_priv *priv);
1027 int mlx5e_self_test_fill_strings(struct mlx5e_priv *priv, u8 *data);
1028 void mlx5e_self_test(struct net_device *ndev, struct ethtool_test *etest,
1030 void mlx5e_set_rx_mode_work(struct work_struct *work);
1032 int mlx5e_hwstamp_set(struct mlx5e_priv *priv, struct ifreq *ifr);
1033 int mlx5e_hwstamp_get(struct mlx5e_priv *priv, struct ifreq *ifr);
1034 int mlx5e_modify_rx_cqe_compression_locked(struct mlx5e_priv *priv, bool val, bool rx_filter);
1036 int mlx5e_vlan_rx_add_vid(struct net_device *dev, __always_unused __be16 proto,
1038 int mlx5e_vlan_rx_kill_vid(struct net_device *dev, __always_unused __be16 proto,
1040 void mlx5e_timestamp_init(struct mlx5e_priv *priv);
1042 struct mlx5e_xsk_param;
1044 struct mlx5e_rq_param;
1045 int mlx5e_open_rq(struct mlx5e_params *params, struct mlx5e_rq_param *param,
1046 struct mlx5e_xsk_param *xsk, int node,
1047 struct mlx5e_rq *rq);
1048 int mlx5e_wait_for_min_rx_wqes(struct mlx5e_rq *rq, int wait_time);
1049 void mlx5e_close_rq(struct mlx5e_rq *rq);
1050 int mlx5e_create_rq(struct mlx5e_rq *rq, struct mlx5e_rq_param *param);
1051 void mlx5e_destroy_rq(struct mlx5e_rq *rq);
1053 struct mlx5e_sq_param;
1054 int mlx5e_open_xdpsq(struct mlx5e_channel *c, struct mlx5e_params *params,
1055 struct mlx5e_sq_param *param, struct xsk_buff_pool *xsk_pool,
1056 struct mlx5e_xdpsq *sq, bool is_redirect);
1057 void mlx5e_close_xdpsq(struct mlx5e_xdpsq *sq);
1059 struct mlx5e_create_cq_param {
1060 struct napi_struct *napi;
1061 struct mlx5e_ch_stats *ch_stats;
1066 struct mlx5e_cq_param;
1067 int mlx5e_open_cq(struct mlx5e_priv *priv, struct dim_cq_moder moder,
1068 struct mlx5e_cq_param *param, struct mlx5e_create_cq_param *ccp,
1069 struct mlx5e_cq *cq);
1070 void mlx5e_close_cq(struct mlx5e_cq *cq);
1072 int mlx5e_open_locked(struct net_device *netdev);
1073 int mlx5e_close_locked(struct net_device *netdev);
1075 void mlx5e_trigger_napi_icosq(struct mlx5e_channel *c);
1076 void mlx5e_trigger_napi_sched(struct napi_struct *napi);
1078 int mlx5e_open_channels(struct mlx5e_priv *priv,
1079 struct mlx5e_channels *chs);
1080 void mlx5e_close_channels(struct mlx5e_channels *chs);
1082 /* Function pointer to be used to modify HW or kernel settings while
1083 * switching channels
1085 typedef int (*mlx5e_fp_preactivate)(struct mlx5e_priv *priv, void *context);
1086 #define MLX5E_DEFINE_PREACTIVATE_WRAPPER_CTX(fn) \
1087 int fn##_ctx(struct mlx5e_priv *priv, void *context) \
1091 int mlx5e_safe_reopen_channels(struct mlx5e_priv *priv);
1092 int mlx5e_safe_switch_params(struct mlx5e_priv *priv,
1093 struct mlx5e_params *new_params,
1094 mlx5e_fp_preactivate preactivate,
1095 void *context, bool reset);
1096 int mlx5e_update_tx_netdev_queues(struct mlx5e_priv *priv);
1097 int mlx5e_num_channels_changed_ctx(struct mlx5e_priv *priv, void *context);
1098 void mlx5e_activate_priv_channels(struct mlx5e_priv *priv);
1099 void mlx5e_deactivate_priv_channels(struct mlx5e_priv *priv);
1100 int mlx5e_ptp_rx_manage_fs_ctx(struct mlx5e_priv *priv, void *ctx);
1102 int mlx5e_modify_rq_state(struct mlx5e_rq *rq, int curr_state, int next_state);
1103 void mlx5e_activate_rq(struct mlx5e_rq *rq);
1104 void mlx5e_deactivate_rq(struct mlx5e_rq *rq);
1105 void mlx5e_activate_icosq(struct mlx5e_icosq *icosq);
1106 void mlx5e_deactivate_icosq(struct mlx5e_icosq *icosq);
1108 int mlx5e_modify_sq(struct mlx5_core_dev *mdev, u32 sqn,
1109 struct mlx5e_modify_sq_param *p);
1110 int mlx5e_open_txqsq(struct mlx5e_channel *c, u32 tisn, int txq_ix,
1111 struct mlx5e_params *params, struct mlx5e_sq_param *param,
1112 struct mlx5e_txqsq *sq, int tc, u16 qos_queue_group_id,
1113 struct mlx5e_sq_stats *sq_stats);
1114 void mlx5e_activate_txqsq(struct mlx5e_txqsq *sq);
1115 void mlx5e_deactivate_txqsq(struct mlx5e_txqsq *sq);
1116 void mlx5e_free_txqsq(struct mlx5e_txqsq *sq);
1117 void mlx5e_tx_disable_queue(struct netdev_queue *txq);
1118 int mlx5e_alloc_txqsq_db(struct mlx5e_txqsq *sq, int numa);
1119 void mlx5e_free_txqsq_db(struct mlx5e_txqsq *sq);
1120 struct mlx5e_create_sq_param;
1121 int mlx5e_create_sq_rdy(struct mlx5_core_dev *mdev,
1122 struct mlx5e_sq_param *param,
1123 struct mlx5e_create_sq_param *csp,
1124 u16 qos_queue_group_id,
1126 void mlx5e_tx_err_cqe_work(struct work_struct *recover_work);
1127 void mlx5e_close_txqsq(struct mlx5e_txqsq *sq);
1129 static inline bool mlx5_tx_swp_supported(struct mlx5_core_dev *mdev)
1131 return MLX5_CAP_ETH(mdev, swp) &&
1132 MLX5_CAP_ETH(mdev, swp_csum) && MLX5_CAP_ETH(mdev, swp_lso);
1135 extern const struct ethtool_ops mlx5e_ethtool_ops;
1137 int mlx5e_create_mdev_resources(struct mlx5_core_dev *mdev);
1138 void mlx5e_destroy_mdev_resources(struct mlx5_core_dev *mdev);
1139 int mlx5e_refresh_tirs(struct mlx5e_priv *priv, bool enable_uc_lb,
1141 void mlx5e_mkey_set_relaxed_ordering(struct mlx5_core_dev *mdev, void *mkc);
1143 /* common netdev helpers */
1144 void mlx5e_create_q_counters(struct mlx5e_priv *priv);
1145 void mlx5e_destroy_q_counters(struct mlx5e_priv *priv);
1146 int mlx5e_open_drop_rq(struct mlx5e_priv *priv,
1147 struct mlx5e_rq *drop_rq);
1148 void mlx5e_close_drop_rq(struct mlx5e_rq *drop_rq);
1149 int mlx5e_init_di_list(struct mlx5e_rq *rq, int wq_sz, int node);
1150 void mlx5e_free_di_list(struct mlx5e_rq *rq);
1152 int mlx5e_create_tis(struct mlx5_core_dev *mdev, void *in, u32 *tisn);
1153 void mlx5e_destroy_tis(struct mlx5_core_dev *mdev, u32 tisn);
1155 int mlx5e_create_tises(struct mlx5e_priv *priv);
1156 void mlx5e_destroy_tises(struct mlx5e_priv *priv);
1157 int mlx5e_update_nic_rx(struct mlx5e_priv *priv);
1158 void mlx5e_update_carrier(struct mlx5e_priv *priv);
1159 int mlx5e_close(struct net_device *netdev);
1160 int mlx5e_open(struct net_device *netdev);
1162 void mlx5e_queue_update_stats(struct mlx5e_priv *priv);
1164 int mlx5e_set_dev_port_mtu(struct mlx5e_priv *priv);
1165 int mlx5e_set_dev_port_mtu_ctx(struct mlx5e_priv *priv, void *context);
1166 int mlx5e_change_mtu(struct net_device *netdev, int new_mtu,
1167 mlx5e_fp_preactivate preactivate);
1168 void mlx5e_vxlan_set_netdev_info(struct mlx5e_priv *priv);
1170 /* ethtool helpers */
1171 void mlx5e_ethtool_get_drvinfo(struct mlx5e_priv *priv,
1172 struct ethtool_drvinfo *drvinfo);
1173 void mlx5e_ethtool_get_strings(struct mlx5e_priv *priv,
1174 uint32_t stringset, uint8_t *data);
1175 int mlx5e_ethtool_get_sset_count(struct mlx5e_priv *priv, int sset);
1176 void mlx5e_ethtool_get_ethtool_stats(struct mlx5e_priv *priv,
1177 struct ethtool_stats *stats, u64 *data);
1178 void mlx5e_ethtool_get_ringparam(struct mlx5e_priv *priv,
1179 struct ethtool_ringparam *param,
1180 struct kernel_ethtool_ringparam *kernel_param);
1181 int mlx5e_ethtool_set_ringparam(struct mlx5e_priv *priv,
1182 struct ethtool_ringparam *param);
1183 void mlx5e_ethtool_get_channels(struct mlx5e_priv *priv,
1184 struct ethtool_channels *ch);
1185 int mlx5e_ethtool_set_channels(struct mlx5e_priv *priv,
1186 struct ethtool_channels *ch);
1187 int mlx5e_ethtool_get_coalesce(struct mlx5e_priv *priv,
1188 struct ethtool_coalesce *coal,
1189 struct kernel_ethtool_coalesce *kernel_coal);
1190 int mlx5e_ethtool_set_coalesce(struct mlx5e_priv *priv,
1191 struct ethtool_coalesce *coal,
1192 struct kernel_ethtool_coalesce *kernel_coal,
1193 struct netlink_ext_ack *extack);
1194 int mlx5e_ethtool_get_link_ksettings(struct mlx5e_priv *priv,
1195 struct ethtool_link_ksettings *link_ksettings);
1196 int mlx5e_ethtool_set_link_ksettings(struct mlx5e_priv *priv,
1197 const struct ethtool_link_ksettings *link_ksettings);
1198 int mlx5e_get_rxfh(struct net_device *netdev, u32 *indir, u8 *key, u8 *hfunc);
1199 int mlx5e_set_rxfh(struct net_device *dev, const u32 *indir, const u8 *key,
1201 int mlx5e_get_rxnfc(struct net_device *dev, struct ethtool_rxnfc *info,
1203 int mlx5e_set_rxnfc(struct net_device *dev, struct ethtool_rxnfc *cmd);
1204 u32 mlx5e_ethtool_get_rxfh_key_size(struct mlx5e_priv *priv);
1205 u32 mlx5e_ethtool_get_rxfh_indir_size(struct mlx5e_priv *priv);
1206 int mlx5e_ethtool_get_ts_info(struct mlx5e_priv *priv,
1207 struct ethtool_ts_info *info);
1208 int mlx5e_ethtool_flash_device(struct mlx5e_priv *priv,
1209 struct ethtool_flash *flash);
1210 void mlx5e_ethtool_get_pauseparam(struct mlx5e_priv *priv,
1211 struct ethtool_pauseparam *pauseparam);
1212 int mlx5e_ethtool_set_pauseparam(struct mlx5e_priv *priv,
1213 struct ethtool_pauseparam *pauseparam);
1215 /* mlx5e generic netdev management API */
1217 mlx5e_tx_mpwqe_supported(struct mlx5_core_dev *mdev)
1219 return !is_kdump_kernel() &&
1220 MLX5_CAP_ETH(mdev, enhanced_multi_pkt_send_wqe);
1223 int mlx5e_get_pf_num_tirs(struct mlx5_core_dev *mdev);
1224 int mlx5e_priv_init(struct mlx5e_priv *priv,
1225 const struct mlx5e_profile *profile,
1226 struct net_device *netdev,
1227 struct mlx5_core_dev *mdev);
1228 void mlx5e_priv_cleanup(struct mlx5e_priv *priv);
1230 mlx5e_create_netdev(struct mlx5_core_dev *mdev, const struct mlx5e_profile *profile);
1231 int mlx5e_attach_netdev(struct mlx5e_priv *priv);
1232 void mlx5e_detach_netdev(struct mlx5e_priv *priv);
1233 void mlx5e_destroy_netdev(struct mlx5e_priv *priv);
1234 int mlx5e_netdev_change_profile(struct mlx5e_priv *priv,
1235 const struct mlx5e_profile *new_profile, void *new_ppriv);
1236 void mlx5e_netdev_attach_nic_profile(struct mlx5e_priv *priv);
1237 void mlx5e_set_netdev_mtu_boundaries(struct mlx5e_priv *priv);
1238 void mlx5e_build_nic_params(struct mlx5e_priv *priv, struct mlx5e_xsk *xsk, u16 mtu);
1239 void mlx5e_rx_dim_work(struct work_struct *work);
1240 void mlx5e_tx_dim_work(struct work_struct *work);
1242 netdev_features_t mlx5e_features_check(struct sk_buff *skb,
1243 struct net_device *netdev,
1244 netdev_features_t features);
1245 int mlx5e_set_features(struct net_device *netdev, netdev_features_t features);
1246 #ifdef CONFIG_MLX5_ESWITCH
1247 int mlx5e_set_vf_mac(struct net_device *dev, int vf, u8 *mac);
1248 int mlx5e_set_vf_rate(struct net_device *dev, int vf, int min_tx_rate, int max_tx_rate);
1249 int mlx5e_get_vf_config(struct net_device *dev, int vf, struct ifla_vf_info *ivi);
1250 int mlx5e_get_vf_stats(struct net_device *dev, int vf, struct ifla_vf_stats *vf_stats);
1252 #endif /* __MLX5_EN_H__ */