2 * Copyright (c) 2015-2016, Mellanox Technologies. All rights reserved.
4 * This software is available to you under a choice of one of two
5 * licenses. You may choose to be licensed under the terms of the GNU
6 * General Public License (GPL) Version 2, available from the file
7 * COPYING in the main directory of this source tree, or the
8 * OpenIB.org BSD license below:
10 * Redistribution and use in source and binary forms, with or
11 * without modification, are permitted provided that the following
14 * - Redistributions of source code must retain the above
15 * copyright notice, this list of conditions and the following
18 * - Redistributions in binary form must reproduce the above
19 * copyright notice, this list of conditions and the following
20 * disclaimer in the documentation and/or other materials
21 * provided with the distribution.
23 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
24 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
25 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
26 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
27 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
28 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
29 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
35 #include <linux/if_vlan.h>
36 #include <linux/etherdevice.h>
37 #include <linux/timecounter.h>
38 #include <linux/net_tstamp.h>
39 #include <linux/ptp_clock_kernel.h>
40 #include <linux/crash_dump.h>
41 #include <linux/mlx5/driver.h>
42 #include <linux/mlx5/qp.h>
43 #include <linux/mlx5/cq.h>
44 #include <linux/mlx5/port.h>
45 #include <linux/mlx5/vport.h>
46 #include <linux/mlx5/transobj.h>
47 #include <linux/mlx5/fs.h>
48 #include <linux/rhashtable.h>
49 #include <net/switchdev.h>
51 #include <linux/net_dim.h>
52 #include <linux/bits.h>
54 #include "mlx5_core.h"
58 extern const struct net_device_ops mlx5e_netdev_ops;
61 #define MLX5E_METADATA_ETHER_TYPE (0x8CE4)
62 #define MLX5E_METADATA_ETHER_LEN 8
64 #define MLX5_SET_CFG(p, f, v) MLX5_SET(create_flow_group_in, p, f, v)
66 #define MLX5E_ETH_HARD_MTU (ETH_HLEN + VLAN_HLEN + ETH_FCS_LEN)
68 #define MLX5E_HW2SW_MTU(params, hwmtu) ((hwmtu) - ((params)->hard_mtu))
69 #define MLX5E_SW2HW_MTU(params, swmtu) ((swmtu) + ((params)->hard_mtu))
71 #define MLX5E_MAX_PRIORITY 8
72 #define MLX5E_MAX_DSCP 64
73 #define MLX5E_MAX_NUM_TC 8
75 #define MLX5_RX_HEADROOM NET_SKB_PAD
76 #define MLX5_SKB_FRAG_SZ(len) (SKB_DATA_ALIGN(len) + \
77 SKB_DATA_ALIGN(sizeof(struct skb_shared_info)))
79 #define MLX5E_RX_MAX_HEAD (256)
81 #define MLX5_MPWRQ_MIN_LOG_STRIDE_SZ(mdev) \
82 (6 + MLX5_CAP_GEN(mdev, cache_line_128byte)) /* HW restriction */
83 #define MLX5_MPWRQ_LOG_STRIDE_SZ(mdev, req) \
84 max_t(u32, MLX5_MPWRQ_MIN_LOG_STRIDE_SZ(mdev), req)
85 #define MLX5_MPWRQ_DEF_LOG_STRIDE_SZ(mdev) \
86 MLX5_MPWRQ_LOG_STRIDE_SZ(mdev, order_base_2(MLX5E_RX_MAX_HEAD))
88 #define MLX5_MPWRQ_LOG_WQE_SZ 18
89 #define MLX5_MPWRQ_WQE_PAGE_ORDER (MLX5_MPWRQ_LOG_WQE_SZ - PAGE_SHIFT > 0 ? \
90 MLX5_MPWRQ_LOG_WQE_SZ - PAGE_SHIFT : 0)
91 #define MLX5_MPWRQ_PAGES_PER_WQE BIT(MLX5_MPWRQ_WQE_PAGE_ORDER)
93 #define MLX5_MTT_OCTW(npages) (ALIGN(npages, 8) / 2)
94 #define MLX5E_REQUIRED_WQE_MTTS (ALIGN(MLX5_MPWRQ_PAGES_PER_WQE, 8))
95 #define MLX5E_LOG_ALIGNED_MPWQE_PPW (ilog2(MLX5E_REQUIRED_WQE_MTTS))
96 #define MLX5E_REQUIRED_MTTS(wqes) (wqes * MLX5E_REQUIRED_WQE_MTTS)
97 #define MLX5E_MAX_RQ_NUM_MTTS \
98 ((1 << 16) * 2) /* So that MLX5_MTT_OCTW(num_mtts) fits into u16 */
99 #define MLX5E_ORDER2_MAX_PACKET_MTU (order_base_2(10 * 1024))
100 #define MLX5E_PARAMS_MAXIMUM_LOG_RQ_SIZE_MPW \
101 (ilog2(MLX5E_MAX_RQ_NUM_MTTS / MLX5E_REQUIRED_WQE_MTTS))
102 #define MLX5E_LOG_MAX_RQ_NUM_PACKETS_MPW \
103 (MLX5E_PARAMS_MAXIMUM_LOG_RQ_SIZE_MPW + \
104 (MLX5_MPWRQ_LOG_WQE_SZ - MLX5E_ORDER2_MAX_PACKET_MTU))
106 #define MLX5E_MIN_SKB_FRAG_SZ (MLX5_SKB_FRAG_SZ(MLX5_RX_HEADROOM))
107 #define MLX5E_LOG_MAX_RX_WQE_BULK \
108 (ilog2(PAGE_SIZE / roundup_pow_of_two(MLX5E_MIN_SKB_FRAG_SZ)))
110 #define MLX5E_PARAMS_MINIMUM_LOG_SQ_SIZE 0x6
111 #define MLX5E_PARAMS_DEFAULT_LOG_SQ_SIZE 0xa
112 #define MLX5E_PARAMS_MAXIMUM_LOG_SQ_SIZE 0xd
114 #define MLX5E_PARAMS_MINIMUM_LOG_RQ_SIZE (1 + MLX5E_LOG_MAX_RX_WQE_BULK)
115 #define MLX5E_PARAMS_DEFAULT_LOG_RQ_SIZE 0xa
116 #define MLX5E_PARAMS_MAXIMUM_LOG_RQ_SIZE min_t(u8, 0xd, \
117 MLX5E_LOG_MAX_RQ_NUM_PACKETS_MPW)
119 #define MLX5E_PARAMS_MINIMUM_LOG_RQ_SIZE_MPW 0x2
121 #define MLX5E_PARAMS_DEFAULT_LRO_WQE_SZ (64 * 1024)
122 #define MLX5E_DEFAULT_LRO_TIMEOUT 32
123 #define MLX5E_LRO_TIMEOUT_ARR_SIZE 4
125 #define MLX5E_PARAMS_DEFAULT_RX_CQ_MODERATION_USEC 0x10
126 #define MLX5E_PARAMS_DEFAULT_RX_CQ_MODERATION_USEC_FROM_CQE 0x3
127 #define MLX5E_PARAMS_DEFAULT_RX_CQ_MODERATION_PKTS 0x20
128 #define MLX5E_PARAMS_DEFAULT_TX_CQ_MODERATION_USEC 0x10
129 #define MLX5E_PARAMS_DEFAULT_TX_CQ_MODERATION_USEC_FROM_CQE 0x10
130 #define MLX5E_PARAMS_DEFAULT_TX_CQ_MODERATION_PKTS 0x20
131 #define MLX5E_PARAMS_DEFAULT_MIN_RX_WQES 0x80
132 #define MLX5E_PARAMS_DEFAULT_MIN_RX_WQES_MPW 0x2
134 #define MLX5E_LOG_INDIR_RQT_SIZE 0x7
135 #define MLX5E_INDIR_RQT_SIZE BIT(MLX5E_LOG_INDIR_RQT_SIZE)
136 #define MLX5E_MIN_NUM_CHANNELS 0x1
137 #define MLX5E_MAX_NUM_CHANNELS (MLX5E_INDIR_RQT_SIZE >> 1)
138 #define MLX5E_MAX_NUM_SQS (MLX5E_MAX_NUM_CHANNELS * MLX5E_MAX_NUM_TC)
139 #define MLX5E_TX_CQ_POLL_BUDGET 128
140 #define MLX5E_SQ_RECOVER_MIN_INTERVAL 500 /* msecs */
142 #define MLX5E_UMR_WQE_INLINE_SZ \
143 (sizeof(struct mlx5e_umr_wqe) + \
144 ALIGN(MLX5_MPWRQ_PAGES_PER_WQE * sizeof(struct mlx5_mtt), \
145 MLX5_UMR_MTT_ALIGNMENT))
146 #define MLX5E_UMR_WQEBBS \
147 (DIV_ROUND_UP(MLX5E_UMR_WQE_INLINE_SZ, MLX5_SEND_WQE_BB))
149 #define MLX5E_MSG_LEVEL NETIF_MSG_LINK
151 #define mlx5e_dbg(mlevel, priv, format, ...) \
153 if (NETIF_MSG_##mlevel & (priv)->msglevel) \
154 netdev_warn(priv->netdev, format, \
159 static inline u16 mlx5_min_rx_wqes(int wq_type, u32 wq_size)
162 case MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ:
163 return min_t(u16, MLX5E_PARAMS_DEFAULT_MIN_RX_WQES_MPW,
166 return min_t(u16, MLX5E_PARAMS_DEFAULT_MIN_RX_WQES,
171 /* Use this function to get max num channels (rxqs/txqs) only to create netdev */
172 static inline int mlx5e_get_max_num_channels(struct mlx5_core_dev *mdev)
174 return is_kdump_kernel() ?
175 MLX5E_MIN_NUM_CHANNELS :
176 min_t(int, mlx5_comp_vectors_count(mdev), MLX5E_MAX_NUM_CHANNELS);
179 /* Use this function to get max num channels after netdev was created */
180 static inline int mlx5e_get_netdev_max_channels(struct net_device *netdev)
182 return min_t(unsigned int, netdev->num_rx_queues,
183 netdev->num_tx_queues);
186 struct mlx5e_tx_wqe {
187 struct mlx5_wqe_ctrl_seg ctrl;
188 struct mlx5_wqe_eth_seg eth;
189 struct mlx5_wqe_data_seg data[0];
192 struct mlx5e_rx_wqe_ll {
193 struct mlx5_wqe_srq_next_seg next;
194 struct mlx5_wqe_data_seg data[0];
197 struct mlx5e_rx_wqe_cyc {
198 struct mlx5_wqe_data_seg data[0];
201 struct mlx5e_umr_wqe {
202 struct mlx5_wqe_ctrl_seg ctrl;
203 struct mlx5_wqe_umr_ctrl_seg uctrl;
204 struct mlx5_mkey_seg mkc;
205 struct mlx5_mtt inline_mtts[0];
208 extern const char mlx5e_self_tests[][ETH_GSTRING_LEN];
210 enum mlx5e_priv_flag {
211 MLX5E_PFLAG_RX_CQE_BASED_MODER,
212 MLX5E_PFLAG_TX_CQE_BASED_MODER,
213 MLX5E_PFLAG_RX_CQE_COMPRESS,
214 MLX5E_PFLAG_RX_STRIDING_RQ,
215 MLX5E_PFLAG_RX_NO_CSUM_COMPLETE,
216 MLX5E_PFLAG_XDP_TX_MPWQE,
217 MLX5E_NUM_PFLAGS, /* Keep last */
220 #define MLX5E_SET_PFLAG(params, pflag, enable) \
223 (params)->pflags |= BIT(pflag); \
225 (params)->pflags &= ~(BIT(pflag)); \
228 #define MLX5E_GET_PFLAG(params, pflag) (!!((params)->pflags & (BIT(pflag))))
230 #ifdef CONFIG_MLX5_CORE_EN_DCB
231 #define MLX5E_MAX_BW_ALLOC 100 /* Max percentage of BW allocation */
234 struct mlx5e_params {
237 u8 log_rq_mtu_frames;
240 bool rx_cqe_compress_def;
241 struct net_dim_cq_moder rx_cq_moderation;
242 struct net_dim_cq_moder tx_cq_moderation;
245 u8 tx_min_inline_mode;
246 bool vlan_strip_disable;
252 struct bpf_prog *xdp_prog;
257 #ifdef CONFIG_MLX5_CORE_EN_DCB
258 struct mlx5e_cee_config {
259 /* bw pct for priority group */
260 u8 pg_bw_pct[CEE_DCBX_MAX_PGS];
261 u8 prio_to_pg_map[CEE_DCBX_MAX_PRIO];
262 bool pfc_setting[CEE_DCBX_MAX_PRIO];
269 MLX5_DCB_CHG_NO_RESET,
273 enum mlx5_dcbx_oper_mode mode;
274 struct mlx5e_cee_config cee_cfg; /* pending configuration */
277 /* The only setting that cannot be read from FW */
278 u8 tc_tsa[IEEE_8021QAZ_MAX_TCS];
281 /* Buffer configuration */
287 struct mlx5e_dcbx_dp {
288 u8 dscp2prio[MLX5E_MAX_DSCP];
294 MLX5E_RQ_STATE_ENABLED,
296 MLX5E_RQ_STATE_NO_CSUM_COMPLETE,
300 /* data path - accessed per cqe */
303 /* data path - accessed per napi poll */
305 struct napi_struct *napi;
306 struct mlx5_core_cq mcq;
307 struct mlx5e_channel *channel;
310 struct mlx5_core_dev *mdev;
311 struct mlx5_wq_ctrl wq_ctrl;
312 } ____cacheline_aligned_in_smp;
314 struct mlx5e_cq_decomp {
315 /* cqe decompression */
316 struct mlx5_cqe64 title;
317 struct mlx5_mini_cqe8 mini_arr[MLX5_MINI_CQE_ARRAY_SIZE];
321 } ____cacheline_aligned_in_smp;
323 struct mlx5e_tx_wqe_info {
330 enum mlx5e_dma_map_type {
331 MLX5E_DMA_MAP_SINGLE,
335 struct mlx5e_sq_dma {
338 enum mlx5e_dma_map_type type;
342 MLX5E_SQ_STATE_ENABLED,
343 MLX5E_SQ_STATE_RECOVERING,
344 MLX5E_SQ_STATE_IPSEC,
349 struct mlx5e_sq_wqe_info {
356 /* dirtied @completion */
359 struct net_dim dim; /* Adaptive Moderation */
362 u16 pc ____cacheline_aligned_in_smp;
368 struct mlx5_wq_cyc wq;
370 struct mlx5e_sq_stats *stats;
372 struct mlx5e_sq_dma *dma_fifo;
373 struct mlx5e_tx_wqe_info *wqe_info;
375 void __iomem *uar_map;
376 struct netdev_queue *txq;
382 struct hwtstamp_config *tstamp;
383 struct mlx5_clock *clock;
386 struct mlx5_wq_ctrl wq_ctrl;
387 struct mlx5e_channel *channel;
390 struct work_struct recover_work;
391 } ____cacheline_aligned_in_smp;
393 struct mlx5e_dma_info {
398 struct mlx5e_xdp_info {
399 struct xdp_frame *xdpf;
401 struct mlx5e_dma_info di;
404 struct mlx5e_xdp_info_fifo {
405 struct mlx5e_xdp_info *xi;
411 struct mlx5e_xdp_wqe_info {
416 struct mlx5e_xdp_mpwqe {
417 /* Current MPWQE session */
418 struct mlx5e_tx_wqe *wqe;
424 typedef bool (*mlx5e_fp_xmit_xdp_frame)(struct mlx5e_xdpsq*,
425 struct mlx5e_xdp_info*);
429 /* dirtied @completion */
435 u32 xdpi_fifo_pc ____cacheline_aligned_in_smp;
437 struct mlx5_wqe_ctrl_seg *doorbell_cseg;
438 struct mlx5e_xdp_mpwqe mpwqe;
443 struct mlx5_wq_cyc wq;
444 struct mlx5e_xdpsq_stats *stats;
445 mlx5e_fp_xmit_xdp_frame xmit_xdp_frame;
447 struct mlx5e_xdp_wqe_info *wqe_info;
448 struct mlx5e_xdp_info_fifo xdpi_fifo;
450 void __iomem *uar_map;
459 struct mlx5_wq_ctrl wq_ctrl;
460 struct mlx5e_channel *channel;
461 } ____cacheline_aligned_in_smp;
467 u16 pc ____cacheline_aligned_in_smp;
471 /* write@xmit, read@completion */
473 struct mlx5e_sq_wqe_info *ico_wqe;
477 struct mlx5_wq_cyc wq;
478 void __iomem *uar_map;
483 struct mlx5_wq_ctrl wq_ctrl;
484 struct mlx5e_channel *channel;
485 } ____cacheline_aligned_in_smp;
488 mlx5e_wqc_has_room_for(struct mlx5_wq_cyc *wq, u16 cc, u16 pc, u16 n)
490 return (mlx5_wq_cyc_ctr2ix(wq, cc - pc) >= n) || (cc == pc);
493 struct mlx5e_wqe_frag_info {
494 struct mlx5e_dma_info *di;
499 struct mlx5e_umr_dma_info {
500 struct mlx5e_dma_info dma_info[MLX5_MPWRQ_PAGES_PER_WQE];
503 struct mlx5e_mpw_info {
504 struct mlx5e_umr_dma_info umr;
505 u16 consumed_strides;
506 DECLARE_BITMAP(xdp_xmit_bitmap, MLX5_MPWRQ_PAGES_PER_WQE);
509 #define MLX5E_MAX_RX_FRAGS 4
511 /* a single cache unit is capable to serve one napi call (for non-striding rq)
512 * or a MPWQE (for striding rq).
514 #define MLX5E_CACHE_UNIT (MLX5_MPWRQ_PAGES_PER_WQE > NAPI_POLL_WEIGHT ? \
515 MLX5_MPWRQ_PAGES_PER_WQE : NAPI_POLL_WEIGHT)
516 #define MLX5E_CACHE_SIZE (4 * roundup_pow_of_two(MLX5E_CACHE_UNIT))
517 struct mlx5e_page_cache {
520 struct mlx5e_dma_info page_cache[MLX5E_CACHE_SIZE];
524 typedef void (*mlx5e_fp_handle_rx_cqe)(struct mlx5e_rq*, struct mlx5_cqe64*);
525 typedef struct sk_buff *
526 (*mlx5e_fp_skb_from_cqe_mpwrq)(struct mlx5e_rq *rq, struct mlx5e_mpw_info *wi,
527 u16 cqe_bcnt, u32 head_offset, u32 page_idx);
528 typedef struct sk_buff *
529 (*mlx5e_fp_skb_from_cqe)(struct mlx5e_rq *rq, struct mlx5_cqe64 *cqe,
530 struct mlx5e_wqe_frag_info *wi, u32 cqe_bcnt);
531 typedef bool (*mlx5e_fp_post_rx_wqes)(struct mlx5e_rq *rq);
532 typedef void (*mlx5e_fp_dealloc_wqe)(struct mlx5e_rq*, u16);
535 MLX5E_RQ_FLAG_XDP_XMIT = BIT(0),
538 struct mlx5e_rq_frag_info {
543 struct mlx5e_rq_frags_info {
544 struct mlx5e_rq_frag_info arr[MLX5E_MAX_RX_FRAGS];
554 struct mlx5_wq_cyc wq;
555 struct mlx5e_wqe_frag_info *frags;
556 struct mlx5e_dma_info *di;
557 struct mlx5e_rq_frags_info info;
558 mlx5e_fp_skb_from_cqe skb_from_cqe;
561 struct mlx5_wq_ll wq;
562 struct mlx5e_umr_wqe umr_wqe;
563 struct mlx5e_mpw_info *info;
564 mlx5e_fp_skb_from_cqe_mpwrq skb_from_cqe_mpwrq;
567 bool umr_in_progress;
572 u8 map_dir; /* dma map direction */
575 struct mlx5e_channel *channel;
577 struct net_device *netdev;
578 struct mlx5e_rq_stats *stats;
580 struct mlx5e_cq_decomp cqd;
581 struct mlx5e_page_cache page_cache;
582 struct hwtstamp_config *tstamp;
583 struct mlx5_clock *clock;
585 mlx5e_fp_handle_rx_cqe handle_rx_cqe;
586 mlx5e_fp_post_rx_wqes post_wqes;
587 mlx5e_fp_dealloc_wqe dealloc_wqe;
593 struct net_dim dim; /* Dynamic Interrupt Moderation */
596 struct bpf_prog *xdp_prog;
597 struct mlx5e_xdpsq xdpsq;
598 DECLARE_BITMAP(flags, 8);
599 struct page_pool *page_pool;
602 struct mlx5_wq_ctrl wq_ctrl;
606 struct mlx5_core_dev *mdev;
607 struct mlx5_core_mkey umr_mkey;
609 /* XDP read-mostly */
610 struct xdp_rxq_info xdp_rxq;
611 } ____cacheline_aligned_in_smp;
613 struct mlx5e_channel {
616 struct mlx5e_txqsq sq[MLX5E_MAX_NUM_TC];
617 struct mlx5e_icosq icosq; /* internal control operations */
619 struct napi_struct napi;
621 struct net_device *netdev;
626 struct mlx5e_xdpsq xdpsq;
628 /* data path - accessed per napi poll */
629 struct irq_desc *irq_desc;
630 struct mlx5e_ch_stats *stats;
633 struct mlx5e_priv *priv;
634 struct mlx5_core_dev *mdev;
635 struct hwtstamp_config *tstamp;
638 cpumask_var_t xps_cpumask;
641 struct mlx5e_channels {
642 struct mlx5e_channel **c;
644 struct mlx5e_params params;
647 struct mlx5e_channel_stats {
648 struct mlx5e_ch_stats ch;
649 struct mlx5e_sq_stats sq[MLX5E_MAX_NUM_TC];
650 struct mlx5e_rq_stats rq;
651 struct mlx5e_xdpsq_stats rq_xdpsq;
652 struct mlx5e_xdpsq_stats xdpsq;
653 } ____cacheline_aligned_in_smp;
657 MLX5E_STATE_DESTROYING,
658 MLX5E_STATE_XDP_TX_ENABLED,
668 struct mlx5e_rqt rqt;
669 struct list_head list;
677 struct mlx5e_rss_params {
678 u32 indirection_rqt[MLX5E_INDIR_RQT_SIZE];
679 u32 rx_hash_fields[MLX5E_NUM_INDIR_TIRS];
680 u8 toeplitz_hash_key[40];
684 struct mlx5e_modify_sq_param {
692 /* priv data path fields - start */
693 struct mlx5e_txqsq *txq2sq[MLX5E_MAX_NUM_CHANNELS * MLX5E_MAX_NUM_TC];
694 int channel_tc2txq[MLX5E_MAX_NUM_CHANNELS][MLX5E_MAX_NUM_TC];
695 #ifdef CONFIG_MLX5_CORE_EN_DCB
696 struct mlx5e_dcbx_dp dcbx_dp;
698 /* priv data path fields - end */
702 struct mutex state_lock; /* Protects Interface state */
703 struct mlx5e_rq drop_rq;
705 struct mlx5e_channels channels;
706 u32 tisn[MLX5E_MAX_NUM_TC];
707 struct mlx5e_rqt indir_rqt;
708 struct mlx5e_tir indir_tir[MLX5E_NUM_INDIR_TIRS];
709 struct mlx5e_tir inner_indir_tir[MLX5E_NUM_INDIR_TIRS];
710 struct mlx5e_tir direct_tir[MLX5E_MAX_NUM_CHANNELS];
711 struct mlx5e_rss_params rss_params;
712 u32 tx_rates[MLX5E_MAX_NUM_SQS];
714 struct mlx5e_flow_steering fs;
716 struct workqueue_struct *wq;
717 struct work_struct update_carrier_work;
718 struct work_struct set_rx_mode_work;
719 struct work_struct tx_timeout_work;
720 struct work_struct update_stats_work;
721 struct work_struct monitor_counters_work;
722 struct mlx5_nb monitor_counters_nb;
724 struct mlx5_core_dev *mdev;
725 struct net_device *netdev;
726 struct mlx5e_stats stats;
727 struct mlx5e_channel_stats channel_stats[MLX5E_MAX_NUM_CHANNELS];
729 struct hwtstamp_config tstamp;
731 u16 drop_rq_q_counter;
732 struct notifier_block events_nb;
734 #ifdef CONFIG_MLX5_CORE_EN_DCB
735 struct mlx5e_dcbx dcbx;
738 const struct mlx5e_profile *profile;
740 #ifdef CONFIG_MLX5_EN_IPSEC
741 struct mlx5e_ipsec *ipsec;
743 #ifdef CONFIG_MLX5_EN_TLS
744 struct mlx5e_tls *tls;
746 struct devlink_health_reporter *tx_reporter;
749 struct mlx5e_profile {
750 int (*init)(struct mlx5_core_dev *mdev,
751 struct net_device *netdev,
752 const struct mlx5e_profile *profile, void *ppriv);
753 void (*cleanup)(struct mlx5e_priv *priv);
754 int (*init_rx)(struct mlx5e_priv *priv);
755 void (*cleanup_rx)(struct mlx5e_priv *priv);
756 int (*init_tx)(struct mlx5e_priv *priv);
757 void (*cleanup_tx)(struct mlx5e_priv *priv);
758 void (*enable)(struct mlx5e_priv *priv);
759 void (*disable)(struct mlx5e_priv *priv);
760 void (*update_stats)(struct mlx5e_priv *priv);
761 void (*update_carrier)(struct mlx5e_priv *priv);
763 mlx5e_fp_handle_rx_cqe handle_rx_cqe;
764 mlx5e_fp_handle_rx_cqe handle_rx_cqe_mpwqe;
769 void mlx5e_build_ptys2ethtool_map(void);
771 u16 mlx5e_select_queue(struct net_device *dev, struct sk_buff *skb,
772 struct net_device *sb_dev,
773 select_queue_fallback_t fallback);
774 netdev_tx_t mlx5e_xmit(struct sk_buff *skb, struct net_device *dev);
775 netdev_tx_t mlx5e_sq_xmit(struct mlx5e_txqsq *sq, struct sk_buff *skb,
776 struct mlx5e_tx_wqe *wqe, u16 pi);
778 void mlx5e_completion_event(struct mlx5_core_cq *mcq);
779 void mlx5e_cq_error_event(struct mlx5_core_cq *mcq, enum mlx5_event event);
780 int mlx5e_napi_poll(struct napi_struct *napi, int budget);
781 bool mlx5e_poll_tx_cq(struct mlx5e_cq *cq, int napi_budget);
782 int mlx5e_poll_rx_cq(struct mlx5e_cq *cq, int budget);
783 void mlx5e_free_txqsq_descs(struct mlx5e_txqsq *sq);
785 bool mlx5e_check_fragmented_striding_rq_cap(struct mlx5_core_dev *mdev);
786 bool mlx5e_striding_rq_possible(struct mlx5_core_dev *mdev,
787 struct mlx5e_params *params);
789 void mlx5e_page_dma_unmap(struct mlx5e_rq *rq, struct mlx5e_dma_info *dma_info);
790 void mlx5e_page_release(struct mlx5e_rq *rq, struct mlx5e_dma_info *dma_info,
792 void mlx5e_handle_rx_cqe(struct mlx5e_rq *rq, struct mlx5_cqe64 *cqe);
793 void mlx5e_handle_rx_cqe_mpwrq(struct mlx5e_rq *rq, struct mlx5_cqe64 *cqe);
794 bool mlx5e_post_rx_wqes(struct mlx5e_rq *rq);
795 bool mlx5e_post_rx_mpwqes(struct mlx5e_rq *rq);
796 void mlx5e_dealloc_rx_wqe(struct mlx5e_rq *rq, u16 ix);
797 void mlx5e_dealloc_rx_mpwqe(struct mlx5e_rq *rq, u16 ix);
799 mlx5e_skb_from_cqe_mpwrq_linear(struct mlx5e_rq *rq, struct mlx5e_mpw_info *wi,
800 u16 cqe_bcnt, u32 head_offset, u32 page_idx);
802 mlx5e_skb_from_cqe_mpwrq_nonlinear(struct mlx5e_rq *rq, struct mlx5e_mpw_info *wi,
803 u16 cqe_bcnt, u32 head_offset, u32 page_idx);
805 mlx5e_skb_from_cqe_linear(struct mlx5e_rq *rq, struct mlx5_cqe64 *cqe,
806 struct mlx5e_wqe_frag_info *wi, u32 cqe_bcnt);
808 mlx5e_skb_from_cqe_nonlinear(struct mlx5e_rq *rq, struct mlx5_cqe64 *cqe,
809 struct mlx5e_wqe_frag_info *wi, u32 cqe_bcnt);
811 void mlx5e_update_stats(struct mlx5e_priv *priv);
812 void mlx5e_get_stats(struct net_device *dev, struct rtnl_link_stats64 *stats);
813 void mlx5e_fold_sw_stats64(struct mlx5e_priv *priv, struct rtnl_link_stats64 *s);
815 void mlx5e_init_l2_addr(struct mlx5e_priv *priv);
816 int mlx5e_self_test_num(struct mlx5e_priv *priv);
817 void mlx5e_self_test(struct net_device *ndev, struct ethtool_test *etest,
819 void mlx5e_set_rx_mode_work(struct work_struct *work);
821 int mlx5e_hwstamp_set(struct mlx5e_priv *priv, struct ifreq *ifr);
822 int mlx5e_hwstamp_get(struct mlx5e_priv *priv, struct ifreq *ifr);
823 int mlx5e_modify_rx_cqe_compression_locked(struct mlx5e_priv *priv, bool val);
825 int mlx5e_vlan_rx_add_vid(struct net_device *dev, __always_unused __be16 proto,
827 int mlx5e_vlan_rx_kill_vid(struct net_device *dev, __always_unused __be16 proto,
829 void mlx5e_timestamp_init(struct mlx5e_priv *priv);
831 struct mlx5e_redirect_rqt_param {
834 u32 rqn; /* Direct RQN (Non-RSS) */
837 struct mlx5e_channels *channels;
838 } rss; /* RSS data */
842 int mlx5e_redirect_rqt(struct mlx5e_priv *priv, u32 rqtn, int sz,
843 struct mlx5e_redirect_rqt_param rrp);
844 void mlx5e_build_indir_tir_ctx_hash(struct mlx5e_rss_params *rss_params,
845 const struct mlx5e_tirc_config *ttconfig,
846 void *tirc, bool inner);
847 void mlx5e_modify_tirs_hash(struct mlx5e_priv *priv, void *in, int inlen);
848 struct mlx5e_tirc_config mlx5e_tirc_get_default_config(enum mlx5e_traffic_types tt);
850 int mlx5e_open_locked(struct net_device *netdev);
851 int mlx5e_close_locked(struct net_device *netdev);
853 int mlx5e_open_channels(struct mlx5e_priv *priv,
854 struct mlx5e_channels *chs);
855 void mlx5e_close_channels(struct mlx5e_channels *chs);
857 /* Function pointer to be used to modify WH settings while
860 typedef int (*mlx5e_fp_hw_modify)(struct mlx5e_priv *priv);
861 int mlx5e_safe_switch_channels(struct mlx5e_priv *priv,
862 struct mlx5e_channels *new_chs,
863 mlx5e_fp_hw_modify hw_modify);
864 void mlx5e_activate_priv_channels(struct mlx5e_priv *priv);
865 void mlx5e_deactivate_priv_channels(struct mlx5e_priv *priv);
867 void mlx5e_build_default_indir_rqt(u32 *indirection_rqt, int len,
869 void mlx5e_set_tx_cq_mode_params(struct mlx5e_params *params,
871 void mlx5e_set_rx_cq_mode_params(struct mlx5e_params *params,
873 void mlx5e_set_rq_type(struct mlx5_core_dev *mdev, struct mlx5e_params *params);
874 void mlx5e_init_rq_type_params(struct mlx5_core_dev *mdev,
875 struct mlx5e_params *params);
877 int mlx5e_modify_sq(struct mlx5_core_dev *mdev, u32 sqn,
878 struct mlx5e_modify_sq_param *p);
879 void mlx5e_activate_txqsq(struct mlx5e_txqsq *sq);
880 void mlx5e_tx_disable_queue(struct netdev_queue *txq);
882 static inline bool mlx5e_tunnel_inner_ft_supported(struct mlx5_core_dev *mdev)
884 return (MLX5_CAP_ETH(mdev, tunnel_stateless_gre) &&
885 MLX5_CAP_FLOWTABLE_NIC_RX(mdev, ft_field_support.inner_ip_version));
888 static inline void mlx5e_sq_fetch_wqe(struct mlx5e_txqsq *sq,
889 struct mlx5e_tx_wqe **wqe,
892 struct mlx5_wq_cyc *wq = &sq->wq;
894 *pi = mlx5_wq_cyc_ctr2ix(wq, sq->pc);
895 *wqe = mlx5_wq_cyc_get_wqe(wq, *pi);
896 memset(*wqe, 0, sizeof(**wqe));
900 struct mlx5e_tx_wqe *mlx5e_post_nop(struct mlx5_wq_cyc *wq, u32 sqn, u16 *pc)
902 u16 pi = mlx5_wq_cyc_ctr2ix(wq, *pc);
903 struct mlx5e_tx_wqe *wqe = mlx5_wq_cyc_get_wqe(wq, pi);
904 struct mlx5_wqe_ctrl_seg *cseg = &wqe->ctrl;
906 memset(cseg, 0, sizeof(*cseg));
908 cseg->opmod_idx_opcode = cpu_to_be32((*pc << 8) | MLX5_OPCODE_NOP);
909 cseg->qpn_ds = cpu_to_be32((sqn << 8) | 0x01);
917 void mlx5e_notify_hw(struct mlx5_wq_cyc *wq, u16 pc,
918 void __iomem *uar_map,
919 struct mlx5_wqe_ctrl_seg *ctrl)
921 ctrl->fm_ce_se = MLX5_WQE_CTRL_CQ_UPDATE;
922 /* ensure wqe is visible to device before updating doorbell record */
925 *wq->db = cpu_to_be32(pc);
927 /* ensure doorbell record is visible to device before ringing the
932 mlx5_write64((__be32 *)ctrl, uar_map);
935 static inline void mlx5e_cq_arm(struct mlx5e_cq *cq)
937 struct mlx5_core_cq *mcq;
940 mlx5_cq_arm(mcq, MLX5_CQ_DB_REQ_NOT, mcq->uar->map, cq->wq.cc);
943 extern const struct ethtool_ops mlx5e_ethtool_ops;
944 #ifdef CONFIG_MLX5_CORE_EN_DCB
945 extern const struct dcbnl_rtnl_ops mlx5e_dcbnl_ops;
946 int mlx5e_dcbnl_ieee_setets_core(struct mlx5e_priv *priv, struct ieee_ets *ets);
947 void mlx5e_dcbnl_initialize(struct mlx5e_priv *priv);
948 void mlx5e_dcbnl_init_app(struct mlx5e_priv *priv);
949 void mlx5e_dcbnl_delete_app(struct mlx5e_priv *priv);
952 int mlx5e_create_tir(struct mlx5_core_dev *mdev,
953 struct mlx5e_tir *tir, u32 *in, int inlen);
954 void mlx5e_destroy_tir(struct mlx5_core_dev *mdev,
955 struct mlx5e_tir *tir);
956 int mlx5e_create_mdev_resources(struct mlx5_core_dev *mdev);
957 void mlx5e_destroy_mdev_resources(struct mlx5_core_dev *mdev);
958 int mlx5e_refresh_tirs(struct mlx5e_priv *priv, bool enable_uc_lb);
960 /* common netdev helpers */
961 void mlx5e_create_q_counters(struct mlx5e_priv *priv);
962 void mlx5e_destroy_q_counters(struct mlx5e_priv *priv);
963 int mlx5e_open_drop_rq(struct mlx5e_priv *priv,
964 struct mlx5e_rq *drop_rq);
965 void mlx5e_close_drop_rq(struct mlx5e_rq *drop_rq);
967 int mlx5e_create_indirect_rqt(struct mlx5e_priv *priv);
969 int mlx5e_create_indirect_tirs(struct mlx5e_priv *priv, bool inner_ttc);
970 void mlx5e_destroy_indirect_tirs(struct mlx5e_priv *priv, bool inner_ttc);
972 int mlx5e_create_direct_rqts(struct mlx5e_priv *priv);
973 void mlx5e_destroy_direct_rqts(struct mlx5e_priv *priv);
974 int mlx5e_create_direct_tirs(struct mlx5e_priv *priv);
975 void mlx5e_destroy_direct_tirs(struct mlx5e_priv *priv);
976 void mlx5e_destroy_rqt(struct mlx5e_priv *priv, struct mlx5e_rqt *rqt);
978 int mlx5e_create_tis(struct mlx5_core_dev *mdev, int tc,
979 u32 underlay_qpn, u32 *tisn);
980 void mlx5e_destroy_tis(struct mlx5_core_dev *mdev, u32 tisn);
982 int mlx5e_create_tises(struct mlx5e_priv *priv);
983 void mlx5e_update_carrier(struct mlx5e_priv *priv);
984 int mlx5e_close(struct net_device *netdev);
985 int mlx5e_open(struct net_device *netdev);
986 void mlx5e_update_ndo_stats(struct mlx5e_priv *priv);
988 void mlx5e_queue_update_stats(struct mlx5e_priv *priv);
989 int mlx5e_bits_invert(unsigned long a, int size);
991 typedef int (*change_hw_mtu_cb)(struct mlx5e_priv *priv);
992 int mlx5e_set_dev_port_mtu(struct mlx5e_priv *priv);
993 int mlx5e_change_mtu(struct net_device *netdev, int new_mtu,
994 change_hw_mtu_cb set_mtu_cb);
996 /* ethtool helpers */
997 void mlx5e_ethtool_get_drvinfo(struct mlx5e_priv *priv,
998 struct ethtool_drvinfo *drvinfo);
999 void mlx5e_ethtool_get_strings(struct mlx5e_priv *priv,
1000 uint32_t stringset, uint8_t *data);
1001 int mlx5e_ethtool_get_sset_count(struct mlx5e_priv *priv, int sset);
1002 void mlx5e_ethtool_get_ethtool_stats(struct mlx5e_priv *priv,
1003 struct ethtool_stats *stats, u64 *data);
1004 void mlx5e_ethtool_get_ringparam(struct mlx5e_priv *priv,
1005 struct ethtool_ringparam *param);
1006 int mlx5e_ethtool_set_ringparam(struct mlx5e_priv *priv,
1007 struct ethtool_ringparam *param);
1008 void mlx5e_ethtool_get_channels(struct mlx5e_priv *priv,
1009 struct ethtool_channels *ch);
1010 int mlx5e_ethtool_set_channels(struct mlx5e_priv *priv,
1011 struct ethtool_channels *ch);
1012 int mlx5e_ethtool_get_coalesce(struct mlx5e_priv *priv,
1013 struct ethtool_coalesce *coal);
1014 int mlx5e_ethtool_set_coalesce(struct mlx5e_priv *priv,
1015 struct ethtool_coalesce *coal);
1016 int mlx5e_ethtool_get_link_ksettings(struct mlx5e_priv *priv,
1017 struct ethtool_link_ksettings *link_ksettings);
1018 int mlx5e_ethtool_set_link_ksettings(struct mlx5e_priv *priv,
1019 const struct ethtool_link_ksettings *link_ksettings);
1020 u32 mlx5e_ethtool_get_rxfh_key_size(struct mlx5e_priv *priv);
1021 u32 mlx5e_ethtool_get_rxfh_indir_size(struct mlx5e_priv *priv);
1022 int mlx5e_ethtool_get_ts_info(struct mlx5e_priv *priv,
1023 struct ethtool_ts_info *info);
1024 int mlx5e_ethtool_flash_device(struct mlx5e_priv *priv,
1025 struct ethtool_flash *flash);
1026 void mlx5e_ethtool_get_pauseparam(struct mlx5e_priv *priv,
1027 struct ethtool_pauseparam *pauseparam);
1028 int mlx5e_ethtool_set_pauseparam(struct mlx5e_priv *priv,
1029 struct ethtool_pauseparam *pauseparam);
1031 /* mlx5e generic netdev management API */
1032 int mlx5e_netdev_init(struct net_device *netdev,
1033 struct mlx5e_priv *priv,
1034 struct mlx5_core_dev *mdev,
1035 const struct mlx5e_profile *profile,
1037 void mlx5e_netdev_cleanup(struct net_device *netdev, struct mlx5e_priv *priv);
1039 mlx5e_create_netdev(struct mlx5_core_dev *mdev, const struct mlx5e_profile *profile,
1040 int nch, void *ppriv);
1041 int mlx5e_attach_netdev(struct mlx5e_priv *priv);
1042 void mlx5e_detach_netdev(struct mlx5e_priv *priv);
1043 void mlx5e_destroy_netdev(struct mlx5e_priv *priv);
1044 void mlx5e_build_nic_params(struct mlx5_core_dev *mdev,
1045 struct mlx5e_rss_params *rss_params,
1046 struct mlx5e_params *params,
1047 u16 max_channels, u16 mtu);
1048 void mlx5e_build_rq_params(struct mlx5_core_dev *mdev,
1049 struct mlx5e_params *params);
1050 void mlx5e_build_rss_params(struct mlx5e_rss_params *rss_params,
1052 u8 mlx5e_params_calculate_tx_min_inline(struct mlx5_core_dev *mdev);
1053 void mlx5e_rx_dim_work(struct work_struct *work);
1054 void mlx5e_tx_dim_work(struct work_struct *work);
1056 void mlx5e_add_vxlan_port(struct net_device *netdev, struct udp_tunnel_info *ti);
1057 void mlx5e_del_vxlan_port(struct net_device *netdev, struct udp_tunnel_info *ti);
1058 netdev_features_t mlx5e_features_check(struct sk_buff *skb,
1059 struct net_device *netdev,
1060 netdev_features_t features);
1061 #ifdef CONFIG_MLX5_ESWITCH
1062 int mlx5e_set_vf_mac(struct net_device *dev, int vf, u8 *mac);
1063 int mlx5e_set_vf_rate(struct net_device *dev, int vf, int min_tx_rate, int max_tx_rate);
1064 int mlx5e_get_vf_config(struct net_device *dev, int vf, struct ifla_vf_info *ivi);
1065 int mlx5e_get_vf_stats(struct net_device *dev, int vf, struct ifla_vf_stats *vf_stats);
1067 #endif /* __MLX5_EN_H__ */