2 * Copyright (c) 2015-2016, Mellanox Technologies. All rights reserved.
4 * This software is available to you under a choice of one of two
5 * licenses. You may choose to be licensed under the terms of the GNU
6 * General Public License (GPL) Version 2, available from the file
7 * COPYING in the main directory of this source tree, or the
8 * OpenIB.org BSD license below:
10 * Redistribution and use in source and binary forms, with or
11 * without modification, are permitted provided that the following
14 * - Redistributions of source code must retain the above
15 * copyright notice, this list of conditions and the following
18 * - Redistributions in binary form must reproduce the above
19 * copyright notice, this list of conditions and the following
20 * disclaimer in the documentation and/or other materials
21 * provided with the distribution.
23 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
24 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
25 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
26 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
27 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
28 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
29 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
35 #include <linux/if_vlan.h>
36 #include <linux/etherdevice.h>
37 #include <linux/timecounter.h>
38 #include <linux/net_tstamp.h>
39 #include <linux/crash_dump.h>
40 #include <linux/mlx5/driver.h>
41 #include <linux/mlx5/qp.h>
42 #include <linux/mlx5/cq.h>
43 #include <linux/mlx5/port.h>
44 #include <linux/mlx5/vport.h>
45 #include <linux/mlx5/transobj.h>
46 #include <linux/mlx5/fs.h>
47 #include <linux/rhashtable.h>
48 #include <net/udp_tunnel.h>
49 #include <net/switchdev.h>
51 #include <linux/dim.h>
52 #include <linux/bits.h>
54 #include "mlx5_core.h"
59 #include "lib/hv_vhca.h"
60 #include "lib/clock.h"
62 extern const struct net_device_ops mlx5e_netdev_ops;
65 #define MLX5E_METADATA_ETHER_TYPE (0x8CE4)
66 #define MLX5E_METADATA_ETHER_LEN 8
68 #define MLX5_SET_CFG(p, f, v) MLX5_SET(create_flow_group_in, p, f, v)
70 #define MLX5E_ETH_HARD_MTU (ETH_HLEN + VLAN_HLEN + ETH_FCS_LEN)
72 #define MLX5E_HW2SW_MTU(params, hwmtu) ((hwmtu) - ((params)->hard_mtu))
73 #define MLX5E_SW2HW_MTU(params, swmtu) ((swmtu) + ((params)->hard_mtu))
75 #define MLX5E_MAX_NUM_TC 8
77 #define MLX5_RX_HEADROOM NET_SKB_PAD
78 #define MLX5_SKB_FRAG_SZ(len) (SKB_DATA_ALIGN(len) + \
79 SKB_DATA_ALIGN(sizeof(struct skb_shared_info)))
81 #define MLX5E_RX_MAX_HEAD (256)
83 #define MLX5_MPWRQ_MIN_LOG_STRIDE_SZ(mdev) \
84 (6 + MLX5_CAP_GEN(mdev, cache_line_128byte)) /* HW restriction */
85 #define MLX5_MPWRQ_LOG_STRIDE_SZ(mdev, req) \
86 max_t(u32, MLX5_MPWRQ_MIN_LOG_STRIDE_SZ(mdev), req)
87 #define MLX5_MPWRQ_DEF_LOG_STRIDE_SZ(mdev) \
88 MLX5_MPWRQ_LOG_STRIDE_SZ(mdev, order_base_2(MLX5E_RX_MAX_HEAD))
90 #define MLX5_MPWRQ_LOG_WQE_SZ 18
91 #define MLX5_MPWRQ_WQE_PAGE_ORDER (MLX5_MPWRQ_LOG_WQE_SZ - PAGE_SHIFT > 0 ? \
92 MLX5_MPWRQ_LOG_WQE_SZ - PAGE_SHIFT : 0)
93 #define MLX5_MPWRQ_PAGES_PER_WQE BIT(MLX5_MPWRQ_WQE_PAGE_ORDER)
95 #define MLX5_ALIGN_MTTS(mtts) (ALIGN(mtts, 8))
96 #define MLX5_ALIGNED_MTTS_OCTW(mtts) ((mtts) / 2)
97 #define MLX5_MTT_OCTW(mtts) (MLX5_ALIGNED_MTTS_OCTW(MLX5_ALIGN_MTTS(mtts)))
98 /* Add another page to MLX5E_REQUIRED_WQE_MTTS as a buffer between
99 * WQEs, This page will absorb write overflow by the hardware, when
100 * receiving packets larger than MTU. These oversize packets are
101 * dropped by the driver at a later stage.
103 #define MLX5E_REQUIRED_WQE_MTTS (MLX5_ALIGN_MTTS(MLX5_MPWRQ_PAGES_PER_WQE + 1))
104 #define MLX5E_REQUIRED_MTTS(wqes) (wqes * MLX5E_REQUIRED_WQE_MTTS)
105 #define MLX5E_MAX_RQ_NUM_MTTS \
106 ((1 << 16) * 2) /* So that MLX5_MTT_OCTW(num_mtts) fits into u16 */
107 #define MLX5E_ORDER2_MAX_PACKET_MTU (order_base_2(10 * 1024))
108 #define MLX5E_PARAMS_MAXIMUM_LOG_RQ_SIZE_MPW \
109 (ilog2(MLX5E_MAX_RQ_NUM_MTTS / MLX5E_REQUIRED_WQE_MTTS))
110 #define MLX5E_LOG_MAX_RQ_NUM_PACKETS_MPW \
111 (MLX5E_PARAMS_MAXIMUM_LOG_RQ_SIZE_MPW + \
112 (MLX5_MPWRQ_LOG_WQE_SZ - MLX5E_ORDER2_MAX_PACKET_MTU))
114 #define MLX5E_MIN_SKB_FRAG_SZ (MLX5_SKB_FRAG_SZ(MLX5_RX_HEADROOM))
115 #define MLX5E_LOG_MAX_RX_WQE_BULK \
116 (ilog2(PAGE_SIZE / roundup_pow_of_two(MLX5E_MIN_SKB_FRAG_SZ)))
118 #define MLX5E_PARAMS_MINIMUM_LOG_SQ_SIZE 0x6
119 #define MLX5E_PARAMS_DEFAULT_LOG_SQ_SIZE 0xa
120 #define MLX5E_PARAMS_MAXIMUM_LOG_SQ_SIZE 0xd
122 #define MLX5E_PARAMS_MINIMUM_LOG_RQ_SIZE (1 + MLX5E_LOG_MAX_RX_WQE_BULK)
123 #define MLX5E_PARAMS_DEFAULT_LOG_RQ_SIZE 0xa
124 #define MLX5E_PARAMS_MAXIMUM_LOG_RQ_SIZE min_t(u8, 0xd, \
125 MLX5E_LOG_MAX_RQ_NUM_PACKETS_MPW)
127 #define MLX5E_PARAMS_MINIMUM_LOG_RQ_SIZE_MPW 0x2
129 #define MLX5E_PARAMS_DEFAULT_LRO_WQE_SZ (64 * 1024)
130 #define MLX5E_DEFAULT_LRO_TIMEOUT 32
131 #define MLX5E_LRO_TIMEOUT_ARR_SIZE 4
133 #define MLX5E_PARAMS_DEFAULT_RX_CQ_MODERATION_USEC 0x10
134 #define MLX5E_PARAMS_DEFAULT_RX_CQ_MODERATION_USEC_FROM_CQE 0x3
135 #define MLX5E_PARAMS_DEFAULT_RX_CQ_MODERATION_PKTS 0x20
136 #define MLX5E_PARAMS_DEFAULT_TX_CQ_MODERATION_USEC 0x10
137 #define MLX5E_PARAMS_DEFAULT_TX_CQ_MODERATION_USEC_FROM_CQE 0x10
138 #define MLX5E_PARAMS_DEFAULT_TX_CQ_MODERATION_PKTS 0x20
139 #define MLX5E_PARAMS_DEFAULT_MIN_RX_WQES 0x80
140 #define MLX5E_PARAMS_DEFAULT_MIN_RX_WQES_MPW 0x2
142 #define MLX5E_LOG_INDIR_RQT_SIZE 0x8
143 #define MLX5E_INDIR_RQT_SIZE BIT(MLX5E_LOG_INDIR_RQT_SIZE)
144 #define MLX5E_MIN_NUM_CHANNELS 0x1
145 #define MLX5E_MAX_NUM_CHANNELS (MLX5E_INDIR_RQT_SIZE / 2)
146 #define MLX5E_MAX_NUM_SQS (MLX5E_MAX_NUM_CHANNELS * MLX5E_MAX_NUM_TC)
147 #define MLX5E_TX_CQ_POLL_BUDGET 128
148 #define MLX5E_TX_XSK_POLL_BUDGET 64
149 #define MLX5E_SQ_RECOVER_MIN_INTERVAL 500 /* msecs */
151 #define MLX5E_UMR_WQE_INLINE_SZ \
152 (sizeof(struct mlx5e_umr_wqe) + \
153 ALIGN(MLX5_MPWRQ_PAGES_PER_WQE * sizeof(struct mlx5_mtt), \
154 MLX5_UMR_MTT_ALIGNMENT))
155 #define MLX5E_UMR_WQEBBS \
156 (DIV_ROUND_UP(MLX5E_UMR_WQE_INLINE_SZ, MLX5_SEND_WQE_BB))
158 #define MLX5E_MSG_LEVEL NETIF_MSG_LINK
160 #define mlx5e_dbg(mlevel, priv, format, ...) \
162 if (NETIF_MSG_##mlevel & (priv)->msglevel) \
163 netdev_warn(priv->netdev, format, \
167 #define mlx5e_state_dereference(priv, p) \
168 rcu_dereference_protected((p), lockdep_is_held(&(priv)->state_lock))
170 enum mlx5e_rq_group {
171 MLX5E_RQ_GROUP_REGULAR,
173 #define MLX5E_NUM_RQ_GROUPS(g) (1 + MLX5E_RQ_GROUP_##g)
176 static inline u8 mlx5e_get_num_lag_ports(struct mlx5_core_dev *mdev)
178 if (mlx5_lag_is_lacp_owner(mdev))
181 return clamp_t(u8, MLX5_CAP_GEN(mdev, num_lag_ports), 1, MLX5_MAX_PORTS);
184 static inline u16 mlx5_min_rx_wqes(int wq_type, u32 wq_size)
187 case MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ:
188 return min_t(u16, MLX5E_PARAMS_DEFAULT_MIN_RX_WQES_MPW,
191 return min_t(u16, MLX5E_PARAMS_DEFAULT_MIN_RX_WQES,
196 /* Use this function to get max num channels (rxqs/txqs) only to create netdev */
197 static inline int mlx5e_get_max_num_channels(struct mlx5_core_dev *mdev)
199 return is_kdump_kernel() ?
200 MLX5E_MIN_NUM_CHANNELS :
201 min_t(int, mlx5_comp_vectors_count(mdev), MLX5E_MAX_NUM_CHANNELS);
204 struct mlx5e_tx_wqe {
205 struct mlx5_wqe_ctrl_seg ctrl;
206 struct mlx5_wqe_eth_seg eth;
207 struct mlx5_wqe_data_seg data[0];
210 struct mlx5e_rx_wqe_ll {
211 struct mlx5_wqe_srq_next_seg next;
212 struct mlx5_wqe_data_seg data[];
215 struct mlx5e_rx_wqe_cyc {
216 struct mlx5_wqe_data_seg data[0];
219 struct mlx5e_umr_wqe {
220 struct mlx5_wqe_ctrl_seg ctrl;
221 struct mlx5_wqe_umr_ctrl_seg uctrl;
222 struct mlx5_mkey_seg mkc;
223 struct mlx5_mtt inline_mtts[0];
226 extern const char mlx5e_self_tests[][ETH_GSTRING_LEN];
228 enum mlx5e_priv_flag {
229 MLX5E_PFLAG_RX_CQE_BASED_MODER,
230 MLX5E_PFLAG_TX_CQE_BASED_MODER,
231 MLX5E_PFLAG_RX_CQE_COMPRESS,
232 MLX5E_PFLAG_RX_STRIDING_RQ,
233 MLX5E_PFLAG_RX_NO_CSUM_COMPLETE,
234 MLX5E_PFLAG_XDP_TX_MPWQE,
235 MLX5E_PFLAG_SKB_TX_MPWQE,
236 MLX5E_PFLAG_TX_PORT_TS,
237 MLX5E_NUM_PFLAGS, /* Keep last */
240 #define MLX5E_SET_PFLAG(params, pflag, enable) \
243 (params)->pflags |= BIT(pflag); \
245 (params)->pflags &= ~(BIT(pflag)); \
248 #define MLX5E_GET_PFLAG(params, pflag) (!!((params)->pflags & (BIT(pflag))))
250 struct mlx5e_params {
253 u8 log_rq_mtu_frames;
256 bool rx_cqe_compress_def;
257 bool tunneled_offload_en;
258 struct dim_cq_moder rx_cq_moderation;
259 struct dim_cq_moder tx_cq_moderation;
261 u8 tx_min_inline_mode;
262 bool vlan_strip_disable;
268 struct bpf_prog *xdp_prog;
269 struct mlx5e_xsk *xsk;
275 MLX5E_RQ_STATE_ENABLED,
276 MLX5E_RQ_STATE_RECOVERING,
278 MLX5E_RQ_STATE_NO_CSUM_COMPLETE,
279 MLX5E_RQ_STATE_CSUM_FULL, /* cqe_csum_full hw bit is set */
280 MLX5E_RQ_STATE_FPGA_TLS, /* FPGA TLS enabled */
281 MLX5E_RQ_STATE_MINI_CQE_HW_STRIDX /* set when mini_cqe_resp_stride_index cap is used */
285 /* data path - accessed per cqe */
288 /* data path - accessed per napi poll */
290 struct napi_struct *napi;
291 struct mlx5_core_cq mcq;
292 struct mlx5e_ch_stats *ch_stats;
295 struct net_device *netdev;
296 struct mlx5_core_dev *mdev;
297 struct mlx5e_priv *priv;
298 struct mlx5_wq_ctrl wq_ctrl;
299 } ____cacheline_aligned_in_smp;
301 struct mlx5e_cq_decomp {
302 /* cqe decompression */
303 struct mlx5_cqe64 title;
304 struct mlx5_mini_cqe8 mini_arr[MLX5_MINI_CQE_ARRAY_SIZE];
308 } ____cacheline_aligned_in_smp;
310 enum mlx5e_dma_map_type {
311 MLX5E_DMA_MAP_SINGLE,
315 struct mlx5e_sq_dma {
318 enum mlx5e_dma_map_type type;
322 MLX5E_SQ_STATE_ENABLED,
323 MLX5E_SQ_STATE_MPWQE,
324 MLX5E_SQ_STATE_RECOVERING,
325 MLX5E_SQ_STATE_IPSEC,
328 MLX5E_SQ_STATE_VLAN_NEED_L2_INLINE,
329 MLX5E_SQ_STATE_PENDING_XSK_TX,
332 struct mlx5e_tx_mpwqe {
333 /* Current MPWQE session */
334 struct mlx5e_tx_wqe *wqe;
341 struct mlx5e_skb_fifo {
342 struct sk_buff **fifo;
353 /* dirtied @completion */
357 struct dim dim; /* Adaptive Moderation */
360 u16 pc ____cacheline_aligned_in_smp;
363 struct mlx5e_tx_mpwqe mpwqe;
368 struct mlx5_wq_cyc wq;
370 struct mlx5e_sq_stats *stats;
372 struct mlx5e_sq_dma *dma_fifo;
373 struct mlx5e_skb_fifo skb_fifo;
374 struct mlx5e_tx_wqe_info *wqe_info;
376 void __iomem *uar_map;
377 struct netdev_queue *txq;
385 struct hwtstamp_config *tstamp;
386 struct mlx5_clock *clock;
387 struct net_device *netdev;
388 struct mlx5_core_dev *mdev;
389 struct mlx5e_priv *priv;
392 struct mlx5_wq_ctrl wq_ctrl;
396 struct work_struct recover_work;
397 struct mlx5e_ptpsq *ptpsq;
398 cqe_ts_to_ns ptp_cyc2time;
399 } ____cacheline_aligned_in_smp;
401 struct mlx5e_dma_info {
405 struct xdp_buff *xsk;
409 /* XDP packets can be transmitted in different ways. On completion, we need to
410 * distinguish between them to clean up things in a proper way.
412 enum mlx5e_xdp_xmit_mode {
413 /* An xdp_frame was transmitted due to either XDP_REDIRECT from another
414 * device or XDP_TX from an XSK RQ. The frame has to be unmapped and
417 MLX5E_XDP_XMIT_MODE_FRAME,
419 /* The xdp_frame was created in place as a result of XDP_TX from a
420 * regular RQ. No DMA remapping happened, and the page belongs to us.
422 MLX5E_XDP_XMIT_MODE_PAGE,
424 /* No xdp_frame was created at all, the transmit happened from a UMEM
425 * page. The UMEM Completion Ring producer pointer has to be increased.
427 MLX5E_XDP_XMIT_MODE_XSK,
430 struct mlx5e_xdp_info {
431 enum mlx5e_xdp_xmit_mode mode;
434 struct xdp_frame *xdpf;
439 struct mlx5e_dma_info di;
444 struct mlx5e_xmit_data {
450 struct mlx5e_xdp_info_fifo {
451 struct mlx5e_xdp_info *xi;
458 typedef int (*mlx5e_fp_xmit_xdp_frame_check)(struct mlx5e_xdpsq *);
459 typedef bool (*mlx5e_fp_xmit_xdp_frame)(struct mlx5e_xdpsq *,
460 struct mlx5e_xmit_data *,
461 struct mlx5e_xdp_info *,
467 /* dirtied @completion */
472 u32 xdpi_fifo_pc ____cacheline_aligned_in_smp;
474 struct mlx5_wqe_ctrl_seg *doorbell_cseg;
475 struct mlx5e_tx_mpwqe mpwqe;
480 struct xsk_buff_pool *xsk_pool;
481 struct mlx5_wq_cyc wq;
482 struct mlx5e_xdpsq_stats *stats;
483 mlx5e_fp_xmit_xdp_frame_check xmit_xdp_frame_check;
484 mlx5e_fp_xmit_xdp_frame xmit_xdp_frame;
486 struct mlx5e_xdp_wqe_info *wqe_info;
487 struct mlx5e_xdp_info_fifo xdpi_fifo;
489 void __iomem *uar_map;
498 struct mlx5_wq_ctrl wq_ctrl;
499 struct mlx5e_channel *channel;
500 } ____cacheline_aligned_in_smp;
507 struct mlx5_wqe_ctrl_seg *doorbell_cseg;
510 /* write@xmit, read@completion */
512 struct mlx5e_icosq_wqe_info *wqe_info;
516 struct mlx5_wq_cyc wq;
517 void __iomem *uar_map;
522 struct mlx5_wq_ctrl wq_ctrl;
523 struct mlx5e_channel *channel;
525 struct work_struct recover_work;
526 } ____cacheline_aligned_in_smp;
528 struct mlx5e_wqe_frag_info {
529 struct mlx5e_dma_info *di;
534 struct mlx5e_umr_dma_info {
535 struct mlx5e_dma_info dma_info[MLX5_MPWRQ_PAGES_PER_WQE];
538 struct mlx5e_mpw_info {
539 struct mlx5e_umr_dma_info umr;
540 u16 consumed_strides;
541 DECLARE_BITMAP(xdp_xmit_bitmap, MLX5_MPWRQ_PAGES_PER_WQE);
544 #define MLX5E_MAX_RX_FRAGS 4
546 /* a single cache unit is capable to serve one napi call (for non-striding rq)
547 * or a MPWQE (for striding rq).
549 #define MLX5E_CACHE_UNIT (MLX5_MPWRQ_PAGES_PER_WQE > NAPI_POLL_WEIGHT ? \
550 MLX5_MPWRQ_PAGES_PER_WQE : NAPI_POLL_WEIGHT)
551 #define MLX5E_CACHE_SIZE (4 * roundup_pow_of_two(MLX5E_CACHE_UNIT))
552 struct mlx5e_page_cache {
555 struct mlx5e_dma_info page_cache[MLX5E_CACHE_SIZE];
559 typedef void (*mlx5e_fp_handle_rx_cqe)(struct mlx5e_rq*, struct mlx5_cqe64*);
560 typedef struct sk_buff *
561 (*mlx5e_fp_skb_from_cqe_mpwrq)(struct mlx5e_rq *rq, struct mlx5e_mpw_info *wi,
562 u16 cqe_bcnt, u32 head_offset, u32 page_idx);
563 typedef struct sk_buff *
564 (*mlx5e_fp_skb_from_cqe)(struct mlx5e_rq *rq, struct mlx5_cqe64 *cqe,
565 struct mlx5e_wqe_frag_info *wi, u32 cqe_bcnt);
566 typedef bool (*mlx5e_fp_post_rx_wqes)(struct mlx5e_rq *rq);
567 typedef void (*mlx5e_fp_dealloc_wqe)(struct mlx5e_rq*, u16);
569 int mlx5e_rq_set_handlers(struct mlx5e_rq *rq, struct mlx5e_params *params, bool xsk);
570 void mlx5e_rq_set_trap_handlers(struct mlx5e_rq *rq, struct mlx5e_params *params);
573 MLX5E_RQ_FLAG_XDP_XMIT,
574 MLX5E_RQ_FLAG_XDP_REDIRECT,
577 struct mlx5e_rq_frag_info {
582 struct mlx5e_rq_frags_info {
583 struct mlx5e_rq_frag_info arr[MLX5E_MAX_RX_FRAGS];
593 struct mlx5_wq_cyc wq;
594 struct mlx5e_wqe_frag_info *frags;
595 struct mlx5e_dma_info *di;
596 struct mlx5e_rq_frags_info info;
597 mlx5e_fp_skb_from_cqe skb_from_cqe;
600 struct mlx5_wq_ll wq;
601 struct mlx5e_umr_wqe umr_wqe;
602 struct mlx5e_mpw_info *info;
603 mlx5e_fp_skb_from_cqe_mpwrq skb_from_cqe_mpwrq;
615 u8 map_dir; /* dma map direction */
619 struct net_device *netdev;
620 struct mlx5e_rq_stats *stats;
622 struct mlx5e_cq_decomp cqd;
623 struct mlx5e_page_cache page_cache;
624 struct hwtstamp_config *tstamp;
625 struct mlx5_clock *clock;
626 struct mlx5e_icosq *icosq;
627 struct mlx5e_priv *priv;
629 mlx5e_fp_handle_rx_cqe handle_rx_cqe;
630 mlx5e_fp_post_rx_wqes post_wqes;
631 mlx5e_fp_dealloc_wqe dealloc_wqe;
637 struct dim dim; /* Dynamic Interrupt Moderation */
640 struct bpf_prog __rcu *xdp_prog;
641 struct mlx5e_xdpsq *xdpsq;
642 DECLARE_BITMAP(flags, 8);
643 struct page_pool *page_pool;
645 /* AF_XDP zero-copy */
646 struct xsk_buff_pool *xsk_pool;
648 struct work_struct recover_work;
651 struct mlx5_wq_ctrl wq_ctrl;
655 struct mlx5_core_dev *mdev;
656 struct mlx5_core_mkey umr_mkey;
657 struct mlx5e_dma_info wqe_overflow;
659 /* XDP read-mostly */
660 struct xdp_rxq_info xdp_rxq;
661 cqe_ts_to_ns ptp_cyc2time;
662 } ____cacheline_aligned_in_smp;
664 enum mlx5e_channel_state {
665 MLX5E_CHANNEL_STATE_XSK,
666 MLX5E_CHANNEL_NUM_STATES
669 struct mlx5e_channel {
672 struct mlx5e_xdpsq rq_xdpsq;
673 struct mlx5e_txqsq sq[MLX5E_MAX_NUM_TC];
674 struct mlx5e_icosq icosq; /* internal control operations */
675 struct mlx5e_txqsq __rcu * __rcu *qos_sqs;
677 struct napi_struct napi;
679 struct net_device *netdev;
686 struct mlx5e_xdpsq xdpsq;
688 /* AF_XDP zero-copy */
689 struct mlx5e_rq xskrq;
690 struct mlx5e_xdpsq xsksq;
693 struct mlx5e_icosq async_icosq;
694 /* async_icosq can be accessed from any CPU - the spinlock protects it. */
695 spinlock_t async_icosq_lock;
697 /* data path - accessed per napi poll */
698 const struct cpumask *aff_mask;
699 struct mlx5e_ch_stats *stats;
702 struct mlx5e_priv *priv;
703 struct mlx5_core_dev *mdev;
704 struct hwtstamp_config *tstamp;
705 DECLARE_BITMAP(state, MLX5E_CHANNEL_NUM_STATES);
712 struct mlx5e_channels {
713 struct mlx5e_channel **c;
714 struct mlx5e_ptp *ptp;
716 struct mlx5e_params params;
719 struct mlx5e_channel_stats {
720 struct mlx5e_ch_stats ch;
721 struct mlx5e_sq_stats sq[MLX5E_MAX_NUM_TC];
722 struct mlx5e_rq_stats rq;
723 struct mlx5e_rq_stats xskrq;
724 struct mlx5e_xdpsq_stats rq_xdpsq;
725 struct mlx5e_xdpsq_stats xdpsq;
726 struct mlx5e_xdpsq_stats xsksq;
727 } ____cacheline_aligned_in_smp;
729 struct mlx5e_ptp_stats {
730 struct mlx5e_ch_stats ch;
731 struct mlx5e_sq_stats sq[MLX5E_MAX_NUM_TC];
732 struct mlx5e_ptp_cq_stats cq[MLX5E_MAX_NUM_TC];
733 struct mlx5e_rq_stats rq;
734 } ____cacheline_aligned_in_smp;
738 MLX5E_STATE_DESTROYING,
739 MLX5E_STATE_XDP_TX_ENABLED,
740 MLX5E_STATE_XDP_ACTIVE,
750 struct mlx5e_rqt rqt;
751 struct list_head list;
759 struct mlx5e_rss_params {
760 u32 indirection_rqt[MLX5E_INDIR_RQT_SIZE];
761 u32 rx_hash_fields[MLX5E_NUM_INDIR_TIRS];
762 u8 toeplitz_hash_key[40];
766 struct mlx5e_modify_sq_param {
772 u16 qos_queue_group_id;
775 #if IS_ENABLED(CONFIG_PCI_HYPERV_INTERFACE)
776 struct mlx5e_hv_vhca_stats_agent {
777 struct mlx5_hv_vhca_agent *agent;
778 struct delayed_work work;
785 /* XSK buffer pools are stored separately from channels,
786 * because we don't want to lose them when channels are
787 * recreated. The kernel also stores buffer pool, but it doesn't
788 * distinguish between zero-copy and non-zero-copy UMEMs, so
789 * rely on our mechanism.
791 struct xsk_buff_pool **pools;
796 /* Temporary storage for variables that are allocated when struct mlx5e_priv is
797 * initialized, and used where we can't allocate them because that functions
798 * must not fail. Use with care and make sure the same variable is not used
799 * simultaneously by multiple users.
801 struct mlx5e_scratchpad {
802 cpumask_var_t cpumask;
806 DECLARE_HASHTABLE(qos_tc2node, order_base_2(MLX5E_QOS_MAX_LEAF_NODES));
807 DECLARE_BITMAP(qos_used_qids, MLX5E_QOS_MAX_LEAF_NODES);
808 struct mlx5e_sq_stats **qos_sq_stats;
817 /* priv data path fields - start */
818 /* +1 for port ptp ts */
819 struct mlx5e_txqsq *txq2sq[(MLX5E_MAX_NUM_CHANNELS + 1) * MLX5E_MAX_NUM_TC +
820 MLX5E_QOS_MAX_LEAF_NODES];
821 int channel_tc2realtxq[MLX5E_MAX_NUM_CHANNELS][MLX5E_MAX_NUM_TC];
822 int port_ptp_tc2realtxq[MLX5E_MAX_NUM_TC];
823 #ifdef CONFIG_MLX5_CORE_EN_DCB
824 struct mlx5e_dcbx_dp dcbx_dp;
826 /* priv data path fields - end */
830 struct mutex state_lock; /* Protects Interface state */
831 struct mlx5e_rq drop_rq;
833 struct mlx5e_channels channels;
834 u32 tisn[MLX5_MAX_PORTS][MLX5E_MAX_NUM_TC];
835 struct mlx5e_rqt indir_rqt;
836 struct mlx5e_tir indir_tir[MLX5E_NUM_INDIR_TIRS];
837 struct mlx5e_tir inner_indir_tir[MLX5E_NUM_INDIR_TIRS];
838 struct mlx5e_tir direct_tir[MLX5E_MAX_NUM_CHANNELS];
839 struct mlx5e_tir xsk_tir[MLX5E_MAX_NUM_CHANNELS];
840 struct mlx5e_rss_params rss_params;
841 u32 tx_rates[MLX5E_MAX_NUM_SQS];
843 struct mlx5e_flow_steering fs;
845 struct workqueue_struct *wq;
846 struct work_struct update_carrier_work;
847 struct work_struct set_rx_mode_work;
848 struct work_struct tx_timeout_work;
849 struct work_struct update_stats_work;
850 struct work_struct monitor_counters_work;
851 struct mlx5_nb monitor_counters_nb;
853 struct mlx5_core_dev *mdev;
854 struct net_device *netdev;
855 struct mlx5e_trap *en_trap;
856 struct mlx5e_stats stats;
857 struct mlx5e_channel_stats channel_stats[MLX5E_MAX_NUM_CHANNELS];
858 struct mlx5e_channel_stats trap_stats;
859 struct mlx5e_ptp_stats ptp_stats;
863 struct hwtstamp_config tstamp;
865 u16 drop_rq_q_counter;
866 struct notifier_block events_nb;
867 struct notifier_block blocking_events_nb;
870 struct udp_tunnel_nic_info nic_info;
871 #ifdef CONFIG_MLX5_CORE_EN_DCB
872 struct mlx5e_dcbx dcbx;
875 const struct mlx5e_profile *profile;
877 #ifdef CONFIG_MLX5_EN_IPSEC
878 struct mlx5e_ipsec *ipsec;
880 #ifdef CONFIG_MLX5_EN_TLS
881 struct mlx5e_tls *tls;
883 struct devlink_health_reporter *tx_reporter;
884 struct devlink_health_reporter *rx_reporter;
885 struct mlx5e_xsk xsk;
886 #if IS_ENABLED(CONFIG_PCI_HYPERV_INTERFACE)
887 struct mlx5e_hv_vhca_stats_agent stats_agent;
889 struct mlx5e_scratchpad scratchpad;
890 struct mlx5e_htb htb;
893 struct mlx5e_rx_handlers {
894 mlx5e_fp_handle_rx_cqe handle_rx_cqe;
895 mlx5e_fp_handle_rx_cqe handle_rx_cqe_mpwqe;
898 extern const struct mlx5e_rx_handlers mlx5e_rx_handlers_nic;
900 struct mlx5e_profile {
901 int (*init)(struct mlx5_core_dev *mdev,
902 struct net_device *netdev);
903 void (*cleanup)(struct mlx5e_priv *priv);
904 int (*init_rx)(struct mlx5e_priv *priv);
905 void (*cleanup_rx)(struct mlx5e_priv *priv);
906 int (*init_tx)(struct mlx5e_priv *priv);
907 void (*cleanup_tx)(struct mlx5e_priv *priv);
908 void (*enable)(struct mlx5e_priv *priv);
909 void (*disable)(struct mlx5e_priv *priv);
910 int (*update_rx)(struct mlx5e_priv *priv);
911 void (*update_stats)(struct mlx5e_priv *priv);
912 void (*update_carrier)(struct mlx5e_priv *priv);
913 unsigned int (*stats_grps_num)(struct mlx5e_priv *priv);
914 mlx5e_stats_grp_t *stats_grps;
915 const struct mlx5e_rx_handlers *rx_handlers;
920 void mlx5e_build_ptys2ethtool_map(void);
922 bool mlx5e_check_fragmented_striding_rq_cap(struct mlx5_core_dev *mdev);
924 void mlx5e_get_stats(struct net_device *dev, struct rtnl_link_stats64 *stats);
925 void mlx5e_fold_sw_stats64(struct mlx5e_priv *priv, struct rtnl_link_stats64 *s);
927 void mlx5e_init_l2_addr(struct mlx5e_priv *priv);
928 int mlx5e_self_test_num(struct mlx5e_priv *priv);
929 void mlx5e_self_test(struct net_device *ndev, struct ethtool_test *etest,
931 void mlx5e_set_rx_mode_work(struct work_struct *work);
933 int mlx5e_hwstamp_set(struct mlx5e_priv *priv, struct ifreq *ifr);
934 int mlx5e_hwstamp_get(struct mlx5e_priv *priv, struct ifreq *ifr);
935 int mlx5e_modify_rx_cqe_compression_locked(struct mlx5e_priv *priv, bool val);
937 int mlx5e_vlan_rx_add_vid(struct net_device *dev, __always_unused __be16 proto,
939 int mlx5e_vlan_rx_kill_vid(struct net_device *dev, __always_unused __be16 proto,
941 void mlx5e_timestamp_init(struct mlx5e_priv *priv);
943 struct mlx5e_redirect_rqt_param {
946 u32 rqn; /* Direct RQN (Non-RSS) */
949 struct mlx5e_channels *channels;
950 } rss; /* RSS data */
954 int mlx5e_redirect_rqt(struct mlx5e_priv *priv, u32 rqtn, int sz,
955 struct mlx5e_redirect_rqt_param rrp);
956 void mlx5e_build_indir_tir_ctx_hash(struct mlx5e_rss_params *rss_params,
957 const struct mlx5e_tirc_config *ttconfig,
958 void *tirc, bool inner);
959 void mlx5e_modify_tirs_hash(struct mlx5e_priv *priv, void *in);
960 struct mlx5e_tirc_config mlx5e_tirc_get_default_config(enum mlx5e_traffic_types tt);
962 struct mlx5e_xsk_param;
964 struct mlx5e_rq_param;
965 int mlx5e_open_rq(struct mlx5e_params *params, struct mlx5e_rq_param *param,
966 struct mlx5e_xsk_param *xsk, int node,
967 struct mlx5e_rq *rq);
968 int mlx5e_wait_for_min_rx_wqes(struct mlx5e_rq *rq, int wait_time);
969 void mlx5e_deactivate_rq(struct mlx5e_rq *rq);
970 void mlx5e_close_rq(struct mlx5e_rq *rq);
971 int mlx5e_create_rq(struct mlx5e_rq *rq, struct mlx5e_rq_param *param);
972 void mlx5e_destroy_rq(struct mlx5e_rq *rq);
974 struct mlx5e_sq_param;
975 int mlx5e_open_icosq(struct mlx5e_channel *c, struct mlx5e_params *params,
976 struct mlx5e_sq_param *param, struct mlx5e_icosq *sq);
977 void mlx5e_close_icosq(struct mlx5e_icosq *sq);
978 int mlx5e_open_xdpsq(struct mlx5e_channel *c, struct mlx5e_params *params,
979 struct mlx5e_sq_param *param, struct xsk_buff_pool *xsk_pool,
980 struct mlx5e_xdpsq *sq, bool is_redirect);
981 void mlx5e_close_xdpsq(struct mlx5e_xdpsq *sq);
983 struct mlx5e_create_cq_param {
984 struct napi_struct *napi;
985 struct mlx5e_ch_stats *ch_stats;
990 struct mlx5e_cq_param;
991 int mlx5e_open_cq(struct mlx5e_priv *priv, struct dim_cq_moder moder,
992 struct mlx5e_cq_param *param, struct mlx5e_create_cq_param *ccp,
993 struct mlx5e_cq *cq);
994 void mlx5e_close_cq(struct mlx5e_cq *cq);
996 int mlx5e_open_locked(struct net_device *netdev);
997 int mlx5e_close_locked(struct net_device *netdev);
999 int mlx5e_open_channels(struct mlx5e_priv *priv,
1000 struct mlx5e_channels *chs);
1001 void mlx5e_close_channels(struct mlx5e_channels *chs);
1003 /* Function pointer to be used to modify HW or kernel settings while
1004 * switching channels
1006 typedef int (*mlx5e_fp_preactivate)(struct mlx5e_priv *priv, void *context);
1007 #define MLX5E_DEFINE_PREACTIVATE_WRAPPER_CTX(fn) \
1008 int fn##_ctx(struct mlx5e_priv *priv, void *context) \
1012 int mlx5e_safe_reopen_channels(struct mlx5e_priv *priv);
1013 int mlx5e_safe_switch_channels(struct mlx5e_priv *priv,
1014 struct mlx5e_channels *new_chs,
1015 mlx5e_fp_preactivate preactivate,
1017 int mlx5e_update_tx_netdev_queues(struct mlx5e_priv *priv);
1018 int mlx5e_num_channels_changed(struct mlx5e_priv *priv);
1019 int mlx5e_num_channels_changed_ctx(struct mlx5e_priv *priv, void *context);
1020 void mlx5e_activate_priv_channels(struct mlx5e_priv *priv);
1021 void mlx5e_deactivate_priv_channels(struct mlx5e_priv *priv);
1023 void mlx5e_build_default_indir_rqt(u32 *indirection_rqt, int len,
1026 int mlx5e_modify_rq_state(struct mlx5e_rq *rq, int curr_state, int next_state);
1027 void mlx5e_activate_rq(struct mlx5e_rq *rq);
1028 void mlx5e_deactivate_rq(struct mlx5e_rq *rq);
1029 void mlx5e_activate_icosq(struct mlx5e_icosq *icosq);
1030 void mlx5e_deactivate_icosq(struct mlx5e_icosq *icosq);
1032 int mlx5e_modify_sq(struct mlx5_core_dev *mdev, u32 sqn,
1033 struct mlx5e_modify_sq_param *p);
1034 int mlx5e_open_txqsq(struct mlx5e_channel *c, u32 tisn, int txq_ix,
1035 struct mlx5e_params *params, struct mlx5e_sq_param *param,
1036 struct mlx5e_txqsq *sq, int tc, u16 qos_queue_group_id, u16 qos_qid);
1037 void mlx5e_activate_txqsq(struct mlx5e_txqsq *sq);
1038 void mlx5e_deactivate_txqsq(struct mlx5e_txqsq *sq);
1039 void mlx5e_free_txqsq(struct mlx5e_txqsq *sq);
1040 void mlx5e_tx_disable_queue(struct netdev_queue *txq);
1041 int mlx5e_alloc_txqsq_db(struct mlx5e_txqsq *sq, int numa);
1042 void mlx5e_free_txqsq_db(struct mlx5e_txqsq *sq);
1043 struct mlx5e_create_sq_param;
1044 int mlx5e_create_sq_rdy(struct mlx5_core_dev *mdev,
1045 struct mlx5e_sq_param *param,
1046 struct mlx5e_create_sq_param *csp,
1047 u16 qos_queue_group_id,
1049 void mlx5e_tx_err_cqe_work(struct work_struct *recover_work);
1050 void mlx5e_close_txqsq(struct mlx5e_txqsq *sq);
1052 static inline bool mlx5_tx_swp_supported(struct mlx5_core_dev *mdev)
1054 return MLX5_CAP_ETH(mdev, swp) &&
1055 MLX5_CAP_ETH(mdev, swp_csum) && MLX5_CAP_ETH(mdev, swp_lso);
1058 extern const struct ethtool_ops mlx5e_ethtool_ops;
1060 int mlx5e_create_tir(struct mlx5_core_dev *mdev, struct mlx5e_tir *tir,
1062 void mlx5e_destroy_tir(struct mlx5_core_dev *mdev,
1063 struct mlx5e_tir *tir);
1064 int mlx5e_create_mdev_resources(struct mlx5_core_dev *mdev);
1065 void mlx5e_destroy_mdev_resources(struct mlx5_core_dev *mdev);
1066 int mlx5e_refresh_tirs(struct mlx5e_priv *priv, bool enable_uc_lb,
1068 void mlx5e_mkey_set_relaxed_ordering(struct mlx5_core_dev *mdev, void *mkc);
1070 /* common netdev helpers */
1071 void mlx5e_create_q_counters(struct mlx5e_priv *priv);
1072 void mlx5e_destroy_q_counters(struct mlx5e_priv *priv);
1073 int mlx5e_open_drop_rq(struct mlx5e_priv *priv,
1074 struct mlx5e_rq *drop_rq);
1075 void mlx5e_close_drop_rq(struct mlx5e_rq *drop_rq);
1076 int mlx5e_init_di_list(struct mlx5e_rq *rq, int wq_sz, int node);
1077 void mlx5e_free_di_list(struct mlx5e_rq *rq);
1079 int mlx5e_create_indirect_rqt(struct mlx5e_priv *priv);
1081 int mlx5e_create_indirect_tirs(struct mlx5e_priv *priv, bool inner_ttc);
1082 void mlx5e_destroy_indirect_tirs(struct mlx5e_priv *priv);
1084 int mlx5e_create_direct_rqts(struct mlx5e_priv *priv, struct mlx5e_tir *tirs, int n);
1085 void mlx5e_destroy_direct_rqts(struct mlx5e_priv *priv, struct mlx5e_tir *tirs, int n);
1086 int mlx5e_create_direct_tirs(struct mlx5e_priv *priv, struct mlx5e_tir *tirs, int n);
1087 void mlx5e_destroy_direct_tirs(struct mlx5e_priv *priv, struct mlx5e_tir *tirs, int n);
1088 void mlx5e_destroy_rqt(struct mlx5e_priv *priv, struct mlx5e_rqt *rqt);
1090 int mlx5e_create_tis(struct mlx5_core_dev *mdev, void *in, u32 *tisn);
1091 void mlx5e_destroy_tis(struct mlx5_core_dev *mdev, u32 tisn);
1093 int mlx5e_create_tises(struct mlx5e_priv *priv);
1094 void mlx5e_destroy_tises(struct mlx5e_priv *priv);
1095 int mlx5e_update_nic_rx(struct mlx5e_priv *priv);
1096 void mlx5e_update_carrier(struct mlx5e_priv *priv);
1097 int mlx5e_close(struct net_device *netdev);
1098 int mlx5e_open(struct net_device *netdev);
1100 void mlx5e_queue_update_stats(struct mlx5e_priv *priv);
1101 int mlx5e_bits_invert(unsigned long a, int size);
1103 int mlx5e_set_dev_port_mtu(struct mlx5e_priv *priv);
1104 int mlx5e_set_dev_port_mtu_ctx(struct mlx5e_priv *priv, void *context);
1105 int mlx5e_change_mtu(struct net_device *netdev, int new_mtu,
1106 mlx5e_fp_preactivate preactivate);
1107 void mlx5e_vxlan_set_netdev_info(struct mlx5e_priv *priv);
1109 /* ethtool helpers */
1110 void mlx5e_ethtool_get_drvinfo(struct mlx5e_priv *priv,
1111 struct ethtool_drvinfo *drvinfo);
1112 void mlx5e_ethtool_get_strings(struct mlx5e_priv *priv,
1113 uint32_t stringset, uint8_t *data);
1114 int mlx5e_ethtool_get_sset_count(struct mlx5e_priv *priv, int sset);
1115 void mlx5e_ethtool_get_ethtool_stats(struct mlx5e_priv *priv,
1116 struct ethtool_stats *stats, u64 *data);
1117 void mlx5e_ethtool_get_ringparam(struct mlx5e_priv *priv,
1118 struct ethtool_ringparam *param);
1119 int mlx5e_ethtool_set_ringparam(struct mlx5e_priv *priv,
1120 struct ethtool_ringparam *param);
1121 void mlx5e_ethtool_get_channels(struct mlx5e_priv *priv,
1122 struct ethtool_channels *ch);
1123 int mlx5e_ethtool_set_channels(struct mlx5e_priv *priv,
1124 struct ethtool_channels *ch);
1125 int mlx5e_ethtool_get_coalesce(struct mlx5e_priv *priv,
1126 struct ethtool_coalesce *coal);
1127 int mlx5e_ethtool_set_coalesce(struct mlx5e_priv *priv,
1128 struct ethtool_coalesce *coal);
1129 int mlx5e_ethtool_get_link_ksettings(struct mlx5e_priv *priv,
1130 struct ethtool_link_ksettings *link_ksettings);
1131 int mlx5e_ethtool_set_link_ksettings(struct mlx5e_priv *priv,
1132 const struct ethtool_link_ksettings *link_ksettings);
1133 int mlx5e_get_rxfh(struct net_device *netdev, u32 *indir, u8 *key, u8 *hfunc);
1134 int mlx5e_set_rxfh(struct net_device *dev, const u32 *indir, const u8 *key,
1136 int mlx5e_get_rxnfc(struct net_device *dev, struct ethtool_rxnfc *info,
1138 int mlx5e_set_rxnfc(struct net_device *dev, struct ethtool_rxnfc *cmd);
1139 u32 mlx5e_ethtool_get_rxfh_key_size(struct mlx5e_priv *priv);
1140 u32 mlx5e_ethtool_get_rxfh_indir_size(struct mlx5e_priv *priv);
1141 int mlx5e_ethtool_get_ts_info(struct mlx5e_priv *priv,
1142 struct ethtool_ts_info *info);
1143 int mlx5e_ethtool_flash_device(struct mlx5e_priv *priv,
1144 struct ethtool_flash *flash);
1145 void mlx5e_ethtool_get_pauseparam(struct mlx5e_priv *priv,
1146 struct ethtool_pauseparam *pauseparam);
1147 int mlx5e_ethtool_set_pauseparam(struct mlx5e_priv *priv,
1148 struct ethtool_pauseparam *pauseparam);
1150 /* mlx5e generic netdev management API */
1151 static inline unsigned int
1152 mlx5e_calc_max_nch(struct mlx5e_priv *priv, const struct mlx5e_profile *profile)
1154 return priv->netdev->num_rx_queues / max_t(u8, profile->rq_groups, 1);
1157 int mlx5e_priv_init(struct mlx5e_priv *priv,
1158 struct net_device *netdev,
1159 struct mlx5_core_dev *mdev);
1160 void mlx5e_priv_cleanup(struct mlx5e_priv *priv);
1162 mlx5e_create_netdev(struct mlx5_core_dev *mdev, unsigned int txqs, unsigned int rxqs);
1163 int mlx5e_attach_netdev(struct mlx5e_priv *priv);
1164 void mlx5e_detach_netdev(struct mlx5e_priv *priv);
1165 void mlx5e_destroy_netdev(struct mlx5e_priv *priv);
1166 int mlx5e_netdev_change_profile(struct mlx5e_priv *priv,
1167 const struct mlx5e_profile *new_profile, void *new_ppriv);
1168 void mlx5e_netdev_attach_nic_profile(struct mlx5e_priv *priv);
1169 void mlx5e_set_netdev_mtu_boundaries(struct mlx5e_priv *priv);
1170 void mlx5e_build_nic_params(struct mlx5e_priv *priv, struct mlx5e_xsk *xsk, u16 mtu);
1171 void mlx5e_build_rss_params(struct mlx5e_rss_params *rss_params,
1173 void mlx5e_rx_dim_work(struct work_struct *work);
1174 void mlx5e_tx_dim_work(struct work_struct *work);
1176 netdev_features_t mlx5e_features_check(struct sk_buff *skb,
1177 struct net_device *netdev,
1178 netdev_features_t features);
1179 int mlx5e_set_features(struct net_device *netdev, netdev_features_t features);
1180 #ifdef CONFIG_MLX5_ESWITCH
1181 int mlx5e_set_vf_mac(struct net_device *dev, int vf, u8 *mac);
1182 int mlx5e_set_vf_rate(struct net_device *dev, int vf, int min_tx_rate, int max_tx_rate);
1183 int mlx5e_get_vf_config(struct net_device *dev, int vf, struct ifla_vf_info *ivi);
1184 int mlx5e_get_vf_stats(struct net_device *dev, int vf, struct ifla_vf_stats *vf_stats);
1186 #endif /* __MLX5_EN_H__ */