2 * Copyright (c) 2015-2016, Mellanox Technologies. All rights reserved.
4 * This software is available to you under a choice of one of two
5 * licenses. You may choose to be licensed under the terms of the GNU
6 * General Public License (GPL) Version 2, available from the file
7 * COPYING in the main directory of this source tree, or the
8 * OpenIB.org BSD license below:
10 * Redistribution and use in source and binary forms, with or
11 * without modification, are permitted provided that the following
14 * - Redistributions of source code must retain the above
15 * copyright notice, this list of conditions and the following
18 * - Redistributions in binary form must reproduce the above
19 * copyright notice, this list of conditions and the following
20 * disclaimer in the documentation and/or other materials
21 * provided with the distribution.
23 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
24 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
25 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
26 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
27 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
28 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
29 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
35 #include <linux/if_vlan.h>
36 #include <linux/etherdevice.h>
37 #include <linux/timecounter.h>
38 #include <linux/net_tstamp.h>
39 #include <linux/ptp_clock_kernel.h>
40 #include <linux/crash_dump.h>
41 #include <linux/mlx5/driver.h>
42 #include <linux/mlx5/qp.h>
43 #include <linux/mlx5/cq.h>
44 #include <linux/mlx5/port.h>
45 #include <linux/mlx5/vport.h>
46 #include <linux/mlx5/transobj.h>
47 #include <linux/mlx5/fs.h>
48 #include <linux/rhashtable.h>
49 #include <net/switchdev.h>
51 #include <linux/dim.h>
52 #include <linux/bits.h>
54 #include "mlx5_core.h"
57 #include "lib/hv_vhca.h"
59 extern const struct net_device_ops mlx5e_netdev_ops;
62 #define MLX5E_METADATA_ETHER_TYPE (0x8CE4)
63 #define MLX5E_METADATA_ETHER_LEN 8
65 #define MLX5_SET_CFG(p, f, v) MLX5_SET(create_flow_group_in, p, f, v)
67 #define MLX5E_ETH_HARD_MTU (ETH_HLEN + VLAN_HLEN + ETH_FCS_LEN)
69 #define MLX5E_HW2SW_MTU(params, hwmtu) ((hwmtu) - ((params)->hard_mtu))
70 #define MLX5E_SW2HW_MTU(params, swmtu) ((swmtu) + ((params)->hard_mtu))
72 #define MLX5E_MAX_PRIORITY 8
73 #define MLX5E_MAX_DSCP 64
74 #define MLX5E_MAX_NUM_TC 8
76 #define MLX5_RX_HEADROOM NET_SKB_PAD
77 #define MLX5_SKB_FRAG_SZ(len) (SKB_DATA_ALIGN(len) + \
78 SKB_DATA_ALIGN(sizeof(struct skb_shared_info)))
80 #define MLX5E_RX_MAX_HEAD (256)
82 #define MLX5_MPWRQ_MIN_LOG_STRIDE_SZ(mdev) \
83 (6 + MLX5_CAP_GEN(mdev, cache_line_128byte)) /* HW restriction */
84 #define MLX5_MPWRQ_LOG_STRIDE_SZ(mdev, req) \
85 max_t(u32, MLX5_MPWRQ_MIN_LOG_STRIDE_SZ(mdev), req)
86 #define MLX5_MPWRQ_DEF_LOG_STRIDE_SZ(mdev) \
87 MLX5_MPWRQ_LOG_STRIDE_SZ(mdev, order_base_2(MLX5E_RX_MAX_HEAD))
89 #define MLX5_MPWRQ_LOG_WQE_SZ 18
90 #define MLX5_MPWRQ_WQE_PAGE_ORDER (MLX5_MPWRQ_LOG_WQE_SZ - PAGE_SHIFT > 0 ? \
91 MLX5_MPWRQ_LOG_WQE_SZ - PAGE_SHIFT : 0)
92 #define MLX5_MPWRQ_PAGES_PER_WQE BIT(MLX5_MPWRQ_WQE_PAGE_ORDER)
94 #define MLX5_MTT_OCTW(npages) (ALIGN(npages, 8) / 2)
95 #define MLX5E_REQUIRED_WQE_MTTS (ALIGN(MLX5_MPWRQ_PAGES_PER_WQE, 8))
96 #define MLX5E_LOG_ALIGNED_MPWQE_PPW (ilog2(MLX5E_REQUIRED_WQE_MTTS))
97 #define MLX5E_REQUIRED_MTTS(wqes) (wqes * MLX5E_REQUIRED_WQE_MTTS)
98 #define MLX5E_MAX_RQ_NUM_MTTS \
99 ((1 << 16) * 2) /* So that MLX5_MTT_OCTW(num_mtts) fits into u16 */
100 #define MLX5E_ORDER2_MAX_PACKET_MTU (order_base_2(10 * 1024))
101 #define MLX5E_PARAMS_MAXIMUM_LOG_RQ_SIZE_MPW \
102 (ilog2(MLX5E_MAX_RQ_NUM_MTTS / MLX5E_REQUIRED_WQE_MTTS))
103 #define MLX5E_LOG_MAX_RQ_NUM_PACKETS_MPW \
104 (MLX5E_PARAMS_MAXIMUM_LOG_RQ_SIZE_MPW + \
105 (MLX5_MPWRQ_LOG_WQE_SZ - MLX5E_ORDER2_MAX_PACKET_MTU))
107 #define MLX5E_MIN_SKB_FRAG_SZ (MLX5_SKB_FRAG_SZ(MLX5_RX_HEADROOM))
108 #define MLX5E_LOG_MAX_RX_WQE_BULK \
109 (ilog2(PAGE_SIZE / roundup_pow_of_two(MLX5E_MIN_SKB_FRAG_SZ)))
111 #define MLX5E_PARAMS_MINIMUM_LOG_SQ_SIZE 0x6
112 #define MLX5E_PARAMS_DEFAULT_LOG_SQ_SIZE 0xa
113 #define MLX5E_PARAMS_MAXIMUM_LOG_SQ_SIZE 0xd
115 #define MLX5E_PARAMS_MINIMUM_LOG_RQ_SIZE (1 + MLX5E_LOG_MAX_RX_WQE_BULK)
116 #define MLX5E_PARAMS_DEFAULT_LOG_RQ_SIZE 0xa
117 #define MLX5E_PARAMS_MAXIMUM_LOG_RQ_SIZE min_t(u8, 0xd, \
118 MLX5E_LOG_MAX_RQ_NUM_PACKETS_MPW)
120 #define MLX5E_PARAMS_MINIMUM_LOG_RQ_SIZE_MPW 0x2
122 #define MLX5E_PARAMS_DEFAULT_LRO_WQE_SZ (64 * 1024)
123 #define MLX5E_DEFAULT_LRO_TIMEOUT 32
124 #define MLX5E_LRO_TIMEOUT_ARR_SIZE 4
126 #define MLX5E_PARAMS_DEFAULT_RX_CQ_MODERATION_USEC 0x10
127 #define MLX5E_PARAMS_DEFAULT_RX_CQ_MODERATION_USEC_FROM_CQE 0x3
128 #define MLX5E_PARAMS_DEFAULT_RX_CQ_MODERATION_PKTS 0x20
129 #define MLX5E_PARAMS_DEFAULT_TX_CQ_MODERATION_USEC 0x10
130 #define MLX5E_PARAMS_DEFAULT_TX_CQ_MODERATION_USEC_FROM_CQE 0x10
131 #define MLX5E_PARAMS_DEFAULT_TX_CQ_MODERATION_PKTS 0x20
132 #define MLX5E_PARAMS_DEFAULT_MIN_RX_WQES 0x80
133 #define MLX5E_PARAMS_DEFAULT_MIN_RX_WQES_MPW 0x2
135 #define MLX5E_LOG_INDIR_RQT_SIZE 0x7
136 #define MLX5E_INDIR_RQT_SIZE BIT(MLX5E_LOG_INDIR_RQT_SIZE)
137 #define MLX5E_MIN_NUM_CHANNELS 0x1
138 #define MLX5E_MAX_NUM_CHANNELS MLX5E_INDIR_RQT_SIZE
139 #define MLX5E_MAX_NUM_SQS (MLX5E_MAX_NUM_CHANNELS * MLX5E_MAX_NUM_TC)
140 #define MLX5E_TX_CQ_POLL_BUDGET 128
141 #define MLX5E_TX_XSK_POLL_BUDGET 64
142 #define MLX5E_SQ_RECOVER_MIN_INTERVAL 500 /* msecs */
144 #define MLX5E_UMR_WQE_INLINE_SZ \
145 (sizeof(struct mlx5e_umr_wqe) + \
146 ALIGN(MLX5_MPWRQ_PAGES_PER_WQE * sizeof(struct mlx5_mtt), \
147 MLX5_UMR_MTT_ALIGNMENT))
148 #define MLX5E_UMR_WQEBBS \
149 (DIV_ROUND_UP(MLX5E_UMR_WQE_INLINE_SZ, MLX5_SEND_WQE_BB))
151 #define MLX5E_MSG_LEVEL NETIF_MSG_LINK
153 #define mlx5e_dbg(mlevel, priv, format, ...) \
155 if (NETIF_MSG_##mlevel & (priv)->msglevel) \
156 netdev_warn(priv->netdev, format, \
160 enum mlx5e_rq_group {
161 MLX5E_RQ_GROUP_REGULAR,
163 #define MLX5E_NUM_RQ_GROUPS(g) (1 + MLX5E_RQ_GROUP_##g)
166 static inline u8 mlx5e_get_num_lag_ports(struct mlx5_core_dev *mdev)
168 if (mlx5_lag_is_lacp_owner(mdev))
171 return clamp_t(u8, MLX5_CAP_GEN(mdev, num_lag_ports), 1, MLX5_MAX_PORTS);
174 static inline u16 mlx5_min_rx_wqes(int wq_type, u32 wq_size)
177 case MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ:
178 return min_t(u16, MLX5E_PARAMS_DEFAULT_MIN_RX_WQES_MPW,
181 return min_t(u16, MLX5E_PARAMS_DEFAULT_MIN_RX_WQES,
186 /* Use this function to get max num channels (rxqs/txqs) only to create netdev */
187 static inline int mlx5e_get_max_num_channels(struct mlx5_core_dev *mdev)
189 return is_kdump_kernel() ?
190 MLX5E_MIN_NUM_CHANNELS :
191 min_t(int, mlx5_comp_vectors_count(mdev), MLX5E_MAX_NUM_CHANNELS);
194 struct mlx5e_tx_wqe {
195 struct mlx5_wqe_ctrl_seg ctrl;
198 struct mlx5_wqe_eth_seg eth;
199 struct mlx5_wqe_data_seg data[0];
201 u8 tls_progress_params_ctx[0];
205 struct mlx5e_rx_wqe_ll {
206 struct mlx5_wqe_srq_next_seg next;
207 struct mlx5_wqe_data_seg data[];
210 struct mlx5e_rx_wqe_cyc {
211 struct mlx5_wqe_data_seg data[0];
214 struct mlx5e_umr_wqe {
215 struct mlx5_wqe_ctrl_seg ctrl;
216 struct mlx5_wqe_umr_ctrl_seg uctrl;
217 struct mlx5_mkey_seg mkc;
219 struct mlx5_mtt inline_mtts[0];
220 u8 tls_static_params_ctx[0];
224 extern const char mlx5e_self_tests[][ETH_GSTRING_LEN];
226 enum mlx5e_priv_flag {
227 MLX5E_PFLAG_RX_CQE_BASED_MODER,
228 MLX5E_PFLAG_TX_CQE_BASED_MODER,
229 MLX5E_PFLAG_RX_CQE_COMPRESS,
230 MLX5E_PFLAG_RX_STRIDING_RQ,
231 MLX5E_PFLAG_RX_NO_CSUM_COMPLETE,
232 MLX5E_PFLAG_XDP_TX_MPWQE,
233 MLX5E_NUM_PFLAGS, /* Keep last */
236 #define MLX5E_SET_PFLAG(params, pflag, enable) \
239 (params)->pflags |= BIT(pflag); \
241 (params)->pflags &= ~(BIT(pflag)); \
244 #define MLX5E_GET_PFLAG(params, pflag) (!!((params)->pflags & (BIT(pflag))))
246 #ifdef CONFIG_MLX5_CORE_EN_DCB
247 #define MLX5E_MAX_BW_ALLOC 100 /* Max percentage of BW allocation */
250 struct mlx5e_params {
253 u8 log_rq_mtu_frames;
256 bool rx_cqe_compress_def;
257 bool tunneled_offload_en;
258 struct dim_cq_moder rx_cq_moderation;
259 struct dim_cq_moder tx_cq_moderation;
261 u8 tx_min_inline_mode;
262 bool vlan_strip_disable;
268 struct bpf_prog *xdp_prog;
269 struct mlx5e_xsk *xsk;
274 #ifdef CONFIG_MLX5_CORE_EN_DCB
275 struct mlx5e_cee_config {
276 /* bw pct for priority group */
277 u8 pg_bw_pct[CEE_DCBX_MAX_PGS];
278 u8 prio_to_pg_map[CEE_DCBX_MAX_PRIO];
279 bool pfc_setting[CEE_DCBX_MAX_PRIO];
286 MLX5_DCB_CHG_NO_RESET,
290 enum mlx5_dcbx_oper_mode mode;
291 struct mlx5e_cee_config cee_cfg; /* pending configuration */
294 /* The only setting that cannot be read from FW */
295 u8 tc_tsa[IEEE_8021QAZ_MAX_TCS];
298 /* Buffer configuration */
304 struct mlx5e_dcbx_dp {
305 u8 dscp2prio[MLX5E_MAX_DSCP];
311 MLX5E_RQ_STATE_ENABLED,
312 MLX5E_RQ_STATE_RECOVERING,
314 MLX5E_RQ_STATE_NO_CSUM_COMPLETE,
315 MLX5E_RQ_STATE_CSUM_FULL, /* cqe_csum_full hw bit is set */
319 /* data path - accessed per cqe */
322 /* data path - accessed per napi poll */
324 struct napi_struct *napi;
325 struct mlx5_core_cq mcq;
326 struct mlx5e_channel *channel;
329 struct mlx5_core_dev *mdev;
330 struct mlx5_wq_ctrl wq_ctrl;
331 } ____cacheline_aligned_in_smp;
333 struct mlx5e_cq_decomp {
334 /* cqe decompression */
335 struct mlx5_cqe64 title;
336 struct mlx5_mini_cqe8 mini_arr[MLX5_MINI_CQE_ARRAY_SIZE];
340 } ____cacheline_aligned_in_smp;
342 enum mlx5e_dma_map_type {
343 MLX5E_DMA_MAP_SINGLE,
347 struct mlx5e_sq_dma {
350 enum mlx5e_dma_map_type type;
354 MLX5E_SQ_STATE_ENABLED,
355 MLX5E_SQ_STATE_RECOVERING,
356 MLX5E_SQ_STATE_IPSEC,
359 MLX5E_SQ_STATE_VLAN_NEED_L2_INLINE,
360 MLX5E_SQ_STATE_PENDING_XSK_TX,
366 /* dirtied @completion */
369 struct dim dim; /* Adaptive Moderation */
372 u16 pc ____cacheline_aligned_in_smp;
378 struct mlx5_wq_cyc wq;
380 struct mlx5e_sq_stats *stats;
382 struct mlx5e_sq_dma *dma_fifo;
383 struct mlx5e_tx_wqe_info *wqe_info;
385 void __iomem *uar_map;
386 struct netdev_queue *txq;
394 struct hwtstamp_config *tstamp;
395 struct mlx5_clock *clock;
398 struct mlx5_wq_ctrl wq_ctrl;
399 struct mlx5e_channel *channel;
403 struct work_struct recover_work;
404 } ____cacheline_aligned_in_smp;
406 struct mlx5e_dma_info {
410 struct xdp_buff *xsk;
414 /* XDP packets can be transmitted in different ways. On completion, we need to
415 * distinguish between them to clean up things in a proper way.
417 enum mlx5e_xdp_xmit_mode {
418 /* An xdp_frame was transmitted due to either XDP_REDIRECT from another
419 * device or XDP_TX from an XSK RQ. The frame has to be unmapped and
422 MLX5E_XDP_XMIT_MODE_FRAME,
424 /* The xdp_frame was created in place as a result of XDP_TX from a
425 * regular RQ. No DMA remapping happened, and the page belongs to us.
427 MLX5E_XDP_XMIT_MODE_PAGE,
429 /* No xdp_frame was created at all, the transmit happened from a UMEM
430 * page. The UMEM Completion Ring producer pointer has to be increased.
432 MLX5E_XDP_XMIT_MODE_XSK,
435 struct mlx5e_xdp_info {
436 enum mlx5e_xdp_xmit_mode mode;
439 struct xdp_frame *xdpf;
444 struct mlx5e_dma_info di;
449 struct mlx5e_xdp_xmit_data {
455 struct mlx5e_xdp_info_fifo {
456 struct mlx5e_xdp_info *xi;
462 struct mlx5e_xdp_mpwqe {
463 /* Current MPWQE session */
464 struct mlx5e_tx_wqe *wqe;
471 typedef int (*mlx5e_fp_xmit_xdp_frame_check)(struct mlx5e_xdpsq *);
472 typedef bool (*mlx5e_fp_xmit_xdp_frame)(struct mlx5e_xdpsq *,
473 struct mlx5e_xdp_xmit_data *,
474 struct mlx5e_xdp_info *,
480 /* dirtied @completion */
485 u32 xdpi_fifo_pc ____cacheline_aligned_in_smp;
487 struct mlx5_wqe_ctrl_seg *doorbell_cseg;
488 struct mlx5e_xdp_mpwqe mpwqe;
493 struct xdp_umem *umem;
494 struct mlx5_wq_cyc wq;
495 struct mlx5e_xdpsq_stats *stats;
496 mlx5e_fp_xmit_xdp_frame_check xmit_xdp_frame_check;
497 mlx5e_fp_xmit_xdp_frame xmit_xdp_frame;
499 struct mlx5e_xdp_wqe_info *wqe_info;
500 struct mlx5e_xdp_info_fifo xdpi_fifo;
502 void __iomem *uar_map;
511 struct mlx5_wq_ctrl wq_ctrl;
512 struct mlx5e_channel *channel;
513 } ____cacheline_aligned_in_smp;
520 struct mlx5_wqe_ctrl_seg *doorbell_cseg;
523 /* write@xmit, read@completion */
525 struct mlx5e_icosq_wqe_info *wqe_info;
529 struct mlx5_wq_cyc wq;
530 void __iomem *uar_map;
535 struct mlx5_wq_ctrl wq_ctrl;
536 struct mlx5e_channel *channel;
538 struct work_struct recover_work;
539 } ____cacheline_aligned_in_smp;
541 struct mlx5e_wqe_frag_info {
542 struct mlx5e_dma_info *di;
547 struct mlx5e_umr_dma_info {
548 struct mlx5e_dma_info dma_info[MLX5_MPWRQ_PAGES_PER_WQE];
551 struct mlx5e_mpw_info {
552 struct mlx5e_umr_dma_info umr;
553 u16 consumed_strides;
554 DECLARE_BITMAP(xdp_xmit_bitmap, MLX5_MPWRQ_PAGES_PER_WQE);
557 #define MLX5E_MAX_RX_FRAGS 4
559 /* a single cache unit is capable to serve one napi call (for non-striding rq)
560 * or a MPWQE (for striding rq).
562 #define MLX5E_CACHE_UNIT (MLX5_MPWRQ_PAGES_PER_WQE > NAPI_POLL_WEIGHT ? \
563 MLX5_MPWRQ_PAGES_PER_WQE : NAPI_POLL_WEIGHT)
564 #define MLX5E_CACHE_SIZE (4 * roundup_pow_of_two(MLX5E_CACHE_UNIT))
565 struct mlx5e_page_cache {
568 struct mlx5e_dma_info page_cache[MLX5E_CACHE_SIZE];
572 typedef void (*mlx5e_fp_handle_rx_cqe)(struct mlx5e_rq*, struct mlx5_cqe64*);
573 typedef struct sk_buff *
574 (*mlx5e_fp_skb_from_cqe_mpwrq)(struct mlx5e_rq *rq, struct mlx5e_mpw_info *wi,
575 u16 cqe_bcnt, u32 head_offset, u32 page_idx);
576 typedef struct sk_buff *
577 (*mlx5e_fp_skb_from_cqe)(struct mlx5e_rq *rq, struct mlx5_cqe64 *cqe,
578 struct mlx5e_wqe_frag_info *wi, u32 cqe_bcnt);
579 typedef bool (*mlx5e_fp_post_rx_wqes)(struct mlx5e_rq *rq);
580 typedef void (*mlx5e_fp_dealloc_wqe)(struct mlx5e_rq*, u16);
583 MLX5E_RQ_FLAG_XDP_XMIT,
584 MLX5E_RQ_FLAG_XDP_REDIRECT,
587 struct mlx5e_rq_frag_info {
592 struct mlx5e_rq_frags_info {
593 struct mlx5e_rq_frag_info arr[MLX5E_MAX_RX_FRAGS];
603 struct mlx5_wq_cyc wq;
604 struct mlx5e_wqe_frag_info *frags;
605 struct mlx5e_dma_info *di;
606 struct mlx5e_rq_frags_info info;
607 mlx5e_fp_skb_from_cqe skb_from_cqe;
610 struct mlx5_wq_ll wq;
611 struct mlx5e_umr_wqe umr_wqe;
612 struct mlx5e_mpw_info *info;
613 mlx5e_fp_skb_from_cqe_mpwrq skb_from_cqe_mpwrq;
625 u8 map_dir; /* dma map direction */
628 struct mlx5e_channel *channel;
630 struct net_device *netdev;
631 struct mlx5e_rq_stats *stats;
633 struct mlx5e_cq_decomp cqd;
634 struct mlx5e_page_cache page_cache;
635 struct hwtstamp_config *tstamp;
636 struct mlx5_clock *clock;
638 mlx5e_fp_handle_rx_cqe handle_rx_cqe;
639 mlx5e_fp_post_rx_wqes post_wqes;
640 mlx5e_fp_dealloc_wqe dealloc_wqe;
646 struct dim dim; /* Dynamic Interrupt Moderation */
649 struct bpf_prog *xdp_prog;
650 struct mlx5e_xdpsq *xdpsq;
651 DECLARE_BITMAP(flags, 8);
652 struct page_pool *page_pool;
654 /* AF_XDP zero-copy */
655 struct xdp_umem *umem;
657 struct work_struct recover_work;
660 struct mlx5_wq_ctrl wq_ctrl;
664 struct mlx5_core_dev *mdev;
665 struct mlx5_core_mkey umr_mkey;
667 /* XDP read-mostly */
668 struct xdp_rxq_info xdp_rxq;
669 } ____cacheline_aligned_in_smp;
671 enum mlx5e_channel_state {
672 MLX5E_CHANNEL_STATE_XSK,
673 MLX5E_CHANNEL_NUM_STATES
676 struct mlx5e_channel {
679 struct mlx5e_xdpsq rq_xdpsq;
680 struct mlx5e_txqsq sq[MLX5E_MAX_NUM_TC];
681 struct mlx5e_icosq icosq; /* internal control operations */
683 struct napi_struct napi;
685 struct net_device *netdev;
691 struct mlx5e_xdpsq xdpsq;
693 /* AF_XDP zero-copy */
694 struct mlx5e_rq xskrq;
695 struct mlx5e_xdpsq xsksq;
696 struct mlx5e_icosq xskicosq;
697 /* xskicosq can be accessed from any CPU - the spinlock protects it. */
698 spinlock_t xskicosq_lock;
700 /* data path - accessed per napi poll */
701 struct irq_desc *irq_desc;
702 struct mlx5e_ch_stats *stats;
705 struct mlx5e_priv *priv;
706 struct mlx5_core_dev *mdev;
707 struct hwtstamp_config *tstamp;
708 DECLARE_BITMAP(state, MLX5E_CHANNEL_NUM_STATES);
713 struct mlx5e_channels {
714 struct mlx5e_channel **c;
716 struct mlx5e_params params;
719 struct mlx5e_channel_stats {
720 struct mlx5e_ch_stats ch;
721 struct mlx5e_sq_stats sq[MLX5E_MAX_NUM_TC];
722 struct mlx5e_rq_stats rq;
723 struct mlx5e_rq_stats xskrq;
724 struct mlx5e_xdpsq_stats rq_xdpsq;
725 struct mlx5e_xdpsq_stats xdpsq;
726 struct mlx5e_xdpsq_stats xsksq;
727 } ____cacheline_aligned_in_smp;
731 MLX5E_STATE_DESTROYING,
732 MLX5E_STATE_XDP_TX_ENABLED,
733 MLX5E_STATE_XDP_ACTIVE,
743 struct mlx5e_rqt rqt;
744 struct list_head list;
752 struct mlx5e_rss_params {
753 u32 indirection_rqt[MLX5E_INDIR_RQT_SIZE];
754 u32 rx_hash_fields[MLX5E_NUM_INDIR_TIRS];
755 u8 toeplitz_hash_key[40];
759 struct mlx5e_modify_sq_param {
766 #if IS_ENABLED(CONFIG_PCI_HYPERV_INTERFACE)
767 struct mlx5e_hv_vhca_stats_agent {
768 struct mlx5_hv_vhca_agent *agent;
769 struct delayed_work work;
776 /* UMEMs are stored separately from channels, because we don't want to
777 * lose them when channels are recreated. The kernel also stores UMEMs,
778 * but it doesn't distinguish between zero-copy and non-zero-copy UMEMs,
779 * so rely on our mechanism.
781 struct xdp_umem **umems;
786 /* Temporary storage for variables that are allocated when struct mlx5e_priv is
787 * initialized, and used where we can't allocate them because that functions
788 * must not fail. Use with care and make sure the same variable is not used
789 * simultaneously by multiple users.
791 struct mlx5e_scratchpad {
792 cpumask_var_t cpumask;
796 /* priv data path fields - start */
797 struct mlx5e_txqsq *txq2sq[MLX5E_MAX_NUM_CHANNELS * MLX5E_MAX_NUM_TC];
798 int channel_tc2realtxq[MLX5E_MAX_NUM_CHANNELS][MLX5E_MAX_NUM_TC];
799 #ifdef CONFIG_MLX5_CORE_EN_DCB
800 struct mlx5e_dcbx_dp dcbx_dp;
802 /* priv data path fields - end */
806 struct mutex state_lock; /* Protects Interface state */
807 struct mlx5e_rq drop_rq;
809 struct mlx5e_channels channels;
810 u32 tisn[MLX5_MAX_PORTS][MLX5E_MAX_NUM_TC];
811 struct mlx5e_rqt indir_rqt;
812 struct mlx5e_tir indir_tir[MLX5E_NUM_INDIR_TIRS];
813 struct mlx5e_tir inner_indir_tir[MLX5E_NUM_INDIR_TIRS];
814 struct mlx5e_tir direct_tir[MLX5E_MAX_NUM_CHANNELS];
815 struct mlx5e_tir xsk_tir[MLX5E_MAX_NUM_CHANNELS];
816 struct mlx5e_rss_params rss_params;
817 u32 tx_rates[MLX5E_MAX_NUM_SQS];
819 struct mlx5e_flow_steering fs;
821 struct workqueue_struct *wq;
822 struct work_struct update_carrier_work;
823 struct work_struct set_rx_mode_work;
824 struct work_struct tx_timeout_work;
825 struct work_struct update_stats_work;
826 struct work_struct monitor_counters_work;
827 struct mlx5_nb monitor_counters_nb;
829 struct mlx5_core_dev *mdev;
830 struct net_device *netdev;
831 struct mlx5e_stats stats;
832 struct mlx5e_channel_stats channel_stats[MLX5E_MAX_NUM_CHANNELS];
835 struct hwtstamp_config tstamp;
837 u16 drop_rq_q_counter;
838 struct notifier_block events_nb;
840 #ifdef CONFIG_MLX5_CORE_EN_DCB
841 struct mlx5e_dcbx dcbx;
844 const struct mlx5e_profile *profile;
846 #ifdef CONFIG_MLX5_EN_IPSEC
847 struct mlx5e_ipsec *ipsec;
849 #ifdef CONFIG_MLX5_EN_TLS
850 struct mlx5e_tls *tls;
852 struct devlink_health_reporter *tx_reporter;
853 struct devlink_health_reporter *rx_reporter;
854 struct devlink_port dl_port;
855 struct mlx5e_xsk xsk;
856 #if IS_ENABLED(CONFIG_PCI_HYPERV_INTERFACE)
857 struct mlx5e_hv_vhca_stats_agent stats_agent;
859 struct mlx5e_scratchpad scratchpad;
862 struct mlx5e_profile {
863 int (*init)(struct mlx5_core_dev *mdev,
864 struct net_device *netdev,
865 const struct mlx5e_profile *profile, void *ppriv);
866 void (*cleanup)(struct mlx5e_priv *priv);
867 int (*init_rx)(struct mlx5e_priv *priv);
868 void (*cleanup_rx)(struct mlx5e_priv *priv);
869 int (*init_tx)(struct mlx5e_priv *priv);
870 void (*cleanup_tx)(struct mlx5e_priv *priv);
871 void (*enable)(struct mlx5e_priv *priv);
872 void (*disable)(struct mlx5e_priv *priv);
873 int (*update_rx)(struct mlx5e_priv *priv);
874 void (*update_stats)(struct mlx5e_priv *priv);
875 void (*update_carrier)(struct mlx5e_priv *priv);
876 unsigned int (*stats_grps_num)(struct mlx5e_priv *priv);
877 mlx5e_stats_grp_t *stats_grps;
879 mlx5e_fp_handle_rx_cqe handle_rx_cqe;
880 mlx5e_fp_handle_rx_cqe handle_rx_cqe_mpwqe;
886 void mlx5e_build_ptys2ethtool_map(void);
888 u16 mlx5e_select_queue(struct net_device *dev, struct sk_buff *skb,
889 struct net_device *sb_dev);
890 netdev_tx_t mlx5e_xmit(struct sk_buff *skb, struct net_device *dev);
891 void mlx5e_sq_xmit(struct mlx5e_txqsq *sq, struct sk_buff *skb,
892 struct mlx5e_tx_wqe *wqe, u16 pi, bool xmit_more);
894 void mlx5e_trigger_irq(struct mlx5e_icosq *sq);
895 void mlx5e_completion_event(struct mlx5_core_cq *mcq, struct mlx5_eqe *eqe);
896 void mlx5e_cq_error_event(struct mlx5_core_cq *mcq, enum mlx5_event event);
897 int mlx5e_napi_poll(struct napi_struct *napi, int budget);
898 bool mlx5e_poll_tx_cq(struct mlx5e_cq *cq, int napi_budget);
899 int mlx5e_poll_rx_cq(struct mlx5e_cq *cq, int budget);
900 void mlx5e_free_txqsq_descs(struct mlx5e_txqsq *sq);
902 static inline u32 mlx5e_rqwq_get_size(struct mlx5e_rq *rq)
904 switch (rq->wq_type) {
905 case MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ:
906 return mlx5_wq_ll_get_size(&rq->mpwqe.wq);
908 return mlx5_wq_cyc_get_size(&rq->wqe.wq);
912 static inline u32 mlx5e_rqwq_get_cur_sz(struct mlx5e_rq *rq)
914 switch (rq->wq_type) {
915 case MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ:
916 return rq->mpwqe.wq.cur_sz;
918 return rq->wqe.wq.cur_sz;
922 bool mlx5e_check_fragmented_striding_rq_cap(struct mlx5_core_dev *mdev);
923 bool mlx5e_striding_rq_possible(struct mlx5_core_dev *mdev,
924 struct mlx5e_params *params);
926 void mlx5e_page_dma_unmap(struct mlx5e_rq *rq, struct mlx5e_dma_info *dma_info);
927 void mlx5e_page_release_dynamic(struct mlx5e_rq *rq,
928 struct mlx5e_dma_info *dma_info,
930 void mlx5e_handle_rx_cqe(struct mlx5e_rq *rq, struct mlx5_cqe64 *cqe);
931 void mlx5e_handle_rx_cqe_mpwrq(struct mlx5e_rq *rq, struct mlx5_cqe64 *cqe);
932 bool mlx5e_post_rx_wqes(struct mlx5e_rq *rq);
933 int mlx5e_poll_ico_cq(struct mlx5e_cq *cq);
934 bool mlx5e_post_rx_mpwqes(struct mlx5e_rq *rq);
935 void mlx5e_dealloc_rx_wqe(struct mlx5e_rq *rq, u16 ix);
936 void mlx5e_dealloc_rx_mpwqe(struct mlx5e_rq *rq, u16 ix);
938 mlx5e_skb_from_cqe_mpwrq_linear(struct mlx5e_rq *rq, struct mlx5e_mpw_info *wi,
939 u16 cqe_bcnt, u32 head_offset, u32 page_idx);
941 mlx5e_skb_from_cqe_mpwrq_nonlinear(struct mlx5e_rq *rq, struct mlx5e_mpw_info *wi,
942 u16 cqe_bcnt, u32 head_offset, u32 page_idx);
944 mlx5e_skb_from_cqe_linear(struct mlx5e_rq *rq, struct mlx5_cqe64 *cqe,
945 struct mlx5e_wqe_frag_info *wi, u32 cqe_bcnt);
947 mlx5e_skb_from_cqe_nonlinear(struct mlx5e_rq *rq, struct mlx5_cqe64 *cqe,
948 struct mlx5e_wqe_frag_info *wi, u32 cqe_bcnt);
950 void mlx5e_get_stats(struct net_device *dev, struct rtnl_link_stats64 *stats);
951 void mlx5e_fold_sw_stats64(struct mlx5e_priv *priv, struct rtnl_link_stats64 *s);
953 void mlx5e_init_l2_addr(struct mlx5e_priv *priv);
954 int mlx5e_self_test_num(struct mlx5e_priv *priv);
955 void mlx5e_self_test(struct net_device *ndev, struct ethtool_test *etest,
957 void mlx5e_set_rx_mode_work(struct work_struct *work);
959 int mlx5e_hwstamp_set(struct mlx5e_priv *priv, struct ifreq *ifr);
960 int mlx5e_hwstamp_get(struct mlx5e_priv *priv, struct ifreq *ifr);
961 int mlx5e_modify_rx_cqe_compression_locked(struct mlx5e_priv *priv, bool val);
963 int mlx5e_vlan_rx_add_vid(struct net_device *dev, __always_unused __be16 proto,
965 int mlx5e_vlan_rx_kill_vid(struct net_device *dev, __always_unused __be16 proto,
967 void mlx5e_timestamp_init(struct mlx5e_priv *priv);
969 struct mlx5e_redirect_rqt_param {
972 u32 rqn; /* Direct RQN (Non-RSS) */
975 struct mlx5e_channels *channels;
976 } rss; /* RSS data */
980 int mlx5e_redirect_rqt(struct mlx5e_priv *priv, u32 rqtn, int sz,
981 struct mlx5e_redirect_rqt_param rrp);
982 void mlx5e_build_indir_tir_ctx_hash(struct mlx5e_rss_params *rss_params,
983 const struct mlx5e_tirc_config *ttconfig,
984 void *tirc, bool inner);
985 void mlx5e_modify_tirs_hash(struct mlx5e_priv *priv, void *in);
986 struct mlx5e_tirc_config mlx5e_tirc_get_default_config(enum mlx5e_traffic_types tt);
988 struct mlx5e_xsk_param;
990 struct mlx5e_rq_param;
991 int mlx5e_open_rq(struct mlx5e_channel *c, struct mlx5e_params *params,
992 struct mlx5e_rq_param *param, struct mlx5e_xsk_param *xsk,
993 struct xdp_umem *umem, struct mlx5e_rq *rq);
994 int mlx5e_wait_for_min_rx_wqes(struct mlx5e_rq *rq, int wait_time);
995 void mlx5e_deactivate_rq(struct mlx5e_rq *rq);
996 void mlx5e_close_rq(struct mlx5e_rq *rq);
998 struct mlx5e_sq_param;
999 int mlx5e_open_icosq(struct mlx5e_channel *c, struct mlx5e_params *params,
1000 struct mlx5e_sq_param *param, struct mlx5e_icosq *sq);
1001 void mlx5e_close_icosq(struct mlx5e_icosq *sq);
1002 int mlx5e_open_xdpsq(struct mlx5e_channel *c, struct mlx5e_params *params,
1003 struct mlx5e_sq_param *param, struct xdp_umem *umem,
1004 struct mlx5e_xdpsq *sq, bool is_redirect);
1005 void mlx5e_close_xdpsq(struct mlx5e_xdpsq *sq);
1007 struct mlx5e_cq_param;
1008 int mlx5e_open_cq(struct mlx5e_channel *c, struct dim_cq_moder moder,
1009 struct mlx5e_cq_param *param, struct mlx5e_cq *cq);
1010 void mlx5e_close_cq(struct mlx5e_cq *cq);
1012 int mlx5e_open_locked(struct net_device *netdev);
1013 int mlx5e_close_locked(struct net_device *netdev);
1015 int mlx5e_open_channels(struct mlx5e_priv *priv,
1016 struct mlx5e_channels *chs);
1017 void mlx5e_close_channels(struct mlx5e_channels *chs);
1019 /* Function pointer to be used to modify HW or kernel settings while
1020 * switching channels
1022 typedef int (*mlx5e_fp_preactivate)(struct mlx5e_priv *priv, void *context);
1023 #define MLX5E_DEFINE_PREACTIVATE_WRAPPER_CTX(fn) \
1024 int fn##_ctx(struct mlx5e_priv *priv, void *context) \
1028 int mlx5e_safe_reopen_channels(struct mlx5e_priv *priv);
1029 int mlx5e_safe_switch_channels(struct mlx5e_priv *priv,
1030 struct mlx5e_channels *new_chs,
1031 mlx5e_fp_preactivate preactivate,
1033 int mlx5e_num_channels_changed(struct mlx5e_priv *priv);
1034 int mlx5e_num_channels_changed_ctx(struct mlx5e_priv *priv, void *context);
1035 void mlx5e_activate_priv_channels(struct mlx5e_priv *priv);
1036 void mlx5e_deactivate_priv_channels(struct mlx5e_priv *priv);
1038 void mlx5e_build_default_indir_rqt(u32 *indirection_rqt, int len,
1040 void mlx5e_set_tx_cq_mode_params(struct mlx5e_params *params,
1042 void mlx5e_set_rx_cq_mode_params(struct mlx5e_params *params,
1044 void mlx5e_set_rq_type(struct mlx5_core_dev *mdev, struct mlx5e_params *params);
1045 void mlx5e_init_rq_type_params(struct mlx5_core_dev *mdev,
1046 struct mlx5e_params *params);
1047 int mlx5e_modify_rq_state(struct mlx5e_rq *rq, int curr_state, int next_state);
1048 void mlx5e_activate_rq(struct mlx5e_rq *rq);
1049 void mlx5e_deactivate_rq(struct mlx5e_rq *rq);
1050 void mlx5e_free_rx_descs(struct mlx5e_rq *rq);
1051 void mlx5e_free_rx_in_progress_descs(struct mlx5e_rq *rq);
1052 void mlx5e_activate_icosq(struct mlx5e_icosq *icosq);
1053 void mlx5e_deactivate_icosq(struct mlx5e_icosq *icosq);
1055 int mlx5e_modify_sq(struct mlx5_core_dev *mdev, u32 sqn,
1056 struct mlx5e_modify_sq_param *p);
1057 void mlx5e_activate_txqsq(struct mlx5e_txqsq *sq);
1058 void mlx5e_tx_disable_queue(struct netdev_queue *txq);
1060 static inline bool mlx5_tx_swp_supported(struct mlx5_core_dev *mdev)
1062 return MLX5_CAP_ETH(mdev, swp) &&
1063 MLX5_CAP_ETH(mdev, swp_csum) && MLX5_CAP_ETH(mdev, swp_lso);
1066 extern const struct ethtool_ops mlx5e_ethtool_ops;
1067 #ifdef CONFIG_MLX5_CORE_EN_DCB
1068 extern const struct dcbnl_rtnl_ops mlx5e_dcbnl_ops;
1069 int mlx5e_dcbnl_ieee_setets_core(struct mlx5e_priv *priv, struct ieee_ets *ets);
1070 void mlx5e_dcbnl_initialize(struct mlx5e_priv *priv);
1071 void mlx5e_dcbnl_init_app(struct mlx5e_priv *priv);
1072 void mlx5e_dcbnl_delete_app(struct mlx5e_priv *priv);
1075 int mlx5e_create_tir(struct mlx5_core_dev *mdev, struct mlx5e_tir *tir,
1077 void mlx5e_destroy_tir(struct mlx5_core_dev *mdev,
1078 struct mlx5e_tir *tir);
1079 int mlx5e_create_mdev_resources(struct mlx5_core_dev *mdev);
1080 void mlx5e_destroy_mdev_resources(struct mlx5_core_dev *mdev);
1081 int mlx5e_refresh_tirs(struct mlx5e_priv *priv, bool enable_uc_lb);
1083 /* common netdev helpers */
1084 void mlx5e_create_q_counters(struct mlx5e_priv *priv);
1085 void mlx5e_destroy_q_counters(struct mlx5e_priv *priv);
1086 int mlx5e_open_drop_rq(struct mlx5e_priv *priv,
1087 struct mlx5e_rq *drop_rq);
1088 void mlx5e_close_drop_rq(struct mlx5e_rq *drop_rq);
1090 int mlx5e_create_indirect_rqt(struct mlx5e_priv *priv);
1092 int mlx5e_create_indirect_tirs(struct mlx5e_priv *priv, bool inner_ttc);
1093 void mlx5e_destroy_indirect_tirs(struct mlx5e_priv *priv, bool inner_ttc);
1095 int mlx5e_create_direct_rqts(struct mlx5e_priv *priv, struct mlx5e_tir *tirs);
1096 void mlx5e_destroy_direct_rqts(struct mlx5e_priv *priv, struct mlx5e_tir *tirs);
1097 int mlx5e_create_direct_tirs(struct mlx5e_priv *priv, struct mlx5e_tir *tirs);
1098 void mlx5e_destroy_direct_tirs(struct mlx5e_priv *priv, struct mlx5e_tir *tirs);
1099 void mlx5e_destroy_rqt(struct mlx5e_priv *priv, struct mlx5e_rqt *rqt);
1101 int mlx5e_create_tis(struct mlx5_core_dev *mdev, void *in, u32 *tisn);
1102 void mlx5e_destroy_tis(struct mlx5_core_dev *mdev, u32 tisn);
1104 int mlx5e_create_tises(struct mlx5e_priv *priv);
1105 void mlx5e_destroy_tises(struct mlx5e_priv *priv);
1106 int mlx5e_update_nic_rx(struct mlx5e_priv *priv);
1107 void mlx5e_update_carrier(struct mlx5e_priv *priv);
1108 int mlx5e_close(struct net_device *netdev);
1109 int mlx5e_open(struct net_device *netdev);
1110 void mlx5e_update_ndo_stats(struct mlx5e_priv *priv);
1112 void mlx5e_queue_update_stats(struct mlx5e_priv *priv);
1113 int mlx5e_bits_invert(unsigned long a, int size);
1115 int mlx5e_set_dev_port_mtu(struct mlx5e_priv *priv);
1116 int mlx5e_set_dev_port_mtu_ctx(struct mlx5e_priv *priv, void *context);
1117 int mlx5e_change_mtu(struct net_device *netdev, int new_mtu,
1118 mlx5e_fp_preactivate preactivate);
1120 /* ethtool helpers */
1121 void mlx5e_ethtool_get_drvinfo(struct mlx5e_priv *priv,
1122 struct ethtool_drvinfo *drvinfo);
1123 void mlx5e_ethtool_get_strings(struct mlx5e_priv *priv,
1124 uint32_t stringset, uint8_t *data);
1125 int mlx5e_ethtool_get_sset_count(struct mlx5e_priv *priv, int sset);
1126 void mlx5e_ethtool_get_ethtool_stats(struct mlx5e_priv *priv,
1127 struct ethtool_stats *stats, u64 *data);
1128 void mlx5e_ethtool_get_ringparam(struct mlx5e_priv *priv,
1129 struct ethtool_ringparam *param);
1130 int mlx5e_ethtool_set_ringparam(struct mlx5e_priv *priv,
1131 struct ethtool_ringparam *param);
1132 void mlx5e_ethtool_get_channels(struct mlx5e_priv *priv,
1133 struct ethtool_channels *ch);
1134 int mlx5e_ethtool_set_channels(struct mlx5e_priv *priv,
1135 struct ethtool_channels *ch);
1136 int mlx5e_ethtool_get_coalesce(struct mlx5e_priv *priv,
1137 struct ethtool_coalesce *coal);
1138 int mlx5e_ethtool_set_coalesce(struct mlx5e_priv *priv,
1139 struct ethtool_coalesce *coal);
1140 int mlx5e_ethtool_get_link_ksettings(struct mlx5e_priv *priv,
1141 struct ethtool_link_ksettings *link_ksettings);
1142 int mlx5e_ethtool_set_link_ksettings(struct mlx5e_priv *priv,
1143 const struct ethtool_link_ksettings *link_ksettings);
1144 int mlx5e_get_rxfh(struct net_device *netdev, u32 *indir, u8 *key, u8 *hfunc);
1145 int mlx5e_set_rxfh(struct net_device *dev, const u32 *indir, const u8 *key,
1147 int mlx5e_get_rxnfc(struct net_device *dev, struct ethtool_rxnfc *info,
1149 int mlx5e_set_rxnfc(struct net_device *dev, struct ethtool_rxnfc *cmd);
1150 u32 mlx5e_ethtool_get_rxfh_key_size(struct mlx5e_priv *priv);
1151 u32 mlx5e_ethtool_get_rxfh_indir_size(struct mlx5e_priv *priv);
1152 int mlx5e_ethtool_get_ts_info(struct mlx5e_priv *priv,
1153 struct ethtool_ts_info *info);
1154 int mlx5e_ethtool_flash_device(struct mlx5e_priv *priv,
1155 struct ethtool_flash *flash);
1156 void mlx5e_ethtool_get_pauseparam(struct mlx5e_priv *priv,
1157 struct ethtool_pauseparam *pauseparam);
1158 int mlx5e_ethtool_set_pauseparam(struct mlx5e_priv *priv,
1159 struct ethtool_pauseparam *pauseparam);
1161 /* mlx5e generic netdev management API */
1162 int mlx5e_netdev_init(struct net_device *netdev,
1163 struct mlx5e_priv *priv,
1164 struct mlx5_core_dev *mdev,
1165 const struct mlx5e_profile *profile,
1167 void mlx5e_netdev_cleanup(struct net_device *netdev, struct mlx5e_priv *priv);
1169 mlx5e_create_netdev(struct mlx5_core_dev *mdev, const struct mlx5e_profile *profile,
1170 int nch, void *ppriv);
1171 int mlx5e_attach_netdev(struct mlx5e_priv *priv);
1172 void mlx5e_detach_netdev(struct mlx5e_priv *priv);
1173 void mlx5e_destroy_netdev(struct mlx5e_priv *priv);
1174 void mlx5e_set_netdev_mtu_boundaries(struct mlx5e_priv *priv);
1175 void mlx5e_build_nic_params(struct mlx5e_priv *priv,
1176 struct mlx5e_xsk *xsk,
1177 struct mlx5e_rss_params *rss_params,
1178 struct mlx5e_params *params,
1180 void mlx5e_build_rq_params(struct mlx5_core_dev *mdev,
1181 struct mlx5e_params *params);
1182 void mlx5e_build_rss_params(struct mlx5e_rss_params *rss_params,
1184 void mlx5e_rx_dim_work(struct work_struct *work);
1185 void mlx5e_tx_dim_work(struct work_struct *work);
1187 void mlx5e_add_vxlan_port(struct net_device *netdev, struct udp_tunnel_info *ti);
1188 void mlx5e_del_vxlan_port(struct net_device *netdev, struct udp_tunnel_info *ti);
1189 netdev_features_t mlx5e_features_check(struct sk_buff *skb,
1190 struct net_device *netdev,
1191 netdev_features_t features);
1192 int mlx5e_set_features(struct net_device *netdev, netdev_features_t features);
1193 #ifdef CONFIG_MLX5_ESWITCH
1194 int mlx5e_set_vf_mac(struct net_device *dev, int vf, u8 *mac);
1195 int mlx5e_set_vf_rate(struct net_device *dev, int vf, int min_tx_rate, int max_tx_rate);
1196 int mlx5e_get_vf_config(struct net_device *dev, int vf, struct ifla_vf_info *ivi);
1197 int mlx5e_get_vf_stats(struct net_device *dev, int vf, struct ifla_vf_stats *vf_stats);
1199 #endif /* __MLX5_EN_H__ */