2 * Copyright (c) 2018, Mellanox Technologies. All rights reserved.
4 * This software is available to you under a choice of one of two
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6 * General Public License (GPL) Version 2, available from the file
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8 * OpenIB.org BSD license below:
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11 * without modification, are permitted provided that the following
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15 * copyright notice, this list of conditions and the following
18 * - Redistributions in binary form must reproduce the above
19 * copyright notice, this list of conditions and the following
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21 * provided with the distribution.
23 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
24 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
25 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
26 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
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29 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
33 #include <linux/bpf_trace.h>
34 #include <net/xdp_sock_drv.h>
36 #include "en/params.h"
38 int mlx5e_xdp_max_mtu(struct mlx5e_params *params, struct mlx5e_xsk_param *xsk)
40 int hr = mlx5e_get_linear_rq_headroom(params, xsk);
42 /* Let S := SKB_DATA_ALIGN(sizeof(struct skb_shared_info)).
43 * The condition checked in mlx5e_rx_is_linear_skb is:
44 * SKB_DATA_ALIGN(sw_mtu + hard_mtu + hr) + S <= PAGE_SIZE (1)
45 * (Note that hw_mtu == sw_mtu + hard_mtu.)
46 * What is returned from this function is:
47 * max_mtu = PAGE_SIZE - S - hr - hard_mtu (2)
48 * After assigning sw_mtu := max_mtu, the left side of (1) turns to
49 * SKB_DATA_ALIGN(PAGE_SIZE - S) + S, which is equal to PAGE_SIZE,
50 * because both PAGE_SIZE and S are already aligned. Any number greater
51 * than max_mtu would make the left side of (1) greater than PAGE_SIZE,
52 * so max_mtu is the maximum MTU allowed.
55 return MLX5E_HW2SW_MTU(params, SKB_MAX_HEAD(hr));
59 mlx5e_xmit_xdp_buff(struct mlx5e_xdpsq *sq, struct mlx5e_rq *rq,
60 struct mlx5e_dma_info *di, struct xdp_buff *xdp)
62 struct mlx5e_xdp_xmit_data xdptxd;
63 struct mlx5e_xdp_info xdpi;
64 struct xdp_frame *xdpf;
67 xdpf = convert_to_xdp_frame(xdp);
71 xdptxd.data = xdpf->data;
72 xdptxd.len = xdpf->len;
74 if (xdp->rxq->mem.type == MEM_TYPE_XSK_BUFF_POOL) {
75 /* The xdp_buff was in the UMEM and was copied into a newly
76 * allocated page. The UMEM page was returned via the ZCA, and
77 * this new page has to be mapped at this point and has to be
78 * unmapped and returned via xdp_return_frame on completion.
81 /* Prevent double recycling of the UMEM page. Even in case this
82 * function returns false, the xdp_buff shouldn't be recycled,
83 * as it was already done in xdp_convert_zc_to_xdp_frame.
85 __set_bit(MLX5E_RQ_FLAG_XDP_XMIT, rq->flags); /* non-atomic */
87 xdpi.mode = MLX5E_XDP_XMIT_MODE_FRAME;
89 dma_addr = dma_map_single(sq->pdev, xdptxd.data, xdptxd.len,
91 if (dma_mapping_error(sq->pdev, dma_addr)) {
92 xdp_return_frame(xdpf);
96 xdptxd.dma_addr = dma_addr;
97 xdpi.frame.xdpf = xdpf;
98 xdpi.frame.dma_addr = dma_addr;
100 /* Driver assumes that convert_to_xdp_frame returns an xdp_frame
101 * that points to the same memory region as the original
102 * xdp_buff. It allows to map the memory only once and to use
103 * the DMA_BIDIRECTIONAL mode.
106 xdpi.mode = MLX5E_XDP_XMIT_MODE_PAGE;
108 dma_addr = di->addr + (xdpf->data - (void *)xdpf);
109 dma_sync_single_for_device(sq->pdev, dma_addr, xdptxd.len,
112 xdptxd.dma_addr = dma_addr;
117 return sq->xmit_xdp_frame(sq, &xdptxd, &xdpi, 0);
120 /* returns true if packet was consumed by xdp */
121 bool mlx5e_xdp_handle(struct mlx5e_rq *rq, struct mlx5e_dma_info *di,
122 u32 *len, struct xdp_buff *xdp)
124 struct bpf_prog *prog = READ_ONCE(rq->xdp_prog);
131 act = bpf_prog_run_xdp(prog, xdp);
134 *len = xdp->data_end - xdp->data;
137 if (unlikely(!mlx5e_xmit_xdp_buff(rq->xdpsq, rq, di, xdp)))
139 __set_bit(MLX5E_RQ_FLAG_XDP_XMIT, rq->flags); /* non-atomic */
142 /* When XDP enabled then page-refcnt==1 here */
143 err = xdp_do_redirect(rq->netdev, xdp, prog);
146 __set_bit(MLX5E_RQ_FLAG_XDP_XMIT, rq->flags);
147 __set_bit(MLX5E_RQ_FLAG_XDP_REDIRECT, rq->flags);
148 if (xdp->rxq->mem.type != MEM_TYPE_XSK_BUFF_POOL)
149 mlx5e_page_dma_unmap(rq, di);
150 rq->stats->xdp_redirect++;
153 bpf_warn_invalid_xdp_action(act);
157 trace_xdp_exception(rq->netdev, prog, act);
160 rq->stats->xdp_drop++;
165 static u16 mlx5e_xdpsq_get_next_pi(struct mlx5e_xdpsq *sq, u16 size)
167 struct mlx5_wq_cyc *wq = &sq->wq;
168 u16 pi, contig_wqebbs;
170 pi = mlx5_wq_cyc_ctr2ix(wq, sq->pc);
171 contig_wqebbs = mlx5_wq_cyc_get_contig_wqebbs(wq, pi);
172 if (unlikely(contig_wqebbs < size)) {
173 struct mlx5e_xdp_wqe_info *wi, *edge_wi;
175 wi = &sq->db.wqe_info[pi];
176 edge_wi = wi + contig_wqebbs;
178 /* Fill SQ frag edge with NOPs to avoid WQE wrapping two pages. */
179 for (; wi < edge_wi; wi++) {
180 *wi = (struct mlx5e_xdp_wqe_info) {
184 mlx5e_post_nop(wq, sq->sqn, &sq->pc);
186 sq->stats->nops += contig_wqebbs;
188 pi = mlx5_wq_cyc_ctr2ix(wq, sq->pc);
194 static void mlx5e_xdp_mpwqe_session_start(struct mlx5e_xdpsq *sq)
196 struct mlx5e_xdp_mpwqe *session = &sq->mpwqe;
197 struct mlx5e_xdpsq_stats *stats = sq->stats;
200 pi = mlx5e_xdpsq_get_next_pi(sq, MLX5_SEND_WQE_MAX_WQEBBS);
201 session->wqe = MLX5E_TX_FETCH_WQE(sq, pi);
203 prefetchw(session->wqe->data);
204 session->ds_count = MLX5E_XDP_TX_EMPTY_DS_COUNT;
205 session->pkt_count = 0;
207 mlx5e_xdp_update_inline_state(sq);
212 void mlx5e_xdp_mpwqe_complete(struct mlx5e_xdpsq *sq)
214 struct mlx5_wq_cyc *wq = &sq->wq;
215 struct mlx5e_xdp_mpwqe *session = &sq->mpwqe;
216 struct mlx5_wqe_ctrl_seg *cseg = &session->wqe->ctrl;
217 u16 ds_count = session->ds_count;
218 u16 pi = mlx5_wq_cyc_ctr2ix(wq, sq->pc);
219 struct mlx5e_xdp_wqe_info *wi = &sq->db.wqe_info[pi];
221 cseg->opmod_idx_opcode =
222 cpu_to_be32((sq->pc << 8) | MLX5_OPCODE_ENHANCED_MPSW);
223 cseg->qpn_ds = cpu_to_be32((sq->sqn << 8) | ds_count);
225 wi->num_wqebbs = DIV_ROUND_UP(ds_count, MLX5_SEND_WQEBB_NUM_DS);
226 wi->num_pkts = session->pkt_count;
228 sq->pc += wi->num_wqebbs;
230 sq->doorbell_cseg = cseg;
232 session->wqe = NULL; /* Close session */
236 MLX5E_XDP_CHECK_OK = 1,
237 MLX5E_XDP_CHECK_START_MPWQE = 2,
240 static int mlx5e_xmit_xdp_frame_check_mpwqe(struct mlx5e_xdpsq *sq)
242 if (unlikely(!sq->mpwqe.wqe)) {
243 if (unlikely(!mlx5e_wqc_has_room_for(&sq->wq, sq->cc, sq->pc,
244 MLX5E_XDPSQ_STOP_ROOM))) {
245 /* SQ is full, ring doorbell */
246 mlx5e_xmit_xdp_doorbell(sq);
251 return MLX5E_XDP_CHECK_START_MPWQE;
254 return MLX5E_XDP_CHECK_OK;
257 static bool mlx5e_xmit_xdp_frame_mpwqe(struct mlx5e_xdpsq *sq,
258 struct mlx5e_xdp_xmit_data *xdptxd,
259 struct mlx5e_xdp_info *xdpi,
262 struct mlx5e_xdp_mpwqe *session = &sq->mpwqe;
263 struct mlx5e_xdpsq_stats *stats = sq->stats;
265 if (unlikely(xdptxd->len > sq->hw_mtu)) {
271 check_result = mlx5e_xmit_xdp_frame_check_mpwqe(sq);
272 if (unlikely(check_result < 0))
275 if (check_result == MLX5E_XDP_CHECK_START_MPWQE) {
276 /* Start the session when nothing can fail, so it's guaranteed
277 * that if there is an active session, it has at least one dseg,
278 * and it's safe to complete it at any time.
280 mlx5e_xdp_mpwqe_session_start(sq);
283 mlx5e_xdp_mpwqe_add_dseg(sq, xdptxd, stats);
285 if (unlikely(mlx5e_xdp_no_room_for_inline_pkt(session) ||
286 session->ds_count == MLX5E_XDP_MPW_MAX_NUM_DS))
287 mlx5e_xdp_mpwqe_complete(sq);
289 mlx5e_xdpi_fifo_push(&sq->db.xdpi_fifo, xdpi);
294 static int mlx5e_xmit_xdp_frame_check(struct mlx5e_xdpsq *sq)
296 if (unlikely(!mlx5e_wqc_has_room_for(&sq->wq, sq->cc, sq->pc, 1))) {
297 /* SQ is full, ring doorbell */
298 mlx5e_xmit_xdp_doorbell(sq);
303 return MLX5E_XDP_CHECK_OK;
306 static bool mlx5e_xmit_xdp_frame(struct mlx5e_xdpsq *sq,
307 struct mlx5e_xdp_xmit_data *xdptxd,
308 struct mlx5e_xdp_info *xdpi,
311 struct mlx5_wq_cyc *wq = &sq->wq;
312 u16 pi = mlx5_wq_cyc_ctr2ix(wq, sq->pc);
313 struct mlx5e_tx_wqe *wqe = mlx5_wq_cyc_get_wqe(wq, pi);
315 struct mlx5_wqe_ctrl_seg *cseg = &wqe->ctrl;
316 struct mlx5_wqe_eth_seg *eseg = &wqe->eth;
317 struct mlx5_wqe_data_seg *dseg = wqe->data;
319 dma_addr_t dma_addr = xdptxd->dma_addr;
320 u32 dma_len = xdptxd->len;
322 struct mlx5e_xdpsq_stats *stats = sq->stats;
326 if (unlikely(dma_len < MLX5E_XDP_MIN_INLINE || sq->hw_mtu < dma_len)) {
332 check_result = mlx5e_xmit_xdp_frame_check(sq);
333 if (unlikely(check_result < 0))
338 /* copy the inline part if required */
339 if (sq->min_inline_mode != MLX5_INLINE_MODE_NONE) {
340 memcpy(eseg->inline_hdr.start, xdptxd->data, MLX5E_XDP_MIN_INLINE);
341 eseg->inline_hdr.sz = cpu_to_be16(MLX5E_XDP_MIN_INLINE);
342 dma_len -= MLX5E_XDP_MIN_INLINE;
343 dma_addr += MLX5E_XDP_MIN_INLINE;
347 /* write the dma part */
348 dseg->addr = cpu_to_be64(dma_addr);
349 dseg->byte_count = cpu_to_be32(dma_len);
351 cseg->opmod_idx_opcode = cpu_to_be32((sq->pc << 8) | MLX5_OPCODE_SEND);
355 sq->doorbell_cseg = cseg;
357 mlx5e_xdpi_fifo_push(&sq->db.xdpi_fifo, xdpi);
362 static void mlx5e_free_xdpsq_desc(struct mlx5e_xdpsq *sq,
363 struct mlx5e_xdp_wqe_info *wi,
367 struct mlx5e_xdp_info_fifo *xdpi_fifo = &sq->db.xdpi_fifo;
370 for (i = 0; i < wi->num_pkts; i++) {
371 struct mlx5e_xdp_info xdpi = mlx5e_xdpi_fifo_pop(xdpi_fifo);
374 case MLX5E_XDP_XMIT_MODE_FRAME:
375 /* XDP_TX from the XSK RQ and XDP_REDIRECT */
376 dma_unmap_single(sq->pdev, xdpi.frame.dma_addr,
377 xdpi.frame.xdpf->len, DMA_TO_DEVICE);
378 xdp_return_frame(xdpi.frame.xdpf);
380 case MLX5E_XDP_XMIT_MODE_PAGE:
381 /* XDP_TX from the regular RQ */
382 mlx5e_page_release_dynamic(xdpi.page.rq, &xdpi.page.di, recycle);
384 case MLX5E_XDP_XMIT_MODE_XSK:
394 bool mlx5e_poll_xdpsq_cq(struct mlx5e_cq *cq)
396 struct mlx5e_xdpsq *sq;
397 struct mlx5_cqe64 *cqe;
402 sq = container_of(cq, struct mlx5e_xdpsq, cq);
404 if (unlikely(!test_bit(MLX5E_SQ_STATE_ENABLED, &sq->state)))
407 cqe = mlx5_cqwq_get_cqe(&cq->wq);
411 /* sq->cc must be updated only after mlx5_cqwq_update_db_record(),
412 * otherwise a cq overrun may occur
418 struct mlx5e_xdp_wqe_info *wi;
422 mlx5_cqwq_pop(&cq->wq);
424 wqe_counter = be16_to_cpu(cqe->wqe_counter);
427 last_wqe = (sqcc == wqe_counter);
428 ci = mlx5_wq_cyc_ctr2ix(&sq->wq, sqcc);
429 wi = &sq->db.wqe_info[ci];
431 sqcc += wi->num_wqebbs;
433 mlx5e_free_xdpsq_desc(sq, wi, &xsk_frames, true);
436 if (unlikely(get_cqe_opcode(cqe) != MLX5_CQE_REQ)) {
437 netdev_WARN_ONCE(sq->channel->netdev,
438 "Bad OP in XDPSQ CQE: 0x%x\n",
439 get_cqe_opcode(cqe));
440 mlx5e_dump_error_cqe(&sq->cq, sq->sqn,
441 (struct mlx5_err_cqe *)cqe);
442 mlx5_wq_cyc_wqe_dump(&sq->wq, ci, wi->num_wqebbs);
444 } while ((++i < MLX5E_TX_CQ_POLL_BUDGET) && (cqe = mlx5_cqwq_get_cqe(&cq->wq)));
447 xsk_umem_complete_tx(sq->umem, xsk_frames);
449 sq->stats->cqes += i;
451 mlx5_cqwq_update_db_record(&cq->wq);
453 /* ensure cq space is freed before enabling more cqes */
457 return (i == MLX5E_TX_CQ_POLL_BUDGET);
460 void mlx5e_free_xdpsq_descs(struct mlx5e_xdpsq *sq)
464 while (sq->cc != sq->pc) {
465 struct mlx5e_xdp_wqe_info *wi;
468 ci = mlx5_wq_cyc_ctr2ix(&sq->wq, sq->cc);
469 wi = &sq->db.wqe_info[ci];
471 sq->cc += wi->num_wqebbs;
473 mlx5e_free_xdpsq_desc(sq, wi, &xsk_frames, false);
477 xsk_umem_complete_tx(sq->umem, xsk_frames);
480 int mlx5e_xdp_xmit(struct net_device *dev, int n, struct xdp_frame **frames,
483 struct mlx5e_priv *priv = netdev_priv(dev);
484 struct mlx5e_xdpsq *sq;
489 /* this flag is sufficient, no need to test internal sq state */
490 if (unlikely(!mlx5e_xdp_tx_is_enabled(priv)))
493 if (unlikely(flags & ~XDP_XMIT_FLAGS_MASK))
496 sq_num = smp_processor_id();
498 if (unlikely(sq_num >= priv->channels.num))
501 sq = &priv->channels.c[sq_num]->xdpsq;
503 for (i = 0; i < n; i++) {
504 struct xdp_frame *xdpf = frames[i];
505 struct mlx5e_xdp_xmit_data xdptxd;
506 struct mlx5e_xdp_info xdpi;
508 xdptxd.data = xdpf->data;
509 xdptxd.len = xdpf->len;
510 xdptxd.dma_addr = dma_map_single(sq->pdev, xdptxd.data,
511 xdptxd.len, DMA_TO_DEVICE);
513 if (unlikely(dma_mapping_error(sq->pdev, xdptxd.dma_addr))) {
514 xdp_return_frame_rx_napi(xdpf);
519 xdpi.mode = MLX5E_XDP_XMIT_MODE_FRAME;
520 xdpi.frame.xdpf = xdpf;
521 xdpi.frame.dma_addr = xdptxd.dma_addr;
523 if (unlikely(!sq->xmit_xdp_frame(sq, &xdptxd, &xdpi, 0))) {
524 dma_unmap_single(sq->pdev, xdptxd.dma_addr,
525 xdptxd.len, DMA_TO_DEVICE);
526 xdp_return_frame_rx_napi(xdpf);
531 if (flags & XDP_XMIT_FLUSH) {
533 mlx5e_xdp_mpwqe_complete(sq);
534 mlx5e_xmit_xdp_doorbell(sq);
540 void mlx5e_xdp_rx_poll_complete(struct mlx5e_rq *rq)
542 struct mlx5e_xdpsq *xdpsq = rq->xdpsq;
544 if (xdpsq->mpwqe.wqe)
545 mlx5e_xdp_mpwqe_complete(xdpsq);
547 mlx5e_xmit_xdp_doorbell(xdpsq);
549 if (test_bit(MLX5E_RQ_FLAG_XDP_REDIRECT, rq->flags)) {
551 __clear_bit(MLX5E_RQ_FLAG_XDP_REDIRECT, rq->flags);
555 void mlx5e_set_xmit_fp(struct mlx5e_xdpsq *sq, bool is_mpw)
557 sq->xmit_xdp_frame_check = is_mpw ?
558 mlx5e_xmit_xdp_frame_check_mpwqe : mlx5e_xmit_xdp_frame_check;
559 sq->xmit_xdp_frame = is_mpw ?
560 mlx5e_xmit_xdp_frame_mpwqe : mlx5e_xmit_xdp_frame;