1 /* SPDX-License-Identifier: GPL-2.0 OR Linux-OpenIB */
2 /* Copyright (c) 2019 Mellanox Technologies. */
4 #ifndef __MLX5_EN_TXRX_H___
5 #define __MLX5_EN_TXRX_H___
8 #include <linux/indirect_call_wrapper.h>
10 #define MLX5E_TX_WQE_EMPTY_DS_COUNT (sizeof(struct mlx5e_tx_wqe) / MLX5_SEND_WQE_DS)
12 /* The mult of MLX5_SEND_WQE_MAX_WQEBBS * MLX5_SEND_WQEBB_NUM_DS
13 * (16 * 4 == 64) does not fit in the 6-bit DS field of Ctrl Segment.
14 * We use a bound lower that MLX5_SEND_WQE_MAX_WQEBBS to let a
15 * full-session WQE be cache-aligned.
17 #if L1_CACHE_BYTES < 128
18 #define MLX5E_TX_MPW_MAX_WQEBBS (MLX5_SEND_WQE_MAX_WQEBBS - 1)
20 #define MLX5E_TX_MPW_MAX_WQEBBS (MLX5_SEND_WQE_MAX_WQEBBS - 2)
23 #define MLX5E_TX_MPW_MAX_NUM_DS (MLX5E_TX_MPW_MAX_WQEBBS * MLX5_SEND_WQEBB_NUM_DS)
25 #define INL_HDR_START_SZ (sizeof(((struct mlx5_wqe_eth_seg *)NULL)->inline_hdr.start))
27 #define MLX5E_RX_ERR_CQE(cqe) (get_cqe_opcode(cqe) != MLX5_CQE_RESP_SEND)
29 enum mlx5e_icosq_wqe_type {
31 MLX5E_ICOSQ_WQE_UMR_RX,
32 #ifdef CONFIG_MLX5_EN_TLS
33 MLX5E_ICOSQ_WQE_UMR_TLS,
34 MLX5E_ICOSQ_WQE_SET_PSV_TLS,
35 MLX5E_ICOSQ_WQE_GET_PSV_TLS,
40 static inline bool mlx5e_skb_is_multicast(struct sk_buff *skb)
42 return skb->pkt_type == PACKET_MULTICAST || skb->pkt_type == PACKET_BROADCAST;
45 void mlx5e_trigger_irq(struct mlx5e_icosq *sq);
46 void mlx5e_completion_event(struct mlx5_core_cq *mcq, struct mlx5_eqe *eqe);
47 void mlx5e_cq_error_event(struct mlx5_core_cq *mcq, enum mlx5_event event);
48 int mlx5e_napi_poll(struct napi_struct *napi, int budget);
49 int mlx5e_poll_ico_cq(struct mlx5e_cq *cq);
52 void mlx5e_page_dma_unmap(struct mlx5e_rq *rq, struct mlx5e_dma_info *dma_info);
53 void mlx5e_page_release_dynamic(struct mlx5e_rq *rq,
54 struct mlx5e_dma_info *dma_info,
56 INDIRECT_CALLABLE_DECLARE(bool mlx5e_post_rx_wqes(struct mlx5e_rq *rq));
57 INDIRECT_CALLABLE_DECLARE(bool mlx5e_post_rx_mpwqes(struct mlx5e_rq *rq));
58 int mlx5e_poll_rx_cq(struct mlx5e_cq *cq, int budget);
59 void mlx5e_free_rx_descs(struct mlx5e_rq *rq);
60 void mlx5e_free_rx_in_progress_descs(struct mlx5e_rq *rq);
63 u16 mlx5e_select_queue(struct net_device *dev, struct sk_buff *skb,
64 struct net_device *sb_dev);
65 netdev_tx_t mlx5e_xmit(struct sk_buff *skb, struct net_device *dev);
66 bool mlx5e_poll_tx_cq(struct mlx5e_cq *cq, int napi_budget);
67 void mlx5e_free_txqsq_descs(struct mlx5e_txqsq *sq);
70 mlx5e_wqc_has_room_for(struct mlx5_wq_cyc *wq, u16 cc, u16 pc, u16 n)
72 return (mlx5_wq_cyc_ctr2ix(wq, cc - pc) >= n) || (cc == pc);
75 static inline void *mlx5e_fetch_wqe(struct mlx5_wq_cyc *wq, u16 pi, size_t wqe_size)
79 wqe = mlx5_wq_cyc_get_wqe(wq, pi);
80 memset(wqe, 0, wqe_size);
85 #define MLX5E_TX_FETCH_WQE(sq, pi) \
86 ((struct mlx5e_tx_wqe *)mlx5e_fetch_wqe(&(sq)->wq, pi, sizeof(struct mlx5e_tx_wqe)))
88 static inline struct mlx5e_tx_wqe *
89 mlx5e_post_nop(struct mlx5_wq_cyc *wq, u32 sqn, u16 *pc)
91 u16 pi = mlx5_wq_cyc_ctr2ix(wq, *pc);
92 struct mlx5e_tx_wqe *wqe = mlx5_wq_cyc_get_wqe(wq, pi);
93 struct mlx5_wqe_ctrl_seg *cseg = &wqe->ctrl;
95 memset(cseg, 0, sizeof(*cseg));
97 cseg->opmod_idx_opcode = cpu_to_be32((*pc << 8) | MLX5_OPCODE_NOP);
98 cseg->qpn_ds = cpu_to_be32((sqn << 8) | 0x01);
105 static inline struct mlx5e_tx_wqe *
106 mlx5e_post_nop_fence(struct mlx5_wq_cyc *wq, u32 sqn, u16 *pc)
108 u16 pi = mlx5_wq_cyc_ctr2ix(wq, *pc);
109 struct mlx5e_tx_wqe *wqe = mlx5_wq_cyc_get_wqe(wq, pi);
110 struct mlx5_wqe_ctrl_seg *cseg = &wqe->ctrl;
112 memset(cseg, 0, sizeof(*cseg));
114 cseg->opmod_idx_opcode = cpu_to_be32((*pc << 8) | MLX5_OPCODE_NOP);
115 cseg->qpn_ds = cpu_to_be32((sqn << 8) | 0x01);
116 cseg->fm_ce_se = MLX5_FENCE_MODE_INITIATOR_SMALL;
123 struct mlx5e_tx_wqe_info {
129 #ifdef CONFIG_MLX5_EN_TLS
130 struct page *resync_dump_frag_page;
134 static inline u16 mlx5e_txqsq_get_next_pi(struct mlx5e_txqsq *sq, u16 size)
136 struct mlx5_wq_cyc *wq = &sq->wq;
137 u16 pi, contig_wqebbs;
139 pi = mlx5_wq_cyc_ctr2ix(wq, sq->pc);
140 contig_wqebbs = mlx5_wq_cyc_get_contig_wqebbs(wq, pi);
141 if (unlikely(contig_wqebbs < size)) {
142 struct mlx5e_tx_wqe_info *wi, *edge_wi;
144 wi = &sq->db.wqe_info[pi];
145 edge_wi = wi + contig_wqebbs;
147 /* Fill SQ frag edge with NOPs to avoid WQE wrapping two pages. */
148 for (; wi < edge_wi; wi++) {
149 *wi = (struct mlx5e_tx_wqe_info) {
152 mlx5e_post_nop(wq, sq->sqn, &sq->pc);
154 sq->stats->nop += contig_wqebbs;
156 pi = mlx5_wq_cyc_ctr2ix(wq, sq->pc);
162 struct mlx5e_icosq_wqe_info {
166 /* Auxiliary data for different wqe types. */
171 #ifdef CONFIG_MLX5_EN_TLS
173 struct mlx5e_ktls_offload_context_rx *priv_rx;
176 struct mlx5e_ktls_rx_resync_buf *buf;
182 void mlx5e_free_icosq_descs(struct mlx5e_icosq *sq);
184 static inline u16 mlx5e_icosq_get_next_pi(struct mlx5e_icosq *sq, u16 size)
186 struct mlx5_wq_cyc *wq = &sq->wq;
187 u16 pi, contig_wqebbs;
189 pi = mlx5_wq_cyc_ctr2ix(wq, sq->pc);
190 contig_wqebbs = mlx5_wq_cyc_get_contig_wqebbs(wq, pi);
191 if (unlikely(contig_wqebbs < size)) {
192 struct mlx5e_icosq_wqe_info *wi, *edge_wi;
194 wi = &sq->db.wqe_info[pi];
195 edge_wi = wi + contig_wqebbs;
197 /* Fill SQ frag edge with NOPs to avoid WQE wrapping two pages. */
198 for (; wi < edge_wi; wi++) {
199 *wi = (struct mlx5e_icosq_wqe_info) {
200 .wqe_type = MLX5E_ICOSQ_WQE_NOP,
203 mlx5e_post_nop(wq, sq->sqn, &sq->pc);
206 pi = mlx5_wq_cyc_ctr2ix(wq, sq->pc);
213 mlx5e_notify_hw(struct mlx5_wq_cyc *wq, u16 pc, void __iomem *uar_map,
214 struct mlx5_wqe_ctrl_seg *ctrl)
216 ctrl->fm_ce_se |= MLX5_WQE_CTRL_CQ_UPDATE;
217 /* ensure wqe is visible to device before updating doorbell record */
220 *wq->db = cpu_to_be32(pc);
222 /* ensure doorbell record is visible to device before ringing the
227 mlx5_write64((__be32 *)ctrl, uar_map);
230 static inline void mlx5e_cq_arm(struct mlx5e_cq *cq)
232 struct mlx5_core_cq *mcq;
235 mlx5_cq_arm(mcq, MLX5_CQ_DB_REQ_NOT, mcq->uar->map, cq->wq.cc);
238 static inline struct mlx5e_sq_dma *
239 mlx5e_dma_get(struct mlx5e_txqsq *sq, u32 i)
241 return &sq->db.dma_fifo[i & sq->dma_fifo_mask];
245 mlx5e_dma_push(struct mlx5e_txqsq *sq, dma_addr_t addr, u32 size,
246 enum mlx5e_dma_map_type map_type)
248 struct mlx5e_sq_dma *dma = mlx5e_dma_get(sq, sq->dma_fifo_pc++);
252 dma->type = map_type;
256 struct sk_buff **mlx5e_skb_fifo_get(struct mlx5e_skb_fifo *fifo, u16 i)
258 return &fifo->fifo[i & fifo->mask];
262 void mlx5e_skb_fifo_push(struct mlx5e_skb_fifo *fifo, struct sk_buff *skb)
264 struct sk_buff **skb_item = mlx5e_skb_fifo_get(fifo, (*fifo->pc)++);
270 struct sk_buff *mlx5e_skb_fifo_pop(struct mlx5e_skb_fifo *fifo)
272 return *mlx5e_skb_fifo_get(fifo, (*fifo->cc)++);
276 mlx5e_tx_dma_unmap(struct device *pdev, struct mlx5e_sq_dma *dma)
279 case MLX5E_DMA_MAP_SINGLE:
280 dma_unmap_single(pdev, dma->addr, dma->size, DMA_TO_DEVICE);
282 case MLX5E_DMA_MAP_PAGE:
283 dma_unmap_page(pdev, dma->addr, dma->size, DMA_TO_DEVICE);
286 WARN_ONCE(true, "mlx5e_tx_dma_unmap unknown DMA type!\n");
290 void mlx5e_sq_xmit_simple(struct mlx5e_txqsq *sq, struct sk_buff *skb, bool xmit_more);
291 void mlx5e_tx_mpwqe_ensure_complete(struct mlx5e_txqsq *sq);
293 static inline bool mlx5e_tx_mpwqe_is_full(struct mlx5e_tx_mpwqe *session)
295 return session->ds_count == MLX5E_TX_MPW_MAX_NUM_DS;
298 static inline void mlx5e_rqwq_reset(struct mlx5e_rq *rq)
300 if (rq->wq_type == MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ) {
301 mlx5_wq_ll_reset(&rq->mpwqe.wq);
302 rq->mpwqe.actual_wq_head = 0;
304 mlx5_wq_cyc_reset(&rq->wqe.wq);
308 static inline void mlx5e_dump_error_cqe(struct mlx5e_cq *cq, u32 qn,
309 struct mlx5_err_cqe *err_cqe)
311 struct mlx5_cqwq *wq = &cq->wq;
314 ci = mlx5_cqwq_ctr2ix(wq, wq->cc - 1);
316 netdev_err(cq->netdev,
317 "Error cqe on cqn 0x%x, ci 0x%x, qn 0x%x, opcode 0x%x, syndrome 0x%x, vendor syndrome 0x%x\n",
319 get_cqe_opcode((struct mlx5_cqe64 *)err_cqe),
320 err_cqe->syndrome, err_cqe->vendor_err_synd);
321 mlx5_dump_err_cqe(cq->mdev, err_cqe);
324 static inline u32 mlx5e_rqwq_get_size(struct mlx5e_rq *rq)
326 switch (rq->wq_type) {
327 case MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ:
328 return mlx5_wq_ll_get_size(&rq->mpwqe.wq);
330 return mlx5_wq_cyc_get_size(&rq->wqe.wq);
334 static inline u32 mlx5e_rqwq_get_cur_sz(struct mlx5e_rq *rq)
336 switch (rq->wq_type) {
337 case MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ:
338 return rq->mpwqe.wq.cur_sz;
340 return rq->wqe.wq.cur_sz;
344 static inline u16 mlx5e_rqwq_get_head(struct mlx5e_rq *rq)
346 switch (rq->wq_type) {
347 case MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ:
348 return mlx5_wq_ll_get_head(&rq->mpwqe.wq);
350 return mlx5_wq_cyc_get_head(&rq->wqe.wq);
354 static inline u16 mlx5e_rqwq_get_wqe_counter(struct mlx5e_rq *rq)
356 switch (rq->wq_type) {
357 case MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ:
358 return mlx5_wq_ll_get_counter(&rq->mpwqe.wq);
360 return mlx5_wq_cyc_get_counter(&rq->wqe.wq);
364 /* SW parser related functions */
366 struct mlx5e_swp_spec {
375 mlx5e_set_eseg_swp(struct sk_buff *skb, struct mlx5_wqe_eth_seg *eseg,
376 struct mlx5e_swp_spec *swp_spec)
378 /* SWP offsets are in 2-bytes words */
379 eseg->swp_outer_l3_offset = skb_network_offset(skb) / 2;
380 if (swp_spec->l3_proto == htons(ETH_P_IPV6))
381 eseg->swp_flags |= MLX5_ETH_WQE_SWP_OUTER_L3_IPV6;
382 if (swp_spec->l4_proto) {
383 eseg->swp_outer_l4_offset = skb_transport_offset(skb) / 2;
384 if (swp_spec->l4_proto == IPPROTO_UDP)
385 eseg->swp_flags |= MLX5_ETH_WQE_SWP_OUTER_L4_UDP;
388 if (swp_spec->is_tun) {
389 eseg->swp_inner_l3_offset = skb_inner_network_offset(skb) / 2;
390 if (swp_spec->tun_l3_proto == htons(ETH_P_IPV6))
391 eseg->swp_flags |= MLX5_ETH_WQE_SWP_INNER_L3_IPV6;
392 } else { /* typically for ipsec when xfrm mode != XFRM_MODE_TUNNEL */
393 eseg->swp_inner_l3_offset = skb_network_offset(skb) / 2;
394 if (swp_spec->l3_proto == htons(ETH_P_IPV6))
395 eseg->swp_flags |= MLX5_ETH_WQE_SWP_INNER_L3_IPV6;
397 switch (swp_spec->tun_l4_proto) {
399 eseg->swp_flags |= MLX5_ETH_WQE_SWP_INNER_L4_UDP;
402 eseg->swp_inner_l4_offset = skb_inner_transport_offset(skb) / 2;
407 static inline u16 mlx5e_stop_room_for_wqe(u16 wqe_size)
409 BUILD_BUG_ON(PAGE_SIZE / MLX5_SEND_WQE_BB < MLX5_SEND_WQE_MAX_WQEBBS);
411 /* A WQE must not cross the page boundary, hence two conditions:
412 * 1. Its size must not exceed the page size.
413 * 2. If the WQE size is X, and the space remaining in a page is less
414 * than X, this space needs to be padded with NOPs. So, one WQE of
415 * size X may require up to X-1 WQEBBs of padding, which makes the
416 * stop room of X-1 + X.
417 * WQE size is also limited by the hardware limit.
420 if (__builtin_constant_p(wqe_size))
421 BUILD_BUG_ON(wqe_size > MLX5_SEND_WQE_MAX_WQEBBS);
423 WARN_ON_ONCE(wqe_size > MLX5_SEND_WQE_MAX_WQEBBS);
425 return wqe_size * 2 - 1;