1 // SPDX-License-Identifier: GPL-2.0 OR Linux-OpenIB
2 // Copyright (c) 2020 Mellanox Technologies
7 #include "en/fs_tt_redirect.h"
10 struct mlx5_flow_handle *l2_rule;
11 struct mlx5_flow_handle *udp_v4_rule;
12 struct mlx5_flow_handle *udp_v6_rule;
16 #define MLX5E_PTP_CHANNEL_IX 0
18 struct mlx5e_ptp_params {
19 struct mlx5e_params params;
20 struct mlx5e_sq_param txq_sq_param;
21 struct mlx5e_rq_param rq_param;
24 struct mlx5e_skb_cb_hwtstamp {
26 ktime_t port_hwtstamp;
29 void mlx5e_skb_cb_hwtstamp_init(struct sk_buff *skb)
31 memset(skb->cb, 0, sizeof(struct mlx5e_skb_cb_hwtstamp));
34 static struct mlx5e_skb_cb_hwtstamp *mlx5e_skb_cb_get_hwts(struct sk_buff *skb)
36 BUILD_BUG_ON(sizeof(struct mlx5e_skb_cb_hwtstamp) > sizeof(skb->cb));
37 return (struct mlx5e_skb_cb_hwtstamp *)skb->cb;
40 static void mlx5e_skb_cb_hwtstamp_tx(struct sk_buff *skb,
41 struct mlx5e_ptp_cq_stats *cq_stats)
43 struct skb_shared_hwtstamps hwts = {};
46 diff = abs(mlx5e_skb_cb_get_hwts(skb)->port_hwtstamp -
47 mlx5e_skb_cb_get_hwts(skb)->cqe_hwtstamp);
49 /* Maximal allowed diff is 1 / 128 second */
50 if (diff > (NSEC_PER_SEC >> 7)) {
52 cq_stats->abort_abs_diff_ns += diff;
56 hwts.hwtstamp = mlx5e_skb_cb_get_hwts(skb)->port_hwtstamp;
57 skb_tstamp_tx(skb, &hwts);
60 void mlx5e_skb_cb_hwtstamp_handler(struct sk_buff *skb, int hwtstamp_type,
62 struct mlx5e_ptp_cq_stats *cq_stats)
64 switch (hwtstamp_type) {
65 case (MLX5E_SKB_CB_CQE_HWTSTAMP):
66 mlx5e_skb_cb_get_hwts(skb)->cqe_hwtstamp = hwtstamp;
68 case (MLX5E_SKB_CB_PORT_HWTSTAMP):
69 mlx5e_skb_cb_get_hwts(skb)->port_hwtstamp = hwtstamp;
73 /* If both CQEs arrive, check and report the port tstamp, and clear skb cb as
74 * skb soon to be released.
76 if (!mlx5e_skb_cb_get_hwts(skb)->cqe_hwtstamp ||
77 !mlx5e_skb_cb_get_hwts(skb)->port_hwtstamp)
80 mlx5e_skb_cb_hwtstamp_tx(skb, cq_stats);
81 memset(skb->cb, 0, sizeof(struct mlx5e_skb_cb_hwtstamp));
84 static void mlx5e_ptp_handle_ts_cqe(struct mlx5e_ptpsq *ptpsq,
85 struct mlx5_cqe64 *cqe,
88 struct sk_buff *skb = mlx5e_skb_fifo_pop(&ptpsq->skb_fifo);
89 struct mlx5e_txqsq *sq = &ptpsq->txqsq;
92 if (unlikely(MLX5E_RX_ERR_CQE(cqe))) {
93 ptpsq->cq_stats->err_cqe++;
97 hwtstamp = mlx5e_cqe_ts_to_ns(sq->ptp_cyc2time, sq->clock, get_cqe_ts(cqe));
98 mlx5e_skb_cb_hwtstamp_handler(skb, MLX5E_SKB_CB_PORT_HWTSTAMP,
99 hwtstamp, ptpsq->cq_stats);
100 ptpsq->cq_stats->cqe++;
103 napi_consume_skb(skb, budget);
106 static bool mlx5e_ptp_poll_ts_cq(struct mlx5e_cq *cq, int budget)
108 struct mlx5e_ptpsq *ptpsq = container_of(cq, struct mlx5e_ptpsq, ts_cq);
109 struct mlx5_cqwq *cqwq = &cq->wq;
110 struct mlx5_cqe64 *cqe;
113 if (unlikely(!test_bit(MLX5E_SQ_STATE_ENABLED, &ptpsq->txqsq.state)))
116 cqe = mlx5_cqwq_get_cqe(cqwq);
123 mlx5e_ptp_handle_ts_cqe(ptpsq, cqe, budget);
124 } while ((++work_done < budget) && (cqe = mlx5_cqwq_get_cqe(cqwq)));
126 mlx5_cqwq_update_db_record(cqwq);
128 /* ensure cq space is freed before enabling more cqes */
131 return work_done == budget;
134 static int mlx5e_ptp_napi_poll(struct napi_struct *napi, int budget)
136 struct mlx5e_ptp *c = container_of(napi, struct mlx5e_ptp, napi);
137 struct mlx5e_ch_stats *ch_stats = c->stats;
138 struct mlx5e_rq *rq = &c->rq;
147 if (test_bit(MLX5E_PTP_STATE_TX, c->state)) {
148 for (i = 0; i < c->num_tc; i++) {
149 busy |= mlx5e_poll_tx_cq(&c->ptpsq[i].txqsq.cq, budget);
150 busy |= mlx5e_ptp_poll_ts_cq(&c->ptpsq[i].ts_cq, budget);
153 if (test_bit(MLX5E_PTP_STATE_RX, c->state) && likely(budget)) {
154 work_done = mlx5e_poll_rx_cq(&rq->cq, budget);
155 busy |= work_done == budget;
156 busy |= INDIRECT_CALL_2(rq->post_wqes,
157 mlx5e_post_rx_mpwqes,
167 if (unlikely(!napi_complete_done(napi, work_done)))
172 if (test_bit(MLX5E_PTP_STATE_TX, c->state)) {
173 for (i = 0; i < c->num_tc; i++) {
174 mlx5e_cq_arm(&c->ptpsq[i].txqsq.cq);
175 mlx5e_cq_arm(&c->ptpsq[i].ts_cq);
178 if (test_bit(MLX5E_PTP_STATE_RX, c->state))
179 mlx5e_cq_arm(&rq->cq);
187 static int mlx5e_ptp_alloc_txqsq(struct mlx5e_ptp *c, int txq_ix,
188 struct mlx5e_params *params,
189 struct mlx5e_sq_param *param,
190 struct mlx5e_txqsq *sq, int tc,
191 struct mlx5e_ptpsq *ptpsq)
193 void *sqc_wq = MLX5_ADDR_OF(sqc, param->sqc, wq);
194 struct mlx5_core_dev *mdev = c->mdev;
195 struct mlx5_wq_cyc *wq = &sq->wq;
200 sq->tstamp = c->tstamp;
201 sq->clock = &mdev->clock;
202 sq->mkey_be = c->mkey_be;
203 sq->netdev = c->netdev;
206 sq->ch_ix = MLX5E_PTP_CHANNEL_IX;
208 sq->uar_map = mdev->mlx5e_res.hw_objs.bfreg.map;
209 sq->min_inline_mode = params->tx_min_inline_mode;
210 sq->hw_mtu = MLX5E_SW2HW_MTU(params, params->sw_mtu);
211 sq->stats = &c->priv->ptp_stats.sq[tc];
213 INIT_WORK(&sq->recover_work, mlx5e_tx_err_cqe_work);
214 if (!MLX5_CAP_ETH(mdev, wqe_vlan_insert))
215 set_bit(MLX5E_SQ_STATE_VLAN_NEED_L2_INLINE, &sq->state);
216 sq->stop_room = param->stop_room;
217 sq->ptp_cyc2time = mlx5_sq_ts_translator(mdev);
219 node = dev_to_node(mlx5_core_dma_dev(mdev));
221 param->wq.db_numa_node = node;
222 err = mlx5_wq_cyc_create(mdev, ¶m->wq, sqc_wq, wq, &sq->wq_ctrl);
225 wq->db = &wq->db[MLX5_SND_DBR];
227 err = mlx5e_alloc_txqsq_db(sq, node);
229 goto err_sq_wq_destroy;
234 mlx5_wq_destroy(&sq->wq_ctrl);
239 static void mlx5e_ptp_destroy_sq(struct mlx5_core_dev *mdev, u32 sqn)
241 mlx5_core_destroy_sq(mdev, sqn);
244 static int mlx5e_ptp_alloc_traffic_db(struct mlx5e_ptpsq *ptpsq, int numa)
246 int wq_sz = mlx5_wq_cyc_get_size(&ptpsq->txqsq.wq);
248 ptpsq->skb_fifo.fifo = kvzalloc_node(array_size(wq_sz, sizeof(*ptpsq->skb_fifo.fifo)),
250 if (!ptpsq->skb_fifo.fifo)
253 ptpsq->skb_fifo.pc = &ptpsq->skb_fifo_pc;
254 ptpsq->skb_fifo.cc = &ptpsq->skb_fifo_cc;
255 ptpsq->skb_fifo.mask = wq_sz - 1;
260 static void mlx5e_ptp_drain_skb_fifo(struct mlx5e_skb_fifo *skb_fifo)
262 while (*skb_fifo->pc != *skb_fifo->cc) {
263 struct sk_buff *skb = mlx5e_skb_fifo_pop(skb_fifo);
265 dev_kfree_skb_any(skb);
269 static void mlx5e_ptp_free_traffic_db(struct mlx5e_skb_fifo *skb_fifo)
271 mlx5e_ptp_drain_skb_fifo(skb_fifo);
272 kvfree(skb_fifo->fifo);
275 static int mlx5e_ptp_open_txqsq(struct mlx5e_ptp *c, u32 tisn,
276 int txq_ix, struct mlx5e_ptp_params *cparams,
277 int tc, struct mlx5e_ptpsq *ptpsq)
279 struct mlx5e_sq_param *sqp = &cparams->txq_sq_param;
280 struct mlx5e_txqsq *txqsq = &ptpsq->txqsq;
281 struct mlx5e_create_sq_param csp = {};
284 err = mlx5e_ptp_alloc_txqsq(c, txq_ix, &cparams->params, sqp,
291 csp.cqn = txqsq->cq.mcq.cqn;
292 csp.wq_ctrl = &txqsq->wq_ctrl;
293 csp.min_inline_mode = txqsq->min_inline_mode;
294 csp.ts_cqe_to_dest_cqn = ptpsq->ts_cq.mcq.cqn;
296 err = mlx5e_create_sq_rdy(c->mdev, sqp, &csp, 0, &txqsq->sqn);
300 err = mlx5e_ptp_alloc_traffic_db(ptpsq,
301 dev_to_node(mlx5_core_dma_dev(c->mdev)));
308 mlx5e_free_txqsq(txqsq);
313 static void mlx5e_ptp_close_txqsq(struct mlx5e_ptpsq *ptpsq)
315 struct mlx5e_txqsq *sq = &ptpsq->txqsq;
316 struct mlx5_core_dev *mdev = sq->mdev;
318 mlx5e_ptp_free_traffic_db(&ptpsq->skb_fifo);
319 cancel_work_sync(&sq->recover_work);
320 mlx5e_ptp_destroy_sq(mdev, sq->sqn);
321 mlx5e_free_txqsq_descs(sq);
322 mlx5e_free_txqsq(sq);
325 static int mlx5e_ptp_open_txqsqs(struct mlx5e_ptp *c,
326 struct mlx5e_ptp_params *cparams)
328 struct mlx5e_params *params = &cparams->params;
333 ix_base = params->num_tc * params->num_channels;
335 for (tc = 0; tc < params->num_tc; tc++) {
336 int txq_ix = ix_base + tc;
338 err = mlx5e_ptp_open_txqsq(c, c->priv->tisn[c->lag_port][tc], txq_ix,
339 cparams, tc, &c->ptpsq[tc]);
347 for (--tc; tc >= 0; tc--)
348 mlx5e_ptp_close_txqsq(&c->ptpsq[tc]);
353 static void mlx5e_ptp_close_txqsqs(struct mlx5e_ptp *c)
357 for (tc = 0; tc < c->num_tc; tc++)
358 mlx5e_ptp_close_txqsq(&c->ptpsq[tc]);
361 static int mlx5e_ptp_open_tx_cqs(struct mlx5e_ptp *c,
362 struct mlx5e_ptp_params *cparams)
364 struct mlx5e_params *params = &cparams->params;
365 struct mlx5e_create_cq_param ccp = {};
366 struct dim_cq_moder ptp_moder = {};
367 struct mlx5e_cq_param *cq_param;
371 ccp.node = dev_to_node(mlx5_core_dma_dev(c->mdev));
372 ccp.ch_stats = c->stats;
374 ccp.ix = MLX5E_PTP_CHANNEL_IX;
376 cq_param = &cparams->txq_sq_param.cqp;
378 for (tc = 0; tc < params->num_tc; tc++) {
379 struct mlx5e_cq *cq = &c->ptpsq[tc].txqsq.cq;
381 err = mlx5e_open_cq(c->priv, ptp_moder, cq_param, &ccp, cq);
383 goto out_err_txqsq_cq;
386 for (tc = 0; tc < params->num_tc; tc++) {
387 struct mlx5e_cq *cq = &c->ptpsq[tc].ts_cq;
388 struct mlx5e_ptpsq *ptpsq = &c->ptpsq[tc];
390 err = mlx5e_open_cq(c->priv, ptp_moder, cq_param, &ccp, cq);
394 ptpsq->cq_stats = &c->priv->ptp_stats.cq[tc];
400 for (--tc; tc >= 0; tc--)
401 mlx5e_close_cq(&c->ptpsq[tc].ts_cq);
404 for (--tc; tc >= 0; tc--)
405 mlx5e_close_cq(&c->ptpsq[tc].txqsq.cq);
410 static int mlx5e_ptp_open_rx_cq(struct mlx5e_ptp *c,
411 struct mlx5e_ptp_params *cparams)
413 struct mlx5e_create_cq_param ccp = {};
414 struct dim_cq_moder ptp_moder = {};
415 struct mlx5e_cq_param *cq_param;
416 struct mlx5e_cq *cq = &c->rq.cq;
418 ccp.node = dev_to_node(mlx5_core_dma_dev(c->mdev));
419 ccp.ch_stats = c->stats;
421 ccp.ix = MLX5E_PTP_CHANNEL_IX;
423 cq_param = &cparams->rq_param.cqp;
425 return mlx5e_open_cq(c->priv, ptp_moder, cq_param, &ccp, cq);
428 static void mlx5e_ptp_close_tx_cqs(struct mlx5e_ptp *c)
432 for (tc = 0; tc < c->num_tc; tc++)
433 mlx5e_close_cq(&c->ptpsq[tc].ts_cq);
435 for (tc = 0; tc < c->num_tc; tc++)
436 mlx5e_close_cq(&c->ptpsq[tc].txqsq.cq);
439 static void mlx5e_ptp_build_sq_param(struct mlx5_core_dev *mdev,
440 struct mlx5e_params *params,
441 struct mlx5e_sq_param *param)
443 void *sqc = param->sqc;
446 mlx5e_build_sq_param_common(mdev, param);
448 wq = MLX5_ADDR_OF(sqc, sqc, wq);
449 MLX5_SET(wq, wq, log_wq_sz, params->log_sq_size);
450 param->stop_room = mlx5e_stop_room_for_wqe(MLX5_SEND_WQE_MAX_WQEBBS);
451 mlx5e_build_tx_cq_param(mdev, params, ¶m->cqp);
454 static void mlx5e_ptp_build_rq_param(struct mlx5_core_dev *mdev,
455 struct net_device *netdev,
457 struct mlx5e_ptp_params *ptp_params)
459 struct mlx5e_rq_param *rq_params = &ptp_params->rq_param;
460 struct mlx5e_params *params = &ptp_params->params;
462 params->rq_wq_type = MLX5_WQ_TYPE_CYCLIC;
463 mlx5e_init_rq_type_params(mdev, params);
464 params->sw_mtu = netdev->max_mtu;
465 mlx5e_build_rq_param(mdev, params, NULL, q_counter, rq_params);
468 static void mlx5e_ptp_build_params(struct mlx5e_ptp *c,
469 struct mlx5e_ptp_params *cparams,
470 struct mlx5e_params *orig)
472 struct mlx5e_params *params = &cparams->params;
474 params->tx_min_inline_mode = orig->tx_min_inline_mode;
475 params->num_channels = orig->num_channels;
476 params->hard_mtu = orig->hard_mtu;
477 params->sw_mtu = orig->sw_mtu;
478 params->num_tc = orig->num_tc;
481 if (test_bit(MLX5E_PTP_STATE_TX, c->state)) {
482 params->log_sq_size = orig->log_sq_size;
483 mlx5e_ptp_build_sq_param(c->mdev, params, &cparams->txq_sq_param);
485 if (test_bit(MLX5E_PTP_STATE_RX, c->state))
486 mlx5e_ptp_build_rq_param(c->mdev, c->netdev, c->priv->q_counter, cparams);
489 static int mlx5e_init_ptp_rq(struct mlx5e_ptp *c, struct mlx5e_params *params,
492 struct mlx5_core_dev *mdev = c->mdev;
493 struct mlx5e_priv *priv = c->priv;
496 rq->wq_type = params->rq_wq_type;
497 rq->pdev = mdev->device;
498 rq->netdev = priv->netdev;
500 rq->clock = &mdev->clock;
501 rq->tstamp = &priv->tstamp;
503 rq->hw_mtu = MLX5E_SW2HW_MTU(params, params->sw_mtu);
504 rq->stats = &c->priv->ptp_stats.rq;
505 rq->ptp_cyc2time = mlx5_rq_ts_translator(mdev);
506 err = mlx5e_rq_set_handlers(rq, params, false);
510 return xdp_rxq_info_reg(&rq->xdp_rxq, rq->netdev, rq->ix, 0);
513 static int mlx5e_ptp_open_rq(struct mlx5e_ptp *c, struct mlx5e_params *params,
514 struct mlx5e_rq_param *rq_param)
516 int node = dev_to_node(c->mdev->device);
519 err = mlx5e_init_ptp_rq(c, params, &c->rq);
523 return mlx5e_open_rq(params, rq_param, NULL, node, &c->rq);
526 static int mlx5e_ptp_open_queues(struct mlx5e_ptp *c,
527 struct mlx5e_ptp_params *cparams)
531 if (test_bit(MLX5E_PTP_STATE_TX, c->state)) {
532 err = mlx5e_ptp_open_tx_cqs(c, cparams);
536 err = mlx5e_ptp_open_txqsqs(c, cparams);
540 if (test_bit(MLX5E_PTP_STATE_RX, c->state)) {
541 err = mlx5e_ptp_open_rx_cq(c, cparams);
545 err = mlx5e_ptp_open_rq(c, &cparams->params, &cparams->rq_param);
552 if (test_bit(MLX5E_PTP_STATE_RX, c->state))
553 mlx5e_close_cq(&c->rq.cq);
555 if (test_bit(MLX5E_PTP_STATE_TX, c->state))
556 mlx5e_ptp_close_txqsqs(c);
558 if (test_bit(MLX5E_PTP_STATE_TX, c->state))
559 mlx5e_ptp_close_tx_cqs(c);
564 static void mlx5e_ptp_close_queues(struct mlx5e_ptp *c)
566 if (test_bit(MLX5E_PTP_STATE_RX, c->state)) {
567 mlx5e_close_rq(&c->rq);
568 mlx5e_close_cq(&c->rq.cq);
570 if (test_bit(MLX5E_PTP_STATE_TX, c->state)) {
571 mlx5e_ptp_close_txqsqs(c);
572 mlx5e_ptp_close_tx_cqs(c);
576 static int mlx5e_ptp_set_state(struct mlx5e_ptp *c, struct mlx5e_params *params)
578 if (MLX5E_GET_PFLAG(params, MLX5E_PFLAG_TX_PORT_TS))
579 __set_bit(MLX5E_PTP_STATE_TX, c->state);
582 __set_bit(MLX5E_PTP_STATE_RX, c->state);
584 return bitmap_empty(c->state, MLX5E_PTP_STATE_NUM_STATES) ? -EINVAL : 0;
587 static void mlx5e_ptp_rx_unset_fs(struct mlx5e_priv *priv)
589 struct mlx5e_ptp_fs *ptp_fs = priv->fs.ptp_fs;
594 mlx5e_fs_tt_redirect_del_rule(ptp_fs->l2_rule);
595 mlx5e_fs_tt_redirect_any_destroy(priv);
597 mlx5e_fs_tt_redirect_del_rule(ptp_fs->udp_v6_rule);
598 mlx5e_fs_tt_redirect_del_rule(ptp_fs->udp_v4_rule);
599 mlx5e_fs_tt_redirect_udp_destroy(priv);
600 ptp_fs->valid = false;
603 static int mlx5e_ptp_rx_set_fs(struct mlx5e_priv *priv)
605 struct mlx5e_ptp_fs *ptp_fs = priv->fs.ptp_fs;
606 struct mlx5_flow_handle *rule;
607 u32 tirn = priv->ptp_tir.tirn;
613 err = mlx5e_fs_tt_redirect_udp_create(priv);
617 rule = mlx5e_fs_tt_redirect_udp_add_rule(priv, MLX5E_TT_IPV4_UDP,
621 goto out_destroy_fs_udp;
623 ptp_fs->udp_v4_rule = rule;
625 rule = mlx5e_fs_tt_redirect_udp_add_rule(priv, MLX5E_TT_IPV6_UDP,
629 goto out_destroy_udp_v4_rule;
631 ptp_fs->udp_v6_rule = rule;
633 err = mlx5e_fs_tt_redirect_any_create(priv);
635 goto out_destroy_udp_v6_rule;
637 rule = mlx5e_fs_tt_redirect_any_add_rule(priv, tirn, ETH_P_1588);
640 goto out_destroy_fs_any;
642 ptp_fs->l2_rule = rule;
643 ptp_fs->valid = true;
648 mlx5e_fs_tt_redirect_any_destroy(priv);
649 out_destroy_udp_v6_rule:
650 mlx5e_fs_tt_redirect_del_rule(ptp_fs->udp_v6_rule);
651 out_destroy_udp_v4_rule:
652 mlx5e_fs_tt_redirect_del_rule(ptp_fs->udp_v4_rule);
654 mlx5e_fs_tt_redirect_udp_destroy(priv);
659 int mlx5e_ptp_open(struct mlx5e_priv *priv, struct mlx5e_params *params,
660 u8 lag_port, struct mlx5e_ptp **cp)
662 struct net_device *netdev = priv->netdev;
663 struct mlx5_core_dev *mdev = priv->mdev;
664 struct mlx5e_ptp_params *cparams;
669 c = kvzalloc_node(sizeof(*c), GFP_KERNEL, dev_to_node(mlx5_core_dma_dev(mdev)));
670 cparams = kvzalloc(sizeof(*cparams), GFP_KERNEL);
675 c->mdev = priv->mdev;
676 c->tstamp = &priv->tstamp;
677 c->pdev = mlx5_core_dma_dev(priv->mdev);
678 c->netdev = priv->netdev;
679 c->mkey_be = cpu_to_be32(priv->mdev->mlx5e_res.hw_objs.mkey.key);
680 c->num_tc = params->num_tc;
681 c->stats = &priv->ptp_stats.ch;
682 c->lag_port = lag_port;
684 err = mlx5e_ptp_set_state(c, params);
688 netif_napi_add(netdev, &c->napi, mlx5e_ptp_napi_poll, 64);
690 mlx5e_ptp_build_params(c, cparams, params);
692 err = mlx5e_ptp_open_queues(c, cparams);
696 if (test_bit(MLX5E_PTP_STATE_RX, c->state))
697 priv->rx_ptp_opened = true;
706 netif_napi_del(&c->napi);
713 void mlx5e_ptp_close(struct mlx5e_ptp *c)
715 mlx5e_ptp_close_queues(c);
716 netif_napi_del(&c->napi);
721 void mlx5e_ptp_activate_channel(struct mlx5e_ptp *c)
725 napi_enable(&c->napi);
727 if (test_bit(MLX5E_PTP_STATE_TX, c->state)) {
728 for (tc = 0; tc < c->num_tc; tc++)
729 mlx5e_activate_txqsq(&c->ptpsq[tc].txqsq);
731 if (test_bit(MLX5E_PTP_STATE_RX, c->state)) {
732 mlx5e_ptp_rx_set_fs(c->priv);
733 mlx5e_activate_rq(&c->rq);
737 void mlx5e_ptp_deactivate_channel(struct mlx5e_ptp *c)
741 if (test_bit(MLX5E_PTP_STATE_RX, c->state))
742 mlx5e_deactivate_rq(&c->rq);
744 if (test_bit(MLX5E_PTP_STATE_TX, c->state)) {
745 for (tc = 0; tc < c->num_tc; tc++)
746 mlx5e_deactivate_txqsq(&c->ptpsq[tc].txqsq);
749 napi_disable(&c->napi);
752 int mlx5e_ptp_get_rqn(struct mlx5e_ptp *c, u32 *rqn)
754 if (!c || !test_bit(MLX5E_PTP_STATE_RX, c->state))
761 int mlx5e_ptp_alloc_rx_fs(struct mlx5e_priv *priv)
763 struct mlx5e_ptp_fs *ptp_fs;
765 if (!priv->profile->rx_ptp_support)
768 ptp_fs = kzalloc(sizeof(*ptp_fs), GFP_KERNEL);
772 priv->fs.ptp_fs = ptp_fs;
776 void mlx5e_ptp_free_rx_fs(struct mlx5e_priv *priv)
778 struct mlx5e_ptp_fs *ptp_fs = priv->fs.ptp_fs;
780 if (!priv->profile->rx_ptp_support)
783 mlx5e_ptp_rx_unset_fs(priv);
787 int mlx5e_ptp_rx_manage_fs(struct mlx5e_priv *priv, bool set)
789 struct mlx5e_ptp *c = priv->channels.ptp;
791 if (!priv->profile->rx_ptp_support)
794 if (!test_bit(MLX5E_STATE_OPENED, &priv->state))
798 if (!c || !test_bit(MLX5E_PTP_STATE_RX, c->state)) {
799 netdev_WARN_ONCE(priv->netdev, "Don't try to add PTP RX-FS rules");
802 return mlx5e_ptp_rx_set_fs(priv);
805 if (c && test_bit(MLX5E_PTP_STATE_RX, c->state)) {
806 netdev_WARN_ONCE(priv->netdev, "Don't try to remove PTP RX-FS rules");
809 mlx5e_ptp_rx_unset_fs(priv);