1 // SPDX-License-Identifier: GPL-2.0 OR Linux-OpenIB
2 // Copyright (c) 2020 Mellanox Technologies
8 #define MLX5E_PTP_CHANNEL_IX 0
10 struct mlx5e_ptp_params {
11 struct mlx5e_params params;
12 struct mlx5e_sq_param txq_sq_param;
13 struct mlx5e_rq_param rq_param;
16 struct mlx5e_skb_cb_hwtstamp {
18 ktime_t port_hwtstamp;
21 void mlx5e_skb_cb_hwtstamp_init(struct sk_buff *skb)
23 memset(skb->cb, 0, sizeof(struct mlx5e_skb_cb_hwtstamp));
26 static struct mlx5e_skb_cb_hwtstamp *mlx5e_skb_cb_get_hwts(struct sk_buff *skb)
28 BUILD_BUG_ON(sizeof(struct mlx5e_skb_cb_hwtstamp) > sizeof(skb->cb));
29 return (struct mlx5e_skb_cb_hwtstamp *)skb->cb;
32 static void mlx5e_skb_cb_hwtstamp_tx(struct sk_buff *skb,
33 struct mlx5e_ptp_cq_stats *cq_stats)
35 struct skb_shared_hwtstamps hwts = {};
38 diff = abs(mlx5e_skb_cb_get_hwts(skb)->port_hwtstamp -
39 mlx5e_skb_cb_get_hwts(skb)->cqe_hwtstamp);
41 /* Maximal allowed diff is 1 / 128 second */
42 if (diff > (NSEC_PER_SEC >> 7)) {
44 cq_stats->abort_abs_diff_ns += diff;
48 hwts.hwtstamp = mlx5e_skb_cb_get_hwts(skb)->port_hwtstamp;
49 skb_tstamp_tx(skb, &hwts);
52 void mlx5e_skb_cb_hwtstamp_handler(struct sk_buff *skb, int hwtstamp_type,
54 struct mlx5e_ptp_cq_stats *cq_stats)
56 switch (hwtstamp_type) {
57 case (MLX5E_SKB_CB_CQE_HWTSTAMP):
58 mlx5e_skb_cb_get_hwts(skb)->cqe_hwtstamp = hwtstamp;
60 case (MLX5E_SKB_CB_PORT_HWTSTAMP):
61 mlx5e_skb_cb_get_hwts(skb)->port_hwtstamp = hwtstamp;
65 /* If both CQEs arrive, check and report the port tstamp, and clear skb cb as
66 * skb soon to be released.
68 if (!mlx5e_skb_cb_get_hwts(skb)->cqe_hwtstamp ||
69 !mlx5e_skb_cb_get_hwts(skb)->port_hwtstamp)
72 mlx5e_skb_cb_hwtstamp_tx(skb, cq_stats);
73 memset(skb->cb, 0, sizeof(struct mlx5e_skb_cb_hwtstamp));
76 static void mlx5e_ptp_handle_ts_cqe(struct mlx5e_ptpsq *ptpsq,
77 struct mlx5_cqe64 *cqe,
80 struct sk_buff *skb = mlx5e_skb_fifo_pop(&ptpsq->skb_fifo);
81 struct mlx5e_txqsq *sq = &ptpsq->txqsq;
84 if (unlikely(MLX5E_RX_ERR_CQE(cqe))) {
85 ptpsq->cq_stats->err_cqe++;
89 hwtstamp = mlx5e_cqe_ts_to_ns(sq->ptp_cyc2time, sq->clock, get_cqe_ts(cqe));
90 mlx5e_skb_cb_hwtstamp_handler(skb, MLX5E_SKB_CB_PORT_HWTSTAMP,
91 hwtstamp, ptpsq->cq_stats);
92 ptpsq->cq_stats->cqe++;
95 napi_consume_skb(skb, budget);
98 static bool mlx5e_ptp_poll_ts_cq(struct mlx5e_cq *cq, int budget)
100 struct mlx5e_ptpsq *ptpsq = container_of(cq, struct mlx5e_ptpsq, ts_cq);
101 struct mlx5_cqwq *cqwq = &cq->wq;
102 struct mlx5_cqe64 *cqe;
105 if (unlikely(!test_bit(MLX5E_SQ_STATE_ENABLED, &ptpsq->txqsq.state)))
108 cqe = mlx5_cqwq_get_cqe(cqwq);
115 mlx5e_ptp_handle_ts_cqe(ptpsq, cqe, budget);
116 } while ((++work_done < budget) && (cqe = mlx5_cqwq_get_cqe(cqwq)));
118 mlx5_cqwq_update_db_record(cqwq);
120 /* ensure cq space is freed before enabling more cqes */
123 return work_done == budget;
126 static int mlx5e_ptp_napi_poll(struct napi_struct *napi, int budget)
128 struct mlx5e_ptp *c = container_of(napi, struct mlx5e_ptp, napi);
129 struct mlx5e_ch_stats *ch_stats = c->stats;
130 struct mlx5e_rq *rq = &c->rq;
139 if (test_bit(MLX5E_PTP_STATE_TX, c->state)) {
140 for (i = 0; i < c->num_tc; i++) {
141 busy |= mlx5e_poll_tx_cq(&c->ptpsq[i].txqsq.cq, budget);
142 busy |= mlx5e_ptp_poll_ts_cq(&c->ptpsq[i].ts_cq, budget);
145 if (test_bit(MLX5E_PTP_STATE_RX, c->state) && likely(budget)) {
146 work_done = mlx5e_poll_rx_cq(&rq->cq, budget);
147 busy |= work_done == budget;
148 busy |= INDIRECT_CALL_2(rq->post_wqes,
149 mlx5e_post_rx_mpwqes,
159 if (unlikely(!napi_complete_done(napi, work_done)))
164 if (test_bit(MLX5E_PTP_STATE_TX, c->state)) {
165 for (i = 0; i < c->num_tc; i++) {
166 mlx5e_cq_arm(&c->ptpsq[i].txqsq.cq);
167 mlx5e_cq_arm(&c->ptpsq[i].ts_cq);
170 if (test_bit(MLX5E_PTP_STATE_RX, c->state))
171 mlx5e_cq_arm(&rq->cq);
179 static int mlx5e_ptp_alloc_txqsq(struct mlx5e_ptp *c, int txq_ix,
180 struct mlx5e_params *params,
181 struct mlx5e_sq_param *param,
182 struct mlx5e_txqsq *sq, int tc,
183 struct mlx5e_ptpsq *ptpsq)
185 void *sqc_wq = MLX5_ADDR_OF(sqc, param->sqc, wq);
186 struct mlx5_core_dev *mdev = c->mdev;
187 struct mlx5_wq_cyc *wq = &sq->wq;
192 sq->tstamp = c->tstamp;
193 sq->clock = &mdev->clock;
194 sq->mkey_be = c->mkey_be;
195 sq->netdev = c->netdev;
198 sq->ch_ix = MLX5E_PTP_CHANNEL_IX;
200 sq->uar_map = mdev->mlx5e_res.hw_objs.bfreg.map;
201 sq->min_inline_mode = params->tx_min_inline_mode;
202 sq->hw_mtu = MLX5E_SW2HW_MTU(params, params->sw_mtu);
203 sq->stats = &c->priv->ptp_stats.sq[tc];
205 INIT_WORK(&sq->recover_work, mlx5e_tx_err_cqe_work);
206 if (!MLX5_CAP_ETH(mdev, wqe_vlan_insert))
207 set_bit(MLX5E_SQ_STATE_VLAN_NEED_L2_INLINE, &sq->state);
208 sq->stop_room = param->stop_room;
209 sq->ptp_cyc2time = mlx5_sq_ts_translator(mdev);
211 node = dev_to_node(mlx5_core_dma_dev(mdev));
213 param->wq.db_numa_node = node;
214 err = mlx5_wq_cyc_create(mdev, ¶m->wq, sqc_wq, wq, &sq->wq_ctrl);
217 wq->db = &wq->db[MLX5_SND_DBR];
219 err = mlx5e_alloc_txqsq_db(sq, node);
221 goto err_sq_wq_destroy;
226 mlx5_wq_destroy(&sq->wq_ctrl);
231 static void mlx5e_ptp_destroy_sq(struct mlx5_core_dev *mdev, u32 sqn)
233 mlx5_core_destroy_sq(mdev, sqn);
236 static int mlx5e_ptp_alloc_traffic_db(struct mlx5e_ptpsq *ptpsq, int numa)
238 int wq_sz = mlx5_wq_cyc_get_size(&ptpsq->txqsq.wq);
240 ptpsq->skb_fifo.fifo = kvzalloc_node(array_size(wq_sz, sizeof(*ptpsq->skb_fifo.fifo)),
242 if (!ptpsq->skb_fifo.fifo)
245 ptpsq->skb_fifo.pc = &ptpsq->skb_fifo_pc;
246 ptpsq->skb_fifo.cc = &ptpsq->skb_fifo_cc;
247 ptpsq->skb_fifo.mask = wq_sz - 1;
252 static void mlx5e_ptp_drain_skb_fifo(struct mlx5e_skb_fifo *skb_fifo)
254 while (*skb_fifo->pc != *skb_fifo->cc) {
255 struct sk_buff *skb = mlx5e_skb_fifo_pop(skb_fifo);
257 dev_kfree_skb_any(skb);
261 static void mlx5e_ptp_free_traffic_db(struct mlx5e_skb_fifo *skb_fifo)
263 mlx5e_ptp_drain_skb_fifo(skb_fifo);
264 kvfree(skb_fifo->fifo);
267 static int mlx5e_ptp_open_txqsq(struct mlx5e_ptp *c, u32 tisn,
268 int txq_ix, struct mlx5e_ptp_params *cparams,
269 int tc, struct mlx5e_ptpsq *ptpsq)
271 struct mlx5e_sq_param *sqp = &cparams->txq_sq_param;
272 struct mlx5e_txqsq *txqsq = &ptpsq->txqsq;
273 struct mlx5e_create_sq_param csp = {};
276 err = mlx5e_ptp_alloc_txqsq(c, txq_ix, &cparams->params, sqp,
283 csp.cqn = txqsq->cq.mcq.cqn;
284 csp.wq_ctrl = &txqsq->wq_ctrl;
285 csp.min_inline_mode = txqsq->min_inline_mode;
286 csp.ts_cqe_to_dest_cqn = ptpsq->ts_cq.mcq.cqn;
288 err = mlx5e_create_sq_rdy(c->mdev, sqp, &csp, 0, &txqsq->sqn);
292 err = mlx5e_ptp_alloc_traffic_db(ptpsq,
293 dev_to_node(mlx5_core_dma_dev(c->mdev)));
300 mlx5e_free_txqsq(txqsq);
305 static void mlx5e_ptp_close_txqsq(struct mlx5e_ptpsq *ptpsq)
307 struct mlx5e_txqsq *sq = &ptpsq->txqsq;
308 struct mlx5_core_dev *mdev = sq->mdev;
310 mlx5e_ptp_free_traffic_db(&ptpsq->skb_fifo);
311 cancel_work_sync(&sq->recover_work);
312 mlx5e_ptp_destroy_sq(mdev, sq->sqn);
313 mlx5e_free_txqsq_descs(sq);
314 mlx5e_free_txqsq(sq);
317 static int mlx5e_ptp_open_txqsqs(struct mlx5e_ptp *c,
318 struct mlx5e_ptp_params *cparams)
320 struct mlx5e_params *params = &cparams->params;
325 ix_base = params->num_tc * params->num_channels;
327 for (tc = 0; tc < params->num_tc; tc++) {
328 int txq_ix = ix_base + tc;
330 err = mlx5e_ptp_open_txqsq(c, c->priv->tisn[c->lag_port][tc], txq_ix,
331 cparams, tc, &c->ptpsq[tc]);
339 for (--tc; tc >= 0; tc--)
340 mlx5e_ptp_close_txqsq(&c->ptpsq[tc]);
345 static void mlx5e_ptp_close_txqsqs(struct mlx5e_ptp *c)
349 for (tc = 0; tc < c->num_tc; tc++)
350 mlx5e_ptp_close_txqsq(&c->ptpsq[tc]);
353 static int mlx5e_ptp_open_tx_cqs(struct mlx5e_ptp *c,
354 struct mlx5e_ptp_params *cparams)
356 struct mlx5e_params *params = &cparams->params;
357 struct mlx5e_create_cq_param ccp = {};
358 struct dim_cq_moder ptp_moder = {};
359 struct mlx5e_cq_param *cq_param;
363 ccp.node = dev_to_node(mlx5_core_dma_dev(c->mdev));
364 ccp.ch_stats = c->stats;
366 ccp.ix = MLX5E_PTP_CHANNEL_IX;
368 cq_param = &cparams->txq_sq_param.cqp;
370 for (tc = 0; tc < params->num_tc; tc++) {
371 struct mlx5e_cq *cq = &c->ptpsq[tc].txqsq.cq;
373 err = mlx5e_open_cq(c->priv, ptp_moder, cq_param, &ccp, cq);
375 goto out_err_txqsq_cq;
378 for (tc = 0; tc < params->num_tc; tc++) {
379 struct mlx5e_cq *cq = &c->ptpsq[tc].ts_cq;
380 struct mlx5e_ptpsq *ptpsq = &c->ptpsq[tc];
382 err = mlx5e_open_cq(c->priv, ptp_moder, cq_param, &ccp, cq);
386 ptpsq->cq_stats = &c->priv->ptp_stats.cq[tc];
392 for (--tc; tc >= 0; tc--)
393 mlx5e_close_cq(&c->ptpsq[tc].ts_cq);
396 for (--tc; tc >= 0; tc--)
397 mlx5e_close_cq(&c->ptpsq[tc].txqsq.cq);
402 static int mlx5e_ptp_open_rx_cq(struct mlx5e_ptp *c,
403 struct mlx5e_ptp_params *cparams)
405 struct mlx5e_create_cq_param ccp = {};
406 struct dim_cq_moder ptp_moder = {};
407 struct mlx5e_cq_param *cq_param;
408 struct mlx5e_cq *cq = &c->rq.cq;
410 ccp.node = dev_to_node(mlx5_core_dma_dev(c->mdev));
411 ccp.ch_stats = c->stats;
413 ccp.ix = MLX5E_PTP_CHANNEL_IX;
415 cq_param = &cparams->rq_param.cqp;
417 return mlx5e_open_cq(c->priv, ptp_moder, cq_param, &ccp, cq);
420 static void mlx5e_ptp_close_tx_cqs(struct mlx5e_ptp *c)
424 for (tc = 0; tc < c->num_tc; tc++)
425 mlx5e_close_cq(&c->ptpsq[tc].ts_cq);
427 for (tc = 0; tc < c->num_tc; tc++)
428 mlx5e_close_cq(&c->ptpsq[tc].txqsq.cq);
431 static void mlx5e_ptp_build_sq_param(struct mlx5_core_dev *mdev,
432 struct mlx5e_params *params,
433 struct mlx5e_sq_param *param)
435 void *sqc = param->sqc;
438 mlx5e_build_sq_param_common(mdev, param);
440 wq = MLX5_ADDR_OF(sqc, sqc, wq);
441 MLX5_SET(wq, wq, log_wq_sz, params->log_sq_size);
442 param->stop_room = mlx5e_stop_room_for_wqe(MLX5_SEND_WQE_MAX_WQEBBS);
443 mlx5e_build_tx_cq_param(mdev, params, ¶m->cqp);
446 static void mlx5e_ptp_build_rq_param(struct mlx5_core_dev *mdev,
447 struct net_device *netdev,
449 struct mlx5e_ptp_params *ptp_params)
451 struct mlx5e_rq_param *rq_params = &ptp_params->rq_param;
452 struct mlx5e_params *params = &ptp_params->params;
454 params->rq_wq_type = MLX5_WQ_TYPE_CYCLIC;
455 mlx5e_init_rq_type_params(mdev, params);
456 params->sw_mtu = netdev->max_mtu;
457 mlx5e_build_rq_param(mdev, params, NULL, q_counter, rq_params);
460 static void mlx5e_ptp_build_params(struct mlx5e_ptp *c,
461 struct mlx5e_ptp_params *cparams,
462 struct mlx5e_params *orig)
464 struct mlx5e_params *params = &cparams->params;
466 params->tx_min_inline_mode = orig->tx_min_inline_mode;
467 params->num_channels = orig->num_channels;
468 params->hard_mtu = orig->hard_mtu;
469 params->sw_mtu = orig->sw_mtu;
470 params->num_tc = orig->num_tc;
473 if (test_bit(MLX5E_PTP_STATE_TX, c->state)) {
474 params->log_sq_size = orig->log_sq_size;
475 mlx5e_ptp_build_sq_param(c->mdev, params, &cparams->txq_sq_param);
477 if (test_bit(MLX5E_PTP_STATE_RX, c->state))
478 mlx5e_ptp_build_rq_param(c->mdev, c->netdev, c->priv->q_counter, cparams);
481 static int mlx5e_init_ptp_rq(struct mlx5e_ptp *c, struct mlx5e_params *params,
484 struct mlx5_core_dev *mdev = c->mdev;
485 struct mlx5e_priv *priv = c->priv;
488 rq->wq_type = params->rq_wq_type;
489 rq->pdev = mdev->device;
490 rq->netdev = priv->netdev;
492 rq->clock = &mdev->clock;
493 rq->tstamp = &priv->tstamp;
495 rq->hw_mtu = MLX5E_SW2HW_MTU(params, params->sw_mtu);
496 rq->stats = &c->priv->ptp_stats.rq;
497 rq->ptp_cyc2time = mlx5_rq_ts_translator(mdev);
498 err = mlx5e_rq_set_handlers(rq, params, false);
502 return xdp_rxq_info_reg(&rq->xdp_rxq, rq->netdev, rq->ix, 0);
505 static int mlx5e_ptp_open_rq(struct mlx5e_ptp *c, struct mlx5e_params *params,
506 struct mlx5e_rq_param *rq_param)
508 int node = dev_to_node(c->mdev->device);
511 err = mlx5e_init_ptp_rq(c, params, &c->rq);
515 return mlx5e_open_rq(params, rq_param, NULL, node, &c->rq);
518 static int mlx5e_ptp_open_queues(struct mlx5e_ptp *c,
519 struct mlx5e_ptp_params *cparams)
523 if (test_bit(MLX5E_PTP_STATE_TX, c->state)) {
524 err = mlx5e_ptp_open_tx_cqs(c, cparams);
528 err = mlx5e_ptp_open_txqsqs(c, cparams);
532 if (test_bit(MLX5E_PTP_STATE_RX, c->state)) {
533 err = mlx5e_ptp_open_rx_cq(c, cparams);
537 err = mlx5e_ptp_open_rq(c, &cparams->params, &cparams->rq_param);
544 if (test_bit(MLX5E_PTP_STATE_RX, c->state))
545 mlx5e_close_cq(&c->rq.cq);
547 if (test_bit(MLX5E_PTP_STATE_TX, c->state))
548 mlx5e_ptp_close_txqsqs(c);
550 if (test_bit(MLX5E_PTP_STATE_TX, c->state))
551 mlx5e_ptp_close_tx_cqs(c);
556 static void mlx5e_ptp_close_queues(struct mlx5e_ptp *c)
558 if (test_bit(MLX5E_PTP_STATE_RX, c->state)) {
559 mlx5e_close_rq(&c->rq);
560 mlx5e_close_cq(&c->rq.cq);
562 if (test_bit(MLX5E_PTP_STATE_TX, c->state)) {
563 mlx5e_ptp_close_txqsqs(c);
564 mlx5e_ptp_close_tx_cqs(c);
568 static int mlx5e_ptp_set_state(struct mlx5e_ptp *c, struct mlx5e_params *params)
570 if (MLX5E_GET_PFLAG(params, MLX5E_PFLAG_TX_PORT_TS))
571 __set_bit(MLX5E_PTP_STATE_TX, c->state);
573 return bitmap_empty(c->state, MLX5E_PTP_STATE_NUM_STATES) ? -EINVAL : 0;
576 int mlx5e_ptp_open(struct mlx5e_priv *priv, struct mlx5e_params *params,
577 u8 lag_port, struct mlx5e_ptp **cp)
579 struct net_device *netdev = priv->netdev;
580 struct mlx5_core_dev *mdev = priv->mdev;
581 struct mlx5e_ptp_params *cparams;
586 c = kvzalloc_node(sizeof(*c), GFP_KERNEL, dev_to_node(mlx5_core_dma_dev(mdev)));
587 cparams = kvzalloc(sizeof(*cparams), GFP_KERNEL);
592 c->mdev = priv->mdev;
593 c->tstamp = &priv->tstamp;
594 c->pdev = mlx5_core_dma_dev(priv->mdev);
595 c->netdev = priv->netdev;
596 c->mkey_be = cpu_to_be32(priv->mdev->mlx5e_res.hw_objs.mkey.key);
597 c->num_tc = params->num_tc;
598 c->stats = &priv->ptp_stats.ch;
599 c->lag_port = lag_port;
601 err = mlx5e_ptp_set_state(c, params);
605 netif_napi_add(netdev, &c->napi, mlx5e_ptp_napi_poll, 64);
607 mlx5e_ptp_build_params(c, cparams, params);
609 err = mlx5e_ptp_open_queues(c, cparams);
613 if (test_bit(MLX5E_PTP_STATE_RX, c->state))
614 priv->rx_ptp_opened = true;
623 netif_napi_del(&c->napi);
630 void mlx5e_ptp_close(struct mlx5e_ptp *c)
632 mlx5e_ptp_close_queues(c);
633 netif_napi_del(&c->napi);
638 void mlx5e_ptp_activate_channel(struct mlx5e_ptp *c)
642 napi_enable(&c->napi);
644 if (test_bit(MLX5E_PTP_STATE_TX, c->state)) {
645 for (tc = 0; tc < c->num_tc; tc++)
646 mlx5e_activate_txqsq(&c->ptpsq[tc].txqsq);
648 if (test_bit(MLX5E_PTP_STATE_RX, c->state))
649 mlx5e_activate_rq(&c->rq);
652 void mlx5e_ptp_deactivate_channel(struct mlx5e_ptp *c)
656 if (test_bit(MLX5E_PTP_STATE_RX, c->state))
657 mlx5e_deactivate_rq(&c->rq);
659 if (test_bit(MLX5E_PTP_STATE_TX, c->state)) {
660 for (tc = 0; tc < c->num_tc; tc++)
661 mlx5e_deactivate_txqsq(&c->ptpsq[tc].txqsq);
664 napi_disable(&c->napi);
667 int mlx5e_ptp_get_rqn(struct mlx5e_ptp *c, u32 *rqn)
669 if (!c || !test_bit(MLX5E_PTP_STATE_RX, c->state))