1 // SPDX-License-Identifier: GPL-2.0 OR Linux-OpenIB
2 /* Copyright (c) 2019 Mellanox Technologies. */
7 #include "en_accel/en_accel.h"
8 #include "accel/ipsec.h"
9 #include "fpga/ipsec.h"
11 static bool mlx5e_rx_is_xdp(struct mlx5e_params *params,
12 struct mlx5e_xsk_param *xsk)
14 return params->xdp_prog || xsk;
17 u16 mlx5e_get_linear_rq_headroom(struct mlx5e_params *params,
18 struct mlx5e_xsk_param *xsk)
25 headroom = NET_IP_ALIGN;
26 if (mlx5e_rx_is_xdp(params, xsk))
27 headroom += XDP_PACKET_HEADROOM;
29 headroom += MLX5_RX_HEADROOM;
34 u32 mlx5e_rx_get_min_frag_sz(struct mlx5e_params *params,
35 struct mlx5e_xsk_param *xsk)
37 u32 hw_mtu = MLX5E_SW2HW_MTU(params, params->sw_mtu);
38 u16 linear_rq_headroom = mlx5e_get_linear_rq_headroom(params, xsk);
40 return linear_rq_headroom + hw_mtu;
43 static u32 mlx5e_rx_get_linear_frag_sz(struct mlx5e_params *params,
44 struct mlx5e_xsk_param *xsk)
46 u32 frag_sz = mlx5e_rx_get_min_frag_sz(params, xsk);
48 /* AF_XDP doesn't build SKBs in place. */
50 frag_sz = MLX5_SKB_FRAG_SZ(frag_sz);
52 /* XDP in mlx5e doesn't support multiple packets per page. AF_XDP is a
53 * special case. It can run with frames smaller than a page, as it
54 * doesn't allocate pages dynamically. However, here we pretend that
55 * fragments are page-sized: it allows to treat XSK frames like pages
56 * by redirecting alloc and free operations to XSK rings and by using
57 * the fact there are no multiple packets per "page" (which is a frame).
58 * The latter is important, because frames may come in a random order,
59 * and we will have trouble assemblying a real page of multiple frames.
61 if (mlx5e_rx_is_xdp(params, xsk))
62 frag_sz = max_t(u32, frag_sz, PAGE_SIZE);
64 /* Even if we can go with a smaller fragment size, we must not put
65 * multiple packets into a single frame.
68 frag_sz = max_t(u32, frag_sz, xsk->chunk_size);
73 u8 mlx5e_mpwqe_log_pkts_per_wqe(struct mlx5e_params *params,
74 struct mlx5e_xsk_param *xsk)
76 u32 linear_frag_sz = mlx5e_rx_get_linear_frag_sz(params, xsk);
78 return MLX5_MPWRQ_LOG_WQE_SZ - order_base_2(linear_frag_sz);
81 bool mlx5e_rx_is_linear_skb(struct mlx5e_params *params,
82 struct mlx5e_xsk_param *xsk)
84 /* AF_XDP allocates SKBs on XDP_PASS - ensure they don't occupy more
85 * than one page. For this, check both with and without xsk.
87 u32 linear_frag_sz = max(mlx5e_rx_get_linear_frag_sz(params, xsk),
88 mlx5e_rx_get_linear_frag_sz(params, NULL));
90 return params->packet_merge.type == MLX5E_PACKET_MERGE_NONE &&
91 linear_frag_sz <= PAGE_SIZE;
94 bool mlx5e_verify_rx_mpwqe_strides(struct mlx5_core_dev *mdev,
95 u8 log_stride_sz, u8 log_num_strides)
97 if (log_stride_sz + log_num_strides != MLX5_MPWRQ_LOG_WQE_SZ)
100 if (log_stride_sz < MLX5_MPWQE_LOG_STRIDE_SZ_BASE ||
101 log_stride_sz > MLX5_MPWQE_LOG_STRIDE_SZ_MAX)
104 if (log_num_strides > MLX5_MPWQE_LOG_NUM_STRIDES_MAX)
107 if (MLX5_CAP_GEN(mdev, ext_stride_num_range))
108 return log_num_strides >= MLX5_MPWQE_LOG_NUM_STRIDES_EXT_BASE;
110 return log_num_strides >= MLX5_MPWQE_LOG_NUM_STRIDES_BASE;
113 bool mlx5e_rx_mpwqe_is_linear_skb(struct mlx5_core_dev *mdev,
114 struct mlx5e_params *params,
115 struct mlx5e_xsk_param *xsk)
120 if (!mlx5e_rx_is_linear_skb(params, xsk))
123 log_stride_sz = order_base_2(mlx5e_rx_get_linear_frag_sz(params, xsk));
124 log_num_strides = MLX5_MPWRQ_LOG_WQE_SZ - log_stride_sz;
126 return mlx5e_verify_rx_mpwqe_strides(mdev, log_stride_sz, log_num_strides);
129 u8 mlx5e_mpwqe_get_log_rq_size(struct mlx5e_params *params,
130 struct mlx5e_xsk_param *xsk)
132 u8 log_pkts_per_wqe = mlx5e_mpwqe_log_pkts_per_wqe(params, xsk);
134 /* Numbers are unsigned, don't subtract to avoid underflow. */
135 if (params->log_rq_mtu_frames <
136 log_pkts_per_wqe + MLX5E_PARAMS_MINIMUM_LOG_RQ_SIZE_MPW)
137 return MLX5E_PARAMS_MINIMUM_LOG_RQ_SIZE_MPW;
139 return params->log_rq_mtu_frames - log_pkts_per_wqe;
142 u8 mlx5e_shampo_get_log_hd_entry_size(struct mlx5_core_dev *mdev,
143 struct mlx5e_params *params)
145 return order_base_2(DIV_ROUND_UP(MLX5E_RX_MAX_HEAD, MLX5E_SHAMPO_WQ_BASE_HEAD_ENTRY_SIZE));
148 u8 mlx5e_shampo_get_log_rsrv_size(struct mlx5_core_dev *mdev,
149 struct mlx5e_params *params)
151 return order_base_2(MLX5E_SHAMPO_WQ_RESRV_SIZE / MLX5E_SHAMPO_WQ_BASE_RESRV_SIZE);
154 u8 mlx5e_shampo_get_log_pkt_per_rsrv(struct mlx5_core_dev *mdev,
155 struct mlx5e_params *params)
157 u32 resrv_size = BIT(mlx5e_shampo_get_log_rsrv_size(mdev, params)) *
160 return order_base_2(DIV_ROUND_UP(resrv_size, params->sw_mtu));
163 u8 mlx5e_mpwqe_get_log_stride_size(struct mlx5_core_dev *mdev,
164 struct mlx5e_params *params,
165 struct mlx5e_xsk_param *xsk)
167 if (mlx5e_rx_mpwqe_is_linear_skb(mdev, params, xsk))
168 return order_base_2(mlx5e_rx_get_linear_frag_sz(params, xsk));
170 return MLX5_MPWRQ_DEF_LOG_STRIDE_SZ(mdev);
173 u8 mlx5e_mpwqe_get_log_num_strides(struct mlx5_core_dev *mdev,
174 struct mlx5e_params *params,
175 struct mlx5e_xsk_param *xsk)
177 return MLX5_MPWRQ_LOG_WQE_SZ -
178 mlx5e_mpwqe_get_log_stride_size(mdev, params, xsk);
181 u8 mlx5e_mpwqe_get_min_wqe_bulk(unsigned int wq_sz)
183 #define UMR_WQE_BULK (2)
184 return min_t(unsigned int, UMR_WQE_BULK, wq_sz / 2 - 1);
187 u16 mlx5e_get_rq_headroom(struct mlx5_core_dev *mdev,
188 struct mlx5e_params *params,
189 struct mlx5e_xsk_param *xsk)
191 bool is_linear_skb = (params->rq_wq_type == MLX5_WQ_TYPE_CYCLIC) ?
192 mlx5e_rx_is_linear_skb(params, xsk) :
193 mlx5e_rx_mpwqe_is_linear_skb(mdev, params, xsk);
195 return is_linear_skb || params->packet_merge.type == MLX5E_PACKET_MERGE_SHAMPO ?
196 mlx5e_get_linear_rq_headroom(params, xsk) : 0;
199 u16 mlx5e_calc_sq_stop_room(struct mlx5_core_dev *mdev, struct mlx5e_params *params)
201 bool is_mpwqe = MLX5E_GET_PFLAG(params, MLX5E_PFLAG_SKB_TX_MPWQE);
204 stop_room = mlx5e_tls_get_stop_room(mdev, params);
205 stop_room += mlx5e_stop_room_for_max_wqe(mdev);
207 /* A MPWQE can take up to the maximum-sized WQE + all the normal
208 * stop room can be taken if a new packet breaks the active
209 * MPWQE session and allocates its WQEs right away.
211 stop_room += mlx5e_stop_room_for_max_wqe(mdev);
216 int mlx5e_validate_params(struct mlx5_core_dev *mdev, struct mlx5e_params *params)
218 size_t sq_size = 1 << params->log_sq_size;
221 stop_room = mlx5e_calc_sq_stop_room(mdev, params);
222 if (stop_room >= sq_size) {
223 mlx5_core_err(mdev, "Stop room %u is bigger than the SQ size %zu\n",
231 static struct dim_cq_moder mlx5e_get_def_tx_moderation(u8 cq_period_mode)
233 struct dim_cq_moder moder = {};
235 moder.cq_period_mode = cq_period_mode;
236 moder.pkts = MLX5E_PARAMS_DEFAULT_TX_CQ_MODERATION_PKTS;
237 moder.usec = MLX5E_PARAMS_DEFAULT_TX_CQ_MODERATION_USEC;
238 if (cq_period_mode == MLX5_CQ_PERIOD_MODE_START_FROM_CQE)
239 moder.usec = MLX5E_PARAMS_DEFAULT_TX_CQ_MODERATION_USEC_FROM_CQE;
244 static struct dim_cq_moder mlx5e_get_def_rx_moderation(u8 cq_period_mode)
246 struct dim_cq_moder moder = {};
248 moder.cq_period_mode = cq_period_mode;
249 moder.pkts = MLX5E_PARAMS_DEFAULT_RX_CQ_MODERATION_PKTS;
250 moder.usec = MLX5E_PARAMS_DEFAULT_RX_CQ_MODERATION_USEC;
251 if (cq_period_mode == MLX5_CQ_PERIOD_MODE_START_FROM_CQE)
252 moder.usec = MLX5E_PARAMS_DEFAULT_RX_CQ_MODERATION_USEC_FROM_CQE;
257 static u8 mlx5_to_net_dim_cq_period_mode(u8 cq_period_mode)
259 return cq_period_mode == MLX5_CQ_PERIOD_MODE_START_FROM_CQE ?
260 DIM_CQ_PERIOD_MODE_START_FROM_CQE :
261 DIM_CQ_PERIOD_MODE_START_FROM_EQE;
264 void mlx5e_reset_tx_moderation(struct mlx5e_params *params, u8 cq_period_mode)
266 if (params->tx_dim_enabled) {
267 u8 dim_period_mode = mlx5_to_net_dim_cq_period_mode(cq_period_mode);
269 params->tx_cq_moderation = net_dim_get_def_tx_moderation(dim_period_mode);
271 params->tx_cq_moderation = mlx5e_get_def_tx_moderation(cq_period_mode);
275 void mlx5e_reset_rx_moderation(struct mlx5e_params *params, u8 cq_period_mode)
277 if (params->rx_dim_enabled) {
278 u8 dim_period_mode = mlx5_to_net_dim_cq_period_mode(cq_period_mode);
280 params->rx_cq_moderation = net_dim_get_def_rx_moderation(dim_period_mode);
282 params->rx_cq_moderation = mlx5e_get_def_rx_moderation(cq_period_mode);
286 void mlx5e_set_tx_cq_mode_params(struct mlx5e_params *params, u8 cq_period_mode)
288 mlx5e_reset_tx_moderation(params, cq_period_mode);
289 MLX5E_SET_PFLAG(params, MLX5E_PFLAG_TX_CQE_BASED_MODER,
290 params->tx_cq_moderation.cq_period_mode ==
291 MLX5_CQ_PERIOD_MODE_START_FROM_CQE);
294 void mlx5e_set_rx_cq_mode_params(struct mlx5e_params *params, u8 cq_period_mode)
296 mlx5e_reset_rx_moderation(params, cq_period_mode);
297 MLX5E_SET_PFLAG(params, MLX5E_PFLAG_RX_CQE_BASED_MODER,
298 params->rx_cq_moderation.cq_period_mode ==
299 MLX5_CQ_PERIOD_MODE_START_FROM_CQE);
302 bool slow_pci_heuristic(struct mlx5_core_dev *mdev)
307 mlx5e_port_max_linkspeed(mdev, &link_speed);
308 pci_bw = pcie_bandwidth_available(mdev->pdev, NULL, NULL, NULL);
309 mlx5_core_dbg_once(mdev, "Max link speed = %d, PCI BW = %d\n",
312 #define MLX5E_SLOW_PCI_RATIO (2)
314 return link_speed && pci_bw &&
315 link_speed > MLX5E_SLOW_PCI_RATIO * pci_bw;
318 bool mlx5e_striding_rq_possible(struct mlx5_core_dev *mdev,
319 struct mlx5e_params *params)
321 if (!mlx5e_check_fragmented_striding_rq_cap(mdev))
324 if (mlx5_fpga_is_ipsec_device(mdev))
327 if (params->xdp_prog) {
328 /* XSK params are not considered here. If striding RQ is in use,
329 * and an XSK is being opened, mlx5e_rx_mpwqe_is_linear_skb will
330 * be called with the known XSK params.
332 if (!mlx5e_rx_mpwqe_is_linear_skb(mdev, params, NULL))
339 void mlx5e_init_rq_type_params(struct mlx5_core_dev *mdev,
340 struct mlx5e_params *params)
342 params->log_rq_mtu_frames = is_kdump_kernel() ?
343 MLX5E_PARAMS_MINIMUM_LOG_RQ_SIZE :
344 MLX5E_PARAMS_DEFAULT_LOG_RQ_SIZE;
346 mlx5_core_info(mdev, "MLX5E: StrdRq(%d) RqSz(%ld) StrdSz(%ld) RxCqeCmprss(%d)\n",
347 params->rq_wq_type == MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ,
348 params->rq_wq_type == MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ ?
349 BIT(mlx5e_mpwqe_get_log_rq_size(params, NULL)) :
350 BIT(params->log_rq_mtu_frames),
351 BIT(mlx5e_mpwqe_get_log_stride_size(mdev, params, NULL)),
352 MLX5E_GET_PFLAG(params, MLX5E_PFLAG_RX_CQE_COMPRESS));
355 void mlx5e_set_rq_type(struct mlx5_core_dev *mdev, struct mlx5e_params *params)
357 params->rq_wq_type = mlx5e_striding_rq_possible(mdev, params) &&
358 MLX5E_GET_PFLAG(params, MLX5E_PFLAG_RX_STRIDING_RQ) ?
359 MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ :
363 void mlx5e_build_rq_params(struct mlx5_core_dev *mdev,
364 struct mlx5e_params *params)
366 /* Prefer Striding RQ, unless any of the following holds:
367 * - Striding RQ configuration is not possible/supported.
368 * - CQE compression is ON, and stride_index mini_cqe layout is not supported.
369 * - Legacy RQ would use linear SKB while Striding RQ would use non-linear.
371 * No XSK params: checking the availability of striding RQ in general.
373 if ((!MLX5E_GET_PFLAG(params, MLX5E_PFLAG_RX_CQE_COMPRESS) ||
374 MLX5_CAP_GEN(mdev, mini_cqe_resp_stride_index)) &&
375 mlx5e_striding_rq_possible(mdev, params) &&
376 (mlx5e_rx_mpwqe_is_linear_skb(mdev, params, NULL) ||
377 !mlx5e_rx_is_linear_skb(params, NULL)))
378 MLX5E_SET_PFLAG(params, MLX5E_PFLAG_RX_STRIDING_RQ, true);
379 mlx5e_set_rq_type(mdev, params);
380 mlx5e_init_rq_type_params(mdev, params);
383 /* Build queue parameters */
385 void mlx5e_build_create_cq_param(struct mlx5e_create_cq_param *ccp, struct mlx5e_channel *c)
387 *ccp = (struct mlx5e_create_cq_param) {
389 .ch_stats = c->stats,
390 .node = cpu_to_node(c->cpu),
395 static int mlx5e_max_nonlinear_mtu(int frag_size)
397 /* Optimization for small packets: the last fragment is bigger than the others. */
398 return (MLX5E_MAX_RX_FRAGS - 1) * frag_size + PAGE_SIZE;
401 #define DEFAULT_FRAG_SIZE (2048)
403 static int mlx5e_build_rq_frags_info(struct mlx5_core_dev *mdev,
404 struct mlx5e_params *params,
405 struct mlx5e_xsk_param *xsk,
406 struct mlx5e_rq_frags_info *info)
408 u32 byte_count = MLX5E_SW2HW_MTU(params, params->sw_mtu);
409 int frag_size_max = DEFAULT_FRAG_SIZE;
414 if (mlx5_fpga_is_ipsec_device(mdev))
415 byte_count += MLX5E_METADATA_ETHER_LEN;
417 if (mlx5e_rx_is_linear_skb(params, xsk)) {
420 frag_stride = mlx5e_rx_get_linear_frag_sz(params, xsk);
421 frag_stride = roundup_pow_of_two(frag_stride);
423 info->arr[0].frag_size = byte_count;
424 info->arr[0].frag_stride = frag_stride;
426 info->wqe_bulk = PAGE_SIZE / frag_stride;
430 max_mtu = mlx5e_max_nonlinear_mtu(frag_size_max);
431 if (byte_count > max_mtu) {
432 frag_size_max = PAGE_SIZE;
434 max_mtu = mlx5e_max_nonlinear_mtu(frag_size_max);
435 if (byte_count > max_mtu) {
436 mlx5_core_err(mdev, "MTU %u is too big for non-linear legacy RQ (max %d)\n",
437 params->sw_mtu, max_mtu);
443 while (buf_size < byte_count) {
444 int frag_size = byte_count - buf_size;
446 if (i < MLX5E_MAX_RX_FRAGS - 1)
447 frag_size = min(frag_size, frag_size_max);
449 info->arr[i].frag_size = frag_size;
450 info->arr[i].frag_stride = roundup_pow_of_two(frag_size);
452 buf_size += frag_size;
456 /* number of different wqes sharing a page */
457 info->wqe_bulk = 1 + (info->num_frags % 2);
460 info->wqe_bulk = max_t(u8, info->wqe_bulk, 8);
461 info->log_num_frags = order_base_2(info->num_frags);
466 static u8 mlx5e_get_rqwq_log_stride(u8 wq_type, int ndsegs)
468 int sz = sizeof(struct mlx5_wqe_data_seg) * ndsegs;
471 case MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ:
472 sz += sizeof(struct mlx5e_rx_wqe_ll);
474 default: /* MLX5_WQ_TYPE_CYCLIC */
475 sz += sizeof(struct mlx5e_rx_wqe_cyc);
478 return order_base_2(sz);
481 static void mlx5e_build_common_cq_param(struct mlx5_core_dev *mdev,
482 struct mlx5e_cq_param *param)
484 void *cqc = param->cqc;
486 MLX5_SET(cqc, cqc, uar_page, mdev->priv.uar->index);
487 if (MLX5_CAP_GEN(mdev, cqe_128_always) && cache_line_size() >= 128)
488 MLX5_SET(cqc, cqc, cqe_sz, CQE_STRIDE_128_PAD);
491 static u32 mlx5e_shampo_get_log_cq_size(struct mlx5_core_dev *mdev,
492 struct mlx5e_params *params,
493 struct mlx5e_xsk_param *xsk)
495 int rsrv_size = BIT(mlx5e_shampo_get_log_rsrv_size(mdev, params)) * PAGE_SIZE;
496 u16 num_strides = BIT(mlx5e_mpwqe_get_log_num_strides(mdev, params, xsk));
497 int pkt_per_rsrv = BIT(mlx5e_shampo_get_log_pkt_per_rsrv(mdev, params));
498 u8 log_stride_sz = mlx5e_mpwqe_get_log_stride_size(mdev, params, xsk);
499 int wq_size = BIT(mlx5e_mpwqe_get_log_rq_size(params, xsk));
500 int wqe_size = BIT(log_stride_sz) * num_strides;
502 /* +1 is for the case that the pkt_per_rsrv dont consume the reservation
503 * so we get a filler cqe for the rest of the reservation.
505 return order_base_2((wqe_size / rsrv_size) * wq_size * (pkt_per_rsrv + 1));
508 static void mlx5e_build_rx_cq_param(struct mlx5_core_dev *mdev,
509 struct mlx5e_params *params,
510 struct mlx5e_xsk_param *xsk,
511 struct mlx5e_cq_param *param)
513 bool hw_stridx = false;
514 void *cqc = param->cqc;
517 switch (params->rq_wq_type) {
518 case MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ:
519 hw_stridx = MLX5_CAP_GEN(mdev, mini_cqe_resp_stride_index);
520 if (params->packet_merge.type == MLX5E_PACKET_MERGE_SHAMPO)
521 log_cq_size = mlx5e_shampo_get_log_cq_size(mdev, params, xsk);
523 log_cq_size = mlx5e_mpwqe_get_log_rq_size(params, xsk) +
524 mlx5e_mpwqe_get_log_num_strides(mdev, params, xsk);
526 default: /* MLX5_WQ_TYPE_CYCLIC */
527 log_cq_size = params->log_rq_mtu_frames;
530 MLX5_SET(cqc, cqc, log_cq_size, log_cq_size);
531 if (MLX5E_GET_PFLAG(params, MLX5E_PFLAG_RX_CQE_COMPRESS)) {
532 MLX5_SET(cqc, cqc, mini_cqe_res_format, hw_stridx ?
533 MLX5_CQE_FORMAT_CSUM_STRIDX : MLX5_CQE_FORMAT_CSUM);
534 MLX5_SET(cqc, cqc, cqe_comp_en, 1);
537 mlx5e_build_common_cq_param(mdev, param);
538 param->cq_period_mode = params->rx_cq_moderation.cq_period_mode;
541 static u8 rq_end_pad_mode(struct mlx5_core_dev *mdev, struct mlx5e_params *params)
543 bool lro_en = params->packet_merge.type == MLX5E_PACKET_MERGE_LRO;
544 bool ro = pcie_relaxed_ordering_enabled(mdev->pdev) &&
545 MLX5_CAP_GEN(mdev, relaxed_ordering_write);
547 return ro && lro_en ?
548 MLX5_WQ_END_PAD_MODE_NONE : MLX5_WQ_END_PAD_MODE_ALIGN;
551 int mlx5e_build_rq_param(struct mlx5_core_dev *mdev,
552 struct mlx5e_params *params,
553 struct mlx5e_xsk_param *xsk,
555 struct mlx5e_rq_param *param)
557 void *rqc = param->rqc;
558 void *wq = MLX5_ADDR_OF(rqc, rqc, wq);
562 switch (params->rq_wq_type) {
563 case MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ: {
564 u8 log_wqe_num_of_strides = mlx5e_mpwqe_get_log_num_strides(mdev, params, xsk);
565 u8 log_wqe_stride_size = mlx5e_mpwqe_get_log_stride_size(mdev, params, xsk);
567 if (!mlx5e_verify_rx_mpwqe_strides(mdev, log_wqe_stride_size,
568 log_wqe_num_of_strides)) {
570 "Bad RX MPWQE params: log_stride_size %u, log_num_strides %u\n",
571 log_wqe_stride_size, log_wqe_num_of_strides);
575 MLX5_SET(wq, wq, log_wqe_num_of_strides,
576 log_wqe_num_of_strides - MLX5_MPWQE_LOG_NUM_STRIDES_BASE);
577 MLX5_SET(wq, wq, log_wqe_stride_size,
578 log_wqe_stride_size - MLX5_MPWQE_LOG_STRIDE_SZ_BASE);
579 MLX5_SET(wq, wq, log_wq_sz, mlx5e_mpwqe_get_log_rq_size(params, xsk));
580 if (params->packet_merge.type == MLX5E_PACKET_MERGE_SHAMPO) {
581 MLX5_SET(wq, wq, shampo_enable, true);
582 MLX5_SET(wq, wq, log_reservation_size,
583 mlx5e_shampo_get_log_rsrv_size(mdev, params));
585 log_max_num_of_packets_per_reservation,
586 mlx5e_shampo_get_log_pkt_per_rsrv(mdev, params));
587 MLX5_SET(wq, wq, log_headers_entry_size,
588 mlx5e_shampo_get_log_hd_entry_size(mdev, params));
589 MLX5_SET(rqc, rqc, reservation_timeout,
590 params->packet_merge.timeout);
591 MLX5_SET(rqc, rqc, shampo_match_criteria_type,
592 params->packet_merge.shampo.match_criteria_type);
593 MLX5_SET(rqc, rqc, shampo_no_match_alignment_granularity,
594 params->packet_merge.shampo.alignment_granularity);
598 default: /* MLX5_WQ_TYPE_CYCLIC */
599 MLX5_SET(wq, wq, log_wq_sz, params->log_rq_mtu_frames);
600 err = mlx5e_build_rq_frags_info(mdev, params, xsk, ¶m->frags_info);
603 ndsegs = param->frags_info.num_frags;
606 MLX5_SET(wq, wq, wq_type, params->rq_wq_type);
607 MLX5_SET(wq, wq, end_padding_mode, rq_end_pad_mode(mdev, params));
608 MLX5_SET(wq, wq, log_wq_stride,
609 mlx5e_get_rqwq_log_stride(params->rq_wq_type, ndsegs));
610 MLX5_SET(wq, wq, pd, mdev->mlx5e_res.hw_objs.pdn);
611 MLX5_SET(rqc, rqc, counter_set_id, q_counter);
612 MLX5_SET(rqc, rqc, vsd, params->vlan_strip_disable);
613 MLX5_SET(rqc, rqc, scatter_fcs, params->scatter_fcs_en);
615 param->wq.buf_numa_node = dev_to_node(mlx5_core_dma_dev(mdev));
616 mlx5e_build_rx_cq_param(mdev, params, xsk, ¶m->cqp);
621 void mlx5e_build_drop_rq_param(struct mlx5_core_dev *mdev,
623 struct mlx5e_rq_param *param)
625 void *rqc = param->rqc;
626 void *wq = MLX5_ADDR_OF(rqc, rqc, wq);
628 MLX5_SET(wq, wq, wq_type, MLX5_WQ_TYPE_CYCLIC);
629 MLX5_SET(wq, wq, log_wq_stride,
630 mlx5e_get_rqwq_log_stride(MLX5_WQ_TYPE_CYCLIC, 1));
631 MLX5_SET(rqc, rqc, counter_set_id, q_counter);
633 param->wq.buf_numa_node = dev_to_node(mlx5_core_dma_dev(mdev));
636 void mlx5e_build_tx_cq_param(struct mlx5_core_dev *mdev,
637 struct mlx5e_params *params,
638 struct mlx5e_cq_param *param)
640 void *cqc = param->cqc;
642 MLX5_SET(cqc, cqc, log_cq_size, params->log_sq_size);
644 mlx5e_build_common_cq_param(mdev, param);
645 param->cq_period_mode = params->tx_cq_moderation.cq_period_mode;
648 void mlx5e_build_sq_param_common(struct mlx5_core_dev *mdev,
649 struct mlx5e_sq_param *param)
651 void *sqc = param->sqc;
652 void *wq = MLX5_ADDR_OF(sqc, sqc, wq);
654 MLX5_SET(wq, wq, log_wq_stride, ilog2(MLX5_SEND_WQE_BB));
655 MLX5_SET(wq, wq, pd, mdev->mlx5e_res.hw_objs.pdn);
657 param->wq.buf_numa_node = dev_to_node(mlx5_core_dma_dev(mdev));
660 void mlx5e_build_sq_param(struct mlx5_core_dev *mdev,
661 struct mlx5e_params *params,
662 struct mlx5e_sq_param *param)
664 void *sqc = param->sqc;
665 void *wq = MLX5_ADDR_OF(sqc, sqc, wq);
668 allow_swp = mlx5_geneve_tx_allowed(mdev) ||
669 !!MLX5_IPSEC_DEV(mdev);
670 mlx5e_build_sq_param_common(mdev, param);
671 MLX5_SET(wq, wq, log_wq_sz, params->log_sq_size);
672 MLX5_SET(sqc, sqc, allow_swp, allow_swp);
673 param->is_mpw = MLX5E_GET_PFLAG(params, MLX5E_PFLAG_SKB_TX_MPWQE);
674 param->stop_room = mlx5e_calc_sq_stop_room(mdev, params);
675 mlx5e_build_tx_cq_param(mdev, params, ¶m->cqp);
678 static void mlx5e_build_ico_cq_param(struct mlx5_core_dev *mdev,
680 struct mlx5e_cq_param *param)
682 void *cqc = param->cqc;
684 MLX5_SET(cqc, cqc, log_cq_size, log_wq_size);
686 mlx5e_build_common_cq_param(mdev, param);
688 param->cq_period_mode = DIM_CQ_PERIOD_MODE_START_FROM_EQE;
691 static u8 mlx5e_get_rq_log_wq_sz(void *rqc)
693 void *wq = MLX5_ADDR_OF(rqc, rqc, wq);
695 return MLX5_GET(wq, wq, log_wq_sz);
698 /* This function calculates the maximum number of headers entries that are needed
699 * per WQE, the formula is based on the size of the reservations and the
700 * restriction we have about max packets for reservation that is equal to max
701 * headers per reservation.
703 u32 mlx5e_shampo_hd_per_wqe(struct mlx5_core_dev *mdev,
704 struct mlx5e_params *params,
705 struct mlx5e_rq_param *rq_param)
707 int resv_size = BIT(mlx5e_shampo_get_log_rsrv_size(mdev, params)) * PAGE_SIZE;
708 u16 num_strides = BIT(mlx5e_mpwqe_get_log_num_strides(mdev, params, NULL));
709 int pkt_per_resv = BIT(mlx5e_shampo_get_log_pkt_per_rsrv(mdev, params));
710 u8 log_stride_sz = mlx5e_mpwqe_get_log_stride_size(mdev, params, NULL);
711 int wqe_size = BIT(log_stride_sz) * num_strides;
714 /* Assumption: hd_per_wqe % 8 == 0. */
715 hd_per_wqe = (wqe_size / resv_size) * pkt_per_resv;
716 mlx5_core_dbg(mdev, "%s hd_per_wqe = %d rsrv_size = %d wqe_size = %d pkt_per_resv = %d\n",
717 __func__, hd_per_wqe, resv_size, wqe_size, pkt_per_resv);
721 /* This function calculates the maximum number of headers entries that are needed
722 * for the WQ, this value is uesed to allocate the header buffer in HW, thus
723 * must be a pow of 2.
725 u32 mlx5e_shampo_hd_per_wq(struct mlx5_core_dev *mdev,
726 struct mlx5e_params *params,
727 struct mlx5e_rq_param *rq_param)
729 void *wqc = MLX5_ADDR_OF(rqc, rq_param->rqc, wq);
730 int wq_size = BIT(MLX5_GET(wq, wqc, log_wq_sz));
731 u32 hd_per_wqe, hd_per_wq;
733 hd_per_wqe = mlx5e_shampo_hd_per_wqe(mdev, params, rq_param);
734 hd_per_wq = roundup_pow_of_two(hd_per_wqe * wq_size);
738 static u32 mlx5e_shampo_icosq_sz(struct mlx5_core_dev *mdev,
739 struct mlx5e_params *params,
740 struct mlx5e_rq_param *rq_param)
742 int max_num_of_umr_per_wqe, max_hd_per_wqe, max_klm_per_umr, rest;
743 void *wqc = MLX5_ADDR_OF(rqc, rq_param->rqc, wq);
744 int wq_size = BIT(MLX5_GET(wq, wqc, log_wq_sz));
747 max_klm_per_umr = MLX5E_MAX_KLM_PER_WQE(mdev);
748 max_hd_per_wqe = mlx5e_shampo_hd_per_wqe(mdev, params, rq_param);
749 max_num_of_umr_per_wqe = max_hd_per_wqe / max_klm_per_umr;
750 rest = max_hd_per_wqe % max_klm_per_umr;
751 wqebbs = MLX5E_KLM_UMR_WQEBBS(max_klm_per_umr) * max_num_of_umr_per_wqe;
753 wqebbs += MLX5E_KLM_UMR_WQEBBS(rest);
758 static u8 mlx5e_build_icosq_log_wq_sz(struct mlx5_core_dev *mdev,
759 struct mlx5e_params *params,
760 struct mlx5e_rq_param *rqp)
764 /* MLX5_WQ_TYPE_CYCLIC */
765 if (params->rq_wq_type != MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ)
766 return MLX5E_PARAMS_MINIMUM_LOG_SQ_SIZE;
768 wqebbs = MLX5E_UMR_WQEBBS * BIT(mlx5e_get_rq_log_wq_sz(rqp->rqc));
769 if (params->packet_merge.type == MLX5E_PACKET_MERGE_SHAMPO)
770 wqebbs += mlx5e_shampo_icosq_sz(mdev, params, rqp);
771 return max_t(u8, MLX5E_PARAMS_MINIMUM_LOG_SQ_SIZE, order_base_2(wqebbs));
774 static u8 mlx5e_build_async_icosq_log_wq_sz(struct mlx5_core_dev *mdev)
776 if (mlx5e_accel_is_ktls_rx(mdev))
777 return MLX5E_PARAMS_DEFAULT_LOG_SQ_SIZE;
779 return MLX5E_PARAMS_MINIMUM_LOG_SQ_SIZE;
782 static void mlx5e_build_icosq_param(struct mlx5_core_dev *mdev,
784 struct mlx5e_sq_param *param)
786 void *sqc = param->sqc;
787 void *wq = MLX5_ADDR_OF(sqc, sqc, wq);
789 mlx5e_build_sq_param_common(mdev, param);
791 MLX5_SET(wq, wq, log_wq_sz, log_wq_size);
792 MLX5_SET(sqc, sqc, reg_umr, MLX5_CAP_ETH(mdev, reg_umr_sq));
793 mlx5e_build_ico_cq_param(mdev, log_wq_size, ¶m->cqp);
796 static void mlx5e_build_async_icosq_param(struct mlx5_core_dev *mdev,
798 struct mlx5e_sq_param *param)
800 void *sqc = param->sqc;
801 void *wq = MLX5_ADDR_OF(sqc, sqc, wq);
803 mlx5e_build_sq_param_common(mdev, param);
804 param->stop_room = mlx5e_stop_room_for_wqe(mdev, 1); /* for XSK NOP */
805 param->is_tls = mlx5e_accel_is_ktls_rx(mdev);
807 param->stop_room += mlx5e_stop_room_for_wqe(mdev, 1); /* for TLS RX resync NOP */
808 MLX5_SET(sqc, sqc, reg_umr, MLX5_CAP_ETH(mdev, reg_umr_sq));
809 MLX5_SET(wq, wq, log_wq_sz, log_wq_size);
810 mlx5e_build_ico_cq_param(mdev, log_wq_size, ¶m->cqp);
813 void mlx5e_build_xdpsq_param(struct mlx5_core_dev *mdev,
814 struct mlx5e_params *params,
815 struct mlx5e_sq_param *param)
817 void *sqc = param->sqc;
818 void *wq = MLX5_ADDR_OF(sqc, sqc, wq);
820 mlx5e_build_sq_param_common(mdev, param);
821 MLX5_SET(wq, wq, log_wq_sz, params->log_sq_size);
822 param->is_mpw = MLX5E_GET_PFLAG(params, MLX5E_PFLAG_XDP_TX_MPWQE);
823 mlx5e_build_tx_cq_param(mdev, params, ¶m->cqp);
826 int mlx5e_build_channel_param(struct mlx5_core_dev *mdev,
827 struct mlx5e_params *params,
829 struct mlx5e_channel_param *cparam)
831 u8 icosq_log_wq_sz, async_icosq_log_wq_sz;
834 err = mlx5e_build_rq_param(mdev, params, NULL, q_counter, &cparam->rq);
838 icosq_log_wq_sz = mlx5e_build_icosq_log_wq_sz(mdev, params, &cparam->rq);
839 async_icosq_log_wq_sz = mlx5e_build_async_icosq_log_wq_sz(mdev);
841 mlx5e_build_sq_param(mdev, params, &cparam->txq_sq);
842 mlx5e_build_xdpsq_param(mdev, params, &cparam->xdp_sq);
843 mlx5e_build_icosq_param(mdev, icosq_log_wq_sz, &cparam->icosq);
844 mlx5e_build_async_icosq_param(mdev, async_icosq_log_wq_sz, &cparam->async_icosq);