2 * Copyright (c) 2018 Mellanox Technologies. All rights reserved.
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34 #ifndef __MLX5_ACCEL_TLS_H__
35 #define __MLX5_ACCEL_TLS_H__
37 #include <linux/mlx5/driver.h>
38 #include <linux/tls.h>
40 #ifdef CONFIG_MLX5_TLS
41 int mlx5_ktls_create_key(struct mlx5_core_dev *mdev,
42 struct tls_crypto_info *crypto_info,
44 void mlx5_ktls_destroy_key(struct mlx5_core_dev *mdev, u32 key_id);
46 static inline bool mlx5_accel_is_ktls_device(struct mlx5_core_dev *mdev)
48 if (!MLX5_CAP_GEN(mdev, tls_tx))
51 if (!MLX5_CAP_GEN(mdev, log_max_dek))
54 return MLX5_CAP_TLS(mdev, tls_1_2_aes_gcm_128);
57 static inline bool mlx5e_ktls_type_check(struct mlx5_core_dev *mdev,
58 struct tls_crypto_info *crypto_info)
60 switch (crypto_info->cipher_type) {
61 case TLS_CIPHER_AES_GCM_128:
62 if (crypto_info->version == TLS_1_2_VERSION)
63 return MLX5_CAP_TLS(mdev, tls_1_2_aes_gcm_128);
71 mlx5_ktls_create_key(struct mlx5_core_dev *mdev,
72 struct tls_crypto_info *crypto_info,
73 u32 *p_key_id) { return -ENOTSUPP; }
75 mlx5_ktls_destroy_key(struct mlx5_core_dev *mdev, u32 key_id) {}
78 mlx5_accel_is_ktls_device(struct mlx5_core_dev *mdev) { return false; }
80 mlx5e_ktls_type_check(struct mlx5_core_dev *mdev,
81 struct tls_crypto_info *crypto_info) { return false; }
85 MLX5_ACCEL_TLS_TX = BIT(0),
86 MLX5_ACCEL_TLS_RX = BIT(1),
87 MLX5_ACCEL_TLS_V12 = BIT(2),
88 MLX5_ACCEL_TLS_V13 = BIT(3),
89 MLX5_ACCEL_TLS_LRO = BIT(4),
90 MLX5_ACCEL_TLS_IPV6 = BIT(5),
91 MLX5_ACCEL_TLS_AES_GCM128 = BIT(30),
92 MLX5_ACCEL_TLS_AES_GCM256 = BIT(31),
95 struct mlx5_ifc_tls_flow_bits {
98 union mlx5_ifc_ipv6_layout_ipv4_layout_auto_bits src_ipv4_src_ipv6;
99 union mlx5_ifc_ipv6_layout_ipv4_layout_auto_bits dst_ipv4_dst_ipv6;
101 u8 direction_sx[0x1];
102 u8 reserved_at_2[0x1e];
105 #ifdef CONFIG_MLX5_FPGA_TLS
106 int mlx5_accel_tls_add_flow(struct mlx5_core_dev *mdev, void *flow,
107 struct tls_crypto_info *crypto_info,
108 u32 start_offload_tcp_sn, u32 *p_swid,
110 void mlx5_accel_tls_del_flow(struct mlx5_core_dev *mdev, u32 swid,
112 int mlx5_accel_tls_resync_rx(struct mlx5_core_dev *mdev, u32 handle, u32 seq,
114 bool mlx5_accel_is_tls_device(struct mlx5_core_dev *mdev);
115 u32 mlx5_accel_tls_device_caps(struct mlx5_core_dev *mdev);
116 int mlx5_accel_tls_init(struct mlx5_core_dev *mdev);
117 void mlx5_accel_tls_cleanup(struct mlx5_core_dev *mdev);
122 mlx5_accel_tls_add_flow(struct mlx5_core_dev *mdev, void *flow,
123 struct tls_crypto_info *crypto_info,
124 u32 start_offload_tcp_sn, u32 *p_swid,
125 bool direction_sx) { return -ENOTSUPP; }
126 static inline void mlx5_accel_tls_del_flow(struct mlx5_core_dev *mdev, u32 swid,
127 bool direction_sx) { }
128 static inline int mlx5_accel_tls_resync_rx(struct mlx5_core_dev *mdev, u32 handle,
129 u32 seq, u64 rcd_sn) { return 0; }
130 static inline bool mlx5_accel_is_tls_device(struct mlx5_core_dev *mdev)
132 return mlx5_accel_is_ktls_device(mdev);
134 static inline u32 mlx5_accel_tls_device_caps(struct mlx5_core_dev *mdev) { return 0; }
135 static inline int mlx5_accel_tls_init(struct mlx5_core_dev *mdev) { return 0; }
136 static inline void mlx5_accel_tls_cleanup(struct mlx5_core_dev *mdev) { }
139 #endif /* __MLX5_ACCEL_TLS_H__ */