drivers/net/ethernet/mellanox/mlx4/en_tx.c

   1 /*
   2  * Copyright (c) 2007 Mellanox Technologies. All rights reserved.
   3  *
   4  * This software is available to you under a choice of one of two
   5  * licenses.  You may choose to be licensed under the terms of the GNU
   6  * General Public License (GPL) Version 2, available from the file
   7  * COPYING in the main directory of this source tree, or the
   8  * OpenIB.org BSD license below:
   9  *
  10  *     Redistribution and use in source and binary forms, with or
  11  *     without modification, are permitted provided that the following
  12  *     conditions are met:
  13  *
  14  *      - Redistributions of source code must retain the above
  15  *        copyright notice, this list of conditions and the following
  16  *        disclaimer.
  17  *
  18  *      - Redistributions in binary form must reproduce the above
  19  *        copyright notice, this list of conditions and the following
  20  *        disclaimer in the documentation and/or other materials
  21  *        provided with the distribution.
  22  *
  23  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  24  * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  25  * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
  26  * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
  27  * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
  28  * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
  29  * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
  30  * SOFTWARE.
  31  *
  32  */
  33
  34 #include <asm/page.h>
  35 #include <linux/mlx4/cq.h>
  36 #include <linux/slab.h>
  37 #include <linux/mlx4/qp.h>
  38 #include <linux/skbuff.h>
  39 #include <linux/if_vlan.h>
  40 #include <linux/prefetch.h>
  41 #include <linux/vmalloc.h>
  42 #include <linux/tcp.h>
  43 #include <linux/ip.h>
  44 #include <linux/moduleparam.h>
  45
  46 #include "mlx4_en.h"
  47
  48 int mlx4_en_create_tx_ring(struct mlx4_en_priv *priv,
  49                            struct mlx4_en_tx_ring **pring, int qpn, u32 size,
  50                            u16 stride, int node, int queue_index)
  51 {
  52         struct mlx4_en_dev *mdev = priv->mdev;
  53         struct mlx4_en_tx_ring *ring;
  54         int tmp;
  55         int err;
  56
  57         ring = kzalloc_node(sizeof(*ring), GFP_KERNEL, node);
  58         if (!ring) {
  59                 ring = kzalloc(sizeof(*ring), GFP_KERNEL);
  60                 if (!ring) {
  61                         en_err(priv, "Failed allocating TX ring\n");
  62                         return -ENOMEM;
  63                 }
  64         }
  65
  66         ring->size = size;
  67         ring->size_mask = size - 1;
  68         ring->stride = stride;
  69         ring->inline_thold = priv->prof->inline_thold;
  70
  71         tmp = size * sizeof(struct mlx4_en_tx_info);
  72         ring->tx_info = kmalloc_node(tmp, GFP_KERNEL | __GFP_NOWARN, node);
  73         if (!ring->tx_info) {
  74                 ring->tx_info = vmalloc(tmp);
  75                 if (!ring->tx_info) {
  76                         err = -ENOMEM;
  77                         goto err_ring;
  78                 }
  79         }
  80
  81         en_dbg(DRV, priv, "Allocated tx_info ring at addr:%p size:%d\n",
  82                  ring->tx_info, tmp);
  83
  84         ring->bounce_buf = kmalloc_node(MAX_DESC_SIZE, GFP_KERNEL, node);
  85         if (!ring->bounce_buf) {
  86                 ring->bounce_buf = kmalloc(MAX_DESC_SIZE, GFP_KERNEL);
  87                 if (!ring->bounce_buf) {
  88                         err = -ENOMEM;
  89                         goto err_info;
  90                 }
  91         }
  92         ring->buf_size = ALIGN(size * ring->stride, MLX4_EN_PAGE_SIZE);
  93
  94         /* Allocate HW buffers on provided NUMA node */
  95         set_dev_node(&mdev->dev->pdev->dev, node);
  96         err = mlx4_alloc_hwq_res(mdev->dev, &ring->wqres, ring->buf_size,
  97                                  2 * PAGE_SIZE);
  98         set_dev_node(&mdev->dev->pdev->dev, mdev->dev->numa_node);
  99         if (err) {
 100                 en_err(priv, "Failed allocating hwq resources\n");
 101                 goto err_bounce;
 102         }
 103
 104         err = mlx4_en_map_buffer(&ring->wqres.buf);
 105         if (err) {
 106                 en_err(priv, "Failed to map TX buffer\n");
 107                 goto err_hwq_res;
 108         }
 109
 110         ring->buf = ring->wqres.buf.direct.buf;
 111
 112         en_dbg(DRV, priv, "Allocated TX ring (addr:%p) - buf:%p size:%d buf_size:%d dma:%llx\n",
 113                ring, ring->buf, ring->size, ring->buf_size,
 114                (unsigned long long) ring->wqres.buf.direct.map);
 115
 116         ring->qpn = qpn;
 117         err = mlx4_qp_alloc(mdev->dev, ring->qpn, &ring->qp, GFP_KERNEL);
 118         if (err) {
 119                 en_err(priv, "Failed allocating qp %d\n", ring->qpn);
 120                 goto err_map;
 121         }
 122         ring->qp.event = mlx4_en_sqp_event;
 123
 124         err = mlx4_bf_alloc(mdev->dev, &ring->bf, node);
 125         if (err) {
 126                 en_dbg(DRV, priv, "working without blueflame (%d)\n", err);
 127                 ring->bf.uar = &mdev->priv_uar;
 128                 ring->bf.uar->map = mdev->uar_map;
 129                 ring->bf_enabled = false;
 130                 ring->bf_alloced = false;
 131                 priv->pflags &= ~MLX4_EN_PRIV_FLAGS_BLUEFLAME;
 132         } else {
 133                 ring->bf_alloced = true;
 134                 ring->bf_enabled = !!(priv->pflags &
 135                                       MLX4_EN_PRIV_FLAGS_BLUEFLAME);
 136         }
 137
 138         ring->hwtstamp_tx_type = priv->hwtstamp_config.tx_type;
 139         ring->queue_index = queue_index;
 140
 141         if (queue_index < priv->num_tx_rings_p_up && cpu_online(queue_index))
 142                 cpumask_set_cpu(queue_index, &ring->affinity_mask);
 143
 144         *pring = ring;
 145         return 0;
 146
 147 err_map:
 148         mlx4_en_unmap_buffer(&ring->wqres.buf);
 149 err_hwq_res:
 150         mlx4_free_hwq_res(mdev->dev, &ring->wqres, ring->buf_size);
 151 err_bounce:
 152         kfree(ring->bounce_buf);
 153         ring->bounce_buf = NULL;
 154 err_info:
 155         kvfree(ring->tx_info);
 156         ring->tx_info = NULL;
 157 err_ring:
 158         kfree(ring);
 159         *pring = NULL;
 160         return err;
 161 }
 162
 163 void mlx4_en_destroy_tx_ring(struct mlx4_en_priv *priv,
 164                              struct mlx4_en_tx_ring **pring)
 165 {
 166         struct mlx4_en_dev *mdev = priv->mdev;
 167         struct mlx4_en_tx_ring *ring = *pring;
 168         en_dbg(DRV, priv, "Destroying tx ring, qpn: %d\n", ring->qpn);
 169
 170         if (ring->bf_alloced)
 171                 mlx4_bf_free(mdev->dev, &ring->bf);
 172         mlx4_qp_remove(mdev->dev, &ring->qp);
 173         mlx4_qp_free(mdev->dev, &ring->qp);
 174         mlx4_en_unmap_buffer(&ring->wqres.buf);
 175         mlx4_free_hwq_res(mdev->dev, &ring->wqres, ring->buf_size);
 176         kfree(ring->bounce_buf);
 177         ring->bounce_buf = NULL;
 178         kvfree(ring->tx_info);
 179         ring->tx_info = NULL;
 180         kfree(ring);
 181         *pring = NULL;
 182 }
 183
 184 int mlx4_en_activate_tx_ring(struct mlx4_en_priv *priv,
 185                              struct mlx4_en_tx_ring *ring,
 186                              int cq, int user_prio)
 187 {
 188         struct mlx4_en_dev *mdev = priv->mdev;
 189         int err;
 190
 191         ring->cqn = cq;
 192         ring->prod = 0;
 193         ring->cons = 0xffffffff;
 194         ring->last_nr_txbb = 1;
 195         memset(ring->tx_info, 0, ring->size * sizeof(struct mlx4_en_tx_info));
 196         memset(ring->buf, 0, ring->buf_size);
 197
 198         ring->qp_state = MLX4_QP_STATE_RST;
 199         ring->doorbell_qpn = cpu_to_be32(ring->qp.qpn << 8);
 200         ring->mr_key = cpu_to_be32(mdev->mr.key);
 201
 202         mlx4_en_fill_qp_context(priv, ring->size, ring->stride, 1, 0, ring->qpn,
 203                                 ring->cqn, user_prio, &ring->context);
 204         if (ring->bf_alloced)
 205                 ring->context.usr_page = cpu_to_be32(ring->bf.uar->index);
 206
 207         err = mlx4_qp_to_ready(mdev->dev, &ring->wqres.mtt, &ring->context,
 208                                &ring->qp, &ring->qp_state);
 209         if (!user_prio && cpu_online(ring->queue_index))
 210                 netif_set_xps_queue(priv->dev, &ring->affinity_mask,
 211                                     ring->queue_index);
 212
 213         return err;
 214 }
 215
 216 void mlx4_en_deactivate_tx_ring(struct mlx4_en_priv *priv,
 217                                 struct mlx4_en_tx_ring *ring)
 218 {
 219         struct mlx4_en_dev *mdev = priv->mdev;
 220
 221         mlx4_qp_modify(mdev->dev, NULL, ring->qp_state,
 222                        MLX4_QP_STATE_RST, NULL, 0, 0, &ring->qp);
 223 }
 224
 225 static void mlx4_en_stamp_wqe(struct mlx4_en_priv *priv,
 226                               struct mlx4_en_tx_ring *ring, int index,
 227                               u8 owner)
 228 {
 229         __be32 stamp = cpu_to_be32(STAMP_VAL | (!!owner << STAMP_SHIFT));
 230         struct mlx4_en_tx_desc *tx_desc = ring->buf + index * TXBB_SIZE;
 231         struct mlx4_en_tx_info *tx_info = &ring->tx_info[index];
 232         void *end = ring->buf + ring->buf_size;
 233         __be32 *ptr = (__be32 *)tx_desc;
 234         int i;
 235
 236         /* Optimize the common case when there are no wraparounds */
 237         if (likely((void *)tx_desc + tx_info->nr_txbb * TXBB_SIZE <= end)) {
 238                 /* Stamp the freed descriptor */
 239                 for (i = 0; i < tx_info->nr_txbb * TXBB_SIZE;
 240                      i += STAMP_STRIDE) {
 241                         *ptr = stamp;
 242                         ptr += STAMP_DWORDS;
 243                 }
 244         } else {
 245                 /* Stamp the freed descriptor */
 246                 for (i = 0; i < tx_info->nr_txbb * TXBB_SIZE;
 247                      i += STAMP_STRIDE) {
 248                         *ptr = stamp;
 249                         ptr += STAMP_DWORDS;
 250                         if ((void *)ptr >= end) {
 251                                 ptr = ring->buf;
 252                                 stamp ^= cpu_to_be32(0x80000000);
 253                         }
 254                 }
 255         }
 256 }
 257
 258
 259 static u32 mlx4_en_free_tx_desc(struct mlx4_en_priv *priv,
 260                                 struct mlx4_en_tx_ring *ring,
 261                                 int index, u8 owner, u64 timestamp)
 262 {
 263         struct mlx4_en_tx_info *tx_info = &ring->tx_info[index];
 264         struct mlx4_en_tx_desc *tx_desc = ring->buf + index * TXBB_SIZE;
 265         struct mlx4_wqe_data_seg *data = (void *) tx_desc + tx_info->data_offset;
 266         void *end = ring->buf + ring->buf_size;
 267         struct sk_buff *skb = tx_info->skb;
 268         int nr_maps = tx_info->nr_maps;
 269         int i;
 270
 271         /* We do not touch skb here, so prefetch skb->users location
 272          * to speedup consume_skb()
 273          */
 274         prefetchw(&skb->users);
 275
 276         if (unlikely(timestamp)) {
 277                 struct skb_shared_hwtstamps hwts;
 278
 279                 mlx4_en_fill_hwtstamps(priv->mdev, &hwts, timestamp);
 280                 skb_tstamp_tx(skb, &hwts);
 281         }
 282
 283         /* Optimize the common case when there are no wraparounds */
 284         if (likely((void *) tx_desc + tx_info->nr_txbb * TXBB_SIZE <= end)) {
 285                 if (!tx_info->inl) {
 286                         if (tx_info->linear)
 287                                 dma_unmap_single(priv->ddev,
 288                                                 tx_info->map0_dma,
 289                                                 tx_info->map0_byte_count,
 290                                                 PCI_DMA_TODEVICE);
 291                         else
 292                                 dma_unmap_page(priv->ddev,
 293                                                tx_info->map0_dma,
 294                                                tx_info->map0_byte_count,
 295                                                PCI_DMA_TODEVICE);
 296                         for (i = 1; i < nr_maps; i++) {
 297                                 data++;
 298                                 dma_unmap_page(priv->ddev,
 299                                         (dma_addr_t)be64_to_cpu(data->addr),
 300                                         be32_to_cpu(data->byte_count),
 301                                         PCI_DMA_TODEVICE);
 302                         }
 303                 }
 304         } else {
 305                 if (!tx_info->inl) {
 306                         if ((void *) data >= end) {
 307                                 data = ring->buf + ((void *)data - end);
 308                         }
 309
 310                         if (tx_info->linear)
 311                                 dma_unmap_single(priv->ddev,
 312                                                 tx_info->map0_dma,
 313                                                 tx_info->map0_byte_count,
 314                                                 PCI_DMA_TODEVICE);
 315                         else
 316                                 dma_unmap_page(priv->ddev,
 317                                                tx_info->map0_dma,
 318                                                tx_info->map0_byte_count,
 319                                                PCI_DMA_TODEVICE);
 320                         for (i = 1; i < nr_maps; i++) {
 321                                 data++;
 322                                 /* Check for wraparound before unmapping */
 323                                 if ((void *) data >= end)
 324                                         data = ring->buf;
 325                                 dma_unmap_page(priv->ddev,
 326                                         (dma_addr_t)be64_to_cpu(data->addr),
 327                                         be32_to_cpu(data->byte_count),
 328                                         PCI_DMA_TODEVICE);
 329                         }
 330                 }
 331         }
 332         dev_consume_skb_any(skb);
 333         return tx_info->nr_txbb;
 334 }
 335
 336
 337 int mlx4_en_free_tx_buf(struct net_device *dev, struct mlx4_en_tx_ring *ring)
 338 {
 339         struct mlx4_en_priv *priv = netdev_priv(dev);
 340         int cnt = 0;
 341
 342         /* Skip last polled descriptor */
 343         ring->cons += ring->last_nr_txbb;
 344         en_dbg(DRV, priv, "Freeing Tx buf - cons:0x%x prod:0x%x\n",
 345                  ring->cons, ring->prod);
 346
 347         if ((u32) (ring->prod - ring->cons) > ring->size) {
 348                 if (netif_msg_tx_err(priv))
 349                         en_warn(priv, "Tx consumer passed producer!\n");
 350                 return 0;
 351         }
 352
 353         while (ring->cons != ring->prod) {
 354                 ring->last_nr_txbb = mlx4_en_free_tx_desc(priv, ring,
 355                                                 ring->cons & ring->size_mask,
 356                                                 !!(ring->cons & ring->size), 0);
 357                 ring->cons += ring->last_nr_txbb;
 358                 cnt++;
 359         }
 360
 361         netdev_tx_reset_queue(ring->tx_queue);
 362
 363         if (cnt)
 364                 en_dbg(DRV, priv, "Freed %d uncompleted tx descriptors\n", cnt);
 365
 366         return cnt;
 367 }
 368
 369 static bool mlx4_en_process_tx_cq(struct net_device *dev,
 370                                  struct mlx4_en_cq *cq)
 371 {
 372         struct mlx4_en_priv *priv = netdev_priv(dev);
 373         struct mlx4_cq *mcq = &cq->mcq;
 374         struct mlx4_en_tx_ring *ring = priv->tx_ring[cq->ring];
 375         struct mlx4_cqe *cqe;
 376         u16 index;
 377         u16 new_index, ring_index, stamp_index;
 378         u32 txbbs_skipped = 0;
 379         u32 txbbs_stamp = 0;
 380         u32 cons_index = mcq->cons_index;
 381         int size = cq->size;
 382         u32 size_mask = ring->size_mask;
 383         struct mlx4_cqe *buf = cq->buf;
 384         u32 packets = 0;
 385         u32 bytes = 0;
 386         int factor = priv->cqe_factor;
 387         u64 timestamp = 0;
 388         int done = 0;
 389         int budget = priv->tx_work_limit;
 390         u32 last_nr_txbb;
 391         u32 ring_cons;
 392
 393         if (!priv->port_up)
 394                 return true;
 395
 396         prefetchw(&ring->tx_queue->dql.limit);
 397         index = cons_index & size_mask;
 398         cqe = mlx4_en_get_cqe(buf, index, priv->cqe_size) + factor;
 399         last_nr_txbb = ACCESS_ONCE(ring->last_nr_txbb);
 400         ring_cons = ACCESS_ONCE(ring->cons);
 401         ring_index = ring_cons & size_mask;
 402         stamp_index = ring_index;
 403
 404         /* Process all completed CQEs */
 405         while (XNOR(cqe->owner_sr_opcode & MLX4_CQE_OWNER_MASK,
 406                         cons_index & size) && (done < budget)) {
 407                 /*
 408                  * make sure we read the CQE after we read the
 409                  * ownership bit
 410                  */
 411                 rmb();
 412
 413                 if (unlikely((cqe->owner_sr_opcode & MLX4_CQE_OPCODE_MASK) ==
 414                              MLX4_CQE_OPCODE_ERROR)) {
 415                         struct mlx4_err_cqe *cqe_err = (struct mlx4_err_cqe *)cqe;
 416
 417                         en_err(priv, "CQE error - vendor syndrome: 0x%x syndrome: 0x%x\n",
 418                                cqe_err->vendor_err_syndrome,
 419                                cqe_err->syndrome);
 420                 }
 421
 422                 /* Skip over last polled CQE */
 423                 new_index = be16_to_cpu(cqe->wqe_index) & size_mask;
 424
 425                 do {
 426                         txbbs_skipped += last_nr_txbb;
 427                         ring_index = (ring_index + last_nr_txbb) & size_mask;
 428                         if (ring->tx_info[ring_index].ts_requested)
 429                                 timestamp = mlx4_en_get_cqe_ts(cqe);
 430
 431                         /* free next descriptor */
 432                         last_nr_txbb = mlx4_en_free_tx_desc(
 433                                         priv, ring, ring_index,
 434                                         !!((ring_cons + txbbs_skipped) &
 435                                         ring->size), timestamp);
 436
 437                         mlx4_en_stamp_wqe(priv, ring, stamp_index,
 438                                           !!((ring_cons + txbbs_stamp) &
 439                                                 ring->size));
 440                         stamp_index = ring_index;
 441                         txbbs_stamp = txbbs_skipped;
 442                         packets++;
 443                         bytes += ring->tx_info[ring_index].nr_bytes;
 444                 } while ((++done < budget) && (ring_index != new_index));
 445
 446                 ++cons_index;
 447                 index = cons_index & size_mask;
 448                 cqe = mlx4_en_get_cqe(buf, index, priv->cqe_size) + factor;
 449         }
 450
 451
 452         /*
 453          * To prevent CQ overflow we first update CQ consumer and only then
 454          * the ring consumer.
 455          */
 456         mcq->cons_index = cons_index;
 457         mlx4_cq_set_ci(mcq);
 458         wmb();
 459
 460         /* we want to dirty this cache line once */
 461         ACCESS_ONCE(ring->last_nr_txbb) = last_nr_txbb;
 462         ACCESS_ONCE(ring->cons) = ring_cons + txbbs_skipped;
 463
 464         netdev_tx_completed_queue(ring->tx_queue, packets, bytes);
 465
 466         /*
 467          * Wakeup Tx queue if this stopped, and at least 1 packet
 468          * was completed
 469          */
 470         if (netif_tx_queue_stopped(ring->tx_queue) && txbbs_skipped > 0) {
 471                 netif_tx_wake_queue(ring->tx_queue);
 472                 ring->wake_queue++;
 473         }
 474         return done < budget;
 475 }
 476
 477 void mlx4_en_tx_irq(struct mlx4_cq *mcq)
 478 {
 479         struct mlx4_en_cq *cq = container_of(mcq, struct mlx4_en_cq, mcq);
 480         struct mlx4_en_priv *priv = netdev_priv(cq->dev);
 481
 482         if (priv->port_up)
 483                 napi_schedule(&cq->napi);
 484         else
 485                 mlx4_en_arm_cq(priv, cq);
 486 }
 487
 488 /* TX CQ polling - called by NAPI */
 489 int mlx4_en_poll_tx_cq(struct napi_struct *napi, int budget)
 490 {
 491         struct mlx4_en_cq *cq = container_of(napi, struct mlx4_en_cq, napi);
 492         struct net_device *dev = cq->dev;
 493         struct mlx4_en_priv *priv = netdev_priv(dev);
 494         int clean_complete;
 495
 496         clean_complete = mlx4_en_process_tx_cq(dev, cq);
 497         if (!clean_complete)
 498                 return budget;
 499
 500         napi_complete(napi);
 501         mlx4_en_arm_cq(priv, cq);
 502
 503         return 0;
 504 }
 505
 506 static struct mlx4_en_tx_desc *mlx4_en_bounce_to_desc(struct mlx4_en_priv *priv,
 507                                                       struct mlx4_en_tx_ring *ring,
 508                                                       u32 index,
 509                                                       unsigned int desc_size)
 510 {
 511         u32 copy = (ring->size - index) * TXBB_SIZE;
 512         int i;
 513
 514         for (i = desc_size - copy - 4; i >= 0; i -= 4) {
 515                 if ((i & (TXBB_SIZE - 1)) == 0)
 516                         wmb();
 517
 518                 *((u32 *) (ring->buf + i)) =
 519                         *((u32 *) (ring->bounce_buf + copy + i));
 520         }
 521
 522         for (i = copy - 4; i >= 4 ; i -= 4) {
 523                 if ((i & (TXBB_SIZE - 1)) == 0)
 524                         wmb();
 525
 526                 *((u32 *) (ring->buf + index * TXBB_SIZE + i)) =
 527                         *((u32 *) (ring->bounce_buf + i));
 528         }
 529
 530         /* Return real descriptor location */
 531         return ring->buf + index * TXBB_SIZE;
 532 }
 533
 534 static bool is_inline(int inline_thold, const struct sk_buff *skb,
 535                       const struct skb_shared_info *shinfo,
 536                       void **pfrag)
 537 {
 538         void *ptr;
 539
 540         if (inline_thold && !skb_is_gso(skb) && skb->len <= inline_thold) {
 541                 if (shinfo->nr_frags == 1) {
 542                         ptr = skb_frag_address_safe(&shinfo->frags[0]);
 543                         if (unlikely(!ptr))
 544                                 return 0;
 545
 546                         if (pfrag)
 547                                 *pfrag = ptr;
 548
 549                         return 1;
 550                 } else if (unlikely(shinfo->nr_frags))
 551                         return 0;
 552                 else
 553                         return 1;
 554         }
 555
 556         return 0;
 557 }
 558
 559 static int inline_size(const struct sk_buff *skb)
 560 {
 561         if (skb->len + CTRL_SIZE + sizeof(struct mlx4_wqe_inline_seg)
 562             <= MLX4_INLINE_ALIGN)
 563                 return ALIGN(skb->len + CTRL_SIZE +
 564                              sizeof(struct mlx4_wqe_inline_seg), 16);
 565         else
 566                 return ALIGN(skb->len + CTRL_SIZE + 2 *
 567                              sizeof(struct mlx4_wqe_inline_seg), 16);
 568 }
 569
 570 static int get_real_size(const struct sk_buff *skb,
 571                          const struct skb_shared_info *shinfo,
 572                          struct net_device *dev,
 573                          int *lso_header_size)
 574 {
 575         struct mlx4_en_priv *priv = netdev_priv(dev);
 576         int real_size;
 577
 578         if (shinfo->gso_size) {
 579                 if (skb->encapsulation)
 580                         *lso_header_size = (skb_inner_transport_header(skb) - skb->data) + inner_tcp_hdrlen(skb);
 581                 else
 582                         *lso_header_size = skb_transport_offset(skb) + tcp_hdrlen(skb);
 583                 real_size = CTRL_SIZE + shinfo->nr_frags * DS_SIZE +
 584                         ALIGN(*lso_header_size + 4, DS_SIZE);
 585                 if (unlikely(*lso_header_size != skb_headlen(skb))) {
 586                         /* We add a segment for the skb linear buffer only if
 587                          * it contains data */
 588                         if (*lso_header_size < skb_headlen(skb))
 589                                 real_size += DS_SIZE;
 590                         else {
 591                                 if (netif_msg_tx_err(priv))
 592                                         en_warn(priv, "Non-linear headers\n");
 593                                 return 0;
 594                         }
 595                 }
 596         } else {
 597                 *lso_header_size = 0;
 598                 if (!is_inline(priv->prof->inline_thold, skb, shinfo, NULL))
 599                         real_size = CTRL_SIZE + (shinfo->nr_frags + 1) * DS_SIZE;
 600                 else
 601                         real_size = inline_size(skb);
 602         }
 603
 604         return real_size;
 605 }
 606
 607 static void build_inline_wqe(struct mlx4_en_tx_desc *tx_desc,
 608                              const struct sk_buff *skb,
 609                              const struct skb_shared_info *shinfo,
 610                              int real_size, u16 *vlan_tag,
 611                              int tx_ind, void *fragptr)
 612 {
 613         struct mlx4_wqe_inline_seg *inl = &tx_desc->inl;
 614         int spc = MLX4_INLINE_ALIGN - CTRL_SIZE - sizeof *inl;
 615         unsigned int hlen = skb_headlen(skb);
 616
 617         if (skb->len <= spc) {
 618                 if (likely(skb->len >= MIN_PKT_LEN)) {
 619                         inl->byte_count = cpu_to_be32(1 << 31 | skb->len);
 620                 } else {
 621                         inl->byte_count = cpu_to_be32(1 << 31 | MIN_PKT_LEN);
 622                         memset(((void *)(inl + 1)) + skb->len, 0,
 623                                MIN_PKT_LEN - skb->len);
 624                 }
 625                 skb_copy_from_linear_data(skb, inl + 1, hlen);
 626                 if (shinfo->nr_frags)
 627                         memcpy(((void *)(inl + 1)) + hlen, fragptr,
 628                                skb_frag_size(&shinfo->frags[0]));
 629
 630         } else {
 631                 inl->byte_count = cpu_to_be32(1 << 31 | spc);
 632                 if (hlen <= spc) {
 633                         skb_copy_from_linear_data(skb, inl + 1, hlen);
 634                         if (hlen < spc) {
 635                                 memcpy(((void *)(inl + 1)) + hlen,
 636                                        fragptr, spc - hlen);
 637                                 fragptr +=  spc - hlen;
 638                         }
 639                         inl = (void *) (inl + 1) + spc;
 640                         memcpy(((void *)(inl + 1)), fragptr, skb->len - spc);
 641                 } else {
 642                         skb_copy_from_linear_data(skb, inl + 1, spc);
 643                         inl = (void *) (inl + 1) + spc;
 644                         skb_copy_from_linear_data_offset(skb, spc, inl + 1,
 645                                                          hlen - spc);
 646                         if (shinfo->nr_frags)
 647                                 memcpy(((void *)(inl + 1)) + hlen - spc,
 648                                        fragptr,
 649                                        skb_frag_size(&shinfo->frags[0]));
 650                 }
 651
 652                 wmb();
 653                 inl->byte_count = cpu_to_be32(1 << 31 | (skb->len - spc));
 654         }
 655 }
 656
 657 u16 mlx4_en_select_queue(struct net_device *dev, struct sk_buff *skb,
 658                          void *accel_priv, select_queue_fallback_t fallback)
 659 {
 660         struct mlx4_en_priv *priv = netdev_priv(dev);
 661         u16 rings_p_up = priv->num_tx_rings_p_up;
 662         u8 up = 0;
 663
 664         if (dev->num_tc)
 665                 return skb_tx_hash(dev, skb);
 666
 667         if (vlan_tx_tag_present(skb))
 668                 up = vlan_tx_tag_get(skb) >> VLAN_PRIO_SHIFT;
 669
 670         return fallback(dev, skb) % rings_p_up + up * rings_p_up;
 671 }
 672
 673 static void mlx4_bf_copy(void __iomem *dst, const void *src,
 674                          unsigned int bytecnt)
 675 {
 676         __iowrite64_copy(dst, src, bytecnt / 8);
 677 }
 678
 679 netdev_tx_t mlx4_en_xmit(struct sk_buff *skb, struct net_device *dev)
 680 {
 681         struct skb_shared_info *shinfo = skb_shinfo(skb);
 682         struct mlx4_en_priv *priv = netdev_priv(dev);
 683         struct device *ddev = priv->ddev;
 684         struct mlx4_en_tx_ring *ring;
 685         struct mlx4_en_tx_desc *tx_desc;
 686         struct mlx4_wqe_data_seg *data;
 687         struct mlx4_en_tx_info *tx_info;
 688         int tx_ind = 0;
 689         int nr_txbb;
 690         int desc_size;
 691         int real_size;
 692         u32 index, bf_index;
 693         __be32 op_own;
 694         u16 vlan_tag = 0;
 695         int i_frag;
 696         int lso_header_size;
 697         void *fragptr;
 698         bool bounce = false;
 699         bool send_doorbell;
 700         u32 ring_cons;
 701
 702         if (!priv->port_up)
 703                 goto tx_drop;
 704
 705         tx_ind = skb_get_queue_mapping(skb);
 706         ring = priv->tx_ring[tx_ind];
 707
 708         /* fetch ring->cons far ahead before needing it to avoid stall */
 709         ring_cons = ACCESS_ONCE(ring->cons);
 710
 711         real_size = get_real_size(skb, shinfo, dev, &lso_header_size);
 712         if (unlikely(!real_size))
 713                 goto tx_drop;
 714
 715         /* Align descriptor to TXBB size */
 716         desc_size = ALIGN(real_size, TXBB_SIZE);
 717         nr_txbb = desc_size / TXBB_SIZE;
 718         if (unlikely(nr_txbb > MAX_DESC_TXBBS)) {
 719                 if (netif_msg_tx_err(priv))
 720                         en_warn(priv, "Oversized header or SG list\n");
 721                 goto tx_drop;
 722         }
 723
 724         if (vlan_tx_tag_present(skb))
 725                 vlan_tag = vlan_tx_tag_get(skb);
 726
 727         /* Check available TXBBs And 2K spare for prefetch */
 728         if (unlikely(((int)(ring->prod - ring_cons)) >
 729                      ring->size - HEADROOM - MAX_DESC_TXBBS)) {
 730                 /* every full Tx ring stops queue */
 731                 netif_tx_stop_queue(ring->tx_queue);
 732                 ring->queue_stopped++;
 733
 734                 /* If queue was emptied after the if, and before the
 735                  * stop_queue - need to wake the queue, or else it will remain
 736                  * stopped forever.
 737                  * Need a memory barrier to make sure ring->cons was not
 738                  * updated before queue was stopped.
 739                  */
 740                 wmb();
 741
 742                 ring_cons = ACCESS_ONCE(ring->cons);
 743                 if (unlikely(((int)(ring->prod - ring_cons)) <=
 744                              ring->size - HEADROOM - MAX_DESC_TXBBS)) {
 745                         netif_tx_wake_queue(ring->tx_queue);
 746                         ring->wake_queue++;
 747                 } else {
 748                         return NETDEV_TX_BUSY;
 749                 }
 750         }
 751
 752         prefetchw(&ring->tx_queue->dql);
 753
 754         /* Track current inflight packets for performance analysis */
 755         AVG_PERF_COUNTER(priv->pstats.inflight_avg,
 756                          (u32)(ring->prod - ring_cons - 1));
 757
 758         /* Packet is good - grab an index and transmit it */
 759         index = ring->prod & ring->size_mask;
 760         bf_index = ring->prod;
 761
 762         /* See if we have enough space for whole descriptor TXBB for setting
 763          * SW ownership on next descriptor; if not, use a bounce buffer. */
 764         if (likely(index + nr_txbb <= ring->size))
 765                 tx_desc = ring->buf + index * TXBB_SIZE;
 766         else {
 767                 tx_desc = (struct mlx4_en_tx_desc *) ring->bounce_buf;
 768                 bounce = true;
 769         }
 770
 771         /* Save skb in tx_info ring */
 772         tx_info = &ring->tx_info[index];
 773         tx_info->skb = skb;
 774         tx_info->nr_txbb = nr_txbb;
 775
 776         data = &tx_desc->data;
 777         if (lso_header_size)
 778                 data = ((void *)&tx_desc->lso + ALIGN(lso_header_size + 4,
 779                                                       DS_SIZE));
 780
 781         /* valid only for none inline segments */
 782         tx_info->data_offset = (void *)data - (void *)tx_desc;
 783
 784         tx_info->linear = (lso_header_size < skb_headlen(skb) &&
 785                            !is_inline(ring->inline_thold, skb, shinfo, NULL)) ? 1 : 0;
 786
 787         tx_info->nr_maps = shinfo->nr_frags + tx_info->linear;
 788         data += tx_info->nr_maps - 1;
 789
 790         if (is_inline(ring->inline_thold, skb, shinfo, &fragptr)) {
 791                 tx_info->inl = 1;
 792         } else {
 793                 dma_addr_t dma = 0;
 794                 u32 byte_count = 0;
 795
 796                 /* Map fragments if any */
 797                 for (i_frag = shinfo->nr_frags - 1; i_frag >= 0; i_frag--) {
 798                         const struct skb_frag_struct *frag;
 799
 800                         frag = &shinfo->frags[i_frag];
 801                         byte_count = skb_frag_size(frag);
 802                         dma = skb_frag_dma_map(ddev, frag,
 803                                                0, byte_count,
 804                                                DMA_TO_DEVICE);
 805                         if (dma_mapping_error(ddev, dma))
 806                                 goto tx_drop_unmap;
 807
 808                         data->addr = cpu_to_be64(dma);
 809                         data->lkey = ring->mr_key;
 810                         wmb();
 811                         data->byte_count = cpu_to_be32(byte_count);
 812                         --data;
 813                 }
 814
 815                 /* Map linear part if needed */
 816                 if (tx_info->linear) {
 817                         byte_count = skb_headlen(skb) - lso_header_size;
 818
 819                         dma = dma_map_single(ddev, skb->data +
 820                                              lso_header_size, byte_count,
 821                                              PCI_DMA_TODEVICE);
 822                         if (dma_mapping_error(ddev, dma))
 823                                 goto tx_drop_unmap;
 824
 825                         data->addr = cpu_to_be64(dma);
 826                         data->lkey = ring->mr_key;
 827                         wmb();
 828                         data->byte_count = cpu_to_be32(byte_count);
 829                 }
 830                 tx_info->inl = 0;
 831                 /* tx completion can avoid cache line miss for common cases */
 832                 tx_info->map0_dma = dma;
 833                 tx_info->map0_byte_count = byte_count;
 834         }
 835
 836         /*
 837          * For timestamping add flag to skb_shinfo and
 838          * set flag for further reference
 839          */
 840         if (unlikely(ring->hwtstamp_tx_type == HWTSTAMP_TX_ON &&
 841                      shinfo->tx_flags & SKBTX_HW_TSTAMP)) {
 842                 shinfo->tx_flags |= SKBTX_IN_PROGRESS;
 843                 tx_info->ts_requested = 1;
 844         }
 845
 846         /* Prepare ctrl segement apart opcode+ownership, which depends on
 847          * whether LSO is used */
 848         tx_desc->ctrl.srcrb_flags = priv->ctrl_flags;
 849         if (likely(skb->ip_summed == CHECKSUM_PARTIAL)) {
 850                 tx_desc->ctrl.srcrb_flags |= cpu_to_be32(MLX4_WQE_CTRL_IP_CSUM |
 851                                                          MLX4_WQE_CTRL_TCP_UDP_CSUM);
 852                 ring->tx_csum++;
 853         }
 854
 855         if (priv->flags & MLX4_EN_FLAG_ENABLE_HW_LOOPBACK) {
 856                 struct ethhdr *ethh;
 857
 858                 /* Copy dst mac address to wqe. This allows loopback in eSwitch,
 859                  * so that VFs and PF can communicate with each other
 860                  */
 861                 ethh = (struct ethhdr *)skb->data;
 862                 tx_desc->ctrl.srcrb_flags16[0] = get_unaligned((__be16 *)ethh->h_dest);
 863                 tx_desc->ctrl.imm = get_unaligned((__be32 *)(ethh->h_dest + 2));
 864         }
 865
 866         /* Handle LSO (TSO) packets */
 867         if (lso_header_size) {
 868                 int i;
 869
 870                 /* Mark opcode as LSO */
 871                 op_own = cpu_to_be32(MLX4_OPCODE_LSO | (1 << 6)) |
 872                         ((ring->prod & ring->size) ?
 873                                 cpu_to_be32(MLX4_EN_BIT_DESC_OWN) : 0);
 874
 875                 /* Fill in the LSO prefix */
 876                 tx_desc->lso.mss_hdr_size = cpu_to_be32(
 877                         shinfo->gso_size << 16 | lso_header_size);
 878
 879                 /* Copy headers;
 880                  * note that we already verified that it is linear */
 881                 memcpy(tx_desc->lso.header, skb->data, lso_header_size);
 882
 883                 ring->tso_packets++;
 884
 885                 i = ((skb->len - lso_header_size) / shinfo->gso_size) +
 886                         !!((skb->len - lso_header_size) % shinfo->gso_size);
 887                 tx_info->nr_bytes = skb->len + (i - 1) * lso_header_size;
 888                 ring->packets += i;
 889         } else {
 890                 /* Normal (Non LSO) packet */
 891                 op_own = cpu_to_be32(MLX4_OPCODE_SEND) |
 892                         ((ring->prod & ring->size) ?
 893                          cpu_to_be32(MLX4_EN_BIT_DESC_OWN) : 0);
 894                 tx_info->nr_bytes = max_t(unsigned int, skb->len, ETH_ZLEN);
 895                 ring->packets++;
 896         }
 897         ring->bytes += tx_info->nr_bytes;
 898         netdev_tx_sent_queue(ring->tx_queue, tx_info->nr_bytes);
 899         AVG_PERF_COUNTER(priv->pstats.tx_pktsz_avg, skb->len);
 900
 901         if (tx_info->inl) {
 902                 build_inline_wqe(tx_desc, skb, shinfo, real_size, &vlan_tag,
 903                                  tx_ind, fragptr);
 904                 tx_info->inl = 1;
 905         }
 906
 907         if (skb->encapsulation) {
 908                 struct iphdr *ipv4 = (struct iphdr *)skb_inner_network_header(skb);
 909                 if (ipv4->protocol == IPPROTO_TCP || ipv4->protocol == IPPROTO_UDP)
 910                         op_own |= cpu_to_be32(MLX4_WQE_CTRL_IIP | MLX4_WQE_CTRL_ILP);
 911                 else
 912                         op_own |= cpu_to_be32(MLX4_WQE_CTRL_IIP);
 913         }
 914
 915         ring->prod += nr_txbb;
 916
 917         /* If we used a bounce buffer then copy descriptor back into place */
 918         if (unlikely(bounce))
 919                 tx_desc = mlx4_en_bounce_to_desc(priv, ring, index, desc_size);
 920
 921         skb_tx_timestamp(skb);
 922
 923         send_doorbell = !skb->xmit_more || netif_xmit_stopped(ring->tx_queue);
 924
 925         real_size = (real_size / 16) & 0x3f;
 926
 927         if (ring->bf_enabled && desc_size <= MAX_BF && !bounce &&
 928             !vlan_tx_tag_present(skb) && send_doorbell) {
 929                 tx_desc->ctrl.bf_qpn = ring->doorbell_qpn |
 930                                        cpu_to_be32(real_size);
 931
 932                 op_own |= htonl((bf_index & 0xffff) << 8);
 933                 /* Ensure new descriptor hits memory
 934                  * before setting ownership of this descriptor to HW
 935                  */
 936                 wmb();
 937                 tx_desc->ctrl.owner_opcode = op_own;
 938
 939                 wmb();
 940
 941                 mlx4_bf_copy(ring->bf.reg + ring->bf.offset, &tx_desc->ctrl,
 942                              desc_size);
 943
 944                 wmb();
 945
 946                 ring->bf.offset ^= ring->bf.buf_size;
 947         } else {
 948                 tx_desc->ctrl.vlan_tag = cpu_to_be16(vlan_tag);
 949                 tx_desc->ctrl.ins_vlan = MLX4_WQE_CTRL_INS_VLAN *
 950                         !!vlan_tx_tag_present(skb);
 951                 tx_desc->ctrl.fence_size = real_size;
 952
 953                 /* Ensure new descriptor hits memory
 954                  * before setting ownership of this descriptor to HW
 955                  */
 956                 wmb();
 957                 tx_desc->ctrl.owner_opcode = op_own;
 958                 if (send_doorbell) {
 959                         wmb();
 960                         iowrite32(ring->doorbell_qpn,
 961                                   ring->bf.uar->map + MLX4_SEND_DOORBELL);
 962                 } else {
 963                         ring->xmit_more++;
 964                 }
 965         }
 966
 967         return NETDEV_TX_OK;
 968
 969 tx_drop_unmap:
 970         en_err(priv, "DMA mapping error\n");
 971
 972         while (++i_frag < shinfo->nr_frags) {
 973                 ++data;
 974                 dma_unmap_page(ddev, (dma_addr_t) be64_to_cpu(data->addr),
 975                                be32_to_cpu(data->byte_count),
 976                                PCI_DMA_TODEVICE);
 977         }
 978
 979 tx_drop:
 980         dev_kfree_skb_any(skb);
 981         priv->stats.tx_dropped++;
 982         return NETDEV_TX_OK;
 983 }
 984