1 /* SPDX-License-Identifier: GPL-2.0-only */
4 * Copyright (C) 2009-2016 John Crispin <blogic@openwrt.org>
5 * Copyright (C) 2009-2016 Felix Fietkau <nbd@openwrt.org>
6 * Copyright (C) 2013-2016 Michael Lee <igvtee@gmail.com>
12 #include <linux/dma-mapping.h>
13 #include <linux/netdevice.h>
14 #include <linux/of_net.h>
15 #include <linux/u64_stats_sync.h>
16 #include <linux/refcount.h>
17 #include <linux/phylink.h>
18 #include <linux/rhashtable.h>
19 #include <linux/dim.h>
22 #define MTK_QDMA_PAGE_SIZE 2048
23 #define MTK_MAX_RX_LENGTH 1536
24 #define MTK_MAX_RX_LENGTH_2K 2048
25 #define MTK_TX_DMA_BUF_LEN 0x3fff
26 #define MTK_DMA_SIZE 512
27 #define MTK_NAPI_WEIGHT 64
28 #define MTK_MAC_COUNT 2
29 #define MTK_RX_ETH_HLEN (ETH_HLEN + ETH_FCS_LEN)
30 #define MTK_RX_HLEN (NET_SKB_PAD + MTK_RX_ETH_HLEN + NET_IP_ALIGN)
31 #define MTK_DMA_DUMMY_DESC 0xffffffff
32 #define MTK_DEFAULT_MSG_ENABLE (NETIF_MSG_DRV | \
40 #define MTK_HW_FEATURES (NETIF_F_IP_CSUM | \
42 NETIF_F_HW_VLAN_CTAG_TX | \
43 NETIF_F_HW_VLAN_CTAG_RX | \
44 NETIF_F_SG | NETIF_F_TSO | \
48 #define MTK_HW_FEATURES_MT7628 (NETIF_F_SG | NETIF_F_RXCSUM)
49 #define NEXT_DESP_IDX(X, Y) (((X) + 1) & ((Y) - 1))
51 #define MTK_MAX_RX_RING_NUM 4
52 #define MTK_HW_LRO_DMA_SIZE 8
54 #define MTK_MAX_LRO_RX_LENGTH (4096 * 3)
55 #define MTK_MAX_LRO_IP_CNT 2
56 #define MTK_HW_LRO_TIMER_UNIT 1 /* 20 us */
57 #define MTK_HW_LRO_REFRESH_TIME 50000 /* 1 sec. */
58 #define MTK_HW_LRO_AGG_TIME 10 /* 200us */
59 #define MTK_HW_LRO_AGE_TIME 50 /* 1ms */
60 #define MTK_HW_LRO_MAX_AGG_CNT 64
61 #define MTK_HW_LRO_BW_THRE 3000
62 #define MTK_HW_LRO_REPLACE_DELTA 1000
63 #define MTK_HW_LRO_SDL_REMAIN_ROOM 1522
65 /* Frame Engine Global Reset Register */
66 #define MTK_RST_GL 0x04
67 #define RST_GL_PSE BIT(0)
69 /* Frame Engine Interrupt Status Register */
70 #define MTK_INT_STATUS2 0x08
71 #define MTK_GDM1_AF BIT(28)
72 #define MTK_GDM2_AF BIT(29)
74 /* PDMA HW LRO Alter Flow Timer Register */
75 #define MTK_PDMA_LRO_ALT_REFRESH_TIMER 0x1c
77 /* Frame Engine Interrupt Grouping Register */
78 #define MTK_FE_INT_GRP 0x20
80 /* CDMP Ingress Control Register */
81 #define MTK_CDMQ_IG_CTRL 0x1400
82 #define MTK_CDMQ_STAG_EN BIT(0)
84 /* CDMP Exgress Control Register */
85 #define MTK_CDMP_EG_CTRL 0x404
87 /* GDM Exgress Control Register */
88 #define MTK_GDMA_FWD_CFG(x) (0x500 + (x * 0x1000))
89 #define MTK_GDMA_SPECIAL_TAG BIT(24)
90 #define MTK_GDMA_ICS_EN BIT(22)
91 #define MTK_GDMA_TCS_EN BIT(21)
92 #define MTK_GDMA_UCS_EN BIT(20)
93 #define MTK_GDMA_TO_PDMA 0x0
94 #define MTK_GDMA_TO_PPE 0x4444
95 #define MTK_GDMA_DROP_ALL 0x7777
97 /* Unicast Filter MAC Address Register - Low */
98 #define MTK_GDMA_MAC_ADRL(x) (0x508 + (x * 0x1000))
100 /* Unicast Filter MAC Address Register - High */
101 #define MTK_GDMA_MAC_ADRH(x) (0x50C + (x * 0x1000))
103 /* PDMA RX Base Pointer Register */
104 #define MTK_PRX_BASE_PTR0 0x900
105 #define MTK_PRX_BASE_PTR_CFG(x) (MTK_PRX_BASE_PTR0 + (x * 0x10))
107 /* PDMA RX Maximum Count Register */
108 #define MTK_PRX_MAX_CNT0 0x904
109 #define MTK_PRX_MAX_CNT_CFG(x) (MTK_PRX_MAX_CNT0 + (x * 0x10))
111 /* PDMA RX CPU Pointer Register */
112 #define MTK_PRX_CRX_IDX0 0x908
113 #define MTK_PRX_CRX_IDX_CFG(x) (MTK_PRX_CRX_IDX0 + (x * 0x10))
115 /* PDMA HW LRO Control Registers */
116 #define MTK_PDMA_LRO_CTRL_DW0 0x980
117 #define MTK_LRO_EN BIT(0)
118 #define MTK_L3_CKS_UPD_EN BIT(7)
119 #define MTK_LRO_ALT_PKT_CNT_MODE BIT(21)
120 #define MTK_LRO_RING_RELINQUISH_REQ (0x7 << 26)
121 #define MTK_LRO_RING_RELINQUISH_DONE (0x7 << 29)
123 #define MTK_PDMA_LRO_CTRL_DW1 0x984
124 #define MTK_PDMA_LRO_CTRL_DW2 0x988
125 #define MTK_PDMA_LRO_CTRL_DW3 0x98c
126 #define MTK_ADMA_MODE BIT(15)
127 #define MTK_LRO_MIN_RXD_SDL (MTK_HW_LRO_SDL_REMAIN_ROOM << 16)
129 /* PDMA Global Configuration Register */
130 #define MTK_PDMA_GLO_CFG 0xa04
131 #define MTK_MULTI_EN BIT(10)
132 #define MTK_PDMA_SIZE_8DWORDS (1 << 4)
134 /* PDMA Reset Index Register */
135 #define MTK_PDMA_RST_IDX 0xa08
136 #define MTK_PST_DRX_IDX0 BIT(16)
137 #define MTK_PST_DRX_IDX_CFG(x) (MTK_PST_DRX_IDX0 << (x))
139 /* PDMA Delay Interrupt Register */
140 #define MTK_PDMA_DELAY_INT 0xa0c
141 #define MTK_PDMA_DELAY_RX_MASK GENMASK(15, 0)
142 #define MTK_PDMA_DELAY_RX_EN BIT(15)
143 #define MTK_PDMA_DELAY_RX_PINT_SHIFT 8
144 #define MTK_PDMA_DELAY_RX_PTIME_SHIFT 0
146 #define MTK_PDMA_DELAY_TX_MASK GENMASK(31, 16)
147 #define MTK_PDMA_DELAY_TX_EN BIT(31)
148 #define MTK_PDMA_DELAY_TX_PINT_SHIFT 24
149 #define MTK_PDMA_DELAY_TX_PTIME_SHIFT 16
151 #define MTK_PDMA_DELAY_PINT_MASK 0x7f
152 #define MTK_PDMA_DELAY_PTIME_MASK 0xff
154 /* PDMA Interrupt Status Register */
155 #define MTK_PDMA_INT_STATUS 0xa20
157 /* PDMA Interrupt Mask Register */
158 #define MTK_PDMA_INT_MASK 0xa28
160 /* PDMA HW LRO Alter Flow Delta Register */
161 #define MTK_PDMA_LRO_ALT_SCORE_DELTA 0xa4c
163 /* PDMA Interrupt grouping registers */
164 #define MTK_PDMA_INT_GRP1 0xa50
165 #define MTK_PDMA_INT_GRP2 0xa54
167 /* PDMA HW LRO IP Setting Registers */
168 #define MTK_LRO_RX_RING0_DIP_DW0 0xb04
169 #define MTK_LRO_DIP_DW0_CFG(x) (MTK_LRO_RX_RING0_DIP_DW0 + (x * 0x40))
170 #define MTK_RING_MYIP_VLD BIT(9)
172 /* PDMA HW LRO Ring Control Registers */
173 #define MTK_LRO_RX_RING0_CTRL_DW1 0xb28
174 #define MTK_LRO_RX_RING0_CTRL_DW2 0xb2c
175 #define MTK_LRO_RX_RING0_CTRL_DW3 0xb30
176 #define MTK_LRO_CTRL_DW1_CFG(x) (MTK_LRO_RX_RING0_CTRL_DW1 + (x * 0x40))
177 #define MTK_LRO_CTRL_DW2_CFG(x) (MTK_LRO_RX_RING0_CTRL_DW2 + (x * 0x40))
178 #define MTK_LRO_CTRL_DW3_CFG(x) (MTK_LRO_RX_RING0_CTRL_DW3 + (x * 0x40))
179 #define MTK_RING_AGE_TIME_L ((MTK_HW_LRO_AGE_TIME & 0x3ff) << 22)
180 #define MTK_RING_AGE_TIME_H ((MTK_HW_LRO_AGE_TIME >> 10) & 0x3f)
181 #define MTK_RING_AUTO_LERAN_MODE (3 << 6)
182 #define MTK_RING_VLD BIT(8)
183 #define MTK_RING_MAX_AGG_TIME ((MTK_HW_LRO_AGG_TIME & 0xffff) << 10)
184 #define MTK_RING_MAX_AGG_CNT_L ((MTK_HW_LRO_MAX_AGG_CNT & 0x3f) << 26)
185 #define MTK_RING_MAX_AGG_CNT_H ((MTK_HW_LRO_MAX_AGG_CNT >> 6) & 0x3)
187 /* QDMA TX Queue Configuration Registers */
188 #define MTK_QTX_CFG(x) (0x1800 + (x * 0x10))
189 #define QDMA_RES_THRES 4
191 /* QDMA TX Queue Scheduler Registers */
192 #define MTK_QTX_SCH(x) (0x1804 + (x * 0x10))
194 /* QDMA RX Base Pointer Register */
195 #define MTK_QRX_BASE_PTR0 0x1900
197 /* QDMA RX Maximum Count Register */
198 #define MTK_QRX_MAX_CNT0 0x1904
200 /* QDMA RX CPU Pointer Register */
201 #define MTK_QRX_CRX_IDX0 0x1908
203 /* QDMA RX DMA Pointer Register */
204 #define MTK_QRX_DRX_IDX0 0x190C
206 /* QDMA Global Configuration Register */
207 #define MTK_QDMA_GLO_CFG 0x1A04
208 #define MTK_RX_2B_OFFSET BIT(31)
209 #define MTK_RX_BT_32DWORDS (3 << 11)
210 #define MTK_NDP_CO_PRO BIT(10)
211 #define MTK_TX_WB_DDONE BIT(6)
212 #define MTK_TX_BT_32DWORDS (3 << 4)
213 #define MTK_RX_DMA_BUSY BIT(3)
214 #define MTK_TX_DMA_BUSY BIT(1)
215 #define MTK_RX_DMA_EN BIT(2)
216 #define MTK_TX_DMA_EN BIT(0)
217 #define MTK_DMA_BUSY_TIMEOUT_US 1000000
219 /* QDMA Reset Index Register */
220 #define MTK_QDMA_RST_IDX 0x1A08
222 /* QDMA Delay Interrupt Register */
223 #define MTK_QDMA_DELAY_INT 0x1A0C
225 /* QDMA Flow Control Register */
226 #define MTK_QDMA_FC_THRES 0x1A10
227 #define FC_THRES_DROP_MODE BIT(20)
228 #define FC_THRES_DROP_EN (7 << 16)
229 #define FC_THRES_MIN 0x4444
231 /* QDMA Interrupt Status Register */
232 #define MTK_QDMA_INT_STATUS 0x1A18
233 #define MTK_RX_DONE_DLY BIT(30)
234 #define MTK_TX_DONE_DLY BIT(28)
235 #define MTK_RX_DONE_INT3 BIT(19)
236 #define MTK_RX_DONE_INT2 BIT(18)
237 #define MTK_RX_DONE_INT1 BIT(17)
238 #define MTK_RX_DONE_INT0 BIT(16)
239 #define MTK_TX_DONE_INT3 BIT(3)
240 #define MTK_TX_DONE_INT2 BIT(2)
241 #define MTK_TX_DONE_INT1 BIT(1)
242 #define MTK_TX_DONE_INT0 BIT(0)
243 #define MTK_RX_DONE_INT MTK_RX_DONE_DLY
244 #define MTK_TX_DONE_INT MTK_TX_DONE_DLY
246 /* QDMA Interrupt grouping registers */
247 #define MTK_QDMA_INT_GRP1 0x1a20
248 #define MTK_QDMA_INT_GRP2 0x1a24
249 #define MTK_RLS_DONE_INT BIT(0)
251 /* QDMA Interrupt Status Register */
252 #define MTK_QDMA_INT_MASK 0x1A1C
254 /* QDMA Interrupt Mask Register */
255 #define MTK_QDMA_HRED2 0x1A44
257 /* QDMA TX Forward CPU Pointer Register */
258 #define MTK_QTX_CTX_PTR 0x1B00
260 /* QDMA TX Forward DMA Pointer Register */
261 #define MTK_QTX_DTX_PTR 0x1B04
263 /* QDMA TX Release CPU Pointer Register */
264 #define MTK_QTX_CRX_PTR 0x1B10
266 /* QDMA TX Release DMA Pointer Register */
267 #define MTK_QTX_DRX_PTR 0x1B14
269 /* QDMA FQ Head Pointer Register */
270 #define MTK_QDMA_FQ_HEAD 0x1B20
272 /* QDMA FQ Head Pointer Register */
273 #define MTK_QDMA_FQ_TAIL 0x1B24
275 /* QDMA FQ Free Page Counter Register */
276 #define MTK_QDMA_FQ_CNT 0x1B28
278 /* QDMA FQ Free Page Buffer Length Register */
279 #define MTK_QDMA_FQ_BLEN 0x1B2C
281 /* GMA1 counter / statics register */
282 #define MTK_GDM1_RX_GBCNT_L 0x2400
283 #define MTK_GDM1_RX_GBCNT_H 0x2404
284 #define MTK_GDM1_RX_GPCNT 0x2408
285 #define MTK_GDM1_RX_OERCNT 0x2410
286 #define MTK_GDM1_RX_FERCNT 0x2414
287 #define MTK_GDM1_RX_SERCNT 0x2418
288 #define MTK_GDM1_RX_LENCNT 0x241c
289 #define MTK_GDM1_RX_CERCNT 0x2420
290 #define MTK_GDM1_RX_FCCNT 0x2424
291 #define MTK_GDM1_TX_SKIPCNT 0x2428
292 #define MTK_GDM1_TX_COLCNT 0x242c
293 #define MTK_GDM1_TX_GBCNT_L 0x2430
294 #define MTK_GDM1_TX_GBCNT_H 0x2434
295 #define MTK_GDM1_TX_GPCNT 0x2438
296 #define MTK_STAT_OFFSET 0x40
298 /* QDMA descriptor txd4 */
299 #define TX_DMA_CHKSUM (0x7 << 29)
300 #define TX_DMA_TSO BIT(28)
301 #define TX_DMA_FPORT_SHIFT 25
302 #define TX_DMA_FPORT_MASK 0x7
303 #define TX_DMA_INS_VLAN BIT(16)
305 /* QDMA descriptor txd3 */
306 #define TX_DMA_OWNER_CPU BIT(31)
307 #define TX_DMA_LS0 BIT(30)
308 #define TX_DMA_PLEN0(_x) (((_x) & MTK_TX_DMA_BUF_LEN) << 16)
309 #define TX_DMA_PLEN1(_x) ((_x) & MTK_TX_DMA_BUF_LEN)
310 #define TX_DMA_SWC BIT(14)
311 #define TX_DMA_SDL(_x) (((_x) & 0x3fff) << 16)
314 #define TX_DMA_DONE BIT(31)
315 #define TX_DMA_LS1 BIT(14)
316 #define TX_DMA_DESP2_DEF (TX_DMA_LS0 | TX_DMA_DONE)
318 /* QDMA descriptor rxd2 */
319 #define RX_DMA_DONE BIT(31)
320 #define RX_DMA_LSO BIT(30)
321 #define RX_DMA_PLEN0(_x) (((_x) & 0x3fff) << 16)
322 #define RX_DMA_GET_PLEN0(_x) (((_x) >> 16) & 0x3fff)
323 #define RX_DMA_VTAG BIT(15)
325 /* QDMA descriptor rxd3 */
326 #define RX_DMA_VID(_x) ((_x) & 0xfff)
328 /* QDMA descriptor rxd4 */
329 #define MTK_RXD4_FOE_ENTRY GENMASK(13, 0)
330 #define MTK_RXD4_PPE_CPU_REASON GENMASK(18, 14)
331 #define MTK_RXD4_SRC_PORT GENMASK(21, 19)
332 #define MTK_RXD4_ALG GENMASK(31, 22)
334 /* QDMA descriptor rxd4 */
335 #define RX_DMA_L4_VALID BIT(24)
336 #define RX_DMA_L4_VALID_PDMA BIT(30) /* when PDMA is used */
337 #define RX_DMA_FPORT_SHIFT 19
338 #define RX_DMA_FPORT_MASK 0x7
339 #define RX_DMA_SPECIAL_TAG BIT(22)
341 /* PHY Indirect Access Control registers */
342 #define MTK_PHY_IAC 0x10004
343 #define PHY_IAC_ACCESS BIT(31)
344 #define PHY_IAC_REG_MASK GENMASK(29, 25)
345 #define PHY_IAC_REG(x) FIELD_PREP(PHY_IAC_REG_MASK, (x))
346 #define PHY_IAC_ADDR_MASK GENMASK(24, 20)
347 #define PHY_IAC_ADDR(x) FIELD_PREP(PHY_IAC_ADDR_MASK, (x))
348 #define PHY_IAC_CMD_MASK GENMASK(19, 18)
349 #define PHY_IAC_CMD_C45_ADDR FIELD_PREP(PHY_IAC_CMD_MASK, 0)
350 #define PHY_IAC_CMD_WRITE FIELD_PREP(PHY_IAC_CMD_MASK, 1)
351 #define PHY_IAC_CMD_C22_READ FIELD_PREP(PHY_IAC_CMD_MASK, 2)
352 #define PHY_IAC_CMD_C45_READ FIELD_PREP(PHY_IAC_CMD_MASK, 3)
353 #define PHY_IAC_START_MASK GENMASK(17, 16)
354 #define PHY_IAC_START_C45 FIELD_PREP(PHY_IAC_START_MASK, 0)
355 #define PHY_IAC_START_C22 FIELD_PREP(PHY_IAC_START_MASK, 1)
356 #define PHY_IAC_DATA_MASK GENMASK(15, 0)
357 #define PHY_IAC_DATA(x) FIELD_PREP(PHY_IAC_DATA_MASK, (x))
358 #define PHY_IAC_TIMEOUT HZ
360 #define MTK_MAC_MISC 0x1000c
361 #define MTK_MUX_TO_ESW BIT(0)
363 /* Mac control registers */
364 #define MTK_MAC_MCR(x) (0x10100 + (x * 0x100))
365 #define MAC_MCR_MAX_RX_MASK GENMASK(25, 24)
366 #define MAC_MCR_MAX_RX(_x) (MAC_MCR_MAX_RX_MASK & ((_x) << 24))
367 #define MAC_MCR_MAX_RX_1518 0x0
368 #define MAC_MCR_MAX_RX_1536 0x1
369 #define MAC_MCR_MAX_RX_1552 0x2
370 #define MAC_MCR_MAX_RX_2048 0x3
371 #define MAC_MCR_IPG_CFG (BIT(18) | BIT(16))
372 #define MAC_MCR_FORCE_MODE BIT(15)
373 #define MAC_MCR_TX_EN BIT(14)
374 #define MAC_MCR_RX_EN BIT(13)
375 #define MAC_MCR_BACKOFF_EN BIT(9)
376 #define MAC_MCR_BACKPR_EN BIT(8)
377 #define MAC_MCR_FORCE_RX_FC BIT(5)
378 #define MAC_MCR_FORCE_TX_FC BIT(4)
379 #define MAC_MCR_SPEED_1000 BIT(3)
380 #define MAC_MCR_SPEED_100 BIT(2)
381 #define MAC_MCR_FORCE_DPX BIT(1)
382 #define MAC_MCR_FORCE_LINK BIT(0)
383 #define MAC_MCR_FORCE_LINK_DOWN (MAC_MCR_FORCE_MODE)
385 /* Mac status registers */
386 #define MTK_MAC_MSR(x) (0x10108 + (x * 0x100))
387 #define MAC_MSR_EEE1G BIT(7)
388 #define MAC_MSR_EEE100M BIT(6)
389 #define MAC_MSR_RX_FC BIT(5)
390 #define MAC_MSR_TX_FC BIT(4)
391 #define MAC_MSR_SPEED_1000 BIT(3)
392 #define MAC_MSR_SPEED_100 BIT(2)
393 #define MAC_MSR_SPEED_MASK (MAC_MSR_SPEED_1000 | MAC_MSR_SPEED_100)
394 #define MAC_MSR_DPX BIT(1)
395 #define MAC_MSR_LINK BIT(0)
397 /* TRGMII RXC control register */
398 #define TRGMII_RCK_CTRL 0x10300
399 #define DQSI0(x) ((x << 0) & GENMASK(6, 0))
400 #define DQSI1(x) ((x << 8) & GENMASK(14, 8))
401 #define RXCTL_DMWTLAT(x) ((x << 16) & GENMASK(18, 16))
402 #define RXC_RST BIT(31)
403 #define RXC_DQSISEL BIT(30)
404 #define RCK_CTRL_RGMII_1000 (RXC_DQSISEL | RXCTL_DMWTLAT(2) | DQSI1(16))
405 #define RCK_CTRL_RGMII_10_100 RXCTL_DMWTLAT(2)
407 #define NUM_TRGMII_CTRL 5
409 /* TRGMII RXC control register */
410 #define TRGMII_TCK_CTRL 0x10340
411 #define TXCTL_DMWTLAT(x) ((x << 16) & GENMASK(18, 16))
412 #define TXC_INV BIT(30)
413 #define TCK_CTRL_RGMII_1000 TXCTL_DMWTLAT(2)
414 #define TCK_CTRL_RGMII_10_100 (TXC_INV | TXCTL_DMWTLAT(2))
416 /* TRGMII TX Drive Strength */
417 #define TRGMII_TD_ODT(i) (0x10354 + 8 * (i))
418 #define TD_DM_DRVP(x) ((x) & 0xf)
419 #define TD_DM_DRVN(x) (((x) & 0xf) << 4)
421 /* TRGMII Interface mode register */
422 #define INTF_MODE 0x10390
423 #define TRGMII_INTF_DIS BIT(0)
424 #define TRGMII_MODE BIT(1)
425 #define TRGMII_CENTRAL_ALIGNED BIT(2)
426 #define INTF_MODE_RGMII_1000 (TRGMII_MODE | TRGMII_CENTRAL_ALIGNED)
427 #define INTF_MODE_RGMII_10_100 0
429 /* GPIO port control registers for GMAC 2*/
430 #define GPIO_OD33_CTRL8 0x4c0
431 #define GPIO_BIAS_CTRL 0xed0
432 #define GPIO_DRV_SEL10 0xf00
434 /* ethernet subsystem chip id register */
435 #define ETHSYS_CHIPID0_3 0x0
436 #define ETHSYS_CHIPID4_7 0x4
437 #define MT7623_ETH 7623
438 #define MT7622_ETH 7622
439 #define MT7621_ETH 7621
441 /* ethernet system control register */
442 #define ETHSYS_SYSCFG 0x10
443 #define SYSCFG_DRAM_TYPE_DDR2 BIT(4)
445 /* ethernet subsystem config register */
446 #define ETHSYS_SYSCFG0 0x14
447 #define SYSCFG0_GE_MASK 0x3
448 #define SYSCFG0_GE_MODE(x, y) (x << (12 + (y * 2)))
449 #define SYSCFG0_SGMII_MASK GENMASK(9, 8)
450 #define SYSCFG0_SGMII_GMAC1 ((2 << 8) & SYSCFG0_SGMII_MASK)
451 #define SYSCFG0_SGMII_GMAC2 ((3 << 8) & SYSCFG0_SGMII_MASK)
452 #define SYSCFG0_SGMII_GMAC1_V2 BIT(9)
453 #define SYSCFG0_SGMII_GMAC2_V2 BIT(8)
456 /* ethernet subsystem clock register */
457 #define ETHSYS_CLKCFG0 0x2c
458 #define ETHSYS_TRGMII_CLK_SEL362_5 BIT(11)
459 #define ETHSYS_TRGMII_MT7621_MASK (BIT(5) | BIT(6))
460 #define ETHSYS_TRGMII_MT7621_APLL BIT(6)
461 #define ETHSYS_TRGMII_MT7621_DDR_PLL BIT(5)
463 /* ethernet reset control register */
464 #define ETHSYS_RSTCTRL 0x34
465 #define RSTCTRL_FE BIT(6)
466 #define RSTCTRL_PPE BIT(31)
468 /* SGMII subsystem config registers */
469 /* Register to auto-negotiation restart */
470 #define SGMSYS_PCS_CONTROL_1 0x0
471 #define SGMII_AN_RESTART BIT(9)
472 #define SGMII_ISOLATE BIT(10)
473 #define SGMII_AN_ENABLE BIT(12)
474 #define SGMII_LINK_STATYS BIT(18)
475 #define SGMII_AN_ABILITY BIT(19)
476 #define SGMII_AN_COMPLETE BIT(21)
477 #define SGMII_PCS_FAULT BIT(23)
478 #define SGMII_AN_EXPANSION_CLR BIT(30)
480 /* Register to programmable link timer, the unit in 2 * 8ns */
481 #define SGMSYS_PCS_LINK_TIMER 0x18
482 #define SGMII_LINK_TIMER_DEFAULT (0x186a0 & GENMASK(19, 0))
484 /* Register to control remote fault */
485 #define SGMSYS_SGMII_MODE 0x20
486 #define SGMII_IF_MODE_BIT0 BIT(0)
487 #define SGMII_SPEED_DUPLEX_AN BIT(1)
488 #define SGMII_SPEED_10 0x0
489 #define SGMII_SPEED_100 BIT(2)
490 #define SGMII_SPEED_1000 BIT(3)
491 #define SGMII_DUPLEX_FULL BIT(4)
492 #define SGMII_IF_MODE_BIT5 BIT(5)
493 #define SGMII_REMOTE_FAULT_DIS BIT(8)
494 #define SGMII_CODE_SYNC_SET_VAL BIT(9)
495 #define SGMII_CODE_SYNC_SET_EN BIT(10)
496 #define SGMII_SEND_AN_ERROR_EN BIT(11)
497 #define SGMII_IF_MODE_MASK GENMASK(5, 1)
499 /* Register to set SGMII speed, ANA RG_ Control Signals III*/
500 #define SGMSYS_ANA_RG_CS3 0x2028
501 #define RG_PHY_SPEED_MASK (BIT(2) | BIT(3))
502 #define RG_PHY_SPEED_1_25G 0x0
503 #define RG_PHY_SPEED_3_125G BIT(2)
505 /* Register to power up QPHY */
506 #define SGMSYS_QPHY_PWR_STATE_CTRL 0xe8
507 #define SGMII_PHYA_PWD BIT(4)
509 /* Infrasys subsystem config registers */
510 #define INFRA_MISC2 0x70c
511 #define CO_QPHY_SEL BIT(0)
512 #define GEPHY_MAC_SEL BIT(1)
514 /* MT7628/88 specific stuff */
515 #define MT7628_PDMA_OFFSET 0x0800
516 #define MT7628_SDM_OFFSET 0x0c00
518 #define MT7628_TX_BASE_PTR0 (MT7628_PDMA_OFFSET + 0x00)
519 #define MT7628_TX_MAX_CNT0 (MT7628_PDMA_OFFSET + 0x04)
520 #define MT7628_TX_CTX_IDX0 (MT7628_PDMA_OFFSET + 0x08)
521 #define MT7628_TX_DTX_IDX0 (MT7628_PDMA_OFFSET + 0x0c)
522 #define MT7628_PST_DTX_IDX0 BIT(0)
524 #define MT7628_SDM_MAC_ADRL (MT7628_SDM_OFFSET + 0x0c)
525 #define MT7628_SDM_MAC_ADRH (MT7628_SDM_OFFSET + 0x10)
527 /* Counter / stat register */
528 #define MT7628_SDM_TPCNT (MT7628_SDM_OFFSET + 0x100)
529 #define MT7628_SDM_TBCNT (MT7628_SDM_OFFSET + 0x104)
530 #define MT7628_SDM_RPCNT (MT7628_SDM_OFFSET + 0x108)
531 #define MT7628_SDM_RBCNT (MT7628_SDM_OFFSET + 0x10c)
532 #define MT7628_SDM_CS_ERR (MT7628_SDM_OFFSET + 0x110)
539 } __packed __aligned(4);
546 } __packed __aligned(4);
551 /* struct mtk_hw_stats - the structure that holds the traffic statistics.
552 * @stats_lock: make sure that stats operations are atomic
553 * @reg_offset: the status register offset of the SoC
554 * @syncp: the refcount
556 * All of the supported SoCs have hardware counters for traffic statistics.
557 * Whenever the status IRQ triggers we can read the latest stats from these
558 * counters and store them in this struct.
560 struct mtk_hw_stats {
571 u64 rx_checksum_errors;
572 u64 rx_flow_control_packets;
574 spinlock_t stats_lock;
576 struct u64_stats_sync syncp;
580 /* PDMA descriptor can point at 1-2 segments. This enum allows us to
581 * track how memory was allocated so that it can be freed properly.
583 MTK_TX_FLAGS_SINGLE0 = 0x01,
584 MTK_TX_FLAGS_PAGE0 = 0x02,
586 /* MTK_TX_FLAGS_FPORTx allows tracking which port the transmitted
587 * SKB out instead of looking up through hardware TX descriptor.
589 MTK_TX_FLAGS_FPORT0 = 0x04,
590 MTK_TX_FLAGS_FPORT1 = 0x08,
593 /* This enum allows us to identify how the clock is defined on the array of the
605 MTK_CLK_SGMII_TX_250M,
606 MTK_CLK_SGMII_RX_250M,
607 MTK_CLK_SGMII_CDR_REF,
608 MTK_CLK_SGMII_CDR_FB,
609 MTK_CLK_SGMII2_TX_250M,
610 MTK_CLK_SGMII2_RX_250M,
611 MTK_CLK_SGMII2_CDR_REF,
612 MTK_CLK_SGMII2_CDR_FB,
618 #define MT7623_CLKS_BITMAP (BIT(MTK_CLK_ETHIF) | BIT(MTK_CLK_ESW) | \
619 BIT(MTK_CLK_GP1) | BIT(MTK_CLK_GP2) | \
621 #define MT7622_CLKS_BITMAP (BIT(MTK_CLK_ETHIF) | BIT(MTK_CLK_ESW) | \
622 BIT(MTK_CLK_GP0) | BIT(MTK_CLK_GP1) | \
624 BIT(MTK_CLK_SGMII_TX_250M) | \
625 BIT(MTK_CLK_SGMII_RX_250M) | \
626 BIT(MTK_CLK_SGMII_CDR_REF) | \
627 BIT(MTK_CLK_SGMII_CDR_FB) | \
628 BIT(MTK_CLK_SGMII_CK) | \
629 BIT(MTK_CLK_ETH2PLL))
630 #define MT7621_CLKS_BITMAP (0)
631 #define MT7628_CLKS_BITMAP (0)
632 #define MT7629_CLKS_BITMAP (BIT(MTK_CLK_ETHIF) | BIT(MTK_CLK_ESW) | \
633 BIT(MTK_CLK_GP0) | BIT(MTK_CLK_GP1) | \
634 BIT(MTK_CLK_GP2) | BIT(MTK_CLK_FE) | \
635 BIT(MTK_CLK_SGMII_TX_250M) | \
636 BIT(MTK_CLK_SGMII_RX_250M) | \
637 BIT(MTK_CLK_SGMII_CDR_REF) | \
638 BIT(MTK_CLK_SGMII_CDR_FB) | \
639 BIT(MTK_CLK_SGMII2_TX_250M) | \
640 BIT(MTK_CLK_SGMII2_RX_250M) | \
641 BIT(MTK_CLK_SGMII2_CDR_REF) | \
642 BIT(MTK_CLK_SGMII2_CDR_FB) | \
643 BIT(MTK_CLK_SGMII_CK) | \
644 BIT(MTK_CLK_ETH2PLL) | BIT(MTK_CLK_SGMIITOP))
651 /* struct mtk_tx_buf - This struct holds the pointers to the memory pointed at
652 * by the TX descriptor s
653 * @skb: The SKB pointer of the packet being sent
654 * @dma_addr0: The base addr of the first segment
655 * @dma_len0: The length of the first segment
656 * @dma_addr1: The base addr of the second segment
657 * @dma_len1: The length of the second segment
662 DEFINE_DMA_UNMAP_ADDR(dma_addr0);
663 DEFINE_DMA_UNMAP_LEN(dma_len0);
664 DEFINE_DMA_UNMAP_ADDR(dma_addr1);
665 DEFINE_DMA_UNMAP_LEN(dma_len1);
668 /* struct mtk_tx_ring - This struct holds info describing a TX ring
669 * @dma: The descriptor ring
670 * @buf: The memory pointed at by the ring
671 * @phys: The physical addr of tx_buf
672 * @next_free: Pointer to the next free descriptor
673 * @last_free: Pointer to the last free descriptor
674 * @last_free_ptr: Hardware pointer value of the last free descriptor
675 * @thresh: The threshold of minimum amount of free descriptors
676 * @free_count: QDMA uses a linked list. Track how many free descriptors
680 struct mtk_tx_dma *dma;
681 struct mtk_tx_buf *buf;
683 struct mtk_tx_dma *next_free;
684 struct mtk_tx_dma *last_free;
689 struct mtk_tx_dma *dma_pdma; /* For MT7628/88 PDMA handling */
690 dma_addr_t phys_pdma;
694 /* PDMA rx ring mode */
696 MTK_RX_FLAGS_NORMAL = 0,
701 /* struct mtk_rx_ring - This struct holds info describing a RX ring
702 * @dma: The descriptor ring
703 * @data: The memory pointed at by the ring
704 * @phys: The physical addr of rx_buf
705 * @frag_size: How big can each fragment be
706 * @buf_size: The size of each packet buffer
707 * @calc_idx: The current head of ring
710 struct mtk_rx_dma *dma;
716 bool calc_idx_update;
721 enum mkt_eth_capabilities {
729 MTK_SHARED_SGMII_BIT,
732 MTK_TRGMII_MT7621_CLK_BIT,
737 MTK_ETH_MUX_GDM1_TO_GMAC1_ESW_BIT,
738 MTK_ETH_MUX_GMAC2_GMAC0_TO_GEPHY_BIT,
739 MTK_ETH_MUX_U3_GMAC2_TO_QPHY_BIT,
740 MTK_ETH_MUX_GMAC1_GMAC2_TO_SGMII_RGMII_BIT,
741 MTK_ETH_MUX_GMAC12_TO_GEPHY_SGMII_BIT,
744 MTK_ETH_PATH_GMAC1_RGMII_BIT,
745 MTK_ETH_PATH_GMAC1_TRGMII_BIT,
746 MTK_ETH_PATH_GMAC1_SGMII_BIT,
747 MTK_ETH_PATH_GMAC2_RGMII_BIT,
748 MTK_ETH_PATH_GMAC2_SGMII_BIT,
749 MTK_ETH_PATH_GMAC2_GEPHY_BIT,
750 MTK_ETH_PATH_GDM1_ESW_BIT,
753 /* Supported hardware group on SoCs */
754 #define MTK_RGMII BIT(MTK_RGMII_BIT)
755 #define MTK_TRGMII BIT(MTK_TRGMII_BIT)
756 #define MTK_SGMII BIT(MTK_SGMII_BIT)
757 #define MTK_ESW BIT(MTK_ESW_BIT)
758 #define MTK_GEPHY BIT(MTK_GEPHY_BIT)
759 #define MTK_MUX BIT(MTK_MUX_BIT)
760 #define MTK_INFRA BIT(MTK_INFRA_BIT)
761 #define MTK_SHARED_SGMII BIT(MTK_SHARED_SGMII_BIT)
762 #define MTK_HWLRO BIT(MTK_HWLRO_BIT)
763 #define MTK_SHARED_INT BIT(MTK_SHARED_INT_BIT)
764 #define MTK_TRGMII_MT7621_CLK BIT(MTK_TRGMII_MT7621_CLK_BIT)
765 #define MTK_QDMA BIT(MTK_QDMA_BIT)
766 #define MTK_SOC_MT7628 BIT(MTK_SOC_MT7628_BIT)
768 #define MTK_ETH_MUX_GDM1_TO_GMAC1_ESW \
769 BIT(MTK_ETH_MUX_GDM1_TO_GMAC1_ESW_BIT)
770 #define MTK_ETH_MUX_GMAC2_GMAC0_TO_GEPHY \
771 BIT(MTK_ETH_MUX_GMAC2_GMAC0_TO_GEPHY_BIT)
772 #define MTK_ETH_MUX_U3_GMAC2_TO_QPHY \
773 BIT(MTK_ETH_MUX_U3_GMAC2_TO_QPHY_BIT)
774 #define MTK_ETH_MUX_GMAC1_GMAC2_TO_SGMII_RGMII \
775 BIT(MTK_ETH_MUX_GMAC1_GMAC2_TO_SGMII_RGMII_BIT)
776 #define MTK_ETH_MUX_GMAC12_TO_GEPHY_SGMII \
777 BIT(MTK_ETH_MUX_GMAC12_TO_GEPHY_SGMII_BIT)
779 /* Supported path present on SoCs */
780 #define MTK_ETH_PATH_GMAC1_RGMII BIT(MTK_ETH_PATH_GMAC1_RGMII_BIT)
781 #define MTK_ETH_PATH_GMAC1_TRGMII BIT(MTK_ETH_PATH_GMAC1_TRGMII_BIT)
782 #define MTK_ETH_PATH_GMAC1_SGMII BIT(MTK_ETH_PATH_GMAC1_SGMII_BIT)
783 #define MTK_ETH_PATH_GMAC2_RGMII BIT(MTK_ETH_PATH_GMAC2_RGMII_BIT)
784 #define MTK_ETH_PATH_GMAC2_SGMII BIT(MTK_ETH_PATH_GMAC2_SGMII_BIT)
785 #define MTK_ETH_PATH_GMAC2_GEPHY BIT(MTK_ETH_PATH_GMAC2_GEPHY_BIT)
786 #define MTK_ETH_PATH_GDM1_ESW BIT(MTK_ETH_PATH_GDM1_ESW_BIT)
788 #define MTK_GMAC1_RGMII (MTK_ETH_PATH_GMAC1_RGMII | MTK_RGMII)
789 #define MTK_GMAC1_TRGMII (MTK_ETH_PATH_GMAC1_TRGMII | MTK_TRGMII)
790 #define MTK_GMAC1_SGMII (MTK_ETH_PATH_GMAC1_SGMII | MTK_SGMII)
791 #define MTK_GMAC2_RGMII (MTK_ETH_PATH_GMAC2_RGMII | MTK_RGMII)
792 #define MTK_GMAC2_SGMII (MTK_ETH_PATH_GMAC2_SGMII | MTK_SGMII)
793 #define MTK_GMAC2_GEPHY (MTK_ETH_PATH_GMAC2_GEPHY | MTK_GEPHY)
794 #define MTK_GDM1_ESW (MTK_ETH_PATH_GDM1_ESW | MTK_ESW)
796 /* MUXes present on SoCs */
797 /* 0: GDM1 -> GMAC1, 1: GDM1 -> ESW */
798 #define MTK_MUX_GDM1_TO_GMAC1_ESW (MTK_ETH_MUX_GDM1_TO_GMAC1_ESW | MTK_MUX)
800 /* 0: GMAC2 -> GEPHY, 1: GMAC0 -> GePHY */
801 #define MTK_MUX_GMAC2_GMAC0_TO_GEPHY \
802 (MTK_ETH_MUX_GMAC2_GMAC0_TO_GEPHY | MTK_MUX | MTK_INFRA)
804 /* 0: U3 -> QPHY, 1: GMAC2 -> QPHY */
805 #define MTK_MUX_U3_GMAC2_TO_QPHY \
806 (MTK_ETH_MUX_U3_GMAC2_TO_QPHY | MTK_MUX | MTK_INFRA)
808 /* 2: GMAC1 -> SGMII, 3: GMAC2 -> SGMII */
809 #define MTK_MUX_GMAC1_GMAC2_TO_SGMII_RGMII \
810 (MTK_ETH_MUX_GMAC1_GMAC2_TO_SGMII_RGMII | MTK_MUX | \
813 /* 0: GMACx -> GEPHY, 1: GMACx -> SGMII where x is 1 or 2 */
814 #define MTK_MUX_GMAC12_TO_GEPHY_SGMII \
815 (MTK_ETH_MUX_GMAC12_TO_GEPHY_SGMII | MTK_MUX)
817 #define MTK_HAS_CAPS(caps, _x) (((caps) & (_x)) == (_x))
819 #define MT7621_CAPS (MTK_GMAC1_RGMII | MTK_GMAC1_TRGMII | \
820 MTK_GMAC2_RGMII | MTK_SHARED_INT | \
821 MTK_TRGMII_MT7621_CLK | MTK_QDMA)
823 #define MT7622_CAPS (MTK_GMAC1_RGMII | MTK_GMAC1_SGMII | MTK_GMAC2_RGMII | \
824 MTK_GMAC2_SGMII | MTK_GDM1_ESW | \
825 MTK_MUX_GDM1_TO_GMAC1_ESW | \
826 MTK_MUX_GMAC1_GMAC2_TO_SGMII_RGMII | MTK_QDMA)
828 #define MT7623_CAPS (MTK_GMAC1_RGMII | MTK_GMAC1_TRGMII | MTK_GMAC2_RGMII | \
831 #define MT7628_CAPS (MTK_SHARED_INT | MTK_SOC_MT7628)
833 #define MT7629_CAPS (MTK_GMAC1_SGMII | MTK_GMAC2_SGMII | MTK_GMAC2_GEPHY | \
834 MTK_GDM1_ESW | MTK_MUX_GDM1_TO_GMAC1_ESW | \
835 MTK_MUX_GMAC2_GMAC0_TO_GEPHY | \
836 MTK_MUX_U3_GMAC2_TO_QPHY | \
837 MTK_MUX_GMAC12_TO_GEPHY_SGMII | MTK_QDMA)
839 /* struct mtk_eth_data - This is the structure holding all differences
840 * among various plaforms
841 * @ana_rgc3: The offset for register ANA_RGC3 related to
843 * @caps Flags shown the extra capability for the SoC
844 * @hw_features Flags shown HW features
845 * @required_clks Flags shown the bitmap for required clocks on
847 * @required_pctl A bool value to show whether the SoC requires
848 * the extra setup for those pins used by GMAC.
850 struct mtk_soc_data {
856 netdev_features_t hw_features;
859 /* currently no SoC has more than 2 macs */
860 #define MTK_MAX_DEVS 2
862 #define MTK_SGMII_PHYSPEED_AN BIT(31)
863 #define MTK_SGMII_PHYSPEED_MASK GENMASK(2, 0)
864 #define MTK_SGMII_PHYSPEED_1000 BIT(0)
865 #define MTK_SGMII_PHYSPEED_2500 BIT(1)
866 #define MTK_HAS_FLAGS(flags, _x) (((flags) & (_x)) == (_x))
868 /* struct mtk_sgmii - This is the structure holding sgmii regmap and its
870 * @regmap: The register map pointing at the range used to setup
872 * @flags: The enum refers to which mode the sgmii wants to run on
873 * @ana_rgc3: The offset refers to register ANA_RGC3 related to regmap
877 struct regmap *regmap[MTK_MAX_DEVS];
878 u32 flags[MTK_MAX_DEVS];
882 /* struct mtk_eth - This is the main datasructure for holding the state
884 * @dev: The device pointer
885 * @base: The mapped register i/o base
886 * @page_lock: Make sure that register operations are atomic
887 * @tx_irq__lock: Make sure that IRQ register operations are atomic
888 * @rx_irq__lock: Make sure that IRQ register operations are atomic
889 * @dim_lock: Make sure that Net DIM operations are atomic
890 * @dummy_dev: we run 2 netdevs on 1 physical DMA ring and need a
891 * dummy for NAPI to work
892 * @netdev: The netdev instances
893 * @mac: Each netdev is linked to a physical MAC
894 * @irq: The IRQ that we are using
895 * @msg_enable: Ethtool msg level
896 * @ethsys: The register map pointing at the range used to setup
898 * @infra: The register map pointing at the range used to setup
899 * SGMII and GePHY path
900 * @pctl: The register map pointing at the range used to setup
901 * GMAC port drive/slew values
902 * @dma_refcnt: track how many netdevs are using the DMA engine
903 * @tx_ring: Pointer to the memory holding info about the TX ring
904 * @rx_ring: Pointer to the memory holding info about the RX ring
905 * @rx_ring_qdma: Pointer to the memory holding info about the QDMA RX ring
906 * @tx_napi: The TX NAPI struct
907 * @rx_napi: The RX NAPI struct
908 * @rx_events: Net DIM RX event counter
909 * @rx_packets: Net DIM RX packet counter
910 * @rx_bytes: Net DIM RX byte counter
911 * @rx_dim: Net DIM RX context
912 * @tx_events: Net DIM TX event counter
913 * @tx_packets: Net DIM TX packet counter
914 * @tx_bytes: Net DIM TX byte counter
915 * @tx_dim: Net DIM TX context
916 * @scratch_ring: Newer SoCs need memory for a second HW managed TX ring
917 * @phy_scratch_ring: physical address of scratch_ring
918 * @scratch_head: The scratch memory that scratch_ring points to.
919 * @clks: clock array for all clocks required
920 * @mii_bus: If there is a bus we need to create an instance for it
921 * @pending_work: The workqueue used to reset the dma ring
922 * @state: Initialization and runtime state of the device
923 * @soc: Holding specific data among vaious SoCs
929 spinlock_t page_lock;
930 spinlock_t tx_irq_lock;
931 spinlock_t rx_irq_lock;
932 struct net_device dummy_dev;
933 struct net_device *netdev[MTK_MAX_DEVS];
934 struct mtk_mac *mac[MTK_MAX_DEVS];
937 unsigned long sysclk;
938 struct regmap *ethsys;
939 struct regmap *infra;
940 struct mtk_sgmii *sgmii;
943 refcount_t dma_refcnt;
944 struct mtk_tx_ring tx_ring;
945 struct mtk_rx_ring rx_ring[MTK_MAX_RX_RING_NUM];
946 struct mtk_rx_ring rx_ring_qdma;
947 struct napi_struct tx_napi;
948 struct napi_struct rx_napi;
949 struct mtk_tx_dma *scratch_ring;
950 dma_addr_t phy_scratch_ring;
952 struct clk *clks[MTK_CLK_MAX];
954 struct mii_bus *mii_bus;
955 struct work_struct pending_work;
958 const struct mtk_soc_data *soc;
973 u32 tx_int_status_reg;
978 struct rhashtable flow_table;
981 /* struct mtk_mac - the structure that holds the info about the MACs of the
983 * @id: The number of the MAC
984 * @interface: Interface mode kept for detecting change in hw settings
985 * @of_node: Our devicetree node
986 * @hw: Backpointer to our main datastruture
987 * @hw_stats: Packet statistics counter
991 phy_interface_t interface;
994 struct device_node *of_node;
995 struct phylink *phylink;
996 struct phylink_config phylink_config;
998 struct mtk_hw_stats *hw_stats;
999 __be32 hwlro_ip[MTK_MAX_LRO_IP_CNT];
1003 /* the struct describing the SoC. these are declared in the soc_xyz.c files */
1004 extern const struct of_device_id of_mtk_match[];
1006 /* read the hardware status register */
1007 void mtk_stats_update_mac(struct mtk_mac *mac);
1009 void mtk_w32(struct mtk_eth *eth, u32 val, unsigned reg);
1010 u32 mtk_r32(struct mtk_eth *eth, unsigned reg);
1012 int mtk_sgmii_init(struct mtk_sgmii *ss, struct device_node *np,
1014 int mtk_sgmii_setup_mode_an(struct mtk_sgmii *ss, int id);
1015 int mtk_sgmii_setup_mode_force(struct mtk_sgmii *ss, int id,
1016 const struct phylink_link_state *state);
1017 void mtk_sgmii_restart_an(struct mtk_eth *eth, int mac_id);
1019 int mtk_gmac_sgmii_path_setup(struct mtk_eth *eth, int mac_id);
1020 int mtk_gmac_gephy_path_setup(struct mtk_eth *eth, int mac_id);
1021 int mtk_gmac_rgmii_path_setup(struct mtk_eth *eth, int mac_id);
1023 int mtk_eth_offload_init(struct mtk_eth *eth);
1024 int mtk_eth_setup_tc(struct net_device *dev, enum tc_setup_type type,
1028 #endif /* MTK_ETH_H */