1 // SPDX-License-Identifier: GPL-2.0-only
3 * New driver for Marvell Yukon chipset and SysKonnect Gigabit
4 * Ethernet adapters. Based on earlier sk98lin, e100 and
5 * FreeBSD if_sk drivers.
7 * This driver intentionally does not support all the features
8 * of the original driver such as link fail-over and link management because
9 * those should be done at higher levels.
11 * Copyright (C) 2004, 2005 Stephen Hemminger <shemminger@osdl.org>
14 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
17 #include <linux/kernel.h>
18 #include <linux/module.h>
19 #include <linux/moduleparam.h>
20 #include <linux/netdevice.h>
21 #include <linux/etherdevice.h>
22 #include <linux/ethtool.h>
23 #include <linux/pci.h>
24 #include <linux/if_vlan.h>
26 #include <linux/delay.h>
27 #include <linux/crc32.h>
28 #include <linux/dma-mapping.h>
29 #include <linux/debugfs.h>
30 #include <linux/sched.h>
31 #include <linux/seq_file.h>
32 #include <linux/mii.h>
33 #include <linux/slab.h>
34 #include <linux/dmi.h>
35 #include <linux/prefetch.h>
40 #define DRV_NAME "skge"
41 #define DRV_VERSION "1.14"
43 #define DEFAULT_TX_RING_SIZE 128
44 #define DEFAULT_RX_RING_SIZE 512
45 #define MAX_TX_RING_SIZE 1024
46 #define TX_LOW_WATER (MAX_SKB_FRAGS + 1)
47 #define MAX_RX_RING_SIZE 4096
48 #define RX_COPY_THRESHOLD 128
49 #define RX_BUF_SIZE 1536
50 #define PHY_RETRIES 1000
51 #define ETH_JUMBO_MTU 9000
52 #define TX_WATCHDOG (5 * HZ)
53 #define NAPI_WEIGHT 64
57 #define SKGE_EEPROM_MAGIC 0x9933aabb
60 MODULE_DESCRIPTION("SysKonnect Gigabit Ethernet driver");
61 MODULE_AUTHOR("Stephen Hemminger <shemminger@linux-foundation.org>");
62 MODULE_LICENSE("GPL");
63 MODULE_VERSION(DRV_VERSION);
65 static const u32 default_msg = (NETIF_MSG_DRV | NETIF_MSG_PROBE |
66 NETIF_MSG_LINK | NETIF_MSG_IFUP |
69 static int debug = -1; /* defaults above */
70 module_param(debug, int, 0);
71 MODULE_PARM_DESC(debug, "Debug level (0=none,...,16=all)");
73 static const struct pci_device_id skge_id_table[] = {
74 { PCI_DEVICE(PCI_VENDOR_ID_3COM, 0x1700) }, /* 3Com 3C940 */
75 { PCI_DEVICE(PCI_VENDOR_ID_3COM, 0x80EB) }, /* 3Com 3C940B */
76 #ifdef CONFIG_SKGE_GENESIS
77 { PCI_DEVICE(PCI_VENDOR_ID_SYSKONNECT, 0x4300) }, /* SK-9xx */
79 { PCI_DEVICE(PCI_VENDOR_ID_SYSKONNECT, 0x4320) }, /* SK-98xx V2.0 */
80 { PCI_DEVICE(PCI_VENDOR_ID_DLINK, 0x4b01) }, /* D-Link DGE-530T (rev.B) */
81 { PCI_DEVICE(PCI_VENDOR_ID_DLINK, 0x4c00) }, /* D-Link DGE-530T */
82 { PCI_DEVICE(PCI_VENDOR_ID_DLINK, 0x4302) }, /* D-Link DGE-530T Rev C1 */
83 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4320) }, /* Marvell Yukon 88E8001/8003/8010 */
84 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x5005) }, /* Belkin */
85 { PCI_DEVICE(PCI_VENDOR_ID_CNET, 0x434E) }, /* CNet PowerG-2000 */
86 { PCI_DEVICE(PCI_VENDOR_ID_LINKSYS, 0x1064) }, /* Linksys EG1064 v2 */
87 { PCI_VENDOR_ID_LINKSYS, 0x1032, PCI_ANY_ID, 0x0015 }, /* Linksys EG1032 v2 */
90 MODULE_DEVICE_TABLE(pci, skge_id_table);
92 static int skge_up(struct net_device *dev);
93 static int skge_down(struct net_device *dev);
94 static void skge_phy_reset(struct skge_port *skge);
95 static void skge_tx_clean(struct net_device *dev);
96 static int xm_phy_write(struct skge_hw *hw, int port, u16 reg, u16 val);
97 static int gm_phy_write(struct skge_hw *hw, int port, u16 reg, u16 val);
98 static void genesis_get_stats(struct skge_port *skge, u64 *data);
99 static void yukon_get_stats(struct skge_port *skge, u64 *data);
100 static void yukon_init(struct skge_hw *hw, int port);
101 static void genesis_mac_init(struct skge_hw *hw, int port);
102 static void genesis_link_up(struct skge_port *skge);
103 static void skge_set_multicast(struct net_device *dev);
104 static irqreturn_t skge_intr(int irq, void *dev_id);
106 /* Avoid conditionals by using array */
107 static const int txqaddr[] = { Q_XA1, Q_XA2 };
108 static const int rxqaddr[] = { Q_R1, Q_R2 };
109 static const u32 rxirqmask[] = { IS_R1_F, IS_R2_F };
110 static const u32 txirqmask[] = { IS_XA1_F, IS_XA2_F };
111 static const u32 napimask[] = { IS_R1_F|IS_XA1_F, IS_R2_F|IS_XA2_F };
112 static const u32 portmask[] = { IS_PORT_1, IS_PORT_2 };
114 static inline bool is_genesis(const struct skge_hw *hw)
116 #ifdef CONFIG_SKGE_GENESIS
117 return hw->chip_id == CHIP_ID_GENESIS;
123 static int skge_get_regs_len(struct net_device *dev)
129 * Returns copy of whole control register region
130 * Note: skip RAM address register because accessing it will
133 static void skge_get_regs(struct net_device *dev, struct ethtool_regs *regs,
136 const struct skge_port *skge = netdev_priv(dev);
137 const void __iomem *io = skge->hw->regs;
140 memset(p, 0, regs->len);
141 memcpy_fromio(p, io, B3_RAM_ADDR);
143 if (regs->len > B3_RI_WTO_R1) {
144 memcpy_fromio(p + B3_RI_WTO_R1, io + B3_RI_WTO_R1,
145 regs->len - B3_RI_WTO_R1);
149 /* Wake on Lan only supported on Yukon chips with rev 1 or above */
150 static u32 wol_supported(const struct skge_hw *hw)
155 if (hw->chip_id == CHIP_ID_YUKON && hw->chip_rev == 0)
158 return WAKE_MAGIC | WAKE_PHY;
161 static void skge_wol_init(struct skge_port *skge)
163 struct skge_hw *hw = skge->hw;
164 int port = skge->port;
167 skge_write16(hw, B0_CTST, CS_RST_CLR);
168 skge_write16(hw, SK_REG(port, GMAC_LINK_CTRL), GMLC_RST_CLR);
171 skge_write8(hw, B0_POWER_CTRL,
172 PC_VAUX_ENA | PC_VCC_ENA | PC_VAUX_ON | PC_VCC_OFF);
174 /* WA code for COMA mode -- clear PHY reset */
175 if (hw->chip_id == CHIP_ID_YUKON_LITE &&
176 hw->chip_rev >= CHIP_REV_YU_LITE_A3) {
177 u32 reg = skge_read32(hw, B2_GP_IO);
180 skge_write32(hw, B2_GP_IO, reg);
183 skge_write32(hw, SK_REG(port, GPHY_CTRL),
185 GPC_HWCFG_M_3 | GPC_HWCFG_M_2 | GPC_HWCFG_M_1 | GPC_HWCFG_M_0 |
186 GPC_ANEG_1 | GPC_RST_SET);
188 skge_write32(hw, SK_REG(port, GPHY_CTRL),
190 GPC_HWCFG_M_3 | GPC_HWCFG_M_2 | GPC_HWCFG_M_1 | GPC_HWCFG_M_0 |
191 GPC_ANEG_1 | GPC_RST_CLR);
193 skge_write32(hw, SK_REG(port, GMAC_CTRL), GMC_RST_CLR);
195 /* Force to 10/100 skge_reset will re-enable on resume */
196 gm_phy_write(hw, port, PHY_MARV_AUNE_ADV,
197 (PHY_AN_100FULL | PHY_AN_100HALF |
198 PHY_AN_10FULL | PHY_AN_10HALF | PHY_AN_CSMA));
200 gm_phy_write(hw, port, PHY_MARV_1000T_CTRL, 0);
201 gm_phy_write(hw, port, PHY_MARV_CTRL,
202 PHY_CT_RESET | PHY_CT_SPS_LSB | PHY_CT_ANE |
203 PHY_CT_RE_CFG | PHY_CT_DUP_MD);
206 /* Set GMAC to no flow control and auto update for speed/duplex */
207 gma_write16(hw, port, GM_GP_CTRL,
208 GM_GPCR_FC_TX_DIS|GM_GPCR_TX_ENA|GM_GPCR_RX_ENA|
209 GM_GPCR_DUP_FULL|GM_GPCR_FC_RX_DIS|GM_GPCR_AU_FCT_DIS);
211 /* Set WOL address */
212 memcpy_toio(hw->regs + WOL_REGS(port, WOL_MAC_ADDR),
213 skge->netdev->dev_addr, ETH_ALEN);
215 /* Turn on appropriate WOL control bits */
216 skge_write16(hw, WOL_REGS(port, WOL_CTRL_STAT), WOL_CTL_CLEAR_RESULT);
218 if (skge->wol & WAKE_PHY)
219 ctrl |= WOL_CTL_ENA_PME_ON_LINK_CHG|WOL_CTL_ENA_LINK_CHG_UNIT;
221 ctrl |= WOL_CTL_DIS_PME_ON_LINK_CHG|WOL_CTL_DIS_LINK_CHG_UNIT;
223 if (skge->wol & WAKE_MAGIC)
224 ctrl |= WOL_CTL_ENA_PME_ON_MAGIC_PKT|WOL_CTL_ENA_MAGIC_PKT_UNIT;
226 ctrl |= WOL_CTL_DIS_PME_ON_MAGIC_PKT|WOL_CTL_DIS_MAGIC_PKT_UNIT;
228 ctrl |= WOL_CTL_DIS_PME_ON_PATTERN|WOL_CTL_DIS_PATTERN_UNIT;
229 skge_write16(hw, WOL_REGS(port, WOL_CTRL_STAT), ctrl);
232 skge_write8(hw, SK_REG(port, RX_GMF_CTRL_T), GMF_RST_SET);
235 static void skge_get_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
237 struct skge_port *skge = netdev_priv(dev);
239 wol->supported = wol_supported(skge->hw);
240 wol->wolopts = skge->wol;
243 static int skge_set_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
245 struct skge_port *skge = netdev_priv(dev);
246 struct skge_hw *hw = skge->hw;
248 if ((wol->wolopts & ~wol_supported(hw)) ||
249 !device_can_wakeup(&hw->pdev->dev))
252 skge->wol = wol->wolopts;
254 device_set_wakeup_enable(&hw->pdev->dev, skge->wol);
259 /* Determine supported/advertised modes based on hardware.
260 * Note: ethtool ADVERTISED_xxx == SUPPORTED_xxx
262 static u32 skge_supported_modes(const struct skge_hw *hw)
267 supported = (SUPPORTED_10baseT_Half |
268 SUPPORTED_10baseT_Full |
269 SUPPORTED_100baseT_Half |
270 SUPPORTED_100baseT_Full |
271 SUPPORTED_1000baseT_Half |
272 SUPPORTED_1000baseT_Full |
277 supported &= ~(SUPPORTED_10baseT_Half |
278 SUPPORTED_10baseT_Full |
279 SUPPORTED_100baseT_Half |
280 SUPPORTED_100baseT_Full);
282 else if (hw->chip_id == CHIP_ID_YUKON)
283 supported &= ~SUPPORTED_1000baseT_Half;
285 supported = (SUPPORTED_1000baseT_Full |
286 SUPPORTED_1000baseT_Half |
293 static int skge_get_link_ksettings(struct net_device *dev,
294 struct ethtool_link_ksettings *cmd)
296 struct skge_port *skge = netdev_priv(dev);
297 struct skge_hw *hw = skge->hw;
298 u32 supported, advertising;
300 supported = skge_supported_modes(hw);
303 cmd->base.port = PORT_TP;
304 cmd->base.phy_address = hw->phy_addr;
306 cmd->base.port = PORT_FIBRE;
308 advertising = skge->advertising;
309 cmd->base.autoneg = skge->autoneg;
310 cmd->base.speed = skge->speed;
311 cmd->base.duplex = skge->duplex;
313 ethtool_convert_legacy_u32_to_link_mode(cmd->link_modes.supported,
315 ethtool_convert_legacy_u32_to_link_mode(cmd->link_modes.advertising,
321 static int skge_set_link_ksettings(struct net_device *dev,
322 const struct ethtool_link_ksettings *cmd)
324 struct skge_port *skge = netdev_priv(dev);
325 const struct skge_hw *hw = skge->hw;
326 u32 supported = skge_supported_modes(hw);
330 ethtool_convert_link_mode_to_legacy_u32(&advertising,
331 cmd->link_modes.advertising);
333 if (cmd->base.autoneg == AUTONEG_ENABLE) {
334 advertising = supported;
339 u32 speed = cmd->base.speed;
343 if (cmd->base.duplex == DUPLEX_FULL)
344 setting = SUPPORTED_1000baseT_Full;
345 else if (cmd->base.duplex == DUPLEX_HALF)
346 setting = SUPPORTED_1000baseT_Half;
351 if (cmd->base.duplex == DUPLEX_FULL)
352 setting = SUPPORTED_100baseT_Full;
353 else if (cmd->base.duplex == DUPLEX_HALF)
354 setting = SUPPORTED_100baseT_Half;
360 if (cmd->base.duplex == DUPLEX_FULL)
361 setting = SUPPORTED_10baseT_Full;
362 else if (cmd->base.duplex == DUPLEX_HALF)
363 setting = SUPPORTED_10baseT_Half;
371 if ((setting & supported) == 0)
375 skge->duplex = cmd->base.duplex;
378 skge->autoneg = cmd->base.autoneg;
379 skge->advertising = advertising;
381 if (netif_running(dev)) {
393 static void skge_get_drvinfo(struct net_device *dev,
394 struct ethtool_drvinfo *info)
396 struct skge_port *skge = netdev_priv(dev);
398 strlcpy(info->driver, DRV_NAME, sizeof(info->driver));
399 strlcpy(info->version, DRV_VERSION, sizeof(info->version));
400 strlcpy(info->bus_info, pci_name(skge->hw->pdev),
401 sizeof(info->bus_info));
404 static const struct skge_stat {
405 char name[ETH_GSTRING_LEN];
409 { "tx_bytes", XM_TXO_OK_HI, GM_TXO_OK_HI },
410 { "rx_bytes", XM_RXO_OK_HI, GM_RXO_OK_HI },
412 { "tx_broadcast", XM_TXF_BC_OK, GM_TXF_BC_OK },
413 { "rx_broadcast", XM_RXF_BC_OK, GM_RXF_BC_OK },
414 { "tx_multicast", XM_TXF_MC_OK, GM_TXF_MC_OK },
415 { "rx_multicast", XM_RXF_MC_OK, GM_RXF_MC_OK },
416 { "tx_unicast", XM_TXF_UC_OK, GM_TXF_UC_OK },
417 { "rx_unicast", XM_RXF_UC_OK, GM_RXF_UC_OK },
418 { "tx_mac_pause", XM_TXF_MPAUSE, GM_TXF_MPAUSE },
419 { "rx_mac_pause", XM_RXF_MPAUSE, GM_RXF_MPAUSE },
421 { "collisions", XM_TXF_SNG_COL, GM_TXF_SNG_COL },
422 { "multi_collisions", XM_TXF_MUL_COL, GM_TXF_MUL_COL },
423 { "aborted", XM_TXF_ABO_COL, GM_TXF_ABO_COL },
424 { "late_collision", XM_TXF_LAT_COL, GM_TXF_LAT_COL },
425 { "fifo_underrun", XM_TXE_FIFO_UR, GM_TXE_FIFO_UR },
426 { "fifo_overflow", XM_RXE_FIFO_OV, GM_RXE_FIFO_OV },
428 { "rx_toolong", XM_RXF_LNG_ERR, GM_RXF_LNG_ERR },
429 { "rx_jabber", XM_RXF_JAB_PKT, GM_RXF_JAB_PKT },
430 { "rx_runt", XM_RXE_RUNT, GM_RXE_FRAG },
431 { "rx_too_long", XM_RXF_LNG_ERR, GM_RXF_LNG_ERR },
432 { "rx_fcs_error", XM_RXF_FCS_ERR, GM_RXF_FCS_ERR },
435 static int skge_get_sset_count(struct net_device *dev, int sset)
439 return ARRAY_SIZE(skge_stats);
445 static void skge_get_ethtool_stats(struct net_device *dev,
446 struct ethtool_stats *stats, u64 *data)
448 struct skge_port *skge = netdev_priv(dev);
450 if (is_genesis(skge->hw))
451 genesis_get_stats(skge, data);
453 yukon_get_stats(skge, data);
456 /* Use hardware MIB variables for critical path statistics and
457 * transmit feedback not reported at interrupt.
458 * Other errors are accounted for in interrupt handler.
460 static struct net_device_stats *skge_get_stats(struct net_device *dev)
462 struct skge_port *skge = netdev_priv(dev);
463 u64 data[ARRAY_SIZE(skge_stats)];
465 if (is_genesis(skge->hw))
466 genesis_get_stats(skge, data);
468 yukon_get_stats(skge, data);
470 dev->stats.tx_bytes = data[0];
471 dev->stats.rx_bytes = data[1];
472 dev->stats.tx_packets = data[2] + data[4] + data[6];
473 dev->stats.rx_packets = data[3] + data[5] + data[7];
474 dev->stats.multicast = data[3] + data[5];
475 dev->stats.collisions = data[10];
476 dev->stats.tx_aborted_errors = data[12];
481 static void skge_get_strings(struct net_device *dev, u32 stringset, u8 *data)
487 for (i = 0; i < ARRAY_SIZE(skge_stats); i++)
488 memcpy(data + i * ETH_GSTRING_LEN,
489 skge_stats[i].name, ETH_GSTRING_LEN);
494 static void skge_get_ring_param(struct net_device *dev,
495 struct ethtool_ringparam *p)
497 struct skge_port *skge = netdev_priv(dev);
499 p->rx_max_pending = MAX_RX_RING_SIZE;
500 p->tx_max_pending = MAX_TX_RING_SIZE;
502 p->rx_pending = skge->rx_ring.count;
503 p->tx_pending = skge->tx_ring.count;
506 static int skge_set_ring_param(struct net_device *dev,
507 struct ethtool_ringparam *p)
509 struct skge_port *skge = netdev_priv(dev);
512 if (p->rx_pending == 0 || p->rx_pending > MAX_RX_RING_SIZE ||
513 p->tx_pending < TX_LOW_WATER || p->tx_pending > MAX_TX_RING_SIZE)
516 skge->rx_ring.count = p->rx_pending;
517 skge->tx_ring.count = p->tx_pending;
519 if (netif_running(dev)) {
529 static u32 skge_get_msglevel(struct net_device *netdev)
531 struct skge_port *skge = netdev_priv(netdev);
532 return skge->msg_enable;
535 static void skge_set_msglevel(struct net_device *netdev, u32 value)
537 struct skge_port *skge = netdev_priv(netdev);
538 skge->msg_enable = value;
541 static int skge_nway_reset(struct net_device *dev)
543 struct skge_port *skge = netdev_priv(dev);
545 if (skge->autoneg != AUTONEG_ENABLE || !netif_running(dev))
548 skge_phy_reset(skge);
552 static void skge_get_pauseparam(struct net_device *dev,
553 struct ethtool_pauseparam *ecmd)
555 struct skge_port *skge = netdev_priv(dev);
557 ecmd->rx_pause = ((skge->flow_control == FLOW_MODE_SYMMETRIC) ||
558 (skge->flow_control == FLOW_MODE_SYM_OR_REM));
559 ecmd->tx_pause = (ecmd->rx_pause ||
560 (skge->flow_control == FLOW_MODE_LOC_SEND));
562 ecmd->autoneg = ecmd->rx_pause || ecmd->tx_pause;
565 static int skge_set_pauseparam(struct net_device *dev,
566 struct ethtool_pauseparam *ecmd)
568 struct skge_port *skge = netdev_priv(dev);
569 struct ethtool_pauseparam old;
572 skge_get_pauseparam(dev, &old);
574 if (ecmd->autoneg != old.autoneg)
575 skge->flow_control = ecmd->autoneg ? FLOW_MODE_NONE : FLOW_MODE_SYMMETRIC;
577 if (ecmd->rx_pause && ecmd->tx_pause)
578 skge->flow_control = FLOW_MODE_SYMMETRIC;
579 else if (ecmd->rx_pause && !ecmd->tx_pause)
580 skge->flow_control = FLOW_MODE_SYM_OR_REM;
581 else if (!ecmd->rx_pause && ecmd->tx_pause)
582 skge->flow_control = FLOW_MODE_LOC_SEND;
584 skge->flow_control = FLOW_MODE_NONE;
587 if (netif_running(dev)) {
599 /* Chip internal frequency for clock calculations */
600 static inline u32 hwkhz(const struct skge_hw *hw)
602 return is_genesis(hw) ? 53125 : 78125;
605 /* Chip HZ to microseconds */
606 static inline u32 skge_clk2usec(const struct skge_hw *hw, u32 ticks)
608 return (ticks * 1000) / hwkhz(hw);
611 /* Microseconds to chip HZ */
612 static inline u32 skge_usecs2clk(const struct skge_hw *hw, u32 usec)
614 return hwkhz(hw) * usec / 1000;
617 static int skge_get_coalesce(struct net_device *dev,
618 struct ethtool_coalesce *ecmd)
620 struct skge_port *skge = netdev_priv(dev);
621 struct skge_hw *hw = skge->hw;
622 int port = skge->port;
624 ecmd->rx_coalesce_usecs = 0;
625 ecmd->tx_coalesce_usecs = 0;
627 if (skge_read32(hw, B2_IRQM_CTRL) & TIM_START) {
628 u32 delay = skge_clk2usec(hw, skge_read32(hw, B2_IRQM_INI));
629 u32 msk = skge_read32(hw, B2_IRQM_MSK);
631 if (msk & rxirqmask[port])
632 ecmd->rx_coalesce_usecs = delay;
633 if (msk & txirqmask[port])
634 ecmd->tx_coalesce_usecs = delay;
640 /* Note: interrupt timer is per board, but can turn on/off per port */
641 static int skge_set_coalesce(struct net_device *dev,
642 struct ethtool_coalesce *ecmd)
644 struct skge_port *skge = netdev_priv(dev);
645 struct skge_hw *hw = skge->hw;
646 int port = skge->port;
647 u32 msk = skge_read32(hw, B2_IRQM_MSK);
650 if (ecmd->rx_coalesce_usecs == 0)
651 msk &= ~rxirqmask[port];
652 else if (ecmd->rx_coalesce_usecs < 25 ||
653 ecmd->rx_coalesce_usecs > 33333)
656 msk |= rxirqmask[port];
657 delay = ecmd->rx_coalesce_usecs;
660 if (ecmd->tx_coalesce_usecs == 0)
661 msk &= ~txirqmask[port];
662 else if (ecmd->tx_coalesce_usecs < 25 ||
663 ecmd->tx_coalesce_usecs > 33333)
666 msk |= txirqmask[port];
667 delay = min(delay, ecmd->rx_coalesce_usecs);
670 skge_write32(hw, B2_IRQM_MSK, msk);
672 skge_write32(hw, B2_IRQM_CTRL, TIM_STOP);
674 skge_write32(hw, B2_IRQM_INI, skge_usecs2clk(hw, delay));
675 skge_write32(hw, B2_IRQM_CTRL, TIM_START);
680 enum led_mode { LED_MODE_OFF, LED_MODE_ON, LED_MODE_TST };
681 static void skge_led(struct skge_port *skge, enum led_mode mode)
683 struct skge_hw *hw = skge->hw;
684 int port = skge->port;
686 spin_lock_bh(&hw->phy_lock);
687 if (is_genesis(hw)) {
690 if (hw->phy_type == SK_PHY_BCOM)
691 xm_phy_write(hw, port, PHY_BCOM_P_EXT_CTRL, PHY_B_PEC_LED_OFF);
693 skge_write32(hw, SK_REG(port, TX_LED_VAL), 0);
694 skge_write8(hw, SK_REG(port, TX_LED_CTRL), LED_T_OFF);
696 skge_write8(hw, SK_REG(port, LNK_LED_REG), LINKLED_OFF);
697 skge_write32(hw, SK_REG(port, RX_LED_VAL), 0);
698 skge_write8(hw, SK_REG(port, RX_LED_CTRL), LED_T_OFF);
702 skge_write8(hw, SK_REG(port, LNK_LED_REG), LINKLED_ON);
703 skge_write8(hw, SK_REG(port, LNK_LED_REG), LINKLED_LINKSYNC_ON);
705 skge_write8(hw, SK_REG(port, RX_LED_CTRL), LED_START);
706 skge_write8(hw, SK_REG(port, TX_LED_CTRL), LED_START);
711 skge_write8(hw, SK_REG(port, RX_LED_TST), LED_T_ON);
712 skge_write32(hw, SK_REG(port, RX_LED_VAL), 100);
713 skge_write8(hw, SK_REG(port, RX_LED_CTRL), LED_START);
715 if (hw->phy_type == SK_PHY_BCOM)
716 xm_phy_write(hw, port, PHY_BCOM_P_EXT_CTRL, PHY_B_PEC_LED_ON);
718 skge_write8(hw, SK_REG(port, TX_LED_TST), LED_T_ON);
719 skge_write32(hw, SK_REG(port, TX_LED_VAL), 100);
720 skge_write8(hw, SK_REG(port, TX_LED_CTRL), LED_START);
727 gm_phy_write(hw, port, PHY_MARV_LED_CTRL, 0);
728 gm_phy_write(hw, port, PHY_MARV_LED_OVER,
729 PHY_M_LED_MO_DUP(MO_LED_OFF) |
730 PHY_M_LED_MO_10(MO_LED_OFF) |
731 PHY_M_LED_MO_100(MO_LED_OFF) |
732 PHY_M_LED_MO_1000(MO_LED_OFF) |
733 PHY_M_LED_MO_RX(MO_LED_OFF));
736 gm_phy_write(hw, port, PHY_MARV_LED_CTRL,
737 PHY_M_LED_PULS_DUR(PULS_170MS) |
738 PHY_M_LED_BLINK_RT(BLINK_84MS) |
742 gm_phy_write(hw, port, PHY_MARV_LED_OVER,
743 PHY_M_LED_MO_RX(MO_LED_OFF) |
744 (skge->speed == SPEED_100 ?
745 PHY_M_LED_MO_100(MO_LED_ON) : 0));
748 gm_phy_write(hw, port, PHY_MARV_LED_CTRL, 0);
749 gm_phy_write(hw, port, PHY_MARV_LED_OVER,
750 PHY_M_LED_MO_DUP(MO_LED_ON) |
751 PHY_M_LED_MO_10(MO_LED_ON) |
752 PHY_M_LED_MO_100(MO_LED_ON) |
753 PHY_M_LED_MO_1000(MO_LED_ON) |
754 PHY_M_LED_MO_RX(MO_LED_ON));
757 spin_unlock_bh(&hw->phy_lock);
760 /* blink LED's for finding board */
761 static int skge_set_phys_id(struct net_device *dev,
762 enum ethtool_phys_id_state state)
764 struct skge_port *skge = netdev_priv(dev);
767 case ETHTOOL_ID_ACTIVE:
768 return 2; /* cycle on/off twice per second */
771 skge_led(skge, LED_MODE_TST);
775 skge_led(skge, LED_MODE_OFF);
778 case ETHTOOL_ID_INACTIVE:
779 /* back to regular LED state */
780 skge_led(skge, netif_running(dev) ? LED_MODE_ON : LED_MODE_OFF);
786 static int skge_get_eeprom_len(struct net_device *dev)
788 struct skge_port *skge = netdev_priv(dev);
791 pci_read_config_dword(skge->hw->pdev, PCI_DEV_REG2, ®2);
792 return 1 << (((reg2 & PCI_VPD_ROM_SZ) >> 14) + 8);
795 static u32 skge_vpd_read(struct pci_dev *pdev, int cap, u16 offset)
799 pci_write_config_word(pdev, cap + PCI_VPD_ADDR, offset);
802 pci_read_config_word(pdev, cap + PCI_VPD_ADDR, &offset);
803 } while (!(offset & PCI_VPD_ADDR_F));
805 pci_read_config_dword(pdev, cap + PCI_VPD_DATA, &val);
809 static void skge_vpd_write(struct pci_dev *pdev, int cap, u16 offset, u32 val)
811 pci_write_config_dword(pdev, cap + PCI_VPD_DATA, val);
812 pci_write_config_word(pdev, cap + PCI_VPD_ADDR,
813 offset | PCI_VPD_ADDR_F);
816 pci_read_config_word(pdev, cap + PCI_VPD_ADDR, &offset);
817 } while (offset & PCI_VPD_ADDR_F);
820 static int skge_get_eeprom(struct net_device *dev, struct ethtool_eeprom *eeprom,
823 struct skge_port *skge = netdev_priv(dev);
824 struct pci_dev *pdev = skge->hw->pdev;
825 int cap = pci_find_capability(pdev, PCI_CAP_ID_VPD);
826 int length = eeprom->len;
827 u16 offset = eeprom->offset;
832 eeprom->magic = SKGE_EEPROM_MAGIC;
835 u32 val = skge_vpd_read(pdev, cap, offset);
836 int n = min_t(int, length, sizeof(val));
838 memcpy(data, &val, n);
846 static int skge_set_eeprom(struct net_device *dev, struct ethtool_eeprom *eeprom,
849 struct skge_port *skge = netdev_priv(dev);
850 struct pci_dev *pdev = skge->hw->pdev;
851 int cap = pci_find_capability(pdev, PCI_CAP_ID_VPD);
852 int length = eeprom->len;
853 u16 offset = eeprom->offset;
858 if (eeprom->magic != SKGE_EEPROM_MAGIC)
863 int n = min_t(int, length, sizeof(val));
866 val = skge_vpd_read(pdev, cap, offset);
867 memcpy(&val, data, n);
869 skge_vpd_write(pdev, cap, offset, val);
878 static const struct ethtool_ops skge_ethtool_ops = {
879 .get_drvinfo = skge_get_drvinfo,
880 .get_regs_len = skge_get_regs_len,
881 .get_regs = skge_get_regs,
882 .get_wol = skge_get_wol,
883 .set_wol = skge_set_wol,
884 .get_msglevel = skge_get_msglevel,
885 .set_msglevel = skge_set_msglevel,
886 .nway_reset = skge_nway_reset,
887 .get_link = ethtool_op_get_link,
888 .get_eeprom_len = skge_get_eeprom_len,
889 .get_eeprom = skge_get_eeprom,
890 .set_eeprom = skge_set_eeprom,
891 .get_ringparam = skge_get_ring_param,
892 .set_ringparam = skge_set_ring_param,
893 .get_pauseparam = skge_get_pauseparam,
894 .set_pauseparam = skge_set_pauseparam,
895 .get_coalesce = skge_get_coalesce,
896 .set_coalesce = skge_set_coalesce,
897 .get_strings = skge_get_strings,
898 .set_phys_id = skge_set_phys_id,
899 .get_sset_count = skge_get_sset_count,
900 .get_ethtool_stats = skge_get_ethtool_stats,
901 .get_link_ksettings = skge_get_link_ksettings,
902 .set_link_ksettings = skge_set_link_ksettings,
906 * Allocate ring elements and chain them together
907 * One-to-one association of board descriptors with ring elements
909 static int skge_ring_alloc(struct skge_ring *ring, void *vaddr, u32 base)
911 struct skge_tx_desc *d;
912 struct skge_element *e;
915 ring->start = kcalloc(ring->count, sizeof(*e), GFP_KERNEL);
919 for (i = 0, e = ring->start, d = vaddr; i < ring->count; i++, e++, d++) {
921 if (i == ring->count - 1) {
922 e->next = ring->start;
923 d->next_offset = base;
926 d->next_offset = base + (i+1) * sizeof(*d);
929 ring->to_use = ring->to_clean = ring->start;
934 /* Allocate and setup a new buffer for receiving */
935 static int skge_rx_setup(struct skge_port *skge, struct skge_element *e,
936 struct sk_buff *skb, unsigned int bufsize)
938 struct skge_rx_desc *rd = e->desc;
941 map = pci_map_single(skge->hw->pdev, skb->data, bufsize,
944 if (pci_dma_mapping_error(skge->hw->pdev, map))
947 rd->dma_lo = lower_32_bits(map);
948 rd->dma_hi = upper_32_bits(map);
950 rd->csum1_start = ETH_HLEN;
951 rd->csum2_start = ETH_HLEN;
957 rd->control = BMU_OWN | BMU_STF | BMU_IRQ_EOF | BMU_TCP_CHECK | bufsize;
958 dma_unmap_addr_set(e, mapaddr, map);
959 dma_unmap_len_set(e, maplen, bufsize);
963 /* Resume receiving using existing skb,
964 * Note: DMA address is not changed by chip.
965 * MTU not changed while receiver active.
967 static inline void skge_rx_reuse(struct skge_element *e, unsigned int size)
969 struct skge_rx_desc *rd = e->desc;
972 rd->csum2_start = ETH_HLEN;
976 rd->control = BMU_OWN | BMU_STF | BMU_IRQ_EOF | BMU_TCP_CHECK | size;
980 /* Free all buffers in receive ring, assumes receiver stopped */
981 static void skge_rx_clean(struct skge_port *skge)
983 struct skge_hw *hw = skge->hw;
984 struct skge_ring *ring = &skge->rx_ring;
985 struct skge_element *e;
989 struct skge_rx_desc *rd = e->desc;
992 pci_unmap_single(hw->pdev,
993 dma_unmap_addr(e, mapaddr),
994 dma_unmap_len(e, maplen),
996 dev_kfree_skb(e->skb);
999 } while ((e = e->next) != ring->start);
1003 /* Allocate buffers for receive ring
1004 * For receive: to_clean is next received frame.
1006 static int skge_rx_fill(struct net_device *dev)
1008 struct skge_port *skge = netdev_priv(dev);
1009 struct skge_ring *ring = &skge->rx_ring;
1010 struct skge_element *e;
1014 struct sk_buff *skb;
1016 skb = __netdev_alloc_skb(dev, skge->rx_buf_size + NET_IP_ALIGN,
1021 skb_reserve(skb, NET_IP_ALIGN);
1022 if (skge_rx_setup(skge, e, skb, skge->rx_buf_size) < 0) {
1026 } while ((e = e->next) != ring->start);
1028 ring->to_clean = ring->start;
1032 static const char *skge_pause(enum pause_status status)
1035 case FLOW_STAT_NONE:
1037 case FLOW_STAT_REM_SEND:
1039 case FLOW_STAT_LOC_SEND:
1041 case FLOW_STAT_SYMMETRIC: /* Both station may send PAUSE */
1044 return "indeterminated";
1049 static void skge_link_up(struct skge_port *skge)
1051 skge_write8(skge->hw, SK_REG(skge->port, LNK_LED_REG),
1052 LED_BLK_OFF|LED_SYNC_OFF|LED_REG_ON);
1054 netif_carrier_on(skge->netdev);
1055 netif_wake_queue(skge->netdev);
1057 netif_info(skge, link, skge->netdev,
1058 "Link is up at %d Mbps, %s duplex, flow control %s\n",
1060 skge->duplex == DUPLEX_FULL ? "full" : "half",
1061 skge_pause(skge->flow_status));
1064 static void skge_link_down(struct skge_port *skge)
1066 skge_write8(skge->hw, SK_REG(skge->port, LNK_LED_REG), LED_REG_OFF);
1067 netif_carrier_off(skge->netdev);
1068 netif_stop_queue(skge->netdev);
1070 netif_info(skge, link, skge->netdev, "Link is down\n");
1073 static void xm_link_down(struct skge_hw *hw, int port)
1075 struct net_device *dev = hw->dev[port];
1076 struct skge_port *skge = netdev_priv(dev);
1078 xm_write16(hw, port, XM_IMSK, XM_IMSK_DISABLE);
1080 if (netif_carrier_ok(dev))
1081 skge_link_down(skge);
1084 static int __xm_phy_read(struct skge_hw *hw, int port, u16 reg, u16 *val)
1088 xm_write16(hw, port, XM_PHY_ADDR, reg | hw->phy_addr);
1089 *val = xm_read16(hw, port, XM_PHY_DATA);
1091 if (hw->phy_type == SK_PHY_XMAC)
1094 for (i = 0; i < PHY_RETRIES; i++) {
1095 if (xm_read16(hw, port, XM_MMU_CMD) & XM_MMU_PHY_RDY)
1102 *val = xm_read16(hw, port, XM_PHY_DATA);
1107 static u16 xm_phy_read(struct skge_hw *hw, int port, u16 reg)
1110 if (__xm_phy_read(hw, port, reg, &v))
1111 pr_warn("%s: phy read timed out\n", hw->dev[port]->name);
1115 static int xm_phy_write(struct skge_hw *hw, int port, u16 reg, u16 val)
1119 xm_write16(hw, port, XM_PHY_ADDR, reg | hw->phy_addr);
1120 for (i = 0; i < PHY_RETRIES; i++) {
1121 if (!(xm_read16(hw, port, XM_MMU_CMD) & XM_MMU_PHY_BUSY))
1128 xm_write16(hw, port, XM_PHY_DATA, val);
1129 for (i = 0; i < PHY_RETRIES; i++) {
1130 if (!(xm_read16(hw, port, XM_MMU_CMD) & XM_MMU_PHY_BUSY))
1137 static void genesis_init(struct skge_hw *hw)
1139 /* set blink source counter */
1140 skge_write32(hw, B2_BSC_INI, (SK_BLK_DUR * SK_FACT_53) / 100);
1141 skge_write8(hw, B2_BSC_CTRL, BSC_START);
1143 /* configure mac arbiter */
1144 skge_write16(hw, B3_MA_TO_CTRL, MA_RST_CLR);
1146 /* configure mac arbiter timeout values */
1147 skge_write8(hw, B3_MA_TOINI_RX1, SK_MAC_TO_53);
1148 skge_write8(hw, B3_MA_TOINI_RX2, SK_MAC_TO_53);
1149 skge_write8(hw, B3_MA_TOINI_TX1, SK_MAC_TO_53);
1150 skge_write8(hw, B3_MA_TOINI_TX2, SK_MAC_TO_53);
1152 skge_write8(hw, B3_MA_RCINI_RX1, 0);
1153 skge_write8(hw, B3_MA_RCINI_RX2, 0);
1154 skge_write8(hw, B3_MA_RCINI_TX1, 0);
1155 skge_write8(hw, B3_MA_RCINI_TX2, 0);
1157 /* configure packet arbiter timeout */
1158 skge_write16(hw, B3_PA_CTRL, PA_RST_CLR);
1159 skge_write16(hw, B3_PA_TOINI_RX1, SK_PKT_TO_MAX);
1160 skge_write16(hw, B3_PA_TOINI_TX1, SK_PKT_TO_MAX);
1161 skge_write16(hw, B3_PA_TOINI_RX2, SK_PKT_TO_MAX);
1162 skge_write16(hw, B3_PA_TOINI_TX2, SK_PKT_TO_MAX);
1165 static void genesis_reset(struct skge_hw *hw, int port)
1167 static const u8 zero[8] = { 0 };
1170 skge_write8(hw, SK_REG(port, GMAC_IRQ_MSK), 0);
1172 /* reset the statistics module */
1173 xm_write32(hw, port, XM_GP_PORT, XM_GP_RES_STAT);
1174 xm_write16(hw, port, XM_IMSK, XM_IMSK_DISABLE);
1175 xm_write32(hw, port, XM_MODE, 0); /* clear Mode Reg */
1176 xm_write16(hw, port, XM_TX_CMD, 0); /* reset TX CMD Reg */
1177 xm_write16(hw, port, XM_RX_CMD, 0); /* reset RX CMD Reg */
1179 /* disable Broadcom PHY IRQ */
1180 if (hw->phy_type == SK_PHY_BCOM)
1181 xm_write16(hw, port, PHY_BCOM_INT_MASK, 0xffff);
1183 xm_outhash(hw, port, XM_HSM, zero);
1185 /* Flush TX and RX fifo */
1186 reg = xm_read32(hw, port, XM_MODE);
1187 xm_write32(hw, port, XM_MODE, reg | XM_MD_FTF);
1188 xm_write32(hw, port, XM_MODE, reg | XM_MD_FRF);
1191 /* Convert mode to MII values */
1192 static const u16 phy_pause_map[] = {
1193 [FLOW_MODE_NONE] = 0,
1194 [FLOW_MODE_LOC_SEND] = PHY_AN_PAUSE_ASYM,
1195 [FLOW_MODE_SYMMETRIC] = PHY_AN_PAUSE_CAP,
1196 [FLOW_MODE_SYM_OR_REM] = PHY_AN_PAUSE_CAP | PHY_AN_PAUSE_ASYM,
1199 /* special defines for FIBER (88E1011S only) */
1200 static const u16 fiber_pause_map[] = {
1201 [FLOW_MODE_NONE] = PHY_X_P_NO_PAUSE,
1202 [FLOW_MODE_LOC_SEND] = PHY_X_P_ASYM_MD,
1203 [FLOW_MODE_SYMMETRIC] = PHY_X_P_SYM_MD,
1204 [FLOW_MODE_SYM_OR_REM] = PHY_X_P_BOTH_MD,
1208 /* Check status of Broadcom phy link */
1209 static void bcom_check_link(struct skge_hw *hw, int port)
1211 struct net_device *dev = hw->dev[port];
1212 struct skge_port *skge = netdev_priv(dev);
1215 /* read twice because of latch */
1216 xm_phy_read(hw, port, PHY_BCOM_STAT);
1217 status = xm_phy_read(hw, port, PHY_BCOM_STAT);
1219 if ((status & PHY_ST_LSYNC) == 0) {
1220 xm_link_down(hw, port);
1224 if (skge->autoneg == AUTONEG_ENABLE) {
1227 if (!(status & PHY_ST_AN_OVER))
1230 lpa = xm_phy_read(hw, port, PHY_XMAC_AUNE_LP);
1231 if (lpa & PHY_B_AN_RF) {
1232 netdev_notice(dev, "remote fault\n");
1236 aux = xm_phy_read(hw, port, PHY_BCOM_AUX_STAT);
1238 /* Check Duplex mismatch */
1239 switch (aux & PHY_B_AS_AN_RES_MSK) {
1240 case PHY_B_RES_1000FD:
1241 skge->duplex = DUPLEX_FULL;
1243 case PHY_B_RES_1000HD:
1244 skge->duplex = DUPLEX_HALF;
1247 netdev_notice(dev, "duplex mismatch\n");
1251 /* We are using IEEE 802.3z/D5.0 Table 37-4 */
1252 switch (aux & PHY_B_AS_PAUSE_MSK) {
1253 case PHY_B_AS_PAUSE_MSK:
1254 skge->flow_status = FLOW_STAT_SYMMETRIC;
1257 skge->flow_status = FLOW_STAT_REM_SEND;
1260 skge->flow_status = FLOW_STAT_LOC_SEND;
1263 skge->flow_status = FLOW_STAT_NONE;
1265 skge->speed = SPEED_1000;
1268 if (!netif_carrier_ok(dev))
1269 genesis_link_up(skge);
1272 /* Broadcom 5400 only supports giagabit! SysKonnect did not put an additional
1273 * Phy on for 100 or 10Mbit operation
1275 static void bcom_phy_init(struct skge_port *skge)
1277 struct skge_hw *hw = skge->hw;
1278 int port = skge->port;
1280 u16 id1, r, ext, ctl;
1282 /* magic workaround patterns for Broadcom */
1283 static const struct {
1287 { 0x18, 0x0c20 }, { 0x17, 0x0012 }, { 0x15, 0x1104 },
1288 { 0x17, 0x0013 }, { 0x15, 0x0404 }, { 0x17, 0x8006 },
1289 { 0x15, 0x0132 }, { 0x17, 0x8006 }, { 0x15, 0x0232 },
1290 { 0x17, 0x800D }, { 0x15, 0x000F }, { 0x18, 0x0420 },
1292 { 0x18, 0x0c20 }, { 0x17, 0x0012 }, { 0x15, 0x1204 },
1293 { 0x17, 0x0013 }, { 0x15, 0x0A04 }, { 0x18, 0x0420 },
1296 /* read Id from external PHY (all have the same address) */
1297 id1 = xm_phy_read(hw, port, PHY_XMAC_ID1);
1299 /* Optimize MDIO transfer by suppressing preamble. */
1300 r = xm_read16(hw, port, XM_MMU_CMD);
1302 xm_write16(hw, port, XM_MMU_CMD, r);
1305 case PHY_BCOM_ID1_C0:
1307 * Workaround BCOM Errata for the C0 type.
1308 * Write magic patterns to reserved registers.
1310 for (i = 0; i < ARRAY_SIZE(C0hack); i++)
1311 xm_phy_write(hw, port,
1312 C0hack[i].reg, C0hack[i].val);
1315 case PHY_BCOM_ID1_A1:
1317 * Workaround BCOM Errata for the A1 type.
1318 * Write magic patterns to reserved registers.
1320 for (i = 0; i < ARRAY_SIZE(A1hack); i++)
1321 xm_phy_write(hw, port,
1322 A1hack[i].reg, A1hack[i].val);
1327 * Workaround BCOM Errata (#10523) for all BCom PHYs.
1328 * Disable Power Management after reset.
1330 r = xm_phy_read(hw, port, PHY_BCOM_AUX_CTRL);
1331 r |= PHY_B_AC_DIS_PM;
1332 xm_phy_write(hw, port, PHY_BCOM_AUX_CTRL, r);
1335 xm_read16(hw, port, XM_ISRC);
1337 ext = PHY_B_PEC_EN_LTR; /* enable tx led */
1338 ctl = PHY_CT_SP1000; /* always 1000mbit */
1340 if (skge->autoneg == AUTONEG_ENABLE) {
1342 * Workaround BCOM Errata #1 for the C5 type.
1343 * 1000Base-T Link Acquisition Failure in Slave Mode
1344 * Set Repeater/DTE bit 10 of the 1000Base-T Control Register
1346 u16 adv = PHY_B_1000C_RD;
1347 if (skge->advertising & ADVERTISED_1000baseT_Half)
1348 adv |= PHY_B_1000C_AHD;
1349 if (skge->advertising & ADVERTISED_1000baseT_Full)
1350 adv |= PHY_B_1000C_AFD;
1351 xm_phy_write(hw, port, PHY_BCOM_1000T_CTRL, adv);
1353 ctl |= PHY_CT_ANE | PHY_CT_RE_CFG;
1355 if (skge->duplex == DUPLEX_FULL)
1356 ctl |= PHY_CT_DUP_MD;
1357 /* Force to slave */
1358 xm_phy_write(hw, port, PHY_BCOM_1000T_CTRL, PHY_B_1000C_MSE);
1361 /* Set autonegotiation pause parameters */
1362 xm_phy_write(hw, port, PHY_BCOM_AUNE_ADV,
1363 phy_pause_map[skge->flow_control] | PHY_AN_CSMA);
1365 /* Handle Jumbo frames */
1366 if (hw->dev[port]->mtu > ETH_DATA_LEN) {
1367 xm_phy_write(hw, port, PHY_BCOM_AUX_CTRL,
1368 PHY_B_AC_TX_TST | PHY_B_AC_LONG_PACK);
1370 ext |= PHY_B_PEC_HIGH_LA;
1374 xm_phy_write(hw, port, PHY_BCOM_P_EXT_CTRL, ext);
1375 xm_phy_write(hw, port, PHY_BCOM_CTRL, ctl);
1377 /* Use link status change interrupt */
1378 xm_phy_write(hw, port, PHY_BCOM_INT_MASK, PHY_B_DEF_MSK);
1381 static void xm_phy_init(struct skge_port *skge)
1383 struct skge_hw *hw = skge->hw;
1384 int port = skge->port;
1387 if (skge->autoneg == AUTONEG_ENABLE) {
1388 if (skge->advertising & ADVERTISED_1000baseT_Half)
1389 ctrl |= PHY_X_AN_HD;
1390 if (skge->advertising & ADVERTISED_1000baseT_Full)
1391 ctrl |= PHY_X_AN_FD;
1393 ctrl |= fiber_pause_map[skge->flow_control];
1395 xm_phy_write(hw, port, PHY_XMAC_AUNE_ADV, ctrl);
1397 /* Restart Auto-negotiation */
1398 ctrl = PHY_CT_ANE | PHY_CT_RE_CFG;
1400 /* Set DuplexMode in Config register */
1401 if (skge->duplex == DUPLEX_FULL)
1402 ctrl |= PHY_CT_DUP_MD;
1404 * Do NOT enable Auto-negotiation here. This would hold
1405 * the link down because no IDLEs are transmitted
1409 xm_phy_write(hw, port, PHY_XMAC_CTRL, ctrl);
1411 /* Poll PHY for status changes */
1412 mod_timer(&skge->link_timer, jiffies + LINK_HZ);
1415 static int xm_check_link(struct net_device *dev)
1417 struct skge_port *skge = netdev_priv(dev);
1418 struct skge_hw *hw = skge->hw;
1419 int port = skge->port;
1422 /* read twice because of latch */
1423 xm_phy_read(hw, port, PHY_XMAC_STAT);
1424 status = xm_phy_read(hw, port, PHY_XMAC_STAT);
1426 if ((status & PHY_ST_LSYNC) == 0) {
1427 xm_link_down(hw, port);
1431 if (skge->autoneg == AUTONEG_ENABLE) {
1434 if (!(status & PHY_ST_AN_OVER))
1437 lpa = xm_phy_read(hw, port, PHY_XMAC_AUNE_LP);
1438 if (lpa & PHY_B_AN_RF) {
1439 netdev_notice(dev, "remote fault\n");
1443 res = xm_phy_read(hw, port, PHY_XMAC_RES_ABI);
1445 /* Check Duplex mismatch */
1446 switch (res & (PHY_X_RS_HD | PHY_X_RS_FD)) {
1448 skge->duplex = DUPLEX_FULL;
1451 skge->duplex = DUPLEX_HALF;
1454 netdev_notice(dev, "duplex mismatch\n");
1458 /* We are using IEEE 802.3z/D5.0 Table 37-4 */
1459 if ((skge->flow_control == FLOW_MODE_SYMMETRIC ||
1460 skge->flow_control == FLOW_MODE_SYM_OR_REM) &&
1461 (lpa & PHY_X_P_SYM_MD))
1462 skge->flow_status = FLOW_STAT_SYMMETRIC;
1463 else if (skge->flow_control == FLOW_MODE_SYM_OR_REM &&
1464 (lpa & PHY_X_RS_PAUSE) == PHY_X_P_ASYM_MD)
1465 /* Enable PAUSE receive, disable PAUSE transmit */
1466 skge->flow_status = FLOW_STAT_REM_SEND;
1467 else if (skge->flow_control == FLOW_MODE_LOC_SEND &&
1468 (lpa & PHY_X_RS_PAUSE) == PHY_X_P_BOTH_MD)
1469 /* Disable PAUSE receive, enable PAUSE transmit */
1470 skge->flow_status = FLOW_STAT_LOC_SEND;
1472 skge->flow_status = FLOW_STAT_NONE;
1474 skge->speed = SPEED_1000;
1477 if (!netif_carrier_ok(dev))
1478 genesis_link_up(skge);
1482 /* Poll to check for link coming up.
1484 * Since internal PHY is wired to a level triggered pin, can't
1485 * get an interrupt when carrier is detected, need to poll for
1488 static void xm_link_timer(struct timer_list *t)
1490 struct skge_port *skge = from_timer(skge, t, link_timer);
1491 struct net_device *dev = skge->netdev;
1492 struct skge_hw *hw = skge->hw;
1493 int port = skge->port;
1495 unsigned long flags;
1497 if (!netif_running(dev))
1500 spin_lock_irqsave(&hw->phy_lock, flags);
1503 * Verify that the link by checking GPIO register three times.
1504 * This pin has the signal from the link_sync pin connected to it.
1506 for (i = 0; i < 3; i++) {
1507 if (xm_read16(hw, port, XM_GP_PORT) & XM_GP_INP_ASS)
1511 /* Re-enable interrupt to detect link down */
1512 if (xm_check_link(dev)) {
1513 u16 msk = xm_read16(hw, port, XM_IMSK);
1514 msk &= ~XM_IS_INP_ASS;
1515 xm_write16(hw, port, XM_IMSK, msk);
1516 xm_read16(hw, port, XM_ISRC);
1519 mod_timer(&skge->link_timer,
1520 round_jiffies(jiffies + LINK_HZ));
1522 spin_unlock_irqrestore(&hw->phy_lock, flags);
1525 static void genesis_mac_init(struct skge_hw *hw, int port)
1527 struct net_device *dev = hw->dev[port];
1528 struct skge_port *skge = netdev_priv(dev);
1529 int jumbo = hw->dev[port]->mtu > ETH_DATA_LEN;
1532 static const u8 zero[6] = { 0 };
1534 for (i = 0; i < 10; i++) {
1535 skge_write16(hw, SK_REG(port, TX_MFF_CTRL1),
1537 if (skge_read16(hw, SK_REG(port, TX_MFF_CTRL1)) & MFF_SET_MAC_RST)
1542 netdev_warn(dev, "genesis reset failed\n");
1545 /* Unreset the XMAC. */
1546 skge_write16(hw, SK_REG(port, TX_MFF_CTRL1), MFF_CLR_MAC_RST);
1549 * Perform additional initialization for external PHYs,
1550 * namely for the 1000baseTX cards that use the XMAC's
1553 if (hw->phy_type != SK_PHY_XMAC) {
1554 /* Take external Phy out of reset */
1555 r = skge_read32(hw, B2_GP_IO);
1557 r |= GP_DIR_0|GP_IO_0;
1559 r |= GP_DIR_2|GP_IO_2;
1561 skge_write32(hw, B2_GP_IO, r);
1563 /* Enable GMII interface */
1564 xm_write16(hw, port, XM_HW_CFG, XM_HW_GMII_MD);
1568 switch (hw->phy_type) {
1573 bcom_phy_init(skge);
1574 bcom_check_link(hw, port);
1577 /* Set Station Address */
1578 xm_outaddr(hw, port, XM_SA, dev->dev_addr);
1580 /* We don't use match addresses so clear */
1581 for (i = 1; i < 16; i++)
1582 xm_outaddr(hw, port, XM_EXM(i), zero);
1584 /* Clear MIB counters */
1585 xm_write16(hw, port, XM_STAT_CMD,
1586 XM_SC_CLR_RXC | XM_SC_CLR_TXC);
1587 /* Clear two times according to Errata #3 */
1588 xm_write16(hw, port, XM_STAT_CMD,
1589 XM_SC_CLR_RXC | XM_SC_CLR_TXC);
1591 /* configure Rx High Water Mark (XM_RX_HI_WM) */
1592 xm_write16(hw, port, XM_RX_HI_WM, 1450);
1594 /* We don't need the FCS appended to the packet. */
1595 r = XM_RX_LENERR_OK | XM_RX_STRIP_FCS;
1597 r |= XM_RX_BIG_PK_OK;
1599 if (skge->duplex == DUPLEX_HALF) {
1601 * If in manual half duplex mode the other side might be in
1602 * full duplex mode, so ignore if a carrier extension is not seen
1603 * on frames received
1605 r |= XM_RX_DIS_CEXT;
1607 xm_write16(hw, port, XM_RX_CMD, r);
1609 /* We want short frames padded to 60 bytes. */
1610 xm_write16(hw, port, XM_TX_CMD, XM_TX_AUTO_PAD);
1612 /* Increase threshold for jumbo frames on dual port */
1613 if (hw->ports > 1 && jumbo)
1614 xm_write16(hw, port, XM_TX_THR, 1020);
1616 xm_write16(hw, port, XM_TX_THR, 512);
1619 * Enable the reception of all error frames. This is is
1620 * a necessary evil due to the design of the XMAC. The
1621 * XMAC's receive FIFO is only 8K in size, however jumbo
1622 * frames can be up to 9000 bytes in length. When bad
1623 * frame filtering is enabled, the XMAC's RX FIFO operates
1624 * in 'store and forward' mode. For this to work, the
1625 * entire frame has to fit into the FIFO, but that means
1626 * that jumbo frames larger than 8192 bytes will be
1627 * truncated. Disabling all bad frame filtering causes
1628 * the RX FIFO to operate in streaming mode, in which
1629 * case the XMAC will start transferring frames out of the
1630 * RX FIFO as soon as the FIFO threshold is reached.
1632 xm_write32(hw, port, XM_MODE, XM_DEF_MODE);
1636 * Initialize the Receive Counter Event Mask (XM_RX_EV_MSK)
1637 * - Enable all bits excepting 'Octets Rx OK Low CntOv'
1638 * and 'Octets Rx OK Hi Cnt Ov'.
1640 xm_write32(hw, port, XM_RX_EV_MSK, XMR_DEF_MSK);
1643 * Initialize the Transmit Counter Event Mask (XM_TX_EV_MSK)
1644 * - Enable all bits excepting 'Octets Tx OK Low CntOv'
1645 * and 'Octets Tx OK Hi Cnt Ov'.
1647 xm_write32(hw, port, XM_TX_EV_MSK, XMT_DEF_MSK);
1649 /* Configure MAC arbiter */
1650 skge_write16(hw, B3_MA_TO_CTRL, MA_RST_CLR);
1652 /* configure timeout values */
1653 skge_write8(hw, B3_MA_TOINI_RX1, 72);
1654 skge_write8(hw, B3_MA_TOINI_RX2, 72);
1655 skge_write8(hw, B3_MA_TOINI_TX1, 72);
1656 skge_write8(hw, B3_MA_TOINI_TX2, 72);
1658 skge_write8(hw, B3_MA_RCINI_RX1, 0);
1659 skge_write8(hw, B3_MA_RCINI_RX2, 0);
1660 skge_write8(hw, B3_MA_RCINI_TX1, 0);
1661 skge_write8(hw, B3_MA_RCINI_TX2, 0);
1663 /* Configure Rx MAC FIFO */
1664 skge_write8(hw, SK_REG(port, RX_MFF_CTRL2), MFF_RST_CLR);
1665 skge_write16(hw, SK_REG(port, RX_MFF_CTRL1), MFF_ENA_TIM_PAT);
1666 skge_write8(hw, SK_REG(port, RX_MFF_CTRL2), MFF_ENA_OP_MD);
1668 /* Configure Tx MAC FIFO */
1669 skge_write8(hw, SK_REG(port, TX_MFF_CTRL2), MFF_RST_CLR);
1670 skge_write16(hw, SK_REG(port, TX_MFF_CTRL1), MFF_TX_CTRL_DEF);
1671 skge_write8(hw, SK_REG(port, TX_MFF_CTRL2), MFF_ENA_OP_MD);
1674 /* Enable frame flushing if jumbo frames used */
1675 skge_write16(hw, SK_REG(port, RX_MFF_CTRL1), MFF_ENA_FLUSH);
1677 /* enable timeout timers if normal frames */
1678 skge_write16(hw, B3_PA_CTRL,
1679 (port == 0) ? PA_ENA_TO_TX1 : PA_ENA_TO_TX2);
1683 static void genesis_stop(struct skge_port *skge)
1685 struct skge_hw *hw = skge->hw;
1686 int port = skge->port;
1687 unsigned retries = 1000;
1690 /* Disable Tx and Rx */
1691 cmd = xm_read16(hw, port, XM_MMU_CMD);
1692 cmd &= ~(XM_MMU_ENA_RX | XM_MMU_ENA_TX);
1693 xm_write16(hw, port, XM_MMU_CMD, cmd);
1695 genesis_reset(hw, port);
1697 /* Clear Tx packet arbiter timeout IRQ */
1698 skge_write16(hw, B3_PA_CTRL,
1699 port == 0 ? PA_CLR_TO_TX1 : PA_CLR_TO_TX2);
1702 skge_write16(hw, SK_REG(port, TX_MFF_CTRL1), MFF_CLR_MAC_RST);
1704 skge_write16(hw, SK_REG(port, TX_MFF_CTRL1), MFF_SET_MAC_RST);
1705 if (!(skge_read16(hw, SK_REG(port, TX_MFF_CTRL1)) & MFF_SET_MAC_RST))
1707 } while (--retries > 0);
1709 /* For external PHYs there must be special handling */
1710 if (hw->phy_type != SK_PHY_XMAC) {
1711 u32 reg = skge_read32(hw, B2_GP_IO);
1719 skge_write32(hw, B2_GP_IO, reg);
1720 skge_read32(hw, B2_GP_IO);
1723 xm_write16(hw, port, XM_MMU_CMD,
1724 xm_read16(hw, port, XM_MMU_CMD)
1725 & ~(XM_MMU_ENA_RX | XM_MMU_ENA_TX));
1727 xm_read16(hw, port, XM_MMU_CMD);
1731 static void genesis_get_stats(struct skge_port *skge, u64 *data)
1733 struct skge_hw *hw = skge->hw;
1734 int port = skge->port;
1736 unsigned long timeout = jiffies + HZ;
1738 xm_write16(hw, port,
1739 XM_STAT_CMD, XM_SC_SNP_TXC | XM_SC_SNP_RXC);
1741 /* wait for update to complete */
1742 while (xm_read16(hw, port, XM_STAT_CMD)
1743 & (XM_SC_SNP_TXC | XM_SC_SNP_RXC)) {
1744 if (time_after(jiffies, timeout))
1749 /* special case for 64 bit octet counter */
1750 data[0] = (u64) xm_read32(hw, port, XM_TXO_OK_HI) << 32
1751 | xm_read32(hw, port, XM_TXO_OK_LO);
1752 data[1] = (u64) xm_read32(hw, port, XM_RXO_OK_HI) << 32
1753 | xm_read32(hw, port, XM_RXO_OK_LO);
1755 for (i = 2; i < ARRAY_SIZE(skge_stats); i++)
1756 data[i] = xm_read32(hw, port, skge_stats[i].xmac_offset);
1759 static void genesis_mac_intr(struct skge_hw *hw, int port)
1761 struct net_device *dev = hw->dev[port];
1762 struct skge_port *skge = netdev_priv(dev);
1763 u16 status = xm_read16(hw, port, XM_ISRC);
1765 netif_printk(skge, intr, KERN_DEBUG, skge->netdev,
1766 "mac interrupt status 0x%x\n", status);
1768 if (hw->phy_type == SK_PHY_XMAC && (status & XM_IS_INP_ASS)) {
1769 xm_link_down(hw, port);
1770 mod_timer(&skge->link_timer, jiffies + 1);
1773 if (status & XM_IS_TXF_UR) {
1774 xm_write32(hw, port, XM_MODE, XM_MD_FTF);
1775 ++dev->stats.tx_fifo_errors;
1779 static void genesis_link_up(struct skge_port *skge)
1781 struct skge_hw *hw = skge->hw;
1782 int port = skge->port;
1786 cmd = xm_read16(hw, port, XM_MMU_CMD);
1789 * enabling pause frame reception is required for 1000BT
1790 * because the XMAC is not reset if the link is going down
1792 if (skge->flow_status == FLOW_STAT_NONE ||
1793 skge->flow_status == FLOW_STAT_LOC_SEND)
1794 /* Disable Pause Frame Reception */
1795 cmd |= XM_MMU_IGN_PF;
1797 /* Enable Pause Frame Reception */
1798 cmd &= ~XM_MMU_IGN_PF;
1800 xm_write16(hw, port, XM_MMU_CMD, cmd);
1802 mode = xm_read32(hw, port, XM_MODE);
1803 if (skge->flow_status == FLOW_STAT_SYMMETRIC ||
1804 skge->flow_status == FLOW_STAT_LOC_SEND) {
1806 * Configure Pause Frame Generation
1807 * Use internal and external Pause Frame Generation.
1808 * Sending pause frames is edge triggered.
1809 * Send a Pause frame with the maximum pause time if
1810 * internal oder external FIFO full condition occurs.
1811 * Send a zero pause time frame to re-start transmission.
1813 /* XM_PAUSE_DA = '010000C28001' (default) */
1814 /* XM_MAC_PTIME = 0xffff (maximum) */
1815 /* remember this value is defined in big endian (!) */
1816 xm_write16(hw, port, XM_MAC_PTIME, 0xffff);
1818 mode |= XM_PAUSE_MODE;
1819 skge_write16(hw, SK_REG(port, RX_MFF_CTRL1), MFF_ENA_PAUSE);
1822 * disable pause frame generation is required for 1000BT
1823 * because the XMAC is not reset if the link is going down
1825 /* Disable Pause Mode in Mode Register */
1826 mode &= ~XM_PAUSE_MODE;
1828 skge_write16(hw, SK_REG(port, RX_MFF_CTRL1), MFF_DIS_PAUSE);
1831 xm_write32(hw, port, XM_MODE, mode);
1833 /* Turn on detection of Tx underrun */
1834 msk = xm_read16(hw, port, XM_IMSK);
1835 msk &= ~XM_IS_TXF_UR;
1836 xm_write16(hw, port, XM_IMSK, msk);
1838 xm_read16(hw, port, XM_ISRC);
1840 /* get MMU Command Reg. */
1841 cmd = xm_read16(hw, port, XM_MMU_CMD);
1842 if (hw->phy_type != SK_PHY_XMAC && skge->duplex == DUPLEX_FULL)
1843 cmd |= XM_MMU_GMII_FD;
1846 * Workaround BCOM Errata (#10523) for all BCom Phys
1847 * Enable Power Management after link up
1849 if (hw->phy_type == SK_PHY_BCOM) {
1850 xm_phy_write(hw, port, PHY_BCOM_AUX_CTRL,
1851 xm_phy_read(hw, port, PHY_BCOM_AUX_CTRL)
1852 & ~PHY_B_AC_DIS_PM);
1853 xm_phy_write(hw, port, PHY_BCOM_INT_MASK, PHY_B_DEF_MSK);
1857 xm_write16(hw, port, XM_MMU_CMD,
1858 cmd | XM_MMU_ENA_RX | XM_MMU_ENA_TX);
1863 static inline void bcom_phy_intr(struct skge_port *skge)
1865 struct skge_hw *hw = skge->hw;
1866 int port = skge->port;
1869 isrc = xm_phy_read(hw, port, PHY_BCOM_INT_STAT);
1870 netif_printk(skge, intr, KERN_DEBUG, skge->netdev,
1871 "phy interrupt status 0x%x\n", isrc);
1873 if (isrc & PHY_B_IS_PSE)
1874 pr_err("%s: uncorrectable pair swap error\n",
1875 hw->dev[port]->name);
1877 /* Workaround BCom Errata:
1878 * enable and disable loopback mode if "NO HCD" occurs.
1880 if (isrc & PHY_B_IS_NO_HDCL) {
1881 u16 ctrl = xm_phy_read(hw, port, PHY_BCOM_CTRL);
1882 xm_phy_write(hw, port, PHY_BCOM_CTRL,
1883 ctrl | PHY_CT_LOOP);
1884 xm_phy_write(hw, port, PHY_BCOM_CTRL,
1885 ctrl & ~PHY_CT_LOOP);
1888 if (isrc & (PHY_B_IS_AN_PR | PHY_B_IS_LST_CHANGE))
1889 bcom_check_link(hw, port);
1893 static int gm_phy_write(struct skge_hw *hw, int port, u16 reg, u16 val)
1897 gma_write16(hw, port, GM_SMI_DATA, val);
1898 gma_write16(hw, port, GM_SMI_CTRL,
1899 GM_SMI_CT_PHY_AD(hw->phy_addr) | GM_SMI_CT_REG_AD(reg));
1900 for (i = 0; i < PHY_RETRIES; i++) {
1903 if (!(gma_read16(hw, port, GM_SMI_CTRL) & GM_SMI_CT_BUSY))
1907 pr_warn("%s: phy write timeout\n", hw->dev[port]->name);
1911 static int __gm_phy_read(struct skge_hw *hw, int port, u16 reg, u16 *val)
1915 gma_write16(hw, port, GM_SMI_CTRL,
1916 GM_SMI_CT_PHY_AD(hw->phy_addr)
1917 | GM_SMI_CT_REG_AD(reg) | GM_SMI_CT_OP_RD);
1919 for (i = 0; i < PHY_RETRIES; i++) {
1921 if (gma_read16(hw, port, GM_SMI_CTRL) & GM_SMI_CT_RD_VAL)
1927 *val = gma_read16(hw, port, GM_SMI_DATA);
1931 static u16 gm_phy_read(struct skge_hw *hw, int port, u16 reg)
1934 if (__gm_phy_read(hw, port, reg, &v))
1935 pr_warn("%s: phy read timeout\n", hw->dev[port]->name);
1939 /* Marvell Phy Initialization */
1940 static void yukon_init(struct skge_hw *hw, int port)
1942 struct skge_port *skge = netdev_priv(hw->dev[port]);
1943 u16 ctrl, ct1000, adv;
1945 if (skge->autoneg == AUTONEG_ENABLE) {
1946 u16 ectrl = gm_phy_read(hw, port, PHY_MARV_EXT_CTRL);
1948 ectrl &= ~(PHY_M_EC_M_DSC_MSK | PHY_M_EC_S_DSC_MSK |
1949 PHY_M_EC_MAC_S_MSK);
1950 ectrl |= PHY_M_EC_MAC_S(MAC_TX_CLK_25_MHZ);
1952 ectrl |= PHY_M_EC_M_DSC(0) | PHY_M_EC_S_DSC(1);
1954 gm_phy_write(hw, port, PHY_MARV_EXT_CTRL, ectrl);
1957 ctrl = gm_phy_read(hw, port, PHY_MARV_CTRL);
1958 if (skge->autoneg == AUTONEG_DISABLE)
1959 ctrl &= ~PHY_CT_ANE;
1961 ctrl |= PHY_CT_RESET;
1962 gm_phy_write(hw, port, PHY_MARV_CTRL, ctrl);
1968 if (skge->autoneg == AUTONEG_ENABLE) {
1970 if (skge->advertising & ADVERTISED_1000baseT_Full)
1971 ct1000 |= PHY_M_1000C_AFD;
1972 if (skge->advertising & ADVERTISED_1000baseT_Half)
1973 ct1000 |= PHY_M_1000C_AHD;
1974 if (skge->advertising & ADVERTISED_100baseT_Full)
1975 adv |= PHY_M_AN_100_FD;
1976 if (skge->advertising & ADVERTISED_100baseT_Half)
1977 adv |= PHY_M_AN_100_HD;
1978 if (skge->advertising & ADVERTISED_10baseT_Full)
1979 adv |= PHY_M_AN_10_FD;
1980 if (skge->advertising & ADVERTISED_10baseT_Half)
1981 adv |= PHY_M_AN_10_HD;
1983 /* Set Flow-control capabilities */
1984 adv |= phy_pause_map[skge->flow_control];
1986 if (skge->advertising & ADVERTISED_1000baseT_Full)
1987 adv |= PHY_M_AN_1000X_AFD;
1988 if (skge->advertising & ADVERTISED_1000baseT_Half)
1989 adv |= PHY_M_AN_1000X_AHD;
1991 adv |= fiber_pause_map[skge->flow_control];
1994 /* Restart Auto-negotiation */
1995 ctrl |= PHY_CT_ANE | PHY_CT_RE_CFG;
1997 /* forced speed/duplex settings */
1998 ct1000 = PHY_M_1000C_MSE;
2000 if (skge->duplex == DUPLEX_FULL)
2001 ctrl |= PHY_CT_DUP_MD;
2003 switch (skge->speed) {
2005 ctrl |= PHY_CT_SP1000;
2008 ctrl |= PHY_CT_SP100;
2012 ctrl |= PHY_CT_RESET;
2015 gm_phy_write(hw, port, PHY_MARV_1000T_CTRL, ct1000);
2017 gm_phy_write(hw, port, PHY_MARV_AUNE_ADV, adv);
2018 gm_phy_write(hw, port, PHY_MARV_CTRL, ctrl);
2020 /* Enable phy interrupt on autonegotiation complete (or link up) */
2021 if (skge->autoneg == AUTONEG_ENABLE)
2022 gm_phy_write(hw, port, PHY_MARV_INT_MASK, PHY_M_IS_AN_MSK);
2024 gm_phy_write(hw, port, PHY_MARV_INT_MASK, PHY_M_IS_DEF_MSK);
2027 static void yukon_reset(struct skge_hw *hw, int port)
2029 gm_phy_write(hw, port, PHY_MARV_INT_MASK, 0);/* disable PHY IRQs */
2030 gma_write16(hw, port, GM_MC_ADDR_H1, 0); /* clear MC hash */
2031 gma_write16(hw, port, GM_MC_ADDR_H2, 0);
2032 gma_write16(hw, port, GM_MC_ADDR_H3, 0);
2033 gma_write16(hw, port, GM_MC_ADDR_H4, 0);
2035 gma_write16(hw, port, GM_RX_CTRL,
2036 gma_read16(hw, port, GM_RX_CTRL)
2037 | GM_RXCR_UCF_ENA | GM_RXCR_MCF_ENA);
2040 /* Apparently, early versions of Yukon-Lite had wrong chip_id? */
2041 static int is_yukon_lite_a0(struct skge_hw *hw)
2046 if (hw->chip_id != CHIP_ID_YUKON)
2049 reg = skge_read32(hw, B2_FAR);
2050 skge_write8(hw, B2_FAR + 3, 0xff);
2051 ret = (skge_read8(hw, B2_FAR + 3) != 0);
2052 skge_write32(hw, B2_FAR, reg);
2056 static void yukon_mac_init(struct skge_hw *hw, int port)
2058 struct skge_port *skge = netdev_priv(hw->dev[port]);
2061 const u8 *addr = hw->dev[port]->dev_addr;
2063 /* WA code for COMA mode -- set PHY reset */
2064 if (hw->chip_id == CHIP_ID_YUKON_LITE &&
2065 hw->chip_rev >= CHIP_REV_YU_LITE_A3) {
2066 reg = skge_read32(hw, B2_GP_IO);
2067 reg |= GP_DIR_9 | GP_IO_9;
2068 skge_write32(hw, B2_GP_IO, reg);
2072 skge_write32(hw, SK_REG(port, GPHY_CTRL), GPC_RST_SET);
2073 skge_write32(hw, SK_REG(port, GMAC_CTRL), GMC_RST_SET);
2075 /* WA code for COMA mode -- clear PHY reset */
2076 if (hw->chip_id == CHIP_ID_YUKON_LITE &&
2077 hw->chip_rev >= CHIP_REV_YU_LITE_A3) {
2078 reg = skge_read32(hw, B2_GP_IO);
2081 skge_write32(hw, B2_GP_IO, reg);
2084 /* Set hardware config mode */
2085 reg = GPC_INT_POL_HI | GPC_DIS_FC | GPC_DIS_SLEEP |
2086 GPC_ENA_XC | GPC_ANEG_ADV_ALL_M | GPC_ENA_PAUSE;
2087 reg |= hw->copper ? GPC_HWCFG_GMII_COP : GPC_HWCFG_GMII_FIB;
2089 /* Clear GMC reset */
2090 skge_write32(hw, SK_REG(port, GPHY_CTRL), reg | GPC_RST_SET);
2091 skge_write32(hw, SK_REG(port, GPHY_CTRL), reg | GPC_RST_CLR);
2092 skge_write32(hw, SK_REG(port, GMAC_CTRL), GMC_PAUSE_ON | GMC_RST_CLR);
2094 if (skge->autoneg == AUTONEG_DISABLE) {
2095 reg = GM_GPCR_AU_ALL_DIS;
2096 gma_write16(hw, port, GM_GP_CTRL,
2097 gma_read16(hw, port, GM_GP_CTRL) | reg);
2099 switch (skge->speed) {
2101 reg &= ~GM_GPCR_SPEED_100;
2102 reg |= GM_GPCR_SPEED_1000;
2105 reg &= ~GM_GPCR_SPEED_1000;
2106 reg |= GM_GPCR_SPEED_100;
2109 reg &= ~(GM_GPCR_SPEED_1000 | GM_GPCR_SPEED_100);
2113 if (skge->duplex == DUPLEX_FULL)
2114 reg |= GM_GPCR_DUP_FULL;
2116 reg = GM_GPCR_SPEED_1000 | GM_GPCR_SPEED_100 | GM_GPCR_DUP_FULL;
2118 switch (skge->flow_control) {
2119 case FLOW_MODE_NONE:
2120 skge_write32(hw, SK_REG(port, GMAC_CTRL), GMC_PAUSE_OFF);
2121 reg |= GM_GPCR_FC_TX_DIS | GM_GPCR_FC_RX_DIS | GM_GPCR_AU_FCT_DIS;
2123 case FLOW_MODE_LOC_SEND:
2124 /* disable Rx flow-control */
2125 reg |= GM_GPCR_FC_RX_DIS | GM_GPCR_AU_FCT_DIS;
2127 case FLOW_MODE_SYMMETRIC:
2128 case FLOW_MODE_SYM_OR_REM:
2129 /* enable Tx & Rx flow-control */
2133 gma_write16(hw, port, GM_GP_CTRL, reg);
2134 skge_read16(hw, SK_REG(port, GMAC_IRQ_SRC));
2136 yukon_init(hw, port);
2139 reg = gma_read16(hw, port, GM_PHY_ADDR);
2140 gma_write16(hw, port, GM_PHY_ADDR, reg | GM_PAR_MIB_CLR);
2142 for (i = 0; i < GM_MIB_CNT_SIZE; i++)
2143 gma_read16(hw, port, GM_MIB_CNT_BASE + 8*i);
2144 gma_write16(hw, port, GM_PHY_ADDR, reg);
2146 /* transmit control */
2147 gma_write16(hw, port, GM_TX_CTRL, TX_COL_THR(TX_COL_DEF));
2149 /* receive control reg: unicast + multicast + no FCS */
2150 gma_write16(hw, port, GM_RX_CTRL,
2151 GM_RXCR_UCF_ENA | GM_RXCR_CRC_DIS | GM_RXCR_MCF_ENA);
2153 /* transmit flow control */
2154 gma_write16(hw, port, GM_TX_FLOW_CTRL, 0xffff);
2156 /* transmit parameter */
2157 gma_write16(hw, port, GM_TX_PARAM,
2158 TX_JAM_LEN_VAL(TX_JAM_LEN_DEF) |
2159 TX_JAM_IPG_VAL(TX_JAM_IPG_DEF) |
2160 TX_IPG_JAM_DATA(TX_IPG_JAM_DEF));
2162 /* configure the Serial Mode Register */
2163 reg = DATA_BLIND_VAL(DATA_BLIND_DEF)
2165 | IPG_DATA_VAL(IPG_DATA_DEF);
2167 if (hw->dev[port]->mtu > ETH_DATA_LEN)
2168 reg |= GM_SMOD_JUMBO_ENA;
2170 gma_write16(hw, port, GM_SERIAL_MODE, reg);
2172 /* physical address: used for pause frames */
2173 gma_set_addr(hw, port, GM_SRC_ADDR_1L, addr);
2174 /* virtual address for data */
2175 gma_set_addr(hw, port, GM_SRC_ADDR_2L, addr);
2177 /* enable interrupt mask for counter overflows */
2178 gma_write16(hw, port, GM_TX_IRQ_MSK, 0);
2179 gma_write16(hw, port, GM_RX_IRQ_MSK, 0);
2180 gma_write16(hw, port, GM_TR_IRQ_MSK, 0);
2182 /* Initialize Mac Fifo */
2184 /* Configure Rx MAC FIFO */
2185 skge_write16(hw, SK_REG(port, RX_GMF_FL_MSK), RX_FF_FL_DEF_MSK);
2186 reg = GMF_OPER_ON | GMF_RX_F_FL_ON;
2188 /* disable Rx GMAC FIFO Flush for YUKON-Lite Rev. A0 only */
2189 if (is_yukon_lite_a0(hw))
2190 reg &= ~GMF_RX_F_FL_ON;
2192 skge_write8(hw, SK_REG(port, RX_GMF_CTRL_T), GMF_RST_CLR);
2193 skge_write16(hw, SK_REG(port, RX_GMF_CTRL_T), reg);
2195 * because Pause Packet Truncation in GMAC is not working
2196 * we have to increase the Flush Threshold to 64 bytes
2197 * in order to flush pause packets in Rx FIFO on Yukon-1
2199 skge_write16(hw, SK_REG(port, RX_GMF_FL_THR), RX_GMF_FL_THR_DEF+1);
2201 /* Configure Tx MAC FIFO */
2202 skge_write8(hw, SK_REG(port, TX_GMF_CTRL_T), GMF_RST_CLR);
2203 skge_write16(hw, SK_REG(port, TX_GMF_CTRL_T), GMF_OPER_ON);
2206 /* Go into power down mode */
2207 static void yukon_suspend(struct skge_hw *hw, int port)
2211 ctrl = gm_phy_read(hw, port, PHY_MARV_PHY_CTRL);
2212 ctrl |= PHY_M_PC_POL_R_DIS;
2213 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL, ctrl);
2215 ctrl = gm_phy_read(hw, port, PHY_MARV_CTRL);
2216 ctrl |= PHY_CT_RESET;
2217 gm_phy_write(hw, port, PHY_MARV_CTRL, ctrl);
2219 /* switch IEEE compatible power down mode on */
2220 ctrl = gm_phy_read(hw, port, PHY_MARV_CTRL);
2221 ctrl |= PHY_CT_PDOWN;
2222 gm_phy_write(hw, port, PHY_MARV_CTRL, ctrl);
2225 static void yukon_stop(struct skge_port *skge)
2227 struct skge_hw *hw = skge->hw;
2228 int port = skge->port;
2230 skge_write8(hw, SK_REG(port, GMAC_IRQ_MSK), 0);
2231 yukon_reset(hw, port);
2233 gma_write16(hw, port, GM_GP_CTRL,
2234 gma_read16(hw, port, GM_GP_CTRL)
2235 & ~(GM_GPCR_TX_ENA|GM_GPCR_RX_ENA));
2236 gma_read16(hw, port, GM_GP_CTRL);
2238 yukon_suspend(hw, port);
2240 /* set GPHY Control reset */
2241 skge_write8(hw, SK_REG(port, GPHY_CTRL), GPC_RST_SET);
2242 skge_write8(hw, SK_REG(port, GMAC_CTRL), GMC_RST_SET);
2245 static void yukon_get_stats(struct skge_port *skge, u64 *data)
2247 struct skge_hw *hw = skge->hw;
2248 int port = skge->port;
2251 data[0] = (u64) gma_read32(hw, port, GM_TXO_OK_HI) << 32
2252 | gma_read32(hw, port, GM_TXO_OK_LO);
2253 data[1] = (u64) gma_read32(hw, port, GM_RXO_OK_HI) << 32
2254 | gma_read32(hw, port, GM_RXO_OK_LO);
2256 for (i = 2; i < ARRAY_SIZE(skge_stats); i++)
2257 data[i] = gma_read32(hw, port,
2258 skge_stats[i].gma_offset);
2261 static void yukon_mac_intr(struct skge_hw *hw, int port)
2263 struct net_device *dev = hw->dev[port];
2264 struct skge_port *skge = netdev_priv(dev);
2265 u8 status = skge_read8(hw, SK_REG(port, GMAC_IRQ_SRC));
2267 netif_printk(skge, intr, KERN_DEBUG, skge->netdev,
2268 "mac interrupt status 0x%x\n", status);
2270 if (status & GM_IS_RX_FF_OR) {
2271 ++dev->stats.rx_fifo_errors;
2272 skge_write8(hw, SK_REG(port, RX_GMF_CTRL_T), GMF_CLI_RX_FO);
2275 if (status & GM_IS_TX_FF_UR) {
2276 ++dev->stats.tx_fifo_errors;
2277 skge_write8(hw, SK_REG(port, TX_GMF_CTRL_T), GMF_CLI_TX_FU);
2282 static u16 yukon_speed(const struct skge_hw *hw, u16 aux)
2284 switch (aux & PHY_M_PS_SPEED_MSK) {
2285 case PHY_M_PS_SPEED_1000:
2287 case PHY_M_PS_SPEED_100:
2294 static void yukon_link_up(struct skge_port *skge)
2296 struct skge_hw *hw = skge->hw;
2297 int port = skge->port;
2300 /* Enable Transmit FIFO Underrun */
2301 skge_write8(hw, SK_REG(port, GMAC_IRQ_MSK), GMAC_DEF_MSK);
2303 reg = gma_read16(hw, port, GM_GP_CTRL);
2304 if (skge->duplex == DUPLEX_FULL || skge->autoneg == AUTONEG_ENABLE)
2305 reg |= GM_GPCR_DUP_FULL;
2308 reg |= GM_GPCR_RX_ENA | GM_GPCR_TX_ENA;
2309 gma_write16(hw, port, GM_GP_CTRL, reg);
2311 gm_phy_write(hw, port, PHY_MARV_INT_MASK, PHY_M_IS_DEF_MSK);
2315 static void yukon_link_down(struct skge_port *skge)
2317 struct skge_hw *hw = skge->hw;
2318 int port = skge->port;
2321 ctrl = gma_read16(hw, port, GM_GP_CTRL);
2322 ctrl &= ~(GM_GPCR_RX_ENA | GM_GPCR_TX_ENA);
2323 gma_write16(hw, port, GM_GP_CTRL, ctrl);
2325 if (skge->flow_status == FLOW_STAT_REM_SEND) {
2326 ctrl = gm_phy_read(hw, port, PHY_MARV_AUNE_ADV);
2327 ctrl |= PHY_M_AN_ASP;
2328 /* restore Asymmetric Pause bit */
2329 gm_phy_write(hw, port, PHY_MARV_AUNE_ADV, ctrl);
2332 skge_link_down(skge);
2334 yukon_init(hw, port);
2337 static void yukon_phy_intr(struct skge_port *skge)
2339 struct skge_hw *hw = skge->hw;
2340 int port = skge->port;
2341 const char *reason = NULL;
2342 u16 istatus, phystat;
2344 istatus = gm_phy_read(hw, port, PHY_MARV_INT_STAT);
2345 phystat = gm_phy_read(hw, port, PHY_MARV_PHY_STAT);
2347 netif_printk(skge, intr, KERN_DEBUG, skge->netdev,
2348 "phy interrupt status 0x%x 0x%x\n", istatus, phystat);
2350 if (istatus & PHY_M_IS_AN_COMPL) {
2351 if (gm_phy_read(hw, port, PHY_MARV_AUNE_LP)
2353 reason = "remote fault";
2357 if (gm_phy_read(hw, port, PHY_MARV_1000T_STAT) & PHY_B_1000S_MSF) {
2358 reason = "master/slave fault";
2362 if (!(phystat & PHY_M_PS_SPDUP_RES)) {
2363 reason = "speed/duplex";
2367 skge->duplex = (phystat & PHY_M_PS_FULL_DUP)
2368 ? DUPLEX_FULL : DUPLEX_HALF;
2369 skge->speed = yukon_speed(hw, phystat);
2371 /* We are using IEEE 802.3z/D5.0 Table 37-4 */
2372 switch (phystat & PHY_M_PS_PAUSE_MSK) {
2373 case PHY_M_PS_PAUSE_MSK:
2374 skge->flow_status = FLOW_STAT_SYMMETRIC;
2376 case PHY_M_PS_RX_P_EN:
2377 skge->flow_status = FLOW_STAT_REM_SEND;
2379 case PHY_M_PS_TX_P_EN:
2380 skge->flow_status = FLOW_STAT_LOC_SEND;
2383 skge->flow_status = FLOW_STAT_NONE;
2386 if (skge->flow_status == FLOW_STAT_NONE ||
2387 (skge->speed < SPEED_1000 && skge->duplex == DUPLEX_HALF))
2388 skge_write8(hw, SK_REG(port, GMAC_CTRL), GMC_PAUSE_OFF);
2390 skge_write8(hw, SK_REG(port, GMAC_CTRL), GMC_PAUSE_ON);
2391 yukon_link_up(skge);
2395 if (istatus & PHY_M_IS_LSP_CHANGE)
2396 skge->speed = yukon_speed(hw, phystat);
2398 if (istatus & PHY_M_IS_DUP_CHANGE)
2399 skge->duplex = (phystat & PHY_M_PS_FULL_DUP) ? DUPLEX_FULL : DUPLEX_HALF;
2400 if (istatus & PHY_M_IS_LST_CHANGE) {
2401 if (phystat & PHY_M_PS_LINK_UP)
2402 yukon_link_up(skge);
2404 yukon_link_down(skge);
2408 pr_err("%s: autonegotiation failed (%s)\n", skge->netdev->name, reason);
2410 /* XXX restart autonegotiation? */
2413 static void skge_phy_reset(struct skge_port *skge)
2415 struct skge_hw *hw = skge->hw;
2416 int port = skge->port;
2417 struct net_device *dev = hw->dev[port];
2419 netif_stop_queue(skge->netdev);
2420 netif_carrier_off(skge->netdev);
2422 spin_lock_bh(&hw->phy_lock);
2423 if (is_genesis(hw)) {
2424 genesis_reset(hw, port);
2425 genesis_mac_init(hw, port);
2427 yukon_reset(hw, port);
2428 yukon_init(hw, port);
2430 spin_unlock_bh(&hw->phy_lock);
2432 skge_set_multicast(dev);
2435 /* Basic MII support */
2436 static int skge_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
2438 struct mii_ioctl_data *data = if_mii(ifr);
2439 struct skge_port *skge = netdev_priv(dev);
2440 struct skge_hw *hw = skge->hw;
2441 int err = -EOPNOTSUPP;
2443 if (!netif_running(dev))
2444 return -ENODEV; /* Phy still in reset */
2448 data->phy_id = hw->phy_addr;
2453 spin_lock_bh(&hw->phy_lock);
2456 err = __xm_phy_read(hw, skge->port, data->reg_num & 0x1f, &val);
2458 err = __gm_phy_read(hw, skge->port, data->reg_num & 0x1f, &val);
2459 spin_unlock_bh(&hw->phy_lock);
2460 data->val_out = val;
2465 spin_lock_bh(&hw->phy_lock);
2467 err = xm_phy_write(hw, skge->port, data->reg_num & 0x1f,
2470 err = gm_phy_write(hw, skge->port, data->reg_num & 0x1f,
2472 spin_unlock_bh(&hw->phy_lock);
2478 static void skge_ramset(struct skge_hw *hw, u16 q, u32 start, size_t len)
2484 end = start + len - 1;
2486 skge_write8(hw, RB_ADDR(q, RB_CTRL), RB_RST_CLR);
2487 skge_write32(hw, RB_ADDR(q, RB_START), start);
2488 skge_write32(hw, RB_ADDR(q, RB_WP), start);
2489 skge_write32(hw, RB_ADDR(q, RB_RP), start);
2490 skge_write32(hw, RB_ADDR(q, RB_END), end);
2492 if (q == Q_R1 || q == Q_R2) {
2493 /* Set thresholds on receive queue's */
2494 skge_write32(hw, RB_ADDR(q, RB_RX_UTPP),
2496 skge_write32(hw, RB_ADDR(q, RB_RX_LTPP),
2499 /* Enable store & forward on Tx queue's because
2500 * Tx FIFO is only 4K on Genesis and 1K on Yukon
2502 skge_write8(hw, RB_ADDR(q, RB_CTRL), RB_ENA_STFWD);
2505 skge_write8(hw, RB_ADDR(q, RB_CTRL), RB_ENA_OP_MD);
2508 /* Setup Bus Memory Interface */
2509 static void skge_qset(struct skge_port *skge, u16 q,
2510 const struct skge_element *e)
2512 struct skge_hw *hw = skge->hw;
2513 u32 watermark = 0x600;
2514 u64 base = skge->dma + (e->desc - skge->mem);
2516 /* optimization to reduce window on 32bit/33mhz */
2517 if ((skge_read16(hw, B0_CTST) & (CS_BUS_CLOCK | CS_BUS_SLOT_SZ)) == 0)
2520 skge_write32(hw, Q_ADDR(q, Q_CSR), CSR_CLR_RESET);
2521 skge_write32(hw, Q_ADDR(q, Q_F), watermark);
2522 skge_write32(hw, Q_ADDR(q, Q_DA_H), (u32)(base >> 32));
2523 skge_write32(hw, Q_ADDR(q, Q_DA_L), (u32)base);
2526 static int skge_up(struct net_device *dev)
2528 struct skge_port *skge = netdev_priv(dev);
2529 struct skge_hw *hw = skge->hw;
2530 int port = skge->port;
2531 u32 chunk, ram_addr;
2532 size_t rx_size, tx_size;
2535 if (!is_valid_ether_addr(dev->dev_addr))
2538 netif_info(skge, ifup, skge->netdev, "enabling interface\n");
2540 if (dev->mtu > RX_BUF_SIZE)
2541 skge->rx_buf_size = dev->mtu + ETH_HLEN;
2543 skge->rx_buf_size = RX_BUF_SIZE;
2546 rx_size = skge->rx_ring.count * sizeof(struct skge_rx_desc);
2547 tx_size = skge->tx_ring.count * sizeof(struct skge_tx_desc);
2548 skge->mem_size = tx_size + rx_size;
2549 skge->mem = pci_alloc_consistent(hw->pdev, skge->mem_size, &skge->dma);
2553 BUG_ON(skge->dma & 7);
2555 if (upper_32_bits(skge->dma) != upper_32_bits(skge->dma + skge->mem_size)) {
2556 dev_err(&hw->pdev->dev, "pci_alloc_consistent region crosses 4G boundary\n");
2561 memset(skge->mem, 0, skge->mem_size);
2563 err = skge_ring_alloc(&skge->rx_ring, skge->mem, skge->dma);
2567 err = skge_rx_fill(dev);
2571 err = skge_ring_alloc(&skge->tx_ring, skge->mem + rx_size,
2572 skge->dma + rx_size);
2576 if (hw->ports == 1) {
2577 err = request_irq(hw->pdev->irq, skge_intr, IRQF_SHARED,
2580 netdev_err(dev, "Unable to allocate interrupt %d error: %d\n",
2581 hw->pdev->irq, err);
2586 /* Initialize MAC */
2587 netif_carrier_off(dev);
2588 spin_lock_bh(&hw->phy_lock);
2590 genesis_mac_init(hw, port);
2592 yukon_mac_init(hw, port);
2593 spin_unlock_bh(&hw->phy_lock);
2595 /* Configure RAMbuffers - equally between ports and tx/rx */
2596 chunk = (hw->ram_size - hw->ram_offset) / (hw->ports * 2);
2597 ram_addr = hw->ram_offset + 2 * chunk * port;
2599 skge_ramset(hw, rxqaddr[port], ram_addr, chunk);
2600 skge_qset(skge, rxqaddr[port], skge->rx_ring.to_clean);
2602 BUG_ON(skge->tx_ring.to_use != skge->tx_ring.to_clean);
2603 skge_ramset(hw, txqaddr[port], ram_addr+chunk, chunk);
2604 skge_qset(skge, txqaddr[port], skge->tx_ring.to_use);
2606 /* Start receiver BMU */
2608 skge_write8(hw, Q_ADDR(rxqaddr[port], Q_CSR), CSR_START | CSR_IRQ_CL_F);
2609 skge_led(skge, LED_MODE_ON);
2611 spin_lock_irq(&hw->hw_lock);
2612 hw->intr_mask |= portmask[port];
2613 skge_write32(hw, B0_IMSK, hw->intr_mask);
2614 skge_read32(hw, B0_IMSK);
2615 spin_unlock_irq(&hw->hw_lock);
2617 napi_enable(&skge->napi);
2619 skge_set_multicast(dev);
2624 kfree(skge->tx_ring.start);
2626 skge_rx_clean(skge);
2627 kfree(skge->rx_ring.start);
2629 pci_free_consistent(hw->pdev, skge->mem_size, skge->mem, skge->dma);
2636 static void skge_rx_stop(struct skge_hw *hw, int port)
2638 skge_write8(hw, Q_ADDR(rxqaddr[port], Q_CSR), CSR_STOP);
2639 skge_write32(hw, RB_ADDR(port ? Q_R2 : Q_R1, RB_CTRL),
2640 RB_RST_SET|RB_DIS_OP_MD);
2641 skge_write32(hw, Q_ADDR(rxqaddr[port], Q_CSR), CSR_SET_RESET);
2644 static int skge_down(struct net_device *dev)
2646 struct skge_port *skge = netdev_priv(dev);
2647 struct skge_hw *hw = skge->hw;
2648 int port = skge->port;
2653 netif_info(skge, ifdown, skge->netdev, "disabling interface\n");
2655 netif_tx_disable(dev);
2657 if (is_genesis(hw) && hw->phy_type == SK_PHY_XMAC)
2658 del_timer_sync(&skge->link_timer);
2660 napi_disable(&skge->napi);
2661 netif_carrier_off(dev);
2663 spin_lock_irq(&hw->hw_lock);
2664 hw->intr_mask &= ~portmask[port];
2665 skge_write32(hw, B0_IMSK, (hw->ports == 1) ? 0 : hw->intr_mask);
2666 skge_read32(hw, B0_IMSK);
2667 spin_unlock_irq(&hw->hw_lock);
2670 free_irq(hw->pdev->irq, hw);
2672 skge_write8(skge->hw, SK_REG(skge->port, LNK_LED_REG), LED_REG_OFF);
2678 /* Stop transmitter */
2679 skge_write8(hw, Q_ADDR(txqaddr[port], Q_CSR), CSR_STOP);
2680 skge_write32(hw, RB_ADDR(txqaddr[port], RB_CTRL),
2681 RB_RST_SET|RB_DIS_OP_MD);
2684 /* Disable Force Sync bit and Enable Alloc bit */
2685 skge_write8(hw, SK_REG(port, TXA_CTRL),
2686 TXA_DIS_FSYNC | TXA_DIS_ALLOC | TXA_STOP_RC);
2688 /* Stop Interval Timer and Limit Counter of Tx Arbiter */
2689 skge_write32(hw, SK_REG(port, TXA_ITI_INI), 0L);
2690 skge_write32(hw, SK_REG(port, TXA_LIM_INI), 0L);
2692 /* Reset PCI FIFO */
2693 skge_write32(hw, Q_ADDR(txqaddr[port], Q_CSR), CSR_SET_RESET);
2694 skge_write32(hw, RB_ADDR(txqaddr[port], RB_CTRL), RB_RST_SET);
2696 /* Reset the RAM Buffer async Tx queue */
2697 skge_write8(hw, RB_ADDR(port == 0 ? Q_XA1 : Q_XA2, RB_CTRL), RB_RST_SET);
2699 skge_rx_stop(hw, port);
2701 if (is_genesis(hw)) {
2702 skge_write8(hw, SK_REG(port, TX_MFF_CTRL2), MFF_RST_SET);
2703 skge_write8(hw, SK_REG(port, RX_MFF_CTRL2), MFF_RST_SET);
2705 skge_write8(hw, SK_REG(port, RX_GMF_CTRL_T), GMF_RST_SET);
2706 skge_write8(hw, SK_REG(port, TX_GMF_CTRL_T), GMF_RST_SET);
2709 skge_led(skge, LED_MODE_OFF);
2711 netif_tx_lock_bh(dev);
2713 netif_tx_unlock_bh(dev);
2715 skge_rx_clean(skge);
2717 kfree(skge->rx_ring.start);
2718 kfree(skge->tx_ring.start);
2719 pci_free_consistent(hw->pdev, skge->mem_size, skge->mem, skge->dma);
2724 static inline int skge_avail(const struct skge_ring *ring)
2727 return ((ring->to_clean > ring->to_use) ? 0 : ring->count)
2728 + (ring->to_clean - ring->to_use) - 1;
2731 static netdev_tx_t skge_xmit_frame(struct sk_buff *skb,
2732 struct net_device *dev)
2734 struct skge_port *skge = netdev_priv(dev);
2735 struct skge_hw *hw = skge->hw;
2736 struct skge_element *e;
2737 struct skge_tx_desc *td;
2742 if (skb_padto(skb, ETH_ZLEN))
2743 return NETDEV_TX_OK;
2745 if (unlikely(skge_avail(&skge->tx_ring) < skb_shinfo(skb)->nr_frags + 1))
2746 return NETDEV_TX_BUSY;
2748 e = skge->tx_ring.to_use;
2750 BUG_ON(td->control & BMU_OWN);
2752 len = skb_headlen(skb);
2753 map = pci_map_single(hw->pdev, skb->data, len, PCI_DMA_TODEVICE);
2754 if (pci_dma_mapping_error(hw->pdev, map))
2757 dma_unmap_addr_set(e, mapaddr, map);
2758 dma_unmap_len_set(e, maplen, len);
2760 td->dma_lo = lower_32_bits(map);
2761 td->dma_hi = upper_32_bits(map);
2763 if (skb->ip_summed == CHECKSUM_PARTIAL) {
2764 const int offset = skb_checksum_start_offset(skb);
2766 /* This seems backwards, but it is what the sk98lin
2767 * does. Looks like hardware is wrong?
2769 if (ipip_hdr(skb)->protocol == IPPROTO_UDP &&
2770 hw->chip_rev == 0 && hw->chip_id == CHIP_ID_YUKON)
2771 control = BMU_TCP_CHECK;
2773 control = BMU_UDP_CHECK;
2776 td->csum_start = offset;
2777 td->csum_write = offset + skb->csum_offset;
2779 control = BMU_CHECK;
2781 if (!skb_shinfo(skb)->nr_frags) /* single buffer i.e. no fragments */
2782 control |= BMU_EOF | BMU_IRQ_EOF;
2784 struct skge_tx_desc *tf = td;
2786 control |= BMU_STFWD;
2787 for (i = 0; i < skb_shinfo(skb)->nr_frags; i++) {
2788 const skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
2790 map = skb_frag_dma_map(&hw->pdev->dev, frag, 0,
2791 skb_frag_size(frag), DMA_TO_DEVICE);
2792 if (dma_mapping_error(&hw->pdev->dev, map))
2793 goto mapping_unwind;
2798 BUG_ON(tf->control & BMU_OWN);
2800 tf->dma_lo = lower_32_bits(map);
2801 tf->dma_hi = upper_32_bits(map);
2802 dma_unmap_addr_set(e, mapaddr, map);
2803 dma_unmap_len_set(e, maplen, skb_frag_size(frag));
2805 tf->control = BMU_OWN | BMU_SW | control | skb_frag_size(frag);
2807 tf->control |= BMU_EOF | BMU_IRQ_EOF;
2809 /* Make sure all the descriptors written */
2811 td->control = BMU_OWN | BMU_SW | BMU_STF | control | len;
2814 netdev_sent_queue(dev, skb->len);
2816 skge_write8(hw, Q_ADDR(txqaddr[skge->port], Q_CSR), CSR_START);
2818 netif_printk(skge, tx_queued, KERN_DEBUG, skge->netdev,
2819 "tx queued, slot %td, len %d\n",
2820 e - skge->tx_ring.start, skb->len);
2822 skge->tx_ring.to_use = e->next;
2825 if (skge_avail(&skge->tx_ring) <= TX_LOW_WATER) {
2826 netdev_dbg(dev, "transmit queue full\n");
2827 netif_stop_queue(dev);
2830 return NETDEV_TX_OK;
2833 e = skge->tx_ring.to_use;
2834 pci_unmap_single(hw->pdev,
2835 dma_unmap_addr(e, mapaddr),
2836 dma_unmap_len(e, maplen),
2840 pci_unmap_page(hw->pdev,
2841 dma_unmap_addr(e, mapaddr),
2842 dma_unmap_len(e, maplen),
2847 if (net_ratelimit())
2848 dev_warn(&hw->pdev->dev, "%s: tx mapping error\n", dev->name);
2849 dev_kfree_skb_any(skb);
2850 return NETDEV_TX_OK;
2854 /* Free resources associated with this reing element */
2855 static inline void skge_tx_unmap(struct pci_dev *pdev, struct skge_element *e,
2858 /* skb header vs. fragment */
2859 if (control & BMU_STF)
2860 pci_unmap_single(pdev, dma_unmap_addr(e, mapaddr),
2861 dma_unmap_len(e, maplen),
2864 pci_unmap_page(pdev, dma_unmap_addr(e, mapaddr),
2865 dma_unmap_len(e, maplen),
2869 /* Free all buffers in transmit ring */
2870 static void skge_tx_clean(struct net_device *dev)
2872 struct skge_port *skge = netdev_priv(dev);
2873 struct skge_element *e;
2875 for (e = skge->tx_ring.to_clean; e != skge->tx_ring.to_use; e = e->next) {
2876 struct skge_tx_desc *td = e->desc;
2878 skge_tx_unmap(skge->hw->pdev, e, td->control);
2880 if (td->control & BMU_EOF)
2881 dev_kfree_skb(e->skb);
2885 netdev_reset_queue(dev);
2886 skge->tx_ring.to_clean = e;
2889 static void skge_tx_timeout(struct net_device *dev)
2891 struct skge_port *skge = netdev_priv(dev);
2893 netif_printk(skge, timer, KERN_DEBUG, skge->netdev, "tx timeout\n");
2895 skge_write8(skge->hw, Q_ADDR(txqaddr[skge->port], Q_CSR), CSR_STOP);
2897 netif_wake_queue(dev);
2900 static int skge_change_mtu(struct net_device *dev, int new_mtu)
2904 if (!netif_running(dev)) {
2920 static const u8 pause_mc_addr[ETH_ALEN] = { 0x1, 0x80, 0xc2, 0x0, 0x0, 0x1 };
2922 static void genesis_add_filter(u8 filter[8], const u8 *addr)
2926 crc = ether_crc_le(ETH_ALEN, addr);
2928 filter[bit/8] |= 1 << (bit%8);
2931 static void genesis_set_multicast(struct net_device *dev)
2933 struct skge_port *skge = netdev_priv(dev);
2934 struct skge_hw *hw = skge->hw;
2935 int port = skge->port;
2936 struct netdev_hw_addr *ha;
2940 mode = xm_read32(hw, port, XM_MODE);
2941 mode |= XM_MD_ENA_HASH;
2942 if (dev->flags & IFF_PROMISC)
2943 mode |= XM_MD_ENA_PROM;
2945 mode &= ~XM_MD_ENA_PROM;
2947 if (dev->flags & IFF_ALLMULTI)
2948 memset(filter, 0xff, sizeof(filter));
2950 memset(filter, 0, sizeof(filter));
2952 if (skge->flow_status == FLOW_STAT_REM_SEND ||
2953 skge->flow_status == FLOW_STAT_SYMMETRIC)
2954 genesis_add_filter(filter, pause_mc_addr);
2956 netdev_for_each_mc_addr(ha, dev)
2957 genesis_add_filter(filter, ha->addr);
2960 xm_write32(hw, port, XM_MODE, mode);
2961 xm_outhash(hw, port, XM_HSM, filter);
2964 static void yukon_add_filter(u8 filter[8], const u8 *addr)
2966 u32 bit = ether_crc(ETH_ALEN, addr) & 0x3f;
2967 filter[bit/8] |= 1 << (bit%8);
2970 static void yukon_set_multicast(struct net_device *dev)
2972 struct skge_port *skge = netdev_priv(dev);
2973 struct skge_hw *hw = skge->hw;
2974 int port = skge->port;
2975 struct netdev_hw_addr *ha;
2976 int rx_pause = (skge->flow_status == FLOW_STAT_REM_SEND ||
2977 skge->flow_status == FLOW_STAT_SYMMETRIC);
2981 memset(filter, 0, sizeof(filter));
2983 reg = gma_read16(hw, port, GM_RX_CTRL);
2984 reg |= GM_RXCR_UCF_ENA;
2986 if (dev->flags & IFF_PROMISC) /* promiscuous */
2987 reg &= ~(GM_RXCR_UCF_ENA | GM_RXCR_MCF_ENA);
2988 else if (dev->flags & IFF_ALLMULTI) /* all multicast */
2989 memset(filter, 0xff, sizeof(filter));
2990 else if (netdev_mc_empty(dev) && !rx_pause)/* no multicast */
2991 reg &= ~GM_RXCR_MCF_ENA;
2993 reg |= GM_RXCR_MCF_ENA;
2996 yukon_add_filter(filter, pause_mc_addr);
2998 netdev_for_each_mc_addr(ha, dev)
2999 yukon_add_filter(filter, ha->addr);
3003 gma_write16(hw, port, GM_MC_ADDR_H1,
3004 (u16)filter[0] | ((u16)filter[1] << 8));
3005 gma_write16(hw, port, GM_MC_ADDR_H2,
3006 (u16)filter[2] | ((u16)filter[3] << 8));
3007 gma_write16(hw, port, GM_MC_ADDR_H3,
3008 (u16)filter[4] | ((u16)filter[5] << 8));
3009 gma_write16(hw, port, GM_MC_ADDR_H4,
3010 (u16)filter[6] | ((u16)filter[7] << 8));
3012 gma_write16(hw, port, GM_RX_CTRL, reg);
3015 static inline u16 phy_length(const struct skge_hw *hw, u32 status)
3018 return status >> XMR_FS_LEN_SHIFT;
3020 return status >> GMR_FS_LEN_SHIFT;
3023 static inline int bad_phy_status(const struct skge_hw *hw, u32 status)
3026 return (status & (XMR_FS_ERR | XMR_FS_2L_VLAN)) != 0;
3028 return (status & GMR_FS_ANY_ERR) ||
3029 (status & GMR_FS_RX_OK) == 0;
3032 static void skge_set_multicast(struct net_device *dev)
3034 struct skge_port *skge = netdev_priv(dev);
3036 if (is_genesis(skge->hw))
3037 genesis_set_multicast(dev);
3039 yukon_set_multicast(dev);
3044 /* Get receive buffer from descriptor.
3045 * Handles copy of small buffers and reallocation failures
3047 static struct sk_buff *skge_rx_get(struct net_device *dev,
3048 struct skge_element *e,
3049 u32 control, u32 status, u16 csum)
3051 struct skge_port *skge = netdev_priv(dev);
3052 struct sk_buff *skb;
3053 u16 len = control & BMU_BBC;
3055 netif_printk(skge, rx_status, KERN_DEBUG, skge->netdev,
3056 "rx slot %td status 0x%x len %d\n",
3057 e - skge->rx_ring.start, status, len);
3059 if (len > skge->rx_buf_size)
3062 if ((control & (BMU_EOF|BMU_STF)) != (BMU_STF|BMU_EOF))
3065 if (bad_phy_status(skge->hw, status))
3068 if (phy_length(skge->hw, status) != len)
3071 if (len < RX_COPY_THRESHOLD) {
3072 skb = netdev_alloc_skb_ip_align(dev, len);
3076 pci_dma_sync_single_for_cpu(skge->hw->pdev,
3077 dma_unmap_addr(e, mapaddr),
3078 dma_unmap_len(e, maplen),
3079 PCI_DMA_FROMDEVICE);
3080 skb_copy_from_linear_data(e->skb, skb->data, len);
3081 pci_dma_sync_single_for_device(skge->hw->pdev,
3082 dma_unmap_addr(e, mapaddr),
3083 dma_unmap_len(e, maplen),
3084 PCI_DMA_FROMDEVICE);
3085 skge_rx_reuse(e, skge->rx_buf_size);
3087 struct skge_element ee;
3088 struct sk_buff *nskb;
3090 nskb = netdev_alloc_skb_ip_align(dev, skge->rx_buf_size);
3097 prefetch(skb->data);
3099 if (skge_rx_setup(skge, e, nskb, skge->rx_buf_size) < 0) {
3100 dev_kfree_skb(nskb);
3104 pci_unmap_single(skge->hw->pdev,
3105 dma_unmap_addr(&ee, mapaddr),
3106 dma_unmap_len(&ee, maplen),
3107 PCI_DMA_FROMDEVICE);
3112 if (dev->features & NETIF_F_RXCSUM) {
3114 skb->ip_summed = CHECKSUM_COMPLETE;
3117 skb->protocol = eth_type_trans(skb, dev);
3122 netif_printk(skge, rx_err, KERN_DEBUG, skge->netdev,
3123 "rx err, slot %td control 0x%x status 0x%x\n",
3124 e - skge->rx_ring.start, control, status);
3126 if (is_genesis(skge->hw)) {
3127 if (status & (XMR_FS_RUNT|XMR_FS_LNG_ERR))
3128 dev->stats.rx_length_errors++;
3129 if (status & XMR_FS_FRA_ERR)
3130 dev->stats.rx_frame_errors++;
3131 if (status & XMR_FS_FCS_ERR)
3132 dev->stats.rx_crc_errors++;
3134 if (status & (GMR_FS_LONG_ERR|GMR_FS_UN_SIZE))
3135 dev->stats.rx_length_errors++;
3136 if (status & GMR_FS_FRAGMENT)
3137 dev->stats.rx_frame_errors++;
3138 if (status & GMR_FS_CRC_ERR)
3139 dev->stats.rx_crc_errors++;
3143 skge_rx_reuse(e, skge->rx_buf_size);
3147 /* Free all buffers in Tx ring which are no longer owned by device */
3148 static void skge_tx_done(struct net_device *dev)
3150 struct skge_port *skge = netdev_priv(dev);
3151 struct skge_ring *ring = &skge->tx_ring;
3152 struct skge_element *e;
3153 unsigned int bytes_compl = 0, pkts_compl = 0;
3155 skge_write8(skge->hw, Q_ADDR(txqaddr[skge->port], Q_CSR), CSR_IRQ_CL_F);
3157 for (e = ring->to_clean; e != ring->to_use; e = e->next) {
3158 u32 control = ((const struct skge_tx_desc *) e->desc)->control;
3160 if (control & BMU_OWN)
3163 skge_tx_unmap(skge->hw->pdev, e, control);
3165 if (control & BMU_EOF) {
3166 netif_printk(skge, tx_done, KERN_DEBUG, skge->netdev,
3167 "tx done slot %td\n",
3168 e - skge->tx_ring.start);
3171 bytes_compl += e->skb->len;
3173 dev_consume_skb_any(e->skb);
3176 netdev_completed_queue(dev, pkts_compl, bytes_compl);
3177 skge->tx_ring.to_clean = e;
3179 /* Can run lockless until we need to synchronize to restart queue. */
3182 if (unlikely(netif_queue_stopped(dev) &&
3183 skge_avail(&skge->tx_ring) > TX_LOW_WATER)) {
3185 if (unlikely(netif_queue_stopped(dev) &&
3186 skge_avail(&skge->tx_ring) > TX_LOW_WATER)) {
3187 netif_wake_queue(dev);
3190 netif_tx_unlock(dev);
3194 static int skge_poll(struct napi_struct *napi, int budget)
3196 struct skge_port *skge = container_of(napi, struct skge_port, napi);
3197 struct net_device *dev = skge->netdev;
3198 struct skge_hw *hw = skge->hw;
3199 struct skge_ring *ring = &skge->rx_ring;
3200 struct skge_element *e;
3205 skge_write8(hw, Q_ADDR(rxqaddr[skge->port], Q_CSR), CSR_IRQ_CL_F);
3207 for (e = ring->to_clean; prefetch(e->next), work_done < budget; e = e->next) {
3208 struct skge_rx_desc *rd = e->desc;
3209 struct sk_buff *skb;
3213 control = rd->control;
3214 if (control & BMU_OWN)
3217 skb = skge_rx_get(dev, e, control, rd->status, rd->csum2);
3219 napi_gro_receive(napi, skb);
3225 /* restart receiver */
3227 skge_write8(hw, Q_ADDR(rxqaddr[skge->port], Q_CSR), CSR_START);
3229 if (work_done < budget && napi_complete_done(napi, work_done)) {
3230 unsigned long flags;
3232 spin_lock_irqsave(&hw->hw_lock, flags);
3233 hw->intr_mask |= napimask[skge->port];
3234 skge_write32(hw, B0_IMSK, hw->intr_mask);
3235 skge_read32(hw, B0_IMSK);
3236 spin_unlock_irqrestore(&hw->hw_lock, flags);
3242 /* Parity errors seem to happen when Genesis is connected to a switch
3243 * with no other ports present. Heartbeat error??
3245 static void skge_mac_parity(struct skge_hw *hw, int port)
3247 struct net_device *dev = hw->dev[port];
3249 ++dev->stats.tx_heartbeat_errors;
3252 skge_write16(hw, SK_REG(port, TX_MFF_CTRL1),
3255 /* HW-Bug #8: cleared by GMF_CLI_TX_FC instead of GMF_CLI_TX_PE */
3256 skge_write8(hw, SK_REG(port, TX_GMF_CTRL_T),
3257 (hw->chip_id == CHIP_ID_YUKON && hw->chip_rev == 0)
3258 ? GMF_CLI_TX_FC : GMF_CLI_TX_PE);
3261 static void skge_mac_intr(struct skge_hw *hw, int port)
3264 genesis_mac_intr(hw, port);
3266 yukon_mac_intr(hw, port);
3269 /* Handle device specific framing and timeout interrupts */
3270 static void skge_error_irq(struct skge_hw *hw)
3272 struct pci_dev *pdev = hw->pdev;
3273 u32 hwstatus = skge_read32(hw, B0_HWE_ISRC);
3275 if (is_genesis(hw)) {
3276 /* clear xmac errors */
3277 if (hwstatus & (IS_NO_STAT_M1|IS_NO_TIST_M1))
3278 skge_write16(hw, RX_MFF_CTRL1, MFF_CLR_INSTAT);
3279 if (hwstatus & (IS_NO_STAT_M2|IS_NO_TIST_M2))
3280 skge_write16(hw, RX_MFF_CTRL2, MFF_CLR_INSTAT);
3282 /* Timestamp (unused) overflow */
3283 if (hwstatus & IS_IRQ_TIST_OV)
3284 skge_write8(hw, GMAC_TI_ST_CTRL, GMT_ST_CLR_IRQ);
3287 if (hwstatus & IS_RAM_RD_PAR) {
3288 dev_err(&pdev->dev, "Ram read data parity error\n");
3289 skge_write16(hw, B3_RI_CTRL, RI_CLR_RD_PERR);
3292 if (hwstatus & IS_RAM_WR_PAR) {
3293 dev_err(&pdev->dev, "Ram write data parity error\n");
3294 skge_write16(hw, B3_RI_CTRL, RI_CLR_WR_PERR);
3297 if (hwstatus & IS_M1_PAR_ERR)
3298 skge_mac_parity(hw, 0);
3300 if (hwstatus & IS_M2_PAR_ERR)
3301 skge_mac_parity(hw, 1);
3303 if (hwstatus & IS_R1_PAR_ERR) {
3304 dev_err(&pdev->dev, "%s: receive queue parity error\n",
3306 skge_write32(hw, B0_R1_CSR, CSR_IRQ_CL_P);
3309 if (hwstatus & IS_R2_PAR_ERR) {
3310 dev_err(&pdev->dev, "%s: receive queue parity error\n",
3312 skge_write32(hw, B0_R2_CSR, CSR_IRQ_CL_P);
3315 if (hwstatus & (IS_IRQ_MST_ERR|IS_IRQ_STAT)) {
3316 u16 pci_status, pci_cmd;
3318 pci_read_config_word(pdev, PCI_COMMAND, &pci_cmd);
3319 pci_read_config_word(pdev, PCI_STATUS, &pci_status);
3321 dev_err(&pdev->dev, "PCI error cmd=%#x status=%#x\n",
3322 pci_cmd, pci_status);
3324 /* Write the error bits back to clear them. */
3325 pci_status &= PCI_STATUS_ERROR_BITS;
3326 skge_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_ON);
3327 pci_write_config_word(pdev, PCI_COMMAND,
3328 pci_cmd | PCI_COMMAND_SERR | PCI_COMMAND_PARITY);
3329 pci_write_config_word(pdev, PCI_STATUS, pci_status);
3330 skge_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_OFF);
3332 /* if error still set then just ignore it */
3333 hwstatus = skge_read32(hw, B0_HWE_ISRC);
3334 if (hwstatus & IS_IRQ_STAT) {
3335 dev_warn(&hw->pdev->dev, "unable to clear error (so ignoring them)\n");
3336 hw->intr_mask &= ~IS_HW_ERR;
3342 * Interrupt from PHY are handled in tasklet (softirq)
3343 * because accessing phy registers requires spin wait which might
3344 * cause excess interrupt latency.
3346 static void skge_extirq(unsigned long arg)
3348 struct skge_hw *hw = (struct skge_hw *) arg;
3351 for (port = 0; port < hw->ports; port++) {
3352 struct net_device *dev = hw->dev[port];
3354 if (netif_running(dev)) {
3355 struct skge_port *skge = netdev_priv(dev);
3357 spin_lock(&hw->phy_lock);
3358 if (!is_genesis(hw))
3359 yukon_phy_intr(skge);
3360 else if (hw->phy_type == SK_PHY_BCOM)
3361 bcom_phy_intr(skge);
3362 spin_unlock(&hw->phy_lock);
3366 spin_lock_irq(&hw->hw_lock);
3367 hw->intr_mask |= IS_EXT_REG;
3368 skge_write32(hw, B0_IMSK, hw->intr_mask);
3369 skge_read32(hw, B0_IMSK);
3370 spin_unlock_irq(&hw->hw_lock);
3373 static irqreturn_t skge_intr(int irq, void *dev_id)
3375 struct skge_hw *hw = dev_id;
3379 spin_lock(&hw->hw_lock);
3380 /* Reading this register masks IRQ */
3381 status = skge_read32(hw, B0_SP_ISRC);
3382 if (status == 0 || status == ~0)
3386 status &= hw->intr_mask;
3387 if (status & IS_EXT_REG) {
3388 hw->intr_mask &= ~IS_EXT_REG;
3389 tasklet_schedule(&hw->phy_task);
3392 if (status & (IS_XA1_F|IS_R1_F)) {
3393 struct skge_port *skge = netdev_priv(hw->dev[0]);
3394 hw->intr_mask &= ~(IS_XA1_F|IS_R1_F);
3395 napi_schedule(&skge->napi);
3398 if (status & IS_PA_TO_TX1)
3399 skge_write16(hw, B3_PA_CTRL, PA_CLR_TO_TX1);
3401 if (status & IS_PA_TO_RX1) {
3402 ++hw->dev[0]->stats.rx_over_errors;
3403 skge_write16(hw, B3_PA_CTRL, PA_CLR_TO_RX1);
3407 if (status & IS_MAC1)
3408 skge_mac_intr(hw, 0);
3411 struct skge_port *skge = netdev_priv(hw->dev[1]);
3413 if (status & (IS_XA2_F|IS_R2_F)) {
3414 hw->intr_mask &= ~(IS_XA2_F|IS_R2_F);
3415 napi_schedule(&skge->napi);
3418 if (status & IS_PA_TO_RX2) {
3419 ++hw->dev[1]->stats.rx_over_errors;
3420 skge_write16(hw, B3_PA_CTRL, PA_CLR_TO_RX2);
3423 if (status & IS_PA_TO_TX2)
3424 skge_write16(hw, B3_PA_CTRL, PA_CLR_TO_TX2);
3426 if (status & IS_MAC2)
3427 skge_mac_intr(hw, 1);
3430 if (status & IS_HW_ERR)
3433 skge_write32(hw, B0_IMSK, hw->intr_mask);
3434 skge_read32(hw, B0_IMSK);
3435 spin_unlock(&hw->hw_lock);
3437 return IRQ_RETVAL(handled);
3440 #ifdef CONFIG_NET_POLL_CONTROLLER
3441 static void skge_netpoll(struct net_device *dev)
3443 struct skge_port *skge = netdev_priv(dev);
3445 disable_irq(dev->irq);
3446 skge_intr(dev->irq, skge->hw);
3447 enable_irq(dev->irq);
3451 static int skge_set_mac_address(struct net_device *dev, void *p)
3453 struct skge_port *skge = netdev_priv(dev);
3454 struct skge_hw *hw = skge->hw;
3455 unsigned port = skge->port;
3456 const struct sockaddr *addr = p;
3459 if (!is_valid_ether_addr(addr->sa_data))
3460 return -EADDRNOTAVAIL;
3462 memcpy(dev->dev_addr, addr->sa_data, ETH_ALEN);
3464 if (!netif_running(dev)) {
3465 memcpy_toio(hw->regs + B2_MAC_1 + port*8, dev->dev_addr, ETH_ALEN);
3466 memcpy_toio(hw->regs + B2_MAC_2 + port*8, dev->dev_addr, ETH_ALEN);
3469 spin_lock_bh(&hw->phy_lock);
3470 ctrl = gma_read16(hw, port, GM_GP_CTRL);
3471 gma_write16(hw, port, GM_GP_CTRL, ctrl & ~GM_GPCR_RX_ENA);
3473 memcpy_toio(hw->regs + B2_MAC_1 + port*8, dev->dev_addr, ETH_ALEN);
3474 memcpy_toio(hw->regs + B2_MAC_2 + port*8, dev->dev_addr, ETH_ALEN);
3477 xm_outaddr(hw, port, XM_SA, dev->dev_addr);
3479 gma_set_addr(hw, port, GM_SRC_ADDR_1L, dev->dev_addr);
3480 gma_set_addr(hw, port, GM_SRC_ADDR_2L, dev->dev_addr);
3483 gma_write16(hw, port, GM_GP_CTRL, ctrl);
3484 spin_unlock_bh(&hw->phy_lock);
3490 static const struct {
3494 { CHIP_ID_GENESIS, "Genesis" },
3495 { CHIP_ID_YUKON, "Yukon" },
3496 { CHIP_ID_YUKON_LITE, "Yukon-Lite"},
3497 { CHIP_ID_YUKON_LP, "Yukon-LP"},
3500 static const char *skge_board_name(const struct skge_hw *hw)
3503 static char buf[16];
3505 for (i = 0; i < ARRAY_SIZE(skge_chips); i++)
3506 if (skge_chips[i].id == hw->chip_id)
3507 return skge_chips[i].name;
3509 snprintf(buf, sizeof(buf), "chipid 0x%x", hw->chip_id);
3515 * Setup the board data structure, but don't bring up
3518 static int skge_reset(struct skge_hw *hw)
3521 u16 ctst, pci_status;
3522 u8 t8, mac_cfg, pmd_type;
3525 ctst = skge_read16(hw, B0_CTST);
3528 skge_write8(hw, B0_CTST, CS_RST_SET);
3529 skge_write8(hw, B0_CTST, CS_RST_CLR);
3531 /* clear PCI errors, if any */
3532 skge_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_ON);
3533 skge_write8(hw, B2_TST_CTRL2, 0);
3535 pci_read_config_word(hw->pdev, PCI_STATUS, &pci_status);
3536 pci_write_config_word(hw->pdev, PCI_STATUS,
3537 pci_status | PCI_STATUS_ERROR_BITS);
3538 skge_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_OFF);
3539 skge_write8(hw, B0_CTST, CS_MRST_CLR);
3541 /* restore CLK_RUN bits (for Yukon-Lite) */
3542 skge_write16(hw, B0_CTST,
3543 ctst & (CS_CLK_RUN_HOT|CS_CLK_RUN_RST|CS_CLK_RUN_ENA));
3545 hw->chip_id = skge_read8(hw, B2_CHIP_ID);
3546 hw->phy_type = skge_read8(hw, B2_E_1) & 0xf;
3547 pmd_type = skge_read8(hw, B2_PMD_TYP);
3548 hw->copper = (pmd_type == 'T' || pmd_type == '1');
3550 switch (hw->chip_id) {
3551 case CHIP_ID_GENESIS:
3552 #ifdef CONFIG_SKGE_GENESIS
3553 switch (hw->phy_type) {
3555 hw->phy_addr = PHY_ADDR_XMAC;
3558 hw->phy_addr = PHY_ADDR_BCOM;
3561 dev_err(&hw->pdev->dev, "unsupported phy type 0x%x\n",
3567 dev_err(&hw->pdev->dev, "Genesis chip detected but not configured\n");
3572 case CHIP_ID_YUKON_LITE:
3573 case CHIP_ID_YUKON_LP:
3574 if (hw->phy_type < SK_PHY_MARV_COPPER && pmd_type != 'S')
3577 hw->phy_addr = PHY_ADDR_MARV;
3581 dev_err(&hw->pdev->dev, "unsupported chip type 0x%x\n",
3586 mac_cfg = skge_read8(hw, B2_MAC_CFG);
3587 hw->ports = (mac_cfg & CFG_SNG_MAC) ? 1 : 2;
3588 hw->chip_rev = (mac_cfg & CFG_CHIP_R_MSK) >> 4;
3590 /* read the adapters RAM size */
3591 t8 = skge_read8(hw, B2_E_0);
3592 if (is_genesis(hw)) {
3594 /* special case: 4 x 64k x 36, offset = 0x80000 */
3595 hw->ram_size = 0x100000;
3596 hw->ram_offset = 0x80000;
3598 hw->ram_size = t8 * 512;
3600 hw->ram_size = 0x20000;
3602 hw->ram_size = t8 * 4096;
3604 hw->intr_mask = IS_HW_ERR;
3606 /* Use PHY IRQ for all but fiber based Genesis board */
3607 if (!(is_genesis(hw) && hw->phy_type == SK_PHY_XMAC))
3608 hw->intr_mask |= IS_EXT_REG;
3613 /* switch power to VCC (WA for VAUX problem) */
3614 skge_write8(hw, B0_POWER_CTRL,
3615 PC_VAUX_ENA | PC_VCC_ENA | PC_VAUX_OFF | PC_VCC_ON);
3617 /* avoid boards with stuck Hardware error bits */
3618 if ((skge_read32(hw, B0_ISRC) & IS_HW_ERR) &&
3619 (skge_read32(hw, B0_HWE_ISRC) & IS_IRQ_SENSOR)) {
3620 dev_warn(&hw->pdev->dev, "stuck hardware sensor bit\n");
3621 hw->intr_mask &= ~IS_HW_ERR;
3624 /* Clear PHY COMA */
3625 skge_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_ON);
3626 pci_read_config_dword(hw->pdev, PCI_DEV_REG1, ®);
3627 reg &= ~PCI_PHY_COMA;
3628 pci_write_config_dword(hw->pdev, PCI_DEV_REG1, reg);
3629 skge_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_OFF);
3632 for (i = 0; i < hw->ports; i++) {
3633 skge_write16(hw, SK_REG(i, GMAC_LINK_CTRL), GMLC_RST_SET);
3634 skge_write16(hw, SK_REG(i, GMAC_LINK_CTRL), GMLC_RST_CLR);
3638 /* turn off hardware timer (unused) */
3639 skge_write8(hw, B2_TI_CTRL, TIM_STOP);
3640 skge_write8(hw, B2_TI_CTRL, TIM_CLR_IRQ);
3641 skge_write8(hw, B0_LED, LED_STAT_ON);
3643 /* enable the Tx Arbiters */
3644 for (i = 0; i < hw->ports; i++)
3645 skge_write8(hw, SK_REG(i, TXA_CTRL), TXA_ENA_ARB);
3647 /* Initialize ram interface */
3648 skge_write16(hw, B3_RI_CTRL, RI_RST_CLR);
3650 skge_write8(hw, B3_RI_WTO_R1, SK_RI_TO_53);
3651 skge_write8(hw, B3_RI_WTO_XA1, SK_RI_TO_53);
3652 skge_write8(hw, B3_RI_WTO_XS1, SK_RI_TO_53);
3653 skge_write8(hw, B3_RI_RTO_R1, SK_RI_TO_53);
3654 skge_write8(hw, B3_RI_RTO_XA1, SK_RI_TO_53);
3655 skge_write8(hw, B3_RI_RTO_XS1, SK_RI_TO_53);
3656 skge_write8(hw, B3_RI_WTO_R2, SK_RI_TO_53);
3657 skge_write8(hw, B3_RI_WTO_XA2, SK_RI_TO_53);
3658 skge_write8(hw, B3_RI_WTO_XS2, SK_RI_TO_53);
3659 skge_write8(hw, B3_RI_RTO_R2, SK_RI_TO_53);
3660 skge_write8(hw, B3_RI_RTO_XA2, SK_RI_TO_53);
3661 skge_write8(hw, B3_RI_RTO_XS2, SK_RI_TO_53);
3663 skge_write32(hw, B0_HWE_IMSK, IS_ERR_MSK);
3665 /* Set interrupt moderation for Transmit only
3666 * Receive interrupts avoided by NAPI
3668 skge_write32(hw, B2_IRQM_MSK, IS_XA1_F|IS_XA2_F);
3669 skge_write32(hw, B2_IRQM_INI, skge_usecs2clk(hw, 100));
3670 skge_write32(hw, B2_IRQM_CTRL, TIM_START);
3672 /* Leave irq disabled until first port is brought up. */
3673 skge_write32(hw, B0_IMSK, 0);
3675 for (i = 0; i < hw->ports; i++) {
3677 genesis_reset(hw, i);
3686 #ifdef CONFIG_SKGE_DEBUG
3688 static struct dentry *skge_debug;
3690 static int skge_debug_show(struct seq_file *seq, void *v)
3692 struct net_device *dev = seq->private;
3693 const struct skge_port *skge = netdev_priv(dev);
3694 const struct skge_hw *hw = skge->hw;
3695 const struct skge_element *e;
3697 if (!netif_running(dev))
3700 seq_printf(seq, "IRQ src=%x mask=%x\n", skge_read32(hw, B0_ISRC),
3701 skge_read32(hw, B0_IMSK));
3703 seq_printf(seq, "Tx Ring: (%d)\n", skge_avail(&skge->tx_ring));
3704 for (e = skge->tx_ring.to_clean; e != skge->tx_ring.to_use; e = e->next) {
3705 const struct skge_tx_desc *t = e->desc;
3706 seq_printf(seq, "%#x dma=%#x%08x %#x csum=%#x/%x/%x\n",
3707 t->control, t->dma_hi, t->dma_lo, t->status,
3708 t->csum_offs, t->csum_write, t->csum_start);
3711 seq_puts(seq, "\nRx Ring:\n");
3712 for (e = skge->rx_ring.to_clean; ; e = e->next) {
3713 const struct skge_rx_desc *r = e->desc;
3715 if (r->control & BMU_OWN)
3718 seq_printf(seq, "%#x dma=%#x%08x %#x %#x csum=%#x/%x\n",
3719 r->control, r->dma_hi, r->dma_lo, r->status,
3720 r->timestamp, r->csum1, r->csum1_start);
3725 DEFINE_SHOW_ATTRIBUTE(skge_debug);
3728 * Use network device events to create/remove/rename
3729 * debugfs file entries
3731 static int skge_device_event(struct notifier_block *unused,
3732 unsigned long event, void *ptr)
3734 struct net_device *dev = netdev_notifier_info_to_dev(ptr);
3735 struct skge_port *skge;
3738 if (dev->netdev_ops->ndo_open != &skge_up || !skge_debug)
3741 skge = netdev_priv(dev);
3743 case NETDEV_CHANGENAME:
3744 if (skge->debugfs) {
3745 d = debugfs_rename(skge_debug, skge->debugfs,
3746 skge_debug, dev->name);
3750 netdev_info(dev, "rename failed\n");
3751 debugfs_remove(skge->debugfs);
3756 case NETDEV_GOING_DOWN:
3757 if (skge->debugfs) {
3758 debugfs_remove(skge->debugfs);
3759 skge->debugfs = NULL;
3764 d = debugfs_create_file(dev->name, 0444,
3767 if (!d || IS_ERR(d))
3768 netdev_info(dev, "debugfs create failed\n");
3778 static struct notifier_block skge_notifier = {
3779 .notifier_call = skge_device_event,
3783 static __init void skge_debug_init(void)
3787 ent = debugfs_create_dir("skge", NULL);
3788 if (!ent || IS_ERR(ent)) {
3789 pr_info("debugfs create directory failed\n");
3794 register_netdevice_notifier(&skge_notifier);
3797 static __exit void skge_debug_cleanup(void)
3800 unregister_netdevice_notifier(&skge_notifier);
3801 debugfs_remove(skge_debug);
3807 #define skge_debug_init()
3808 #define skge_debug_cleanup()
3811 static const struct net_device_ops skge_netdev_ops = {
3812 .ndo_open = skge_up,
3813 .ndo_stop = skge_down,
3814 .ndo_start_xmit = skge_xmit_frame,
3815 .ndo_do_ioctl = skge_ioctl,
3816 .ndo_get_stats = skge_get_stats,
3817 .ndo_tx_timeout = skge_tx_timeout,
3818 .ndo_change_mtu = skge_change_mtu,
3819 .ndo_validate_addr = eth_validate_addr,
3820 .ndo_set_rx_mode = skge_set_multicast,
3821 .ndo_set_mac_address = skge_set_mac_address,
3822 #ifdef CONFIG_NET_POLL_CONTROLLER
3823 .ndo_poll_controller = skge_netpoll,
3828 /* Initialize network device */
3829 static struct net_device *skge_devinit(struct skge_hw *hw, int port,
3832 struct skge_port *skge;
3833 struct net_device *dev = alloc_etherdev(sizeof(*skge));
3838 SET_NETDEV_DEV(dev, &hw->pdev->dev);
3839 dev->netdev_ops = &skge_netdev_ops;
3840 dev->ethtool_ops = &skge_ethtool_ops;
3841 dev->watchdog_timeo = TX_WATCHDOG;
3842 dev->irq = hw->pdev->irq;
3844 /* MTU range: 60 - 9000 */
3845 dev->min_mtu = ETH_ZLEN;
3846 dev->max_mtu = ETH_JUMBO_MTU;
3849 dev->features |= NETIF_F_HIGHDMA;
3851 skge = netdev_priv(dev);
3852 netif_napi_add(dev, &skge->napi, skge_poll, NAPI_WEIGHT);
3855 skge->msg_enable = netif_msg_init(debug, default_msg);
3857 skge->tx_ring.count = DEFAULT_TX_RING_SIZE;
3858 skge->rx_ring.count = DEFAULT_RX_RING_SIZE;
3860 /* Auto speed and flow control */
3861 skge->autoneg = AUTONEG_ENABLE;
3862 skge->flow_control = FLOW_MODE_SYM_OR_REM;
3865 skge->advertising = skge_supported_modes(hw);
3867 if (device_can_wakeup(&hw->pdev->dev)) {
3868 skge->wol = wol_supported(hw) & WAKE_MAGIC;
3869 device_set_wakeup_enable(&hw->pdev->dev, skge->wol);
3872 hw->dev[port] = dev;
3876 /* Only used for Genesis XMAC */
3878 timer_setup(&skge->link_timer, xm_link_timer, 0);
3880 dev->hw_features = NETIF_F_IP_CSUM | NETIF_F_SG |
3882 dev->features |= dev->hw_features;
3885 /* read the mac address */
3886 memcpy_fromio(dev->dev_addr, hw->regs + B2_MAC_1 + port*8, ETH_ALEN);
3891 static void skge_show_addr(struct net_device *dev)
3893 const struct skge_port *skge = netdev_priv(dev);
3895 netif_info(skge, probe, skge->netdev, "addr %pM\n", dev->dev_addr);
3898 static int only_32bit_dma;
3900 static int skge_probe(struct pci_dev *pdev, const struct pci_device_id *ent)
3902 struct net_device *dev, *dev1;
3904 int err, using_dac = 0;
3906 err = pci_enable_device(pdev);
3908 dev_err(&pdev->dev, "cannot enable PCI device\n");
3912 err = pci_request_regions(pdev, DRV_NAME);
3914 dev_err(&pdev->dev, "cannot obtain PCI resources\n");
3915 goto err_out_disable_pdev;
3918 pci_set_master(pdev);
3920 if (!only_32bit_dma && !pci_set_dma_mask(pdev, DMA_BIT_MASK(64))) {
3922 err = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(64));
3923 } else if (!(err = pci_set_dma_mask(pdev, DMA_BIT_MASK(32)))) {
3925 err = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(32));
3929 dev_err(&pdev->dev, "no usable DMA configuration\n");
3930 goto err_out_free_regions;
3934 /* byte swap descriptors in hardware */
3938 pci_read_config_dword(pdev, PCI_DEV_REG2, ®);
3939 reg |= PCI_REV_DESC;
3940 pci_write_config_dword(pdev, PCI_DEV_REG2, reg);
3945 /* space for skge@pci:0000:04:00.0 */
3946 hw = kzalloc(sizeof(*hw) + strlen(DRV_NAME "@pci:")
3947 + strlen(pci_name(pdev)) + 1, GFP_KERNEL);
3949 goto err_out_free_regions;
3951 sprintf(hw->irq_name, DRV_NAME "@pci:%s", pci_name(pdev));
3954 spin_lock_init(&hw->hw_lock);
3955 spin_lock_init(&hw->phy_lock);
3956 tasklet_init(&hw->phy_task, skge_extirq, (unsigned long) hw);
3958 hw->regs = ioremap_nocache(pci_resource_start(pdev, 0), 0x4000);
3960 dev_err(&pdev->dev, "cannot map device registers\n");
3961 goto err_out_free_hw;
3964 err = skge_reset(hw);
3966 goto err_out_iounmap;
3968 pr_info("%s addr 0x%llx irq %d chip %s rev %d\n",
3970 (unsigned long long)pci_resource_start(pdev, 0), pdev->irq,
3971 skge_board_name(hw), hw->chip_rev);
3973 dev = skge_devinit(hw, 0, using_dac);
3976 goto err_out_led_off;
3979 /* Some motherboards are broken and has zero in ROM. */
3980 if (!is_valid_ether_addr(dev->dev_addr))
3981 dev_warn(&pdev->dev, "bad (zero?) ethernet address in rom\n");
3983 err = register_netdev(dev);
3985 dev_err(&pdev->dev, "cannot register net device\n");
3986 goto err_out_free_netdev;
3989 skge_show_addr(dev);
3991 if (hw->ports > 1) {
3992 dev1 = skge_devinit(hw, 1, using_dac);
3995 goto err_out_unregister;
3998 err = register_netdev(dev1);
4000 dev_err(&pdev->dev, "cannot register second net device\n");
4001 goto err_out_free_dev1;
4004 err = request_irq(pdev->irq, skge_intr, IRQF_SHARED,
4007 dev_err(&pdev->dev, "cannot assign irq %d\n",
4009 goto err_out_unregister_dev1;
4012 skge_show_addr(dev1);
4014 pci_set_drvdata(pdev, hw);
4018 err_out_unregister_dev1:
4019 unregister_netdev(dev1);
4023 unregister_netdev(dev);
4024 err_out_free_netdev:
4027 skge_write16(hw, B0_LED, LED_STAT_OFF);
4032 err_out_free_regions:
4033 pci_release_regions(pdev);
4034 err_out_disable_pdev:
4035 pci_disable_device(pdev);
4040 static void skge_remove(struct pci_dev *pdev)
4042 struct skge_hw *hw = pci_get_drvdata(pdev);
4043 struct net_device *dev0, *dev1;
4050 unregister_netdev(dev1);
4052 unregister_netdev(dev0);
4054 tasklet_kill(&hw->phy_task);
4056 spin_lock_irq(&hw->hw_lock);
4059 if (hw->ports > 1) {
4060 skge_write32(hw, B0_IMSK, 0);
4061 skge_read32(hw, B0_IMSK);
4063 spin_unlock_irq(&hw->hw_lock);
4065 skge_write16(hw, B0_LED, LED_STAT_OFF);
4066 skge_write8(hw, B0_CTST, CS_RST_SET);
4069 free_irq(pdev->irq, hw);
4070 pci_release_regions(pdev);
4071 pci_disable_device(pdev);
4080 #ifdef CONFIG_PM_SLEEP
4081 static int skge_suspend(struct device *dev)
4083 struct pci_dev *pdev = to_pci_dev(dev);
4084 struct skge_hw *hw = pci_get_drvdata(pdev);
4090 for (i = 0; i < hw->ports; i++) {
4091 struct net_device *dev = hw->dev[i];
4092 struct skge_port *skge = netdev_priv(dev);
4094 if (netif_running(dev))
4098 skge_wol_init(skge);
4101 skge_write32(hw, B0_IMSK, 0);
4106 static int skge_resume(struct device *dev)
4108 struct pci_dev *pdev = to_pci_dev(dev);
4109 struct skge_hw *hw = pci_get_drvdata(pdev);
4115 err = skge_reset(hw);
4119 for (i = 0; i < hw->ports; i++) {
4120 struct net_device *dev = hw->dev[i];
4122 if (netif_running(dev)) {
4126 netdev_err(dev, "could not up: %d\n", err);
4136 static SIMPLE_DEV_PM_OPS(skge_pm_ops, skge_suspend, skge_resume);
4137 #define SKGE_PM_OPS (&skge_pm_ops)
4141 #define SKGE_PM_OPS NULL
4142 #endif /* CONFIG_PM_SLEEP */
4144 static void skge_shutdown(struct pci_dev *pdev)
4146 struct skge_hw *hw = pci_get_drvdata(pdev);
4152 for (i = 0; i < hw->ports; i++) {
4153 struct net_device *dev = hw->dev[i];
4154 struct skge_port *skge = netdev_priv(dev);
4157 skge_wol_init(skge);
4160 pci_wake_from_d3(pdev, device_may_wakeup(&pdev->dev));
4161 pci_set_power_state(pdev, PCI_D3hot);
4164 static struct pci_driver skge_driver = {
4166 .id_table = skge_id_table,
4167 .probe = skge_probe,
4168 .remove = skge_remove,
4169 .shutdown = skge_shutdown,
4170 .driver.pm = SKGE_PM_OPS,
4173 static const struct dmi_system_id skge_32bit_dma_boards[] = {
4175 .ident = "Gigabyte nForce boards",
4177 DMI_MATCH(DMI_BOARD_VENDOR, "Gigabyte Technology Co"),
4178 DMI_MATCH(DMI_BOARD_NAME, "nForce"),
4182 .ident = "ASUS P5NSLI",
4184 DMI_MATCH(DMI_BOARD_VENDOR, "ASUSTeK Computer INC."),
4185 DMI_MATCH(DMI_BOARD_NAME, "P5NSLI")
4189 .ident = "FUJITSU SIEMENS A8NE-FM",
4191 DMI_MATCH(DMI_BOARD_VENDOR, "ASUSTek Computer INC."),
4192 DMI_MATCH(DMI_BOARD_NAME, "A8NE-FM")
4198 static int __init skge_init_module(void)
4200 if (dmi_check_system(skge_32bit_dma_boards))
4203 return pci_register_driver(&skge_driver);
4206 static void __exit skge_cleanup_module(void)
4208 pci_unregister_driver(&skge_driver);
4209 skge_debug_cleanup();
4212 module_init(skge_init_module);
4213 module_exit(skge_cleanup_module);