1 // SPDX-License-Identifier: GPL-2.0
2 /* Marvell OcteonTx2 RVU Virtual Function ethernet driver */
4 #include <linux/etherdevice.h>
5 #include <linux/module.h>
8 #include "otx2_common.h"
12 #define DRV_NAME "rvu_nicvf"
13 #define DRV_STRING "Marvell RVU NIC Virtual Function Driver"
15 static const struct pci_device_id otx2_vf_id_table[] = {
16 { PCI_DEVICE(PCI_VENDOR_ID_CAVIUM, PCI_DEVID_OCTEONTX2_RVU_AFVF) },
17 { PCI_DEVICE(PCI_VENDOR_ID_CAVIUM, PCI_DEVID_OCTEONTX2_RVU_VF) },
21 MODULE_AUTHOR("Sunil Goutham <sgoutham@marvell.com>");
22 MODULE_DESCRIPTION(DRV_STRING);
23 MODULE_LICENSE("GPL v2");
24 MODULE_DEVICE_TABLE(pci, otx2_vf_id_table);
26 /* RVU VF Interrupt Vector Enumeration */
28 RVU_VF_INT_VEC_MBOX = 0x0,
31 static void otx2vf_process_vfaf_mbox_msg(struct otx2_nic *vf,
32 struct mbox_msghdr *msg)
34 if (msg->id >= MBOX_MSG_MAX) {
36 "Mbox msg with unknown ID %d\n", msg->id);
40 if (msg->sig != OTX2_MBOX_RSP_SIG) {
42 "Mbox msg with wrong signature %x, ID %d\n",
47 if (msg->rc == MBOX_MSG_INVALID) {
49 "PF/AF says the sent msg(s) %d were invalid\n",
56 vf->pcifunc = msg->pcifunc;
58 case MBOX_MSG_MSIX_OFFSET:
59 mbox_handler_msix_offset(vf, (struct msix_offset_rsp *)msg);
61 case MBOX_MSG_NPA_LF_ALLOC:
62 mbox_handler_npa_lf_alloc(vf, (struct npa_lf_alloc_rsp *)msg);
64 case MBOX_MSG_NIX_LF_ALLOC:
65 mbox_handler_nix_lf_alloc(vf, (struct nix_lf_alloc_rsp *)msg);
67 case MBOX_MSG_NIX_TXSCH_ALLOC:
68 mbox_handler_nix_txsch_alloc(vf,
69 (struct nix_txsch_alloc_rsp *)msg);
71 case MBOX_MSG_NIX_BP_ENABLE:
72 mbox_handler_nix_bp_enable(vf, (struct nix_bp_cfg_rsp *)msg);
77 "Mbox msg response has err %d, ID %d\n",
82 static void otx2vf_vfaf_mbox_handler(struct work_struct *work)
84 struct otx2_mbox_dev *mdev;
85 struct mbox_hdr *rsp_hdr;
86 struct mbox_msghdr *msg;
87 struct otx2_mbox *mbox;
91 af_mbox = container_of(work, struct mbox, mbox_wrk);
92 mbox = &af_mbox->mbox;
94 rsp_hdr = (struct mbox_hdr *)(mdev->mbase + mbox->rx_start);
95 if (af_mbox->num_msgs == 0)
97 offset = mbox->rx_start + ALIGN(sizeof(*rsp_hdr), MBOX_MSG_ALIGN);
99 for (id = 0; id < af_mbox->num_msgs; id++) {
100 msg = (struct mbox_msghdr *)(mdev->mbase + offset);
101 otx2vf_process_vfaf_mbox_msg(af_mbox->pfvf, msg);
102 offset = mbox->rx_start + msg->next_msgoff;
103 if (mdev->msgs_acked == (af_mbox->num_msgs - 1))
104 __otx2_mbox_reset(mbox, 0);
109 static int otx2vf_process_mbox_msg_up(struct otx2_nic *vf,
110 struct mbox_msghdr *req)
115 /* Check if valid, if not reply with a invalid msg */
116 if (req->sig != OTX2_MBOX_REQ_SIG) {
117 otx2_reply_invalid_msg(&vf->mbox.mbox_up, 0, 0, req->id);
122 case MBOX_MSG_CGX_LINK_EVENT:
123 rsp = (struct msg_rsp *)otx2_mbox_alloc_msg(
124 &vf->mbox.mbox_up, 0,
125 sizeof(struct msg_rsp));
129 rsp->hdr.id = MBOX_MSG_CGX_LINK_EVENT;
130 rsp->hdr.sig = OTX2_MBOX_RSP_SIG;
131 rsp->hdr.pcifunc = 0;
133 err = otx2_mbox_up_handler_cgx_link_event(
134 vf, (struct cgx_link_info_msg *)req, rsp);
137 otx2_reply_invalid_msg(&vf->mbox.mbox_up, 0, 0, req->id);
143 static void otx2vf_vfaf_mbox_up_handler(struct work_struct *work)
145 struct otx2_mbox_dev *mdev;
146 struct mbox_hdr *rsp_hdr;
147 struct mbox_msghdr *msg;
148 struct otx2_mbox *mbox;
149 struct mbox *vf_mbox;
153 vf_mbox = container_of(work, struct mbox, mbox_up_wrk);
155 mbox = &vf_mbox->mbox_up;
156 mdev = &mbox->dev[0];
158 rsp_hdr = (struct mbox_hdr *)(mdev->mbase + mbox->rx_start);
159 if (vf_mbox->up_num_msgs == 0)
162 offset = mbox->rx_start + ALIGN(sizeof(*rsp_hdr), MBOX_MSG_ALIGN);
164 for (id = 0; id < vf_mbox->up_num_msgs; id++) {
165 msg = (struct mbox_msghdr *)(mdev->mbase + offset);
166 otx2vf_process_mbox_msg_up(vf, msg);
167 offset = mbox->rx_start + msg->next_msgoff;
170 otx2_mbox_msg_send(mbox, 0);
173 static irqreturn_t otx2vf_vfaf_mbox_intr_handler(int irq, void *vf_irq)
175 struct otx2_nic *vf = (struct otx2_nic *)vf_irq;
176 struct otx2_mbox_dev *mdev;
177 struct otx2_mbox *mbox;
178 struct mbox_hdr *hdr;
181 otx2_write64(vf, RVU_VF_INT, BIT_ULL(0));
183 /* Read latest mbox data */
186 /* Check for PF => VF response messages */
187 mbox = &vf->mbox.mbox;
188 mdev = &mbox->dev[0];
189 otx2_sync_mbox_bbuf(mbox, 0);
191 trace_otx2_msg_interrupt(mbox->pdev, "PF to VF", BIT_ULL(0));
193 hdr = (struct mbox_hdr *)(mdev->mbase + mbox->rx_start);
195 vf->mbox.num_msgs = hdr->num_msgs;
197 memset(mbox->hwbase + mbox->rx_start, 0,
198 ALIGN(sizeof(struct mbox_hdr), sizeof(u64)));
199 queue_work(vf->mbox_wq, &vf->mbox.mbox_wrk);
201 /* Check for PF => VF notification messages */
202 mbox = &vf->mbox.mbox_up;
203 mdev = &mbox->dev[0];
204 otx2_sync_mbox_bbuf(mbox, 0);
206 hdr = (struct mbox_hdr *)(mdev->mbase + mbox->rx_start);
208 vf->mbox.up_num_msgs = hdr->num_msgs;
210 memset(mbox->hwbase + mbox->rx_start, 0,
211 ALIGN(sizeof(struct mbox_hdr), sizeof(u64)));
212 queue_work(vf->mbox_wq, &vf->mbox.mbox_up_wrk);
218 static void otx2vf_disable_mbox_intr(struct otx2_nic *vf)
220 int vector = pci_irq_vector(vf->pdev, RVU_VF_INT_VEC_MBOX);
222 /* Disable VF => PF mailbox IRQ */
223 otx2_write64(vf, RVU_VF_INT_ENA_W1C, BIT_ULL(0));
224 free_irq(vector, vf);
227 static int otx2vf_register_mbox_intr(struct otx2_nic *vf, bool probe_pf)
229 struct otx2_hw *hw = &vf->hw;
234 /* Register mailbox interrupt handler */
235 irq_name = &hw->irq_name[RVU_VF_INT_VEC_MBOX * NAME_SIZE];
236 snprintf(irq_name, NAME_SIZE, "RVUVFAF Mbox");
237 err = request_irq(pci_irq_vector(vf->pdev, RVU_VF_INT_VEC_MBOX),
238 otx2vf_vfaf_mbox_intr_handler, 0, irq_name, vf);
241 "RVUPF: IRQ registration failed for VFAF mbox irq\n");
245 /* Enable mailbox interrupt for msgs coming from PF.
246 * First clear to avoid spurious interrupts, if any.
248 otx2_write64(vf, RVU_VF_INT, BIT_ULL(0));
249 otx2_write64(vf, RVU_VF_INT_ENA_W1S, BIT_ULL(0));
254 /* Check mailbox communication with PF */
255 req = otx2_mbox_alloc_msg_ready(&vf->mbox);
257 otx2vf_disable_mbox_intr(vf);
261 err = otx2_sync_mbox_msg(&vf->mbox);
264 "AF not responding to mailbox, deferring probe\n");
265 otx2vf_disable_mbox_intr(vf);
266 return -EPROBE_DEFER;
271 static void otx2vf_vfaf_mbox_destroy(struct otx2_nic *vf)
273 struct mbox *mbox = &vf->mbox;
276 flush_workqueue(vf->mbox_wq);
277 destroy_workqueue(vf->mbox_wq);
281 if (mbox->mbox.hwbase && !test_bit(CN10K_MBOX, &vf->hw.cap_flag))
282 iounmap((void __iomem *)mbox->mbox.hwbase);
284 otx2_mbox_destroy(&mbox->mbox);
285 otx2_mbox_destroy(&mbox->mbox_up);
288 static int otx2vf_vfaf_mbox_init(struct otx2_nic *vf)
290 struct mbox *mbox = &vf->mbox;
291 void __iomem *hwbase;
295 vf->mbox_wq = alloc_workqueue("otx2_vfaf_mailbox",
296 WQ_UNBOUND | WQ_HIGHPRI |
301 if (test_bit(CN10K_MBOX, &vf->hw.cap_flag)) {
302 /* For cn10k platform, VF mailbox region is in its BAR2
305 hwbase = vf->reg_base + RVU_VF_MBOX_REGION;
307 /* Mailbox is a reserved memory (in RAM) region shared between
308 * admin function (i.e PF0) and this VF, shouldn't be mapped as
309 * device memory to allow unaligned accesses.
311 hwbase = ioremap_wc(pci_resource_start(vf->pdev,
313 pci_resource_len(vf->pdev,
316 dev_err(vf->dev, "Unable to map VFAF mailbox region\n");
322 err = otx2_mbox_init(&mbox->mbox, hwbase, vf->pdev, vf->reg_base,
327 err = otx2_mbox_init(&mbox->mbox_up, hwbase, vf->pdev, vf->reg_base,
328 MBOX_DIR_VFPF_UP, 1);
332 err = otx2_mbox_bbuf_init(mbox, vf->pdev);
336 INIT_WORK(&mbox->mbox_wrk, otx2vf_vfaf_mbox_handler);
337 INIT_WORK(&mbox->mbox_up_wrk, otx2vf_vfaf_mbox_up_handler);
338 mutex_init(&mbox->lock);
342 if (hwbase && !test_bit(CN10K_MBOX, &vf->hw.cap_flag))
344 destroy_workqueue(vf->mbox_wq);
348 static int otx2vf_open(struct net_device *netdev)
353 err = otx2_open(netdev);
357 /* LBKs do not receive link events so tell everyone we are up here */
358 vf = netdev_priv(netdev);
359 if (is_otx2_lbkvf(vf->pdev)) {
360 pr_info("%s NIC Link is UP\n", netdev->name);
361 netif_carrier_on(netdev);
362 netif_tx_start_all_queues(netdev);
368 static int otx2vf_stop(struct net_device *netdev)
370 return otx2_stop(netdev);
373 static netdev_tx_t otx2vf_xmit(struct sk_buff *skb, struct net_device *netdev)
375 struct otx2_nic *vf = netdev_priv(netdev);
376 int qidx = skb_get_queue_mapping(skb);
377 struct otx2_snd_queue *sq;
378 struct netdev_queue *txq;
380 sq = &vf->qset.sq[qidx];
381 txq = netdev_get_tx_queue(netdev, qidx);
383 if (!otx2_sq_append_skb(netdev, sq, skb, qidx)) {
384 netif_tx_stop_queue(txq);
386 /* Check again, incase SQBs got freed up */
388 if (((sq->num_sqbs - *sq->aura_fc_addr) * sq->sqe_per_sqb)
390 netif_tx_wake_queue(txq);
392 return NETDEV_TX_BUSY;
398 static void otx2vf_set_rx_mode(struct net_device *netdev)
400 struct otx2_nic *vf = netdev_priv(netdev);
402 queue_work(vf->otx2_wq, &vf->rx_mode_work);
405 static void otx2vf_do_set_rx_mode(struct work_struct *work)
407 struct otx2_nic *vf = container_of(work, struct otx2_nic, rx_mode_work);
408 struct net_device *netdev = vf->netdev;
409 unsigned int flags = netdev->flags;
410 struct nix_rx_mode *req;
412 mutex_lock(&vf->mbox.lock);
414 req = otx2_mbox_alloc_msg_nix_set_rx_mode(&vf->mbox);
416 mutex_unlock(&vf->mbox.lock);
420 req->mode = NIX_RX_MODE_UCAST;
422 if (flags & IFF_PROMISC)
423 req->mode |= NIX_RX_MODE_PROMISC;
424 if (flags & (IFF_ALLMULTI | IFF_MULTICAST))
425 req->mode |= NIX_RX_MODE_ALLMULTI;
427 req->mode |= NIX_RX_MODE_USE_MCE;
429 otx2_sync_mbox_msg(&vf->mbox);
431 mutex_unlock(&vf->mbox.lock);
434 static int otx2vf_change_mtu(struct net_device *netdev, int new_mtu)
436 bool if_up = netif_running(netdev);
442 netdev_info(netdev, "Changing MTU from %d to %d\n",
443 netdev->mtu, new_mtu);
444 netdev->mtu = new_mtu;
447 err = otx2vf_open(netdev);
452 static void otx2vf_reset_task(struct work_struct *work)
454 struct otx2_nic *vf = container_of(work, struct otx2_nic, reset_task);
458 if (netif_running(vf->netdev)) {
459 otx2vf_stop(vf->netdev);
461 otx2vf_open(vf->netdev);
467 static const struct net_device_ops otx2vf_netdev_ops = {
468 .ndo_open = otx2vf_open,
469 .ndo_stop = otx2vf_stop,
470 .ndo_start_xmit = otx2vf_xmit,
471 .ndo_set_rx_mode = otx2vf_set_rx_mode,
472 .ndo_set_mac_address = otx2_set_mac_address,
473 .ndo_change_mtu = otx2vf_change_mtu,
474 .ndo_get_stats64 = otx2_get_stats64,
475 .ndo_tx_timeout = otx2_tx_timeout,
478 static int otx2_wq_init(struct otx2_nic *vf)
480 vf->otx2_wq = create_singlethread_workqueue("otx2vf_wq");
484 INIT_WORK(&vf->rx_mode_work, otx2vf_do_set_rx_mode);
485 INIT_WORK(&vf->reset_task, otx2vf_reset_task);
489 static int otx2vf_realloc_msix_vectors(struct otx2_nic *vf)
491 struct otx2_hw *hw = &vf->hw;
494 num_vec = hw->nix_msixoff;
495 num_vec += NIX_LF_CINT_VEC_START + hw->max_queues;
497 otx2vf_disable_mbox_intr(vf);
498 pci_free_irq_vectors(hw->pdev);
499 err = pci_alloc_irq_vectors(hw->pdev, num_vec, num_vec, PCI_IRQ_MSIX);
501 dev_err(vf->dev, "%s: Failed to realloc %d IRQ vectors\n",
506 return otx2vf_register_mbox_intr(vf, false);
509 static int otx2vf_probe(struct pci_dev *pdev, const struct pci_device_id *id)
511 int num_vec = pci_msix_vec_count(pdev);
512 struct device *dev = &pdev->dev;
513 struct net_device *netdev;
518 err = pcim_enable_device(pdev);
520 dev_err(dev, "Failed to enable PCI device\n");
524 err = pci_request_regions(pdev, DRV_NAME);
526 dev_err(dev, "PCI request regions failed 0x%x\n", err);
530 err = dma_set_mask_and_coherent(dev, DMA_BIT_MASK(48));
532 dev_err(dev, "DMA mask config failed, abort\n");
533 goto err_release_regions;
536 pci_set_master(pdev);
538 qcount = num_online_cpus();
539 netdev = alloc_etherdev_mqs(sizeof(*vf), qcount, qcount);
542 goto err_release_regions;
545 pci_set_drvdata(pdev, netdev);
546 SET_NETDEV_DEV(netdev, &pdev->dev);
547 vf = netdev_priv(netdev);
551 vf->iommu_domain = iommu_get_domain_for_dev(dev);
553 vf->flags |= OTX2_FLAG_INTF_DOWN;
556 hw->rx_queues = qcount;
557 hw->tx_queues = qcount;
558 hw->max_queues = qcount;
560 hw->irq_name = devm_kmalloc_array(&hw->pdev->dev, num_vec, NAME_SIZE,
564 goto err_free_netdev;
567 hw->affinity_mask = devm_kcalloc(&hw->pdev->dev, num_vec,
568 sizeof(cpumask_var_t), GFP_KERNEL);
569 if (!hw->affinity_mask) {
571 goto err_free_netdev;
574 err = pci_alloc_irq_vectors(hw->pdev, num_vec, num_vec, PCI_IRQ_MSIX);
576 dev_err(dev, "%s: Failed to alloc %d IRQ vectors\n",
578 goto err_free_netdev;
581 vf->reg_base = pcim_iomap(pdev, PCI_CFG_REG_BAR_NUM, 0);
583 dev_err(dev, "Unable to map physical function CSRs, aborting\n");
585 goto err_free_irq_vectors;
588 otx2_setup_dev_hw_settings(vf);
589 /* Init VF <=> PF mailbox stuff */
590 err = otx2vf_vfaf_mbox_init(vf);
592 goto err_free_irq_vectors;
594 /* Register mailbox interrupt */
595 err = otx2vf_register_mbox_intr(vf, true);
597 goto err_mbox_destroy;
599 /* Request AF to attach NPA and LIX LFs to this AF */
600 err = otx2_attach_npa_nix(vf);
602 goto err_disable_mbox_intr;
604 err = otx2vf_realloc_msix_vectors(vf);
606 goto err_mbox_destroy;
608 err = otx2_set_real_num_queues(netdev, qcount, qcount);
610 goto err_detach_rsrc;
612 err = cn10k_lmtst_init(vf);
614 goto err_detach_rsrc;
616 /* Assign default mac address */
617 otx2_get_mac_from_af(netdev);
619 netdev->hw_features = NETIF_F_RXCSUM | NETIF_F_IP_CSUM |
620 NETIF_F_IPV6_CSUM | NETIF_F_RXHASH |
621 NETIF_F_SG | NETIF_F_TSO | NETIF_F_TSO6 |
623 netdev->features = netdev->hw_features;
624 /* Support TSO on tag interface */
625 netdev->vlan_features |= netdev->features;
626 netdev->hw_features |= NETIF_F_HW_VLAN_CTAG_TX |
627 NETIF_F_HW_VLAN_STAG_TX;
628 netdev->features |= netdev->hw_features;
630 netdev->gso_max_segs = OTX2_MAX_GSO_SEGS;
631 netdev->watchdog_timeo = OTX2_TX_TIMEOUT;
633 netdev->netdev_ops = &otx2vf_netdev_ops;
635 /* MTU range: 68 - 9190 */
636 netdev->min_mtu = OTX2_MIN_MTU;
637 netdev->max_mtu = otx2_get_max_mtu(vf);
639 /* To distinguish, for LBK VFs set netdev name explicitly */
640 if (is_otx2_lbkvf(vf->pdev)) {
643 n = (vf->pcifunc >> RVU_PFVF_FUNC_SHIFT) & RVU_PFVF_FUNC_MASK;
644 /* Need to subtract 1 to get proper VF number */
646 snprintf(netdev->name, sizeof(netdev->name), "lbk%d", n);
649 err = register_netdev(netdev);
651 dev_err(dev, "Failed to register netdevice\n");
652 goto err_detach_rsrc;
655 err = otx2_wq_init(vf);
657 goto err_unreg_netdev;
659 otx2vf_set_ethtool_ops(netdev);
661 /* Enable pause frames by default */
662 vf->flags |= OTX2_FLAG_RX_PAUSE_ENABLED;
663 vf->flags |= OTX2_FLAG_TX_PAUSE_ENABLED;
668 unregister_netdev(netdev);
670 if (test_bit(CN10K_LMTST, &vf->hw.cap_flag))
671 qmem_free(vf->dev, vf->dync_lmt);
672 otx2_detach_resources(&vf->mbox);
673 err_disable_mbox_intr:
674 otx2vf_disable_mbox_intr(vf);
676 otx2vf_vfaf_mbox_destroy(vf);
677 err_free_irq_vectors:
678 pci_free_irq_vectors(hw->pdev);
680 pci_set_drvdata(pdev, NULL);
683 pci_release_regions(pdev);
687 static void otx2vf_remove(struct pci_dev *pdev)
689 struct net_device *netdev = pci_get_drvdata(pdev);
695 vf = netdev_priv(netdev);
697 cancel_work_sync(&vf->reset_task);
698 unregister_netdev(netdev);
700 destroy_workqueue(vf->otx2_wq);
701 otx2vf_disable_mbox_intr(vf);
702 otx2_detach_resources(&vf->mbox);
703 if (test_bit(CN10K_LMTST, &vf->hw.cap_flag))
704 qmem_free(vf->dev, vf->dync_lmt);
705 otx2vf_vfaf_mbox_destroy(vf);
706 pci_free_irq_vectors(vf->pdev);
707 pci_set_drvdata(pdev, NULL);
710 pci_release_regions(pdev);
713 static struct pci_driver otx2vf_driver = {
715 .id_table = otx2_vf_id_table,
716 .probe = otx2vf_probe,
717 .remove = otx2vf_remove,
718 .shutdown = otx2vf_remove,
721 static int __init otx2vf_init_module(void)
723 pr_info("%s: %s\n", DRV_NAME, DRV_STRING);
725 return pci_register_driver(&otx2vf_driver);
728 static void __exit otx2vf_cleanup_module(void)
730 pci_unregister_driver(&otx2vf_driver);
733 module_init(otx2vf_init_module);
734 module_exit(otx2vf_cleanup_module);