1 /* SPDX-License-Identifier: GPL-2.0 */
2 /* Marvell OcteonTx2 RVU Ethernet driver
4 * Copyright (C) 2020 Marvell International Ltd.
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2 as
8 * published by the Free Software Foundation.
14 #include <linux/etherdevice.h>
15 #include <linux/iommu.h>
16 #include <linux/if_vlan.h>
18 #define LBK_CHAN_BASE 0x000
19 #define SDP_CHAN_BASE 0x700
20 #define CGX_CHAN_BASE 0x800
22 #define OTX2_DATA_ALIGN(X) ALIGN(X, OTX2_ALIGN)
23 #define OTX2_HEAD_ROOM OTX2_ALIGN
25 #define OTX2_ETH_HLEN (VLAN_ETH_HLEN + VLAN_HLEN)
26 #define OTX2_MIN_MTU 64
28 #define OTX2_MAX_GSO_SEGS 255
29 #define OTX2_MAX_FRAGS_IN_SQE 9
31 /* Rx buffer size should be in multiples of 128bytes */
32 #define RCV_FRAG_LEN1(x) \
33 ((OTX2_HEAD_ROOM + OTX2_DATA_ALIGN(x)) + \
34 OTX2_DATA_ALIGN(sizeof(struct skb_shared_info)))
36 /* Prefer 2048 byte buffers for better last level cache
37 * utilization or data distribution across regions.
39 #define RCV_FRAG_LEN(x) \
40 ((RCV_FRAG_LEN1(x) < 2048) ? 2048 : RCV_FRAG_LEN1(x))
42 #define DMA_BUFFER_LEN(x) \
43 ((x) - OTX2_HEAD_ROOM - \
44 OTX2_DATA_ALIGN(sizeof(struct skb_shared_info)))
46 /* IRQ triggered when NIX_LF_CINTX_CNT[ECOUNT]
47 * is equal to this value.
49 #define CQ_CQE_THRESH_DEFAULT 10
51 /* IRQ triggered when NIX_LF_CINTX_CNT[ECOUNT]
52 * is nonzero and this much time elapses after that.
54 #define CQ_TIMER_THRESH_DEFAULT 1 /* 1 usec */
55 #define CQ_TIMER_THRESH_MAX 25 /* 25 usec */
57 /* Min number of CQs (of the ones mapped to this CINT)
60 #define CQ_QCOUNT_DEFAULT 1
67 struct otx2_rcv_queue {
68 struct queue_stats stats;
74 u64 size[OTX2_MAX_FRAGS_IN_SQE];
75 u64 dma_addr[OTX2_MAX_FRAGS_IN_SQE];
78 struct otx2_snd_queue {
91 struct qmem *tso_hdrs;
93 struct qmem *timestamps;
94 struct queue_stats stats;
97 } ____cacheline_aligned_in_smp;
102 CQS_PER_CINT = 2, /* RQ + SQ */
105 struct otx2_cq_poll {
107 #define CINT_INVALID_CQ 255
109 u8 cq_ids[CQS_PER_CINT];
110 struct napi_struct napi;
115 struct qmem *fc_addr;
120 struct otx2_cq_queue {
123 u8 cint_idx; /* CQ interrupt id */
124 u8 refill_task_sched;
131 struct otx2_pool *rbpool;
132 } ____cacheline_aligned_in_smp;
136 u32 sqe_cnt; /* Keep these two at top */
137 #define OTX2_MAX_CQ_CNT 64
140 struct otx2_pool *pool;
141 struct otx2_cq_poll *napi;
142 struct otx2_cq_queue *cq;
143 struct otx2_snd_queue *sq;
144 struct otx2_rcv_queue *rq;
147 /* Translate IOVA to physical address */
148 static inline u64 otx2_iova_to_phys(void *iommu_domain, dma_addr_t dma_addr)
150 /* Translation is installed only when IOMMU is present */
151 if (likely(iommu_domain))
152 return iommu_iova_to_phys(iommu_domain, dma_addr);
156 int otx2_napi_handler(struct napi_struct *napi, int budget);
157 bool otx2_sq_append_skb(struct net_device *netdev, struct otx2_snd_queue *sq,
158 struct sk_buff *skb, u16 qidx);
159 void cn10k_sqe_flush(void *dev, struct otx2_snd_queue *sq,
161 void otx2_sqe_flush(void *dev, struct otx2_snd_queue *sq,
163 void otx2_refill_pool_ptrs(void *dev, struct otx2_cq_queue *cq);
164 void cn10k_refill_pool_ptrs(void *dev, struct otx2_cq_queue *cq);
165 #endif /* OTX2_TXRX_H */