1 // SPDX-License-Identifier: GPL-2.0
2 /* Marvell RVU Physical Function ethernet driver
4 * Copyright (C) 2020 Marvell.
8 #include <linux/module.h>
9 #include <linux/interrupt.h>
10 #include <linux/pci.h>
11 #include <linux/etherdevice.h>
13 #include <linux/if_vlan.h>
14 #include <linux/iommu.h>
16 #include <linux/bpf.h>
17 #include <linux/bpf_trace.h>
20 #include "otx2_common.h"
21 #include "otx2_txrx.h"
22 #include "otx2_struct.h"
25 #include <rvu_trace.h>
27 #define DRV_NAME "rvu_nicpf"
28 #define DRV_STRING "Marvell RVU NIC Physical Function Driver"
30 /* Supported devices */
31 static const struct pci_device_id otx2_pf_id_table[] = {
32 { PCI_DEVICE(PCI_VENDOR_ID_CAVIUM, PCI_DEVID_OCTEONTX2_RVU_PF) },
33 { 0, } /* end of table */
36 MODULE_AUTHOR("Sunil Goutham <sgoutham@marvell.com>");
37 MODULE_DESCRIPTION(DRV_STRING);
38 MODULE_LICENSE("GPL v2");
39 MODULE_DEVICE_TABLE(pci, otx2_pf_id_table);
41 static void otx2_vf_link_event_task(struct work_struct *work);
48 static int otx2_config_hw_tx_tstamp(struct otx2_nic *pfvf, bool enable);
49 static int otx2_config_hw_rx_tstamp(struct otx2_nic *pfvf, bool enable);
51 static int otx2_change_mtu(struct net_device *netdev, int new_mtu)
53 struct otx2_nic *pf = netdev_priv(netdev);
54 bool if_up = netif_running(netdev);
57 if (pf->xdp_prog && new_mtu > MAX_XDP_MTU) {
58 netdev_warn(netdev, "Jumbo frames not yet supported with XDP, current MTU %d.\n",
65 netdev_info(netdev, "Changing MTU from %d to %d\n",
66 netdev->mtu, new_mtu);
67 netdev->mtu = new_mtu;
70 err = otx2_open(netdev);
75 static void otx2_disable_flr_me_intr(struct otx2_nic *pf)
77 int irq, vfs = pf->total_vfs;
79 /* Disable VFs ME interrupts */
80 otx2_write64(pf, RVU_PF_VFME_INT_ENA_W1CX(0), INTR_MASK(vfs));
81 irq = pci_irq_vector(pf->pdev, RVU_PF_INT_VEC_VFME0);
84 /* Disable VFs FLR interrupts */
85 otx2_write64(pf, RVU_PF_VFFLR_INT_ENA_W1CX(0), INTR_MASK(vfs));
86 irq = pci_irq_vector(pf->pdev, RVU_PF_INT_VEC_VFFLR0);
92 otx2_write64(pf, RVU_PF_VFME_INT_ENA_W1CX(1), INTR_MASK(vfs - 64));
93 irq = pci_irq_vector(pf->pdev, RVU_PF_INT_VEC_VFME1);
96 otx2_write64(pf, RVU_PF_VFFLR_INT_ENA_W1CX(1), INTR_MASK(vfs - 64));
97 irq = pci_irq_vector(pf->pdev, RVU_PF_INT_VEC_VFFLR1);
101 static void otx2_flr_wq_destroy(struct otx2_nic *pf)
105 destroy_workqueue(pf->flr_wq);
107 devm_kfree(pf->dev, pf->flr_wrk);
110 static void otx2_flr_handler(struct work_struct *work)
112 struct flr_work *flrwork = container_of(work, struct flr_work, work);
113 struct otx2_nic *pf = flrwork->pf;
114 struct mbox *mbox = &pf->mbox;
118 vf = flrwork - pf->flr_wrk;
120 mutex_lock(&mbox->lock);
121 req = otx2_mbox_alloc_msg_vf_flr(mbox);
123 mutex_unlock(&mbox->lock);
126 req->hdr.pcifunc &= RVU_PFVF_FUNC_MASK;
127 req->hdr.pcifunc |= (vf + 1) & RVU_PFVF_FUNC_MASK;
129 if (!otx2_sync_mbox_msg(&pf->mbox)) {
134 /* clear transcation pending bit */
135 otx2_write64(pf, RVU_PF_VFTRPENDX(reg), BIT_ULL(vf));
136 otx2_write64(pf, RVU_PF_VFFLR_INT_ENA_W1SX(reg), BIT_ULL(vf));
139 mutex_unlock(&mbox->lock);
142 static irqreturn_t otx2_pf_flr_intr_handler(int irq, void *pf_irq)
144 struct otx2_nic *pf = (struct otx2_nic *)pf_irq;
145 int reg, dev, vf, start_vf, num_reg = 1;
148 if (pf->total_vfs > 64)
151 for (reg = 0; reg < num_reg; reg++) {
152 intr = otx2_read64(pf, RVU_PF_VFFLR_INTX(reg));
156 for (vf = 0; vf < 64; vf++) {
157 if (!(intr & BIT_ULL(vf)))
160 queue_work(pf->flr_wq, &pf->flr_wrk[dev].work);
161 /* Clear interrupt */
162 otx2_write64(pf, RVU_PF_VFFLR_INTX(reg), BIT_ULL(vf));
163 /* Disable the interrupt */
164 otx2_write64(pf, RVU_PF_VFFLR_INT_ENA_W1CX(reg),
171 static irqreturn_t otx2_pf_me_intr_handler(int irq, void *pf_irq)
173 struct otx2_nic *pf = (struct otx2_nic *)pf_irq;
174 int vf, reg, num_reg = 1;
177 if (pf->total_vfs > 64)
180 for (reg = 0; reg < num_reg; reg++) {
181 intr = otx2_read64(pf, RVU_PF_VFME_INTX(reg));
184 for (vf = 0; vf < 64; vf++) {
185 if (!(intr & BIT_ULL(vf)))
187 /* clear trpend bit */
188 otx2_write64(pf, RVU_PF_VFTRPENDX(reg), BIT_ULL(vf));
189 /* clear interrupt */
190 otx2_write64(pf, RVU_PF_VFME_INTX(reg), BIT_ULL(vf));
196 static int otx2_register_flr_me_intr(struct otx2_nic *pf, int numvfs)
198 struct otx2_hw *hw = &pf->hw;
202 /* Register ME interrupt handler*/
203 irq_name = &hw->irq_name[RVU_PF_INT_VEC_VFME0 * NAME_SIZE];
204 snprintf(irq_name, NAME_SIZE, "RVUPF%d_ME0", rvu_get_pf(pf->pcifunc));
205 ret = request_irq(pci_irq_vector(pf->pdev, RVU_PF_INT_VEC_VFME0),
206 otx2_pf_me_intr_handler, 0, irq_name, pf);
209 "RVUPF: IRQ registration failed for ME0\n");
212 /* Register FLR interrupt handler */
213 irq_name = &hw->irq_name[RVU_PF_INT_VEC_VFFLR0 * NAME_SIZE];
214 snprintf(irq_name, NAME_SIZE, "RVUPF%d_FLR0", rvu_get_pf(pf->pcifunc));
215 ret = request_irq(pci_irq_vector(pf->pdev, RVU_PF_INT_VEC_VFFLR0),
216 otx2_pf_flr_intr_handler, 0, irq_name, pf);
219 "RVUPF: IRQ registration failed for FLR0\n");
224 irq_name = &hw->irq_name[RVU_PF_INT_VEC_VFME1 * NAME_SIZE];
225 snprintf(irq_name, NAME_SIZE, "RVUPF%d_ME1",
226 rvu_get_pf(pf->pcifunc));
227 ret = request_irq(pci_irq_vector
228 (pf->pdev, RVU_PF_INT_VEC_VFME1),
229 otx2_pf_me_intr_handler, 0, irq_name, pf);
232 "RVUPF: IRQ registration failed for ME1\n");
234 irq_name = &hw->irq_name[RVU_PF_INT_VEC_VFFLR1 * NAME_SIZE];
235 snprintf(irq_name, NAME_SIZE, "RVUPF%d_FLR1",
236 rvu_get_pf(pf->pcifunc));
237 ret = request_irq(pci_irq_vector
238 (pf->pdev, RVU_PF_INT_VEC_VFFLR1),
239 otx2_pf_flr_intr_handler, 0, irq_name, pf);
242 "RVUPF: IRQ registration failed for FLR1\n");
247 /* Enable ME interrupt for all VFs*/
248 otx2_write64(pf, RVU_PF_VFME_INTX(0), INTR_MASK(numvfs));
249 otx2_write64(pf, RVU_PF_VFME_INT_ENA_W1SX(0), INTR_MASK(numvfs));
251 /* Enable FLR interrupt for all VFs*/
252 otx2_write64(pf, RVU_PF_VFFLR_INTX(0), INTR_MASK(numvfs));
253 otx2_write64(pf, RVU_PF_VFFLR_INT_ENA_W1SX(0), INTR_MASK(numvfs));
258 otx2_write64(pf, RVU_PF_VFME_INTX(1), INTR_MASK(numvfs));
259 otx2_write64(pf, RVU_PF_VFME_INT_ENA_W1SX(1),
262 otx2_write64(pf, RVU_PF_VFFLR_INTX(1), INTR_MASK(numvfs));
263 otx2_write64(pf, RVU_PF_VFFLR_INT_ENA_W1SX(1),
269 static int otx2_pf_flr_init(struct otx2_nic *pf, int num_vfs)
273 pf->flr_wq = alloc_workqueue("otx2_pf_flr_wq",
274 WQ_UNBOUND | WQ_HIGHPRI, 1);
278 pf->flr_wrk = devm_kcalloc(pf->dev, num_vfs,
279 sizeof(struct flr_work), GFP_KERNEL);
281 destroy_workqueue(pf->flr_wq);
285 for (vf = 0; vf < num_vfs; vf++) {
286 pf->flr_wrk[vf].pf = pf;
287 INIT_WORK(&pf->flr_wrk[vf].work, otx2_flr_handler);
293 static void otx2_queue_work(struct mbox *mw, struct workqueue_struct *mbox_wq,
294 int first, int mdevs, u64 intr, int type)
296 struct otx2_mbox_dev *mdev;
297 struct otx2_mbox *mbox;
298 struct mbox_hdr *hdr;
301 for (i = first; i < mdevs; i++) {
303 if (!(intr & BIT_ULL(i - first)))
307 mdev = &mbox->dev[i];
308 if (type == TYPE_PFAF)
309 otx2_sync_mbox_bbuf(mbox, i);
310 hdr = mdev->mbase + mbox->rx_start;
311 /* The hdr->num_msgs is set to zero immediately in the interrupt
312 * handler to ensure that it holds a correct value next time
313 * when the interrupt handler is called.
314 * pf->mbox.num_msgs holds the data for use in pfaf_mbox_handler
315 * pf>mbox.up_num_msgs holds the data for use in
316 * pfaf_mbox_up_handler.
319 mw[i].num_msgs = hdr->num_msgs;
321 if (type == TYPE_PFAF)
322 memset(mbox->hwbase + mbox->rx_start, 0,
323 ALIGN(sizeof(struct mbox_hdr),
326 queue_work(mbox_wq, &mw[i].mbox_wrk);
330 mdev = &mbox->dev[i];
331 if (type == TYPE_PFAF)
332 otx2_sync_mbox_bbuf(mbox, i);
333 hdr = mdev->mbase + mbox->rx_start;
335 mw[i].up_num_msgs = hdr->num_msgs;
337 if (type == TYPE_PFAF)
338 memset(mbox->hwbase + mbox->rx_start, 0,
339 ALIGN(sizeof(struct mbox_hdr),
342 queue_work(mbox_wq, &mw[i].mbox_up_wrk);
347 static void otx2_forward_msg_pfvf(struct otx2_mbox_dev *mdev,
348 struct otx2_mbox *pfvf_mbox, void *bbuf_base,
351 struct otx2_mbox_dev *src_mdev = mdev;
354 /* Msgs are already copied, trigger VF's mbox irq */
357 offset = pfvf_mbox->trigger | (devid << pfvf_mbox->tr_shift);
358 writeq(1, (void __iomem *)pfvf_mbox->reg_base + offset);
360 /* Restore VF's mbox bounce buffer region address */
361 src_mdev->mbase = bbuf_base;
364 static int otx2_forward_vf_mbox_msgs(struct otx2_nic *pf,
365 struct otx2_mbox *src_mbox,
366 int dir, int vf, int num_msgs)
368 struct otx2_mbox_dev *src_mdev, *dst_mdev;
369 struct mbox_hdr *mbox_hdr;
370 struct mbox_hdr *req_hdr;
371 struct mbox *dst_mbox;
374 if (dir == MBOX_DIR_PFAF) {
375 /* Set VF's mailbox memory as PF's bounce buffer memory, so
376 * that explicit copying of VF's msgs to PF=>AF mbox region
377 * and AF=>PF responses to VF's mbox region can be avoided.
379 src_mdev = &src_mbox->dev[vf];
380 mbox_hdr = src_mbox->hwbase +
381 src_mbox->rx_start + (vf * MBOX_SIZE);
383 dst_mbox = &pf->mbox;
384 dst_size = dst_mbox->mbox.tx_size -
385 ALIGN(sizeof(*mbox_hdr), MBOX_MSG_ALIGN);
386 /* Check if msgs fit into destination area and has valid size */
387 if (mbox_hdr->msg_size > dst_size || !mbox_hdr->msg_size)
390 dst_mdev = &dst_mbox->mbox.dev[0];
392 mutex_lock(&pf->mbox.lock);
393 dst_mdev->mbase = src_mdev->mbase;
394 dst_mdev->msg_size = mbox_hdr->msg_size;
395 dst_mdev->num_msgs = num_msgs;
396 err = otx2_sync_mbox_msg(dst_mbox);
399 "AF not responding to VF%d messages\n", vf);
400 /* restore PF mbase and exit */
401 dst_mdev->mbase = pf->mbox.bbuf_base;
402 mutex_unlock(&pf->mbox.lock);
405 /* At this point, all the VF messages sent to AF are acked
406 * with proper responses and responses are copied to VF
407 * mailbox hence raise interrupt to VF.
409 req_hdr = (struct mbox_hdr *)(dst_mdev->mbase +
410 dst_mbox->mbox.rx_start);
411 req_hdr->num_msgs = num_msgs;
413 otx2_forward_msg_pfvf(dst_mdev, &pf->mbox_pfvf[0].mbox,
414 pf->mbox.bbuf_base, vf);
415 mutex_unlock(&pf->mbox.lock);
416 } else if (dir == MBOX_DIR_PFVF_UP) {
417 src_mdev = &src_mbox->dev[0];
418 mbox_hdr = src_mbox->hwbase + src_mbox->rx_start;
419 req_hdr = (struct mbox_hdr *)(src_mdev->mbase +
421 req_hdr->num_msgs = num_msgs;
423 dst_mbox = &pf->mbox_pfvf[0];
424 dst_size = dst_mbox->mbox_up.tx_size -
425 ALIGN(sizeof(*mbox_hdr), MBOX_MSG_ALIGN);
426 /* Check if msgs fit into destination area */
427 if (mbox_hdr->msg_size > dst_size)
430 dst_mdev = &dst_mbox->mbox_up.dev[vf];
431 dst_mdev->mbase = src_mdev->mbase;
432 dst_mdev->msg_size = mbox_hdr->msg_size;
433 dst_mdev->num_msgs = mbox_hdr->num_msgs;
434 err = otx2_sync_mbox_up_msg(dst_mbox, vf);
437 "VF%d is not responding to mailbox\n", vf);
440 } else if (dir == MBOX_DIR_VFPF_UP) {
441 req_hdr = (struct mbox_hdr *)(src_mbox->dev[0].mbase +
443 req_hdr->num_msgs = num_msgs;
444 otx2_forward_msg_pfvf(&pf->mbox_pfvf->mbox_up.dev[vf],
446 pf->mbox_pfvf[vf].bbuf_base,
453 static void otx2_pfvf_mbox_handler(struct work_struct *work)
455 struct mbox_msghdr *msg = NULL;
456 int offset, vf_idx, id, err;
457 struct otx2_mbox_dev *mdev;
458 struct mbox_hdr *req_hdr;
459 struct otx2_mbox *mbox;
460 struct mbox *vf_mbox;
463 vf_mbox = container_of(work, struct mbox, mbox_wrk);
465 vf_idx = vf_mbox - pf->mbox_pfvf;
467 mbox = &pf->mbox_pfvf[0].mbox;
468 mdev = &mbox->dev[vf_idx];
469 req_hdr = (struct mbox_hdr *)(mdev->mbase + mbox->rx_start);
471 offset = ALIGN(sizeof(*req_hdr), MBOX_MSG_ALIGN);
473 for (id = 0; id < vf_mbox->num_msgs; id++) {
474 msg = (struct mbox_msghdr *)(mdev->mbase + mbox->rx_start +
477 if (msg->sig != OTX2_MBOX_REQ_SIG)
480 /* Set VF's number in each of the msg */
481 msg->pcifunc &= RVU_PFVF_FUNC_MASK;
482 msg->pcifunc |= (vf_idx + 1) & RVU_PFVF_FUNC_MASK;
483 offset = msg->next_msgoff;
485 err = otx2_forward_vf_mbox_msgs(pf, mbox, MBOX_DIR_PFAF, vf_idx,
492 otx2_reply_invalid_msg(mbox, vf_idx, 0, msg->id);
493 otx2_mbox_msg_send(mbox, vf_idx);
496 static void otx2_pfvf_mbox_up_handler(struct work_struct *work)
498 struct mbox *vf_mbox = container_of(work, struct mbox, mbox_up_wrk);
499 struct otx2_nic *pf = vf_mbox->pfvf;
500 struct otx2_mbox_dev *mdev;
501 int offset, id, vf_idx = 0;
502 struct mbox_hdr *rsp_hdr;
503 struct mbox_msghdr *msg;
504 struct otx2_mbox *mbox;
506 vf_idx = vf_mbox - pf->mbox_pfvf;
507 mbox = &pf->mbox_pfvf[0].mbox_up;
508 mdev = &mbox->dev[vf_idx];
510 rsp_hdr = (struct mbox_hdr *)(mdev->mbase + mbox->rx_start);
511 offset = mbox->rx_start + ALIGN(sizeof(*rsp_hdr), MBOX_MSG_ALIGN);
513 for (id = 0; id < vf_mbox->up_num_msgs; id++) {
514 msg = mdev->mbase + offset;
516 if (msg->id >= MBOX_MSG_MAX) {
518 "Mbox msg with unknown ID 0x%x\n", msg->id);
522 if (msg->sig != OTX2_MBOX_RSP_SIG) {
524 "Mbox msg with wrong signature %x, ID 0x%x\n",
530 case MBOX_MSG_CGX_LINK_EVENT:
535 "Mbox msg response has err %d, ID 0x%x\n",
541 offset = mbox->rx_start + msg->next_msgoff;
542 if (mdev->msgs_acked == (vf_mbox->up_num_msgs - 1))
543 __otx2_mbox_reset(mbox, 0);
548 static irqreturn_t otx2_pfvf_mbox_intr_handler(int irq, void *pf_irq)
550 struct otx2_nic *pf = (struct otx2_nic *)(pf_irq);
551 int vfs = pf->total_vfs;
555 mbox = pf->mbox_pfvf;
556 /* Handle VF interrupts */
558 intr = otx2_read64(pf, RVU_PF_VFPF_MBOX_INTX(1));
559 otx2_write64(pf, RVU_PF_VFPF_MBOX_INTX(1), intr);
560 otx2_queue_work(mbox, pf->mbox_pfvf_wq, 64, vfs, intr,
565 intr = otx2_read64(pf, RVU_PF_VFPF_MBOX_INTX(0));
566 otx2_write64(pf, RVU_PF_VFPF_MBOX_INTX(0), intr);
568 otx2_queue_work(mbox, pf->mbox_pfvf_wq, 0, vfs, intr, TYPE_PFVF);
570 trace_otx2_msg_interrupt(mbox->mbox.pdev, "VF(s) to PF", intr);
575 static int otx2_pfvf_mbox_init(struct otx2_nic *pf, int numvfs)
577 void __iomem *hwbase;
585 pf->mbox_pfvf = devm_kcalloc(&pf->pdev->dev, numvfs,
586 sizeof(struct mbox), GFP_KERNEL);
590 pf->mbox_pfvf_wq = alloc_workqueue("otx2_pfvf_mailbox",
591 WQ_UNBOUND | WQ_HIGHPRI |
593 if (!pf->mbox_pfvf_wq)
596 /* On CN10K platform, PF <-> VF mailbox region follows after
597 * PF <-> AF mailbox region.
599 if (test_bit(CN10K_MBOX, &pf->hw.cap_flag))
600 base = pci_resource_start(pf->pdev, PCI_MBOX_BAR_NUM) +
603 base = readq((void __iomem *)((u64)pf->reg_base +
604 RVU_PF_VF_BAR4_ADDR));
606 hwbase = ioremap_wc(base, MBOX_SIZE * pf->total_vfs);
612 mbox = &pf->mbox_pfvf[0];
613 err = otx2_mbox_init(&mbox->mbox, hwbase, pf->pdev, pf->reg_base,
614 MBOX_DIR_PFVF, numvfs);
618 err = otx2_mbox_init(&mbox->mbox_up, hwbase, pf->pdev, pf->reg_base,
619 MBOX_DIR_PFVF_UP, numvfs);
623 for (vf = 0; vf < numvfs; vf++) {
625 INIT_WORK(&mbox->mbox_wrk, otx2_pfvf_mbox_handler);
626 INIT_WORK(&mbox->mbox_up_wrk, otx2_pfvf_mbox_up_handler);
636 destroy_workqueue(pf->mbox_pfvf_wq);
640 static void otx2_pfvf_mbox_destroy(struct otx2_nic *pf)
642 struct mbox *mbox = &pf->mbox_pfvf[0];
647 if (pf->mbox_pfvf_wq) {
648 destroy_workqueue(pf->mbox_pfvf_wq);
649 pf->mbox_pfvf_wq = NULL;
652 if (mbox->mbox.hwbase)
653 iounmap(mbox->mbox.hwbase);
655 otx2_mbox_destroy(&mbox->mbox);
658 static void otx2_enable_pfvf_mbox_intr(struct otx2_nic *pf, int numvfs)
660 /* Clear PF <=> VF mailbox IRQ */
661 otx2_write64(pf, RVU_PF_VFPF_MBOX_INTX(0), ~0ull);
662 otx2_write64(pf, RVU_PF_VFPF_MBOX_INTX(1), ~0ull);
664 /* Enable PF <=> VF mailbox IRQ */
665 otx2_write64(pf, RVU_PF_VFPF_MBOX_INT_ENA_W1SX(0), INTR_MASK(numvfs));
668 otx2_write64(pf, RVU_PF_VFPF_MBOX_INT_ENA_W1SX(1),
673 static void otx2_disable_pfvf_mbox_intr(struct otx2_nic *pf, int numvfs)
677 /* Disable PF <=> VF mailbox IRQ */
678 otx2_write64(pf, RVU_PF_VFPF_MBOX_INT_ENA_W1CX(0), ~0ull);
679 otx2_write64(pf, RVU_PF_VFPF_MBOX_INT_ENA_W1CX(1), ~0ull);
681 otx2_write64(pf, RVU_PF_VFPF_MBOX_INTX(0), ~0ull);
682 vector = pci_irq_vector(pf->pdev, RVU_PF_INT_VEC_VFPF_MBOX0);
683 free_irq(vector, pf);
686 otx2_write64(pf, RVU_PF_VFPF_MBOX_INTX(1), ~0ull);
687 vector = pci_irq_vector(pf->pdev, RVU_PF_INT_VEC_VFPF_MBOX1);
688 free_irq(vector, pf);
692 static int otx2_register_pfvf_mbox_intr(struct otx2_nic *pf, int numvfs)
694 struct otx2_hw *hw = &pf->hw;
698 /* Register MBOX0 interrupt handler */
699 irq_name = &hw->irq_name[RVU_PF_INT_VEC_VFPF_MBOX0 * NAME_SIZE];
701 snprintf(irq_name, NAME_SIZE,
702 "RVUPF%d_VF Mbox0", rvu_get_pf(pf->pcifunc));
704 snprintf(irq_name, NAME_SIZE, "RVUPF_VF Mbox0");
705 err = request_irq(pci_irq_vector(pf->pdev, RVU_PF_INT_VEC_VFPF_MBOX0),
706 otx2_pfvf_mbox_intr_handler, 0, irq_name, pf);
709 "RVUPF: IRQ registration failed for PFVF mbox0 irq\n");
714 /* Register MBOX1 interrupt handler */
715 irq_name = &hw->irq_name[RVU_PF_INT_VEC_VFPF_MBOX1 * NAME_SIZE];
717 snprintf(irq_name, NAME_SIZE,
718 "RVUPF%d_VF Mbox1", rvu_get_pf(pf->pcifunc));
720 snprintf(irq_name, NAME_SIZE, "RVUPF_VF Mbox1");
721 err = request_irq(pci_irq_vector(pf->pdev,
722 RVU_PF_INT_VEC_VFPF_MBOX1),
723 otx2_pfvf_mbox_intr_handler,
727 "RVUPF: IRQ registration failed for PFVF mbox1 irq\n");
732 otx2_enable_pfvf_mbox_intr(pf, numvfs);
737 static void otx2_process_pfaf_mbox_msg(struct otx2_nic *pf,
738 struct mbox_msghdr *msg)
742 if (msg->id >= MBOX_MSG_MAX) {
744 "Mbox msg with unknown ID 0x%x\n", msg->id);
748 if (msg->sig != OTX2_MBOX_RSP_SIG) {
750 "Mbox msg with wrong signature %x, ID 0x%x\n",
755 /* message response heading VF */
756 devid = msg->pcifunc & RVU_PFVF_FUNC_MASK;
758 struct otx2_vf_config *config = &pf->vf_configs[devid - 1];
759 struct delayed_work *dwork;
762 case MBOX_MSG_NIX_LF_START_RX:
763 config->intf_down = false;
764 dwork = &config->link_event_work;
765 schedule_delayed_work(dwork, msecs_to_jiffies(100));
767 case MBOX_MSG_NIX_LF_STOP_RX:
768 config->intf_down = true;
777 pf->pcifunc = msg->pcifunc;
779 case MBOX_MSG_MSIX_OFFSET:
780 mbox_handler_msix_offset(pf, (struct msix_offset_rsp *)msg);
782 case MBOX_MSG_NPA_LF_ALLOC:
783 mbox_handler_npa_lf_alloc(pf, (struct npa_lf_alloc_rsp *)msg);
785 case MBOX_MSG_NIX_LF_ALLOC:
786 mbox_handler_nix_lf_alloc(pf, (struct nix_lf_alloc_rsp *)msg);
788 case MBOX_MSG_NIX_TXSCH_ALLOC:
789 mbox_handler_nix_txsch_alloc(pf,
790 (struct nix_txsch_alloc_rsp *)msg);
792 case MBOX_MSG_NIX_BP_ENABLE:
793 mbox_handler_nix_bp_enable(pf, (struct nix_bp_cfg_rsp *)msg);
795 case MBOX_MSG_CGX_STATS:
796 mbox_handler_cgx_stats(pf, (struct cgx_stats_rsp *)msg);
798 case MBOX_MSG_CGX_FEC_STATS:
799 mbox_handler_cgx_fec_stats(pf, (struct cgx_fec_stats_rsp *)msg);
804 "Mbox msg response has err %d, ID 0x%x\n",
810 static void otx2_pfaf_mbox_handler(struct work_struct *work)
812 struct otx2_mbox_dev *mdev;
813 struct mbox_hdr *rsp_hdr;
814 struct mbox_msghdr *msg;
815 struct otx2_mbox *mbox;
816 struct mbox *af_mbox;
820 af_mbox = container_of(work, struct mbox, mbox_wrk);
821 mbox = &af_mbox->mbox;
822 mdev = &mbox->dev[0];
823 rsp_hdr = (struct mbox_hdr *)(mdev->mbase + mbox->rx_start);
825 offset = mbox->rx_start + ALIGN(sizeof(*rsp_hdr), MBOX_MSG_ALIGN);
828 for (id = 0; id < af_mbox->num_msgs; id++) {
829 msg = (struct mbox_msghdr *)(mdev->mbase + offset);
830 otx2_process_pfaf_mbox_msg(pf, msg);
831 offset = mbox->rx_start + msg->next_msgoff;
832 if (mdev->msgs_acked == (af_mbox->num_msgs - 1))
833 __otx2_mbox_reset(mbox, 0);
839 static void otx2_handle_link_event(struct otx2_nic *pf)
841 struct cgx_link_user_info *linfo = &pf->linfo;
842 struct net_device *netdev = pf->netdev;
844 pr_info("%s NIC Link is %s %d Mbps %s duplex\n", netdev->name,
845 linfo->link_up ? "UP" : "DOWN", linfo->speed,
846 linfo->full_duplex ? "Full" : "Half");
847 if (linfo->link_up) {
848 netif_carrier_on(netdev);
849 netif_tx_start_all_queues(netdev);
851 netif_tx_stop_all_queues(netdev);
852 netif_carrier_off(netdev);
856 int otx2_mbox_up_handler_cgx_link_event(struct otx2_nic *pf,
857 struct cgx_link_info_msg *msg,
862 /* Copy the link info sent by AF */
863 pf->linfo = msg->link_info;
865 /* notify VFs about link event */
866 for (i = 0; i < pci_num_vf(pf->pdev); i++) {
867 struct otx2_vf_config *config = &pf->vf_configs[i];
868 struct delayed_work *dwork = &config->link_event_work;
870 if (config->intf_down)
873 schedule_delayed_work(dwork, msecs_to_jiffies(100));
876 /* interface has not been fully configured yet */
877 if (pf->flags & OTX2_FLAG_INTF_DOWN)
880 otx2_handle_link_event(pf);
884 static int otx2_process_mbox_msg_up(struct otx2_nic *pf,
885 struct mbox_msghdr *req)
887 /* Check if valid, if not reply with a invalid msg */
888 if (req->sig != OTX2_MBOX_REQ_SIG) {
889 otx2_reply_invalid_msg(&pf->mbox.mbox_up, 0, 0, req->id);
894 #define M(_name, _id, _fn_name, _req_type, _rsp_type) \
896 struct _rsp_type *rsp; \
899 rsp = (struct _rsp_type *)otx2_mbox_alloc_msg( \
900 &pf->mbox.mbox_up, 0, \
901 sizeof(struct _rsp_type)); \
906 rsp->hdr.sig = OTX2_MBOX_RSP_SIG; \
907 rsp->hdr.pcifunc = 0; \
910 err = otx2_mbox_up_handler_ ## _fn_name( \
911 pf, (struct _req_type *)req, rsp); \
918 otx2_reply_invalid_msg(&pf->mbox.mbox_up, 0, 0, req->id);
924 static void otx2_pfaf_mbox_up_handler(struct work_struct *work)
926 struct mbox *af_mbox = container_of(work, struct mbox, mbox_up_wrk);
927 struct otx2_mbox *mbox = &af_mbox->mbox_up;
928 struct otx2_mbox_dev *mdev = &mbox->dev[0];
929 struct otx2_nic *pf = af_mbox->pfvf;
930 int offset, id, devid = 0;
931 struct mbox_hdr *rsp_hdr;
932 struct mbox_msghdr *msg;
934 rsp_hdr = (struct mbox_hdr *)(mdev->mbase + mbox->rx_start);
936 offset = mbox->rx_start + ALIGN(sizeof(*rsp_hdr), MBOX_MSG_ALIGN);
938 for (id = 0; id < af_mbox->up_num_msgs; id++) {
939 msg = (struct mbox_msghdr *)(mdev->mbase + offset);
941 devid = msg->pcifunc & RVU_PFVF_FUNC_MASK;
942 /* Skip processing VF's messages */
944 otx2_process_mbox_msg_up(pf, msg);
945 offset = mbox->rx_start + msg->next_msgoff;
948 otx2_forward_vf_mbox_msgs(pf, &pf->mbox.mbox_up,
949 MBOX_DIR_PFVF_UP, devid - 1,
950 af_mbox->up_num_msgs);
954 otx2_mbox_msg_send(mbox, 0);
957 static irqreturn_t otx2_pfaf_mbox_intr_handler(int irq, void *pf_irq)
959 struct otx2_nic *pf = (struct otx2_nic *)pf_irq;
963 otx2_write64(pf, RVU_PF_INT, BIT_ULL(0));
967 trace_otx2_msg_interrupt(mbox->mbox.pdev, "AF to PF", BIT_ULL(0));
969 otx2_queue_work(mbox, pf->mbox_wq, 0, 1, 1, TYPE_PFAF);
974 static void otx2_disable_mbox_intr(struct otx2_nic *pf)
976 int vector = pci_irq_vector(pf->pdev, RVU_PF_INT_VEC_AFPF_MBOX);
978 /* Disable AF => PF mailbox IRQ */
979 otx2_write64(pf, RVU_PF_INT_ENA_W1C, BIT_ULL(0));
980 free_irq(vector, pf);
983 static int otx2_register_mbox_intr(struct otx2_nic *pf, bool probe_af)
985 struct otx2_hw *hw = &pf->hw;
990 /* Register mailbox interrupt handler */
991 irq_name = &hw->irq_name[RVU_PF_INT_VEC_AFPF_MBOX * NAME_SIZE];
992 snprintf(irq_name, NAME_SIZE, "RVUPFAF Mbox");
993 err = request_irq(pci_irq_vector(pf->pdev, RVU_PF_INT_VEC_AFPF_MBOX),
994 otx2_pfaf_mbox_intr_handler, 0, irq_name, pf);
997 "RVUPF: IRQ registration failed for PFAF mbox irq\n");
1001 /* Enable mailbox interrupt for msgs coming from AF.
1002 * First clear to avoid spurious interrupts, if any.
1004 otx2_write64(pf, RVU_PF_INT, BIT_ULL(0));
1005 otx2_write64(pf, RVU_PF_INT_ENA_W1S, BIT_ULL(0));
1010 /* Check mailbox communication with AF */
1011 req = otx2_mbox_alloc_msg_ready(&pf->mbox);
1013 otx2_disable_mbox_intr(pf);
1016 err = otx2_sync_mbox_msg(&pf->mbox);
1019 "AF not responding to mailbox, deferring probe\n");
1020 otx2_disable_mbox_intr(pf);
1021 return -EPROBE_DEFER;
1027 static void otx2_pfaf_mbox_destroy(struct otx2_nic *pf)
1029 struct mbox *mbox = &pf->mbox;
1032 destroy_workqueue(pf->mbox_wq);
1036 if (mbox->mbox.hwbase)
1037 iounmap((void __iomem *)mbox->mbox.hwbase);
1039 otx2_mbox_destroy(&mbox->mbox);
1040 otx2_mbox_destroy(&mbox->mbox_up);
1043 static int otx2_pfaf_mbox_init(struct otx2_nic *pf)
1045 struct mbox *mbox = &pf->mbox;
1046 void __iomem *hwbase;
1050 pf->mbox_wq = alloc_workqueue("otx2_pfaf_mailbox",
1051 WQ_UNBOUND | WQ_HIGHPRI |
1056 /* Mailbox is a reserved memory (in RAM) region shared between
1057 * admin function (i.e AF) and this PF, shouldn't be mapped as
1058 * device memory to allow unaligned accesses.
1060 hwbase = ioremap_wc(pci_resource_start(pf->pdev, PCI_MBOX_BAR_NUM),
1063 dev_err(pf->dev, "Unable to map PFAF mailbox region\n");
1068 err = otx2_mbox_init(&mbox->mbox, hwbase, pf->pdev, pf->reg_base,
1073 err = otx2_mbox_init(&mbox->mbox_up, hwbase, pf->pdev, pf->reg_base,
1074 MBOX_DIR_PFAF_UP, 1);
1078 err = otx2_mbox_bbuf_init(mbox, pf->pdev);
1082 INIT_WORK(&mbox->mbox_wrk, otx2_pfaf_mbox_handler);
1083 INIT_WORK(&mbox->mbox_up_wrk, otx2_pfaf_mbox_up_handler);
1084 mutex_init(&mbox->lock);
1088 otx2_pfaf_mbox_destroy(pf);
1092 static int otx2_cgx_config_linkevents(struct otx2_nic *pf, bool enable)
1094 struct msg_req *msg;
1097 mutex_lock(&pf->mbox.lock);
1099 msg = otx2_mbox_alloc_msg_cgx_start_linkevents(&pf->mbox);
1101 msg = otx2_mbox_alloc_msg_cgx_stop_linkevents(&pf->mbox);
1104 mutex_unlock(&pf->mbox.lock);
1108 err = otx2_sync_mbox_msg(&pf->mbox);
1109 mutex_unlock(&pf->mbox.lock);
1113 static int otx2_cgx_config_loopback(struct otx2_nic *pf, bool enable)
1115 struct msg_req *msg;
1118 if (enable && bitmap_weight(&pf->flow_cfg->dmacflt_bmap,
1119 pf->flow_cfg->dmacflt_max_flows))
1120 netdev_warn(pf->netdev,
1121 "CGX/RPM internal loopback might not work as DMAC filters are active\n");
1123 mutex_lock(&pf->mbox.lock);
1125 msg = otx2_mbox_alloc_msg_cgx_intlbk_enable(&pf->mbox);
1127 msg = otx2_mbox_alloc_msg_cgx_intlbk_disable(&pf->mbox);
1130 mutex_unlock(&pf->mbox.lock);
1134 err = otx2_sync_mbox_msg(&pf->mbox);
1135 mutex_unlock(&pf->mbox.lock);
1139 int otx2_set_real_num_queues(struct net_device *netdev,
1140 int tx_queues, int rx_queues)
1144 err = netif_set_real_num_tx_queues(netdev, tx_queues);
1147 "Failed to set no of Tx queues: %d\n", tx_queues);
1151 err = netif_set_real_num_rx_queues(netdev, rx_queues);
1154 "Failed to set no of Rx queues: %d\n", rx_queues);
1157 EXPORT_SYMBOL(otx2_set_real_num_queues);
1159 static irqreturn_t otx2_q_intr_handler(int irq, void *data)
1161 struct otx2_nic *pf = data;
1166 for (qidx = 0; qidx < pf->qset.cq_cnt; qidx++) {
1167 ptr = otx2_get_regaddr(pf, NIX_LF_CQ_OP_INT);
1168 val = otx2_atomic64_add((qidx << 44), ptr);
1170 otx2_write64(pf, NIX_LF_CQ_OP_INT, (qidx << 44) |
1171 (val & NIX_CQERRINT_BITS));
1172 if (!(val & (NIX_CQERRINT_BITS | BIT_ULL(42))))
1175 if (val & BIT_ULL(42)) {
1176 netdev_err(pf->netdev, "CQ%lld: error reading NIX_LF_CQ_OP_INT, NIX_LF_ERR_INT 0x%llx\n",
1177 qidx, otx2_read64(pf, NIX_LF_ERR_INT));
1179 if (val & BIT_ULL(NIX_CQERRINT_DOOR_ERR))
1180 netdev_err(pf->netdev, "CQ%lld: Doorbell error",
1182 if (val & BIT_ULL(NIX_CQERRINT_CQE_FAULT))
1183 netdev_err(pf->netdev, "CQ%lld: Memory fault on CQE write to LLC/DRAM",
1187 schedule_work(&pf->reset_task);
1191 for (qidx = 0; qidx < pf->hw.tot_tx_queues; qidx++) {
1192 ptr = otx2_get_regaddr(pf, NIX_LF_SQ_OP_INT);
1193 val = otx2_atomic64_add((qidx << 44), ptr);
1194 otx2_write64(pf, NIX_LF_SQ_OP_INT, (qidx << 44) |
1195 (val & NIX_SQINT_BITS));
1197 if (!(val & (NIX_SQINT_BITS | BIT_ULL(42))))
1200 if (val & BIT_ULL(42)) {
1201 netdev_err(pf->netdev, "SQ%lld: error reading NIX_LF_SQ_OP_INT, NIX_LF_ERR_INT 0x%llx\n",
1202 qidx, otx2_read64(pf, NIX_LF_ERR_INT));
1204 if (val & BIT_ULL(NIX_SQINT_LMT_ERR)) {
1205 netdev_err(pf->netdev, "SQ%lld: LMT store error NIX_LF_SQ_OP_ERR_DBG:0x%llx",
1208 NIX_LF_SQ_OP_ERR_DBG));
1209 otx2_write64(pf, NIX_LF_SQ_OP_ERR_DBG,
1212 if (val & BIT_ULL(NIX_SQINT_MNQ_ERR)) {
1213 netdev_err(pf->netdev, "SQ%lld: Meta-descriptor enqueue error NIX_LF_MNQ_ERR_DGB:0x%llx\n",
1215 otx2_read64(pf, NIX_LF_MNQ_ERR_DBG));
1216 otx2_write64(pf, NIX_LF_MNQ_ERR_DBG,
1219 if (val & BIT_ULL(NIX_SQINT_SEND_ERR)) {
1220 netdev_err(pf->netdev, "SQ%lld: Send error, NIX_LF_SEND_ERR_DBG 0x%llx",
1223 NIX_LF_SEND_ERR_DBG));
1224 otx2_write64(pf, NIX_LF_SEND_ERR_DBG,
1227 if (val & BIT_ULL(NIX_SQINT_SQB_ALLOC_FAIL))
1228 netdev_err(pf->netdev, "SQ%lld: SQB allocation failed",
1232 schedule_work(&pf->reset_task);
1238 static irqreturn_t otx2_cq_intr_handler(int irq, void *cq_irq)
1240 struct otx2_cq_poll *cq_poll = (struct otx2_cq_poll *)cq_irq;
1241 struct otx2_nic *pf = (struct otx2_nic *)cq_poll->dev;
1242 int qidx = cq_poll->cint_idx;
1244 /* Disable interrupts.
1246 * Completion interrupts behave in a level-triggered interrupt
1247 * fashion, and hence have to be cleared only after it is serviced.
1249 otx2_write64(pf, NIX_LF_CINTX_ENA_W1C(qidx), BIT_ULL(0));
1252 napi_schedule_irqoff(&cq_poll->napi);
1257 static void otx2_disable_napi(struct otx2_nic *pf)
1259 struct otx2_qset *qset = &pf->qset;
1260 struct otx2_cq_poll *cq_poll;
1263 for (qidx = 0; qidx < pf->hw.cint_cnt; qidx++) {
1264 cq_poll = &qset->napi[qidx];
1265 napi_disable(&cq_poll->napi);
1266 netif_napi_del(&cq_poll->napi);
1270 static void otx2_free_cq_res(struct otx2_nic *pf)
1272 struct otx2_qset *qset = &pf->qset;
1273 struct otx2_cq_queue *cq;
1277 otx2_ctx_disable(&pf->mbox, NIX_AQ_CTYPE_CQ, false);
1278 for (qidx = 0; qidx < qset->cq_cnt; qidx++) {
1279 cq = &qset->cq[qidx];
1280 qmem_free(pf->dev, cq->cqe);
1284 static void otx2_free_sq_res(struct otx2_nic *pf)
1286 struct otx2_qset *qset = &pf->qset;
1287 struct otx2_snd_queue *sq;
1291 otx2_ctx_disable(&pf->mbox, NIX_AQ_CTYPE_SQ, false);
1292 /* Free SQB pointers */
1293 otx2_sq_free_sqbs(pf);
1294 for (qidx = 0; qidx < pf->hw.tot_tx_queues; qidx++) {
1295 sq = &qset->sq[qidx];
1296 qmem_free(pf->dev, sq->sqe);
1297 qmem_free(pf->dev, sq->tso_hdrs);
1299 kfree(sq->sqb_ptrs);
1303 static int otx2_get_rbuf_size(struct otx2_nic *pf, int mtu)
1309 /* The data transferred by NIX to memory consists of actual packet
1310 * plus additional data which has timestamp and/or EDSA/HIGIG2
1311 * headers if interface is configured in corresponding modes.
1312 * NIX transfers entire data using 6 segments/buffers and writes
1313 * a CQE_RX descriptor with those segment addresses. First segment
1314 * has additional data prepended to packet. Also software omits a
1315 * headroom of 128 bytes in each segment. Hence the total size of
1316 * memory needed to receive a packet with 'mtu' is:
1317 * frame size = mtu + additional data;
1318 * memory = frame_size + headroom * 6;
1319 * each receive buffer size = memory / 6;
1321 frame_size = mtu + OTX2_ETH_HLEN + OTX2_HW_TIMESTAMP_LEN;
1322 total_size = frame_size + OTX2_HEAD_ROOM * 6;
1323 rbuf_size = total_size / 6;
1325 return ALIGN(rbuf_size, 2048);
1328 static int otx2_init_hw_resources(struct otx2_nic *pf)
1330 struct nix_lf_free_req *free_req;
1331 struct mbox *mbox = &pf->mbox;
1332 struct otx2_hw *hw = &pf->hw;
1333 struct msg_req *req;
1336 /* Set required NPA LF's pool counts
1337 * Auras and Pools are used in a 1:1 mapping,
1338 * so, aura count = pool count.
1340 hw->rqpool_cnt = hw->rx_queues;
1341 hw->sqpool_cnt = hw->tot_tx_queues;
1342 hw->pool_cnt = hw->rqpool_cnt + hw->sqpool_cnt;
1344 /* Maximum hardware supported transmit length */
1345 pf->tx_max_pktlen = pf->netdev->max_mtu + OTX2_ETH_HLEN;
1347 pf->rbsize = otx2_get_rbuf_size(pf, pf->netdev->mtu);
1349 mutex_lock(&mbox->lock);
1351 err = otx2_config_npa(pf);
1356 err = otx2_config_nix(pf);
1358 goto err_free_npa_lf;
1360 /* Enable backpressure */
1361 otx2_nix_config_bp(pf, true);
1363 /* Init Auras and pools used by NIX RQ, for free buffer ptrs */
1364 err = otx2_rq_aura_pool_init(pf);
1366 mutex_unlock(&mbox->lock);
1367 goto err_free_nix_lf;
1369 /* Init Auras and pools used by NIX SQ, for queueing SQEs */
1370 err = otx2_sq_aura_pool_init(pf);
1372 mutex_unlock(&mbox->lock);
1373 goto err_free_rq_ptrs;
1376 err = otx2_txsch_alloc(pf);
1378 mutex_unlock(&mbox->lock);
1379 goto err_free_sq_ptrs;
1382 err = otx2_config_nix_queues(pf);
1384 mutex_unlock(&mbox->lock);
1385 goto err_free_txsch;
1387 for (lvl = 0; lvl < NIX_TXSCH_LVL_CNT; lvl++) {
1388 err = otx2_txschq_config(pf, lvl);
1390 mutex_unlock(&mbox->lock);
1391 goto err_free_nix_queues;
1394 mutex_unlock(&mbox->lock);
1397 err_free_nix_queues:
1398 otx2_free_sq_res(pf);
1399 otx2_free_cq_res(pf);
1400 otx2_ctx_disable(mbox, NIX_AQ_CTYPE_RQ, false);
1402 if (otx2_txschq_stop(pf))
1403 dev_err(pf->dev, "%s failed to stop TX schedulers\n", __func__);
1405 otx2_sq_free_sqbs(pf);
1407 otx2_free_aura_ptr(pf, AURA_NIX_RQ);
1408 otx2_ctx_disable(mbox, NPA_AQ_CTYPE_POOL, true);
1409 otx2_ctx_disable(mbox, NPA_AQ_CTYPE_AURA, true);
1410 otx2_aura_pool_free(pf);
1412 mutex_lock(&mbox->lock);
1413 free_req = otx2_mbox_alloc_msg_nix_lf_free(mbox);
1415 free_req->flags = NIX_LF_DISABLE_FLOWS;
1416 if (otx2_sync_mbox_msg(mbox))
1417 dev_err(pf->dev, "%s failed to free nixlf\n", __func__);
1421 req = otx2_mbox_alloc_msg_npa_lf_free(mbox);
1423 if (otx2_sync_mbox_msg(mbox))
1424 dev_err(pf->dev, "%s failed to free npalf\n", __func__);
1427 mutex_unlock(&mbox->lock);
1431 static void otx2_free_hw_resources(struct otx2_nic *pf)
1433 struct otx2_qset *qset = &pf->qset;
1434 struct nix_lf_free_req *free_req;
1435 struct mbox *mbox = &pf->mbox;
1436 struct otx2_cq_queue *cq;
1437 struct msg_req *req;
1440 /* Ensure all SQE are processed */
1443 /* Stop transmission */
1444 err = otx2_txschq_stop(pf);
1446 dev_err(pf->dev, "RVUPF: Failed to stop/free TX schedulers\n");
1448 mutex_lock(&mbox->lock);
1449 /* Disable backpressure */
1450 if (!(pf->pcifunc & RVU_PFVF_FUNC_MASK))
1451 otx2_nix_config_bp(pf, false);
1452 mutex_unlock(&mbox->lock);
1455 otx2_ctx_disable(mbox, NIX_AQ_CTYPE_RQ, false);
1457 /*Dequeue all CQEs */
1458 for (qidx = 0; qidx < qset->cq_cnt; qidx++) {
1459 cq = &qset->cq[qidx];
1460 if (cq->cq_type == CQ_RX)
1461 otx2_cleanup_rx_cqes(pf, cq);
1463 otx2_cleanup_tx_cqes(pf, cq);
1466 otx2_free_sq_res(pf);
1468 /* Free RQ buffer pointers*/
1469 otx2_free_aura_ptr(pf, AURA_NIX_RQ);
1471 otx2_free_cq_res(pf);
1473 /* Free all ingress bandwidth profiles allocated */
1474 cn10k_free_all_ipolicers(pf);
1476 mutex_lock(&mbox->lock);
1478 free_req = otx2_mbox_alloc_msg_nix_lf_free(mbox);
1480 free_req->flags = NIX_LF_DISABLE_FLOWS;
1481 if (!(pf->flags & OTX2_FLAG_PF_SHUTDOWN))
1482 free_req->flags |= NIX_LF_DONT_FREE_TX_VTAG;
1483 if (otx2_sync_mbox_msg(mbox))
1484 dev_err(pf->dev, "%s failed to free nixlf\n", __func__);
1486 mutex_unlock(&mbox->lock);
1488 /* Disable NPA Pool and Aura hw context */
1489 otx2_ctx_disable(mbox, NPA_AQ_CTYPE_POOL, true);
1490 otx2_ctx_disable(mbox, NPA_AQ_CTYPE_AURA, true);
1491 otx2_aura_pool_free(pf);
1493 mutex_lock(&mbox->lock);
1495 req = otx2_mbox_alloc_msg_npa_lf_free(mbox);
1497 if (otx2_sync_mbox_msg(mbox))
1498 dev_err(pf->dev, "%s failed to free npalf\n", __func__);
1500 mutex_unlock(&mbox->lock);
1503 static void otx2_do_set_rx_mode(struct otx2_nic *pf)
1505 struct net_device *netdev = pf->netdev;
1506 struct nix_rx_mode *req;
1507 bool promisc = false;
1509 if (!(netdev->flags & IFF_UP))
1512 if ((netdev->flags & IFF_PROMISC) ||
1513 (netdev_uc_count(netdev) > OTX2_MAX_UNICAST_FLOWS)) {
1517 /* Write unicast address to mcam entries or del from mcam */
1518 if (!promisc && netdev->priv_flags & IFF_UNICAST_FLT)
1519 __dev_uc_sync(netdev, otx2_add_macfilter, otx2_del_macfilter);
1521 mutex_lock(&pf->mbox.lock);
1522 req = otx2_mbox_alloc_msg_nix_set_rx_mode(&pf->mbox);
1524 mutex_unlock(&pf->mbox.lock);
1528 req->mode = NIX_RX_MODE_UCAST;
1531 req->mode |= NIX_RX_MODE_PROMISC;
1532 if (netdev->flags & (IFF_ALLMULTI | IFF_MULTICAST))
1533 req->mode |= NIX_RX_MODE_ALLMULTI;
1535 req->mode |= NIX_RX_MODE_USE_MCE;
1537 otx2_sync_mbox_msg(&pf->mbox);
1538 mutex_unlock(&pf->mbox.lock);
1541 int otx2_open(struct net_device *netdev)
1543 struct otx2_nic *pf = netdev_priv(netdev);
1544 struct otx2_cq_poll *cq_poll = NULL;
1545 struct otx2_qset *qset = &pf->qset;
1546 int err = 0, qidx, vec;
1549 netif_carrier_off(netdev);
1551 pf->qset.cq_cnt = pf->hw.rx_queues + pf->hw.tot_tx_queues;
1552 /* RQ and SQs are mapped to different CQs,
1553 * so find out max CQ IRQs (i.e CINTs) needed.
1555 pf->hw.cint_cnt = max(pf->hw.rx_queues, pf->hw.tx_queues);
1556 qset->napi = kcalloc(pf->hw.cint_cnt, sizeof(*cq_poll), GFP_KERNEL);
1561 qset->rqe_cnt = qset->rqe_cnt ? qset->rqe_cnt : Q_COUNT(Q_SIZE_256);
1563 qset->sqe_cnt = qset->sqe_cnt ? qset->sqe_cnt : Q_COUNT(Q_SIZE_4K);
1566 qset->cq = kcalloc(pf->qset.cq_cnt,
1567 sizeof(struct otx2_cq_queue), GFP_KERNEL);
1571 qset->sq = kcalloc(pf->hw.tot_tx_queues,
1572 sizeof(struct otx2_snd_queue), GFP_KERNEL);
1576 qset->rq = kcalloc(pf->hw.rx_queues,
1577 sizeof(struct otx2_rcv_queue), GFP_KERNEL);
1581 err = otx2_init_hw_resources(pf);
1585 /* Register NAPI handler */
1586 for (qidx = 0; qidx < pf->hw.cint_cnt; qidx++) {
1587 cq_poll = &qset->napi[qidx];
1588 cq_poll->cint_idx = qidx;
1589 /* RQ0 & SQ0 are mapped to CINT0 and so on..
1590 * 'cq_ids[0]' points to RQ's CQ and
1591 * 'cq_ids[1]' points to SQ's CQ and
1592 * 'cq_ids[2]' points to XDP's CQ and
1594 cq_poll->cq_ids[CQ_RX] =
1595 (qidx < pf->hw.rx_queues) ? qidx : CINT_INVALID_CQ;
1596 cq_poll->cq_ids[CQ_TX] = (qidx < pf->hw.tx_queues) ?
1597 qidx + pf->hw.rx_queues : CINT_INVALID_CQ;
1599 cq_poll->cq_ids[CQ_XDP] = (qidx < pf->hw.xdp_queues) ?
1600 (qidx + pf->hw.rx_queues +
1604 cq_poll->cq_ids[CQ_XDP] = CINT_INVALID_CQ;
1606 cq_poll->dev = (void *)pf;
1607 netif_napi_add(netdev, &cq_poll->napi,
1608 otx2_napi_handler, NAPI_POLL_WEIGHT);
1609 napi_enable(&cq_poll->napi);
1612 /* Set maximum frame size allowed in HW */
1613 err = otx2_hw_set_mtu(pf, netdev->mtu);
1615 goto err_disable_napi;
1617 /* Setup segmentation algorithms, if failed, clear offload capability */
1618 otx2_setup_segmentation(pf);
1620 /* Initialize RSS */
1621 err = otx2_rss_init(pf);
1623 goto err_disable_napi;
1625 /* Register Queue IRQ handlers */
1626 vec = pf->hw.nix_msixoff + NIX_LF_QINT_VEC_START;
1627 irq_name = &pf->hw.irq_name[vec * NAME_SIZE];
1629 snprintf(irq_name, NAME_SIZE, "%s-qerr", pf->netdev->name);
1631 err = request_irq(pci_irq_vector(pf->pdev, vec),
1632 otx2_q_intr_handler, 0, irq_name, pf);
1635 "RVUPF%d: IRQ registration failed for QERR\n",
1636 rvu_get_pf(pf->pcifunc));
1637 goto err_disable_napi;
1640 /* Enable QINT IRQ */
1641 otx2_write64(pf, NIX_LF_QINTX_ENA_W1S(0), BIT_ULL(0));
1643 /* Register CQ IRQ handlers */
1644 vec = pf->hw.nix_msixoff + NIX_LF_CINT_VEC_START;
1645 for (qidx = 0; qidx < pf->hw.cint_cnt; qidx++) {
1646 irq_name = &pf->hw.irq_name[vec * NAME_SIZE];
1648 snprintf(irq_name, NAME_SIZE, "%s-rxtx-%d", pf->netdev->name,
1651 err = request_irq(pci_irq_vector(pf->pdev, vec),
1652 otx2_cq_intr_handler, 0, irq_name,
1656 "RVUPF%d: IRQ registration failed for CQ%d\n",
1657 rvu_get_pf(pf->pcifunc), qidx);
1658 goto err_free_cints;
1662 otx2_config_irq_coalescing(pf, qidx);
1665 otx2_write64(pf, NIX_LF_CINTX_INT(qidx), BIT_ULL(0));
1666 otx2_write64(pf, NIX_LF_CINTX_ENA_W1S(qidx), BIT_ULL(0));
1669 otx2_set_cints_affinity(pf);
1671 if (pf->flags & OTX2_FLAG_RX_VLAN_SUPPORT)
1672 otx2_enable_rxvlan(pf, true);
1674 /* When reinitializing enable time stamping if it is enabled before */
1675 if (pf->flags & OTX2_FLAG_TX_TSTAMP_ENABLED) {
1676 pf->flags &= ~OTX2_FLAG_TX_TSTAMP_ENABLED;
1677 otx2_config_hw_tx_tstamp(pf, true);
1679 if (pf->flags & OTX2_FLAG_RX_TSTAMP_ENABLED) {
1680 pf->flags &= ~OTX2_FLAG_RX_TSTAMP_ENABLED;
1681 otx2_config_hw_rx_tstamp(pf, true);
1684 pf->flags &= ~OTX2_FLAG_INTF_DOWN;
1685 /* 'intf_down' may be checked on any cpu */
1688 /* we have already received link status notification */
1689 if (pf->linfo.link_up && !(pf->pcifunc & RVU_PFVF_FUNC_MASK))
1690 otx2_handle_link_event(pf);
1692 /* Restore pause frame settings */
1693 otx2_config_pause_frm(pf);
1695 /* Install DMAC Filters */
1696 if (pf->flags & OTX2_FLAG_DMACFLTR_SUPPORT)
1697 otx2_dmacflt_reinstall_flows(pf);
1699 err = otx2_rxtx_enable(pf, true);
1701 goto err_tx_stop_queues;
1703 otx2_do_set_rx_mode(pf);
1708 netif_tx_stop_all_queues(netdev);
1709 netif_carrier_off(netdev);
1710 pf->flags |= OTX2_FLAG_INTF_DOWN;
1712 otx2_free_cints(pf, qidx);
1713 vec = pci_irq_vector(pf->pdev,
1714 pf->hw.nix_msixoff + NIX_LF_QINT_VEC_START);
1715 otx2_write64(pf, NIX_LF_QINTX_ENA_W1C(0), BIT_ULL(0));
1716 synchronize_irq(vec);
1719 otx2_disable_napi(pf);
1720 otx2_free_hw_resources(pf);
1728 EXPORT_SYMBOL(otx2_open);
1730 int otx2_stop(struct net_device *netdev)
1732 struct otx2_nic *pf = netdev_priv(netdev);
1733 struct otx2_cq_poll *cq_poll = NULL;
1734 struct otx2_qset *qset = &pf->qset;
1735 struct otx2_rss_info *rss;
1738 /* If the DOWN flag is set resources are already freed */
1739 if (pf->flags & OTX2_FLAG_INTF_DOWN)
1742 netif_carrier_off(netdev);
1743 netif_tx_stop_all_queues(netdev);
1745 pf->flags |= OTX2_FLAG_INTF_DOWN;
1746 /* 'intf_down' may be checked on any cpu */
1749 /* First stop packet Rx/Tx */
1750 otx2_rxtx_enable(pf, false);
1752 /* Clear RSS enable flag */
1753 rss = &pf->hw.rss_info;
1754 rss->enable = false;
1756 /* Cleanup Queue IRQ */
1757 vec = pci_irq_vector(pf->pdev,
1758 pf->hw.nix_msixoff + NIX_LF_QINT_VEC_START);
1759 otx2_write64(pf, NIX_LF_QINTX_ENA_W1C(0), BIT_ULL(0));
1760 synchronize_irq(vec);
1763 /* Cleanup CQ NAPI and IRQ */
1764 vec = pf->hw.nix_msixoff + NIX_LF_CINT_VEC_START;
1765 for (qidx = 0; qidx < pf->hw.cint_cnt; qidx++) {
1766 /* Disable interrupt */
1767 otx2_write64(pf, NIX_LF_CINTX_ENA_W1C(qidx), BIT_ULL(0));
1769 synchronize_irq(pci_irq_vector(pf->pdev, vec));
1771 cq_poll = &qset->napi[qidx];
1772 napi_synchronize(&cq_poll->napi);
1776 netif_tx_disable(netdev);
1778 otx2_free_hw_resources(pf);
1779 otx2_free_cints(pf, pf->hw.cint_cnt);
1780 otx2_disable_napi(pf);
1782 for (qidx = 0; qidx < netdev->num_tx_queues; qidx++)
1783 netdev_tx_reset_queue(netdev_get_tx_queue(netdev, qidx));
1785 for (wrk = 0; wrk < pf->qset.cq_cnt; wrk++)
1786 cancel_delayed_work_sync(&pf->refill_wrk[wrk].pool_refill_work);
1787 devm_kfree(pf->dev, pf->refill_wrk);
1793 /* Do not clear RQ/SQ ringsize settings */
1794 memset((void *)qset + offsetof(struct otx2_qset, sqe_cnt), 0,
1795 sizeof(*qset) - offsetof(struct otx2_qset, sqe_cnt));
1798 EXPORT_SYMBOL(otx2_stop);
1800 static netdev_tx_t otx2_xmit(struct sk_buff *skb, struct net_device *netdev)
1802 struct otx2_nic *pf = netdev_priv(netdev);
1803 int qidx = skb_get_queue_mapping(skb);
1804 struct otx2_snd_queue *sq;
1805 struct netdev_queue *txq;
1807 /* Check for minimum and maximum packet length */
1808 if (skb->len <= ETH_HLEN ||
1809 (!skb_shinfo(skb)->gso_size && skb->len > pf->tx_max_pktlen)) {
1811 return NETDEV_TX_OK;
1814 sq = &pf->qset.sq[qidx];
1815 txq = netdev_get_tx_queue(netdev, qidx);
1817 if (!otx2_sq_append_skb(netdev, sq, skb, qidx)) {
1818 netif_tx_stop_queue(txq);
1820 /* Check again, incase SQBs got freed up */
1822 if (((sq->num_sqbs - *sq->aura_fc_addr) * sq->sqe_per_sqb)
1824 netif_tx_wake_queue(txq);
1826 return NETDEV_TX_BUSY;
1829 return NETDEV_TX_OK;
1832 static netdev_features_t otx2_fix_features(struct net_device *dev,
1833 netdev_features_t features)
1835 if (features & NETIF_F_HW_VLAN_CTAG_RX)
1836 features |= NETIF_F_HW_VLAN_STAG_RX;
1838 features &= ~NETIF_F_HW_VLAN_STAG_RX;
1843 static void otx2_set_rx_mode(struct net_device *netdev)
1845 struct otx2_nic *pf = netdev_priv(netdev);
1847 queue_work(pf->otx2_wq, &pf->rx_mode_work);
1850 static void otx2_rx_mode_wrk_handler(struct work_struct *work)
1852 struct otx2_nic *pf = container_of(work, struct otx2_nic, rx_mode_work);
1854 otx2_do_set_rx_mode(pf);
1857 static int otx2_set_features(struct net_device *netdev,
1858 netdev_features_t features)
1860 netdev_features_t changed = features ^ netdev->features;
1861 bool ntuple = !!(features & NETIF_F_NTUPLE);
1862 struct otx2_nic *pf = netdev_priv(netdev);
1863 bool tc = !!(features & NETIF_F_HW_TC);
1865 if ((changed & NETIF_F_LOOPBACK) && netif_running(netdev))
1866 return otx2_cgx_config_loopback(pf,
1867 features & NETIF_F_LOOPBACK);
1869 if ((changed & NETIF_F_HW_VLAN_CTAG_RX) && netif_running(netdev))
1870 return otx2_enable_rxvlan(pf,
1871 features & NETIF_F_HW_VLAN_CTAG_RX);
1873 if ((changed & NETIF_F_NTUPLE) && !ntuple)
1874 otx2_destroy_ntuple_flows(pf);
1876 if ((changed & NETIF_F_NTUPLE) && ntuple) {
1877 if (!pf->flow_cfg->max_flows) {
1879 "Can't enable NTUPLE, MCAM entries not allocated\n");
1884 if ((changed & NETIF_F_HW_TC) && tc) {
1885 if (!pf->flow_cfg->max_flows) {
1887 "Can't enable TC, MCAM entries not allocated\n");
1892 if ((changed & NETIF_F_HW_TC) && !tc &&
1893 pf->flow_cfg && pf->flow_cfg->nr_flows) {
1894 netdev_err(netdev, "Can't disable TC hardware offload while flows are active\n");
1898 if ((changed & NETIF_F_NTUPLE) && ntuple &&
1899 (netdev->features & NETIF_F_HW_TC) && !(changed & NETIF_F_HW_TC)) {
1901 "Can't enable NTUPLE when TC is active, disable TC and retry\n");
1905 if ((changed & NETIF_F_HW_TC) && tc &&
1906 (netdev->features & NETIF_F_NTUPLE) && !(changed & NETIF_F_NTUPLE)) {
1908 "Can't enable TC when NTUPLE is active, disable NTUPLE and retry\n");
1915 static void otx2_reset_task(struct work_struct *work)
1917 struct otx2_nic *pf = container_of(work, struct otx2_nic, reset_task);
1919 if (!netif_running(pf->netdev))
1923 otx2_stop(pf->netdev);
1925 otx2_open(pf->netdev);
1926 netif_trans_update(pf->netdev);
1930 static int otx2_config_hw_rx_tstamp(struct otx2_nic *pfvf, bool enable)
1932 struct msg_req *req;
1935 if (pfvf->flags & OTX2_FLAG_RX_TSTAMP_ENABLED && enable)
1938 mutex_lock(&pfvf->mbox.lock);
1940 req = otx2_mbox_alloc_msg_cgx_ptp_rx_enable(&pfvf->mbox);
1942 req = otx2_mbox_alloc_msg_cgx_ptp_rx_disable(&pfvf->mbox);
1944 mutex_unlock(&pfvf->mbox.lock);
1948 err = otx2_sync_mbox_msg(&pfvf->mbox);
1950 mutex_unlock(&pfvf->mbox.lock);
1954 mutex_unlock(&pfvf->mbox.lock);
1956 pfvf->flags |= OTX2_FLAG_RX_TSTAMP_ENABLED;
1958 pfvf->flags &= ~OTX2_FLAG_RX_TSTAMP_ENABLED;
1962 static int otx2_config_hw_tx_tstamp(struct otx2_nic *pfvf, bool enable)
1964 struct msg_req *req;
1967 if (pfvf->flags & OTX2_FLAG_TX_TSTAMP_ENABLED && enable)
1970 mutex_lock(&pfvf->mbox.lock);
1972 req = otx2_mbox_alloc_msg_nix_lf_ptp_tx_enable(&pfvf->mbox);
1974 req = otx2_mbox_alloc_msg_nix_lf_ptp_tx_disable(&pfvf->mbox);
1976 mutex_unlock(&pfvf->mbox.lock);
1980 err = otx2_sync_mbox_msg(&pfvf->mbox);
1982 mutex_unlock(&pfvf->mbox.lock);
1986 mutex_unlock(&pfvf->mbox.lock);
1988 pfvf->flags |= OTX2_FLAG_TX_TSTAMP_ENABLED;
1990 pfvf->flags &= ~OTX2_FLAG_TX_TSTAMP_ENABLED;
1994 int otx2_config_hwtstamp(struct net_device *netdev, struct ifreq *ifr)
1996 struct otx2_nic *pfvf = netdev_priv(netdev);
1997 struct hwtstamp_config config;
2002 if (copy_from_user(&config, ifr->ifr_data, sizeof(config)))
2005 switch (config.tx_type) {
2006 case HWTSTAMP_TX_OFF:
2007 otx2_config_hw_tx_tstamp(pfvf, false);
2009 case HWTSTAMP_TX_ON:
2010 otx2_config_hw_tx_tstamp(pfvf, true);
2016 switch (config.rx_filter) {
2017 case HWTSTAMP_FILTER_NONE:
2018 otx2_config_hw_rx_tstamp(pfvf, false);
2020 case HWTSTAMP_FILTER_ALL:
2021 case HWTSTAMP_FILTER_SOME:
2022 case HWTSTAMP_FILTER_PTP_V1_L4_EVENT:
2023 case HWTSTAMP_FILTER_PTP_V1_L4_SYNC:
2024 case HWTSTAMP_FILTER_PTP_V1_L4_DELAY_REQ:
2025 case HWTSTAMP_FILTER_PTP_V2_L4_EVENT:
2026 case HWTSTAMP_FILTER_PTP_V2_L4_SYNC:
2027 case HWTSTAMP_FILTER_PTP_V2_L4_DELAY_REQ:
2028 case HWTSTAMP_FILTER_PTP_V2_L2_EVENT:
2029 case HWTSTAMP_FILTER_PTP_V2_L2_SYNC:
2030 case HWTSTAMP_FILTER_PTP_V2_L2_DELAY_REQ:
2031 case HWTSTAMP_FILTER_PTP_V2_EVENT:
2032 case HWTSTAMP_FILTER_PTP_V2_SYNC:
2033 case HWTSTAMP_FILTER_PTP_V2_DELAY_REQ:
2034 otx2_config_hw_rx_tstamp(pfvf, true);
2035 config.rx_filter = HWTSTAMP_FILTER_ALL;
2041 memcpy(&pfvf->tstamp, &config, sizeof(config));
2043 return copy_to_user(ifr->ifr_data, &config,
2044 sizeof(config)) ? -EFAULT : 0;
2046 EXPORT_SYMBOL(otx2_config_hwtstamp);
2048 int otx2_ioctl(struct net_device *netdev, struct ifreq *req, int cmd)
2050 struct otx2_nic *pfvf = netdev_priv(netdev);
2051 struct hwtstamp_config *cfg = &pfvf->tstamp;
2055 return otx2_config_hwtstamp(netdev, req);
2057 return copy_to_user(req->ifr_data, cfg,
2058 sizeof(*cfg)) ? -EFAULT : 0;
2063 EXPORT_SYMBOL(otx2_ioctl);
2065 static int otx2_do_set_vf_mac(struct otx2_nic *pf, int vf, const u8 *mac)
2067 struct npc_install_flow_req *req;
2070 mutex_lock(&pf->mbox.lock);
2071 req = otx2_mbox_alloc_msg_npc_install_flow(&pf->mbox);
2077 ether_addr_copy(req->packet.dmac, mac);
2078 eth_broadcast_addr((u8 *)&req->mask.dmac);
2079 req->features = BIT_ULL(NPC_DMAC);
2080 req->channel = pf->hw.rx_chan_base;
2081 req->intf = NIX_INTF_RX;
2082 req->default_rule = 1;
2085 req->op = NIX_RX_ACTION_DEFAULT;
2087 err = otx2_sync_mbox_msg(&pf->mbox);
2089 mutex_unlock(&pf->mbox.lock);
2093 static int otx2_set_vf_mac(struct net_device *netdev, int vf, u8 *mac)
2095 struct otx2_nic *pf = netdev_priv(netdev);
2096 struct pci_dev *pdev = pf->pdev;
2097 struct otx2_vf_config *config;
2100 if (!netif_running(netdev))
2103 if (vf >= pf->total_vfs)
2106 if (!is_valid_ether_addr(mac))
2109 config = &pf->vf_configs[vf];
2110 ether_addr_copy(config->mac, mac);
2112 ret = otx2_do_set_vf_mac(pf, vf, mac);
2114 dev_info(&pdev->dev,
2115 "Load/Reload VF driver\n");
2120 static int otx2_do_set_vf_vlan(struct otx2_nic *pf, int vf, u16 vlan, u8 qos,
2123 struct otx2_flow_config *flow_cfg = pf->flow_cfg;
2124 struct nix_vtag_config_rsp *vtag_rsp;
2125 struct npc_delete_flow_req *del_req;
2126 struct nix_vtag_config *vtag_req;
2127 struct npc_install_flow_req *req;
2128 struct otx2_vf_config *config;
2132 config = &pf->vf_configs[vf];
2134 if (!vlan && !config->vlan)
2137 mutex_lock(&pf->mbox.lock);
2139 /* free old tx vtag entry */
2141 vtag_req = otx2_mbox_alloc_msg_nix_vtag_cfg(&pf->mbox);
2146 vtag_req->cfg_type = 0;
2147 vtag_req->tx.free_vtag0 = 1;
2148 vtag_req->tx.vtag0_idx = config->tx_vtag_idx;
2150 err = otx2_sync_mbox_msg(&pf->mbox);
2155 if (!vlan && config->vlan) {
2157 del_req = otx2_mbox_alloc_msg_npc_delete_flow(&pf->mbox);
2162 idx = ((vf * OTX2_PER_VF_VLAN_FLOWS) + OTX2_VF_VLAN_RX_INDEX);
2164 flow_cfg->def_ent[flow_cfg->vf_vlan_offset + idx];
2165 err = otx2_sync_mbox_msg(&pf->mbox);
2170 del_req = otx2_mbox_alloc_msg_npc_delete_flow(&pf->mbox);
2175 idx = ((vf * OTX2_PER_VF_VLAN_FLOWS) + OTX2_VF_VLAN_TX_INDEX);
2177 flow_cfg->def_ent[flow_cfg->vf_vlan_offset + idx];
2178 err = otx2_sync_mbox_msg(&pf->mbox);
2184 req = otx2_mbox_alloc_msg_npc_install_flow(&pf->mbox);
2190 idx = ((vf * OTX2_PER_VF_VLAN_FLOWS) + OTX2_VF_VLAN_RX_INDEX);
2191 req->entry = flow_cfg->def_ent[flow_cfg->vf_vlan_offset + idx];
2192 req->packet.vlan_tci = htons(vlan);
2193 req->mask.vlan_tci = htons(VLAN_VID_MASK);
2194 /* af fills the destination mac addr */
2195 eth_broadcast_addr((u8 *)&req->mask.dmac);
2196 req->features = BIT_ULL(NPC_OUTER_VID) | BIT_ULL(NPC_DMAC);
2197 req->channel = pf->hw.rx_chan_base;
2198 req->intf = NIX_INTF_RX;
2200 req->op = NIX_RX_ACTION_DEFAULT;
2201 req->vtag0_valid = true;
2202 req->vtag0_type = NIX_AF_LFX_RX_VTAG_TYPE7;
2205 err = otx2_sync_mbox_msg(&pf->mbox);
2210 vtag_req = otx2_mbox_alloc_msg_nix_vtag_cfg(&pf->mbox);
2216 /* configure tx vtag params */
2217 vtag_req->vtag_size = VTAGSIZE_T4;
2218 vtag_req->cfg_type = 0; /* tx vlan cfg */
2219 vtag_req->tx.cfg_vtag0 = 1;
2220 vtag_req->tx.vtag0 = ((u64)ntohs(proto) << 16) | vlan;
2222 err = otx2_sync_mbox_msg(&pf->mbox);
2226 vtag_rsp = (struct nix_vtag_config_rsp *)otx2_mbox_get_rsp
2227 (&pf->mbox.mbox, 0, &vtag_req->hdr);
2228 if (IS_ERR(vtag_rsp)) {
2229 err = PTR_ERR(vtag_rsp);
2232 config->tx_vtag_idx = vtag_rsp->vtag0_idx;
2234 req = otx2_mbox_alloc_msg_npc_install_flow(&pf->mbox);
2240 eth_zero_addr((u8 *)&req->mask.dmac);
2241 idx = ((vf * OTX2_PER_VF_VLAN_FLOWS) + OTX2_VF_VLAN_TX_INDEX);
2242 req->entry = flow_cfg->def_ent[flow_cfg->vf_vlan_offset + idx];
2243 req->features = BIT_ULL(NPC_DMAC);
2244 req->channel = pf->hw.tx_chan_base;
2245 req->intf = NIX_INTF_TX;
2247 req->op = NIX_TX_ACTIONOP_UCAST_DEFAULT;
2248 req->vtag0_def = vtag_rsp->vtag0_idx;
2249 req->vtag0_op = VTAG_INSERT;
2252 err = otx2_sync_mbox_msg(&pf->mbox);
2254 config->vlan = vlan;
2255 mutex_unlock(&pf->mbox.lock);
2259 static int otx2_set_vf_vlan(struct net_device *netdev, int vf, u16 vlan, u8 qos,
2262 struct otx2_nic *pf = netdev_priv(netdev);
2263 struct pci_dev *pdev = pf->pdev;
2265 if (!netif_running(netdev))
2268 if (vf >= pci_num_vf(pdev))
2271 /* qos is currently unsupported */
2272 if (vlan >= VLAN_N_VID || qos)
2275 if (proto != htons(ETH_P_8021Q))
2276 return -EPROTONOSUPPORT;
2278 if (!(pf->flags & OTX2_FLAG_VF_VLAN_SUPPORT))
2281 return otx2_do_set_vf_vlan(pf, vf, vlan, qos, proto);
2284 static int otx2_get_vf_config(struct net_device *netdev, int vf,
2285 struct ifla_vf_info *ivi)
2287 struct otx2_nic *pf = netdev_priv(netdev);
2288 struct pci_dev *pdev = pf->pdev;
2289 struct otx2_vf_config *config;
2291 if (!netif_running(netdev))
2294 if (vf >= pci_num_vf(pdev))
2297 config = &pf->vf_configs[vf];
2299 ether_addr_copy(ivi->mac, config->mac);
2300 ivi->vlan = config->vlan;
2301 ivi->trusted = config->trusted;
2306 static int otx2_xdp_xmit_tx(struct otx2_nic *pf, struct xdp_frame *xdpf,
2313 dma_addr = otx2_dma_map_page(pf, virt_to_page(xdpf->data),
2314 offset_in_page(xdpf->data), xdpf->len,
2316 if (dma_mapping_error(pf->dev, dma_addr))
2319 err = otx2_xdp_sq_append_pkt(pf, dma_addr, xdpf->len, qidx);
2321 otx2_dma_unmap_page(pf, dma_addr, xdpf->len, DMA_TO_DEVICE);
2322 page = virt_to_page(xdpf->data);
2329 static int otx2_xdp_xmit(struct net_device *netdev, int n,
2330 struct xdp_frame **frames, u32 flags)
2332 struct otx2_nic *pf = netdev_priv(netdev);
2333 int qidx = smp_processor_id();
2334 struct otx2_snd_queue *sq;
2337 if (!netif_running(netdev))
2340 qidx += pf->hw.tx_queues;
2341 sq = pf->xdp_prog ? &pf->qset.sq[qidx] : NULL;
2343 /* Abort xmit if xdp queue is not */
2347 if (unlikely(flags & ~XDP_XMIT_FLAGS_MASK))
2350 for (i = 0; i < n; i++) {
2351 struct xdp_frame *xdpf = frames[i];
2354 err = otx2_xdp_xmit_tx(pf, xdpf, qidx);
2361 static int otx2_xdp_setup(struct otx2_nic *pf, struct bpf_prog *prog)
2363 struct net_device *dev = pf->netdev;
2364 bool if_up = netif_running(pf->netdev);
2365 struct bpf_prog *old_prog;
2367 if (prog && dev->mtu > MAX_XDP_MTU) {
2368 netdev_warn(dev, "Jumbo frames not yet supported with XDP\n");
2373 otx2_stop(pf->netdev);
2375 old_prog = xchg(&pf->xdp_prog, prog);
2378 bpf_prog_put(old_prog);
2381 bpf_prog_add(pf->xdp_prog, pf->hw.rx_queues - 1);
2383 /* Network stack and XDP shared same rx queues.
2384 * Use separate tx queues for XDP and network stack.
2387 pf->hw.xdp_queues = pf->hw.rx_queues;
2389 pf->hw.xdp_queues = 0;
2391 pf->hw.tot_tx_queues += pf->hw.xdp_queues;
2394 otx2_open(pf->netdev);
2399 static int otx2_xdp(struct net_device *netdev, struct netdev_bpf *xdp)
2401 struct otx2_nic *pf = netdev_priv(netdev);
2403 switch (xdp->command) {
2404 case XDP_SETUP_PROG:
2405 return otx2_xdp_setup(pf, xdp->prog);
2411 static int otx2_set_vf_permissions(struct otx2_nic *pf, int vf,
2414 struct set_vf_perm *req;
2417 mutex_lock(&pf->mbox.lock);
2418 req = otx2_mbox_alloc_msg_set_vf_perm(&pf->mbox);
2424 /* Let AF reset VF permissions as sriov is disabled */
2425 if (req_perm == OTX2_RESET_VF_PERM) {
2426 req->flags |= RESET_VF_PERM;
2427 } else if (req_perm == OTX2_TRUSTED_VF) {
2428 if (pf->vf_configs[vf].trusted)
2429 req->flags |= VF_TRUSTED;
2433 rc = otx2_sync_mbox_msg(&pf->mbox);
2435 mutex_unlock(&pf->mbox.lock);
2439 static int otx2_ndo_set_vf_trust(struct net_device *netdev, int vf,
2442 struct otx2_nic *pf = netdev_priv(netdev);
2443 struct pci_dev *pdev = pf->pdev;
2446 if (vf >= pci_num_vf(pdev))
2449 if (pf->vf_configs[vf].trusted == enable)
2452 pf->vf_configs[vf].trusted = enable;
2453 rc = otx2_set_vf_permissions(pf, vf, OTX2_TRUSTED_VF);
2456 pf->vf_configs[vf].trusted = !enable;
2458 netdev_info(pf->netdev, "VF %d is %strusted\n",
2459 vf, enable ? "" : "not ");
2463 static const struct net_device_ops otx2_netdev_ops = {
2464 .ndo_open = otx2_open,
2465 .ndo_stop = otx2_stop,
2466 .ndo_start_xmit = otx2_xmit,
2467 .ndo_fix_features = otx2_fix_features,
2468 .ndo_set_mac_address = otx2_set_mac_address,
2469 .ndo_change_mtu = otx2_change_mtu,
2470 .ndo_set_rx_mode = otx2_set_rx_mode,
2471 .ndo_set_features = otx2_set_features,
2472 .ndo_tx_timeout = otx2_tx_timeout,
2473 .ndo_get_stats64 = otx2_get_stats64,
2474 .ndo_eth_ioctl = otx2_ioctl,
2475 .ndo_set_vf_mac = otx2_set_vf_mac,
2476 .ndo_set_vf_vlan = otx2_set_vf_vlan,
2477 .ndo_get_vf_config = otx2_get_vf_config,
2478 .ndo_bpf = otx2_xdp,
2479 .ndo_xdp_xmit = otx2_xdp_xmit,
2480 .ndo_setup_tc = otx2_setup_tc,
2481 .ndo_set_vf_trust = otx2_ndo_set_vf_trust,
2484 static int otx2_wq_init(struct otx2_nic *pf)
2486 pf->otx2_wq = create_singlethread_workqueue("otx2_wq");
2490 INIT_WORK(&pf->rx_mode_work, otx2_rx_mode_wrk_handler);
2491 INIT_WORK(&pf->reset_task, otx2_reset_task);
2495 static int otx2_check_pf_usable(struct otx2_nic *nic)
2499 rev = otx2_read64(nic, RVU_PF_BLOCK_ADDRX_DISC(BLKADDR_RVUM));
2500 rev = (rev >> 12) & 0xFF;
2501 /* Check if AF has setup revision for RVUM block,
2502 * otherwise this driver probe should be deferred
2503 * until AF driver comes up.
2507 "AF is not initialized, deferring probe\n");
2508 return -EPROBE_DEFER;
2513 static int otx2_realloc_msix_vectors(struct otx2_nic *pf)
2515 struct otx2_hw *hw = &pf->hw;
2518 /* NPA interrupts are inot registered, so alloc only
2519 * upto NIX vector offset.
2521 num_vec = hw->nix_msixoff;
2522 num_vec += NIX_LF_CINT_VEC_START + hw->max_queues;
2524 otx2_disable_mbox_intr(pf);
2525 pci_free_irq_vectors(hw->pdev);
2526 err = pci_alloc_irq_vectors(hw->pdev, num_vec, num_vec, PCI_IRQ_MSIX);
2528 dev_err(pf->dev, "%s: Failed to realloc %d IRQ vectors\n",
2533 return otx2_register_mbox_intr(pf, false);
2536 static int otx2_sriov_vfcfg_init(struct otx2_nic *pf)
2540 pf->vf_configs = devm_kcalloc(pf->dev, pf->total_vfs,
2541 sizeof(struct otx2_vf_config),
2543 if (!pf->vf_configs)
2546 for (i = 0; i < pf->total_vfs; i++) {
2547 pf->vf_configs[i].pf = pf;
2548 pf->vf_configs[i].intf_down = true;
2549 pf->vf_configs[i].trusted = false;
2550 INIT_DELAYED_WORK(&pf->vf_configs[i].link_event_work,
2551 otx2_vf_link_event_task);
2557 static void otx2_sriov_vfcfg_cleanup(struct otx2_nic *pf)
2561 if (!pf->vf_configs)
2564 for (i = 0; i < pf->total_vfs; i++) {
2565 cancel_delayed_work_sync(&pf->vf_configs[i].link_event_work);
2566 otx2_set_vf_permissions(pf, i, OTX2_RESET_VF_PERM);
2570 static int otx2_probe(struct pci_dev *pdev, const struct pci_device_id *id)
2572 struct device *dev = &pdev->dev;
2573 struct net_device *netdev;
2574 struct otx2_nic *pf;
2579 err = pcim_enable_device(pdev);
2581 dev_err(dev, "Failed to enable PCI device\n");
2585 err = pci_request_regions(pdev, DRV_NAME);
2587 dev_err(dev, "PCI request regions failed 0x%x\n", err);
2591 err = dma_set_mask_and_coherent(dev, DMA_BIT_MASK(48));
2593 dev_err(dev, "DMA mask config failed, abort\n");
2594 goto err_release_regions;
2597 pci_set_master(pdev);
2599 /* Set number of queues */
2600 qcount = min_t(int, num_online_cpus(), OTX2_MAX_CQ_CNT);
2602 netdev = alloc_etherdev_mqs(sizeof(*pf), qcount, qcount);
2605 goto err_release_regions;
2608 pci_set_drvdata(pdev, netdev);
2609 SET_NETDEV_DEV(netdev, &pdev->dev);
2610 pf = netdev_priv(netdev);
2611 pf->netdev = netdev;
2614 pf->total_vfs = pci_sriov_get_totalvfs(pdev);
2615 pf->flags |= OTX2_FLAG_INTF_DOWN;
2619 hw->rx_queues = qcount;
2620 hw->tx_queues = qcount;
2621 hw->tot_tx_queues = qcount;
2622 hw->max_queues = qcount;
2624 num_vec = pci_msix_vec_count(pdev);
2625 hw->irq_name = devm_kmalloc_array(&hw->pdev->dev, num_vec, NAME_SIZE,
2627 if (!hw->irq_name) {
2629 goto err_free_netdev;
2632 hw->affinity_mask = devm_kcalloc(&hw->pdev->dev, num_vec,
2633 sizeof(cpumask_var_t), GFP_KERNEL);
2634 if (!hw->affinity_mask) {
2636 goto err_free_netdev;
2640 pf->reg_base = pcim_iomap(pdev, PCI_CFG_REG_BAR_NUM, 0);
2641 if (!pf->reg_base) {
2642 dev_err(dev, "Unable to map physical function CSRs, aborting\n");
2644 goto err_free_netdev;
2647 err = otx2_check_pf_usable(pf);
2649 goto err_free_netdev;
2651 err = pci_alloc_irq_vectors(hw->pdev, RVU_PF_INT_VEC_CNT,
2652 RVU_PF_INT_VEC_CNT, PCI_IRQ_MSIX);
2654 dev_err(dev, "%s: Failed to alloc %d IRQ vectors\n",
2656 goto err_free_netdev;
2659 otx2_setup_dev_hw_settings(pf);
2661 /* Init PF <=> AF mailbox stuff */
2662 err = otx2_pfaf_mbox_init(pf);
2664 goto err_free_irq_vectors;
2666 /* Register mailbox interrupt */
2667 err = otx2_register_mbox_intr(pf, true);
2669 goto err_mbox_destroy;
2671 /* Request AF to attach NPA and NIX LFs to this PF.
2672 * NIX and NPA LFs are needed for this PF to function as a NIC.
2674 err = otx2_attach_npa_nix(pf);
2676 goto err_disable_mbox_intr;
2678 err = otx2_realloc_msix_vectors(pf);
2680 goto err_detach_rsrc;
2682 err = otx2_set_real_num_queues(netdev, hw->tx_queues, hw->rx_queues);
2684 goto err_detach_rsrc;
2686 err = cn10k_lmtst_init(pf);
2688 goto err_detach_rsrc;
2690 /* Assign default mac address */
2691 otx2_get_mac_from_af(netdev);
2693 /* Don't check for error. Proceed without ptp */
2696 /* NPA's pool is a stack to which SW frees buffer pointers via Aura.
2697 * HW allocates buffer pointer from stack and uses it for DMA'ing
2698 * ingress packet. In some scenarios HW can free back allocated buffer
2699 * pointers to pool. This makes it impossible for SW to maintain a
2700 * parallel list where physical addresses of buffer pointers (IOVAs)
2701 * given to HW can be saved for later reference.
2703 * So the only way to convert Rx packet's buffer address is to use
2704 * IOMMU's iova_to_phys() handler which translates the address by
2705 * walking through the translation tables.
2707 pf->iommu_domain = iommu_get_domain_for_dev(dev);
2709 netdev->hw_features = (NETIF_F_RXCSUM | NETIF_F_IP_CSUM |
2710 NETIF_F_IPV6_CSUM | NETIF_F_RXHASH |
2711 NETIF_F_SG | NETIF_F_TSO | NETIF_F_TSO6 |
2712 NETIF_F_GSO_UDP_L4);
2713 netdev->features |= netdev->hw_features;
2715 err = otx2_mcam_flow_init(pf);
2717 goto err_ptp_destroy;
2719 if (pf->flags & OTX2_FLAG_NTUPLE_SUPPORT)
2720 netdev->hw_features |= NETIF_F_NTUPLE;
2722 if (pf->flags & OTX2_FLAG_UCAST_FLTR_SUPPORT)
2723 netdev->priv_flags |= IFF_UNICAST_FLT;
2725 /* Support TSO on tag interface */
2726 netdev->vlan_features |= netdev->features;
2727 netdev->hw_features |= NETIF_F_HW_VLAN_CTAG_TX |
2728 NETIF_F_HW_VLAN_STAG_TX;
2729 if (pf->flags & OTX2_FLAG_RX_VLAN_SUPPORT)
2730 netdev->hw_features |= NETIF_F_HW_VLAN_CTAG_RX |
2731 NETIF_F_HW_VLAN_STAG_RX;
2732 netdev->features |= netdev->hw_features;
2734 /* HW supports tc offload but mutually exclusive with n-tuple filters */
2735 if (pf->flags & OTX2_FLAG_TC_FLOWER_SUPPORT)
2736 netdev->hw_features |= NETIF_F_HW_TC;
2738 netdev->hw_features |= NETIF_F_LOOPBACK | NETIF_F_RXALL;
2740 netif_set_gso_max_segs(netdev, OTX2_MAX_GSO_SEGS);
2741 netdev->watchdog_timeo = OTX2_TX_TIMEOUT;
2743 netdev->netdev_ops = &otx2_netdev_ops;
2745 netdev->min_mtu = OTX2_MIN_MTU;
2746 netdev->max_mtu = otx2_get_max_mtu(pf);
2748 err = register_netdev(netdev);
2750 dev_err(dev, "Failed to register netdevice\n");
2751 goto err_del_mcam_entries;
2754 err = otx2_wq_init(pf);
2756 goto err_unreg_netdev;
2758 otx2_set_ethtool_ops(netdev);
2760 err = otx2_init_tc(pf);
2762 goto err_mcam_flow_del;
2764 err = otx2_register_dl(pf);
2766 goto err_mcam_flow_del;
2768 /* Initialize SR-IOV resources */
2769 err = otx2_sriov_vfcfg_init(pf);
2771 goto err_pf_sriov_init;
2773 /* Enable link notifications */
2774 otx2_cgx_config_linkevents(pf, true);
2776 /* Enable pause frames by default */
2777 pf->flags |= OTX2_FLAG_RX_PAUSE_ENABLED;
2778 pf->flags |= OTX2_FLAG_TX_PAUSE_ENABLED;
2783 otx2_shutdown_tc(pf);
2785 otx2_mcam_flow_del(pf);
2787 unregister_netdev(netdev);
2788 err_del_mcam_entries:
2789 otx2_mcam_flow_del(pf);
2791 otx2_ptp_destroy(pf);
2793 if (pf->hw.lmt_info)
2794 free_percpu(pf->hw.lmt_info);
2795 if (test_bit(CN10K_LMTST, &pf->hw.cap_flag))
2796 qmem_free(pf->dev, pf->dync_lmt);
2797 otx2_detach_resources(&pf->mbox);
2798 err_disable_mbox_intr:
2799 otx2_disable_mbox_intr(pf);
2801 otx2_pfaf_mbox_destroy(pf);
2802 err_free_irq_vectors:
2803 pci_free_irq_vectors(hw->pdev);
2805 pci_set_drvdata(pdev, NULL);
2806 free_netdev(netdev);
2807 err_release_regions:
2808 pci_release_regions(pdev);
2812 static void otx2_vf_link_event_task(struct work_struct *work)
2814 struct otx2_vf_config *config;
2815 struct cgx_link_info_msg *req;
2816 struct mbox_msghdr *msghdr;
2817 struct otx2_nic *pf;
2820 config = container_of(work, struct otx2_vf_config,
2821 link_event_work.work);
2822 vf_idx = config - config->pf->vf_configs;
2825 msghdr = otx2_mbox_alloc_msg_rsp(&pf->mbox_pfvf[0].mbox_up, vf_idx,
2826 sizeof(*req), sizeof(struct msg_rsp));
2828 dev_err(pf->dev, "Failed to create VF%d link event\n", vf_idx);
2832 req = (struct cgx_link_info_msg *)msghdr;
2833 req->hdr.id = MBOX_MSG_CGX_LINK_EVENT;
2834 req->hdr.sig = OTX2_MBOX_REQ_SIG;
2835 memcpy(&req->link_info, &pf->linfo, sizeof(req->link_info));
2837 otx2_sync_mbox_up_msg(&pf->mbox_pfvf[0], vf_idx);
2840 static int otx2_sriov_enable(struct pci_dev *pdev, int numvfs)
2842 struct net_device *netdev = pci_get_drvdata(pdev);
2843 struct otx2_nic *pf = netdev_priv(netdev);
2846 /* Init PF <=> VF mailbox stuff */
2847 ret = otx2_pfvf_mbox_init(pf, numvfs);
2851 ret = otx2_register_pfvf_mbox_intr(pf, numvfs);
2855 ret = otx2_pf_flr_init(pf, numvfs);
2859 ret = otx2_register_flr_me_intr(pf, numvfs);
2863 ret = pci_enable_sriov(pdev, numvfs);
2869 otx2_disable_flr_me_intr(pf);
2871 otx2_flr_wq_destroy(pf);
2873 otx2_disable_pfvf_mbox_intr(pf, numvfs);
2875 otx2_pfvf_mbox_destroy(pf);
2879 static int otx2_sriov_disable(struct pci_dev *pdev)
2881 struct net_device *netdev = pci_get_drvdata(pdev);
2882 struct otx2_nic *pf = netdev_priv(netdev);
2883 int numvfs = pci_num_vf(pdev);
2888 pci_disable_sriov(pdev);
2890 otx2_disable_flr_me_intr(pf);
2891 otx2_flr_wq_destroy(pf);
2892 otx2_disable_pfvf_mbox_intr(pf, numvfs);
2893 otx2_pfvf_mbox_destroy(pf);
2898 static int otx2_sriov_configure(struct pci_dev *pdev, int numvfs)
2901 return otx2_sriov_disable(pdev);
2903 return otx2_sriov_enable(pdev, numvfs);
2906 static void otx2_remove(struct pci_dev *pdev)
2908 struct net_device *netdev = pci_get_drvdata(pdev);
2909 struct otx2_nic *pf;
2914 pf = netdev_priv(netdev);
2916 pf->flags |= OTX2_FLAG_PF_SHUTDOWN;
2918 if (pf->flags & OTX2_FLAG_TX_TSTAMP_ENABLED)
2919 otx2_config_hw_tx_tstamp(pf, false);
2920 if (pf->flags & OTX2_FLAG_RX_TSTAMP_ENABLED)
2921 otx2_config_hw_rx_tstamp(pf, false);
2923 cancel_work_sync(&pf->reset_task);
2924 /* Disable link notifications */
2925 otx2_cgx_config_linkevents(pf, false);
2927 otx2_unregister_dl(pf);
2928 unregister_netdev(netdev);
2929 otx2_sriov_disable(pf->pdev);
2930 otx2_sriov_vfcfg_cleanup(pf);
2932 destroy_workqueue(pf->otx2_wq);
2934 otx2_ptp_destroy(pf);
2935 otx2_mcam_flow_del(pf);
2936 otx2_shutdown_tc(pf);
2937 otx2_detach_resources(&pf->mbox);
2938 if (pf->hw.lmt_info)
2939 free_percpu(pf->hw.lmt_info);
2940 if (test_bit(CN10K_LMTST, &pf->hw.cap_flag))
2941 qmem_free(pf->dev, pf->dync_lmt);
2942 otx2_disable_mbox_intr(pf);
2943 otx2_pfaf_mbox_destroy(pf);
2944 pci_free_irq_vectors(pf->pdev);
2945 pci_set_drvdata(pdev, NULL);
2946 free_netdev(netdev);
2948 pci_release_regions(pdev);
2951 static struct pci_driver otx2_pf_driver = {
2953 .id_table = otx2_pf_id_table,
2954 .probe = otx2_probe,
2955 .shutdown = otx2_remove,
2956 .remove = otx2_remove,
2957 .sriov_configure = otx2_sriov_configure
2960 static int __init otx2_rvupf_init_module(void)
2962 pr_info("%s: %s\n", DRV_NAME, DRV_STRING);
2964 return pci_register_driver(&otx2_pf_driver);
2967 static void __exit otx2_rvupf_cleanup_module(void)
2969 pci_unregister_driver(&otx2_pf_driver);
2972 module_init(otx2_rvupf_init_module);
2973 module_exit(otx2_rvupf_cleanup_module);