1 /* SPDX-License-Identifier: GPL-2.0 */
2 /* Marvell OcteonTx2 RVU Ethernet driver
4 * Copyright (C) 2020 Marvell International Ltd.
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2 as
8 * published by the Free Software Foundation.
14 #include <linux/ethtool.h>
15 #include <linux/pci.h>
16 #include <linux/iommu.h>
17 #include <linux/net_tstamp.h>
18 #include <linux/ptp_clock_kernel.h>
19 #include <linux/timecounter.h>
20 #include <linux/soc/marvell/octeontx2/asm.h>
21 #include <net/pkt_cls.h>
26 #include "otx2_txrx.h"
27 #include <rvu_trace.h>
30 #define PCI_DEVID_OCTEONTX2_RVU_PF 0xA063
31 #define PCI_DEVID_OCTEONTX2_RVU_VF 0xA064
32 #define PCI_DEVID_OCTEONTX2_RVU_AFVF 0xA0F8
34 #define PCI_SUBSYS_DEVID_96XX_RVU_PFVF 0xB200
37 #define PCI_CFG_REG_BAR_NUM 2
38 #define PCI_MBOX_BAR_NUM 4
42 enum arua_mapped_qtypes {
47 /* NIX LF interrupts range*/
48 #define NIX_LF_QINT_VEC_START 0x00
49 #define NIX_LF_CINT_VEC_START 0x40
50 #define NIX_LF_GINT_VEC 0x80
51 #define NIX_LF_ERR_VEC 0x81
52 #define NIX_LF_POISON_VEC 0x82
54 /* Send skid of 2000 packets required for CQ size of 4K CQEs. */
55 #define SEND_CQ_SKID 2000
57 /* RSS configuration */
59 u8 ind_tbl[MAX_RSS_INDIR_TBL_SIZE];
62 struct otx2_rss_info {
66 #define RSS_HASH_KEY_SIZE 44 /* 352 bit key */
67 u8 key[RSS_HASH_KEY_SIZE];
68 struct otx2_rss_ctx *rss_ctx[MAX_RSS_GROUPS];
71 /* NIX (or NPC) RX errors */
82 NPC_ERRLVL_NIX = 0x0F,
85 enum otx2_errcodes_re {
86 /* NPC_ERRLVL_RE errcodes */
88 ERRCODE_FCS_RCV = 0x8,
89 ERRCODE_UNDERSIZE = 0x10,
90 ERRCODE_OVERSIZE = 0x11,
91 ERRCODE_OL2_LEN_MISMATCH = 0x12,
92 /* NPC_ERRLVL_NIX errcodes */
93 ERRCODE_OL3_LEN = 0x10,
94 ERRCODE_OL4_LEN = 0x11,
95 ERRCODE_OL4_CSUM = 0x12,
96 ERRCODE_IL3_LEN = 0x20,
97 ERRCODE_IL4_LEN = 0x21,
98 ERRCODE_IL4_CSUM = 0x22,
102 enum nix_stat_lf_tx {
112 enum nix_stat_lf_rx {
123 RX_DRP_L3BCAST = 0xa,
124 RX_DRP_L3MCAST = 0xb,
128 struct otx2_dev_stats {
144 /* Driver counted stats */
145 struct otx2_drv_stats {
146 atomic_t rx_fcs_errs;
147 atomic_t rx_oversize_errs;
148 atomic_t rx_undersize_errs;
149 atomic_t rx_csum_errs;
150 atomic_t rx_len_errs;
151 atomic_t rx_other_errs;
155 struct otx2_mbox mbox;
156 struct work_struct mbox_wrk;
157 struct otx2_mbox mbox_up;
158 struct work_struct mbox_up_wrk;
159 struct otx2_nic *pfvf;
160 void *bbuf_base; /* Bounce buffer for mbox memory */
161 struct mutex lock; /* serialize mailbox access */
162 int num_msgs; /* mbox number of messages */
163 int up_num_msgs; /* mbox_up number of messages */
167 struct pci_dev *pdev;
168 struct otx2_rss_info rss_info;
177 u32 stack_pg_ptrs; /* No of ptrs per stack page */
178 u32 stack_pg_bytes; /* Size of stack page */
182 u16 txschq_list[NIX_TXSCH_LVL_CNT][MAX_TXSCHQ_PER_FUNC];
183 u16 matchall_ipolicer;
185 /* HW settings, coalescing etc */
200 u8 cint_cnt; /* CQ interrupt count */
201 u16 npa_msixoff; /* Offset of NPA vectors */
202 u16 nix_msixoff; /* Offset of NIX vectors */
204 cpumask_var_t *affinity_mask;
207 struct otx2_dev_stats dev_stats;
208 struct otx2_drv_stats drv_stats;
209 u64 cgx_rx_stats[CGX_RX_STATS_COUNT];
210 u64 cgx_tx_stats[CGX_TX_STATS_COUNT];
211 u64 cgx_fec_corr_blks;
212 u64 cgx_fec_uncorr_blks;
213 u8 cgx_links; /* No. of CGX links present in HW */
214 u8 lbk_links; /* No. of LBK links present in HW */
217 #define CN10K_LMTST 2
218 unsigned long cap_flag;
220 #define LMT_LINE_SIZE 128
221 #define NIX_LMTID_BASE 72 /* RX + TX + XDP */
222 void __iomem *lmt_base;
232 struct otx2_vf_config {
234 struct delayed_work link_event_work;
235 bool intf_down; /* interface was either configured or not */
243 struct work_struct work;
248 struct delayed_work pool_refill_work;
253 struct ptp_clock_info ptp_info;
254 struct ptp_clock *ptp_clock;
255 struct otx2_nic *nic;
257 struct cyclecounter cycle_counter;
258 struct timecounter time_counter;
261 #define OTX2_HW_TIMESTAMP_LEN 8
263 struct otx2_mac_table {
269 struct otx2_flow_config {
270 u16 entry[NPC_MAX_NONCONTIG_ENTRIES];
274 #define OTX2_DEFAULT_FLOWCOUNT 16
275 #define OTX2_MAX_UNICAST_FLOWS 8
276 #define OTX2_MAX_VLAN_FLOWS 1
277 #define OTX2_MAX_TC_FLOWS OTX2_DEFAULT_FLOWCOUNT
278 #define OTX2_MCAM_COUNT (OTX2_DEFAULT_FLOWCOUNT + \
279 OTX2_MAX_UNICAST_FLOWS + \
285 #define OTX2_PER_VF_VLAN_FLOWS 2 /* Rx + Tx per VF */
286 #define OTX2_VF_VLAN_RX_INDEX 0
287 #define OTX2_VF_VLAN_TX_INDEX 1
288 u16 tc_flower_offset;
289 u16 ntuple_max_flows;
291 struct list_head flow_list;
294 struct otx2_tc_info {
295 /* hash table to store TC offloaded flows */
296 struct rhashtable flow_table;
297 struct rhashtable_params flow_ht_params;
298 DECLARE_BITMAP(tc_entries_bitmap, OTX2_MAX_TC_FLOWS);
299 unsigned long num_entries;
303 int (*sq_aq_init)(void *dev, u16 qidx, u16 sqb_aura);
304 void (*sqe_flush)(void *dev, struct otx2_snd_queue *sq,
306 void (*refill_pool_ptrs)(void *dev, struct otx2_cq_queue *cq);
307 void (*aura_freeptr)(void *dev, int aura, u64 buf);
311 void __iomem *reg_base;
312 struct net_device *netdev;
313 struct dev_hw_ops *hw_ops;
316 u16 rbsize; /* Receive buffer size */
318 #define OTX2_FLAG_RX_TSTAMP_ENABLED BIT_ULL(0)
319 #define OTX2_FLAG_TX_TSTAMP_ENABLED BIT_ULL(1)
320 #define OTX2_FLAG_INTF_DOWN BIT_ULL(2)
321 #define OTX2_FLAG_MCAM_ENTRIES_ALLOC BIT_ULL(3)
322 #define OTX2_FLAG_NTUPLE_SUPPORT BIT_ULL(4)
323 #define OTX2_FLAG_UCAST_FLTR_SUPPORT BIT_ULL(5)
324 #define OTX2_FLAG_RX_VLAN_SUPPORT BIT_ULL(6)
325 #define OTX2_FLAG_VF_VLAN_SUPPORT BIT_ULL(7)
326 #define OTX2_FLAG_PF_SHUTDOWN BIT_ULL(8)
327 #define OTX2_FLAG_RX_PAUSE_ENABLED BIT_ULL(9)
328 #define OTX2_FLAG_TX_PAUSE_ENABLED BIT_ULL(10)
329 #define OTX2_FLAG_TC_FLOWER_SUPPORT BIT_ULL(11)
330 #define OTX2_FLAG_TC_MATCHALL_EGRESS_ENABLED BIT_ULL(12)
331 #define OTX2_FLAG_TC_MATCHALL_INGRESS_ENABLED BIT_ULL(13)
334 struct otx2_qset qset;
336 struct pci_dev *pdev;
341 struct mbox *mbox_pfvf;
342 struct workqueue_struct *mbox_wq;
343 struct workqueue_struct *mbox_pfvf_wq;
346 u16 pcifunc; /* RVU PF_FUNC */
347 u16 bpid[NIX_MAX_BPID_CHAN];
348 struct otx2_vf_config *vf_configs;
349 struct cgx_link_user_info linfo;
352 struct work_struct reset_task;
353 struct workqueue_struct *flr_wq;
354 struct flr_work *flr_wrk;
355 struct refill_work *refill_wrk;
356 struct workqueue_struct *otx2_wq;
357 struct work_struct rx_mode_work;
358 struct otx2_mac_table *mac_table;
363 /* Block address of NIX either BLKADDR_NIX0 or BLKADDR_NIX1 */
365 /* LMTST Lines info */
370 struct otx2_ptp *ptp;
371 struct hwtstamp_config tstamp;
373 struct otx2_flow_config *flow_cfg;
374 struct otx2_tc_info tc_info;
375 unsigned long rq_bmap;
378 static inline bool is_otx2_lbkvf(struct pci_dev *pdev)
380 return pdev->device == PCI_DEVID_OCTEONTX2_RVU_AFVF;
383 static inline bool is_96xx_A0(struct pci_dev *pdev)
385 return (pdev->revision == 0x00) &&
386 (pdev->subsystem_device == PCI_SUBSYS_DEVID_96XX_RVU_PFVF);
389 static inline bool is_96xx_B0(struct pci_dev *pdev)
391 return (pdev->revision == 0x01) &&
392 (pdev->subsystem_device == PCI_SUBSYS_DEVID_96XX_RVU_PFVF);
395 /* REVID for PCIe devices.
396 * Bits 0..1: minor pass, bit 3..2: major pass
399 #define PCI_REVISION_ID_96XX 0x00
400 #define PCI_REVISION_ID_95XX 0x10
401 #define PCI_REVISION_ID_LOKI 0x20
402 #define PCI_REVISION_ID_98XX 0x30
403 #define PCI_REVISION_ID_95XXMM 0x40
405 static inline bool is_dev_otx2(struct pci_dev *pdev)
407 u8 midr = pdev->revision & 0xF0;
409 return (midr == PCI_REVISION_ID_96XX || midr == PCI_REVISION_ID_95XX ||
410 midr == PCI_REVISION_ID_LOKI || midr == PCI_REVISION_ID_98XX ||
411 midr == PCI_REVISION_ID_95XXMM);
414 static inline void otx2_setup_dev_hw_settings(struct otx2_nic *pfvf)
416 struct otx2_hw *hw = &pfvf->hw;
418 pfvf->hw.cq_time_wait = CQ_TIMER_THRESH_DEFAULT;
419 pfvf->hw.cq_ecount_wait = CQ_CQE_THRESH_DEFAULT;
420 pfvf->hw.cq_qcount_wait = CQ_QCOUNT_DEFAULT;
422 __set_bit(HW_TSO, &hw->cap_flag);
424 if (is_96xx_A0(pfvf->pdev)) {
425 __clear_bit(HW_TSO, &hw->cap_flag);
427 /* Time based irq coalescing is not supported */
428 pfvf->hw.cq_qcount_wait = 0x0;
430 /* Due to HW issue previous silicons required minimum
431 * 600 unused CQE to avoid CQ overflow.
433 pfvf->hw.rq_skid = 600;
434 pfvf->qset.rqe_cnt = Q_COUNT(Q_SIZE_1K);
436 if (is_96xx_B0(pfvf->pdev))
437 __clear_bit(HW_TSO, &hw->cap_flag);
439 if (!is_dev_otx2(pfvf->pdev)) {
440 __set_bit(CN10K_MBOX, &hw->cap_flag);
441 __set_bit(CN10K_LMTST, &hw->cap_flag);
445 /* Register read/write APIs */
446 static inline void __iomem *otx2_get_regaddr(struct otx2_nic *nic, u64 offset)
450 switch ((offset >> RVU_FUNC_BLKADDR_SHIFT) & RVU_FUNC_BLKADDR_MASK) {
452 blkaddr = nic->nix_blkaddr;
455 blkaddr = BLKADDR_NPA;
458 blkaddr = BLKADDR_RVUM;
462 offset &= ~(RVU_FUNC_BLKADDR_MASK << RVU_FUNC_BLKADDR_SHIFT);
463 offset |= (blkaddr << RVU_FUNC_BLKADDR_SHIFT);
465 return nic->reg_base + offset;
468 static inline void otx2_write64(struct otx2_nic *nic, u64 offset, u64 val)
470 void __iomem *addr = otx2_get_regaddr(nic, offset);
475 static inline u64 otx2_read64(struct otx2_nic *nic, u64 offset)
477 void __iomem *addr = otx2_get_regaddr(nic, offset);
482 /* Mbox bounce buffer APIs */
483 static inline int otx2_mbox_bbuf_init(struct mbox *mbox, struct pci_dev *pdev)
485 struct otx2_mbox *otx2_mbox;
486 struct otx2_mbox_dev *mdev;
488 mbox->bbuf_base = devm_kmalloc(&pdev->dev, MBOX_SIZE, GFP_KERNEL);
489 if (!mbox->bbuf_base)
492 /* Overwrite mbox mbase to point to bounce buffer, so that PF/VF
493 * prepare all mbox messages in bounce buffer instead of directly
496 otx2_mbox = &mbox->mbox;
497 mdev = &otx2_mbox->dev[0];
498 mdev->mbase = mbox->bbuf_base;
500 otx2_mbox = &mbox->mbox_up;
501 mdev = &otx2_mbox->dev[0];
502 mdev->mbase = mbox->bbuf_base;
506 static inline void otx2_sync_mbox_bbuf(struct otx2_mbox *mbox, int devid)
508 u16 msgs_offset = ALIGN(sizeof(struct mbox_hdr), MBOX_MSG_ALIGN);
509 void *hw_mbase = mbox->hwbase + (devid * MBOX_SIZE);
510 struct otx2_mbox_dev *mdev = &mbox->dev[devid];
511 struct mbox_hdr *hdr;
514 if (mdev->mbase == hw_mbase)
517 hdr = hw_mbase + mbox->rx_start;
518 msg_size = hdr->msg_size;
520 if (msg_size > mbox->rx_size - msgs_offset)
521 msg_size = mbox->rx_size - msgs_offset;
523 /* Copy mbox messages from mbox memory to bounce buffer */
524 memcpy(mdev->mbase + mbox->rx_start,
525 hw_mbase + mbox->rx_start, msg_size + msgs_offset);
528 /* With the absence of API for 128-bit IO memory access for arm64,
529 * implement required operations at place.
531 #if defined(CONFIG_ARM64)
532 static inline void otx2_write128(u64 lo, u64 hi, void __iomem *addr)
534 __asm__ volatile("stp %x[x0], %x[x1], [%x[p1],#0]!"
535 ::[x0]"r"(lo), [x1]"r"(hi), [p1]"r"(addr));
538 static inline u64 otx2_atomic64_add(u64 incr, u64 *ptr)
542 __asm__ volatile(".cpu generic+lse\n"
543 "ldadd %x[i], %x[r], [%[b]]"
544 : [r]"=r"(result), "+m"(*ptr)
545 : [i]"r"(incr), [b]"r"(ptr)
551 #define otx2_write128(lo, hi, addr) writeq((hi) | (lo), addr)
552 #define otx2_atomic64_add(incr, ptr) ({ *ptr += incr; })
555 static inline void __cn10k_aura_freeptr(struct otx2_nic *pfvf, u64 aura,
556 u64 *ptrs, u64 num_ptrs,
559 u64 size = 0, count_eot = 0;
560 u64 tar_addr, val = 0;
562 tar_addr = (__force u64)otx2_get_regaddr(pfvf, NPA_LF_AURA_BATCH_FREE0);
563 /* LMTID is same as AURA Id */
564 val = (aura & 0x7FF) | BIT_ULL(63);
565 /* Set if [127:64] of last 128bit word has a valid pointer */
566 count_eot = (num_ptrs % 2) ? 0ULL : 1ULL;
567 /* Set AURA ID to free pointer */
568 ptrs[0] = (count_eot << 32) | (aura & 0xFFFFF);
569 /* Target address for LMTST flush tells HW how many 128bit
570 * words are valid from NPA_LF_AURA_BATCH_FREE0.
572 * tar_addr[6:4] is LMTST size-1 in units of 128b.
575 size = (sizeof(u64) * num_ptrs) / 16;
578 tar_addr |= ((size - 1) & 0x7) << 4;
580 memcpy(lmt_addr, ptrs, sizeof(u64) * num_ptrs);
581 /* Perform LMTST flush */
582 cn10k_lmt_flush(val, tar_addr);
585 static inline void cn10k_aura_freeptr(void *dev, int aura, u64 buf)
587 struct otx2_nic *pfvf = dev;
588 struct otx2_pool *pool;
591 pool = &pfvf->qset.pool[aura];
593 __cn10k_aura_freeptr(pfvf, aura, ptrs, 2, pool->lmt_addr);
596 /* Alloc pointer from pool/aura */
597 static inline u64 otx2_aura_allocptr(struct otx2_nic *pfvf, int aura)
599 u64 *ptr = (u64 *)otx2_get_regaddr(pfvf,
600 NPA_LF_AURA_OP_ALLOCX(0));
601 u64 incr = (u64)aura | BIT_ULL(63);
603 return otx2_atomic64_add(incr, ptr);
606 /* Free pointer to a pool/aura */
607 static inline void otx2_aura_freeptr(void *dev, int aura, u64 buf)
609 struct otx2_nic *pfvf = dev;
610 void __iomem *addr = otx2_get_regaddr(pfvf, NPA_LF_AURA_OP_FREE0);
612 otx2_write128(buf, (u64)aura | BIT_ULL(63), addr);
615 static inline int otx2_get_pool_idx(struct otx2_nic *pfvf, int type, int idx)
617 if (type == AURA_NIX_SQ)
618 return pfvf->hw.rqpool_cnt + idx;
625 static inline int otx2_sync_mbox_msg(struct mbox *mbox)
629 if (!otx2_mbox_nonempty(&mbox->mbox, 0))
631 otx2_mbox_msg_send(&mbox->mbox, 0);
632 err = otx2_mbox_wait_for_rsp(&mbox->mbox, 0);
636 return otx2_mbox_check_rsp_msgs(&mbox->mbox, 0);
639 static inline int otx2_sync_mbox_up_msg(struct mbox *mbox, int devid)
643 if (!otx2_mbox_nonempty(&mbox->mbox_up, devid))
645 otx2_mbox_msg_send(&mbox->mbox_up, devid);
646 err = otx2_mbox_wait_for_rsp(&mbox->mbox_up, devid);
650 return otx2_mbox_check_rsp_msgs(&mbox->mbox_up, devid);
653 /* Use this API to send mbox msgs in atomic context
654 * where sleeping is not allowed
656 static inline int otx2_sync_mbox_msg_busy_poll(struct mbox *mbox)
660 if (!otx2_mbox_nonempty(&mbox->mbox, 0))
662 otx2_mbox_msg_send(&mbox->mbox, 0);
663 err = otx2_mbox_busy_poll_for_rsp(&mbox->mbox, 0);
667 return otx2_mbox_check_rsp_msgs(&mbox->mbox, 0);
670 #define M(_name, _id, _fn_name, _req_type, _rsp_type) \
671 static struct _req_type __maybe_unused \
672 *otx2_mbox_alloc_msg_ ## _fn_name(struct mbox *mbox) \
674 struct _req_type *req; \
676 req = (struct _req_type *)otx2_mbox_alloc_msg_rsp( \
677 &mbox->mbox, 0, sizeof(struct _req_type), \
678 sizeof(struct _rsp_type)); \
681 req->hdr.sig = OTX2_MBOX_REQ_SIG; \
683 trace_otx2_msg_alloc(mbox->mbox.pdev, _id, sizeof(*req)); \
690 #define M(_name, _id, _fn_name, _req_type, _rsp_type) \
692 otx2_mbox_up_handler_ ## _fn_name(struct otx2_nic *pfvf, \
693 struct _req_type *req, \
694 struct _rsp_type *rsp); \
699 /* Time to wait before watchdog kicks off */
700 #define OTX2_TX_TIMEOUT (100 * HZ)
702 #define RVU_PFVF_PF_SHIFT 10
703 #define RVU_PFVF_PF_MASK 0x3F
704 #define RVU_PFVF_FUNC_SHIFT 0
705 #define RVU_PFVF_FUNC_MASK 0x3FF
707 static inline int rvu_get_pf(u16 pcifunc)
709 return (pcifunc >> RVU_PFVF_PF_SHIFT) & RVU_PFVF_PF_MASK;
712 static inline dma_addr_t otx2_dma_map_page(struct otx2_nic *pfvf,
714 size_t offset, size_t size,
715 enum dma_data_direction dir)
719 iova = dma_map_page_attrs(pfvf->dev, page,
720 offset, size, dir, DMA_ATTR_SKIP_CPU_SYNC);
721 if (unlikely(dma_mapping_error(pfvf->dev, iova)))
722 return (dma_addr_t)NULL;
726 static inline void otx2_dma_unmap_page(struct otx2_nic *pfvf,
727 dma_addr_t addr, size_t size,
728 enum dma_data_direction dir)
730 dma_unmap_page_attrs(pfvf->dev, addr, size,
731 dir, DMA_ATTR_SKIP_CPU_SYNC);
735 void otx2_free_cints(struct otx2_nic *pfvf, int n);
736 void otx2_set_cints_affinity(struct otx2_nic *pfvf);
737 int otx2_set_mac_address(struct net_device *netdev, void *p);
738 int otx2_hw_set_mtu(struct otx2_nic *pfvf, int mtu);
739 void otx2_tx_timeout(struct net_device *netdev, unsigned int txq);
740 void otx2_get_mac_from_af(struct net_device *netdev);
741 void otx2_config_irq_coalescing(struct otx2_nic *pfvf, int qidx);
742 int otx2_config_pause_frm(struct otx2_nic *pfvf);
743 void otx2_setup_segmentation(struct otx2_nic *pfvf);
745 /* RVU block related APIs */
746 int otx2_attach_npa_nix(struct otx2_nic *pfvf);
747 int otx2_detach_resources(struct mbox *mbox);
748 int otx2_config_npa(struct otx2_nic *pfvf);
749 int otx2_sq_aura_pool_init(struct otx2_nic *pfvf);
750 int otx2_rq_aura_pool_init(struct otx2_nic *pfvf);
751 void otx2_aura_pool_free(struct otx2_nic *pfvf);
752 void otx2_free_aura_ptr(struct otx2_nic *pfvf, int type);
753 void otx2_sq_free_sqbs(struct otx2_nic *pfvf);
754 int otx2_config_nix(struct otx2_nic *pfvf);
755 int otx2_config_nix_queues(struct otx2_nic *pfvf);
756 int otx2_txschq_config(struct otx2_nic *pfvf, int lvl);
757 int otx2_txsch_alloc(struct otx2_nic *pfvf);
758 int otx2_txschq_stop(struct otx2_nic *pfvf);
759 void otx2_sqb_flush(struct otx2_nic *pfvf);
760 int __otx2_alloc_rbuf(struct otx2_nic *pfvf, struct otx2_pool *pool,
762 int otx2_rxtx_enable(struct otx2_nic *pfvf, bool enable);
763 void otx2_ctx_disable(struct mbox *mbox, int type, bool npa);
764 int otx2_nix_config_bp(struct otx2_nic *pfvf, bool enable);
765 void otx2_cleanup_rx_cqes(struct otx2_nic *pfvf, struct otx2_cq_queue *cq);
766 void otx2_cleanup_tx_cqes(struct otx2_nic *pfvf, struct otx2_cq_queue *cq);
767 int otx2_sq_aq_init(void *dev, u16 qidx, u16 sqb_aura);
768 int cn10k_sq_aq_init(void *dev, u16 qidx, u16 sqb_aura);
769 int otx2_alloc_buffer(struct otx2_nic *pfvf, struct otx2_cq_queue *cq,
772 /* RSS configuration APIs*/
773 int otx2_rss_init(struct otx2_nic *pfvf);
774 int otx2_set_flowkey_cfg(struct otx2_nic *pfvf);
775 void otx2_set_rss_key(struct otx2_nic *pfvf);
776 int otx2_set_rss_table(struct otx2_nic *pfvf, int ctx_id);
779 void mbox_handler_msix_offset(struct otx2_nic *pfvf,
780 struct msix_offset_rsp *rsp);
781 void mbox_handler_npa_lf_alloc(struct otx2_nic *pfvf,
782 struct npa_lf_alloc_rsp *rsp);
783 void mbox_handler_nix_lf_alloc(struct otx2_nic *pfvf,
784 struct nix_lf_alloc_rsp *rsp);
785 void mbox_handler_nix_txsch_alloc(struct otx2_nic *pf,
786 struct nix_txsch_alloc_rsp *rsp);
787 void mbox_handler_cgx_stats(struct otx2_nic *pfvf,
788 struct cgx_stats_rsp *rsp);
789 void mbox_handler_cgx_fec_stats(struct otx2_nic *pfvf,
790 struct cgx_fec_stats_rsp *rsp);
791 void otx2_set_fec_stats_count(struct otx2_nic *pfvf);
792 void mbox_handler_nix_bp_enable(struct otx2_nic *pfvf,
793 struct nix_bp_cfg_rsp *rsp);
795 /* Device stats APIs */
796 void otx2_get_dev_stats(struct otx2_nic *pfvf);
797 void otx2_get_stats64(struct net_device *netdev,
798 struct rtnl_link_stats64 *stats);
799 void otx2_update_lmac_stats(struct otx2_nic *pfvf);
800 void otx2_update_lmac_fec_stats(struct otx2_nic *pfvf);
801 int otx2_update_rq_stats(struct otx2_nic *pfvf, int qidx);
802 int otx2_update_sq_stats(struct otx2_nic *pfvf, int qidx);
803 void otx2_set_ethtool_ops(struct net_device *netdev);
804 void otx2vf_set_ethtool_ops(struct net_device *netdev);
806 int otx2_open(struct net_device *netdev);
807 int otx2_stop(struct net_device *netdev);
808 int otx2_set_real_num_queues(struct net_device *netdev,
809 int tx_queues, int rx_queues);
810 /* MCAM filter related APIs */
811 int otx2_mcam_flow_init(struct otx2_nic *pf);
812 int otx2_alloc_mcam_entries(struct otx2_nic *pfvf);
813 void otx2_mcam_flow_del(struct otx2_nic *pf);
814 int otx2_destroy_ntuple_flows(struct otx2_nic *pf);
815 int otx2_destroy_mcam_flows(struct otx2_nic *pfvf);
816 int otx2_get_flow(struct otx2_nic *pfvf,
817 struct ethtool_rxnfc *nfc, u32 location);
818 int otx2_get_all_flows(struct otx2_nic *pfvf,
819 struct ethtool_rxnfc *nfc, u32 *rule_locs);
820 int otx2_add_flow(struct otx2_nic *pfvf,
821 struct ethtool_rxnfc *nfc);
822 int otx2_remove_flow(struct otx2_nic *pfvf, u32 location);
823 int otx2_prepare_flow_request(struct ethtool_rx_flow_spec *fsp,
824 struct npc_install_flow_req *req);
825 void otx2_rss_ctx_flow_del(struct otx2_nic *pfvf, int ctx_id);
826 int otx2_del_macfilter(struct net_device *netdev, const u8 *mac);
827 int otx2_add_macfilter(struct net_device *netdev, const u8 *mac);
828 int otx2_enable_rxvlan(struct otx2_nic *pf, bool enable);
829 int otx2_install_rxvlan_offload_flow(struct otx2_nic *pfvf);
830 u16 otx2_get_max_mtu(struct otx2_nic *pfvf);
832 int otx2_init_tc(struct otx2_nic *nic);
833 void otx2_shutdown_tc(struct otx2_nic *nic);
834 int otx2_setup_tc(struct net_device *netdev, enum tc_setup_type type,
836 #endif /* OTX2_COMMON_H */