1 /* SPDX-License-Identifier: GPL-2.0 */
2 /* Marvell RVU Ethernet driver
4 * Copyright (C) 2020 Marvell.
11 #include <linux/ethtool.h>
12 #include <linux/pci.h>
13 #include <linux/iommu.h>
14 #include <linux/net_tstamp.h>
15 #include <linux/ptp_clock_kernel.h>
16 #include <linux/timecounter.h>
17 #include <linux/soc/marvell/octeontx2/asm.h>
18 #include <net/pkt_cls.h>
19 #include <net/devlink.h>
24 #include "otx2_txrx.h"
25 #include "otx2_devlink.h"
26 #include <rvu_trace.h>
29 #define PCI_DEVID_OCTEONTX2_RVU_PF 0xA063
30 #define PCI_DEVID_OCTEONTX2_RVU_VF 0xA064
31 #define PCI_DEVID_OCTEONTX2_RVU_AFVF 0xA0F8
33 #define PCI_SUBSYS_DEVID_96XX_RVU_PFVF 0xB200
36 #define PCI_CFG_REG_BAR_NUM 2
37 #define PCI_MBOX_BAR_NUM 4
41 enum arua_mapped_qtypes {
46 /* NIX LF interrupts range*/
47 #define NIX_LF_QINT_VEC_START 0x00
48 #define NIX_LF_CINT_VEC_START 0x40
49 #define NIX_LF_GINT_VEC 0x80
50 #define NIX_LF_ERR_VEC 0x81
51 #define NIX_LF_POISON_VEC 0x82
53 /* Send skid of 2000 packets required for CQ size of 4K CQEs. */
54 #define SEND_CQ_SKID 2000
56 /* RSS configuration */
58 u8 ind_tbl[MAX_RSS_INDIR_TBL_SIZE];
61 struct otx2_rss_info {
65 #define RSS_HASH_KEY_SIZE 44 /* 352 bit key */
66 u8 key[RSS_HASH_KEY_SIZE];
67 struct otx2_rss_ctx *rss_ctx[MAX_RSS_GROUPS];
70 /* NIX (or NPC) RX errors */
81 NPC_ERRLVL_NIX = 0x0F,
84 enum otx2_errcodes_re {
85 /* NPC_ERRLVL_RE errcodes */
87 ERRCODE_FCS_RCV = 0x8,
88 ERRCODE_UNDERSIZE = 0x10,
89 ERRCODE_OVERSIZE = 0x11,
90 ERRCODE_OL2_LEN_MISMATCH = 0x12,
91 /* NPC_ERRLVL_NIX errcodes */
92 ERRCODE_OL3_LEN = 0x10,
93 ERRCODE_OL4_LEN = 0x11,
94 ERRCODE_OL4_CSUM = 0x12,
95 ERRCODE_IL3_LEN = 0x20,
96 ERRCODE_IL4_LEN = 0x21,
97 ERRCODE_IL4_CSUM = 0x22,
101 enum nix_stat_lf_tx {
111 enum nix_stat_lf_rx {
122 RX_DRP_L3BCAST = 0xa,
123 RX_DRP_L3MCAST = 0xb,
127 struct otx2_dev_stats {
143 /* Driver counted stats */
144 struct otx2_drv_stats {
145 atomic_t rx_fcs_errs;
146 atomic_t rx_oversize_errs;
147 atomic_t rx_undersize_errs;
148 atomic_t rx_csum_errs;
149 atomic_t rx_len_errs;
150 atomic_t rx_other_errs;
154 struct otx2_mbox mbox;
155 struct work_struct mbox_wrk;
156 struct otx2_mbox mbox_up;
157 struct work_struct mbox_up_wrk;
158 struct otx2_nic *pfvf;
159 void *bbuf_base; /* Bounce buffer for mbox memory */
160 struct mutex lock; /* serialize mailbox access */
161 int num_msgs; /* mbox number of messages */
162 int up_num_msgs; /* mbox_up number of messages */
166 struct pci_dev *pdev;
167 struct otx2_rss_info rss_info;
176 u32 stack_pg_ptrs; /* No of ptrs per stack page */
177 u32 stack_pg_bytes; /* Size of stack page */
181 u16 txschq_list[NIX_TXSCH_LVL_CNT][MAX_TXSCHQ_PER_FUNC];
182 u16 matchall_ipolicer;
185 /* HW settings, coalescing etc */
203 u8 cint_cnt; /* CQ interrupt count */
204 u16 npa_msixoff; /* Offset of NPA vectors */
205 u16 nix_msixoff; /* Offset of NIX vectors */
207 cpumask_var_t *affinity_mask;
210 struct otx2_dev_stats dev_stats;
211 struct otx2_drv_stats drv_stats;
212 u64 cgx_rx_stats[CGX_RX_STATS_COUNT];
213 u64 cgx_tx_stats[CGX_TX_STATS_COUNT];
214 u64 cgx_fec_corr_blks;
215 u64 cgx_fec_uncorr_blks;
216 u8 cgx_links; /* No. of CGX links present in HW */
217 u8 lbk_links; /* No. of LBK links present in HW */
218 u8 tx_link; /* Transmit channel link number */
221 #define CN10K_LMTST 2
222 unsigned long cap_flag;
224 #define LMT_LINE_SIZE 128
225 #define LMT_BURST_SIZE 32 /* 32 LMTST lines for burst SQE flush */
236 struct otx2_vf_config {
238 struct delayed_work link_event_work;
239 bool intf_down; /* interface was either configured or not */
247 struct work_struct work;
252 struct delayed_work pool_refill_work;
257 struct ptp_clock_info ptp_info;
258 struct ptp_clock *ptp_clock;
259 struct otx2_nic *nic;
261 struct cyclecounter cycle_counter;
262 struct timecounter time_counter;
265 #define OTX2_HW_TIMESTAMP_LEN 8
267 struct otx2_mac_table {
273 struct otx2_flow_config {
277 #define OTX2_DEFAULT_FLOWCOUNT 16
278 #define OTX2_MAX_UNICAST_FLOWS 8
279 #define OTX2_MAX_VLAN_FLOWS 1
280 #define OTX2_MAX_TC_FLOWS OTX2_DEFAULT_FLOWCOUNT
281 #define OTX2_MCAM_COUNT (OTX2_DEFAULT_FLOWCOUNT + \
282 OTX2_MAX_UNICAST_FLOWS + \
287 #define OTX2_PER_VF_VLAN_FLOWS 2 /* Rx + Tx per VF */
288 #define OTX2_VF_VLAN_RX_INDEX 0
289 #define OTX2_VF_VLAN_TX_INDEX 1
291 u8 dmacflt_max_flows;
292 u8 *bmap_to_dmacindex;
293 unsigned long dmacflt_bmap;
294 struct list_head flow_list;
297 struct otx2_tc_info {
298 /* hash table to store TC offloaded flows */
299 struct rhashtable flow_table;
300 struct rhashtable_params flow_ht_params;
301 unsigned long *tc_entries_bitmap;
305 int (*sq_aq_init)(void *dev, u16 qidx, u16 sqb_aura);
306 void (*sqe_flush)(void *dev, struct otx2_snd_queue *sq,
308 void (*refill_pool_ptrs)(void *dev, struct otx2_cq_queue *cq);
309 void (*aura_freeptr)(void *dev, int aura, u64 buf);
313 void __iomem *reg_base;
314 struct net_device *netdev;
315 struct dev_hw_ops *hw_ops;
318 u16 rbsize; /* Receive buffer size */
320 #define OTX2_FLAG_RX_TSTAMP_ENABLED BIT_ULL(0)
321 #define OTX2_FLAG_TX_TSTAMP_ENABLED BIT_ULL(1)
322 #define OTX2_FLAG_INTF_DOWN BIT_ULL(2)
323 #define OTX2_FLAG_MCAM_ENTRIES_ALLOC BIT_ULL(3)
324 #define OTX2_FLAG_NTUPLE_SUPPORT BIT_ULL(4)
325 #define OTX2_FLAG_UCAST_FLTR_SUPPORT BIT_ULL(5)
326 #define OTX2_FLAG_RX_VLAN_SUPPORT BIT_ULL(6)
327 #define OTX2_FLAG_VF_VLAN_SUPPORT BIT_ULL(7)
328 #define OTX2_FLAG_PF_SHUTDOWN BIT_ULL(8)
329 #define OTX2_FLAG_RX_PAUSE_ENABLED BIT_ULL(9)
330 #define OTX2_FLAG_TX_PAUSE_ENABLED BIT_ULL(10)
331 #define OTX2_FLAG_TC_FLOWER_SUPPORT BIT_ULL(11)
332 #define OTX2_FLAG_TC_MATCHALL_EGRESS_ENABLED BIT_ULL(12)
333 #define OTX2_FLAG_TC_MATCHALL_INGRESS_ENABLED BIT_ULL(13)
334 #define OTX2_FLAG_DMACFLTR_SUPPORT BIT_ULL(14)
337 struct otx2_qset qset;
339 struct pci_dev *pdev;
344 struct mbox *mbox_pfvf;
345 struct workqueue_struct *mbox_wq;
346 struct workqueue_struct *mbox_pfvf_wq;
349 u16 pcifunc; /* RVU PF_FUNC */
350 u16 bpid[NIX_MAX_BPID_CHAN];
351 struct otx2_vf_config *vf_configs;
352 struct cgx_link_user_info linfo;
355 struct otx2_flow_config *flow_cfg;
356 struct otx2_mac_table *mac_table;
357 struct otx2_tc_info tc_info;
360 struct work_struct reset_task;
361 struct workqueue_struct *flr_wq;
362 struct flr_work *flr_wrk;
363 struct refill_work *refill_wrk;
364 struct workqueue_struct *otx2_wq;
365 struct work_struct rx_mode_work;
370 /* Block address of NIX either BLKADDR_NIX0 or BLKADDR_NIX1 */
372 /* LMTST Lines info */
373 struct qmem *dync_lmt;
378 struct otx2_ptp *ptp;
379 struct hwtstamp_config tstamp;
381 unsigned long rq_bmap;
384 struct otx2_devlink *dl;
387 static inline bool is_otx2_lbkvf(struct pci_dev *pdev)
389 return pdev->device == PCI_DEVID_OCTEONTX2_RVU_AFVF;
392 static inline bool is_96xx_A0(struct pci_dev *pdev)
394 return (pdev->revision == 0x00) &&
395 (pdev->subsystem_device == PCI_SUBSYS_DEVID_96XX_RVU_PFVF);
398 static inline bool is_96xx_B0(struct pci_dev *pdev)
400 return (pdev->revision == 0x01) &&
401 (pdev->subsystem_device == PCI_SUBSYS_DEVID_96XX_RVU_PFVF);
404 /* REVID for PCIe devices.
405 * Bits 0..1: minor pass, bit 3..2: major pass
408 #define PCI_REVISION_ID_96XX 0x00
409 #define PCI_REVISION_ID_95XX 0x10
410 #define PCI_REVISION_ID_LOKI 0x20
411 #define PCI_REVISION_ID_98XX 0x30
412 #define PCI_REVISION_ID_95XXMM 0x40
414 static inline bool is_dev_otx2(struct pci_dev *pdev)
416 u8 midr = pdev->revision & 0xF0;
418 return (midr == PCI_REVISION_ID_96XX || midr == PCI_REVISION_ID_95XX ||
419 midr == PCI_REVISION_ID_LOKI || midr == PCI_REVISION_ID_98XX ||
420 midr == PCI_REVISION_ID_95XXMM);
423 static inline void otx2_setup_dev_hw_settings(struct otx2_nic *pfvf)
425 struct otx2_hw *hw = &pfvf->hw;
427 pfvf->hw.cq_time_wait = CQ_TIMER_THRESH_DEFAULT;
428 pfvf->hw.cq_ecount_wait = CQ_CQE_THRESH_DEFAULT;
429 pfvf->hw.cq_qcount_wait = CQ_QCOUNT_DEFAULT;
431 __set_bit(HW_TSO, &hw->cap_flag);
433 if (is_96xx_A0(pfvf->pdev)) {
434 __clear_bit(HW_TSO, &hw->cap_flag);
436 /* Time based irq coalescing is not supported */
437 pfvf->hw.cq_qcount_wait = 0x0;
439 /* Due to HW issue previous silicons required minimum
440 * 600 unused CQE to avoid CQ overflow.
442 pfvf->hw.rq_skid = 600;
443 pfvf->qset.rqe_cnt = Q_COUNT(Q_SIZE_1K);
445 if (is_96xx_B0(pfvf->pdev))
446 __clear_bit(HW_TSO, &hw->cap_flag);
448 if (!is_dev_otx2(pfvf->pdev)) {
449 __set_bit(CN10K_MBOX, &hw->cap_flag);
450 __set_bit(CN10K_LMTST, &hw->cap_flag);
454 /* Register read/write APIs */
455 static inline void __iomem *otx2_get_regaddr(struct otx2_nic *nic, u64 offset)
459 switch ((offset >> RVU_FUNC_BLKADDR_SHIFT) & RVU_FUNC_BLKADDR_MASK) {
461 blkaddr = nic->nix_blkaddr;
464 blkaddr = BLKADDR_NPA;
467 blkaddr = BLKADDR_RVUM;
471 offset &= ~(RVU_FUNC_BLKADDR_MASK << RVU_FUNC_BLKADDR_SHIFT);
472 offset |= (blkaddr << RVU_FUNC_BLKADDR_SHIFT);
474 return nic->reg_base + offset;
477 static inline void otx2_write64(struct otx2_nic *nic, u64 offset, u64 val)
479 void __iomem *addr = otx2_get_regaddr(nic, offset);
484 static inline u64 otx2_read64(struct otx2_nic *nic, u64 offset)
486 void __iomem *addr = otx2_get_regaddr(nic, offset);
491 /* Mbox bounce buffer APIs */
492 static inline int otx2_mbox_bbuf_init(struct mbox *mbox, struct pci_dev *pdev)
494 struct otx2_mbox *otx2_mbox;
495 struct otx2_mbox_dev *mdev;
497 mbox->bbuf_base = devm_kmalloc(&pdev->dev, MBOX_SIZE, GFP_KERNEL);
498 if (!mbox->bbuf_base)
501 /* Overwrite mbox mbase to point to bounce buffer, so that PF/VF
502 * prepare all mbox messages in bounce buffer instead of directly
505 otx2_mbox = &mbox->mbox;
506 mdev = &otx2_mbox->dev[0];
507 mdev->mbase = mbox->bbuf_base;
509 otx2_mbox = &mbox->mbox_up;
510 mdev = &otx2_mbox->dev[0];
511 mdev->mbase = mbox->bbuf_base;
515 static inline void otx2_sync_mbox_bbuf(struct otx2_mbox *mbox, int devid)
517 u16 msgs_offset = ALIGN(sizeof(struct mbox_hdr), MBOX_MSG_ALIGN);
518 void *hw_mbase = mbox->hwbase + (devid * MBOX_SIZE);
519 struct otx2_mbox_dev *mdev = &mbox->dev[devid];
520 struct mbox_hdr *hdr;
523 if (mdev->mbase == hw_mbase)
526 hdr = hw_mbase + mbox->rx_start;
527 msg_size = hdr->msg_size;
529 if (msg_size > mbox->rx_size - msgs_offset)
530 msg_size = mbox->rx_size - msgs_offset;
532 /* Copy mbox messages from mbox memory to bounce buffer */
533 memcpy(mdev->mbase + mbox->rx_start,
534 hw_mbase + mbox->rx_start, msg_size + msgs_offset);
537 /* With the absence of API for 128-bit IO memory access for arm64,
538 * implement required operations at place.
540 #if defined(CONFIG_ARM64)
541 static inline void otx2_write128(u64 lo, u64 hi, void __iomem *addr)
543 __asm__ volatile("stp %x[x0], %x[x1], [%x[p1],#0]!"
544 ::[x0]"r"(lo), [x1]"r"(hi), [p1]"r"(addr));
547 static inline u64 otx2_atomic64_add(u64 incr, u64 *ptr)
551 __asm__ volatile(".cpu generic+lse\n"
552 "ldadd %x[i], %x[r], [%[b]]"
553 : [r]"=r"(result), "+m"(*ptr)
554 : [i]"r"(incr), [b]"r"(ptr)
560 #define otx2_write128(lo, hi, addr) writeq((hi) | (lo), addr)
561 #define otx2_atomic64_add(incr, ptr) ({ *ptr += incr; })
564 static inline void __cn10k_aura_freeptr(struct otx2_nic *pfvf, u64 aura,
565 u64 *ptrs, u64 num_ptrs,
568 u64 size = 0, count_eot = 0;
569 u64 tar_addr, val = 0;
571 tar_addr = (__force u64)otx2_get_regaddr(pfvf, NPA_LF_AURA_BATCH_FREE0);
572 /* LMTID is same as AURA Id */
573 val = (aura & 0x7FF) | BIT_ULL(63);
574 /* Set if [127:64] of last 128bit word has a valid pointer */
575 count_eot = (num_ptrs % 2) ? 0ULL : 1ULL;
576 /* Set AURA ID to free pointer */
577 ptrs[0] = (count_eot << 32) | (aura & 0xFFFFF);
578 /* Target address for LMTST flush tells HW how many 128bit
579 * words are valid from NPA_LF_AURA_BATCH_FREE0.
581 * tar_addr[6:4] is LMTST size-1 in units of 128b.
584 size = (sizeof(u64) * num_ptrs) / 16;
587 tar_addr |= ((size - 1) & 0x7) << 4;
589 memcpy(lmt_addr, ptrs, sizeof(u64) * num_ptrs);
590 /* Perform LMTST flush */
591 cn10k_lmt_flush(val, tar_addr);
594 static inline void cn10k_aura_freeptr(void *dev, int aura, u64 buf)
596 struct otx2_nic *pfvf = dev;
597 struct otx2_pool *pool;
600 pool = &pfvf->qset.pool[aura];
602 __cn10k_aura_freeptr(pfvf, aura, ptrs, 2, pool->lmt_addr);
605 /* Alloc pointer from pool/aura */
606 static inline u64 otx2_aura_allocptr(struct otx2_nic *pfvf, int aura)
608 u64 *ptr = (u64 *)otx2_get_regaddr(pfvf,
609 NPA_LF_AURA_OP_ALLOCX(0));
610 u64 incr = (u64)aura | BIT_ULL(63);
612 return otx2_atomic64_add(incr, ptr);
615 /* Free pointer to a pool/aura */
616 static inline void otx2_aura_freeptr(void *dev, int aura, u64 buf)
618 struct otx2_nic *pfvf = dev;
619 void __iomem *addr = otx2_get_regaddr(pfvf, NPA_LF_AURA_OP_FREE0);
621 otx2_write128(buf, (u64)aura | BIT_ULL(63), addr);
624 static inline int otx2_get_pool_idx(struct otx2_nic *pfvf, int type, int idx)
626 if (type == AURA_NIX_SQ)
627 return pfvf->hw.rqpool_cnt + idx;
634 static inline int otx2_sync_mbox_msg(struct mbox *mbox)
638 if (!otx2_mbox_nonempty(&mbox->mbox, 0))
640 otx2_mbox_msg_send(&mbox->mbox, 0);
641 err = otx2_mbox_wait_for_rsp(&mbox->mbox, 0);
645 return otx2_mbox_check_rsp_msgs(&mbox->mbox, 0);
648 static inline int otx2_sync_mbox_up_msg(struct mbox *mbox, int devid)
652 if (!otx2_mbox_nonempty(&mbox->mbox_up, devid))
654 otx2_mbox_msg_send(&mbox->mbox_up, devid);
655 err = otx2_mbox_wait_for_rsp(&mbox->mbox_up, devid);
659 return otx2_mbox_check_rsp_msgs(&mbox->mbox_up, devid);
662 /* Use this API to send mbox msgs in atomic context
663 * where sleeping is not allowed
665 static inline int otx2_sync_mbox_msg_busy_poll(struct mbox *mbox)
669 if (!otx2_mbox_nonempty(&mbox->mbox, 0))
671 otx2_mbox_msg_send(&mbox->mbox, 0);
672 err = otx2_mbox_busy_poll_for_rsp(&mbox->mbox, 0);
676 return otx2_mbox_check_rsp_msgs(&mbox->mbox, 0);
679 #define M(_name, _id, _fn_name, _req_type, _rsp_type) \
680 static struct _req_type __maybe_unused \
681 *otx2_mbox_alloc_msg_ ## _fn_name(struct mbox *mbox) \
683 struct _req_type *req; \
685 req = (struct _req_type *)otx2_mbox_alloc_msg_rsp( \
686 &mbox->mbox, 0, sizeof(struct _req_type), \
687 sizeof(struct _rsp_type)); \
690 req->hdr.sig = OTX2_MBOX_REQ_SIG; \
692 trace_otx2_msg_alloc(mbox->mbox.pdev, _id, sizeof(*req)); \
699 #define M(_name, _id, _fn_name, _req_type, _rsp_type) \
701 otx2_mbox_up_handler_ ## _fn_name(struct otx2_nic *pfvf, \
702 struct _req_type *req, \
703 struct _rsp_type *rsp); \
708 /* Time to wait before watchdog kicks off */
709 #define OTX2_TX_TIMEOUT (100 * HZ)
711 #define RVU_PFVF_PF_SHIFT 10
712 #define RVU_PFVF_PF_MASK 0x3F
713 #define RVU_PFVF_FUNC_SHIFT 0
714 #define RVU_PFVF_FUNC_MASK 0x3FF
716 static inline bool is_otx2_vf(u16 pcifunc)
718 return !!(pcifunc & RVU_PFVF_FUNC_MASK);
721 static inline int rvu_get_pf(u16 pcifunc)
723 return (pcifunc >> RVU_PFVF_PF_SHIFT) & RVU_PFVF_PF_MASK;
726 static inline dma_addr_t otx2_dma_map_page(struct otx2_nic *pfvf,
728 size_t offset, size_t size,
729 enum dma_data_direction dir)
733 iova = dma_map_page_attrs(pfvf->dev, page,
734 offset, size, dir, DMA_ATTR_SKIP_CPU_SYNC);
735 if (unlikely(dma_mapping_error(pfvf->dev, iova)))
736 return (dma_addr_t)NULL;
740 static inline void otx2_dma_unmap_page(struct otx2_nic *pfvf,
741 dma_addr_t addr, size_t size,
742 enum dma_data_direction dir)
744 dma_unmap_page_attrs(pfvf->dev, addr, size,
745 dir, DMA_ATTR_SKIP_CPU_SYNC);
749 void otx2_free_cints(struct otx2_nic *pfvf, int n);
750 void otx2_set_cints_affinity(struct otx2_nic *pfvf);
751 int otx2_set_mac_address(struct net_device *netdev, void *p);
752 int otx2_hw_set_mtu(struct otx2_nic *pfvf, int mtu);
753 void otx2_tx_timeout(struct net_device *netdev, unsigned int txq);
754 void otx2_get_mac_from_af(struct net_device *netdev);
755 void otx2_config_irq_coalescing(struct otx2_nic *pfvf, int qidx);
756 int otx2_config_pause_frm(struct otx2_nic *pfvf);
757 void otx2_setup_segmentation(struct otx2_nic *pfvf);
759 /* RVU block related APIs */
760 int otx2_attach_npa_nix(struct otx2_nic *pfvf);
761 int otx2_detach_resources(struct mbox *mbox);
762 int otx2_config_npa(struct otx2_nic *pfvf);
763 int otx2_sq_aura_pool_init(struct otx2_nic *pfvf);
764 int otx2_rq_aura_pool_init(struct otx2_nic *pfvf);
765 void otx2_aura_pool_free(struct otx2_nic *pfvf);
766 void otx2_free_aura_ptr(struct otx2_nic *pfvf, int type);
767 void otx2_sq_free_sqbs(struct otx2_nic *pfvf);
768 int otx2_config_nix(struct otx2_nic *pfvf);
769 int otx2_config_nix_queues(struct otx2_nic *pfvf);
770 int otx2_txschq_config(struct otx2_nic *pfvf, int lvl);
771 int otx2_txsch_alloc(struct otx2_nic *pfvf);
772 int otx2_txschq_stop(struct otx2_nic *pfvf);
773 void otx2_sqb_flush(struct otx2_nic *pfvf);
774 int __otx2_alloc_rbuf(struct otx2_nic *pfvf, struct otx2_pool *pool,
776 int otx2_rxtx_enable(struct otx2_nic *pfvf, bool enable);
777 void otx2_ctx_disable(struct mbox *mbox, int type, bool npa);
778 int otx2_nix_config_bp(struct otx2_nic *pfvf, bool enable);
779 void otx2_cleanup_rx_cqes(struct otx2_nic *pfvf, struct otx2_cq_queue *cq);
780 void otx2_cleanup_tx_cqes(struct otx2_nic *pfvf, struct otx2_cq_queue *cq);
781 int otx2_sq_aq_init(void *dev, u16 qidx, u16 sqb_aura);
782 int cn10k_sq_aq_init(void *dev, u16 qidx, u16 sqb_aura);
783 int otx2_alloc_buffer(struct otx2_nic *pfvf, struct otx2_cq_queue *cq,
786 /* RSS configuration APIs*/
787 int otx2_rss_init(struct otx2_nic *pfvf);
788 int otx2_set_flowkey_cfg(struct otx2_nic *pfvf);
789 void otx2_set_rss_key(struct otx2_nic *pfvf);
790 int otx2_set_rss_table(struct otx2_nic *pfvf, int ctx_id);
793 void mbox_handler_msix_offset(struct otx2_nic *pfvf,
794 struct msix_offset_rsp *rsp);
795 void mbox_handler_npa_lf_alloc(struct otx2_nic *pfvf,
796 struct npa_lf_alloc_rsp *rsp);
797 void mbox_handler_nix_lf_alloc(struct otx2_nic *pfvf,
798 struct nix_lf_alloc_rsp *rsp);
799 void mbox_handler_nix_txsch_alloc(struct otx2_nic *pf,
800 struct nix_txsch_alloc_rsp *rsp);
801 void mbox_handler_cgx_stats(struct otx2_nic *pfvf,
802 struct cgx_stats_rsp *rsp);
803 void mbox_handler_cgx_fec_stats(struct otx2_nic *pfvf,
804 struct cgx_fec_stats_rsp *rsp);
805 void otx2_set_fec_stats_count(struct otx2_nic *pfvf);
806 void mbox_handler_nix_bp_enable(struct otx2_nic *pfvf,
807 struct nix_bp_cfg_rsp *rsp);
809 /* Device stats APIs */
810 void otx2_get_dev_stats(struct otx2_nic *pfvf);
811 void otx2_get_stats64(struct net_device *netdev,
812 struct rtnl_link_stats64 *stats);
813 void otx2_update_lmac_stats(struct otx2_nic *pfvf);
814 void otx2_update_lmac_fec_stats(struct otx2_nic *pfvf);
815 int otx2_update_rq_stats(struct otx2_nic *pfvf, int qidx);
816 int otx2_update_sq_stats(struct otx2_nic *pfvf, int qidx);
817 void otx2_set_ethtool_ops(struct net_device *netdev);
818 void otx2vf_set_ethtool_ops(struct net_device *netdev);
820 int otx2_open(struct net_device *netdev);
821 int otx2_stop(struct net_device *netdev);
822 int otx2_set_real_num_queues(struct net_device *netdev,
823 int tx_queues, int rx_queues);
824 /* MCAM filter related APIs */
825 int otx2_mcam_flow_init(struct otx2_nic *pf);
826 int otx2vf_mcam_flow_init(struct otx2_nic *pfvf);
827 int otx2_alloc_mcam_entries(struct otx2_nic *pfvf, u16 count);
828 void otx2_mcam_flow_del(struct otx2_nic *pf);
829 int otx2_destroy_ntuple_flows(struct otx2_nic *pf);
830 int otx2_destroy_mcam_flows(struct otx2_nic *pfvf);
831 int otx2_get_flow(struct otx2_nic *pfvf,
832 struct ethtool_rxnfc *nfc, u32 location);
833 int otx2_get_all_flows(struct otx2_nic *pfvf,
834 struct ethtool_rxnfc *nfc, u32 *rule_locs);
835 int otx2_add_flow(struct otx2_nic *pfvf,
836 struct ethtool_rxnfc *nfc);
837 int otx2_remove_flow(struct otx2_nic *pfvf, u32 location);
838 int otx2_get_maxflows(struct otx2_flow_config *flow_cfg);
839 void otx2_rss_ctx_flow_del(struct otx2_nic *pfvf, int ctx_id);
840 int otx2_del_macfilter(struct net_device *netdev, const u8 *mac);
841 int otx2_add_macfilter(struct net_device *netdev, const u8 *mac);
842 int otx2_enable_rxvlan(struct otx2_nic *pf, bool enable);
843 int otx2_install_rxvlan_offload_flow(struct otx2_nic *pfvf);
844 u16 otx2_get_max_mtu(struct otx2_nic *pfvf);
846 int otx2_init_tc(struct otx2_nic *nic);
847 void otx2_shutdown_tc(struct otx2_nic *nic);
848 int otx2_setup_tc(struct net_device *netdev, enum tc_setup_type type,
850 int otx2_tc_alloc_ent_bitmap(struct otx2_nic *nic);
851 /* CGX/RPM DMAC filters support */
852 int otx2_dmacflt_get_max_cnt(struct otx2_nic *pf);
853 int otx2_dmacflt_add(struct otx2_nic *pf, const u8 *mac, u8 bit_pos);
854 int otx2_dmacflt_remove(struct otx2_nic *pf, const u8 *mac, u8 bit_pos);
855 int otx2_dmacflt_update(struct otx2_nic *pf, u8 *mac, u8 bit_pos);
856 void otx2_dmacflt_reinstall_flows(struct otx2_nic *pf);
857 void otx2_dmacflt_update_pfmac_flow(struct otx2_nic *pfvf);
858 #endif /* OTX2_COMMON_H */