1 // SPDX-License-Identifier: GPL-2.0
2 /* Marvell OcteonTx2 RVU Ethernet driver
4 * Copyright (C) 2020 Marvell International Ltd.
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2 as
8 * published by the Free Software Foundation.
11 #include <linux/interrupt.h>
12 #include <linux/pci.h>
16 #include "otx2_common.h"
17 #include "otx2_struct.h"
20 static void otx2_nix_rq_op_stats(struct queue_stats *stats,
21 struct otx2_nic *pfvf, int qidx)
23 u64 incr = (u64)qidx << 32;
26 ptr = (u64 *)otx2_get_regaddr(pfvf, NIX_LF_RQ_OP_OCTS);
27 stats->bytes = otx2_atomic64_add(incr, ptr);
29 ptr = (u64 *)otx2_get_regaddr(pfvf, NIX_LF_RQ_OP_PKTS);
30 stats->pkts = otx2_atomic64_add(incr, ptr);
33 static void otx2_nix_sq_op_stats(struct queue_stats *stats,
34 struct otx2_nic *pfvf, int qidx)
36 u64 incr = (u64)qidx << 32;
39 ptr = (u64 *)otx2_get_regaddr(pfvf, NIX_LF_SQ_OP_OCTS);
40 stats->bytes = otx2_atomic64_add(incr, ptr);
42 ptr = (u64 *)otx2_get_regaddr(pfvf, NIX_LF_SQ_OP_PKTS);
43 stats->pkts = otx2_atomic64_add(incr, ptr);
46 void otx2_update_lmac_stats(struct otx2_nic *pfvf)
50 if (!netif_running(pfvf->netdev))
53 mutex_lock(&pfvf->mbox.lock);
54 req = otx2_mbox_alloc_msg_cgx_stats(&pfvf->mbox);
56 mutex_unlock(&pfvf->mbox.lock);
60 otx2_sync_mbox_msg(&pfvf->mbox);
61 mutex_unlock(&pfvf->mbox.lock);
64 void otx2_update_lmac_fec_stats(struct otx2_nic *pfvf)
68 if (!netif_running(pfvf->netdev))
70 mutex_lock(&pfvf->mbox.lock);
71 req = otx2_mbox_alloc_msg_cgx_fec_stats(&pfvf->mbox);
73 otx2_sync_mbox_msg(&pfvf->mbox);
74 mutex_unlock(&pfvf->mbox.lock);
77 int otx2_update_rq_stats(struct otx2_nic *pfvf, int qidx)
79 struct otx2_rcv_queue *rq = &pfvf->qset.rq[qidx];
84 otx2_nix_rq_op_stats(&rq->stats, pfvf, qidx);
88 int otx2_update_sq_stats(struct otx2_nic *pfvf, int qidx)
90 struct otx2_snd_queue *sq = &pfvf->qset.sq[qidx];
95 otx2_nix_sq_op_stats(&sq->stats, pfvf, qidx);
99 void otx2_get_dev_stats(struct otx2_nic *pfvf)
101 struct otx2_dev_stats *dev_stats = &pfvf->hw.dev_stats;
103 #define OTX2_GET_RX_STATS(reg) \
104 otx2_read64(pfvf, NIX_LF_RX_STATX(reg))
105 #define OTX2_GET_TX_STATS(reg) \
106 otx2_read64(pfvf, NIX_LF_TX_STATX(reg))
108 dev_stats->rx_bytes = OTX2_GET_RX_STATS(RX_OCTS);
109 dev_stats->rx_drops = OTX2_GET_RX_STATS(RX_DROP);
110 dev_stats->rx_bcast_frames = OTX2_GET_RX_STATS(RX_BCAST);
111 dev_stats->rx_mcast_frames = OTX2_GET_RX_STATS(RX_MCAST);
112 dev_stats->rx_ucast_frames = OTX2_GET_RX_STATS(RX_UCAST);
113 dev_stats->rx_frames = dev_stats->rx_bcast_frames +
114 dev_stats->rx_mcast_frames +
115 dev_stats->rx_ucast_frames;
117 dev_stats->tx_bytes = OTX2_GET_TX_STATS(TX_OCTS);
118 dev_stats->tx_drops = OTX2_GET_TX_STATS(TX_DROP);
119 dev_stats->tx_bcast_frames = OTX2_GET_TX_STATS(TX_BCAST);
120 dev_stats->tx_mcast_frames = OTX2_GET_TX_STATS(TX_MCAST);
121 dev_stats->tx_ucast_frames = OTX2_GET_TX_STATS(TX_UCAST);
122 dev_stats->tx_frames = dev_stats->tx_bcast_frames +
123 dev_stats->tx_mcast_frames +
124 dev_stats->tx_ucast_frames;
127 void otx2_get_stats64(struct net_device *netdev,
128 struct rtnl_link_stats64 *stats)
130 struct otx2_nic *pfvf = netdev_priv(netdev);
131 struct otx2_dev_stats *dev_stats;
133 otx2_get_dev_stats(pfvf);
135 dev_stats = &pfvf->hw.dev_stats;
136 stats->rx_bytes = dev_stats->rx_bytes;
137 stats->rx_packets = dev_stats->rx_frames;
138 stats->rx_dropped = dev_stats->rx_drops;
139 stats->multicast = dev_stats->rx_mcast_frames;
141 stats->tx_bytes = dev_stats->tx_bytes;
142 stats->tx_packets = dev_stats->tx_frames;
143 stats->tx_dropped = dev_stats->tx_drops;
145 EXPORT_SYMBOL(otx2_get_stats64);
147 /* Sync MAC address with RVU AF */
148 static int otx2_hw_set_mac_addr(struct otx2_nic *pfvf, u8 *mac)
150 struct nix_set_mac_addr *req;
153 mutex_lock(&pfvf->mbox.lock);
154 req = otx2_mbox_alloc_msg_nix_set_mac_addr(&pfvf->mbox);
156 mutex_unlock(&pfvf->mbox.lock);
160 ether_addr_copy(req->mac_addr, mac);
162 err = otx2_sync_mbox_msg(&pfvf->mbox);
163 mutex_unlock(&pfvf->mbox.lock);
167 static int otx2_hw_get_mac_addr(struct otx2_nic *pfvf,
168 struct net_device *netdev)
170 struct nix_get_mac_addr_rsp *rsp;
171 struct mbox_msghdr *msghdr;
175 mutex_lock(&pfvf->mbox.lock);
176 req = otx2_mbox_alloc_msg_nix_get_mac_addr(&pfvf->mbox);
178 mutex_unlock(&pfvf->mbox.lock);
182 err = otx2_sync_mbox_msg(&pfvf->mbox);
184 mutex_unlock(&pfvf->mbox.lock);
188 msghdr = otx2_mbox_get_rsp(&pfvf->mbox.mbox, 0, &req->hdr);
189 if (IS_ERR(msghdr)) {
190 mutex_unlock(&pfvf->mbox.lock);
191 return PTR_ERR(msghdr);
193 rsp = (struct nix_get_mac_addr_rsp *)msghdr;
194 ether_addr_copy(netdev->dev_addr, rsp->mac_addr);
195 mutex_unlock(&pfvf->mbox.lock);
200 int otx2_set_mac_address(struct net_device *netdev, void *p)
202 struct otx2_nic *pfvf = netdev_priv(netdev);
203 struct sockaddr *addr = p;
205 if (!is_valid_ether_addr(addr->sa_data))
206 return -EADDRNOTAVAIL;
208 if (!otx2_hw_set_mac_addr(pfvf, addr->sa_data)) {
209 memcpy(netdev->dev_addr, addr->sa_data, netdev->addr_len);
210 /* update dmac field in vlan offload rule */
211 if (pfvf->flags & OTX2_FLAG_RX_VLAN_SUPPORT)
212 otx2_install_rxvlan_offload_flow(pfvf);
213 /* update dmac address in ntuple and DMAC filter list */
214 if (pfvf->flags & OTX2_FLAG_DMACFLTR_SUPPORT)
215 otx2_dmacflt_update_pfmac_flow(pfvf);
222 EXPORT_SYMBOL(otx2_set_mac_address);
224 int otx2_hw_set_mtu(struct otx2_nic *pfvf, int mtu)
226 struct nix_frs_cfg *req;
229 mutex_lock(&pfvf->mbox.lock);
230 req = otx2_mbox_alloc_msg_nix_set_hw_frs(&pfvf->mbox);
232 mutex_unlock(&pfvf->mbox.lock);
236 req->maxlen = pfvf->max_frs;
238 err = otx2_sync_mbox_msg(&pfvf->mbox);
239 mutex_unlock(&pfvf->mbox.lock);
243 int otx2_config_pause_frm(struct otx2_nic *pfvf)
245 struct cgx_pause_frm_cfg *req;
248 if (is_otx2_lbkvf(pfvf->pdev))
251 mutex_lock(&pfvf->mbox.lock);
252 req = otx2_mbox_alloc_msg_cgx_cfg_pause_frm(&pfvf->mbox);
258 req->rx_pause = !!(pfvf->flags & OTX2_FLAG_RX_PAUSE_ENABLED);
259 req->tx_pause = !!(pfvf->flags & OTX2_FLAG_TX_PAUSE_ENABLED);
262 err = otx2_sync_mbox_msg(&pfvf->mbox);
264 mutex_unlock(&pfvf->mbox.lock);
268 int otx2_set_flowkey_cfg(struct otx2_nic *pfvf)
270 struct otx2_rss_info *rss = &pfvf->hw.rss_info;
271 struct nix_rss_flowkey_cfg *req;
274 mutex_lock(&pfvf->mbox.lock);
275 req = otx2_mbox_alloc_msg_nix_rss_flowkey_cfg(&pfvf->mbox);
277 mutex_unlock(&pfvf->mbox.lock);
280 req->mcam_index = -1; /* Default or reserved index */
281 req->flowkey_cfg = rss->flowkey_cfg;
282 req->group = DEFAULT_RSS_CONTEXT_GROUP;
284 err = otx2_sync_mbox_msg(&pfvf->mbox);
285 mutex_unlock(&pfvf->mbox.lock);
289 int otx2_set_rss_table(struct otx2_nic *pfvf, int ctx_id)
291 struct otx2_rss_info *rss = &pfvf->hw.rss_info;
292 const int index = rss->rss_size * ctx_id;
293 struct mbox *mbox = &pfvf->mbox;
294 struct otx2_rss_ctx *rss_ctx;
295 struct nix_aq_enq_req *aq;
298 mutex_lock(&mbox->lock);
299 rss_ctx = rss->rss_ctx[ctx_id];
300 /* Get memory to put this msg */
301 for (idx = 0; idx < rss->rss_size; idx++) {
302 aq = otx2_mbox_alloc_msg_nix_aq_enq(mbox);
304 /* The shared memory buffer can be full.
307 err = otx2_sync_mbox_msg(mbox);
309 mutex_unlock(&mbox->lock);
312 aq = otx2_mbox_alloc_msg_nix_aq_enq(mbox);
314 mutex_unlock(&mbox->lock);
319 aq->rss.rq = rss_ctx->ind_tbl[idx];
322 aq->qidx = index + idx;
323 aq->ctype = NIX_AQ_CTYPE_RSS;
324 aq->op = NIX_AQ_INSTOP_INIT;
326 err = otx2_sync_mbox_msg(mbox);
327 mutex_unlock(&mbox->lock);
331 void otx2_set_rss_key(struct otx2_nic *pfvf)
333 struct otx2_rss_info *rss = &pfvf->hw.rss_info;
334 u64 *key = (u64 *)&rss->key[4];
337 /* 352bit or 44byte key needs to be configured as below
338 * NIX_LF_RX_SECRETX0 = key<351:288>
339 * NIX_LF_RX_SECRETX1 = key<287:224>
340 * NIX_LF_RX_SECRETX2 = key<223:160>
341 * NIX_LF_RX_SECRETX3 = key<159:96>
342 * NIX_LF_RX_SECRETX4 = key<95:32>
343 * NIX_LF_RX_SECRETX5<63:32> = key<31:0>
345 otx2_write64(pfvf, NIX_LF_RX_SECRETX(5),
346 (u64)(*((u32 *)&rss->key)) << 32);
347 idx = sizeof(rss->key) / sizeof(u64);
350 otx2_write64(pfvf, NIX_LF_RX_SECRETX(idx), *key++);
354 int otx2_rss_init(struct otx2_nic *pfvf)
356 struct otx2_rss_info *rss = &pfvf->hw.rss_info;
357 struct otx2_rss_ctx *rss_ctx;
360 rss->rss_size = sizeof(*rss->rss_ctx[DEFAULT_RSS_CONTEXT_GROUP]);
362 /* Init RSS key if it is not setup already */
364 netdev_rss_key_fill(rss->key, sizeof(rss->key));
365 otx2_set_rss_key(pfvf);
367 if (!netif_is_rxfh_configured(pfvf->netdev)) {
368 /* Set RSS group 0 as default indirection table */
369 rss->rss_ctx[DEFAULT_RSS_CONTEXT_GROUP] = kzalloc(rss->rss_size,
371 if (!rss->rss_ctx[DEFAULT_RSS_CONTEXT_GROUP])
374 rss_ctx = rss->rss_ctx[DEFAULT_RSS_CONTEXT_GROUP];
375 for (idx = 0; idx < rss->rss_size; idx++)
376 rss_ctx->ind_tbl[idx] =
377 ethtool_rxfh_indir_default(idx,
380 ret = otx2_set_rss_table(pfvf, DEFAULT_RSS_CONTEXT_GROUP);
384 /* Flowkey or hash config to be used for generating flow tag */
385 rss->flowkey_cfg = rss->enable ? rss->flowkey_cfg :
386 NIX_FLOW_KEY_TYPE_IPV4 | NIX_FLOW_KEY_TYPE_IPV6 |
387 NIX_FLOW_KEY_TYPE_TCP | NIX_FLOW_KEY_TYPE_UDP |
388 NIX_FLOW_KEY_TYPE_SCTP | NIX_FLOW_KEY_TYPE_VLAN |
389 NIX_FLOW_KEY_TYPE_IPV4_PROTO;
391 ret = otx2_set_flowkey_cfg(pfvf);
399 /* Setup UDP segmentation algorithm in HW */
400 static void otx2_setup_udp_segmentation(struct nix_lso_format_cfg *lso, bool v4)
402 struct nix_lso_format *field;
404 field = (struct nix_lso_format *)&lso->fields[0];
405 lso->field_mask = GENMASK(18, 0);
407 /* IP's Length field */
408 field->layer = NIX_TXLAYER_OL3;
409 /* In ipv4, length field is at offset 2 bytes, for ipv6 it's 4 */
410 field->offset = v4 ? 2 : 4;
411 field->sizem1 = 1; /* i.e 2 bytes */
412 field->alg = NIX_LSOALG_ADD_PAYLEN;
415 /* No ID field in IPv6 header */
418 field->layer = NIX_TXLAYER_OL3;
420 field->sizem1 = 1; /* i.e 2 bytes */
421 field->alg = NIX_LSOALG_ADD_SEGNUM;
425 /* Update length in UDP header */
426 field->layer = NIX_TXLAYER_OL4;
429 field->alg = NIX_LSOALG_ADD_PAYLEN;
432 /* Setup segmentation algorithms in HW and retrieve algorithm index */
433 void otx2_setup_segmentation(struct otx2_nic *pfvf)
435 struct nix_lso_format_cfg_rsp *rsp;
436 struct nix_lso_format_cfg *lso;
437 struct otx2_hw *hw = &pfvf->hw;
440 mutex_lock(&pfvf->mbox.lock);
442 /* UDPv4 segmentation */
443 lso = otx2_mbox_alloc_msg_nix_lso_format_cfg(&pfvf->mbox);
447 /* Setup UDP/IP header fields that HW should update per segment */
448 otx2_setup_udp_segmentation(lso, true);
450 err = otx2_sync_mbox_msg(&pfvf->mbox);
454 rsp = (struct nix_lso_format_cfg_rsp *)
455 otx2_mbox_get_rsp(&pfvf->mbox.mbox, 0, &lso->hdr);
459 hw->lso_udpv4_idx = rsp->lso_format_idx;
461 /* UDPv6 segmentation */
462 lso = otx2_mbox_alloc_msg_nix_lso_format_cfg(&pfvf->mbox);
466 /* Setup UDP/IP header fields that HW should update per segment */
467 otx2_setup_udp_segmentation(lso, false);
469 err = otx2_sync_mbox_msg(&pfvf->mbox);
473 rsp = (struct nix_lso_format_cfg_rsp *)
474 otx2_mbox_get_rsp(&pfvf->mbox.mbox, 0, &lso->hdr);
478 hw->lso_udpv6_idx = rsp->lso_format_idx;
479 mutex_unlock(&pfvf->mbox.lock);
482 mutex_unlock(&pfvf->mbox.lock);
483 netdev_info(pfvf->netdev,
484 "Failed to get LSO index for UDP GSO offload, disabling\n");
485 pfvf->netdev->hw_features &= ~NETIF_F_GSO_UDP_L4;
488 void otx2_config_irq_coalescing(struct otx2_nic *pfvf, int qidx)
490 /* Configure CQE interrupt coalescing parameters
492 * HW triggers an irq when ECOUNT > cq_ecount_wait, hence
493 * set 1 less than cq_ecount_wait. And cq_time_wait is in
494 * usecs, convert that to 100ns count.
496 otx2_write64(pfvf, NIX_LF_CINTX_WAIT(qidx),
497 ((u64)(pfvf->hw.cq_time_wait * 10) << 48) |
498 ((u64)pfvf->hw.cq_qcount_wait << 32) |
499 (pfvf->hw.cq_ecount_wait - 1));
502 int __otx2_alloc_rbuf(struct otx2_nic *pfvf, struct otx2_pool *pool,
507 buf = napi_alloc_frag_align(pool->rbsize, OTX2_ALIGN);
511 *dma = dma_map_single_attrs(pfvf->dev, buf, pool->rbsize,
512 DMA_FROM_DEVICE, DMA_ATTR_SKIP_CPU_SYNC);
513 if (unlikely(dma_mapping_error(pfvf->dev, *dma))) {
521 static int otx2_alloc_rbuf(struct otx2_nic *pfvf, struct otx2_pool *pool,
527 ret = __otx2_alloc_rbuf(pfvf, pool, dma);
532 int otx2_alloc_buffer(struct otx2_nic *pfvf, struct otx2_cq_queue *cq,
535 if (unlikely(__otx2_alloc_rbuf(pfvf, cq->rbpool, dma))) {
536 struct refill_work *work;
537 struct delayed_work *dwork;
539 work = &pfvf->refill_wrk[cq->cq_idx];
540 dwork = &work->pool_refill_work;
541 /* Schedule a task if no other task is running */
542 if (!cq->refill_task_sched) {
543 cq->refill_task_sched = true;
544 schedule_delayed_work(dwork,
545 msecs_to_jiffies(100));
552 void otx2_tx_timeout(struct net_device *netdev, unsigned int txq)
554 struct otx2_nic *pfvf = netdev_priv(netdev);
556 schedule_work(&pfvf->reset_task);
558 EXPORT_SYMBOL(otx2_tx_timeout);
560 void otx2_get_mac_from_af(struct net_device *netdev)
562 struct otx2_nic *pfvf = netdev_priv(netdev);
565 err = otx2_hw_get_mac_addr(pfvf, netdev);
567 dev_warn(pfvf->dev, "Failed to read mac from hardware\n");
569 /* If AF doesn't provide a valid MAC, generate a random one */
570 if (!is_valid_ether_addr(netdev->dev_addr))
571 eth_hw_addr_random(netdev);
573 EXPORT_SYMBOL(otx2_get_mac_from_af);
575 static int otx2_get_link(struct otx2_nic *pfvf)
581 if (pfvf->hw.tx_chan_base >= CGX_CHAN_BASE) {
582 map = pfvf->hw.tx_chan_base & 0x7FF;
583 link = 4 * ((map >> 8) & 0xF) + ((map >> 4) & 0xF);
586 if (pfvf->hw.tx_chan_base < SDP_CHAN_BASE) {
587 map = pfvf->hw.tx_chan_base & 0x7FF;
588 link = pfvf->hw.cgx_links | ((map >> 8) & 0xF);
594 int otx2_txschq_config(struct otx2_nic *pfvf, int lvl)
596 struct otx2_hw *hw = &pfvf->hw;
597 struct nix_txschq_config *req;
600 req = otx2_mbox_alloc_msg_nix_txschq_cfg(&pfvf->mbox);
607 schq = hw->txschq_list[lvl][0];
608 /* Set topology e.t.c configuration */
609 if (lvl == NIX_TXSCH_LVL_SMQ) {
610 req->reg[0] = NIX_AF_SMQX_CFG(schq);
611 req->regval[0] = ((pfvf->netdev->max_mtu + OTX2_ETH_HLEN) << 8)
614 req->regval[0] |= (0x20ULL << 51) | (0x80ULL << 39) |
618 parent = hw->txschq_list[NIX_TXSCH_LVL_TL4][0];
619 req->reg[1] = NIX_AF_MDQX_PARENT(schq);
620 req->regval[1] = parent << 16;
622 /* Set DWRR quantum */
623 req->reg[2] = NIX_AF_MDQX_SCHEDULE(schq);
624 req->regval[2] = DFLT_RR_QTM;
625 } else if (lvl == NIX_TXSCH_LVL_TL4) {
626 parent = hw->txschq_list[NIX_TXSCH_LVL_TL3][0];
627 req->reg[0] = NIX_AF_TL4X_PARENT(schq);
628 req->regval[0] = parent << 16;
630 req->reg[1] = NIX_AF_TL4X_SCHEDULE(schq);
631 req->regval[1] = DFLT_RR_QTM;
632 } else if (lvl == NIX_TXSCH_LVL_TL3) {
633 parent = hw->txschq_list[NIX_TXSCH_LVL_TL2][0];
634 req->reg[0] = NIX_AF_TL3X_PARENT(schq);
635 req->regval[0] = parent << 16;
637 req->reg[1] = NIX_AF_TL3X_SCHEDULE(schq);
638 req->regval[1] = DFLT_RR_QTM;
639 } else if (lvl == NIX_TXSCH_LVL_TL2) {
640 parent = hw->txschq_list[NIX_TXSCH_LVL_TL1][0];
641 req->reg[0] = NIX_AF_TL2X_PARENT(schq);
642 req->regval[0] = parent << 16;
645 req->reg[1] = NIX_AF_TL2X_SCHEDULE(schq);
646 req->regval[1] = TXSCH_TL1_DFLT_RR_PRIO << 24 | DFLT_RR_QTM;
649 req->reg[2] = NIX_AF_TL3_TL2X_LINKX_CFG(schq,
650 otx2_get_link(pfvf));
651 /* Enable this queue and backpressure */
652 req->regval[2] = BIT_ULL(13) | BIT_ULL(12);
654 } else if (lvl == NIX_TXSCH_LVL_TL1) {
655 /* Default config for TL1.
656 * For VF this is always ignored.
659 /* Set DWRR quantum */
660 req->reg[0] = NIX_AF_TL1X_SCHEDULE(schq);
661 req->regval[0] = TXSCH_TL1_DFLT_RR_QTM;
664 req->reg[1] = NIX_AF_TL1X_TOPOLOGY(schq);
665 req->regval[1] = (TXSCH_TL1_DFLT_RR_PRIO << 1);
668 req->reg[2] = NIX_AF_TL1X_CIR(schq);
672 return otx2_sync_mbox_msg(&pfvf->mbox);
675 int otx2_txsch_alloc(struct otx2_nic *pfvf)
677 struct nix_txsch_alloc_req *req;
680 /* Get memory to put this msg */
681 req = otx2_mbox_alloc_msg_nix_txsch_alloc(&pfvf->mbox);
685 /* Request one schq per level */
686 for (lvl = 0; lvl < NIX_TXSCH_LVL_CNT; lvl++)
689 return otx2_sync_mbox_msg(&pfvf->mbox);
692 int otx2_txschq_stop(struct otx2_nic *pfvf)
694 struct nix_txsch_free_req *free_req;
697 mutex_lock(&pfvf->mbox.lock);
698 /* Free the transmit schedulers */
699 free_req = otx2_mbox_alloc_msg_nix_txsch_free(&pfvf->mbox);
701 mutex_unlock(&pfvf->mbox.lock);
705 free_req->flags = TXSCHQ_FREE_ALL;
706 err = otx2_sync_mbox_msg(&pfvf->mbox);
707 mutex_unlock(&pfvf->mbox.lock);
709 /* Clear the txschq list */
710 for (lvl = 0; lvl < NIX_TXSCH_LVL_CNT; lvl++) {
711 for (schq = 0; schq < MAX_TXSCHQ_PER_FUNC; schq++)
712 pfvf->hw.txschq_list[lvl][schq] = 0;
717 void otx2_sqb_flush(struct otx2_nic *pfvf)
719 int qidx, sqe_tail, sqe_head;
723 ptr = (u64 *)otx2_get_regaddr(pfvf, NIX_LF_SQ_OP_STATUS);
724 for (qidx = 0; qidx < pfvf->hw.tx_queues; qidx++) {
725 incr = (u64)qidx << 32;
727 val = otx2_atomic64_add(incr, ptr);
728 sqe_head = (val >> 20) & 0x3F;
729 sqe_tail = (val >> 28) & 0x3F;
730 if (sqe_head == sqe_tail)
738 /* RED and drop levels of CQ on packet reception.
739 * For CQ level is measure of emptiness ( 0x0 = full, 255 = empty).
741 #define RQ_PASS_LVL_CQ(skid, qsize) ((((skid) + 16) * 256) / (qsize))
742 #define RQ_DROP_LVL_CQ(skid, qsize) (((skid) * 256) / (qsize))
744 /* RED and drop levels of AURA for packet reception.
745 * For AURA level is measure of fullness (0x0 = empty, 255 = full).
746 * Eg: For RQ length 1K, for pass/drop level 204/230.
747 * RED accepts pkts if free pointers > 102 & <= 205.
748 * Drops pkts if free pointers < 102.
750 #define RQ_BP_LVL_AURA (255 - ((85 * 256) / 100)) /* BP when 85% is full */
751 #define RQ_PASS_LVL_AURA (255 - ((95 * 256) / 100)) /* RED when 95% is full */
752 #define RQ_DROP_LVL_AURA (255 - ((99 * 256) / 100)) /* Drop when 99% is full */
754 static int otx2_rq_init(struct otx2_nic *pfvf, u16 qidx, u16 lpb_aura)
756 struct otx2_qset *qset = &pfvf->qset;
757 struct nix_aq_enq_req *aq;
759 /* Get memory to put this msg */
760 aq = otx2_mbox_alloc_msg_nix_aq_enq(&pfvf->mbox);
766 aq->rq.pb_caching = 1;
767 aq->rq.lpb_aura = lpb_aura; /* Use large packet buffer aura */
768 aq->rq.lpb_sizem1 = (DMA_BUFFER_LEN(pfvf->rbsize) / 8) - 1;
769 aq->rq.xqe_imm_size = 0; /* Copying of packet to CQE not needed */
770 aq->rq.flow_tagw = 32; /* Copy full 32bit flow_tag to CQE header */
772 aq->rq.lpb_drop_ena = 1; /* Enable RED dropping for AURA */
773 aq->rq.xqe_drop_ena = 1; /* Enable RED dropping for CQ/SSO */
774 aq->rq.xqe_pass = RQ_PASS_LVL_CQ(pfvf->hw.rq_skid, qset->rqe_cnt);
775 aq->rq.xqe_drop = RQ_DROP_LVL_CQ(pfvf->hw.rq_skid, qset->rqe_cnt);
776 aq->rq.lpb_aura_pass = RQ_PASS_LVL_AURA;
777 aq->rq.lpb_aura_drop = RQ_DROP_LVL_AURA;
781 aq->ctype = NIX_AQ_CTYPE_RQ;
782 aq->op = NIX_AQ_INSTOP_INIT;
784 return otx2_sync_mbox_msg(&pfvf->mbox);
787 int otx2_sq_aq_init(void *dev, u16 qidx, u16 sqb_aura)
789 struct otx2_nic *pfvf = dev;
790 struct otx2_snd_queue *sq;
791 struct nix_aq_enq_req *aq;
793 sq = &pfvf->qset.sq[qidx];
794 sq->lmt_addr = (__force u64 *)(pfvf->reg_base + LMT_LF_LMTLINEX(qidx));
795 /* Get memory to put this msg */
796 aq = otx2_mbox_alloc_msg_nix_aq_enq(&pfvf->mbox);
800 aq->sq.cq = pfvf->hw.rx_queues + qidx;
801 aq->sq.max_sqe_size = NIX_MAXSQESZ_W16; /* 128 byte */
804 /* Only one SMQ is allocated, map all SQ's to that SMQ */
805 aq->sq.smq = pfvf->hw.txschq_list[NIX_TXSCH_LVL_SMQ][0];
806 aq->sq.smq_rr_quantum = DFLT_RR_QTM;
807 aq->sq.default_chan = pfvf->hw.tx_chan_base;
808 aq->sq.sqe_stype = NIX_STYPE_STF; /* Cache SQB */
809 aq->sq.sqb_aura = sqb_aura;
810 aq->sq.sq_int_ena = NIX_SQINT_BITS;
812 /* Due pipelining impact minimum 2000 unused SQ CQE's
813 * need to maintain to avoid CQ overflow.
815 aq->sq.cq_limit = ((SEND_CQ_SKID * 256) / (pfvf->qset.sqe_cnt));
819 aq->ctype = NIX_AQ_CTYPE_SQ;
820 aq->op = NIX_AQ_INSTOP_INIT;
822 return otx2_sync_mbox_msg(&pfvf->mbox);
825 static int otx2_sq_init(struct otx2_nic *pfvf, u16 qidx, u16 sqb_aura)
827 struct otx2_qset *qset = &pfvf->qset;
828 struct otx2_snd_queue *sq;
829 struct otx2_pool *pool;
832 pool = &pfvf->qset.pool[sqb_aura];
833 sq = &qset->sq[qidx];
834 sq->sqe_size = NIX_SQESZ_W16 ? 64 : 128;
835 sq->sqe_cnt = qset->sqe_cnt;
837 err = qmem_alloc(pfvf->dev, &sq->sqe, 1, sq->sqe_size);
841 err = qmem_alloc(pfvf->dev, &sq->tso_hdrs, qset->sqe_cnt,
846 sq->sqe_base = sq->sqe->base;
847 sq->sg = kcalloc(qset->sqe_cnt, sizeof(struct sg_list), GFP_KERNEL);
852 err = qmem_alloc(pfvf->dev, &sq->timestamps, qset->sqe_cnt,
853 sizeof(*sq->timestamps));
859 sq->sqe_per_sqb = (pfvf->hw.sqb_size / sq->sqe_size) - 1;
860 sq->num_sqbs = (qset->sqe_cnt + sq->sqe_per_sqb) / sq->sqe_per_sqb;
861 /* Set SQE threshold to 10% of total SQEs */
862 sq->sqe_thresh = ((sq->num_sqbs * sq->sqe_per_sqb) * 10) / 100;
863 sq->aura_id = sqb_aura;
864 sq->aura_fc_addr = pool->fc_addr->base;
865 sq->io_addr = (__force u64)otx2_get_regaddr(pfvf, NIX_LF_OP_SENDX(0));
870 return pfvf->hw_ops->sq_aq_init(pfvf, qidx, sqb_aura);
874 static int otx2_cq_init(struct otx2_nic *pfvf, u16 qidx)
876 struct otx2_qset *qset = &pfvf->qset;
877 struct nix_aq_enq_req *aq;
878 struct otx2_cq_queue *cq;
881 cq = &qset->cq[qidx];
883 if (qidx < pfvf->hw.rx_queues) {
886 cq->cqe_cnt = qset->rqe_cnt;
889 cq->cint_idx = qidx - pfvf->hw.rx_queues;
890 cq->cqe_cnt = qset->sqe_cnt;
892 cq->cqe_size = pfvf->qset.xqe_size;
894 /* Allocate memory for CQEs */
895 err = qmem_alloc(pfvf->dev, &cq->cqe, cq->cqe_cnt, cq->cqe_size);
899 /* Save CQE CPU base for faster reference */
900 cq->cqe_base = cq->cqe->base;
901 /* In case where all RQs auras point to single pool,
902 * all CQs receive buffer pool also point to same pool.
904 pool_id = ((cq->cq_type == CQ_RX) &&
905 (pfvf->hw.rqpool_cnt != pfvf->hw.rx_queues)) ? 0 : qidx;
906 cq->rbpool = &qset->pool[pool_id];
907 cq->refill_task_sched = false;
909 /* Get memory to put this msg */
910 aq = otx2_mbox_alloc_msg_nix_aq_enq(&pfvf->mbox);
915 aq->cq.qsize = Q_SIZE(cq->cqe_cnt, 4);
917 aq->cq.base = cq->cqe->iova;
918 aq->cq.cint_idx = cq->cint_idx;
919 aq->cq.cq_err_int_ena = NIX_CQERRINT_BITS;
921 aq->cq.avg_level = 255;
923 if (qidx < pfvf->hw.rx_queues) {
924 aq->cq.drop = RQ_DROP_LVL_CQ(pfvf->hw.rq_skid, cq->cqe_cnt);
927 /* Enable receive CQ backpressure */
929 aq->cq.bpid = pfvf->bpid[0];
931 /* Set backpressure level is same as cq pass level */
932 aq->cq.bp = RQ_PASS_LVL_CQ(pfvf->hw.rq_skid, qset->rqe_cnt);
937 aq->ctype = NIX_AQ_CTYPE_CQ;
938 aq->op = NIX_AQ_INSTOP_INIT;
940 return otx2_sync_mbox_msg(&pfvf->mbox);
943 static void otx2_pool_refill_task(struct work_struct *work)
945 struct otx2_cq_queue *cq;
946 struct otx2_pool *rbpool;
947 struct refill_work *wrk;
948 int qidx, free_ptrs = 0;
949 struct otx2_nic *pfvf;
952 wrk = container_of(work, struct refill_work, pool_refill_work.work);
954 qidx = wrk - pfvf->refill_wrk;
955 cq = &pfvf->qset.cq[qidx];
957 free_ptrs = cq->pool_ptrs;
959 while (cq->pool_ptrs) {
960 if (otx2_alloc_rbuf(pfvf, rbpool, &bufptr)) {
961 /* Schedule a WQ if we fails to free atleast half of the
962 * pointers else enable napi for this RQ.
964 if (!((free_ptrs - cq->pool_ptrs) > free_ptrs / 2)) {
965 struct delayed_work *dwork;
967 dwork = &wrk->pool_refill_work;
968 schedule_delayed_work(dwork,
969 msecs_to_jiffies(100));
971 cq->refill_task_sched = false;
975 pfvf->hw_ops->aura_freeptr(pfvf, qidx, bufptr + OTX2_HEAD_ROOM);
978 cq->refill_task_sched = false;
981 int otx2_config_nix_queues(struct otx2_nic *pfvf)
985 /* Initialize RX queues */
986 for (qidx = 0; qidx < pfvf->hw.rx_queues; qidx++) {
987 u16 lpb_aura = otx2_get_pool_idx(pfvf, AURA_NIX_RQ, qidx);
989 err = otx2_rq_init(pfvf, qidx, lpb_aura);
994 /* Initialize TX queues */
995 for (qidx = 0; qidx < pfvf->hw.tx_queues; qidx++) {
996 u16 sqb_aura = otx2_get_pool_idx(pfvf, AURA_NIX_SQ, qidx);
998 err = otx2_sq_init(pfvf, qidx, sqb_aura);
1003 /* Initialize completion queues */
1004 for (qidx = 0; qidx < pfvf->qset.cq_cnt; qidx++) {
1005 err = otx2_cq_init(pfvf, qidx);
1010 /* Initialize work queue for receive buffer refill */
1011 pfvf->refill_wrk = devm_kcalloc(pfvf->dev, pfvf->qset.cq_cnt,
1012 sizeof(struct refill_work), GFP_KERNEL);
1013 if (!pfvf->refill_wrk)
1016 for (qidx = 0; qidx < pfvf->qset.cq_cnt; qidx++) {
1017 pfvf->refill_wrk[qidx].pf = pfvf;
1018 INIT_DELAYED_WORK(&pfvf->refill_wrk[qidx].pool_refill_work,
1019 otx2_pool_refill_task);
1024 int otx2_config_nix(struct otx2_nic *pfvf)
1026 struct nix_lf_alloc_req *nixlf;
1027 struct nix_lf_alloc_rsp *rsp;
1030 pfvf->qset.xqe_size = NIX_XQESZ_W16 ? 128 : 512;
1032 /* Get memory to put this msg */
1033 nixlf = otx2_mbox_alloc_msg_nix_lf_alloc(&pfvf->mbox);
1037 /* Set RQ/SQ/CQ counts */
1038 nixlf->rq_cnt = pfvf->hw.rx_queues;
1039 nixlf->sq_cnt = pfvf->hw.tx_queues;
1040 nixlf->cq_cnt = pfvf->qset.cq_cnt;
1041 nixlf->rss_sz = MAX_RSS_INDIR_TBL_SIZE;
1042 nixlf->rss_grps = MAX_RSS_GROUPS;
1043 nixlf->xqe_sz = NIX_XQESZ_W16;
1044 /* We don't know absolute NPA LF idx attached.
1045 * AF will replace 'RVU_DEFAULT_PF_FUNC' with
1046 * NPA LF attached to this RVU PF/VF.
1048 nixlf->npa_func = RVU_DEFAULT_PF_FUNC;
1049 /* Disable alignment pad, enable L2 length check,
1050 * enable L4 TCP/UDP checksum verification.
1052 nixlf->rx_cfg = BIT_ULL(33) | BIT_ULL(35) | BIT_ULL(37);
1054 err = otx2_sync_mbox_msg(&pfvf->mbox);
1058 rsp = (struct nix_lf_alloc_rsp *)otx2_mbox_get_rsp(&pfvf->mbox.mbox, 0,
1061 return PTR_ERR(rsp);
1069 void otx2_sq_free_sqbs(struct otx2_nic *pfvf)
1071 struct otx2_qset *qset = &pfvf->qset;
1072 struct otx2_hw *hw = &pfvf->hw;
1073 struct otx2_snd_queue *sq;
1077 for (qidx = 0; qidx < hw->tx_queues; qidx++) {
1078 sq = &qset->sq[qidx];
1081 for (sqb = 0; sqb < sq->sqb_count; sqb++) {
1082 if (!sq->sqb_ptrs[sqb])
1084 iova = sq->sqb_ptrs[sqb];
1085 pa = otx2_iova_to_phys(pfvf->iommu_domain, iova);
1086 dma_unmap_page_attrs(pfvf->dev, iova, hw->sqb_size,
1088 DMA_ATTR_SKIP_CPU_SYNC);
1089 put_page(virt_to_page(phys_to_virt(pa)));
1095 void otx2_free_aura_ptr(struct otx2_nic *pfvf, int type)
1097 int pool_id, pool_start = 0, pool_end = 0, size = 0;
1100 if (type == AURA_NIX_SQ) {
1101 pool_start = otx2_get_pool_idx(pfvf, type, 0);
1102 pool_end = pool_start + pfvf->hw.sqpool_cnt;
1103 size = pfvf->hw.sqb_size;
1105 if (type == AURA_NIX_RQ) {
1106 pool_start = otx2_get_pool_idx(pfvf, type, 0);
1107 pool_end = pfvf->hw.rqpool_cnt;
1108 size = pfvf->rbsize;
1111 /* Free SQB and RQB pointers from the aura pool */
1112 for (pool_id = pool_start; pool_id < pool_end; pool_id++) {
1113 iova = otx2_aura_allocptr(pfvf, pool_id);
1115 if (type == AURA_NIX_RQ)
1116 iova -= OTX2_HEAD_ROOM;
1118 pa = otx2_iova_to_phys(pfvf->iommu_domain, iova);
1119 dma_unmap_page_attrs(pfvf->dev, iova, size,
1121 DMA_ATTR_SKIP_CPU_SYNC);
1122 put_page(virt_to_page(phys_to_virt(pa)));
1123 iova = otx2_aura_allocptr(pfvf, pool_id);
1128 void otx2_aura_pool_free(struct otx2_nic *pfvf)
1130 struct otx2_pool *pool;
1133 if (!pfvf->qset.pool)
1136 for (pool_id = 0; pool_id < pfvf->hw.pool_cnt; pool_id++) {
1137 pool = &pfvf->qset.pool[pool_id];
1138 qmem_free(pfvf->dev, pool->stack);
1139 qmem_free(pfvf->dev, pool->fc_addr);
1141 devm_kfree(pfvf->dev, pfvf->qset.pool);
1142 pfvf->qset.pool = NULL;
1145 static int otx2_aura_init(struct otx2_nic *pfvf, int aura_id,
1146 int pool_id, int numptrs)
1148 struct npa_aq_enq_req *aq;
1149 struct otx2_pool *pool;
1152 pool = &pfvf->qset.pool[pool_id];
1154 /* Allocate memory for HW to update Aura count.
1155 * Alloc one cache line, so that it fits all FC_STYPE modes.
1157 if (!pool->fc_addr) {
1158 err = qmem_alloc(pfvf->dev, &pool->fc_addr, 1, OTX2_ALIGN);
1163 /* Initialize this aura's context via AF */
1164 aq = otx2_mbox_alloc_msg_npa_aq_enq(&pfvf->mbox);
1166 /* Shared mbox memory buffer is full, flush it and retry */
1167 err = otx2_sync_mbox_msg(&pfvf->mbox);
1170 aq = otx2_mbox_alloc_msg_npa_aq_enq(&pfvf->mbox);
1175 aq->aura_id = aura_id;
1176 /* Will be filled by AF with correct pool context address */
1177 aq->aura.pool_addr = pool_id;
1178 aq->aura.pool_caching = 1;
1179 aq->aura.shift = ilog2(numptrs) - 8;
1180 aq->aura.count = numptrs;
1181 aq->aura.limit = numptrs;
1182 aq->aura.avg_level = 255;
1184 aq->aura.fc_ena = 1;
1185 aq->aura.fc_addr = pool->fc_addr->iova;
1186 aq->aura.fc_hyst_bits = 0; /* Store count on all updates */
1188 /* Enable backpressure for RQ aura */
1189 if (aura_id < pfvf->hw.rqpool_cnt) {
1190 aq->aura.bp_ena = 0;
1191 aq->aura.nix0_bpid = pfvf->bpid[0];
1192 /* Set backpressure level for RQ's Aura */
1193 aq->aura.bp = RQ_BP_LVL_AURA;
1197 aq->ctype = NPA_AQ_CTYPE_AURA;
1198 aq->op = NPA_AQ_INSTOP_INIT;
1203 static int otx2_pool_init(struct otx2_nic *pfvf, u16 pool_id,
1204 int stack_pages, int numptrs, int buf_size)
1206 struct npa_aq_enq_req *aq;
1207 struct otx2_pool *pool;
1210 pool = &pfvf->qset.pool[pool_id];
1211 /* Alloc memory for stack which is used to store buffer pointers */
1212 err = qmem_alloc(pfvf->dev, &pool->stack,
1213 stack_pages, pfvf->hw.stack_pg_bytes);
1217 pool->rbsize = buf_size;
1219 /* Set LMTST addr for NPA batch free */
1220 if (test_bit(CN10K_LMTST, &pfvf->hw.cap_flag))
1221 pool->lmt_addr = (__force u64 *)((u64)pfvf->hw.npa_lmt_base +
1222 (pool_id * LMT_LINE_SIZE));
1224 /* Initialize this pool's context via AF */
1225 aq = otx2_mbox_alloc_msg_npa_aq_enq(&pfvf->mbox);
1227 /* Shared mbox memory buffer is full, flush it and retry */
1228 err = otx2_sync_mbox_msg(&pfvf->mbox);
1230 qmem_free(pfvf->dev, pool->stack);
1233 aq = otx2_mbox_alloc_msg_npa_aq_enq(&pfvf->mbox);
1235 qmem_free(pfvf->dev, pool->stack);
1240 aq->aura_id = pool_id;
1241 aq->pool.stack_base = pool->stack->iova;
1242 aq->pool.stack_caching = 1;
1244 aq->pool.buf_size = buf_size / 128;
1245 aq->pool.stack_max_pages = stack_pages;
1246 aq->pool.shift = ilog2(numptrs) - 8;
1247 aq->pool.ptr_start = 0;
1248 aq->pool.ptr_end = ~0ULL;
1251 aq->ctype = NPA_AQ_CTYPE_POOL;
1252 aq->op = NPA_AQ_INSTOP_INIT;
1257 int otx2_sq_aura_pool_init(struct otx2_nic *pfvf)
1259 int qidx, pool_id, stack_pages, num_sqbs;
1260 struct otx2_qset *qset = &pfvf->qset;
1261 struct otx2_hw *hw = &pfvf->hw;
1262 struct otx2_snd_queue *sq;
1263 struct otx2_pool *pool;
1267 /* Calculate number of SQBs needed.
1269 * For a 128byte SQE, and 4K size SQB, 31 SQEs will fit in one SQB.
1270 * Last SQE is used for pointing to next SQB.
1272 num_sqbs = (hw->sqb_size / 128) - 1;
1273 num_sqbs = (qset->sqe_cnt + num_sqbs) / num_sqbs;
1275 /* Get no of stack pages needed */
1277 (num_sqbs + hw->stack_pg_ptrs - 1) / hw->stack_pg_ptrs;
1279 for (qidx = 0; qidx < hw->tx_queues; qidx++) {
1280 pool_id = otx2_get_pool_idx(pfvf, AURA_NIX_SQ, qidx);
1281 /* Initialize aura context */
1282 err = otx2_aura_init(pfvf, pool_id, pool_id, num_sqbs);
1286 /* Initialize pool context */
1287 err = otx2_pool_init(pfvf, pool_id, stack_pages,
1288 num_sqbs, hw->sqb_size);
1293 /* Flush accumulated messages */
1294 err = otx2_sync_mbox_msg(&pfvf->mbox);
1298 /* Allocate pointers and free them to aura/pool */
1299 for (qidx = 0; qidx < hw->tx_queues; qidx++) {
1300 pool_id = otx2_get_pool_idx(pfvf, AURA_NIX_SQ, qidx);
1301 pool = &pfvf->qset.pool[pool_id];
1303 sq = &qset->sq[qidx];
1305 sq->sqb_ptrs = kcalloc(num_sqbs, sizeof(*sq->sqb_ptrs), GFP_KERNEL);
1309 for (ptr = 0; ptr < num_sqbs; ptr++) {
1310 if (otx2_alloc_rbuf(pfvf, pool, &bufptr))
1312 pfvf->hw_ops->aura_freeptr(pfvf, pool_id, bufptr);
1313 sq->sqb_ptrs[sq->sqb_count++] = (u64)bufptr;
1319 otx2_mbox_reset(&pfvf->mbox.mbox, 0);
1320 otx2_aura_pool_free(pfvf);
1324 int otx2_rq_aura_pool_init(struct otx2_nic *pfvf)
1326 struct otx2_hw *hw = &pfvf->hw;
1327 int stack_pages, pool_id, rq;
1328 struct otx2_pool *pool;
1329 int err, ptr, num_ptrs;
1332 num_ptrs = pfvf->qset.rqe_cnt;
1335 (num_ptrs + hw->stack_pg_ptrs - 1) / hw->stack_pg_ptrs;
1337 for (rq = 0; rq < hw->rx_queues; rq++) {
1338 pool_id = otx2_get_pool_idx(pfvf, AURA_NIX_RQ, rq);
1339 /* Initialize aura context */
1340 err = otx2_aura_init(pfvf, pool_id, pool_id, num_ptrs);
1344 for (pool_id = 0; pool_id < hw->rqpool_cnt; pool_id++) {
1345 err = otx2_pool_init(pfvf, pool_id, stack_pages,
1346 num_ptrs, pfvf->rbsize);
1351 /* Flush accumulated messages */
1352 err = otx2_sync_mbox_msg(&pfvf->mbox);
1356 /* Allocate pointers and free them to aura/pool */
1357 for (pool_id = 0; pool_id < hw->rqpool_cnt; pool_id++) {
1358 pool = &pfvf->qset.pool[pool_id];
1359 for (ptr = 0; ptr < num_ptrs; ptr++) {
1360 if (otx2_alloc_rbuf(pfvf, pool, &bufptr))
1362 pfvf->hw_ops->aura_freeptr(pfvf, pool_id,
1363 bufptr + OTX2_HEAD_ROOM);
1369 otx2_mbox_reset(&pfvf->mbox.mbox, 0);
1370 otx2_aura_pool_free(pfvf);
1374 int otx2_config_npa(struct otx2_nic *pfvf)
1376 struct otx2_qset *qset = &pfvf->qset;
1377 struct npa_lf_alloc_req *npalf;
1378 struct otx2_hw *hw = &pfvf->hw;
1381 /* Pool - Stack of free buffer pointers
1382 * Aura - Alloc/frees pointers from/to pool for NIX DMA.
1388 qset->pool = devm_kcalloc(pfvf->dev, hw->pool_cnt,
1389 sizeof(struct otx2_pool), GFP_KERNEL);
1393 /* Get memory to put this msg */
1394 npalf = otx2_mbox_alloc_msg_npa_lf_alloc(&pfvf->mbox);
1398 /* Set aura and pool counts */
1399 npalf->nr_pools = hw->pool_cnt;
1400 aura_cnt = ilog2(roundup_pow_of_two(hw->pool_cnt));
1401 npalf->aura_sz = (aura_cnt >= ilog2(128)) ? (aura_cnt - 6) : 1;
1403 return otx2_sync_mbox_msg(&pfvf->mbox);
1406 int otx2_detach_resources(struct mbox *mbox)
1408 struct rsrc_detach *detach;
1410 mutex_lock(&mbox->lock);
1411 detach = otx2_mbox_alloc_msg_detach_resources(mbox);
1413 mutex_unlock(&mbox->lock);
1418 detach->partial = false;
1420 /* Send detach request to AF */
1421 otx2_mbox_msg_send(&mbox->mbox, 0);
1422 mutex_unlock(&mbox->lock);
1425 EXPORT_SYMBOL(otx2_detach_resources);
1427 int otx2_attach_npa_nix(struct otx2_nic *pfvf)
1429 struct rsrc_attach *attach;
1430 struct msg_req *msix;
1433 mutex_lock(&pfvf->mbox.lock);
1434 /* Get memory to put this msg */
1435 attach = otx2_mbox_alloc_msg_attach_resources(&pfvf->mbox);
1437 mutex_unlock(&pfvf->mbox.lock);
1441 attach->npalf = true;
1442 attach->nixlf = true;
1444 /* Send attach request to AF */
1445 err = otx2_sync_mbox_msg(&pfvf->mbox);
1447 mutex_unlock(&pfvf->mbox.lock);
1451 pfvf->nix_blkaddr = BLKADDR_NIX0;
1453 /* If the platform has two NIX blocks then LF may be
1454 * allocated from NIX1.
1456 if (otx2_read64(pfvf, RVU_PF_BLOCK_ADDRX_DISC(BLKADDR_NIX1)) & 0x1FFULL)
1457 pfvf->nix_blkaddr = BLKADDR_NIX1;
1459 /* Get NPA and NIX MSIX vector offsets */
1460 msix = otx2_mbox_alloc_msg_msix_offset(&pfvf->mbox);
1462 mutex_unlock(&pfvf->mbox.lock);
1466 err = otx2_sync_mbox_msg(&pfvf->mbox);
1468 mutex_unlock(&pfvf->mbox.lock);
1471 mutex_unlock(&pfvf->mbox.lock);
1473 if (pfvf->hw.npa_msixoff == MSIX_VECTOR_INVALID ||
1474 pfvf->hw.nix_msixoff == MSIX_VECTOR_INVALID) {
1476 "RVUPF: Invalid MSIX vector offset for NPA/NIX\n");
1482 EXPORT_SYMBOL(otx2_attach_npa_nix);
1484 void otx2_ctx_disable(struct mbox *mbox, int type, bool npa)
1486 struct hwctx_disable_req *req;
1488 mutex_lock(&mbox->lock);
1489 /* Request AQ to disable this context */
1491 req = otx2_mbox_alloc_msg_npa_hwctx_disable(mbox);
1493 req = otx2_mbox_alloc_msg_nix_hwctx_disable(mbox);
1496 mutex_unlock(&mbox->lock);
1502 if (otx2_sync_mbox_msg(mbox))
1503 dev_err(mbox->pfvf->dev, "%s failed to disable context\n",
1506 mutex_unlock(&mbox->lock);
1509 int otx2_nix_config_bp(struct otx2_nic *pfvf, bool enable)
1511 struct nix_bp_cfg_req *req;
1514 req = otx2_mbox_alloc_msg_nix_bp_enable(&pfvf->mbox);
1516 req = otx2_mbox_alloc_msg_nix_bp_disable(&pfvf->mbox);
1523 req->bpid_per_chan = 0;
1525 return otx2_sync_mbox_msg(&pfvf->mbox);
1528 /* Mbox message handlers */
1529 void mbox_handler_cgx_stats(struct otx2_nic *pfvf,
1530 struct cgx_stats_rsp *rsp)
1534 for (id = 0; id < CGX_RX_STATS_COUNT; id++)
1535 pfvf->hw.cgx_rx_stats[id] = rsp->rx_stats[id];
1536 for (id = 0; id < CGX_TX_STATS_COUNT; id++)
1537 pfvf->hw.cgx_tx_stats[id] = rsp->tx_stats[id];
1540 void mbox_handler_cgx_fec_stats(struct otx2_nic *pfvf,
1541 struct cgx_fec_stats_rsp *rsp)
1543 pfvf->hw.cgx_fec_corr_blks += rsp->fec_corr_blks;
1544 pfvf->hw.cgx_fec_uncorr_blks += rsp->fec_uncorr_blks;
1547 void mbox_handler_nix_txsch_alloc(struct otx2_nic *pf,
1548 struct nix_txsch_alloc_rsp *rsp)
1552 /* Setup transmit scheduler list */
1553 for (lvl = 0; lvl < NIX_TXSCH_LVL_CNT; lvl++)
1554 for (schq = 0; schq < rsp->schq[lvl]; schq++)
1555 pf->hw.txschq_list[lvl][schq] =
1556 rsp->schq_list[lvl][schq];
1558 EXPORT_SYMBOL(mbox_handler_nix_txsch_alloc);
1560 void mbox_handler_npa_lf_alloc(struct otx2_nic *pfvf,
1561 struct npa_lf_alloc_rsp *rsp)
1563 pfvf->hw.stack_pg_ptrs = rsp->stack_pg_ptrs;
1564 pfvf->hw.stack_pg_bytes = rsp->stack_pg_bytes;
1566 EXPORT_SYMBOL(mbox_handler_npa_lf_alloc);
1568 void mbox_handler_nix_lf_alloc(struct otx2_nic *pfvf,
1569 struct nix_lf_alloc_rsp *rsp)
1571 pfvf->hw.sqb_size = rsp->sqb_size;
1572 pfvf->hw.rx_chan_base = rsp->rx_chan_base;
1573 pfvf->hw.tx_chan_base = rsp->tx_chan_base;
1574 pfvf->hw.lso_tsov4_idx = rsp->lso_tsov4_idx;
1575 pfvf->hw.lso_tsov6_idx = rsp->lso_tsov6_idx;
1576 pfvf->hw.cgx_links = rsp->cgx_links;
1577 pfvf->hw.lbk_links = rsp->lbk_links;
1579 EXPORT_SYMBOL(mbox_handler_nix_lf_alloc);
1581 void mbox_handler_msix_offset(struct otx2_nic *pfvf,
1582 struct msix_offset_rsp *rsp)
1584 pfvf->hw.npa_msixoff = rsp->npa_msixoff;
1585 pfvf->hw.nix_msixoff = rsp->nix_msixoff;
1587 EXPORT_SYMBOL(mbox_handler_msix_offset);
1589 void mbox_handler_nix_bp_enable(struct otx2_nic *pfvf,
1590 struct nix_bp_cfg_rsp *rsp)
1594 for (chan = 0; chan < rsp->chan_cnt; chan++) {
1595 chan_id = ((rsp->chan_bpid[chan] >> 10) & 0x7F);
1596 pfvf->bpid[chan_id] = rsp->chan_bpid[chan] & 0x3FF;
1599 EXPORT_SYMBOL(mbox_handler_nix_bp_enable);
1601 void otx2_free_cints(struct otx2_nic *pfvf, int n)
1603 struct otx2_qset *qset = &pfvf->qset;
1604 struct otx2_hw *hw = &pfvf->hw;
1607 for (qidx = 0, irq = hw->nix_msixoff + NIX_LF_CINT_VEC_START;
1610 int vector = pci_irq_vector(pfvf->pdev, irq);
1612 irq_set_affinity_hint(vector, NULL);
1613 free_cpumask_var(hw->affinity_mask[irq]);
1614 free_irq(vector, &qset->napi[qidx]);
1618 void otx2_set_cints_affinity(struct otx2_nic *pfvf)
1620 struct otx2_hw *hw = &pfvf->hw;
1621 int vec, cpu, irq, cint;
1623 vec = hw->nix_msixoff + NIX_LF_CINT_VEC_START;
1624 cpu = cpumask_first(cpu_online_mask);
1627 for (cint = 0; cint < pfvf->hw.cint_cnt; cint++, vec++) {
1628 if (!alloc_cpumask_var(&hw->affinity_mask[vec], GFP_KERNEL))
1631 cpumask_set_cpu(cpu, hw->affinity_mask[vec]);
1633 irq = pci_irq_vector(pfvf->pdev, vec);
1634 irq_set_affinity_hint(irq, hw->affinity_mask[vec]);
1636 cpu = cpumask_next(cpu, cpu_online_mask);
1637 if (unlikely(cpu >= nr_cpu_ids))
1642 u16 otx2_get_max_mtu(struct otx2_nic *pfvf)
1644 struct nix_hw_info *rsp;
1645 struct msg_req *req;
1649 mutex_lock(&pfvf->mbox.lock);
1651 req = otx2_mbox_alloc_msg_nix_get_hw_info(&pfvf->mbox);
1657 rc = otx2_sync_mbox_msg(&pfvf->mbox);
1659 rsp = (struct nix_hw_info *)
1660 otx2_mbox_get_rsp(&pfvf->mbox.mbox, 0, &req->hdr);
1662 /* HW counts VLAN insertion bytes (8 for double tag)
1663 * irrespective of whether SQE is requesting to insert VLAN
1664 * in the packet or not. Hence these 8 bytes have to be
1665 * discounted from max packet size otherwise HW will throw
1668 max_mtu = rsp->max_mtu - 8 - OTX2_ETH_HLEN;
1672 mutex_unlock(&pfvf->mbox.lock);
1675 "Failed to get MTU from hardware setting default value(1500)\n");
1680 EXPORT_SYMBOL(otx2_get_max_mtu);
1682 #define M(_name, _id, _fn_name, _req_type, _rsp_type) \
1684 otx2_mbox_up_handler_ ## _fn_name(struct otx2_nic *pfvf, \
1685 struct _req_type *req, \
1686 struct _rsp_type *rsp) \
1688 /* Nothing to do here */ \
1691 EXPORT_SYMBOL(otx2_mbox_up_handler_ ## _fn_name);
1692 MBOX_UP_CGX_MESSAGES