1 /* SPDX-License-Identifier: GPL-2.0 */
2 /* Marvell RVU Admin Function driver
4 * Copyright (C) 2018 Marvell.
11 /* RVU Block revision IDs */
12 #define RVU_BLK_RVUM_REVID 0x01
14 #define RVU_MULTI_BLK_VER 0x7ULL
16 /* RVU Block Address Enumeration */
17 enum rvu_block_addr_e {
18 BLKADDR_RVUM = 0x0ULL,
20 BLKADDR_MSIX = 0x2ULL,
22 BLKADDR_NIX0 = 0x4ULL,
23 BLKADDR_NIX1 = 0x5ULL,
26 BLKADDR_SSOW = 0x8ULL,
28 BLKADDR_CPT0 = 0xaULL,
29 BLKADDR_CPT1 = 0xbULL,
30 BLKADDR_NDC_NIX0_RX = 0xcULL,
31 BLKADDR_NDC_NIX0_TX = 0xdULL,
32 BLKADDR_NDC_NPA0 = 0xeULL,
33 BLKADDR_NDC_NIX1_RX = 0x10ULL,
34 BLKADDR_NDC_NIX1_TX = 0x11ULL,
35 BLKADDR_APR = 0x16ULL,
39 /* RVU Block Type Enumeration */
40 enum rvu_block_type_e {
55 /* RVU Admin function Interrupt Vector Enumeration */
56 enum rvu_af_int_vec_e {
57 RVU_AF_INT_VEC_POISON = 0x0,
58 RVU_AF_INT_VEC_PFFLR = 0x1,
59 RVU_AF_INT_VEC_PFME = 0x2,
60 RVU_AF_INT_VEC_GEN = 0x3,
61 RVU_AF_INT_VEC_MBOX = 0x4,
62 RVU_AF_INT_VEC_CNT = 0x5,
65 /* CPT Admin function Interrupt Vector Enumeration */
66 enum cpt_af_int_vec_e {
67 CPT_AF_INT_VEC_FLT0 = 0x0,
68 CPT_AF_INT_VEC_FLT1 = 0x1,
69 CPT_AF_INT_VEC_RVU = 0x2,
70 CPT_AF_INT_VEC_RAS = 0x3,
71 CPT_AF_INT_VEC_CNT = 0x4,
74 enum cpt_10k_af_int_vec_e {
75 CPT_10K_AF_INT_VEC_FLT0 = 0x0,
76 CPT_10K_AF_INT_VEC_FLT1 = 0x1,
77 CPT_10K_AF_INT_VEC_FLT2 = 0x2,
78 CPT_10K_AF_INT_VEC_RVU = 0x3,
79 CPT_10K_AF_INT_VEC_RAS = 0x4,
80 CPT_10K_AF_INT_VEC_CNT = 0x5,
83 /* NPA Admin function Interrupt Vector Enumeration */
84 enum npa_af_int_vec_e {
85 NPA_AF_INT_VEC_RVU = 0x0,
86 NPA_AF_INT_VEC_GEN = 0x1,
87 NPA_AF_INT_VEC_AQ_DONE = 0x2,
88 NPA_AF_INT_VEC_AF_ERR = 0x3,
89 NPA_AF_INT_VEC_POISON = 0x4,
90 NPA_AF_INT_VEC_CNT = 0x5,
93 /* NIX Admin function Interrupt Vector Enumeration */
94 enum nix_af_int_vec_e {
95 NIX_AF_INT_VEC_RVU = 0x0,
96 NIX_AF_INT_VEC_GEN = 0x1,
97 NIX_AF_INT_VEC_AQ_DONE = 0x2,
98 NIX_AF_INT_VEC_AF_ERR = 0x3,
99 NIX_AF_INT_VEC_POISON = 0x4,
100 NIX_AF_INT_VEC_CNT = 0x5,
104 * RVU PF Interrupt Vector Enumeration
106 enum rvu_pf_int_vec_e {
107 RVU_PF_INT_VEC_VFFLR0 = 0x0,
108 RVU_PF_INT_VEC_VFFLR1 = 0x1,
109 RVU_PF_INT_VEC_VFME0 = 0x2,
110 RVU_PF_INT_VEC_VFME1 = 0x3,
111 RVU_PF_INT_VEC_VFPF_MBOX0 = 0x4,
112 RVU_PF_INT_VEC_VFPF_MBOX1 = 0x5,
113 RVU_PF_INT_VEC_AFPF_MBOX = 0x6,
114 RVU_PF_INT_VEC_CNT = 0x7,
117 /* NPA admin queue completion enumeration */
119 NPA_AQ_COMP_NOTDONE = 0x0,
120 NPA_AQ_COMP_GOOD = 0x1,
121 NPA_AQ_COMP_SWERR = 0x2,
122 NPA_AQ_COMP_CTX_POISON = 0x3,
123 NPA_AQ_COMP_CTX_FAULT = 0x4,
124 NPA_AQ_COMP_LOCKERR = 0x5,
127 /* NPA admin queue context types */
129 NPA_AQ_CTYPE_AURA = 0x0,
130 NPA_AQ_CTYPE_POOL = 0x1,
133 /* NPA admin queue instruction opcodes */
135 NPA_AQ_INSTOP_NOP = 0x0,
136 NPA_AQ_INSTOP_INIT = 0x1,
137 NPA_AQ_INSTOP_WRITE = 0x2,
138 NPA_AQ_INSTOP_READ = 0x3,
139 NPA_AQ_INSTOP_LOCK = 0x4,
140 NPA_AQ_INSTOP_UNLOCK = 0x5,
143 /* ALLOC/FREE input queues Enumeration from coprocessors */
145 NPA_INPQ_NIX0_RX = 0x0,
146 NPA_INPQ_NIX0_TX = 0x1,
147 NPA_INPQ_NIX1_RX = 0x2,
148 NPA_INPQ_NIX1_TX = 0x3,
152 NPA_INPQ_AURA_OP = 0xe,
153 NPA_INPQ_INTERNAL_RSV = 0xf,
156 /* NPA admin queue instruction structure */
157 struct npa_aq_inst_s {
161 u64 reserved_17_23 : 7;
163 u64 reserved_44_62 : 19;
165 u64 res_addr; /* W1 */
168 /* NPA admin queue result structure */
169 struct npa_aq_res_s {
174 u64 reserved_17_63 : 47;
175 u64 reserved_64_127; /* W1 */
179 u64 pool_addr; /* W0 */
180 u64 ena : 1; /* W1 */
182 u64 pool_caching : 1;
183 u64 pool_way_mask : 16;
186 u64 pool_drop_ena : 1;
187 u64 aura_drop_ena : 1;
189 u64 reserved_98_103 : 6;
192 u64 reserved_118_119 : 2;
194 u64 count : 36; /* W2 */
195 u64 reserved_164_167 : 4;
197 u64 reserved_177_179 : 3;
199 u64 reserved_189_191 : 3;
200 u64 limit : 36; /* W3 */
201 u64 reserved_228_231 : 4;
203 u64 reserved_241_243 : 3;
206 u64 fc_up_crossing : 1;
208 u64 fc_hyst_bits : 4;
209 u64 reserved_252_255 : 4;
210 u64 fc_addr; /* W4 */
211 u64 pool_drop : 8; /* W5 */
212 u64 update_time : 16;
216 u64 thresh_int_ena : 1;
218 u64 reserved_363 : 1;
219 u64 thresh_qint_idx : 7;
220 u64 reserved_371 : 1;
221 u64 err_qint_idx : 7;
222 u64 reserved_379_383 : 5;
223 u64 thresh : 36; /* W6*/
224 u64 rsvd_423_420 : 4;
226 u64 reserved_435_447 : 13;
227 u64 reserved_448_511; /* W7 */
231 u64 stack_base; /* W0 */
234 u64 reserved_66_67 : 2;
235 u64 stack_caching : 1;
236 u64 reserved_70_71 : 3;
237 u64 stack_way_mask : 16;
239 u64 reserved_100_103 : 4;
241 u64 reserved_115_127 : 13;
242 u64 stack_max_pages : 32;
243 u64 stack_pages : 32;
245 u64 reserved_240_255 : 16;
246 u64 stack_offset : 4;
247 u64 reserved_260_263 : 4;
249 u64 reserved_270_271 : 2;
254 u64 fc_hyst_bits : 4;
255 u64 fc_up_crossing : 1;
257 u64 reserved_298_299 : 2;
258 u64 update_time : 16;
259 u64 reserved_316_319 : 4;
260 u64 fc_addr; /* W5 */
261 u64 ptr_start; /* W6 */
262 u64 ptr_end; /* W7 */
263 u64 reserved_512_535 : 24;
267 u64 thresh_int_ena : 1;
269 u64 reserved_555 : 1;
270 u64 thresh_qint_idx : 7;
271 u64 reserved_563 : 1;
272 u64 err_qint_idx : 7;
273 u64 reserved_571_575 : 5;
275 u64 rsvd_615_612 : 4;
277 u64 reserved_627_639 : 13;
278 u64 reserved_640_703; /* W10 */
279 u64 reserved_704_767; /* W11 */
280 u64 reserved_768_831; /* W12 */
281 u64 reserved_832_895; /* W13 */
282 u64 reserved_896_959; /* W14 */
283 u64 reserved_960_1023; /* W15 */
286 /* NIX admin queue completion status */
288 NIX_AQ_COMP_NOTDONE = 0x0,
289 NIX_AQ_COMP_GOOD = 0x1,
290 NIX_AQ_COMP_SWERR = 0x2,
291 NIX_AQ_COMP_CTX_POISON = 0x3,
292 NIX_AQ_COMP_CTX_FAULT = 0x4,
293 NIX_AQ_COMP_LOCKERR = 0x5,
294 NIX_AQ_COMP_SQB_ALLOC_FAIL = 0x6,
297 /* NIX admin queue context types */
299 NIX_AQ_CTYPE_RQ = 0x0,
300 NIX_AQ_CTYPE_SQ = 0x1,
301 NIX_AQ_CTYPE_CQ = 0x2,
302 NIX_AQ_CTYPE_MCE = 0x3,
303 NIX_AQ_CTYPE_RSS = 0x4,
304 NIX_AQ_CTYPE_DYNO = 0x5,
305 NIX_AQ_CTYPE_BANDPROF = 0x6,
308 /* NIX admin queue instruction opcodes */
310 NIX_AQ_INSTOP_NOP = 0x0,
311 NIX_AQ_INSTOP_INIT = 0x1,
312 NIX_AQ_INSTOP_WRITE = 0x2,
313 NIX_AQ_INSTOP_READ = 0x3,
314 NIX_AQ_INSTOP_LOCK = 0x4,
315 NIX_AQ_INSTOP_UNLOCK = 0x5,
318 /* NIX admin queue instruction structure */
319 struct nix_aq_inst_s {
323 u64 reserved_17_23 : 7;
325 u64 reserved_44_62 : 19;
327 u64 res_addr; /* W1 */
330 /* NIX admin queue result structure */
331 struct nix_aq_res_s {
336 u64 reserved_17_63 : 47;
337 u64 reserved_64_127; /* W1 */
340 /* NIX Completion queue context structure */
341 struct nix_cq_ctx_s {
357 u64 update_time : 16;
362 u64 cpt_drop_err_en : 1;
365 u64 stash_thresh : 4;
369 u64 rsvd_234_235 : 2;
372 u64 cq_err_int_ena : 8;
375 /* CN10K NIX Receive queue context structure */
376 struct nix_cn10k_rq_ctx_s {
384 u64 csum_il4_dis : 1;
385 u64 csum_ol4_dis : 1;
397 u64 xqe_drop_ena : 1;
398 u64 spb_drop_ena : 1;
399 u64 lpb_drop_ena : 1;
401 u64 ipsecd_drop_ena : 1;
403 u64 rsvd_127_125 : 3;
404 u64 band_prof_id : 10; /* W2 */
409 u64 rsvd_150_148 : 3;
415 u64 xqe_imm_size : 6;
416 u64 rsvd_189_184 : 6;
417 u64 xqe_imm_copy : 1;
418 u64 xqe_hdr_split : 1;
419 u64 xqe_drop : 8; /* W3 */
421 u64 wqe_pool_drop : 8;
422 u64 wqe_pool_pass : 8;
423 u64 spb_aura_drop : 8;
424 u64 spb_aura_pass : 8;
425 u64 spb_pool_drop : 8;
426 u64 spb_pool_pass : 8;
427 u64 lpb_aura_drop : 8; /* W4 */
428 u64 lpb_aura_pass : 8;
429 u64 lpb_pool_drop : 8;
430 u64 lpb_pool_pass : 8;
431 u64 rsvd_291_288 : 4;
435 u64 rsvd_319_315 : 5;
436 u64 ltag : 24; /* W5 */
443 u64 max_vsize_exp : 4;
445 u64 rsvd_383_382 : 2;
446 u64 octs : 48; /* W6 */
447 u64 rsvd_447_432 : 16;
448 u64 pkts : 48; /* W7 */
449 u64 rsvd_511_496 : 16;
450 u64 drop_octs : 48; /* W8 */
451 u64 rsvd_575_560 : 16;
452 u64 drop_pkts : 48; /* W9 */
453 u64 rsvd_639_624 : 16;
454 u64 re_pkts : 48; /* W10 */
455 u64 rsvd_703_688 : 16;
456 u64 rsvd_767_704; /* W11 */
457 u64 rsvd_831_768; /* W12 */
458 u64 rsvd_895_832; /* W13 */
459 u64 rsvd_959_896; /* W14 */
460 u64 rsvd_1023_960; /* W15 */
463 /* CN10K NIX Send queue context structure */
464 struct nix_cn10k_sq_ctx_s {
470 u64 sqe_way_mask : 16;
471 u64 smq : 10; /* W1 */
475 u64 smq_rr_weight : 14;
476 u64 default_chan : 12;
478 u64 rsvd_120_119 : 2;
479 u64 smq_rr_count_lb : 7;
480 u64 smq_rr_count_ub : 25; /* W2 */
486 u64 max_sqe_size : 2; /* W3 */
490 u64 smq_next_sq : 20;
491 u64 smq_lso_segnum : 8;
493 u64 smenq_offset : 6;
495 u64 smenq_next_sqb_vld : 1;
497 u64 smq_next_sq_vld : 1;
498 u64 rsvd_255_253 : 3;
499 u64 next_sqb : 64; /* W4 */
500 u64 tail_sqb : 64; /* W5 */
501 u64 smenq_sqb : 64; /* W6 */
502 u64 smenq_next_sqb : 64; /* W7 */
503 u64 head_sqb : 64; /* W8 */
504 u64 rsvd_583_576 : 8; /* W9 */
505 u64 vfi_lso_total : 18;
506 u64 vfi_lso_sizem1 : 3;
508 u64 vfi_lso_mps : 14;
509 u64 vfi_lso_vlan0_ins_ena : 1;
510 u64 vfi_lso_vlan1_ins_ena : 1;
512 u64 rsvd_639_630 : 10;
513 u64 scm_lso_rem : 18; /* W10 */
514 u64 rsvd_703_658 : 46;
515 u64 octs : 48; /* W11 */
516 u64 rsvd_767_752 : 16;
517 u64 pkts : 48; /* W12 */
518 u64 rsvd_831_816 : 16;
519 u64 rsvd_895_832 : 64; /* W13 */
520 u64 dropped_octs : 48;
521 u64 rsvd_959_944 : 16;
522 u64 dropped_pkts : 48;
523 u64 rsvd_1023_1008 : 16;
526 /* NIX Receive queue context structure */
527 struct nix_rq_ctx_s {
541 u64 xqe_drop_ena : 1;
542 u64 spb_drop_ena : 1;
543 u64 lpb_drop_ena : 1;
544 u64 rsvd_127_122 : 6;
545 u64 rsvd_139_128 : 12; /* W2 */
548 u64 rsvd_150_148 : 3;
554 u64 xqe_imm_size : 6;
555 u64 rsvd_189_184 : 6;
556 u64 xqe_imm_copy : 1;
557 u64 xqe_hdr_split : 1;
558 u64 xqe_drop : 8; /* W3*/
560 u64 wqe_pool_drop : 8;
561 u64 wqe_pool_pass : 8;
562 u64 spb_aura_drop : 8;
563 u64 spb_aura_pass : 8;
564 u64 spb_pool_drop : 8;
565 u64 spb_pool_pass : 8;
566 u64 lpb_aura_drop : 8; /* W4 */
567 u64 lpb_aura_pass : 8;
568 u64 lpb_pool_drop : 8;
569 u64 lpb_pool_pass : 8;
570 u64 rsvd_291_288 : 4;
574 u64 rsvd_319_315 : 5;
575 u64 ltag : 24; /* W5 */
579 u64 rsvd_383_366 : 18;
580 u64 octs : 48; /* W6 */
581 u64 rsvd_447_432 : 16;
582 u64 pkts : 48; /* W7 */
583 u64 rsvd_511_496 : 16;
584 u64 drop_octs : 48; /* W8 */
585 u64 rsvd_575_560 : 16;
586 u64 drop_pkts : 48; /* W9 */
587 u64 rsvd_639_624 : 16;
588 u64 re_pkts : 48; /* W10 */
589 u64 rsvd_703_688 : 16;
590 u64 rsvd_767_704; /* W11 */
591 u64 rsvd_831_768; /* W12 */
592 u64 rsvd_895_832; /* W13 */
593 u64 rsvd_959_896; /* W14 */
594 u64 rsvd_1023_960; /* W15 */
599 NIX_MAXSQESZ_W16 = 0x0,
600 NIX_MAXSQESZ_W8 = 0x1,
603 /* NIX SQB caching type */
610 /* NIX Send queue context structure */
611 struct nix_sq_ctx_s {
617 u64 sqe_way_mask : 16;
622 u64 smq_rr_quantum : 24;
623 u64 default_chan : 12;
625 u64 smq_rr_count : 25;
631 u64 max_sqe_size : 2;
635 u64 smq_next_sq : 20;
636 u64 smq_lso_segnum : 8;
638 u64 smenq_offset : 6;
640 u64 smenq_next_sqb_vld : 1;
642 u64 smq_next_sq_vld : 1;
643 u64 rsvd_255_253 : 3;
644 u64 next_sqb : 64;/* W4 */
645 u64 tail_sqb : 64;/* W5 */
646 u64 smenq_sqb : 64;/* W6 */
647 u64 smenq_next_sqb : 64;/* W7 */
648 u64 head_sqb : 64;/* W8 */
649 u64 rsvd_583_576 : 8;
650 u64 vfi_lso_total : 18;
651 u64 vfi_lso_sizem1 : 3;
653 u64 vfi_lso_mps : 14;
654 u64 vfi_lso_vlan0_ins_ena : 1;
655 u64 vfi_lso_vlan1_ins_ena : 1;
657 u64 rsvd_639_630 : 10;
658 u64 scm_lso_rem : 18;
659 u64 rsvd_703_658 : 46;
661 u64 rsvd_767_752 : 16;
663 u64 rsvd_831_816 : 16;
664 u64 rsvd_895_832 : 64;/* W13 */
665 u64 dropped_octs : 48;
666 u64 rsvd_959_944 : 16;
667 u64 dropped_pkts : 48;
668 u64 rsvd_1023_1008 : 16;
671 /* NIX Receive side scaling entry structure*/
674 uint32_t reserved_20_31 : 12;
678 /* NIX receive multicast/mirror entry structure */
679 struct nix_rx_mce_s {
684 uint64_t rsvd_31_24 : 8;
685 uint64_t pf_func : 16;
689 enum nix_band_prof_layers {
690 BAND_PROF_LEAF_LAYER = 0,
691 BAND_PROF_INVAL_LAYER = 1,
692 BAND_PROF_MID_LAYER = 2,
693 BAND_PROF_TOP_LAYER = 3,
694 BAND_PROF_NUM_LAYERS = 4,
697 enum NIX_RX_BAND_PROF_ACTIONRESULT_E {
698 NIX_RX_BAND_PROF_ACTIONRESULT_PASS = 0x0,
699 NIX_RX_BAND_PROF_ACTIONRESULT_DROP = 0x1,
700 NIX_RX_BAND_PROF_ACTIONRESULT_RED = 0x2,
703 enum nix_band_prof_pc_mode {
704 NIX_RX_PC_MODE_VLAN = 0,
705 NIX_RX_PC_MODE_DSCP = 1,
706 NIX_RX_PC_MODE_GEN = 2,
707 NIX_RX_PC_MODE_RSVD = 3,
710 /* NIX ingress policer bandwidth profile structure */
711 struct nix_bandprof_s {
712 uint64_t pc_mode : 2; /* W0 */
714 uint64_t tnl_ena : 1;
715 uint64_t reserved_5_7 : 3;
716 uint64_t peir_exponent : 5;
717 uint64_t reserved_13_15 : 3;
718 uint64_t pebs_exponent : 5;
719 uint64_t reserved_21_23 : 3;
720 uint64_t cir_exponent : 5;
721 uint64_t reserved_29_31 : 3;
722 uint64_t cbs_exponent : 5;
723 uint64_t reserved_37_39 : 3;
724 uint64_t peir_mantissa : 8;
725 uint64_t pebs_mantissa : 8;
726 uint64_t cir_mantissa : 8;
727 uint64_t cbs_mantissa : 8; /* W1 */
729 uint64_t l_sellect : 3;
731 uint64_t adjust_exponent : 5;
732 uint64_t reserved_85_86 : 2;
733 uint64_t adjust_mantissa : 9;
734 uint64_t gc_action : 2;
735 uint64_t yc_action : 2;
736 uint64_t rc_action : 2;
737 uint64_t meter_algo : 2;
738 uint64_t band_prof_id : 7;
739 uint64_t reserved_111_118 : 8;
741 uint64_t reserved_120_127 : 8;
742 uint64_t ts : 48; /* W2 */
743 uint64_t reserved_176_191 : 16;
744 uint64_t pe_accum : 32; /* W3 */
745 uint64_t c_accum : 32;
746 uint64_t green_pkt_pass : 48; /* W4 */
747 uint64_t reserved_304_319 : 16;
748 uint64_t yellow_pkt_pass : 48; /* W5 */
749 uint64_t reserved_368_383 : 16;
750 uint64_t red_pkt_pass : 48; /* W6 */
751 uint64_t reserved_432_447 : 16;
752 uint64_t green_octs_pass : 48; /* W7 */
753 uint64_t reserved_496_511 : 16;
754 uint64_t yellow_octs_pass : 48; /* W8 */
755 uint64_t reserved_560_575 : 16;
756 uint64_t red_octs_pass : 48; /* W9 */
757 uint64_t reserved_624_639 : 16;
758 uint64_t green_pkt_drop : 48; /* W10 */
759 uint64_t reserved_688_703 : 16;
760 uint64_t yellow_pkt_drop : 48; /* W11 */
761 uint64_t reserved_752_767 : 16;
762 uint64_t red_pkt_drop : 48; /* W12 */
763 uint64_t reserved_816_831 : 16;
764 uint64_t green_octs_drop : 48; /* W13 */
765 uint64_t reserved_880_895 : 16;
766 uint64_t yellow_octs_drop : 48; /* W14 */
767 uint64_t reserved_944_959 : 16;
768 uint64_t red_octs_drop : 48; /* W15 */
769 uint64_t reserved_1008_1023 : 16;
774 NIX_LSOALG_ADD_SEGNUM,
775 NIX_LSOALG_ADD_PAYLEN,
776 NIX_LSOALG_ADD_OFFSET,
777 NIX_LSOALG_TCP_FLAGS,
787 struct nix_lso_format {
797 struct nix_rx_flowkey_alg {
804 u64 reserved_24_24 :1;
809 u64 reserved_35_63 :29;
818 enum nix_tx_vtag_op {
824 /* NIX RX VTAG actions */
825 #define VTAG_STRIP BIT_ULL(4)
826 #define VTAG_CAPTURE BIT_ULL(5)
828 #endif /* RVU_STRUCT_H */