1 /* SPDX-License-Identifier: GPL-2.0
2 * Marvell OcteonTx2 RVU Admin Function driver
4 * Copyright (C) 2018 Marvell International Ltd.
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2 as
8 * published by the Free Software Foundation.
14 /* RVU Block Address Enumeration */
15 enum rvu_block_addr_e {
16 BLKADDR_RVUM = 0x0ULL,
18 BLKADDR_MSIX = 0x2ULL,
20 BLKADDR_NIX0 = 0x4ULL,
21 BLKADDR_NIX1 = 0x5ULL,
24 BLKADDR_SSOW = 0x8ULL,
26 BLKADDR_CPT0 = 0xaULL,
27 BLKADDR_CPT1 = 0xbULL,
28 BLKADDR_NDC0 = 0xcULL,
29 BLKADDR_NDC1 = 0xdULL,
30 BLKADDR_NDC2 = 0xeULL,
34 /* RVU Block Type Enumeration */
35 enum rvu_block_type_e {
50 /* RVU Admin function Interrupt Vector Enumeration */
51 enum rvu_af_int_vec_e {
52 RVU_AF_INT_VEC_POISON = 0x0,
53 RVU_AF_INT_VEC_PFFLR = 0x1,
54 RVU_AF_INT_VEC_PFME = 0x2,
55 RVU_AF_INT_VEC_GEN = 0x3,
56 RVU_AF_INT_VEC_MBOX = 0x4,
57 RVU_AF_INT_VEC_CNT = 0x5,
61 * RVU PF Interrupt Vector Enumeration
63 enum rvu_pf_int_vec_e {
64 RVU_PF_INT_VEC_VFFLR0 = 0x0,
65 RVU_PF_INT_VEC_VFFLR1 = 0x1,
66 RVU_PF_INT_VEC_VFME0 = 0x2,
67 RVU_PF_INT_VEC_VFME1 = 0x3,
68 RVU_PF_INT_VEC_VFPF_MBOX0 = 0x4,
69 RVU_PF_INT_VEC_VFPF_MBOX1 = 0x5,
70 RVU_PF_INT_VEC_AFPF_MBOX = 0x6,
71 RVU_PF_INT_VEC_CNT = 0x7,
74 /* NPA admin queue completion enumeration */
76 NPA_AQ_COMP_NOTDONE = 0x0,
77 NPA_AQ_COMP_GOOD = 0x1,
78 NPA_AQ_COMP_SWERR = 0x2,
79 NPA_AQ_COMP_CTX_POISON = 0x3,
80 NPA_AQ_COMP_CTX_FAULT = 0x4,
81 NPA_AQ_COMP_LOCKERR = 0x5,
84 /* NPA admin queue context types */
86 NPA_AQ_CTYPE_AURA = 0x0,
87 NPA_AQ_CTYPE_POOL = 0x1,
90 /* NPA admin queue instruction opcodes */
92 NPA_AQ_INSTOP_NOP = 0x0,
93 NPA_AQ_INSTOP_INIT = 0x1,
94 NPA_AQ_INSTOP_WRITE = 0x2,
95 NPA_AQ_INSTOP_READ = 0x3,
96 NPA_AQ_INSTOP_LOCK = 0x4,
97 NPA_AQ_INSTOP_UNLOCK = 0x5,
100 /* NPA admin queue instruction structure */
101 struct npa_aq_inst_s {
102 #if defined(__BIG_ENDIAN_BITFIELD)
103 u64 doneint : 1; /* W0 */
104 u64 reserved_44_62 : 19;
106 u64 reserved_17_23 : 7;
114 u64 reserved_17_23 : 7;
116 u64 reserved_44_62 : 19;
119 u64 res_addr; /* W1 */
122 /* NPA admin queue result structure */
123 struct npa_aq_res_s {
124 #if defined(__BIG_ENDIAN_BITFIELD)
125 u64 reserved_17_63 : 47; /* W0 */
135 u64 reserved_17_63 : 47;
137 u64 reserved_64_127; /* W1 */
141 u64 pool_addr; /* W0 */
142 #if defined(__BIG_ENDIAN_BITFIELD) /* W1 */
144 u64 reserved_118_119 : 2;
147 u64 reserved_98_103 : 6;
149 u64 aura_drop_ena : 1;
150 u64 pool_drop_ena : 1;
153 u64 pool_way_mask : 16;
154 u64 pool_caching : 1;
160 u64 pool_caching : 1;
161 u64 pool_way_mask : 16;
164 u64 pool_drop_ena : 1;
165 u64 aura_drop_ena : 1;
167 u64 reserved_98_103 : 6;
170 u64 reserved_118_119 : 2;
173 #if defined(__BIG_ENDIAN_BITFIELD) /* W2 */
174 u64 reserved_189_191 : 3;
176 u64 reserved_177_179 : 3;
178 u64 reserved_164_167 : 4;
182 u64 reserved_164_167 : 4;
184 u64 reserved_177_179 : 3;
186 u64 reserved_189_191 : 3;
188 #if defined(__BIG_ENDIAN_BITFIELD) /* W3 */
189 u64 reserved_252_255 : 4;
190 u64 fc_hyst_bits : 4;
192 u64 fc_up_crossing : 1;
194 u64 reserved_240_243 : 4;
196 u64 reserved_228_231 : 4;
200 u64 reserved_228_231 : 4;
202 u64 reserved_240_243 : 4;
204 u64 fc_up_crossing : 1;
206 u64 fc_hyst_bits : 4;
207 u64 reserved_252_255 : 4;
209 u64 fc_addr; /* W4 */
210 #if defined(__BIG_ENDIAN_BITFIELD) /* W5 */
211 u64 reserved_379_383 : 5;
212 u64 err_qint_idx : 7;
213 u64 reserved_371 : 1;
214 u64 thresh_qint_idx : 7;
215 u64 reserved_363 : 1;
217 u64 thresh_int_ena : 1;
221 u64 update_time : 16;
225 u64 update_time : 16;
229 u64 thresh_int_ena : 1;
231 u64 reserved_363 : 1;
232 u64 thresh_qint_idx : 7;
233 u64 reserved_371 : 1;
234 u64 err_qint_idx : 7;
235 u64 reserved_379_383 : 5;
237 #if defined(__BIG_ENDIAN_BITFIELD) /* W6 */
238 u64 reserved_420_447 : 28;
242 u64 reserved_420_447 : 28;
244 u64 reserved_448_511; /* W7 */
248 u64 stack_base; /* W0 */
249 #if defined(__BIG_ENDIAN_BITFIELD) /* W1 */
250 u64 reserved_115_127 : 13;
252 u64 reserved_100_103 : 4;
254 u64 stack_way_mask : 16;
255 u64 reserved_70_71 : 3;
256 u64 stack_caching : 1;
257 u64 reserved_66_67 : 2;
263 u64 reserved_66_67 : 2;
264 u64 stack_caching : 1;
265 u64 reserved_70_71 : 3;
266 u64 stack_way_mask : 16;
268 u64 reserved_100_103 : 4;
270 u64 reserved_115_127 : 13;
272 #if defined(__BIG_ENDIAN_BITFIELD) /* W2 */
273 u64 stack_pages : 32;
274 u64 stack_max_pages : 32;
276 u64 stack_max_pages : 32;
277 u64 stack_pages : 32;
279 #if defined(__BIG_ENDIAN_BITFIELD) /* W3 */
280 u64 reserved_240_255 : 16;
284 u64 reserved_240_255 : 16;
286 #if defined(__BIG_ENDIAN_BITFIELD) /* W4 */
287 u64 reserved_316_319 : 4;
288 u64 update_time : 16;
289 u64 reserved_297_299 : 3;
290 u64 fc_up_crossing : 1;
291 u64 fc_hyst_bits : 4;
296 u64 reserved_270_271 : 2;
298 u64 reserved_260_263 : 4;
299 u64 stack_offset : 4;
301 u64 stack_offset : 4;
302 u64 reserved_260_263 : 4;
304 u64 reserved_270_271 : 2;
309 u64 fc_hyst_bits : 4;
310 u64 fc_up_crossing : 1;
311 u64 reserved_297_299 : 3;
312 u64 update_time : 16;
313 u64 reserved_316_319 : 4;
315 u64 fc_addr; /* W5 */
316 u64 ptr_start; /* W6 */
317 u64 ptr_end; /* W7 */
318 #if defined(__BIG_ENDIAN_BITFIELD) /* W8 */
319 u64 reserved_571_575 : 5;
320 u64 err_qint_idx : 7;
321 u64 reserved_563 : 1;
322 u64 thresh_qint_idx : 7;
323 u64 reserved_555 : 1;
325 u64 thresh_int_ena : 1;
329 u64 reserved_512_535 : 24;
331 u64 reserved_512_535 : 24;
335 u64 thresh_int_ena : 1;
337 u64 reserved_555 : 1;
338 u64 thresh_qint_idx : 7;
339 u64 reserved_563 : 1;
340 u64 err_qint_idx : 7;
341 u64 reserved_571_575 : 5;
343 #if defined(__BIG_ENDIAN_BITFIELD) /* W9 */
344 u64 reserved_612_639 : 28;
348 u64 reserved_612_639 : 28;
350 u64 reserved_640_703; /* W10 */
351 u64 reserved_704_767; /* W11 */
352 u64 reserved_768_831; /* W12 */
353 u64 reserved_832_895; /* W13 */
354 u64 reserved_896_959; /* W14 */
355 u64 reserved_960_1023; /* W15 */
358 /* NIX admin queue completion status */
360 NIX_AQ_COMP_NOTDONE = 0x0,
361 NIX_AQ_COMP_GOOD = 0x1,
362 NIX_AQ_COMP_SWERR = 0x2,
363 NIX_AQ_COMP_CTX_POISON = 0x3,
364 NIX_AQ_COMP_CTX_FAULT = 0x4,
365 NIX_AQ_COMP_LOCKERR = 0x5,
366 NIX_AQ_COMP_SQB_ALLOC_FAIL = 0x6,
369 /* NIX admin queue context types */
371 NIX_AQ_CTYPE_RQ = 0x0,
372 NIX_AQ_CTYPE_SQ = 0x1,
373 NIX_AQ_CTYPE_CQ = 0x2,
374 NIX_AQ_CTYPE_MCE = 0x3,
375 NIX_AQ_CTYPE_RSS = 0x4,
376 NIX_AQ_CTYPE_DYNO = 0x5,
379 /* NIX admin queue instruction opcodes */
381 NIX_AQ_INSTOP_NOP = 0x0,
382 NIX_AQ_INSTOP_INIT = 0x1,
383 NIX_AQ_INSTOP_WRITE = 0x2,
384 NIX_AQ_INSTOP_READ = 0x3,
385 NIX_AQ_INSTOP_LOCK = 0x4,
386 NIX_AQ_INSTOP_UNLOCK = 0x5,
389 /* NIX admin queue instruction structure */
390 struct nix_aq_inst_s {
391 #if defined(__BIG_ENDIAN_BITFIELD)
392 u64 doneint : 1; /* W0 */
393 u64 reserved_44_62 : 19;
395 u64 reserved_15_23 : 9;
403 u64 reserved_15_23 : 9;
405 u64 reserved_44_62 : 19;
408 u64 res_addr; /* W1 */
411 /* NIX admin queue result structure */
412 struct nix_aq_res_s {
413 #if defined(__BIG_ENDIAN_BITFIELD)
414 u64 reserved_17_63 : 47; /* W0 */
424 u64 reserved_17_63 : 47;
426 u64 reserved_64_127; /* W1 */
429 /* NIX Completion queue context structure */
430 struct nix_cq_ctx_s {
432 #if defined(__BIG_ENDIAN_BITFIELD) /* W1 */
455 #if defined(__BIG_ENDIAN_BITFIELD) /* W2 */
456 u64 update_time : 16;
464 u64 update_time : 16;
466 #if defined(__BIG_ENDIAN_BITFIELD) /* W3 */
467 u64 cq_err_int_ena : 8;
470 u64 rsvd_233_235 : 3;
473 u64 rsvd_210_211 : 2;
483 u64 rsvd_210_211 : 2;
486 u64 rsvd_233_235 : 3;
489 u64 cq_err_int_ena : 8;
493 /* NIX Receive queue context structure */
494 struct nix_rq_ctx_s {
495 #if defined(__BIG_ENDIAN_BITFIELD) /* W0 */
512 #if defined(__BIG_ENDIAN_BITFIELD) /* W1 */
513 u64 rsvd_127_122 : 6;
514 u64 lpb_drop_ena : 1;
515 u64 spb_drop_ena : 1;
516 u64 xqe_drop_ena : 1;
530 u64 xqe_drop_ena : 1;
531 u64 spb_drop_ena : 1;
532 u64 lpb_drop_ena : 1;
533 u64 rsvd_127_122 : 6;
535 #if defined(__BIG_ENDIAN_BITFIELD) /* W2 */
536 u64 xqe_hdr_split : 1;
537 u64 xqe_imm_copy : 1;
538 u64 rsvd_189_184 : 6;
539 u64 xqe_imm_size : 6;
545 u64 rsvd_150_148 : 3;
548 u64 rsvd_139_128 : 12;
550 u64 rsvd_139_128 : 12;
553 u64 rsvd_150_148 : 3;
559 u64 xqe_imm_size : 6;
560 u64 rsvd_189_184 : 6;
561 u64 xqe_imm_copy : 1;
562 u64 xqe_hdr_split : 1;
564 #if defined(__BIG_ENDIAN_BITFIELD) /* W3 */
565 u64 spb_pool_pass : 8;
566 u64 spb_pool_drop : 8;
567 u64 spb_aura_pass : 8;
568 u64 spb_aura_drop : 8;
569 u64 wqe_pool_pass : 8;
570 u64 wqe_pool_drop : 8;
576 u64 wqe_pool_drop : 8;
577 u64 wqe_pool_pass : 8;
578 u64 spb_aura_drop : 8;
579 u64 spb_aura_pass : 8;
580 u64 spb_pool_drop : 8;
581 u64 spb_pool_pass : 8;
583 #if defined(__BIG_ENDIAN_BITFIELD) /* W4 */
584 u64 rsvd_319_315 : 5;
588 u64 rsvd_291_288 : 4;
589 u64 lpb_pool_pass : 8;
590 u64 lpb_pool_drop : 8;
591 u64 lpb_aura_pass : 8;
592 u64 lpb_aura_drop : 8;
594 u64 lpb_aura_drop : 8;
595 u64 lpb_aura_pass : 8;
596 u64 lpb_pool_drop : 8;
597 u64 lpb_pool_pass : 8;
598 u64 rsvd_291_288 : 4;
602 u64 rsvd_319_315 : 5;
604 #if defined(__BIG_ENDIAN_BITFIELD) /* W5 */
605 u64 rsvd_383_366 : 18;
615 u64 rsvd_383_366 : 18;
617 #if defined(__BIG_ENDIAN_BITFIELD) /* W6 */
618 u64 rsvd_447_432 : 16;
622 u64 rsvd_447_432 : 16;
624 #if defined(__BIG_ENDIAN_BITFIELD) /* W7 */
625 u64 rsvd_511_496 : 16;
629 u64 rsvd_511_496 : 16;
631 #if defined(__BIG_ENDIAN_BITFIELD) /* W8 */
632 u64 rsvd_575_560 : 16;
636 u64 rsvd_575_560 : 16;
638 #if defined(__BIG_ENDIAN_BITFIELD) /* W9 */
639 u64 rsvd_639_624 : 16;
643 u64 rsvd_639_624 : 16;
645 #if defined(__BIG_ENDIAN_BITFIELD) /* W10 */
646 u64 rsvd_703_688 : 16;
650 u64 rsvd_703_688 : 16;
652 u64 rsvd_767_704; /* W11 */
653 u64 rsvd_831_768; /* W12 */
654 u64 rsvd_895_832; /* W13 */
655 u64 rsvd_959_896; /* W14 */
656 u64 rsvd_1023_960; /* W15 */
661 NIX_MAXSQESZ_W16 = 0x0,
662 NIX_MAXSQESZ_W8 = 0x1,
665 /* NIX SQB caching type */
672 /* NIX Send queue context structure */
673 struct nix_sq_ctx_s {
674 #if defined(__BIG_ENDIAN_BITFIELD) /* W0 */
675 u64 sqe_way_mask : 16;
687 u64 sqe_way_mask : 16;
689 #if defined(__BIG_ENDIAN_BITFIELD) /* W1 */
691 u64 default_chan : 12;
692 u64 smq_rr_quantum : 24;
702 u64 smq_rr_quantum : 24;
703 u64 default_chan : 12;
706 #if defined(__BIG_ENDIAN_BITFIELD) /* W2 */
712 u64 smq_rr_count : 25;
714 u64 smq_rr_count : 25;
721 #if defined(__BIG_ENDIAN_BITFIELD) /* W3 */
722 u64 rsvd_255_253 : 3;
723 u64 smq_next_sq_vld : 1;
725 u64 smenq_next_sqb_vld : 1;
727 u64 smenq_offset : 6;
729 u64 smq_lso_segnum : 8;
730 u64 smq_next_sq : 20;
734 u64 max_sqe_size : 2;
736 u64 max_sqe_size : 2;
740 u64 smq_next_sq : 20;
741 u64 smq_lso_segnum : 8;
743 u64 smenq_offset : 6;
745 u64 smenq_next_sqb_vld : 1;
747 u64 smq_next_sq_vld : 1;
748 u64 rsvd_255_253 : 3;
750 u64 next_sqb : 64;/* W4 */
751 u64 tail_sqb : 64;/* W5 */
752 u64 smenq_sqb : 64;/* W6 */
753 u64 smenq_next_sqb : 64;/* W7 */
754 u64 head_sqb : 64;/* W8 */
755 #if defined(__BIG_ENDIAN_BITFIELD) /* W9 */
756 u64 rsvd_639_630 : 10;
758 u64 vfi_lso_vlan1_ins_ena : 1;
759 u64 vfi_lso_vlan0_ins_ena : 1;
760 u64 vfi_lso_mps : 14;
762 u64 vfi_lso_sizem1 : 3;
763 u64 vfi_lso_total : 18;
764 u64 rsvd_583_576 : 8;
766 u64 rsvd_583_576 : 8;
767 u64 vfi_lso_total : 18;
768 u64 vfi_lso_sizem1 : 3;
770 u64 vfi_lso_mps : 14;
771 u64 vfi_lso_vlan0_ins_ena : 1;
772 u64 vfi_lso_vlan1_ins_ena : 1;
774 u64 rsvd_639_630 : 10;
776 #if defined(__BIG_ENDIAN_BITFIELD) /* W10 */
777 u64 rsvd_703_658 : 46;
778 u64 scm_lso_rem : 18;
780 u64 scm_lso_rem : 18;
781 u64 rsvd_703_658 : 46;
783 #if defined(__BIG_ENDIAN_BITFIELD) /* W11 */
784 u64 rsvd_767_752 : 16;
788 u64 rsvd_767_752 : 16;
790 #if defined(__BIG_ENDIAN_BITFIELD) /* W12 */
791 u64 rsvd_831_816 : 16;
795 u64 rsvd_831_816 : 16;
797 u64 rsvd_895_832 : 64;/* W13 */
798 #if defined(__BIG_ENDIAN_BITFIELD) /* W14 */
799 u64 rsvd_959_944 : 16;
800 u64 dropped_octs : 48;
802 u64 dropped_octs : 48;
803 u64 rsvd_959_944 : 16;
805 #if defined(__BIG_ENDIAN_BITFIELD) /* W15 */
806 u64 rsvd_1023_1008 : 16;
807 u64 dropped_pkts : 48;
809 u64 dropped_pkts : 48;
810 u64 rsvd_1023_1008 : 16;
814 /* NIX Receive side scaling entry structure*/
816 #if defined(__BIG_ENDIAN_BITFIELD)
817 uint32_t reserved_20_31 : 12;
821 uint32_t reserved_20_31 : 12;
826 /* NIX receive multicast/mirror entry structure */
827 struct nix_rx_mce_s {
828 #if defined(__BIG_ENDIAN_BITFIELD) /* W0 */
830 uint64_t pf_func : 16;
831 uint64_t rsvd_31_24 : 8;
841 uint64_t rsvd_31_24 : 8;
842 uint64_t pf_func : 16;
849 NIX_LSOALG_ADD_SEGNUM,
850 NIX_LSOALG_ADD_PAYLEN,
851 NIX_LSOALG_ADD_OFFSET,
852 NIX_LSOALG_TCP_FLAGS,
862 struct nix_lso_format {
863 #if defined(__BIG_ENDIAN_BITFIELD)
887 #endif /* RVU_STRUCT_H */