drivers/net/ethernet/marvell/octeontx2/af/rvu_npc.c

   1 // SPDX-License-Identifier: GPL-2.0
   2 /* Marvell OcteonTx2 RVU Admin Function driver
   3  *
   4  * Copyright (C) 2018 Marvell International Ltd.
   5  *
   6  * This program is free software; you can redistribute it and/or modify
   7  * it under the terms of the GNU General Public License version 2 as
   8  * published by the Free Software Foundation.
   9  */
  10
  11 #include <linux/bitfield.h>
  12 #include <linux/module.h>
  13 #include <linux/pci.h>
  14
  15 #include "rvu_struct.h"
  16 #include "rvu_reg.h"
  17 #include "rvu.h"
  18 #include "npc.h"
  19 #include "cgx.h"
  20 #include "npc_profile.h"
  21
  22 #define RSVD_MCAM_ENTRIES_PER_PF        2 /* Bcast & Promisc */
  23 #define RSVD_MCAM_ENTRIES_PER_NIXLF     1 /* Ucast for LFs */
  24
  25 #define NIXLF_UCAST_ENTRY       0
  26 #define NIXLF_BCAST_ENTRY       1
  27 #define NIXLF_PROMISC_ENTRY     2
  28
  29 #define NPC_PARSE_RESULT_DMAC_OFFSET    8
  30 #define NPC_HW_TSTAMP_OFFSET            8
  31 #define NPC_KEX_CHAN_MASK               0xFFFULL
  32 #define NPC_KEX_PF_FUNC_MASK            0xFFFFULL
  33
  34 static const char def_pfl_name[] = "default";
  35
  36 static void npc_mcam_free_all_entries(struct rvu *rvu, struct npc_mcam *mcam,
  37                                       int blkaddr, u16 pcifunc);
  38 static void npc_mcam_free_all_counters(struct rvu *rvu, struct npc_mcam *mcam,
  39                                        u16 pcifunc);
  40
  41 bool is_npc_intf_tx(u8 intf)
  42 {
  43         return !!(intf & 0x1);
  44 }
  45
  46 bool is_npc_intf_rx(u8 intf)
  47 {
  48         return !(intf & 0x1);
  49 }
  50
  51 bool is_npc_interface_valid(struct rvu *rvu, u8 intf)
  52 {
  53         struct rvu_hwinfo *hw = rvu->hw;
  54
  55         return intf < hw->npc_intfs;
  56 }
  57
  58 int rvu_npc_get_tx_nibble_cfg(struct rvu *rvu, u64 nibble_ena)
  59 {
  60         /* Due to a HW issue in these silicon versions, parse nibble enable
  61          * configuration has to be identical for both Rx and Tx interfaces.
  62          */
  63         if (is_rvu_96xx_B0(rvu))
  64                 return nibble_ena;
  65         return 0;
  66 }
  67
  68 static int npc_mcam_verify_pf_func(struct rvu *rvu,
  69                                    struct mcam_entry *entry_data, u8 intf,
  70                                    u16 pcifunc)
  71 {
  72         u16 pf_func, pf_func_mask;
  73
  74         if (is_npc_intf_rx(intf))
  75                 return 0;
  76
  77         pf_func_mask = (entry_data->kw_mask[0] >> 32) &
  78                 NPC_KEX_PF_FUNC_MASK;
  79         pf_func = (entry_data->kw[0] >> 32) & NPC_KEX_PF_FUNC_MASK;
  80
  81         pf_func = be16_to_cpu((__force __be16)pf_func);
  82         if (pf_func_mask != NPC_KEX_PF_FUNC_MASK ||
  83             ((pf_func & ~RVU_PFVF_FUNC_MASK) !=
  84              (pcifunc & ~RVU_PFVF_FUNC_MASK)))
  85                 return -EINVAL;
  86
  87         return 0;
  88 }
  89
  90 int npc_mcam_verify_channel(struct rvu *rvu, u16 pcifunc, u8 intf, u16 channel)
  91 {
  92         int pf = rvu_get_pf(pcifunc);
  93         u8 cgx_id, lmac_id;
  94         int base = 0, end;
  95
  96         if (is_npc_intf_tx(intf))
  97                 return 0;
  98
  99         if (is_afvf(pcifunc)) {
 100                 end = rvu_get_num_lbk_chans();
 101                 if (end < 0)
 102                         return -EINVAL;
 103         } else {
 104                 rvu_get_cgx_lmac_id(rvu->pf2cgxlmac_map[pf], &cgx_id, &lmac_id);
 105                 base = NIX_CHAN_CGX_LMAC_CHX(cgx_id, lmac_id, 0x0);
 106                 /* CGX mapped functions has maximum of 16 channels */
 107                 end = NIX_CHAN_CGX_LMAC_CHX(cgx_id, lmac_id, 0xF);
 108         }
 109
 110         if (channel < base || channel > end)
 111                 return -EINVAL;
 112
 113         return 0;
 114 }
 115
 116 void rvu_npc_set_pkind(struct rvu *rvu, int pkind, struct rvu_pfvf *pfvf)
 117 {
 118         int blkaddr;
 119         u64 val = 0;
 120
 121         blkaddr = rvu_get_blkaddr(rvu, BLKTYPE_NPC, 0);
 122         if (blkaddr < 0)
 123                 return;
 124
 125         /* Config CPI base for the PKIND */
 126         val = pkind | 1ULL << 62;
 127         rvu_write64(rvu, blkaddr, NPC_AF_PKINDX_CPI_DEFX(pkind, 0), val);
 128 }
 129
 130 int rvu_npc_get_pkind(struct rvu *rvu, u16 pf)
 131 {
 132         struct npc_pkind *pkind = &rvu->hw->pkind;
 133         u32 map;
 134         int i;
 135
 136         for (i = 0; i < pkind->rsrc.max; i++) {
 137                 map = pkind->pfchan_map[i];
 138                 if (((map >> 16) & 0x3F) == pf)
 139                         return i;
 140         }
 141         return -1;
 142 }
 143
 144 #define NPC_AF_ACTION0_PTR_ADVANCE      GENMASK_ULL(27, 20)
 145
 146 int npc_config_ts_kpuaction(struct rvu *rvu, int pf, u16 pcifunc, bool enable)
 147 {
 148         int pkind, blkaddr;
 149         u64 val;
 150
 151         pkind = rvu_npc_get_pkind(rvu, pf);
 152         if (pkind < 0) {
 153                 dev_err(rvu->dev, "%s: pkind not mapped\n", __func__);
 154                 return -EINVAL;
 155         }
 156
 157         blkaddr = rvu_get_blkaddr(rvu, BLKTYPE_NPC, pcifunc);
 158         if (blkaddr < 0) {
 159                 dev_err(rvu->dev, "%s: NPC block not implemented\n", __func__);
 160                 return -EINVAL;
 161         }
 162
 163         val = rvu_read64(rvu, blkaddr, NPC_AF_PKINDX_ACTION0(pkind));
 164         val &= ~NPC_AF_ACTION0_PTR_ADVANCE;
 165         /* If timestamp is enabled then configure NPC to shift 8 bytes */
 166         if (enable)
 167                 val |= FIELD_PREP(NPC_AF_ACTION0_PTR_ADVANCE,
 168                                   NPC_HW_TSTAMP_OFFSET);
 169         rvu_write64(rvu, blkaddr, NPC_AF_PKINDX_ACTION0(pkind), val);
 170
 171         return 0;
 172 }
 173
 174 static int npc_get_ucast_mcam_index(struct npc_mcam *mcam, u16 pcifunc,
 175                                     int nixlf)
 176 {
 177         struct rvu_hwinfo *hw = container_of(mcam, struct rvu_hwinfo, mcam);
 178         struct rvu *rvu = hw->rvu;
 179         int blkaddr = 0, max = 0;
 180         struct rvu_block *block;
 181         struct rvu_pfvf *pfvf;
 182
 183         pfvf = rvu_get_pfvf(rvu, pcifunc);
 184         /* Given a PF/VF and NIX LF number calculate the unicast mcam
 185          * entry index based on the NIX block assigned to the PF/VF.
 186          */
 187         blkaddr = rvu_get_next_nix_blkaddr(rvu, blkaddr);
 188         while (blkaddr) {
 189                 if (pfvf->nix_blkaddr == blkaddr)
 190                         break;
 191                 block = &rvu->hw->block[blkaddr];
 192                 max += block->lf.max;
 193                 blkaddr = rvu_get_next_nix_blkaddr(rvu, blkaddr);
 194         }
 195
 196         return mcam->nixlf_offset + (max + nixlf) * RSVD_MCAM_ENTRIES_PER_NIXLF;
 197 }
 198
 199 static int npc_get_nixlf_mcam_index(struct npc_mcam *mcam,
 200                                     u16 pcifunc, int nixlf, int type)
 201 {
 202         int pf = rvu_get_pf(pcifunc);
 203         int index;
 204
 205         /* Check if this is for a PF */
 206         if (pf && !(pcifunc & RVU_PFVF_FUNC_MASK)) {
 207                 /* Reserved entries exclude PF0 */
 208                 pf--;
 209                 index = mcam->pf_offset + (pf * RSVD_MCAM_ENTRIES_PER_PF);
 210                 /* Broadcast address matching entry should be first so
 211                  * that the packet can be replicated to all VFs.
 212                  */
 213                 if (type == NIXLF_BCAST_ENTRY)
 214                         return index;
 215                 else if (type == NIXLF_PROMISC_ENTRY)
 216                         return index + 1;
 217         }
 218
 219         return npc_get_ucast_mcam_index(mcam, pcifunc, nixlf);
 220 }
 221
 222 static int npc_get_bank(struct npc_mcam *mcam, int index)
 223 {
 224         int bank = index / mcam->banksize;
 225
 226         /* 0,1 & 2,3 banks are combined for this keysize */
 227         if (mcam->keysize == NPC_MCAM_KEY_X2)
 228                 return bank ? 2 : 0;
 229
 230         return bank;
 231 }
 232
 233 static bool is_mcam_entry_enabled(struct rvu *rvu, struct npc_mcam *mcam,
 234                                   int blkaddr, int index)
 235 {
 236         int bank = npc_get_bank(mcam, index);
 237         u64 cfg;
 238
 239         index &= (mcam->banksize - 1);
 240         cfg = rvu_read64(rvu, blkaddr, NPC_AF_MCAMEX_BANKX_CFG(index, bank));
 241         return (cfg & 1);
 242 }
 243
 244 static void npc_enable_mcam_entry(struct rvu *rvu, struct npc_mcam *mcam,
 245                                   int blkaddr, int index, bool enable)
 246 {
 247         int bank = npc_get_bank(mcam, index);
 248         int actbank = bank;
 249
 250         index &= (mcam->banksize - 1);
 251         for (; bank < (actbank + mcam->banks_per_entry); bank++) {
 252                 rvu_write64(rvu, blkaddr,
 253                             NPC_AF_MCAMEX_BANKX_CFG(index, bank),
 254                             enable ? 1 : 0);
 255         }
 256 }
 257
 258 static void npc_clear_mcam_entry(struct rvu *rvu, struct npc_mcam *mcam,
 259                                  int blkaddr, int index)
 260 {
 261         int bank = npc_get_bank(mcam, index);
 262         int actbank = bank;
 263
 264         index &= (mcam->banksize - 1);
 265         for (; bank < (actbank + mcam->banks_per_entry); bank++) {
 266                 rvu_write64(rvu, blkaddr,
 267                             NPC_AF_MCAMEX_BANKX_CAMX_INTF(index, bank, 1), 0);
 268                 rvu_write64(rvu, blkaddr,
 269                             NPC_AF_MCAMEX_BANKX_CAMX_INTF(index, bank, 0), 0);
 270
 271                 rvu_write64(rvu, blkaddr,
 272                             NPC_AF_MCAMEX_BANKX_CAMX_W0(index, bank, 1), 0);
 273                 rvu_write64(rvu, blkaddr,
 274                             NPC_AF_MCAMEX_BANKX_CAMX_W0(index, bank, 0), 0);
 275
 276                 rvu_write64(rvu, blkaddr,
 277                             NPC_AF_MCAMEX_BANKX_CAMX_W1(index, bank, 1), 0);
 278                 rvu_write64(rvu, blkaddr,
 279                             NPC_AF_MCAMEX_BANKX_CAMX_W1(index, bank, 0), 0);
 280         }
 281 }
 282
 283 static void npc_get_keyword(struct mcam_entry *entry, int idx,
 284                             u64 *cam0, u64 *cam1)
 285 {
 286         u64 kw_mask = 0x00;
 287
 288 #define CAM_MASK(n)     (BIT_ULL(n) - 1)
 289
 290         /* 0, 2, 4, 6 indices refer to BANKX_CAMX_W0 and
 291          * 1, 3, 5, 7 indices refer to BANKX_CAMX_W1.
 292          *
 293          * Also, only 48 bits of BANKX_CAMX_W1 are valid.
 294          */
 295         switch (idx) {
 296         case 0:
 297                 /* BANK(X)_CAM_W0<63:0> = MCAM_KEY[KW0]<63:0> */
 298                 *cam1 = entry->kw[0];
 299                 kw_mask = entry->kw_mask[0];
 300                 break;
 301         case 1:
 302                 /* BANK(X)_CAM_W1<47:0> = MCAM_KEY[KW1]<47:0> */
 303                 *cam1 = entry->kw[1] & CAM_MASK(48);
 304                 kw_mask = entry->kw_mask[1] & CAM_MASK(48);
 305                 break;
 306         case 2:
 307                 /* BANK(X + 1)_CAM_W0<15:0> = MCAM_KEY[KW1]<63:48>
 308                  * BANK(X + 1)_CAM_W0<63:16> = MCAM_KEY[KW2]<47:0>
 309                  */
 310                 *cam1 = (entry->kw[1] >> 48) & CAM_MASK(16);
 311                 *cam1 |= ((entry->kw[2] & CAM_MASK(48)) << 16);
 312                 kw_mask = (entry->kw_mask[1] >> 48) & CAM_MASK(16);
 313                 kw_mask |= ((entry->kw_mask[2] & CAM_MASK(48)) << 16);
 314                 break;
 315         case 3:
 316                 /* BANK(X + 1)_CAM_W1<15:0> = MCAM_KEY[KW2]<63:48>
 317                  * BANK(X + 1)_CAM_W1<47:16> = MCAM_KEY[KW3]<31:0>
 318                  */
 319                 *cam1 = (entry->kw[2] >> 48) & CAM_MASK(16);
 320                 *cam1 |= ((entry->kw[3] & CAM_MASK(32)) << 16);
 321                 kw_mask = (entry->kw_mask[2] >> 48) & CAM_MASK(16);
 322                 kw_mask |= ((entry->kw_mask[3] & CAM_MASK(32)) << 16);
 323                 break;
 324         case 4:
 325                 /* BANK(X + 2)_CAM_W0<31:0> = MCAM_KEY[KW3]<63:32>
 326                  * BANK(X + 2)_CAM_W0<63:32> = MCAM_KEY[KW4]<31:0>
 327                  */
 328                 *cam1 = (entry->kw[3] >> 32) & CAM_MASK(32);
 329                 *cam1 |= ((entry->kw[4] & CAM_MASK(32)) << 32);
 330                 kw_mask = (entry->kw_mask[3] >> 32) & CAM_MASK(32);
 331                 kw_mask |= ((entry->kw_mask[4] & CAM_MASK(32)) << 32);
 332                 break;
 333         case 5:
 334                 /* BANK(X + 2)_CAM_W1<31:0> = MCAM_KEY[KW4]<63:32>
 335                  * BANK(X + 2)_CAM_W1<47:32> = MCAM_KEY[KW5]<15:0>
 336                  */
 337                 *cam1 = (entry->kw[4] >> 32) & CAM_MASK(32);
 338                 *cam1 |= ((entry->kw[5] & CAM_MASK(16)) << 32);
 339                 kw_mask = (entry->kw_mask[4] >> 32) & CAM_MASK(32);
 340                 kw_mask |= ((entry->kw_mask[5] & CAM_MASK(16)) << 32);
 341                 break;
 342         case 6:
 343                 /* BANK(X + 3)_CAM_W0<47:0> = MCAM_KEY[KW5]<63:16>
 344                  * BANK(X + 3)_CAM_W0<63:48> = MCAM_KEY[KW6]<15:0>
 345                  */
 346                 *cam1 = (entry->kw[5] >> 16) & CAM_MASK(48);
 347                 *cam1 |= ((entry->kw[6] & CAM_MASK(16)) << 48);
 348                 kw_mask = (entry->kw_mask[5] >> 16) & CAM_MASK(48);
 349                 kw_mask |= ((entry->kw_mask[6] & CAM_MASK(16)) << 48);
 350                 break;
 351         case 7:
 352                 /* BANK(X + 3)_CAM_W1<47:0> = MCAM_KEY[KW6]<63:16> */
 353                 *cam1 = (entry->kw[6] >> 16) & CAM_MASK(48);
 354                 kw_mask = (entry->kw_mask[6] >> 16) & CAM_MASK(48);
 355                 break;
 356         }
 357
 358         *cam1 &= kw_mask;
 359         *cam0 = ~*cam1 & kw_mask;
 360 }
 361
 362 static void npc_config_mcam_entry(struct rvu *rvu, struct npc_mcam *mcam,
 363                                   int blkaddr, int index, u8 intf,
 364                                   struct mcam_entry *entry, bool enable)
 365 {
 366         int bank = npc_get_bank(mcam, index);
 367         int kw = 0, actbank, actindex;
 368         u64 cam0, cam1;
 369
 370         actbank = bank; /* Save bank id, to set action later on */
 371         actindex = index;
 372         index &= (mcam->banksize - 1);
 373
 374         /* Disable before mcam entry update */
 375         npc_enable_mcam_entry(rvu, mcam, blkaddr, actindex, false);
 376
 377         /* Clear mcam entry to avoid writes being suppressed by NPC */
 378         npc_clear_mcam_entry(rvu, mcam, blkaddr, actindex);
 379
 380         /* CAM1 takes the comparison value and
 381          * CAM0 specifies match for a bit in key being '0' or '1' or 'dontcare'.
 382          * CAM1<n> = 0 & CAM0<n> = 1 => match if key<n> = 0
 383          * CAM1<n> = 1 & CAM0<n> = 0 => match if key<n> = 1
 384          * CAM1<n> = 0 & CAM0<n> = 0 => always match i.e dontcare.
 385          */
 386         for (; bank < (actbank + mcam->banks_per_entry); bank++, kw = kw + 2) {
 387                 /* Interface should be set in all banks */
 388                 rvu_write64(rvu, blkaddr,
 389                             NPC_AF_MCAMEX_BANKX_CAMX_INTF(index, bank, 1),
 390                             intf);
 391                 rvu_write64(rvu, blkaddr,
 392                             NPC_AF_MCAMEX_BANKX_CAMX_INTF(index, bank, 0),
 393                             ~intf & 0x3);
 394
 395                 /* Set the match key */
 396                 npc_get_keyword(entry, kw, &cam0, &cam1);
 397                 rvu_write64(rvu, blkaddr,
 398                             NPC_AF_MCAMEX_BANKX_CAMX_W0(index, bank, 1), cam1);
 399                 rvu_write64(rvu, blkaddr,
 400                             NPC_AF_MCAMEX_BANKX_CAMX_W0(index, bank, 0), cam0);
 401
 402                 npc_get_keyword(entry, kw + 1, &cam0, &cam1);
 403                 rvu_write64(rvu, blkaddr,
 404                             NPC_AF_MCAMEX_BANKX_CAMX_W1(index, bank, 1), cam1);
 405                 rvu_write64(rvu, blkaddr,
 406                             NPC_AF_MCAMEX_BANKX_CAMX_W1(index, bank, 0), cam0);
 407         }
 408
 409         /* Set 'action' */
 410         rvu_write64(rvu, blkaddr,
 411                     NPC_AF_MCAMEX_BANKX_ACTION(index, actbank), entry->action);
 412
 413         /* Set TAG 'action' */
 414         rvu_write64(rvu, blkaddr, NPC_AF_MCAMEX_BANKX_TAG_ACT(index, actbank),
 415                     entry->vtag_action);
 416
 417         /* Enable the entry */
 418         if (enable)
 419                 npc_enable_mcam_entry(rvu, mcam, blkaddr, actindex, true);
 420 }
 421
 422 static void npc_copy_mcam_entry(struct rvu *rvu, struct npc_mcam *mcam,
 423                                 int blkaddr, u16 src, u16 dest)
 424 {
 425         int dbank = npc_get_bank(mcam, dest);
 426         int sbank = npc_get_bank(mcam, src);
 427         u64 cfg, sreg, dreg;
 428         int bank, i;
 429
 430         src &= (mcam->banksize - 1);
 431         dest &= (mcam->banksize - 1);
 432
 433         /* Copy INTF's, W0's, W1's CAM0 and CAM1 configuration */
 434         for (bank = 0; bank < mcam->banks_per_entry; bank++) {
 435                 sreg = NPC_AF_MCAMEX_BANKX_CAMX_INTF(src, sbank + bank, 0);
 436                 dreg = NPC_AF_MCAMEX_BANKX_CAMX_INTF(dest, dbank + bank, 0);
 437                 for (i = 0; i < 6; i++) {
 438                         cfg = rvu_read64(rvu, blkaddr, sreg + (i * 8));
 439                         rvu_write64(rvu, blkaddr, dreg + (i * 8), cfg);
 440                 }
 441         }
 442
 443         /* Copy action */
 444         cfg = rvu_read64(rvu, blkaddr,
 445                          NPC_AF_MCAMEX_BANKX_ACTION(src, sbank));
 446         rvu_write64(rvu, blkaddr,
 447                     NPC_AF_MCAMEX_BANKX_ACTION(dest, dbank), cfg);
 448
 449         /* Copy TAG action */
 450         cfg = rvu_read64(rvu, blkaddr,
 451                          NPC_AF_MCAMEX_BANKX_TAG_ACT(src, sbank));
 452         rvu_write64(rvu, blkaddr,
 453                     NPC_AF_MCAMEX_BANKX_TAG_ACT(dest, dbank), cfg);
 454
 455         /* Enable or disable */
 456         cfg = rvu_read64(rvu, blkaddr,
 457                          NPC_AF_MCAMEX_BANKX_CFG(src, sbank));
 458         rvu_write64(rvu, blkaddr,
 459                     NPC_AF_MCAMEX_BANKX_CFG(dest, dbank), cfg);
 460 }
 461
 462 static u64 npc_get_mcam_action(struct rvu *rvu, struct npc_mcam *mcam,
 463                                int blkaddr, int index)
 464 {
 465         int bank = npc_get_bank(mcam, index);
 466
 467         index &= (mcam->banksize - 1);
 468         return rvu_read64(rvu, blkaddr,
 469                           NPC_AF_MCAMEX_BANKX_ACTION(index, bank));
 470 }
 471
 472 void rvu_npc_install_ucast_entry(struct rvu *rvu, u16 pcifunc,
 473                                  int nixlf, u64 chan, u8 *mac_addr)
 474 {
 475         struct rvu_pfvf *pfvf = rvu_get_pfvf(rvu, pcifunc);
 476         struct npc_mcam *mcam = &rvu->hw->mcam;
 477         struct mcam_entry entry = { {0} };
 478         struct nix_rx_action action;
 479         int blkaddr, index, kwi;
 480         u64 mac = 0;
 481
 482         /* AF's VFs work in promiscuous mode */
 483         if (is_afvf(pcifunc))
 484                 return;
 485
 486         blkaddr = rvu_get_blkaddr(rvu, BLKTYPE_NPC, 0);
 487         if (blkaddr < 0)
 488                 return;
 489
 490         for (index = ETH_ALEN - 1; index >= 0; index--)
 491                 mac |= ((u64)*mac_addr++) << (8 * index);
 492
 493         index = npc_get_nixlf_mcam_index(mcam, pcifunc,
 494                                          nixlf, NIXLF_UCAST_ENTRY);
 495
 496         /* Match ingress channel and DMAC */
 497         entry.kw[0] = chan;
 498         entry.kw_mask[0] = 0xFFFULL;
 499
 500         kwi = NPC_PARSE_RESULT_DMAC_OFFSET / sizeof(u64);
 501         entry.kw[kwi] = mac;
 502         entry.kw_mask[kwi] = BIT_ULL(48) - 1;
 503
 504         /* Don't change the action if entry is already enabled
 505          * Otherwise RSS action may get overwritten.
 506          */
 507         if (is_mcam_entry_enabled(rvu, mcam, blkaddr, index)) {
 508                 *(u64 *)&action = npc_get_mcam_action(rvu, mcam,
 509                                                       blkaddr, index);
 510         } else {
 511                 *(u64 *)&action = 0x00;
 512                 action.op = NIX_RX_ACTIONOP_UCAST;
 513                 action.pf_func = pcifunc;
 514         }
 515
 516         entry.action = *(u64 *)&action;
 517         npc_config_mcam_entry(rvu, mcam, blkaddr, index,
 518                               pfvf->nix_rx_intf, &entry, true);
 519
 520         /* add VLAN matching, setup action and save entry back for later */
 521         entry.kw[0] |= (NPC_LT_LB_STAG_QINQ | NPC_LT_LB_CTAG) << 20;
 522         entry.kw_mask[0] |= (NPC_LT_LB_STAG_QINQ & NPC_LT_LB_CTAG) << 20;
 523
 524         entry.vtag_action = VTAG0_VALID_BIT |
 525                             FIELD_PREP(VTAG0_TYPE_MASK, 0) |
 526                             FIELD_PREP(VTAG0_LID_MASK, NPC_LID_LA) |
 527                             FIELD_PREP(VTAG0_RELPTR_MASK, 12);
 528
 529         memcpy(&pfvf->entry, &entry, sizeof(entry));
 530 }
 531
 532 void rvu_npc_install_promisc_entry(struct rvu *rvu, u16 pcifunc,
 533                                    int nixlf, u64 chan, bool allmulti)
 534 {
 535         struct rvu_pfvf *pfvf = rvu_get_pfvf(rvu, pcifunc);
 536         struct npc_mcam *mcam = &rvu->hw->mcam;
 537         int blkaddr, ucast_idx, index, kwi;
 538         struct mcam_entry entry = { {0} };
 539         struct nix_rx_action action = { };
 540
 541         /* Only PF or AF VF can add a promiscuous entry */
 542         if ((pcifunc & RVU_PFVF_FUNC_MASK) && !is_afvf(pcifunc))
 543                 return;
 544
 545         blkaddr = rvu_get_blkaddr(rvu, BLKTYPE_NPC, 0);
 546         if (blkaddr < 0)
 547                 return;
 548
 549         index = npc_get_nixlf_mcam_index(mcam, pcifunc,
 550                                          nixlf, NIXLF_PROMISC_ENTRY);
 551
 552         entry.kw[0] = chan;
 553         entry.kw_mask[0] = 0xFFFULL;
 554
 555         if (allmulti) {
 556                 kwi = NPC_KEXOF_DMAC / sizeof(u64);
 557                 entry.kw[kwi] = BIT_ULL(40); /* LSB bit of 1st byte in DMAC */
 558                 entry.kw_mask[kwi] = BIT_ULL(40);
 559         }
 560
 561         ucast_idx = npc_get_nixlf_mcam_index(mcam, pcifunc,
 562                                              nixlf, NIXLF_UCAST_ENTRY);
 563
 564         /* If the corresponding PF's ucast action is RSS,
 565          * use the same action for promisc also
 566          */
 567         if (is_mcam_entry_enabled(rvu, mcam, blkaddr, ucast_idx))
 568                 *(u64 *)&action = npc_get_mcam_action(rvu, mcam,
 569                                                         blkaddr, ucast_idx);
 570
 571         if (action.op != NIX_RX_ACTIONOP_RSS) {
 572                 *(u64 *)&action = 0x00;
 573                 action.op = NIX_RX_ACTIONOP_UCAST;
 574                 action.pf_func = pcifunc;
 575         }
 576
 577         entry.action = *(u64 *)&action;
 578         npc_config_mcam_entry(rvu, mcam, blkaddr, index,
 579                               pfvf->nix_rx_intf, &entry, true);
 580 }
 581
 582 static void npc_enadis_promisc_entry(struct rvu *rvu, u16 pcifunc,
 583                                      int nixlf, bool enable)
 584 {
 585         struct npc_mcam *mcam = &rvu->hw->mcam;
 586         int blkaddr, index;
 587
 588         blkaddr = rvu_get_blkaddr(rvu, BLKTYPE_NPC, 0);
 589         if (blkaddr < 0)
 590                 return;
 591
 592         /* Only PF's have a promiscuous entry */
 593         if (pcifunc & RVU_PFVF_FUNC_MASK)
 594                 return;
 595
 596         index = npc_get_nixlf_mcam_index(mcam, pcifunc,
 597                                          nixlf, NIXLF_PROMISC_ENTRY);
 598         npc_enable_mcam_entry(rvu, mcam, blkaddr, index, enable);
 599 }
 600
 601 void rvu_npc_disable_promisc_entry(struct rvu *rvu, u16 pcifunc, int nixlf)
 602 {
 603         npc_enadis_promisc_entry(rvu, pcifunc, nixlf, false);
 604 }
 605
 606 void rvu_npc_enable_promisc_entry(struct rvu *rvu, u16 pcifunc, int nixlf)
 607 {
 608         npc_enadis_promisc_entry(rvu, pcifunc, nixlf, true);
 609 }
 610
 611 void rvu_npc_install_bcast_match_entry(struct rvu *rvu, u16 pcifunc,
 612                                        int nixlf, u64 chan)
 613 {
 614         struct npc_mcam *mcam = &rvu->hw->mcam;
 615         struct mcam_entry entry = { {0} };
 616         struct rvu_hwinfo *hw = rvu->hw;
 617         struct nix_rx_action action;
 618         struct rvu_pfvf *pfvf;
 619         int blkaddr, index;
 620
 621         blkaddr = rvu_get_blkaddr(rvu, BLKTYPE_NPC, 0);
 622         if (blkaddr < 0)
 623                 return;
 624
 625         /* Skip LBK VFs */
 626         if (is_afvf(pcifunc))
 627                 return;
 628
 629         /* If pkt replication is not supported,
 630          * then only PF is allowed to add a bcast match entry.
 631          */
 632         if (!hw->cap.nix_rx_multicast && pcifunc & RVU_PFVF_FUNC_MASK)
 633                 return;
 634
 635         /* Get 'pcifunc' of PF device */
 636         pcifunc = pcifunc & ~RVU_PFVF_FUNC_MASK;
 637         pfvf = rvu_get_pfvf(rvu, pcifunc);
 638         index = npc_get_nixlf_mcam_index(mcam, pcifunc,
 639                                          nixlf, NIXLF_BCAST_ENTRY);
 640
 641         /* Match ingress channel */
 642         entry.kw[0] = chan;
 643         entry.kw_mask[0] = 0xfffull;
 644
 645         /* Match broadcast MAC address.
 646          * DMAC is extracted at 0th bit of PARSE_KEX::KW1
 647          */
 648         entry.kw[1] = 0xffffffffffffull;
 649         entry.kw_mask[1] = 0xffffffffffffull;
 650
 651         *(u64 *)&action = 0x00;
 652         if (!hw->cap.nix_rx_multicast) {
 653                 /* Early silicon doesn't support pkt replication,
 654                  * so install entry with UCAST action, so that PF
 655                  * receives all broadcast packets.
 656                  */
 657                 action.op = NIX_RX_ACTIONOP_UCAST;
 658                 action.pf_func = pcifunc;
 659         } else {
 660                 action.index = pfvf->bcast_mce_idx;
 661                 action.op = NIX_RX_ACTIONOP_MCAST;
 662         }
 663
 664         entry.action = *(u64 *)&action;
 665         npc_config_mcam_entry(rvu, mcam, blkaddr, index,
 666                               pfvf->nix_rx_intf, &entry, true);
 667 }
 668
 669 void rvu_npc_enable_bcast_entry(struct rvu *rvu, u16 pcifunc, bool enable)
 670 {
 671         struct npc_mcam *mcam = &rvu->hw->mcam;
 672         int blkaddr, index;
 673
 674         blkaddr = rvu_get_blkaddr(rvu, BLKTYPE_NPC, 0);
 675         if (blkaddr < 0)
 676                 return;
 677
 678         /* Get 'pcifunc' of PF device */
 679         pcifunc = pcifunc & ~RVU_PFVF_FUNC_MASK;
 680
 681         index = npc_get_nixlf_mcam_index(mcam, pcifunc, 0, NIXLF_BCAST_ENTRY);
 682         npc_enable_mcam_entry(rvu, mcam, blkaddr, index, enable);
 683 }
 684
 685 void rvu_npc_update_flowkey_alg_idx(struct rvu *rvu, u16 pcifunc, int nixlf,
 686                                     int group, int alg_idx, int mcam_index)
 687 {
 688         struct npc_mcam *mcam = &rvu->hw->mcam;
 689         struct nix_rx_action action;
 690         int blkaddr, index, bank;
 691
 692         blkaddr = rvu_get_blkaddr(rvu, BLKTYPE_NPC, 0);
 693         if (blkaddr < 0)
 694                 return;
 695
 696         /* Check if this is for reserved default entry */
 697         if (mcam_index < 0) {
 698                 if (group != DEFAULT_RSS_CONTEXT_GROUP)
 699                         return;
 700                 index = npc_get_nixlf_mcam_index(mcam, pcifunc,
 701                                                  nixlf, NIXLF_UCAST_ENTRY);
 702         } else {
 703                 /* TODO: validate this mcam index */
 704                 index = mcam_index;
 705         }
 706
 707         if (index >= mcam->total_entries)
 708                 return;
 709
 710         bank = npc_get_bank(mcam, index);
 711         index &= (mcam->banksize - 1);
 712
 713         *(u64 *)&action = rvu_read64(rvu, blkaddr,
 714                                      NPC_AF_MCAMEX_BANKX_ACTION(index, bank));
 715         /* Ignore if no action was set earlier */
 716         if (!*(u64 *)&action)
 717                 return;
 718
 719         action.op = NIX_RX_ACTIONOP_RSS;
 720         action.pf_func = pcifunc;
 721         action.index = group;
 722         action.flow_key_alg = alg_idx;
 723
 724         rvu_write64(rvu, blkaddr,
 725                     NPC_AF_MCAMEX_BANKX_ACTION(index, bank), *(u64 *)&action);
 726
 727         index = npc_get_nixlf_mcam_index(mcam, pcifunc,
 728                                          nixlf, NIXLF_PROMISC_ENTRY);
 729
 730         /* If PF's promiscuous entry is enabled,
 731          * Set RSS action for that entry as well
 732          */
 733         if (is_mcam_entry_enabled(rvu, mcam, blkaddr, index)) {
 734                 bank = npc_get_bank(mcam, index);
 735                 index &= (mcam->banksize - 1);
 736
 737                 rvu_write64(rvu, blkaddr,
 738                             NPC_AF_MCAMEX_BANKX_ACTION(index, bank),
 739                             *(u64 *)&action);
 740         }
 741
 742         rvu_npc_update_rxvlan(rvu, pcifunc, nixlf);
 743 }
 744
 745 static void npc_enadis_default_entries(struct rvu *rvu, u16 pcifunc,
 746                                        int nixlf, bool enable)
 747 {
 748         struct npc_mcam *mcam = &rvu->hw->mcam;
 749         struct nix_rx_action action;
 750         int index, bank, blkaddr;
 751
 752         blkaddr = rvu_get_blkaddr(rvu, BLKTYPE_NPC, 0);
 753         if (blkaddr < 0)
 754                 return;
 755
 756         /* Ucast MCAM match entry of this PF/VF */
 757         index = npc_get_nixlf_mcam_index(mcam, pcifunc,
 758                                          nixlf, NIXLF_UCAST_ENTRY);
 759         npc_enable_mcam_entry(rvu, mcam, blkaddr, index, enable);
 760
 761         /* For PF, ena/dis promisc and bcast MCAM match entries.
 762          * For VFs add/delete from bcast list when RX multicast
 763          * feature is present.
 764          */
 765         if (pcifunc & RVU_PFVF_FUNC_MASK && !rvu->hw->cap.nix_rx_multicast)
 766                 return;
 767
 768         /* For bcast, enable/disable only if it's action is not
 769          * packet replication, incase if action is replication
 770          * then this PF/VF's nixlf is removed from bcast replication
 771          * list.
 772          */
 773         index = npc_get_nixlf_mcam_index(mcam, pcifunc & ~RVU_PFVF_FUNC_MASK,
 774                                          nixlf, NIXLF_BCAST_ENTRY);
 775         bank = npc_get_bank(mcam, index);
 776         *(u64 *)&action = rvu_read64(rvu, blkaddr,
 777              NPC_AF_MCAMEX_BANKX_ACTION(index & (mcam->banksize - 1), bank));
 778
 779         /* VFs will not have BCAST entry */
 780         if (action.op != NIX_RX_ACTIONOP_MCAST &&
 781             !(pcifunc & RVU_PFVF_FUNC_MASK)) {
 782                 npc_enable_mcam_entry(rvu, mcam,
 783                                       blkaddr, index, enable);
 784         } else {
 785                 nix_update_bcast_mce_list(rvu, pcifunc, enable);
 786                 /* Enable PF's BCAST entry for packet replication */
 787                 rvu_npc_enable_bcast_entry(rvu, pcifunc, enable);
 788         }
 789
 790         if (enable)
 791                 rvu_npc_enable_promisc_entry(rvu, pcifunc, nixlf);
 792         else
 793                 rvu_npc_disable_promisc_entry(rvu, pcifunc, nixlf);
 794
 795         rvu_npc_update_rxvlan(rvu, pcifunc, nixlf);
 796 }
 797
 798 void rvu_npc_disable_default_entries(struct rvu *rvu, u16 pcifunc, int nixlf)
 799 {
 800         npc_enadis_default_entries(rvu, pcifunc, nixlf, false);
 801 }
 802
 803 void rvu_npc_enable_default_entries(struct rvu *rvu, u16 pcifunc, int nixlf)
 804 {
 805         npc_enadis_default_entries(rvu, pcifunc, nixlf, true);
 806 }
 807
 808 void rvu_npc_disable_mcam_entries(struct rvu *rvu, u16 pcifunc, int nixlf)
 809 {
 810         struct npc_mcam *mcam = &rvu->hw->mcam;
 811         int blkaddr;
 812
 813         blkaddr = rvu_get_blkaddr(rvu, BLKTYPE_NPC, 0);
 814         if (blkaddr < 0)
 815                 return;
 816
 817         mutex_lock(&mcam->lock);
 818
 819         /* Disable and free all MCAM entries mapped to this 'pcifunc' */
 820         npc_mcam_free_all_entries(rvu, mcam, blkaddr, pcifunc);
 821
 822         /* Free all MCAM counters mapped to this 'pcifunc' */
 823         npc_mcam_free_all_counters(rvu, mcam, pcifunc);
 824
 825         mutex_unlock(&mcam->lock);
 826
 827         rvu_npc_disable_default_entries(rvu, pcifunc, nixlf);
 828 }
 829
 830 #define SET_KEX_LD(intf, lid, ltype, ld, cfg)   \
 831         rvu_write64(rvu, blkaddr,                       \
 832                 NPC_AF_INTFX_LIDX_LTX_LDX_CFG(intf, lid, ltype, ld), cfg)
 833
 834 #define SET_KEX_LDFLAGS(intf, ld, flags, cfg)   \
 835         rvu_write64(rvu, blkaddr,                       \
 836                 NPC_AF_INTFX_LDATAX_FLAGSX_CFG(intf, ld, flags), cfg)
 837
 838 static void npc_program_mkex_rx(struct rvu *rvu, int blkaddr,
 839                                 struct npc_mcam_kex *mkex, u8 intf)
 840 {
 841         int lid, lt, ld, fl;
 842
 843         if (is_npc_intf_tx(intf))
 844                 return;
 845
 846         rvu_write64(rvu, blkaddr, NPC_AF_INTFX_KEX_CFG(intf),
 847                     mkex->keyx_cfg[NIX_INTF_RX]);
 848
 849         /* Program LDATA */
 850         for (lid = 0; lid < NPC_MAX_LID; lid++) {
 851                 for (lt = 0; lt < NPC_MAX_LT; lt++) {
 852                         for (ld = 0; ld < NPC_MAX_LD; ld++)
 853                                 SET_KEX_LD(intf, lid, lt, ld,
 854                                            mkex->intf_lid_lt_ld[NIX_INTF_RX]
 855                                            [lid][lt][ld]);
 856                 }
 857         }
 858         /* Program LFLAGS */
 859         for (ld = 0; ld < NPC_MAX_LD; ld++) {
 860                 for (fl = 0; fl < NPC_MAX_LFL; fl++)
 861                         SET_KEX_LDFLAGS(intf, ld, fl,
 862                                         mkex->intf_ld_flags[NIX_INTF_RX]
 863                                         [ld][fl]);
 864         }
 865 }
 866
 867 static void npc_program_mkex_tx(struct rvu *rvu, int blkaddr,
 868                                 struct npc_mcam_kex *mkex, u8 intf)
 869 {
 870         int lid, lt, ld, fl;
 871
 872         if (is_npc_intf_rx(intf))
 873                 return;
 874
 875         rvu_write64(rvu, blkaddr, NPC_AF_INTFX_KEX_CFG(intf),
 876                     mkex->keyx_cfg[NIX_INTF_TX]);
 877
 878         /* Program LDATA */
 879         for (lid = 0; lid < NPC_MAX_LID; lid++) {
 880                 for (lt = 0; lt < NPC_MAX_LT; lt++) {
 881                         for (ld = 0; ld < NPC_MAX_LD; ld++)
 882                                 SET_KEX_LD(intf, lid, lt, ld,
 883                                            mkex->intf_lid_lt_ld[NIX_INTF_TX]
 884                                            [lid][lt][ld]);
 885                 }
 886         }
 887         /* Program LFLAGS */
 888         for (ld = 0; ld < NPC_MAX_LD; ld++) {
 889                 for (fl = 0; fl < NPC_MAX_LFL; fl++)
 890                         SET_KEX_LDFLAGS(intf, ld, fl,
 891                                         mkex->intf_ld_flags[NIX_INTF_TX]
 892                                         [ld][fl]);
 893         }
 894 }
 895
 896 static void npc_program_mkex_profile(struct rvu *rvu, int blkaddr,
 897                                      struct npc_mcam_kex *mkex)
 898 {
 899         struct rvu_hwinfo *hw = rvu->hw;
 900         u8 intf;
 901         int ld;
 902
 903         for (ld = 0; ld < NPC_MAX_LD; ld++)
 904                 rvu_write64(rvu, blkaddr, NPC_AF_KEX_LDATAX_FLAGS_CFG(ld),
 905                             mkex->kex_ld_flags[ld]);
 906
 907         for (intf = 0; intf < hw->npc_intfs; intf++) {
 908                 npc_program_mkex_rx(rvu, blkaddr, mkex, intf);
 909                 npc_program_mkex_tx(rvu, blkaddr, mkex, intf);
 910         }
 911 }
 912
 913 #define MKEX_END_SIGN  0xdeadbeef
 914
 915 static void npc_load_mkex_profile(struct rvu *rvu, int blkaddr,
 916                                   const char *mkex_profile)
 917 {
 918         struct device *dev = &rvu->pdev->dev;
 919         struct npc_mcam_kex *mcam_kex;
 920         void *mkex_prfl_addr = NULL;
 921         u64 prfl_addr, prfl_sz;
 922
 923         /* If user not selected mkex profile */
 924         if (!strncmp(mkex_profile, def_pfl_name, MKEX_NAME_LEN))
 925                 goto program_mkex;
 926
 927         if (!rvu->fwdata)
 928                 goto program_mkex;
 929         prfl_addr = rvu->fwdata->mcam_addr;
 930         prfl_sz = rvu->fwdata->mcam_sz;
 931
 932         if (!prfl_addr || !prfl_sz)
 933                 goto program_mkex;
 934
 935         mkex_prfl_addr = memremap(prfl_addr, prfl_sz, MEMREMAP_WC);
 936         if (!mkex_prfl_addr)
 937                 goto program_mkex;
 938
 939         mcam_kex = (struct npc_mcam_kex *)mkex_prfl_addr;
 940
 941         while (((s64)prfl_sz > 0) && (mcam_kex->mkex_sign != MKEX_END_SIGN)) {
 942                 /* Compare with mkex mod_param name string */
 943                 if (mcam_kex->mkex_sign == MKEX_SIGN &&
 944                     !strncmp(mcam_kex->name, mkex_profile, MKEX_NAME_LEN)) {
 945                         /* Due to an errata (35786) in A0/B0 pass silicon,
 946                          * parse nibble enable configuration has to be
 947                          * identical for both Rx and Tx interfaces.
 948                          */
 949                         if (!is_rvu_96xx_B0(rvu) ||
 950                             mcam_kex->keyx_cfg[NIX_INTF_RX] == mcam_kex->keyx_cfg[NIX_INTF_TX])
 951                                 rvu->kpu.mkex = mcam_kex;
 952                         goto program_mkex;
 953                 }
 954
 955                 mcam_kex++;
 956                 prfl_sz -= sizeof(struct npc_mcam_kex);
 957         }
 958         dev_warn(dev, "Failed to load requested profile: %s\n", mkex_profile);
 959
 960 program_mkex:
 961         dev_info(rvu->dev, "Using %s mkex profile\n", rvu->kpu.mkex->name);
 962         /* Program selected mkex profile */
 963         npc_program_mkex_profile(rvu, blkaddr, rvu->kpu.mkex);
 964         if (mkex_prfl_addr)
 965                 memunmap(mkex_prfl_addr);
 966 }
 967
 968 static void npc_config_kpuaction(struct rvu *rvu, int blkaddr,
 969                                  const struct npc_kpu_profile_action *kpuaction,
 970                                  int kpu, int entry, bool pkind)
 971 {
 972         struct npc_kpu_action0 action0 = {0};
 973         struct npc_kpu_action1 action1 = {0};
 974         u64 reg;
 975
 976         action1.errlev = kpuaction->errlev;
 977         action1.errcode = kpuaction->errcode;
 978         action1.dp0_offset = kpuaction->dp0_offset;
 979         action1.dp1_offset = kpuaction->dp1_offset;
 980         action1.dp2_offset = kpuaction->dp2_offset;
 981
 982         if (pkind)
 983                 reg = NPC_AF_PKINDX_ACTION1(entry);
 984         else
 985                 reg = NPC_AF_KPUX_ENTRYX_ACTION1(kpu, entry);
 986
 987         rvu_write64(rvu, blkaddr, reg, *(u64 *)&action1);
 988
 989         action0.byp_count = kpuaction->bypass_count;
 990         action0.capture_ena = kpuaction->cap_ena;
 991         action0.parse_done = kpuaction->parse_done;
 992         action0.next_state = kpuaction->next_state;
 993         action0.capture_lid = kpuaction->lid;
 994         action0.capture_ltype = kpuaction->ltype;
 995         action0.capture_flags = kpuaction->flags;
 996         action0.ptr_advance = kpuaction->ptr_advance;
 997         action0.var_len_offset = kpuaction->offset;
 998         action0.var_len_mask = kpuaction->mask;
 999         action0.var_len_right = kpuaction->right;
1000         action0.var_len_shift = kpuaction->shift;
1001
1002         if (pkind)
1003                 reg = NPC_AF_PKINDX_ACTION0(entry);
1004         else
1005                 reg = NPC_AF_KPUX_ENTRYX_ACTION0(kpu, entry);
1006
1007         rvu_write64(rvu, blkaddr, reg, *(u64 *)&action0);
1008 }
1009
1010 static void npc_config_kpucam(struct rvu *rvu, int blkaddr,
1011                               const struct npc_kpu_profile_cam *kpucam,
1012                               int kpu, int entry)
1013 {
1014         struct npc_kpu_cam cam0 = {0};
1015         struct npc_kpu_cam cam1 = {0};
1016
1017         cam1.state = kpucam->state & kpucam->state_mask;
1018         cam1.dp0_data = kpucam->dp0 & kpucam->dp0_mask;
1019         cam1.dp1_data = kpucam->dp1 & kpucam->dp1_mask;
1020         cam1.dp2_data = kpucam->dp2 & kpucam->dp2_mask;
1021
1022         cam0.state = ~kpucam->state & kpucam->state_mask;
1023         cam0.dp0_data = ~kpucam->dp0 & kpucam->dp0_mask;
1024         cam0.dp1_data = ~kpucam->dp1 & kpucam->dp1_mask;
1025         cam0.dp2_data = ~kpucam->dp2 & kpucam->dp2_mask;
1026
1027         rvu_write64(rvu, blkaddr,
1028                     NPC_AF_KPUX_ENTRYX_CAMX(kpu, entry, 0), *(u64 *)&cam0);
1029         rvu_write64(rvu, blkaddr,
1030                     NPC_AF_KPUX_ENTRYX_CAMX(kpu, entry, 1), *(u64 *)&cam1);
1031 }
1032
1033 static inline u64 enable_mask(int count)
1034 {
1035         return (((count) < 64) ? ~(BIT_ULL(count) - 1) : (0x00ULL));
1036 }
1037
1038 static void npc_program_kpu_profile(struct rvu *rvu, int blkaddr, int kpu,
1039                                     const struct npc_kpu_profile *profile)
1040 {
1041         int entry, num_entries, max_entries;
1042
1043         if (profile->cam_entries != profile->action_entries) {
1044                 dev_err(rvu->dev,
1045                         "KPU%d: CAM and action entries [%d != %d] not equal\n",
1046                         kpu, profile->cam_entries, profile->action_entries);
1047         }
1048
1049         max_entries = rvu->hw->npc_kpu_entries;
1050
1051         /* Program CAM match entries for previous KPU extracted data */
1052         num_entries = min_t(int, profile->cam_entries, max_entries);
1053         for (entry = 0; entry < num_entries; entry++)
1054                 npc_config_kpucam(rvu, blkaddr,
1055                                   &profile->cam[entry], kpu, entry);
1056
1057         /* Program this KPU's actions */
1058         num_entries = min_t(int, profile->action_entries, max_entries);
1059         for (entry = 0; entry < num_entries; entry++)
1060                 npc_config_kpuaction(rvu, blkaddr, &profile->action[entry],
1061                                      kpu, entry, false);
1062
1063         /* Enable all programmed entries */
1064         num_entries = min_t(int, profile->action_entries, profile->cam_entries);
1065         rvu_write64(rvu, blkaddr,
1066                     NPC_AF_KPUX_ENTRY_DISX(kpu, 0), enable_mask(num_entries));
1067         if (num_entries > 64) {
1068                 rvu_write64(rvu, blkaddr,
1069                             NPC_AF_KPUX_ENTRY_DISX(kpu, 1),
1070                             enable_mask(num_entries - 64));
1071         }
1072
1073         /* Enable this KPU */
1074         rvu_write64(rvu, blkaddr, NPC_AF_KPUX_CFG(kpu), 0x01);
1075 }
1076
1077 static int npc_prepare_default_kpu(struct npc_kpu_profile_adapter *profile)
1078 {
1079         profile->name = def_pfl_name;
1080         profile->version = NPC_KPU_PROFILE_VER;
1081         profile->ikpu = ikpu_action_entries;
1082         profile->pkinds = ARRAY_SIZE(ikpu_action_entries);
1083         profile->kpu = npc_kpu_profiles;
1084         profile->kpus = ARRAY_SIZE(npc_kpu_profiles);
1085         profile->lt_def = &npc_lt_defaults;
1086         profile->mkex = &npc_mkex_default;
1087
1088         return 0;
1089 }
1090
1091 static void npc_load_kpu_profile(struct rvu *rvu)
1092 {
1093         struct npc_kpu_profile_adapter *profile = &rvu->kpu;
1094
1095         npc_prepare_default_kpu(profile);
1096 }
1097
1098 static void npc_parser_profile_init(struct rvu *rvu, int blkaddr)
1099 {
1100         struct rvu_hwinfo *hw = rvu->hw;
1101         int num_pkinds, num_kpus, idx;
1102         struct npc_pkind *pkind;
1103
1104         /* Disable all KPUs and their entries */
1105         for (idx = 0; idx < hw->npc_kpus; idx++) {
1106                 rvu_write64(rvu, blkaddr,
1107                             NPC_AF_KPUX_ENTRY_DISX(idx, 0), ~0ULL);
1108                 rvu_write64(rvu, blkaddr,
1109                             NPC_AF_KPUX_ENTRY_DISX(idx, 1), ~0ULL);
1110                 rvu_write64(rvu, blkaddr, NPC_AF_KPUX_CFG(idx), 0x00);
1111         }
1112
1113         /* Load and customize KPU profile. */
1114         npc_load_kpu_profile(rvu);
1115
1116         /* First program IKPU profile i.e PKIND configs.
1117          * Check HW max count to avoid configuring junk or
1118          * writing to unsupported CSR addresses.
1119          */
1120         pkind = &hw->pkind;
1121         num_pkinds = rvu->kpu.pkinds;
1122         num_pkinds = min_t(int, pkind->rsrc.max, num_pkinds);
1123
1124         for (idx = 0; idx < num_pkinds; idx++)
1125                 npc_config_kpuaction(rvu, blkaddr, &rvu->kpu.ikpu[idx], 0, idx, true);
1126
1127         /* Program KPU CAM and Action profiles */
1128         num_kpus = rvu->kpu.kpus;
1129         num_kpus = min_t(int, hw->npc_kpus, num_kpus);
1130
1131         for (idx = 0; idx < num_kpus; idx++)
1132                 npc_program_kpu_profile(rvu, blkaddr, idx, &rvu->kpu.kpu[idx]);
1133 }
1134
1135 static int npc_mcam_rsrcs_init(struct rvu *rvu, int blkaddr)
1136 {
1137         int nixlf_count = rvu_get_nixlf_count(rvu);
1138         struct npc_mcam *mcam = &rvu->hw->mcam;
1139         int rsvd, err;
1140         u64 cfg;
1141
1142         /* Actual number of MCAM entries vary by entry size */
1143         cfg = (rvu_read64(rvu, blkaddr,
1144                           NPC_AF_INTFX_KEX_CFG(0)) >> 32) & 0x07;
1145         mcam->total_entries = (mcam->banks / BIT_ULL(cfg)) * mcam->banksize;
1146         mcam->keysize = cfg;
1147
1148         /* Number of banks combined per MCAM entry */
1149         if (cfg == NPC_MCAM_KEY_X4)
1150                 mcam->banks_per_entry = 4;
1151         else if (cfg == NPC_MCAM_KEY_X2)
1152                 mcam->banks_per_entry = 2;
1153         else
1154                 mcam->banks_per_entry = 1;
1155
1156         /* Reserve one MCAM entry for each of the NIX LF to
1157          * guarantee space to install default matching DMAC rule.
1158          * Also reserve 2 MCAM entries for each PF for default
1159          * channel based matching or 'bcast & promisc' matching to
1160          * support BCAST and PROMISC modes of operation for PFs.
1161          * PF0 is excluded.
1162          */
1163         rsvd = (nixlf_count * RSVD_MCAM_ENTRIES_PER_NIXLF) +
1164                 ((rvu->hw->total_pfs - 1) * RSVD_MCAM_ENTRIES_PER_PF);
1165         if (mcam->total_entries <= rsvd) {
1166                 dev_warn(rvu->dev,
1167                          "Insufficient NPC MCAM size %d for pkt I/O, exiting\n",
1168                          mcam->total_entries);
1169                 return -ENOMEM;
1170         }
1171
1172         mcam->bmap_entries = mcam->total_entries - rsvd;
1173         mcam->nixlf_offset = mcam->bmap_entries;
1174         mcam->pf_offset = mcam->nixlf_offset + nixlf_count;
1175
1176         /* Allocate bitmaps for managing MCAM entries */
1177         mcam->bmap = devm_kcalloc(rvu->dev, BITS_TO_LONGS(mcam->bmap_entries),
1178                                   sizeof(long), GFP_KERNEL);
1179         if (!mcam->bmap)
1180                 return -ENOMEM;
1181
1182         mcam->bmap_reverse = devm_kcalloc(rvu->dev,
1183                                           BITS_TO_LONGS(mcam->bmap_entries),
1184                                           sizeof(long), GFP_KERNEL);
1185         if (!mcam->bmap_reverse)
1186                 return -ENOMEM;
1187
1188         mcam->bmap_fcnt = mcam->bmap_entries;
1189
1190         /* Alloc memory for saving entry to RVU PFFUNC allocation mapping */
1191         mcam->entry2pfvf_map = devm_kcalloc(rvu->dev, mcam->bmap_entries,
1192                                             sizeof(u16), GFP_KERNEL);
1193         if (!mcam->entry2pfvf_map)
1194                 return -ENOMEM;
1195
1196         /* Reserve 1/8th of MCAM entries at the bottom for low priority
1197          * allocations and another 1/8th at the top for high priority
1198          * allocations.
1199          */
1200         mcam->lprio_count = mcam->bmap_entries / 8;
1201         if (mcam->lprio_count > BITS_PER_LONG)
1202                 mcam->lprio_count = round_down(mcam->lprio_count,
1203                                                BITS_PER_LONG);
1204         mcam->lprio_start = mcam->bmap_entries - mcam->lprio_count;
1205         mcam->hprio_count = mcam->lprio_count;
1206         mcam->hprio_end = mcam->hprio_count;
1207
1208
1209         /* Allocate bitmap for managing MCAM counters and memory
1210          * for saving counter to RVU PFFUNC allocation mapping.
1211          */
1212         err = rvu_alloc_bitmap(&mcam->counters);
1213         if (err)
1214                 return err;
1215
1216         mcam->cntr2pfvf_map = devm_kcalloc(rvu->dev, mcam->counters.max,
1217                                            sizeof(u16), GFP_KERNEL);
1218         if (!mcam->cntr2pfvf_map)
1219                 goto free_mem;
1220
1221         /* Alloc memory for MCAM entry to counter mapping and for tracking
1222          * counter's reference count.
1223          */
1224         mcam->entry2cntr_map = devm_kcalloc(rvu->dev, mcam->bmap_entries,
1225                                             sizeof(u16), GFP_KERNEL);
1226         if (!mcam->entry2cntr_map)
1227                 goto free_mem;
1228
1229         mcam->cntr_refcnt = devm_kcalloc(rvu->dev, mcam->counters.max,
1230                                          sizeof(u16), GFP_KERNEL);
1231         if (!mcam->cntr_refcnt)
1232                 goto free_mem;
1233
1234         mutex_init(&mcam->lock);
1235
1236         return 0;
1237
1238 free_mem:
1239         kfree(mcam->counters.bmap);
1240         return -ENOMEM;
1241 }
1242
1243 static void rvu_npc_hw_init(struct rvu *rvu, int blkaddr)
1244 {
1245         struct npc_pkind *pkind = &rvu->hw->pkind;
1246         struct npc_mcam *mcam = &rvu->hw->mcam;
1247         struct rvu_hwinfo *hw = rvu->hw;
1248         u64 npc_const, npc_const1;
1249         u64 npc_const2 = 0;
1250
1251         npc_const = rvu_read64(rvu, blkaddr, NPC_AF_CONST);
1252         npc_const1 = rvu_read64(rvu, blkaddr, NPC_AF_CONST1);
1253         if (npc_const1 & BIT_ULL(63))
1254                 npc_const2 = rvu_read64(rvu, blkaddr, NPC_AF_CONST2);
1255
1256         pkind->rsrc.max = (npc_const1 >> 12) & 0xFFULL;
1257         hw->npc_kpu_entries = npc_const1 & 0xFFFULL;
1258         hw->npc_kpus = (npc_const >> 8) & 0x1FULL;
1259         hw->npc_intfs = npc_const & 0xFULL;
1260         hw->npc_counters = (npc_const >> 48) & 0xFFFFULL;
1261
1262         mcam->banks = (npc_const >> 44) & 0xFULL;
1263         mcam->banksize = (npc_const >> 28) & 0xFFFFULL;
1264         /* Extended set */
1265         if (npc_const2) {
1266                 hw->npc_ext_set = true;
1267                 hw->npc_counters = (npc_const2 >> 16) & 0xFFFFULL;
1268                 mcam->banksize = npc_const2 & 0xFFFFULL;
1269         }
1270
1271         mcam->counters.max = hw->npc_counters;
1272 }
1273
1274 static void rvu_npc_setup_interfaces(struct rvu *rvu, int blkaddr)
1275 {
1276         struct npc_mcam *mcam = &rvu->hw->mcam;
1277         struct rvu_hwinfo *hw = rvu->hw;
1278         u64 nibble_ena, rx_kex, tx_kex;
1279         u8 intf;
1280
1281         /* Reserve last counter for MCAM RX miss action which is set to
1282          * drop packet. This way we will know how many pkts didn't match
1283          * any MCAM entry.
1284          */
1285         mcam->counters.max--;
1286         mcam->rx_miss_act_cntr = mcam->counters.max;
1287
1288         rx_kex = npc_mkex_default.keyx_cfg[NIX_INTF_RX];
1289         tx_kex = npc_mkex_default.keyx_cfg[NIX_INTF_TX];
1290         nibble_ena = FIELD_GET(NPC_PARSE_NIBBLE, rx_kex);
1291
1292         nibble_ena = rvu_npc_get_tx_nibble_cfg(rvu, nibble_ena);
1293         if (nibble_ena) {
1294                 tx_kex &= ~NPC_PARSE_NIBBLE;
1295                 tx_kex |= FIELD_PREP(NPC_PARSE_NIBBLE, nibble_ena);
1296                 npc_mkex_default.keyx_cfg[NIX_INTF_TX] = tx_kex;
1297         }
1298
1299         /* Configure RX interfaces */
1300         for (intf = 0; intf < hw->npc_intfs; intf++) {
1301                 if (is_npc_intf_tx(intf))
1302                         continue;
1303
1304                 /* Set RX MCAM search key size. LA..LE (ltype only) + Channel */
1305                 rvu_write64(rvu, blkaddr, NPC_AF_INTFX_KEX_CFG(intf),
1306                             rx_kex);
1307
1308                 /* If MCAM lookup doesn't result in a match, drop the received
1309                  * packet. And map this action to a counter to count dropped
1310                  * packets.
1311                  */
1312                 rvu_write64(rvu, blkaddr,
1313                             NPC_AF_INTFX_MISS_ACT(intf), NIX_RX_ACTIONOP_DROP);
1314
1315                 /* NPC_AF_INTFX_MISS_STAT_ACT[14:12] - counter[11:9]
1316                  * NPC_AF_INTFX_MISS_STAT_ACT[8:0] - counter[8:0]
1317                  */
1318                 rvu_write64(rvu, blkaddr,
1319                             NPC_AF_INTFX_MISS_STAT_ACT(intf),
1320                             ((mcam->rx_miss_act_cntr >> 9) << 12) |
1321                             BIT_ULL(9) | mcam->rx_miss_act_cntr);
1322         }
1323
1324         /* Configure TX interfaces */
1325         for (intf = 0; intf < hw->npc_intfs; intf++) {
1326                 if (is_npc_intf_rx(intf))
1327                         continue;
1328
1329                 /* Extract Ltypes LID_LA to LID_LE */
1330                 rvu_write64(rvu, blkaddr, NPC_AF_INTFX_KEX_CFG(intf),
1331                             tx_kex);
1332
1333                 /* Set TX miss action to UCAST_DEFAULT i.e
1334                  * transmit the packet on NIX LF SQ's default channel.
1335                  */
1336                 rvu_write64(rvu, blkaddr,
1337                             NPC_AF_INTFX_MISS_ACT(intf),
1338                             NIX_TX_ACTIONOP_UCAST_DEFAULT);
1339         }
1340 }
1341
1342 int rvu_npc_init(struct rvu *rvu)
1343 {
1344         struct npc_kpu_profile_adapter *kpu = &rvu->kpu;
1345         struct npc_pkind *pkind = &rvu->hw->pkind;
1346         struct npc_mcam *mcam = &rvu->hw->mcam;
1347         int blkaddr, entry, bank, err;
1348
1349         blkaddr = rvu_get_blkaddr(rvu, BLKTYPE_NPC, 0);
1350         if (blkaddr < 0) {
1351                 dev_err(rvu->dev, "%s: NPC block not implemented\n", __func__);
1352                 return -ENODEV;
1353         }
1354
1355         rvu_npc_hw_init(rvu, blkaddr);
1356
1357         /* First disable all MCAM entries, to stop traffic towards NIXLFs */
1358         for (bank = 0; bank < mcam->banks; bank++) {
1359                 for (entry = 0; entry < mcam->banksize; entry++)
1360                         rvu_write64(rvu, blkaddr,
1361                                     NPC_AF_MCAMEX_BANKX_CFG(entry, bank), 0);
1362         }
1363
1364         err = rvu_alloc_bitmap(&pkind->rsrc);
1365         if (err)
1366                 return err;
1367
1368         /* Allocate mem for pkind to PF and channel mapping info */
1369         pkind->pfchan_map = devm_kcalloc(rvu->dev, pkind->rsrc.max,
1370                                          sizeof(u32), GFP_KERNEL);
1371         if (!pkind->pfchan_map)
1372                 return -ENOMEM;
1373
1374         /* Configure KPU profile */
1375         npc_parser_profile_init(rvu, blkaddr);
1376
1377         /* Config Outer L2, IPv4's NPC layer info */
1378         rvu_write64(rvu, blkaddr, NPC_AF_PCK_DEF_OL2,
1379                     (kpu->lt_def->pck_ol2.lid << 8) | (kpu->lt_def->pck_ol2.ltype_match << 4) |
1380                     kpu->lt_def->pck_ol2.ltype_mask);
1381         rvu_write64(rvu, blkaddr, NPC_AF_PCK_DEF_OIP4,
1382                     (kpu->lt_def->pck_oip4.lid << 8) | (kpu->lt_def->pck_oip4.ltype_match << 4) |
1383                     kpu->lt_def->pck_oip4.ltype_mask);
1384
1385         /* Config Inner IPV4 NPC layer info */
1386         rvu_write64(rvu, blkaddr, NPC_AF_PCK_DEF_IIP4,
1387                     (kpu->lt_def->pck_iip4.lid << 8) | (kpu->lt_def->pck_iip4.ltype_match << 4) |
1388                     kpu->lt_def->pck_iip4.ltype_mask);
1389
1390         /* Enable below for Rx pkts.
1391          * - Outer IPv4 header checksum validation.
1392          * - Detect outer L2 broadcast address and set NPC_RESULT_S[L2M].
1393          * - Inner IPv4 header checksum validation.
1394          * - Set non zero checksum error code value
1395          */
1396         rvu_write64(rvu, blkaddr, NPC_AF_PCK_CFG,
1397                     rvu_read64(rvu, blkaddr, NPC_AF_PCK_CFG) |
1398                     BIT_ULL(32) | BIT_ULL(24) | BIT_ULL(6) |
1399                     BIT_ULL(2) | BIT_ULL(1));
1400
1401         rvu_npc_setup_interfaces(rvu, blkaddr);
1402
1403         err = npc_mcam_rsrcs_init(rvu, blkaddr);
1404         if (err)
1405                 return err;
1406
1407         /* Configure MKEX profile */
1408         npc_load_mkex_profile(rvu, blkaddr, rvu->mkex_pfl_name);
1409
1410         return 0;
1411 }
1412
1413 void rvu_npc_freemem(struct rvu *rvu)
1414 {
1415         struct npc_pkind *pkind = &rvu->hw->pkind;
1416         struct npc_mcam *mcam = &rvu->hw->mcam;
1417
1418         kfree(pkind->rsrc.bmap);
1419         kfree(mcam->counters.bmap);
1420         mutex_destroy(&mcam->lock);
1421 }
1422
1423 void rvu_npc_get_mcam_entry_alloc_info(struct rvu *rvu, u16 pcifunc,
1424                                        int blkaddr, int *alloc_cnt,
1425                                        int *enable_cnt)
1426 {
1427         struct npc_mcam *mcam = &rvu->hw->mcam;
1428         int entry;
1429
1430         *alloc_cnt = 0;
1431         *enable_cnt = 0;
1432
1433         for (entry = 0; entry < mcam->bmap_entries; entry++) {
1434                 if (mcam->entry2pfvf_map[entry] == pcifunc) {
1435                         (*alloc_cnt)++;
1436                         if (is_mcam_entry_enabled(rvu, mcam, blkaddr, entry))
1437                                 (*enable_cnt)++;
1438                 }
1439         }
1440 }
1441
1442 void rvu_npc_get_mcam_counter_alloc_info(struct rvu *rvu, u16 pcifunc,
1443                                          int blkaddr, int *alloc_cnt,
1444                                          int *enable_cnt)
1445 {
1446         struct npc_mcam *mcam = &rvu->hw->mcam;
1447         int cntr;
1448
1449         *alloc_cnt = 0;
1450         *enable_cnt = 0;
1451
1452         for (cntr = 0; cntr < mcam->counters.max; cntr++) {
1453                 if (mcam->cntr2pfvf_map[cntr] == pcifunc) {
1454                         (*alloc_cnt)++;
1455                         if (mcam->cntr_refcnt[cntr])
1456                                 (*enable_cnt)++;
1457                 }
1458         }
1459 }
1460
1461 static int npc_mcam_verify_entry(struct npc_mcam *mcam,
1462                                  u16 pcifunc, int entry)
1463 {
1464         /* Verify if entry is valid and if it is indeed
1465          * allocated to the requesting PFFUNC.
1466          */
1467         if (entry >= mcam->bmap_entries)
1468                 return NPC_MCAM_INVALID_REQ;
1469
1470         if (pcifunc != mcam->entry2pfvf_map[entry])
1471                 return NPC_MCAM_PERM_DENIED;
1472
1473         return 0;
1474 }
1475
1476 static int npc_mcam_verify_counter(struct npc_mcam *mcam,
1477                                    u16 pcifunc, int cntr)
1478 {
1479         /* Verify if counter is valid and if it is indeed
1480          * allocated to the requesting PFFUNC.
1481          */
1482         if (cntr >= mcam->counters.max)
1483                 return NPC_MCAM_INVALID_REQ;
1484
1485         if (pcifunc != mcam->cntr2pfvf_map[cntr])
1486                 return NPC_MCAM_PERM_DENIED;
1487
1488         return 0;
1489 }
1490
1491 static void npc_map_mcam_entry_and_cntr(struct rvu *rvu, struct npc_mcam *mcam,
1492                                         int blkaddr, u16 entry, u16 cntr)
1493 {
1494         u16 index = entry & (mcam->banksize - 1);
1495         u16 bank = npc_get_bank(mcam, entry);
1496
1497         /* Set mapping and increment counter's refcnt */
1498         mcam->entry2cntr_map[entry] = cntr;
1499         mcam->cntr_refcnt[cntr]++;
1500         /* Enable stats
1501          * NPC_AF_MCAMEX_BANKX_STAT_ACT[14:12] - counter[11:9]
1502          * NPC_AF_MCAMEX_BANKX_STAT_ACT[8:0] - counter[8:0]
1503          */
1504         rvu_write64(rvu, blkaddr,
1505                     NPC_AF_MCAMEX_BANKX_STAT_ACT(index, bank),
1506                     ((cntr >> 9) << 12) | BIT_ULL(9) | cntr);
1507 }
1508
1509 static void npc_unmap_mcam_entry_and_cntr(struct rvu *rvu,
1510                                           struct npc_mcam *mcam,
1511                                           int blkaddr, u16 entry, u16 cntr)
1512 {
1513         u16 index = entry & (mcam->banksize - 1);
1514         u16 bank = npc_get_bank(mcam, entry);
1515
1516         /* Remove mapping and reduce counter's refcnt */
1517         mcam->entry2cntr_map[entry] = NPC_MCAM_INVALID_MAP;
1518         mcam->cntr_refcnt[cntr]--;
1519         /* Disable stats */
1520         rvu_write64(rvu, blkaddr,
1521                     NPC_AF_MCAMEX_BANKX_STAT_ACT(index, bank), 0x00);
1522 }
1523
1524 /* Sets MCAM entry in bitmap as used. Update
1525  * reverse bitmap too. Should be called with
1526  * 'mcam->lock' held.
1527  */
1528 static void npc_mcam_set_bit(struct npc_mcam *mcam, u16 index)
1529 {
1530         u16 entry, rentry;
1531
1532         entry = index;
1533         rentry = mcam->bmap_entries - index - 1;
1534
1535         __set_bit(entry, mcam->bmap);
1536         __set_bit(rentry, mcam->bmap_reverse);
1537         mcam->bmap_fcnt--;
1538 }
1539
1540 /* Sets MCAM entry in bitmap as free. Update
1541  * reverse bitmap too. Should be called with
1542  * 'mcam->lock' held.
1543  */
1544 static void npc_mcam_clear_bit(struct npc_mcam *mcam, u16 index)
1545 {
1546         u16 entry, rentry;
1547
1548         entry = index;
1549         rentry = mcam->bmap_entries - index - 1;
1550
1551         __clear_bit(entry, mcam->bmap);
1552         __clear_bit(rentry, mcam->bmap_reverse);
1553         mcam->bmap_fcnt++;
1554 }
1555
1556 static void npc_mcam_free_all_entries(struct rvu *rvu, struct npc_mcam *mcam,
1557                                       int blkaddr, u16 pcifunc)
1558 {
1559         u16 index, cntr;
1560
1561         /* Scan all MCAM entries and free the ones mapped to 'pcifunc' */
1562         for (index = 0; index < mcam->bmap_entries; index++) {
1563                 if (mcam->entry2pfvf_map[index] == pcifunc) {
1564                         mcam->entry2pfvf_map[index] = NPC_MCAM_INVALID_MAP;
1565                         /* Free the entry in bitmap */
1566                         npc_mcam_clear_bit(mcam, index);
1567                         /* Disable the entry */
1568                         npc_enable_mcam_entry(rvu, mcam, blkaddr, index, false);
1569
1570                         /* Update entry2counter mapping */
1571                         cntr = mcam->entry2cntr_map[index];
1572                         if (cntr != NPC_MCAM_INVALID_MAP)
1573                                 npc_unmap_mcam_entry_and_cntr(rvu, mcam,
1574                                                               blkaddr, index,
1575                                                               cntr);
1576                 }
1577         }
1578 }
1579
1580 static void npc_mcam_free_all_counters(struct rvu *rvu, struct npc_mcam *mcam,
1581                                        u16 pcifunc)
1582 {
1583         u16 cntr;
1584
1585         /* Scan all MCAM counters and free the ones mapped to 'pcifunc' */
1586         for (cntr = 0; cntr < mcam->counters.max; cntr++) {
1587                 if (mcam->cntr2pfvf_map[cntr] == pcifunc) {
1588                         mcam->cntr2pfvf_map[cntr] = NPC_MCAM_INVALID_MAP;
1589                         mcam->cntr_refcnt[cntr] = 0;
1590                         rvu_free_rsrc(&mcam->counters, cntr);
1591                         /* This API is expected to be called after freeing
1592                          * MCAM entries, which inturn will remove
1593                          * 'entry to counter' mapping.
1594                          * No need to do it again.
1595                          */
1596                 }
1597         }
1598 }
1599
1600 /* Find area of contiguous free entries of size 'nr'.
1601  * If not found return max contiguous free entries available.
1602  */
1603 static u16 npc_mcam_find_zero_area(unsigned long *map, u16 size, u16 start,
1604                                    u16 nr, u16 *max_area)
1605 {
1606         u16 max_area_start = 0;
1607         u16 index, next, end;
1608
1609         *max_area = 0;
1610
1611 again:
1612         index = find_next_zero_bit(map, size, start);
1613         if (index >= size)
1614                 return max_area_start;
1615
1616         end = ((index + nr) >= size) ? size : index + nr;
1617         next = find_next_bit(map, end, index);
1618         if (*max_area < (next - index)) {
1619                 *max_area = next - index;
1620                 max_area_start = index;
1621         }
1622
1623         if (next < end) {
1624                 start = next + 1;
1625                 goto again;
1626         }
1627
1628         return max_area_start;
1629 }
1630
1631 /* Find number of free MCAM entries available
1632  * within range i.e in between 'start' and 'end'.
1633  */
1634 static u16 npc_mcam_get_free_count(unsigned long *map, u16 start, u16 end)
1635 {
1636         u16 index, next;
1637         u16 fcnt = 0;
1638
1639 again:
1640         if (start >= end)
1641                 return fcnt;
1642
1643         index = find_next_zero_bit(map, end, start);
1644         if (index >= end)
1645                 return fcnt;
1646
1647         next = find_next_bit(map, end, index);
1648         if (next <= end) {
1649                 fcnt += next - index;
1650                 start = next + 1;
1651                 goto again;
1652         }
1653
1654         fcnt += end - index;
1655         return fcnt;
1656 }
1657
1658 static void
1659 npc_get_mcam_search_range_priority(struct npc_mcam *mcam,
1660                                    struct npc_mcam_alloc_entry_req *req,
1661                                    u16 *start, u16 *end, bool *reverse)
1662 {
1663         u16 fcnt;
1664
1665         if (req->priority == NPC_MCAM_HIGHER_PRIO)
1666                 goto hprio;
1667
1668         /* For a low priority entry allocation
1669          * - If reference entry is not in hprio zone then
1670          *      search range: ref_entry to end.
1671          * - If reference entry is in hprio zone and if
1672          *   request can be accomodated in non-hprio zone then
1673          *      search range: 'start of middle zone' to 'end'
1674          * - else search in reverse, so that less number of hprio
1675          *   zone entries are allocated.
1676          */
1677
1678         *reverse = false;
1679         *start = req->ref_entry + 1;
1680         *end = mcam->bmap_entries;
1681
1682         if (req->ref_entry >= mcam->hprio_end)
1683                 return;
1684
1685         fcnt = npc_mcam_get_free_count(mcam->bmap,
1686                                        mcam->hprio_end, mcam->bmap_entries);
1687         if (fcnt > req->count)
1688                 *start = mcam->hprio_end;
1689         else
1690                 *reverse = true;
1691         return;
1692
1693 hprio:
1694         /* For a high priority entry allocation, search is always
1695          * in reverse to preserve hprio zone entries.
1696          * - If reference entry is not in lprio zone then
1697          *      search range: 0 to ref_entry.
1698          * - If reference entry is in lprio zone and if
1699          *   request can be accomodated in middle zone then
1700          *      search range: 'hprio_end' to 'lprio_start'
1701          */
1702
1703         *reverse = true;
1704         *start = 0;
1705         *end = req->ref_entry;
1706
1707         if (req->ref_entry <= mcam->lprio_start)
1708                 return;
1709
1710         fcnt = npc_mcam_get_free_count(mcam->bmap,
1711                                        mcam->hprio_end, mcam->lprio_start);
1712         if (fcnt < req->count)
1713                 return;
1714         *start = mcam->hprio_end;
1715         *end = mcam->lprio_start;
1716 }
1717
1718 static int npc_mcam_alloc_entries(struct npc_mcam *mcam, u16 pcifunc,
1719                                   struct npc_mcam_alloc_entry_req *req,
1720                                   struct npc_mcam_alloc_entry_rsp *rsp)
1721 {
1722         u16 entry_list[NPC_MAX_NONCONTIG_ENTRIES];
1723         u16 fcnt, hp_fcnt, lp_fcnt;
1724         u16 start, end, index;
1725         int entry, next_start;
1726         bool reverse = false;
1727         unsigned long *bmap;
1728         u16 max_contig;
1729
1730         mutex_lock(&mcam->lock);
1731
1732         /* Check if there are any free entries */
1733         if (!mcam->bmap_fcnt) {
1734                 mutex_unlock(&mcam->lock);
1735                 return NPC_MCAM_ALLOC_FAILED;
1736         }
1737
1738         /* MCAM entries are divided into high priority, middle and
1739          * low priority zones. Idea is to not allocate top and lower
1740          * most entries as much as possible, this is to increase
1741          * probability of honouring priority allocation requests.
1742          *
1743          * Two bitmaps are used for mcam entry management,
1744          * mcam->bmap for forward search i.e '0 to mcam->bmap_entries'.
1745          * mcam->bmap_reverse for reverse search i.e 'mcam->bmap_entries to 0'.
1746          *
1747          * Reverse bitmap is used to allocate entries
1748          * - when a higher priority entry is requested
1749          * - when available free entries are less.
1750          * Lower priority ones out of avaialble free entries are always
1751          * chosen when 'high vs low' question arises.
1752          */
1753
1754         /* Get the search range for priority allocation request */
1755         if (req->priority) {
1756                 npc_get_mcam_search_range_priority(mcam, req,
1757                                                    &start, &end, &reverse);
1758                 goto alloc;
1759         }
1760
1761         /* Find out the search range for non-priority allocation request
1762          *
1763          * Get MCAM free entry count in middle zone.
1764          */
1765         lp_fcnt = npc_mcam_get_free_count(mcam->bmap,
1766                                           mcam->lprio_start,
1767                                           mcam->bmap_entries);
1768         hp_fcnt = npc_mcam_get_free_count(mcam->bmap, 0, mcam->hprio_end);
1769         fcnt = mcam->bmap_fcnt - lp_fcnt - hp_fcnt;
1770
1771         /* Check if request can be accomodated in the middle zone */
1772         if (fcnt > req->count) {
1773                 start = mcam->hprio_end;
1774                 end = mcam->lprio_start;
1775         } else if ((fcnt + (hp_fcnt / 2) + (lp_fcnt / 2)) > req->count) {
1776                 /* Expand search zone from half of hprio zone to
1777                  * half of lprio zone.
1778                  */
1779                 start = mcam->hprio_end / 2;
1780                 end = mcam->bmap_entries - (mcam->lprio_count / 2);
1781                 reverse = true;
1782         } else {
1783                 /* Not enough free entries, search all entries in reverse,
1784                  * so that low priority ones will get used up.
1785                  */
1786                 reverse = true;
1787                 start = 0;
1788                 end = mcam->bmap_entries;
1789         }
1790
1791 alloc:
1792         if (reverse) {
1793                 bmap = mcam->bmap_reverse;
1794                 start = mcam->bmap_entries - start;
1795                 end = mcam->bmap_entries - end;
1796                 index = start;
1797                 start = end;
1798                 end = index;
1799         } else {
1800                 bmap = mcam->bmap;
1801         }
1802
1803         if (req->contig) {
1804                 /* Allocate requested number of contiguous entries, if
1805                  * unsuccessful find max contiguous entries available.
1806                  */
1807                 index = npc_mcam_find_zero_area(bmap, end, start,
1808                                                 req->count, &max_contig);
1809                 rsp->count = max_contig;
1810                 if (reverse)
1811                         rsp->entry = mcam->bmap_entries - index - max_contig;
1812                 else
1813                         rsp->entry = index;
1814         } else {
1815                 /* Allocate requested number of non-contiguous entries,
1816                  * if unsuccessful allocate as many as possible.
1817                  */
1818                 rsp->count = 0;
1819                 next_start = start;
1820                 for (entry = 0; entry < req->count; entry++) {
1821                         index = find_next_zero_bit(bmap, end, next_start);
1822                         if (index >= end)
1823                                 break;
1824
1825                         next_start = start + (index - start) + 1;
1826
1827                         /* Save the entry's index */
1828                         if (reverse)
1829                                 index = mcam->bmap_entries - index - 1;
1830                         entry_list[entry] = index;
1831                         rsp->count++;
1832                 }
1833         }
1834
1835         /* If allocating requested no of entries is unsucessful,
1836          * expand the search range to full bitmap length and retry.
1837          */
1838         if (!req->priority && (rsp->count < req->count) &&
1839             ((end - start) != mcam->bmap_entries)) {
1840                 reverse = true;
1841                 start = 0;
1842                 end = mcam->bmap_entries;
1843                 goto alloc;
1844         }
1845
1846         /* For priority entry allocation requests, if allocation is
1847          * failed then expand search to max possible range and retry.
1848          */
1849         if (req->priority && rsp->count < req->count) {
1850                 if (req->priority == NPC_MCAM_LOWER_PRIO &&
1851                     (start != (req->ref_entry + 1))) {
1852                         start = req->ref_entry + 1;
1853                         end = mcam->bmap_entries;
1854                         reverse = false;
1855                         goto alloc;
1856                 } else if ((req->priority == NPC_MCAM_HIGHER_PRIO) &&
1857                            ((end - start) != req->ref_entry)) {
1858                         start = 0;
1859                         end = req->ref_entry;
1860                         reverse = true;
1861                         goto alloc;
1862                 }
1863         }
1864
1865         /* Copy MCAM entry indices into mbox response entry_list.
1866          * Requester always expects indices in ascending order, so
1867          * so reverse the list if reverse bitmap is used for allocation.
1868          */
1869         if (!req->contig && rsp->count) {
1870                 index = 0;
1871                 for (entry = rsp->count - 1; entry >= 0; entry--) {
1872                         if (reverse)
1873                                 rsp->entry_list[index++] = entry_list[entry];
1874                         else
1875                                 rsp->entry_list[entry] = entry_list[entry];
1876                 }
1877         }
1878
1879         /* Mark the allocated entries as used and set nixlf mapping */
1880         for (entry = 0; entry < rsp->count; entry++) {
1881                 index = req->contig ?
1882                         (rsp->entry + entry) : rsp->entry_list[entry];
1883                 npc_mcam_set_bit(mcam, index);
1884                 mcam->entry2pfvf_map[index] = pcifunc;
1885                 mcam->entry2cntr_map[index] = NPC_MCAM_INVALID_MAP;
1886         }
1887
1888         /* Update available free count in mbox response */
1889         rsp->free_count = mcam->bmap_fcnt;
1890
1891         mutex_unlock(&mcam->lock);
1892         return 0;
1893 }
1894
1895 int rvu_mbox_handler_npc_mcam_alloc_entry(struct rvu *rvu,
1896                                           struct npc_mcam_alloc_entry_req *req,
1897                                           struct npc_mcam_alloc_entry_rsp *rsp)
1898 {
1899         struct npc_mcam *mcam = &rvu->hw->mcam;
1900         u16 pcifunc = req->hdr.pcifunc;
1901         int blkaddr;
1902
1903         blkaddr = rvu_get_blkaddr(rvu, BLKTYPE_NPC, 0);
1904         if (blkaddr < 0)
1905                 return NPC_MCAM_INVALID_REQ;
1906
1907         rsp->entry = NPC_MCAM_ENTRY_INVALID;
1908         rsp->free_count = 0;
1909
1910         /* Check if ref_entry is within range */
1911         if (req->priority && req->ref_entry >= mcam->bmap_entries)
1912                 return NPC_MCAM_INVALID_REQ;
1913
1914         /* ref_entry can't be '0' if requested priority is high.
1915          * Can't be last entry if requested priority is low.
1916          */
1917         if ((!req->ref_entry && req->priority == NPC_MCAM_HIGHER_PRIO) ||
1918             ((req->ref_entry == (mcam->bmap_entries - 1)) &&
1919              req->priority == NPC_MCAM_LOWER_PRIO))
1920                 return NPC_MCAM_INVALID_REQ;
1921
1922         /* Since list of allocated indices needs to be sent to requester,
1923          * max number of non-contiguous entries per mbox msg is limited.
1924          */
1925         if (!req->contig && req->count > NPC_MAX_NONCONTIG_ENTRIES)
1926                 return NPC_MCAM_INVALID_REQ;
1927
1928         /* Alloc request from PFFUNC with no NIXLF attached should be denied */
1929         if (!is_nixlf_attached(rvu, pcifunc))
1930                 return NPC_MCAM_ALLOC_DENIED;
1931
1932         return npc_mcam_alloc_entries(mcam, pcifunc, req, rsp);
1933 }
1934
1935 int rvu_mbox_handler_npc_mcam_free_entry(struct rvu *rvu,
1936                                          struct npc_mcam_free_entry_req *req,
1937                                          struct msg_rsp *rsp)
1938 {
1939         struct npc_mcam *mcam = &rvu->hw->mcam;
1940         u16 pcifunc = req->hdr.pcifunc;
1941         int blkaddr, rc = 0;
1942         u16 cntr;
1943
1944         blkaddr = rvu_get_blkaddr(rvu, BLKTYPE_NPC, 0);
1945         if (blkaddr < 0)
1946                 return NPC_MCAM_INVALID_REQ;
1947
1948         /* Free request from PFFUNC with no NIXLF attached, ignore */
1949         if (!is_nixlf_attached(rvu, pcifunc))
1950                 return NPC_MCAM_INVALID_REQ;
1951
1952         mutex_lock(&mcam->lock);
1953
1954         if (req->all)
1955                 goto free_all;
1956
1957         rc = npc_mcam_verify_entry(mcam, pcifunc, req->entry);
1958         if (rc)
1959                 goto exit;
1960
1961         mcam->entry2pfvf_map[req->entry] = 0;
1962         npc_mcam_clear_bit(mcam, req->entry);
1963         npc_enable_mcam_entry(rvu, mcam, blkaddr, req->entry, false);
1964
1965         /* Update entry2counter mapping */
1966         cntr = mcam->entry2cntr_map[req->entry];
1967         if (cntr != NPC_MCAM_INVALID_MAP)
1968                 npc_unmap_mcam_entry_and_cntr(rvu, mcam, blkaddr,
1969                                               req->entry, cntr);
1970
1971         goto exit;
1972
1973 free_all:
1974         /* Free up all entries allocated to requesting PFFUNC */
1975         npc_mcam_free_all_entries(rvu, mcam, blkaddr, pcifunc);
1976 exit:
1977         mutex_unlock(&mcam->lock);
1978         return rc;
1979 }
1980
1981 int rvu_mbox_handler_npc_mcam_write_entry(struct rvu *rvu,
1982                                           struct npc_mcam_write_entry_req *req,
1983                                           struct msg_rsp *rsp)
1984 {
1985         struct rvu_pfvf *pfvf = rvu_get_pfvf(rvu, req->hdr.pcifunc);
1986         struct npc_mcam *mcam = &rvu->hw->mcam;
1987         u16 pcifunc = req->hdr.pcifunc;
1988         u16 channel, chan_mask;
1989         int blkaddr, rc;
1990         u8 nix_intf;
1991
1992         blkaddr = rvu_get_blkaddr(rvu, BLKTYPE_NPC, 0);
1993         if (blkaddr < 0)
1994                 return NPC_MCAM_INVALID_REQ;
1995
1996         chan_mask = req->entry_data.kw_mask[0] & NPC_KEX_CHAN_MASK;
1997         channel = req->entry_data.kw[0] & NPC_KEX_CHAN_MASK;
1998         channel &= chan_mask;
1999
2000         mutex_lock(&mcam->lock);
2001         rc = npc_mcam_verify_entry(mcam, pcifunc, req->entry);
2002         if (rc)
2003                 goto exit;
2004
2005         if (req->set_cntr &&
2006             npc_mcam_verify_counter(mcam, pcifunc, req->cntr)) {
2007                 rc = NPC_MCAM_INVALID_REQ;
2008                 goto exit;
2009         }
2010
2011         if (!is_npc_interface_valid(rvu, req->intf)) {
2012                 rc = NPC_MCAM_INVALID_REQ;
2013                 goto exit;
2014         }
2015
2016         if (is_npc_intf_tx(req->intf))
2017                 nix_intf = pfvf->nix_tx_intf;
2018         else
2019                 nix_intf = pfvf->nix_rx_intf;
2020
2021         if (npc_mcam_verify_channel(rvu, pcifunc, req->intf, channel)) {
2022                 rc = NPC_MCAM_INVALID_REQ;
2023                 goto exit;
2024         }
2025
2026         if (npc_mcam_verify_pf_func(rvu, &req->entry_data, req->intf,
2027                                     pcifunc)) {
2028                 rc = NPC_MCAM_INVALID_REQ;
2029                 goto exit;
2030         }
2031
2032         npc_config_mcam_entry(rvu, mcam, blkaddr, req->entry, nix_intf,
2033                               &req->entry_data, req->enable_entry);
2034
2035         if (req->set_cntr)
2036                 npc_map_mcam_entry_and_cntr(rvu, mcam, blkaddr,
2037                                             req->entry, req->cntr);
2038
2039         rc = 0;
2040 exit:
2041         mutex_unlock(&mcam->lock);
2042         return rc;
2043 }
2044
2045 int rvu_mbox_handler_npc_mcam_ena_entry(struct rvu *rvu,
2046                                         struct npc_mcam_ena_dis_entry_req *req,
2047                                         struct msg_rsp *rsp)
2048 {
2049         struct npc_mcam *mcam = &rvu->hw->mcam;
2050         u16 pcifunc = req->hdr.pcifunc;
2051         int blkaddr, rc;
2052
2053         blkaddr = rvu_get_blkaddr(rvu, BLKTYPE_NPC, 0);
2054         if (blkaddr < 0)
2055                 return NPC_MCAM_INVALID_REQ;
2056
2057         mutex_lock(&mcam->lock);
2058         rc = npc_mcam_verify_entry(mcam, pcifunc, req->entry);
2059         mutex_unlock(&mcam->lock);
2060         if (rc)
2061                 return rc;
2062
2063         npc_enable_mcam_entry(rvu, mcam, blkaddr, req->entry, true);
2064
2065         return 0;
2066 }
2067
2068 int rvu_mbox_handler_npc_mcam_dis_entry(struct rvu *rvu,
2069                                         struct npc_mcam_ena_dis_entry_req *req,
2070                                         struct msg_rsp *rsp)
2071 {
2072         struct npc_mcam *mcam = &rvu->hw->mcam;
2073         u16 pcifunc = req->hdr.pcifunc;
2074         int blkaddr, rc;
2075
2076         blkaddr = rvu_get_blkaddr(rvu, BLKTYPE_NPC, 0);
2077         if (blkaddr < 0)
2078                 return NPC_MCAM_INVALID_REQ;
2079
2080         mutex_lock(&mcam->lock);
2081         rc = npc_mcam_verify_entry(mcam, pcifunc, req->entry);
2082         mutex_unlock(&mcam->lock);
2083         if (rc)
2084                 return rc;
2085
2086         npc_enable_mcam_entry(rvu, mcam, blkaddr, req->entry, false);
2087
2088         return 0;
2089 }
2090
2091 int rvu_mbox_handler_npc_mcam_shift_entry(struct rvu *rvu,
2092                                           struct npc_mcam_shift_entry_req *req,
2093                                           struct npc_mcam_shift_entry_rsp *rsp)
2094 {
2095         struct npc_mcam *mcam = &rvu->hw->mcam;
2096         u16 pcifunc = req->hdr.pcifunc;
2097         u16 old_entry, new_entry;
2098         u16 index, cntr;
2099         int blkaddr, rc;
2100
2101         blkaddr = rvu_get_blkaddr(rvu, BLKTYPE_NPC, 0);
2102         if (blkaddr < 0)
2103                 return NPC_MCAM_INVALID_REQ;
2104
2105         if (req->shift_count > NPC_MCAM_MAX_SHIFTS)
2106                 return NPC_MCAM_INVALID_REQ;
2107
2108         mutex_lock(&mcam->lock);
2109         for (index = 0; index < req->shift_count; index++) {
2110                 old_entry = req->curr_entry[index];
2111                 new_entry = req->new_entry[index];
2112
2113                 /* Check if both old and new entries are valid and
2114                  * does belong to this PFFUNC or not.
2115                  */
2116                 rc = npc_mcam_verify_entry(mcam, pcifunc, old_entry);
2117                 if (rc)
2118                         break;
2119
2120                 rc = npc_mcam_verify_entry(mcam, pcifunc, new_entry);
2121                 if (rc)
2122                         break;
2123
2124                 /* new_entry should not have a counter mapped */
2125                 if (mcam->entry2cntr_map[new_entry] != NPC_MCAM_INVALID_MAP) {
2126                         rc = NPC_MCAM_PERM_DENIED;
2127                         break;
2128                 }
2129
2130                 /* Disable the new_entry */
2131                 npc_enable_mcam_entry(rvu, mcam, blkaddr, new_entry, false);
2132
2133                 /* Copy rule from old entry to new entry */
2134                 npc_copy_mcam_entry(rvu, mcam, blkaddr, old_entry, new_entry);
2135
2136                 /* Copy counter mapping, if any */
2137                 cntr = mcam->entry2cntr_map[old_entry];
2138                 if (cntr != NPC_MCAM_INVALID_MAP) {
2139                         npc_unmap_mcam_entry_and_cntr(rvu, mcam, blkaddr,
2140                                                       old_entry, cntr);
2141                         npc_map_mcam_entry_and_cntr(rvu, mcam, blkaddr,
2142                                                     new_entry, cntr);
2143                 }
2144
2145                 /* Enable new_entry and disable old_entry */
2146                 npc_enable_mcam_entry(rvu, mcam, blkaddr, new_entry, true);
2147                 npc_enable_mcam_entry(rvu, mcam, blkaddr, old_entry, false);
2148         }
2149
2150         /* If shift has failed then report the failed index */
2151         if (index != req->shift_count) {
2152                 rc = NPC_MCAM_PERM_DENIED;
2153                 rsp->failed_entry_idx = index;
2154         }
2155
2156         mutex_unlock(&mcam->lock);
2157         return rc;
2158 }
2159
2160 int rvu_mbox_handler_npc_mcam_alloc_counter(struct rvu *rvu,
2161                         struct npc_mcam_alloc_counter_req *req,
2162                         struct npc_mcam_alloc_counter_rsp *rsp)
2163 {
2164         struct npc_mcam *mcam = &rvu->hw->mcam;
2165         u16 pcifunc = req->hdr.pcifunc;
2166         u16 max_contig, cntr;
2167         int blkaddr, index;
2168
2169         blkaddr = rvu_get_blkaddr(rvu, BLKTYPE_NPC, 0);
2170         if (blkaddr < 0)
2171                 return NPC_MCAM_INVALID_REQ;
2172
2173         /* If the request is from a PFFUNC with no NIXLF attached, ignore */
2174         if (!is_nixlf_attached(rvu, pcifunc))
2175                 return NPC_MCAM_INVALID_REQ;
2176
2177         /* Since list of allocated counter IDs needs to be sent to requester,
2178          * max number of non-contiguous counters per mbox msg is limited.
2179          */
2180         if (!req->contig && req->count > NPC_MAX_NONCONTIG_COUNTERS)
2181                 return NPC_MCAM_INVALID_REQ;
2182
2183         mutex_lock(&mcam->lock);
2184
2185         /* Check if unused counters are available or not */
2186         if (!rvu_rsrc_free_count(&mcam->counters)) {
2187                 mutex_unlock(&mcam->lock);
2188                 return NPC_MCAM_ALLOC_FAILED;
2189         }
2190
2191         rsp->count = 0;
2192
2193         if (req->contig) {
2194                 /* Allocate requested number of contiguous counters, if
2195                  * unsuccessful find max contiguous entries available.
2196                  */
2197                 index = npc_mcam_find_zero_area(mcam->counters.bmap,
2198                                                 mcam->counters.max, 0,
2199                                                 req->count, &max_contig);
2200                 rsp->count = max_contig;
2201                 rsp->cntr = index;
2202                 for (cntr = index; cntr < (index + max_contig); cntr++) {
2203                         __set_bit(cntr, mcam->counters.bmap);
2204                         mcam->cntr2pfvf_map[cntr] = pcifunc;
2205                 }
2206         } else {
2207                 /* Allocate requested number of non-contiguous counters,
2208                  * if unsuccessful allocate as many as possible.
2209                  */
2210                 for (cntr = 0; cntr < req->count; cntr++) {
2211                         index = rvu_alloc_rsrc(&mcam->counters);
2212                         if (index < 0)
2213                                 break;
2214                         rsp->cntr_list[cntr] = index;
2215                         rsp->count++;
2216                         mcam->cntr2pfvf_map[index] = pcifunc;
2217                 }
2218         }
2219
2220         mutex_unlock(&mcam->lock);
2221         return 0;
2222 }
2223
2224 int rvu_mbox_handler_npc_mcam_free_counter(struct rvu *rvu,
2225                 struct npc_mcam_oper_counter_req *req, struct msg_rsp *rsp)
2226 {
2227         struct npc_mcam *mcam = &rvu->hw->mcam;
2228         u16 index, entry = 0;
2229         int blkaddr, err;
2230
2231         blkaddr = rvu_get_blkaddr(rvu, BLKTYPE_NPC, 0);
2232         if (blkaddr < 0)
2233                 return NPC_MCAM_INVALID_REQ;
2234
2235         mutex_lock(&mcam->lock);
2236         err = npc_mcam_verify_counter(mcam, req->hdr.pcifunc, req->cntr);
2237         if (err) {
2238                 mutex_unlock(&mcam->lock);
2239                 return err;
2240         }
2241
2242         /* Mark counter as free/unused */
2243         mcam->cntr2pfvf_map[req->cntr] = NPC_MCAM_INVALID_MAP;
2244         rvu_free_rsrc(&mcam->counters, req->cntr);
2245
2246         /* Disable all MCAM entry's stats which are using this counter */
2247         while (entry < mcam->bmap_entries) {
2248                 if (!mcam->cntr_refcnt[req->cntr])
2249                         break;
2250
2251                 index = find_next_bit(mcam->bmap, mcam->bmap_entries, entry);
2252                 if (index >= mcam->bmap_entries)
2253                         break;
2254                 if (mcam->entry2cntr_map[index] != req->cntr)
2255                         continue;
2256
2257                 entry = index + 1;
2258                 npc_unmap_mcam_entry_and_cntr(rvu, mcam, blkaddr,
2259                                               index, req->cntr);
2260         }
2261
2262         mutex_unlock(&mcam->lock);
2263         return 0;
2264 }
2265
2266 int rvu_mbox_handler_npc_mcam_unmap_counter(struct rvu *rvu,
2267                 struct npc_mcam_unmap_counter_req *req, struct msg_rsp *rsp)
2268 {
2269         struct npc_mcam *mcam = &rvu->hw->mcam;
2270         u16 index, entry = 0;
2271         int blkaddr, rc;
2272
2273         blkaddr = rvu_get_blkaddr(rvu, BLKTYPE_NPC, 0);
2274         if (blkaddr < 0)
2275                 return NPC_MCAM_INVALID_REQ;
2276
2277         mutex_lock(&mcam->lock);
2278         rc = npc_mcam_verify_counter(mcam, req->hdr.pcifunc, req->cntr);
2279         if (rc)
2280                 goto exit;
2281
2282         /* Unmap the MCAM entry and counter */
2283         if (!req->all) {
2284                 rc = npc_mcam_verify_entry(mcam, req->hdr.pcifunc, req->entry);
2285                 if (rc)
2286                         goto exit;
2287                 npc_unmap_mcam_entry_and_cntr(rvu, mcam, blkaddr,
2288                                               req->entry, req->cntr);
2289                 goto exit;
2290         }
2291
2292         /* Disable all MCAM entry's stats which are using this counter */
2293         while (entry < mcam->bmap_entries) {
2294                 if (!mcam->cntr_refcnt[req->cntr])
2295                         break;
2296
2297                 index = find_next_bit(mcam->bmap, mcam->bmap_entries, entry);
2298                 if (index >= mcam->bmap_entries)
2299                         break;
2300                 if (mcam->entry2cntr_map[index] != req->cntr)
2301                         continue;
2302
2303                 entry = index + 1;
2304                 npc_unmap_mcam_entry_and_cntr(rvu, mcam, blkaddr,
2305                                               index, req->cntr);
2306         }
2307 exit:
2308         mutex_unlock(&mcam->lock);
2309         return rc;
2310 }
2311
2312 int rvu_mbox_handler_npc_mcam_clear_counter(struct rvu *rvu,
2313                 struct npc_mcam_oper_counter_req *req, struct msg_rsp *rsp)
2314 {
2315         struct npc_mcam *mcam = &rvu->hw->mcam;
2316         int blkaddr, err;
2317
2318         blkaddr = rvu_get_blkaddr(rvu, BLKTYPE_NPC, 0);
2319         if (blkaddr < 0)
2320                 return NPC_MCAM_INVALID_REQ;
2321
2322         mutex_lock(&mcam->lock);
2323         err = npc_mcam_verify_counter(mcam, req->hdr.pcifunc, req->cntr);
2324         mutex_unlock(&mcam->lock);
2325         if (err)
2326                 return err;
2327
2328         rvu_write64(rvu, blkaddr, NPC_AF_MATCH_STATX(req->cntr), 0x00);
2329
2330         return 0;
2331 }
2332
2333 int rvu_mbox_handler_npc_mcam_counter_stats(struct rvu *rvu,
2334                         struct npc_mcam_oper_counter_req *req,
2335                         struct npc_mcam_oper_counter_rsp *rsp)
2336 {
2337         struct npc_mcam *mcam = &rvu->hw->mcam;
2338         int blkaddr, err;
2339
2340         blkaddr = rvu_get_blkaddr(rvu, BLKTYPE_NPC, 0);
2341         if (blkaddr < 0)
2342                 return NPC_MCAM_INVALID_REQ;
2343
2344         mutex_lock(&mcam->lock);
2345         err = npc_mcam_verify_counter(mcam, req->hdr.pcifunc, req->cntr);
2346         mutex_unlock(&mcam->lock);
2347         if (err)
2348                 return err;
2349
2350         rsp->stat = rvu_read64(rvu, blkaddr, NPC_AF_MATCH_STATX(req->cntr));
2351         rsp->stat &= BIT_ULL(48) - 1;
2352
2353         return 0;
2354 }
2355
2356 int rvu_mbox_handler_npc_mcam_alloc_and_write_entry(struct rvu *rvu,
2357                           struct npc_mcam_alloc_and_write_entry_req *req,
2358                           struct npc_mcam_alloc_and_write_entry_rsp *rsp)
2359 {
2360         struct rvu_pfvf *pfvf = rvu_get_pfvf(rvu, req->hdr.pcifunc);
2361         struct npc_mcam_alloc_counter_req cntr_req;
2362         struct npc_mcam_alloc_counter_rsp cntr_rsp;
2363         struct npc_mcam_alloc_entry_req entry_req;
2364         struct npc_mcam_alloc_entry_rsp entry_rsp;
2365         struct npc_mcam *mcam = &rvu->hw->mcam;
2366         u16 entry = NPC_MCAM_ENTRY_INVALID;
2367         u16 cntr = NPC_MCAM_ENTRY_INVALID;
2368         u16 channel, chan_mask;
2369         int blkaddr, rc;
2370         u8 nix_intf;
2371
2372         blkaddr = rvu_get_blkaddr(rvu, BLKTYPE_NPC, 0);
2373         if (blkaddr < 0)
2374                 return NPC_MCAM_INVALID_REQ;
2375
2376         if (!is_npc_interface_valid(rvu, req->intf))
2377                 return NPC_MCAM_INVALID_REQ;
2378
2379         chan_mask = req->entry_data.kw_mask[0] & NPC_KEX_CHAN_MASK;
2380         channel = req->entry_data.kw[0] & NPC_KEX_CHAN_MASK;
2381         channel &= chan_mask;
2382
2383         if (npc_mcam_verify_channel(rvu, req->hdr.pcifunc, req->intf, channel))
2384                 return NPC_MCAM_INVALID_REQ;
2385
2386         if (npc_mcam_verify_pf_func(rvu, &req->entry_data, req->intf,
2387                                     req->hdr.pcifunc))
2388                 return NPC_MCAM_INVALID_REQ;
2389
2390         /* Try to allocate a MCAM entry */
2391         entry_req.hdr.pcifunc = req->hdr.pcifunc;
2392         entry_req.contig = true;
2393         entry_req.priority = req->priority;
2394         entry_req.ref_entry = req->ref_entry;
2395         entry_req.count = 1;
2396
2397         rc = rvu_mbox_handler_npc_mcam_alloc_entry(rvu,
2398                                                    &entry_req, &entry_rsp);
2399         if (rc)
2400                 return rc;
2401
2402         if (!entry_rsp.count)
2403                 return NPC_MCAM_ALLOC_FAILED;
2404
2405         entry = entry_rsp.entry;
2406
2407         if (!req->alloc_cntr)
2408                 goto write_entry;
2409
2410         /* Now allocate counter */
2411         cntr_req.hdr.pcifunc = req->hdr.pcifunc;
2412         cntr_req.contig = true;
2413         cntr_req.count = 1;
2414
2415         rc = rvu_mbox_handler_npc_mcam_alloc_counter(rvu, &cntr_req, &cntr_rsp);
2416         if (rc) {
2417                 /* Free allocated MCAM entry */
2418                 mutex_lock(&mcam->lock);
2419                 mcam->entry2pfvf_map[entry] = 0;
2420                 npc_mcam_clear_bit(mcam, entry);
2421                 mutex_unlock(&mcam->lock);
2422                 return rc;
2423         }
2424
2425         cntr = cntr_rsp.cntr;
2426
2427 write_entry:
2428         mutex_lock(&mcam->lock);
2429
2430         if (is_npc_intf_tx(req->intf))
2431                 nix_intf = pfvf->nix_tx_intf;
2432         else
2433                 nix_intf = pfvf->nix_rx_intf;
2434
2435         npc_config_mcam_entry(rvu, mcam, blkaddr, entry, nix_intf,
2436                               &req->entry_data, req->enable_entry);
2437
2438         if (req->alloc_cntr)
2439                 npc_map_mcam_entry_and_cntr(rvu, mcam, blkaddr, entry, cntr);
2440         mutex_unlock(&mcam->lock);
2441
2442         rsp->entry = entry;
2443         rsp->cntr = cntr;
2444
2445         return 0;
2446 }
2447
2448 #define GET_KEX_CFG(intf) \
2449         rvu_read64(rvu, BLKADDR_NPC, NPC_AF_INTFX_KEX_CFG(intf))
2450
2451 #define GET_KEX_FLAGS(ld) \
2452         rvu_read64(rvu, BLKADDR_NPC, NPC_AF_KEX_LDATAX_FLAGS_CFG(ld))
2453
2454 #define GET_KEX_LD(intf, lid, lt, ld)   \
2455         rvu_read64(rvu, BLKADDR_NPC,    \
2456                 NPC_AF_INTFX_LIDX_LTX_LDX_CFG(intf, lid, lt, ld))
2457
2458 #define GET_KEX_LDFLAGS(intf, ld, fl)   \
2459         rvu_read64(rvu, BLKADDR_NPC,    \
2460                 NPC_AF_INTFX_LDATAX_FLAGSX_CFG(intf, ld, fl))
2461
2462 int rvu_mbox_handler_npc_get_kex_cfg(struct rvu *rvu, struct msg_req *req,
2463                                      struct npc_get_kex_cfg_rsp *rsp)
2464 {
2465         int lid, lt, ld, fl;
2466
2467         rsp->rx_keyx_cfg = GET_KEX_CFG(NIX_INTF_RX);
2468         rsp->tx_keyx_cfg = GET_KEX_CFG(NIX_INTF_TX);
2469         for (lid = 0; lid < NPC_MAX_LID; lid++) {
2470                 for (lt = 0; lt < NPC_MAX_LT; lt++) {
2471                         for (ld = 0; ld < NPC_MAX_LD; ld++) {
2472                                 rsp->intf_lid_lt_ld[NIX_INTF_RX][lid][lt][ld] =
2473                                         GET_KEX_LD(NIX_INTF_RX, lid, lt, ld);
2474                                 rsp->intf_lid_lt_ld[NIX_INTF_TX][lid][lt][ld] =
2475                                         GET_KEX_LD(NIX_INTF_TX, lid, lt, ld);
2476                         }
2477                 }
2478         }
2479         for (ld = 0; ld < NPC_MAX_LD; ld++)
2480                 rsp->kex_ld_flags[ld] = GET_KEX_FLAGS(ld);
2481
2482         for (ld = 0; ld < NPC_MAX_LD; ld++) {
2483                 for (fl = 0; fl < NPC_MAX_LFL; fl++) {
2484                         rsp->intf_ld_flags[NIX_INTF_RX][ld][fl] =
2485                                         GET_KEX_LDFLAGS(NIX_INTF_RX, ld, fl);
2486                         rsp->intf_ld_flags[NIX_INTF_TX][ld][fl] =
2487                                         GET_KEX_LDFLAGS(NIX_INTF_TX, ld, fl);
2488                 }
2489         }
2490         memcpy(rsp->mkex_pfl_name, rvu->mkex_pfl_name, MKEX_NAME_LEN);
2491         return 0;
2492 }
2493
2494 int rvu_npc_update_rxvlan(struct rvu *rvu, u16 pcifunc, int nixlf)
2495 {
2496         struct rvu_pfvf *pfvf = rvu_get_pfvf(rvu, pcifunc);
2497         struct npc_mcam *mcam = &rvu->hw->mcam;
2498         int blkaddr, index;
2499         bool enable;
2500
2501         blkaddr = rvu_get_blkaddr(rvu, BLKTYPE_NPC, 0);
2502         if (blkaddr < 0)
2503                 return NIX_AF_ERR_AF_LF_INVALID;
2504
2505         if (!pfvf->rxvlan)
2506                 return 0;
2507
2508         index = npc_get_nixlf_mcam_index(mcam, pcifunc, nixlf,
2509                                          NIXLF_UCAST_ENTRY);
2510         pfvf->entry.action = npc_get_mcam_action(rvu, mcam, blkaddr, index);
2511         enable = is_mcam_entry_enabled(rvu, mcam, blkaddr, index);
2512         npc_config_mcam_entry(rvu, mcam, blkaddr, pfvf->rxvlan_index,
2513                               pfvf->nix_rx_intf, &pfvf->entry, enable);
2514
2515         return 0;
2516 }